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[deliverable/linux.git] / arch / arm / mach-omap2 / gpmc.c
1 /*
2 * GPMC support functions
3 *
4 * Copyright (C) 2005-2006 Nokia Corporation
5 *
6 * Author: Juha Yrjola
7 *
8 * Copyright (C) 2009 Texas Instruments
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15 #undef DEBUG
16
17 #include <linux/irq.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
22 #include <linux/ioport.h>
23 #include <linux/spinlock.h>
24 #include <linux/io.h>
25 #include <linux/module.h>
26 #include <linux/interrupt.h>
27 #include <linux/platform_device.h>
28
29 #include <linux/platform_data/mtd-nand-omap2.h>
30
31 #include <asm/mach-types.h>
32
33 #include <plat/cpu.h>
34
35 #include "soc.h"
36 #include "common.h"
37 #include "omap_device.h"
38 #include "gpmc.h"
39
40 #define DEVICE_NAME "omap-gpmc"
41
42 /* GPMC register offsets */
43 #define GPMC_REVISION 0x00
44 #define GPMC_SYSCONFIG 0x10
45 #define GPMC_SYSSTATUS 0x14
46 #define GPMC_IRQSTATUS 0x18
47 #define GPMC_IRQENABLE 0x1c
48 #define GPMC_TIMEOUT_CONTROL 0x40
49 #define GPMC_ERR_ADDRESS 0x44
50 #define GPMC_ERR_TYPE 0x48
51 #define GPMC_CONFIG 0x50
52 #define GPMC_STATUS 0x54
53 #define GPMC_PREFETCH_CONFIG1 0x1e0
54 #define GPMC_PREFETCH_CONFIG2 0x1e4
55 #define GPMC_PREFETCH_CONTROL 0x1ec
56 #define GPMC_PREFETCH_STATUS 0x1f0
57 #define GPMC_ECC_CONFIG 0x1f4
58 #define GPMC_ECC_CONTROL 0x1f8
59 #define GPMC_ECC_SIZE_CONFIG 0x1fc
60 #define GPMC_ECC1_RESULT 0x200
61 #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
62 #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
63 #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
64 #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
65
66 /* GPMC ECC control settings */
67 #define GPMC_ECC_CTRL_ECCCLEAR 0x100
68 #define GPMC_ECC_CTRL_ECCDISABLE 0x000
69 #define GPMC_ECC_CTRL_ECCREG1 0x001
70 #define GPMC_ECC_CTRL_ECCREG2 0x002
71 #define GPMC_ECC_CTRL_ECCREG3 0x003
72 #define GPMC_ECC_CTRL_ECCREG4 0x004
73 #define GPMC_ECC_CTRL_ECCREG5 0x005
74 #define GPMC_ECC_CTRL_ECCREG6 0x006
75 #define GPMC_ECC_CTRL_ECCREG7 0x007
76 #define GPMC_ECC_CTRL_ECCREG8 0x008
77 #define GPMC_ECC_CTRL_ECCREG9 0x009
78
79 #define GPMC_CS0_OFFSET 0x60
80 #define GPMC_CS_SIZE 0x30
81 #define GPMC_BCH_SIZE 0x10
82
83 #define GPMC_MEM_START 0x00000000
84 #define GPMC_MEM_END 0x3FFFFFFF
85 #define BOOT_ROM_SPACE 0x100000 /* 1MB */
86
87 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
88 #define GPMC_SECTION_SHIFT 28 /* 128 MB */
89
90 #define CS_NUM_SHIFT 24
91 #define ENABLE_PREFETCH (0x1 << 7)
92 #define DMA_MPU_MODE 2
93
94 #define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf)
95 #define GPMC_REVISION_MINOR(l) (l & 0xf)
96
97 #define GPMC_HAS_WR_ACCESS 0x1
98 #define GPMC_HAS_WR_DATA_MUX_BUS 0x2
99
100 /* XXX: Only NAND irq has been considered,currently these are the only ones used
101 */
102 #define GPMC_NR_IRQ 2
103
104 struct gpmc_client_irq {
105 unsigned irq;
106 u32 bitmask;
107 };
108
109 /* Structure to save gpmc cs context */
110 struct gpmc_cs_config {
111 u32 config1;
112 u32 config2;
113 u32 config3;
114 u32 config4;
115 u32 config5;
116 u32 config6;
117 u32 config7;
118 int is_valid;
119 };
120
121 /*
122 * Structure to save/restore gpmc context
123 * to support core off on OMAP3
124 */
125 struct omap3_gpmc_regs {
126 u32 sysconfig;
127 u32 irqenable;
128 u32 timeout_ctrl;
129 u32 config;
130 u32 prefetch_config1;
131 u32 prefetch_config2;
132 u32 prefetch_control;
133 struct gpmc_cs_config cs_context[GPMC_CS_NUM];
134 };
135
136 static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ];
137 static struct irq_chip gpmc_irq_chip;
138 static unsigned gpmc_irq_start;
139
140 static struct resource gpmc_mem_root;
141 static struct resource gpmc_cs_mem[GPMC_CS_NUM];
142 static DEFINE_SPINLOCK(gpmc_mem_lock);
143 static unsigned int gpmc_cs_map; /* flag for cs which are initialized */
144 static struct device *gpmc_dev;
145 static int gpmc_irq;
146 static resource_size_t phys_base, mem_size;
147 static unsigned gpmc_capability;
148 static void __iomem *gpmc_base;
149
150 static struct clk *gpmc_l3_clk;
151
152 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
153
154 static void gpmc_write_reg(int idx, u32 val)
155 {
156 __raw_writel(val, gpmc_base + idx);
157 }
158
159 static u32 gpmc_read_reg(int idx)
160 {
161 return __raw_readl(gpmc_base + idx);
162 }
163
164 void gpmc_cs_write_reg(int cs, int idx, u32 val)
165 {
166 void __iomem *reg_addr;
167
168 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
169 __raw_writel(val, reg_addr);
170 }
171
172 u32 gpmc_cs_read_reg(int cs, int idx)
173 {
174 void __iomem *reg_addr;
175
176 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
177 return __raw_readl(reg_addr);
178 }
179
180 /* TODO: Add support for gpmc_fck to clock framework and use it */
181 unsigned long gpmc_get_fclk_period(void)
182 {
183 unsigned long rate = clk_get_rate(gpmc_l3_clk);
184
185 if (rate == 0) {
186 printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
187 return 0;
188 }
189
190 rate /= 1000;
191 rate = 1000000000 / rate; /* In picoseconds */
192
193 return rate;
194 }
195
196 unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
197 {
198 unsigned long tick_ps;
199
200 /* Calculate in picosecs to yield more exact results */
201 tick_ps = gpmc_get_fclk_period();
202
203 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
204 }
205
206 unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
207 {
208 unsigned long tick_ps;
209
210 /* Calculate in picosecs to yield more exact results */
211 tick_ps = gpmc_get_fclk_period();
212
213 return (time_ps + tick_ps - 1) / tick_ps;
214 }
215
216 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
217 {
218 return ticks * gpmc_get_fclk_period() / 1000;
219 }
220
221 unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
222 {
223 unsigned long ticks = gpmc_ns_to_ticks(time_ns);
224
225 return ticks * gpmc_get_fclk_period() / 1000;
226 }
227
228 #ifdef DEBUG
229 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
230 int time, const char *name)
231 #else
232 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
233 int time)
234 #endif
235 {
236 u32 l;
237 int ticks, mask, nr_bits;
238
239 if (time == 0)
240 ticks = 0;
241 else
242 ticks = gpmc_ns_to_ticks(time);
243 nr_bits = end_bit - st_bit + 1;
244 if (ticks >= 1 << nr_bits) {
245 #ifdef DEBUG
246 printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
247 cs, name, time, ticks, 1 << nr_bits);
248 #endif
249 return -1;
250 }
251
252 mask = (1 << nr_bits) - 1;
253 l = gpmc_cs_read_reg(cs, reg);
254 #ifdef DEBUG
255 printk(KERN_INFO
256 "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
257 cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
258 (l >> st_bit) & mask, time);
259 #endif
260 l &= ~(mask << st_bit);
261 l |= ticks << st_bit;
262 gpmc_cs_write_reg(cs, reg, l);
263
264 return 0;
265 }
266
267 #ifdef DEBUG
268 #define GPMC_SET_ONE(reg, st, end, field) \
269 if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
270 t->field, #field) < 0) \
271 return -1
272 #else
273 #define GPMC_SET_ONE(reg, st, end, field) \
274 if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
275 return -1
276 #endif
277
278 int gpmc_calc_divider(unsigned int sync_clk)
279 {
280 int div;
281 u32 l;
282
283 l = sync_clk + (gpmc_get_fclk_period() - 1);
284 div = l / gpmc_get_fclk_period();
285 if (div > 4)
286 return -1;
287 if (div <= 0)
288 div = 1;
289
290 return div;
291 }
292
293 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
294 {
295 int div;
296 u32 l;
297
298 div = gpmc_calc_divider(t->sync_clk);
299 if (div < 0)
300 return div;
301
302 GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
303 GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
304 GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
305
306 GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
307 GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
308 GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
309
310 GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
311 GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
312 GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
313 GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
314
315 GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
316 GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
317 GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
318
319 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
320
321 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
322 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
323 if (gpmc_capability & GPMC_HAS_WR_ACCESS)
324 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
325
326 /* caller is expected to have initialized CONFIG1 to cover
327 * at least sync vs async
328 */
329 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
330 if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
331 #ifdef DEBUG
332 printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
333 cs, (div * gpmc_get_fclk_period()) / 1000, div);
334 #endif
335 l &= ~0x03;
336 l |= (div - 1);
337 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
338 }
339
340 return 0;
341 }
342
343 static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
344 {
345 u32 l;
346 u32 mask;
347
348 mask = (1 << GPMC_SECTION_SHIFT) - size;
349 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
350 l &= ~0x3f;
351 l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
352 l &= ~(0x0f << 8);
353 l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
354 l |= GPMC_CONFIG7_CSVALID;
355 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
356 }
357
358 static void gpmc_cs_disable_mem(int cs)
359 {
360 u32 l;
361
362 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
363 l &= ~GPMC_CONFIG7_CSVALID;
364 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
365 }
366
367 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
368 {
369 u32 l;
370 u32 mask;
371
372 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
373 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
374 mask = (l >> 8) & 0x0f;
375 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
376 }
377
378 static int gpmc_cs_mem_enabled(int cs)
379 {
380 u32 l;
381
382 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
383 return l & GPMC_CONFIG7_CSVALID;
384 }
385
386 int gpmc_cs_set_reserved(int cs, int reserved)
387 {
388 if (cs > GPMC_CS_NUM)
389 return -ENODEV;
390
391 gpmc_cs_map &= ~(1 << cs);
392 gpmc_cs_map |= (reserved ? 1 : 0) << cs;
393
394 return 0;
395 }
396
397 int gpmc_cs_reserved(int cs)
398 {
399 if (cs > GPMC_CS_NUM)
400 return -ENODEV;
401
402 return gpmc_cs_map & (1 << cs);
403 }
404
405 static unsigned long gpmc_mem_align(unsigned long size)
406 {
407 int order;
408
409 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
410 order = GPMC_CHUNK_SHIFT - 1;
411 do {
412 size >>= 1;
413 order++;
414 } while (size);
415 size = 1 << order;
416 return size;
417 }
418
419 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
420 {
421 struct resource *res = &gpmc_cs_mem[cs];
422 int r;
423
424 size = gpmc_mem_align(size);
425 spin_lock(&gpmc_mem_lock);
426 res->start = base;
427 res->end = base + size - 1;
428 r = request_resource(&gpmc_mem_root, res);
429 spin_unlock(&gpmc_mem_lock);
430
431 return r;
432 }
433
434 static int gpmc_cs_delete_mem(int cs)
435 {
436 struct resource *res = &gpmc_cs_mem[cs];
437 int r;
438
439 spin_lock(&gpmc_mem_lock);
440 r = release_resource(&gpmc_cs_mem[cs]);
441 res->start = 0;
442 res->end = 0;
443 spin_unlock(&gpmc_mem_lock);
444
445 return r;
446 }
447
448 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
449 {
450 struct resource *res = &gpmc_cs_mem[cs];
451 int r = -1;
452
453 if (cs > GPMC_CS_NUM)
454 return -ENODEV;
455
456 size = gpmc_mem_align(size);
457 if (size > (1 << GPMC_SECTION_SHIFT))
458 return -ENOMEM;
459
460 spin_lock(&gpmc_mem_lock);
461 if (gpmc_cs_reserved(cs)) {
462 r = -EBUSY;
463 goto out;
464 }
465 if (gpmc_cs_mem_enabled(cs))
466 r = adjust_resource(res, res->start & ~(size - 1), size);
467 if (r < 0)
468 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
469 size, NULL, NULL);
470 if (r < 0)
471 goto out;
472
473 gpmc_cs_enable_mem(cs, res->start, resource_size(res));
474 *base = res->start;
475 gpmc_cs_set_reserved(cs, 1);
476 out:
477 spin_unlock(&gpmc_mem_lock);
478 return r;
479 }
480 EXPORT_SYMBOL(gpmc_cs_request);
481
482 void gpmc_cs_free(int cs)
483 {
484 spin_lock(&gpmc_mem_lock);
485 if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) {
486 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
487 BUG();
488 spin_unlock(&gpmc_mem_lock);
489 return;
490 }
491 gpmc_cs_disable_mem(cs);
492 release_resource(&gpmc_cs_mem[cs]);
493 gpmc_cs_set_reserved(cs, 0);
494 spin_unlock(&gpmc_mem_lock);
495 }
496 EXPORT_SYMBOL(gpmc_cs_free);
497
498 /**
499 * gpmc_cs_configure - write request to configure gpmc
500 * @cs: chip select number
501 * @cmd: command type
502 * @wval: value to write
503 * @return status of the operation
504 */
505 int gpmc_cs_configure(int cs, int cmd, int wval)
506 {
507 int err = 0;
508 u32 regval = 0;
509
510 switch (cmd) {
511 case GPMC_ENABLE_IRQ:
512 gpmc_write_reg(GPMC_IRQENABLE, wval);
513 break;
514
515 case GPMC_SET_IRQ_STATUS:
516 gpmc_write_reg(GPMC_IRQSTATUS, wval);
517 break;
518
519 case GPMC_CONFIG_WP:
520 regval = gpmc_read_reg(GPMC_CONFIG);
521 if (wval)
522 regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
523 else
524 regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */
525 gpmc_write_reg(GPMC_CONFIG, regval);
526 break;
527
528 case GPMC_CONFIG_RDY_BSY:
529 regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
530 if (wval)
531 regval |= WR_RD_PIN_MONITORING;
532 else
533 regval &= ~WR_RD_PIN_MONITORING;
534 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
535 break;
536
537 case GPMC_CONFIG_DEV_SIZE:
538 regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
539
540 /* clear 2 target bits */
541 regval &= ~GPMC_CONFIG1_DEVICESIZE(3);
542
543 /* set the proper value */
544 regval |= GPMC_CONFIG1_DEVICESIZE(wval);
545
546 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
547 break;
548
549 case GPMC_CONFIG_DEV_TYPE:
550 regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
551 regval |= GPMC_CONFIG1_DEVICETYPE(wval);
552 if (wval == GPMC_DEVICETYPE_NOR)
553 regval |= GPMC_CONFIG1_MUXADDDATA;
554 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
555 break;
556
557 default:
558 printk(KERN_ERR "gpmc_configure_cs: Not supported\n");
559 err = -EINVAL;
560 }
561
562 return err;
563 }
564 EXPORT_SYMBOL(gpmc_cs_configure);
565
566 void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
567 {
568 int i;
569
570 reg->gpmc_status = gpmc_base + GPMC_STATUS;
571 reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
572 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
573 reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
574 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
575 reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
576 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
577 reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
578 reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
579 reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
580 reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
581 reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
582 reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
583 reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
584 reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
585
586 for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
587 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
588 GPMC_BCH_SIZE * i;
589 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
590 GPMC_BCH_SIZE * i;
591 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
592 GPMC_BCH_SIZE * i;
593 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
594 GPMC_BCH_SIZE * i;
595 }
596 }
597
598 int gpmc_get_client_irq(unsigned irq_config)
599 {
600 int i;
601
602 if (hweight32(irq_config) > 1)
603 return 0;
604
605 for (i = 0; i < GPMC_NR_IRQ; i++)
606 if (gpmc_client_irq[i].bitmask & irq_config)
607 return gpmc_client_irq[i].irq;
608
609 return 0;
610 }
611
612 static int gpmc_irq_endis(unsigned irq, bool endis)
613 {
614 int i;
615 u32 regval;
616
617 for (i = 0; i < GPMC_NR_IRQ; i++)
618 if (irq == gpmc_client_irq[i].irq) {
619 regval = gpmc_read_reg(GPMC_IRQENABLE);
620 if (endis)
621 regval |= gpmc_client_irq[i].bitmask;
622 else
623 regval &= ~gpmc_client_irq[i].bitmask;
624 gpmc_write_reg(GPMC_IRQENABLE, regval);
625 break;
626 }
627
628 return 0;
629 }
630
631 static void gpmc_irq_disable(struct irq_data *p)
632 {
633 gpmc_irq_endis(p->irq, false);
634 }
635
636 static void gpmc_irq_enable(struct irq_data *p)
637 {
638 gpmc_irq_endis(p->irq, true);
639 }
640
641 static void gpmc_irq_noop(struct irq_data *data) { }
642
643 static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; }
644
645 static int gpmc_setup_irq(void)
646 {
647 int i;
648 u32 regval;
649
650 if (!gpmc_irq)
651 return -EINVAL;
652
653 gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0);
654 if (IS_ERR_VALUE(gpmc_irq_start)) {
655 pr_err("irq_alloc_descs failed\n");
656 return gpmc_irq_start;
657 }
658
659 gpmc_irq_chip.name = "gpmc";
660 gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret;
661 gpmc_irq_chip.irq_enable = gpmc_irq_enable;
662 gpmc_irq_chip.irq_disable = gpmc_irq_disable;
663 gpmc_irq_chip.irq_shutdown = gpmc_irq_noop;
664 gpmc_irq_chip.irq_ack = gpmc_irq_noop;
665 gpmc_irq_chip.irq_mask = gpmc_irq_noop;
666 gpmc_irq_chip.irq_unmask = gpmc_irq_noop;
667
668 gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE;
669 gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT;
670
671 for (i = 0; i < GPMC_NR_IRQ; i++) {
672 gpmc_client_irq[i].irq = gpmc_irq_start + i;
673 irq_set_chip_and_handler(gpmc_client_irq[i].irq,
674 &gpmc_irq_chip, handle_simple_irq);
675 set_irq_flags(gpmc_client_irq[i].irq,
676 IRQF_VALID | IRQF_NOAUTOEN);
677 }
678
679 /* Disable interrupts */
680 gpmc_write_reg(GPMC_IRQENABLE, 0);
681
682 /* clear interrupts */
683 regval = gpmc_read_reg(GPMC_IRQSTATUS);
684 gpmc_write_reg(GPMC_IRQSTATUS, regval);
685
686 return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL);
687 }
688
689 static __devexit int gpmc_free_irq(void)
690 {
691 int i;
692
693 if (gpmc_irq)
694 free_irq(gpmc_irq, NULL);
695
696 for (i = 0; i < GPMC_NR_IRQ; i++) {
697 irq_set_handler(gpmc_client_irq[i].irq, NULL);
698 irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip);
699 irq_modify_status(gpmc_client_irq[i].irq, 0, 0);
700 }
701
702 irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ);
703
704 return 0;
705 }
706
707 static void __devexit gpmc_mem_exit(void)
708 {
709 int cs;
710
711 for (cs = 0; cs < GPMC_CS_NUM; cs++) {
712 if (!gpmc_cs_mem_enabled(cs))
713 continue;
714 gpmc_cs_delete_mem(cs);
715 }
716
717 }
718
719 static void __devinit gpmc_mem_init(void)
720 {
721 int cs;
722 unsigned long boot_rom_space = 0;
723
724 /* never allocate the first page, to facilitate bug detection;
725 * even if we didn't boot from ROM.
726 */
727 boot_rom_space = BOOT_ROM_SPACE;
728 /* In apollon the CS0 is mapped as 0x0000 0000 */
729 if (machine_is_omap_apollon())
730 boot_rom_space = 0;
731 gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
732 gpmc_mem_root.end = GPMC_MEM_END;
733
734 /* Reserve all regions that has been set up by bootloader */
735 for (cs = 0; cs < GPMC_CS_NUM; cs++) {
736 u32 base, size;
737
738 if (!gpmc_cs_mem_enabled(cs))
739 continue;
740 gpmc_cs_get_memconf(cs, &base, &size);
741 if (gpmc_cs_insert_mem(cs, base, size) < 0)
742 BUG();
743 }
744 }
745
746 static __devinit int gpmc_probe(struct platform_device *pdev)
747 {
748 u32 l;
749 struct resource *res;
750
751 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
752 if (res == NULL)
753 return -ENOENT;
754
755 phys_base = res->start;
756 mem_size = resource_size(res);
757
758 gpmc_base = devm_request_and_ioremap(&pdev->dev, res);
759 if (!gpmc_base) {
760 dev_err(&pdev->dev, "error: request memory / ioremap\n");
761 return -EADDRNOTAVAIL;
762 }
763
764 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
765 if (res == NULL)
766 dev_warn(&pdev->dev, "Failed to get resource: irq\n");
767 else
768 gpmc_irq = res->start;
769
770 gpmc_l3_clk = clk_get(&pdev->dev, "fck");
771 if (IS_ERR(gpmc_l3_clk)) {
772 dev_err(&pdev->dev, "error: clk_get\n");
773 gpmc_irq = 0;
774 return PTR_ERR(gpmc_l3_clk);
775 }
776
777 clk_prepare_enable(gpmc_l3_clk);
778
779 gpmc_dev = &pdev->dev;
780
781 l = gpmc_read_reg(GPMC_REVISION);
782 if (GPMC_REVISION_MAJOR(l) > 0x4)
783 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
784 dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
785 GPMC_REVISION_MINOR(l));
786
787 gpmc_mem_init();
788
789 if (IS_ERR_VALUE(gpmc_setup_irq()))
790 dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
791
792 return 0;
793 }
794
795 static __devexit int gpmc_remove(struct platform_device *pdev)
796 {
797 gpmc_free_irq();
798 gpmc_mem_exit();
799 gpmc_dev = NULL;
800 return 0;
801 }
802
803 static struct platform_driver gpmc_driver = {
804 .probe = gpmc_probe,
805 .remove = __devexit_p(gpmc_remove),
806 .driver = {
807 .name = DEVICE_NAME,
808 .owner = THIS_MODULE,
809 },
810 };
811
812 static __init int gpmc_init(void)
813 {
814 return platform_driver_register(&gpmc_driver);
815 }
816
817 static __exit void gpmc_exit(void)
818 {
819 platform_driver_unregister(&gpmc_driver);
820
821 }
822
823 postcore_initcall(gpmc_init);
824 module_exit(gpmc_exit);
825
826 static int __init omap_gpmc_init(void)
827 {
828 struct omap_hwmod *oh;
829 struct platform_device *pdev;
830 char *oh_name = "gpmc";
831
832 oh = omap_hwmod_lookup(oh_name);
833 if (!oh) {
834 pr_err("Could not look up %s\n", oh_name);
835 return -ENODEV;
836 }
837
838 pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0, NULL, 0, 0);
839 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
840
841 return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
842 }
843 postcore_initcall(omap_gpmc_init);
844
845 static irqreturn_t gpmc_handle_irq(int irq, void *dev)
846 {
847 int i;
848 u32 regval;
849
850 regval = gpmc_read_reg(GPMC_IRQSTATUS);
851
852 if (!regval)
853 return IRQ_NONE;
854
855 for (i = 0; i < GPMC_NR_IRQ; i++)
856 if (regval & gpmc_client_irq[i].bitmask)
857 generic_handle_irq(gpmc_client_irq[i].irq);
858
859 gpmc_write_reg(GPMC_IRQSTATUS, regval);
860
861 return IRQ_HANDLED;
862 }
863
864 #ifdef CONFIG_ARCH_OMAP3
865 static struct omap3_gpmc_regs gpmc_context;
866
867 void omap3_gpmc_save_context(void)
868 {
869 int i;
870
871 gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
872 gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
873 gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
874 gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
875 gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
876 gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
877 gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
878 for (i = 0; i < GPMC_CS_NUM; i++) {
879 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
880 if (gpmc_context.cs_context[i].is_valid) {
881 gpmc_context.cs_context[i].config1 =
882 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
883 gpmc_context.cs_context[i].config2 =
884 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
885 gpmc_context.cs_context[i].config3 =
886 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
887 gpmc_context.cs_context[i].config4 =
888 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
889 gpmc_context.cs_context[i].config5 =
890 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
891 gpmc_context.cs_context[i].config6 =
892 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
893 gpmc_context.cs_context[i].config7 =
894 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
895 }
896 }
897 }
898
899 void omap3_gpmc_restore_context(void)
900 {
901 int i;
902
903 gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
904 gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
905 gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
906 gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
907 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
908 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
909 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
910 for (i = 0; i < GPMC_CS_NUM; i++) {
911 if (gpmc_context.cs_context[i].is_valid) {
912 gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
913 gpmc_context.cs_context[i].config1);
914 gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
915 gpmc_context.cs_context[i].config2);
916 gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
917 gpmc_context.cs_context[i].config3);
918 gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
919 gpmc_context.cs_context[i].config4);
920 gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
921 gpmc_context.cs_context[i].config5);
922 gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
923 gpmc_context.cs_context[i].config6);
924 gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
925 gpmc_context.cs_context[i].config7);
926 }
927 }
928 }
929 #endif /* CONFIG_ARCH_OMAP3 */
Linux kernel - Deliverables
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