2 * GPMC support functions
4 * Copyright (C) 2005-2006 Nokia Corporation
8 * Copyright (C) 2009 Texas Instruments
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/irq.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
22 #include <linux/ioport.h>
23 #include <linux/spinlock.h>
25 #include <linux/module.h>
26 #include <linux/interrupt.h>
27 #include <linux/platform_device.h>
29 #include <linux/of_address.h>
30 #include <linux/of_mtd.h>
31 #include <linux/of_device.h>
32 #include <linux/mtd/nand.h>
34 #include <linux/platform_data/mtd-nand-omap2.h>
36 #include <asm/mach-types.h>
40 #include "omap_device.h"
42 #include "gpmc-nand.h"
43 #include "gpmc-onenand.h"
45 #define DEVICE_NAME "omap-gpmc"
47 /* GPMC register offsets */
48 #define GPMC_REVISION 0x00
49 #define GPMC_SYSCONFIG 0x10
50 #define GPMC_SYSSTATUS 0x14
51 #define GPMC_IRQSTATUS 0x18
52 #define GPMC_IRQENABLE 0x1c
53 #define GPMC_TIMEOUT_CONTROL 0x40
54 #define GPMC_ERR_ADDRESS 0x44
55 #define GPMC_ERR_TYPE 0x48
56 #define GPMC_CONFIG 0x50
57 #define GPMC_STATUS 0x54
58 #define GPMC_PREFETCH_CONFIG1 0x1e0
59 #define GPMC_PREFETCH_CONFIG2 0x1e4
60 #define GPMC_PREFETCH_CONTROL 0x1ec
61 #define GPMC_PREFETCH_STATUS 0x1f0
62 #define GPMC_ECC_CONFIG 0x1f4
63 #define GPMC_ECC_CONTROL 0x1f8
64 #define GPMC_ECC_SIZE_CONFIG 0x1fc
65 #define GPMC_ECC1_RESULT 0x200
66 #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
67 #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
68 #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
69 #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
71 /* GPMC ECC control settings */
72 #define GPMC_ECC_CTRL_ECCCLEAR 0x100
73 #define GPMC_ECC_CTRL_ECCDISABLE 0x000
74 #define GPMC_ECC_CTRL_ECCREG1 0x001
75 #define GPMC_ECC_CTRL_ECCREG2 0x002
76 #define GPMC_ECC_CTRL_ECCREG3 0x003
77 #define GPMC_ECC_CTRL_ECCREG4 0x004
78 #define GPMC_ECC_CTRL_ECCREG5 0x005
79 #define GPMC_ECC_CTRL_ECCREG6 0x006
80 #define GPMC_ECC_CTRL_ECCREG7 0x007
81 #define GPMC_ECC_CTRL_ECCREG8 0x008
82 #define GPMC_ECC_CTRL_ECCREG9 0x009
84 #define GPMC_CONFIG2_CSEXTRADELAY BIT(7)
85 #define GPMC_CONFIG3_ADVEXTRADELAY BIT(7)
86 #define GPMC_CONFIG4_OEEXTRADELAY BIT(7)
87 #define GPMC_CONFIG4_WEEXTRADELAY BIT(23)
88 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6)
89 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7)
91 #define GPMC_CS0_OFFSET 0x60
92 #define GPMC_CS_SIZE 0x30
93 #define GPMC_BCH_SIZE 0x10
95 #define GPMC_MEM_START 0x00000000
96 #define GPMC_MEM_END 0x3FFFFFFF
97 #define BOOT_ROM_SPACE 0x100000 /* 1MB */
99 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
100 #define GPMC_SECTION_SHIFT 28 /* 128 MB */
102 #define CS_NUM_SHIFT 24
103 #define ENABLE_PREFETCH (0x1 << 7)
104 #define DMA_MPU_MODE 2
106 #define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf)
107 #define GPMC_REVISION_MINOR(l) (l & 0xf)
109 #define GPMC_HAS_WR_ACCESS 0x1
110 #define GPMC_HAS_WR_DATA_MUX_BUS 0x2
111 #define GPMC_HAS_MUX_AAD 0x4
113 #define GPMC_NR_WAITPINS 4
115 /* XXX: Only NAND irq has been considered,currently these are the only ones used
117 #define GPMC_NR_IRQ 2
119 struct gpmc_client_irq
{
124 /* Structure to save gpmc cs context */
125 struct gpmc_cs_config
{
137 * Structure to save/restore gpmc context
138 * to support core off on OMAP3
140 struct omap3_gpmc_regs
{
145 u32 prefetch_config1
;
146 u32 prefetch_config2
;
147 u32 prefetch_control
;
148 struct gpmc_cs_config cs_context
[GPMC_CS_NUM
];
151 static struct gpmc_client_irq gpmc_client_irq
[GPMC_NR_IRQ
];
152 static struct irq_chip gpmc_irq_chip
;
153 static unsigned gpmc_irq_start
;
155 static struct resource gpmc_mem_root
;
156 static struct resource gpmc_cs_mem
[GPMC_CS_NUM
];
157 static DEFINE_SPINLOCK(gpmc_mem_lock
);
158 /* Define chip-selects as reserved by default until probe completes */
159 static unsigned int gpmc_cs_map
= ((1 << GPMC_CS_NUM
) - 1);
160 static unsigned int gpmc_nr_waitpins
;
161 static struct device
*gpmc_dev
;
163 static resource_size_t phys_base
, mem_size
;
164 static unsigned gpmc_capability
;
165 static void __iomem
*gpmc_base
;
167 static struct clk
*gpmc_l3_clk
;
169 static irqreturn_t
gpmc_handle_irq(int irq
, void *dev
);
171 static void gpmc_write_reg(int idx
, u32 val
)
173 __raw_writel(val
, gpmc_base
+ idx
);
176 static u32
gpmc_read_reg(int idx
)
178 return __raw_readl(gpmc_base
+ idx
);
181 void gpmc_cs_write_reg(int cs
, int idx
, u32 val
)
183 void __iomem
*reg_addr
;
185 reg_addr
= gpmc_base
+ GPMC_CS0_OFFSET
+ (cs
* GPMC_CS_SIZE
) + idx
;
186 __raw_writel(val
, reg_addr
);
189 static u32
gpmc_cs_read_reg(int cs
, int idx
)
191 void __iomem
*reg_addr
;
193 reg_addr
= gpmc_base
+ GPMC_CS0_OFFSET
+ (cs
* GPMC_CS_SIZE
) + idx
;
194 return __raw_readl(reg_addr
);
197 /* TODO: Add support for gpmc_fck to clock framework and use it */
198 static unsigned long gpmc_get_fclk_period(void)
200 unsigned long rate
= clk_get_rate(gpmc_l3_clk
);
203 printk(KERN_WARNING
"gpmc_l3_clk not enabled\n");
208 rate
= 1000000000 / rate
; /* In picoseconds */
213 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns
)
215 unsigned long tick_ps
;
217 /* Calculate in picosecs to yield more exact results */
218 tick_ps
= gpmc_get_fclk_period();
220 return (time_ns
* 1000 + tick_ps
- 1) / tick_ps
;
223 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps
)
225 unsigned long tick_ps
;
227 /* Calculate in picosecs to yield more exact results */
228 tick_ps
= gpmc_get_fclk_period();
230 return (time_ps
+ tick_ps
- 1) / tick_ps
;
233 unsigned int gpmc_ticks_to_ns(unsigned int ticks
)
235 return ticks
* gpmc_get_fclk_period() / 1000;
238 static unsigned int gpmc_ticks_to_ps(unsigned int ticks
)
240 return ticks
* gpmc_get_fclk_period();
243 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps
)
245 unsigned long ticks
= gpmc_ps_to_ticks(time_ps
);
247 return ticks
* gpmc_get_fclk_period();
250 static inline void gpmc_cs_modify_reg(int cs
, int reg
, u32 mask
, bool value
)
254 l
= gpmc_cs_read_reg(cs
, reg
);
259 gpmc_cs_write_reg(cs
, reg
, l
);
262 static void gpmc_cs_bool_timings(int cs
, const struct gpmc_bool_timings
*p
)
264 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG1
,
265 GPMC_CONFIG1_TIME_PARA_GRAN
,
266 p
->time_para_granularity
);
267 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG2
,
268 GPMC_CONFIG2_CSEXTRADELAY
, p
->cs_extra_delay
);
269 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG3
,
270 GPMC_CONFIG3_ADVEXTRADELAY
, p
->adv_extra_delay
);
271 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG4
,
272 GPMC_CONFIG4_OEEXTRADELAY
, p
->oe_extra_delay
);
273 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG4
,
274 GPMC_CONFIG4_OEEXTRADELAY
, p
->we_extra_delay
);
275 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG6
,
276 GPMC_CONFIG6_CYCLE2CYCLESAMECSEN
,
277 p
->cycle2cyclesamecsen
);
278 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG6
,
279 GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN
,
280 p
->cycle2cyclediffcsen
);
284 static int set_gpmc_timing_reg(int cs
, int reg
, int st_bit
, int end_bit
,
285 int time
, const char *name
)
287 static int set_gpmc_timing_reg(int cs
, int reg
, int st_bit
, int end_bit
,
292 int ticks
, mask
, nr_bits
;
297 ticks
= gpmc_ns_to_ticks(time
);
298 nr_bits
= end_bit
- st_bit
+ 1;
299 if (ticks
>= 1 << nr_bits
) {
301 printk(KERN_INFO
"GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
302 cs
, name
, time
, ticks
, 1 << nr_bits
);
307 mask
= (1 << nr_bits
) - 1;
308 l
= gpmc_cs_read_reg(cs
, reg
);
311 "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
312 cs
, name
, ticks
, gpmc_get_fclk_period() * ticks
/ 1000,
313 (l
>> st_bit
) & mask
, time
);
315 l
&= ~(mask
<< st_bit
);
316 l
|= ticks
<< st_bit
;
317 gpmc_cs_write_reg(cs
, reg
, l
);
323 #define GPMC_SET_ONE(reg, st, end, field) \
324 if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
325 t->field, #field) < 0) \
328 #define GPMC_SET_ONE(reg, st, end, field) \
329 if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
333 int gpmc_calc_divider(unsigned int sync_clk
)
338 l
= sync_clk
+ (gpmc_get_fclk_period() - 1);
339 div
= l
/ gpmc_get_fclk_period();
348 int gpmc_cs_set_timings(int cs
, const struct gpmc_timings
*t
)
353 div
= gpmc_calc_divider(t
->sync_clk
);
357 GPMC_SET_ONE(GPMC_CS_CONFIG2
, 0, 3, cs_on
);
358 GPMC_SET_ONE(GPMC_CS_CONFIG2
, 8, 12, cs_rd_off
);
359 GPMC_SET_ONE(GPMC_CS_CONFIG2
, 16, 20, cs_wr_off
);
361 GPMC_SET_ONE(GPMC_CS_CONFIG3
, 0, 3, adv_on
);
362 GPMC_SET_ONE(GPMC_CS_CONFIG3
, 8, 12, adv_rd_off
);
363 GPMC_SET_ONE(GPMC_CS_CONFIG3
, 16, 20, adv_wr_off
);
365 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 0, 3, oe_on
);
366 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 8, 12, oe_off
);
367 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 16, 19, we_on
);
368 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 24, 28, we_off
);
370 GPMC_SET_ONE(GPMC_CS_CONFIG5
, 0, 4, rd_cycle
);
371 GPMC_SET_ONE(GPMC_CS_CONFIG5
, 8, 12, wr_cycle
);
372 GPMC_SET_ONE(GPMC_CS_CONFIG5
, 16, 20, access
);
374 GPMC_SET_ONE(GPMC_CS_CONFIG5
, 24, 27, page_burst_access
);
376 GPMC_SET_ONE(GPMC_CS_CONFIG6
, 0, 3, bus_turnaround
);
377 GPMC_SET_ONE(GPMC_CS_CONFIG6
, 8, 11, cycle2cycle_delay
);
379 GPMC_SET_ONE(GPMC_CS_CONFIG1
, 18, 19, wait_monitoring
);
380 GPMC_SET_ONE(GPMC_CS_CONFIG1
, 25, 26, clk_activation
);
382 if (gpmc_capability
& GPMC_HAS_WR_DATA_MUX_BUS
)
383 GPMC_SET_ONE(GPMC_CS_CONFIG6
, 16, 19, wr_data_mux_bus
);
384 if (gpmc_capability
& GPMC_HAS_WR_ACCESS
)
385 GPMC_SET_ONE(GPMC_CS_CONFIG6
, 24, 28, wr_access
);
387 /* caller is expected to have initialized CONFIG1 to cover
388 * at least sync vs async
390 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG1
);
391 if (l
& (GPMC_CONFIG1_READTYPE_SYNC
| GPMC_CONFIG1_WRITETYPE_SYNC
)) {
393 printk(KERN_INFO
"GPMC CS%d CLK period is %lu ns (div %d)\n",
394 cs
, (div
* gpmc_get_fclk_period()) / 1000, div
);
398 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG1
, l
);
401 gpmc_cs_bool_timings(cs
, &t
->bool_timings
);
406 static void gpmc_cs_enable_mem(int cs
, u32 base
, u32 size
)
411 mask
= (1 << GPMC_SECTION_SHIFT
) - size
;
412 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
414 l
= (base
>> GPMC_CHUNK_SHIFT
) & 0x3f;
416 l
|= ((mask
>> GPMC_CHUNK_SHIFT
) & 0x0f) << 8;
417 l
|= GPMC_CONFIG7_CSVALID
;
418 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG7
, l
);
421 static void gpmc_cs_disable_mem(int cs
)
425 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
426 l
&= ~GPMC_CONFIG7_CSVALID
;
427 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG7
, l
);
430 static void gpmc_cs_get_memconf(int cs
, u32
*base
, u32
*size
)
435 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
436 *base
= (l
& 0x3f) << GPMC_CHUNK_SHIFT
;
437 mask
= (l
>> 8) & 0x0f;
438 *size
= (1 << GPMC_SECTION_SHIFT
) - (mask
<< GPMC_CHUNK_SHIFT
);
441 static int gpmc_cs_mem_enabled(int cs
)
445 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
446 return l
& GPMC_CONFIG7_CSVALID
;
449 static void gpmc_cs_set_reserved(int cs
, int reserved
)
451 gpmc_cs_map
&= ~(1 << cs
);
452 gpmc_cs_map
|= (reserved
? 1 : 0) << cs
;
455 static bool gpmc_cs_reserved(int cs
)
457 return gpmc_cs_map
& (1 << cs
);
460 static unsigned long gpmc_mem_align(unsigned long size
)
464 size
= (size
- 1) >> (GPMC_CHUNK_SHIFT
- 1);
465 order
= GPMC_CHUNK_SHIFT
- 1;
474 static int gpmc_cs_insert_mem(int cs
, unsigned long base
, unsigned long size
)
476 struct resource
*res
= &gpmc_cs_mem
[cs
];
479 size
= gpmc_mem_align(size
);
480 spin_lock(&gpmc_mem_lock
);
482 res
->end
= base
+ size
- 1;
483 r
= request_resource(&gpmc_mem_root
, res
);
484 spin_unlock(&gpmc_mem_lock
);
489 static int gpmc_cs_delete_mem(int cs
)
491 struct resource
*res
= &gpmc_cs_mem
[cs
];
494 spin_lock(&gpmc_mem_lock
);
495 r
= release_resource(&gpmc_cs_mem
[cs
]);
498 spin_unlock(&gpmc_mem_lock
);
504 * gpmc_cs_remap - remaps a chip-select physical base address
505 * @cs: chip-select to remap
506 * @base: physical base address to re-map chip-select to
508 * Re-maps a chip-select to a new physical base address specified by
509 * "base". Returns 0 on success and appropriate negative error code
512 static int gpmc_cs_remap(int cs
, u32 base
)
517 if (cs
> GPMC_CS_NUM
)
519 gpmc_cs_get_memconf(cs
, &old_base
, &size
);
520 if (base
== old_base
)
522 gpmc_cs_disable_mem(cs
);
523 ret
= gpmc_cs_delete_mem(cs
);
526 ret
= gpmc_cs_insert_mem(cs
, base
, size
);
529 gpmc_cs_enable_mem(cs
, base
, size
);
534 int gpmc_cs_request(int cs
, unsigned long size
, unsigned long *base
)
536 struct resource
*res
= &gpmc_cs_mem
[cs
];
539 if (cs
> GPMC_CS_NUM
)
542 size
= gpmc_mem_align(size
);
543 if (size
> (1 << GPMC_SECTION_SHIFT
))
546 spin_lock(&gpmc_mem_lock
);
547 if (gpmc_cs_reserved(cs
)) {
551 if (gpmc_cs_mem_enabled(cs
))
552 r
= adjust_resource(res
, res
->start
& ~(size
- 1), size
);
554 r
= allocate_resource(&gpmc_mem_root
, res
, size
, 0, ~0,
559 gpmc_cs_enable_mem(cs
, res
->start
, resource_size(res
));
561 gpmc_cs_set_reserved(cs
, 1);
563 spin_unlock(&gpmc_mem_lock
);
566 EXPORT_SYMBOL(gpmc_cs_request
);
568 void gpmc_cs_free(int cs
)
570 spin_lock(&gpmc_mem_lock
);
571 if (cs
>= GPMC_CS_NUM
|| cs
< 0 || !gpmc_cs_reserved(cs
)) {
572 printk(KERN_ERR
"Trying to free non-reserved GPMC CS%d\n", cs
);
574 spin_unlock(&gpmc_mem_lock
);
577 gpmc_cs_disable_mem(cs
);
578 release_resource(&gpmc_cs_mem
[cs
]);
579 gpmc_cs_set_reserved(cs
, 0);
580 spin_unlock(&gpmc_mem_lock
);
582 EXPORT_SYMBOL(gpmc_cs_free
);
585 * gpmc_configure - write request to configure gpmc
587 * @wval: value to write
588 * @return status of the operation
590 int gpmc_configure(int cmd
, int wval
)
595 case GPMC_ENABLE_IRQ
:
596 gpmc_write_reg(GPMC_IRQENABLE
, wval
);
599 case GPMC_SET_IRQ_STATUS
:
600 gpmc_write_reg(GPMC_IRQSTATUS
, wval
);
604 regval
= gpmc_read_reg(GPMC_CONFIG
);
606 regval
&= ~GPMC_CONFIG_WRITEPROTECT
; /* WP is ON */
608 regval
|= GPMC_CONFIG_WRITEPROTECT
; /* WP is OFF */
609 gpmc_write_reg(GPMC_CONFIG
, regval
);
613 pr_err("%s: command not supported\n", __func__
);
619 EXPORT_SYMBOL(gpmc_configure
);
621 void gpmc_update_nand_reg(struct gpmc_nand_regs
*reg
, int cs
)
625 reg
->gpmc_status
= gpmc_base
+ GPMC_STATUS
;
626 reg
->gpmc_nand_command
= gpmc_base
+ GPMC_CS0_OFFSET
+
627 GPMC_CS_NAND_COMMAND
+ GPMC_CS_SIZE
* cs
;
628 reg
->gpmc_nand_address
= gpmc_base
+ GPMC_CS0_OFFSET
+
629 GPMC_CS_NAND_ADDRESS
+ GPMC_CS_SIZE
* cs
;
630 reg
->gpmc_nand_data
= gpmc_base
+ GPMC_CS0_OFFSET
+
631 GPMC_CS_NAND_DATA
+ GPMC_CS_SIZE
* cs
;
632 reg
->gpmc_prefetch_config1
= gpmc_base
+ GPMC_PREFETCH_CONFIG1
;
633 reg
->gpmc_prefetch_config2
= gpmc_base
+ GPMC_PREFETCH_CONFIG2
;
634 reg
->gpmc_prefetch_control
= gpmc_base
+ GPMC_PREFETCH_CONTROL
;
635 reg
->gpmc_prefetch_status
= gpmc_base
+ GPMC_PREFETCH_STATUS
;
636 reg
->gpmc_ecc_config
= gpmc_base
+ GPMC_ECC_CONFIG
;
637 reg
->gpmc_ecc_control
= gpmc_base
+ GPMC_ECC_CONTROL
;
638 reg
->gpmc_ecc_size_config
= gpmc_base
+ GPMC_ECC_SIZE_CONFIG
;
639 reg
->gpmc_ecc1_result
= gpmc_base
+ GPMC_ECC1_RESULT
;
641 for (i
= 0; i
< GPMC_BCH_NUM_REMAINDER
; i
++) {
642 reg
->gpmc_bch_result0
[i
] = gpmc_base
+ GPMC_ECC_BCH_RESULT_0
+
644 reg
->gpmc_bch_result1
[i
] = gpmc_base
+ GPMC_ECC_BCH_RESULT_1
+
646 reg
->gpmc_bch_result2
[i
] = gpmc_base
+ GPMC_ECC_BCH_RESULT_2
+
648 reg
->gpmc_bch_result3
[i
] = gpmc_base
+ GPMC_ECC_BCH_RESULT_3
+
653 int gpmc_get_client_irq(unsigned irq_config
)
657 if (hweight32(irq_config
) > 1)
660 for (i
= 0; i
< GPMC_NR_IRQ
; i
++)
661 if (gpmc_client_irq
[i
].bitmask
& irq_config
)
662 return gpmc_client_irq
[i
].irq
;
667 static int gpmc_irq_endis(unsigned irq
, bool endis
)
672 for (i
= 0; i
< GPMC_NR_IRQ
; i
++)
673 if (irq
== gpmc_client_irq
[i
].irq
) {
674 regval
= gpmc_read_reg(GPMC_IRQENABLE
);
676 regval
|= gpmc_client_irq
[i
].bitmask
;
678 regval
&= ~gpmc_client_irq
[i
].bitmask
;
679 gpmc_write_reg(GPMC_IRQENABLE
, regval
);
686 static void gpmc_irq_disable(struct irq_data
*p
)
688 gpmc_irq_endis(p
->irq
, false);
691 static void gpmc_irq_enable(struct irq_data
*p
)
693 gpmc_irq_endis(p
->irq
, true);
696 static void gpmc_irq_noop(struct irq_data
*data
) { }
698 static unsigned int gpmc_irq_noop_ret(struct irq_data
*data
) { return 0; }
700 static int gpmc_setup_irq(void)
708 gpmc_irq_start
= irq_alloc_descs(-1, 0, GPMC_NR_IRQ
, 0);
709 if (gpmc_irq_start
< 0) {
710 pr_err("irq_alloc_descs failed\n");
711 return gpmc_irq_start
;
714 gpmc_irq_chip
.name
= "gpmc";
715 gpmc_irq_chip
.irq_startup
= gpmc_irq_noop_ret
;
716 gpmc_irq_chip
.irq_enable
= gpmc_irq_enable
;
717 gpmc_irq_chip
.irq_disable
= gpmc_irq_disable
;
718 gpmc_irq_chip
.irq_shutdown
= gpmc_irq_noop
;
719 gpmc_irq_chip
.irq_ack
= gpmc_irq_noop
;
720 gpmc_irq_chip
.irq_mask
= gpmc_irq_noop
;
721 gpmc_irq_chip
.irq_unmask
= gpmc_irq_noop
;
723 gpmc_client_irq
[0].bitmask
= GPMC_IRQ_FIFOEVENTENABLE
;
724 gpmc_client_irq
[1].bitmask
= GPMC_IRQ_COUNT_EVENT
;
726 for (i
= 0; i
< GPMC_NR_IRQ
; i
++) {
727 gpmc_client_irq
[i
].irq
= gpmc_irq_start
+ i
;
728 irq_set_chip_and_handler(gpmc_client_irq
[i
].irq
,
729 &gpmc_irq_chip
, handle_simple_irq
);
730 set_irq_flags(gpmc_client_irq
[i
].irq
,
731 IRQF_VALID
| IRQF_NOAUTOEN
);
734 /* Disable interrupts */
735 gpmc_write_reg(GPMC_IRQENABLE
, 0);
737 /* clear interrupts */
738 regval
= gpmc_read_reg(GPMC_IRQSTATUS
);
739 gpmc_write_reg(GPMC_IRQSTATUS
, regval
);
741 return request_irq(gpmc_irq
, gpmc_handle_irq
, 0, "gpmc", NULL
);
744 static int gpmc_free_irq(void)
749 free_irq(gpmc_irq
, NULL
);
751 for (i
= 0; i
< GPMC_NR_IRQ
; i
++) {
752 irq_set_handler(gpmc_client_irq
[i
].irq
, NULL
);
753 irq_set_chip(gpmc_client_irq
[i
].irq
, &no_irq_chip
);
754 irq_modify_status(gpmc_client_irq
[i
].irq
, 0, 0);
757 irq_free_descs(gpmc_irq_start
, GPMC_NR_IRQ
);
762 static void gpmc_mem_exit(void)
766 for (cs
= 0; cs
< GPMC_CS_NUM
; cs
++) {
767 if (!gpmc_cs_mem_enabled(cs
))
769 gpmc_cs_delete_mem(cs
);
774 static int gpmc_mem_init(void)
777 unsigned long boot_rom_space
= 0;
779 /* never allocate the first page, to facilitate bug detection;
780 * even if we didn't boot from ROM.
782 boot_rom_space
= BOOT_ROM_SPACE
;
783 gpmc_mem_root
.start
= GPMC_MEM_START
+ boot_rom_space
;
784 gpmc_mem_root
.end
= GPMC_MEM_END
;
786 /* Reserve all regions that has been set up by bootloader */
787 for (cs
= 0; cs
< GPMC_CS_NUM
; cs
++) {
790 if (!gpmc_cs_mem_enabled(cs
))
792 gpmc_cs_get_memconf(cs
, &base
, &size
);
793 rc
= gpmc_cs_insert_mem(cs
, base
, size
);
796 if (gpmc_cs_mem_enabled(cs
))
797 gpmc_cs_delete_mem(cs
);
805 static u32
gpmc_round_ps_to_sync_clk(u32 time_ps
, u32 sync_clk
)
810 div
= gpmc_calc_divider(sync_clk
);
811 temp
= gpmc_ps_to_ticks(time_ps
);
812 temp
= (temp
+ div
- 1) / div
;
813 return gpmc_ticks_to_ps(temp
* div
);
816 /* XXX: can the cycles be avoided ? */
817 static int gpmc_calc_sync_read_timings(struct gpmc_timings
*gpmc_t
,
818 struct gpmc_device_timings
*dev_t
,
824 temp
= dev_t
->t_avdp_r
;
825 /* XXX: mux check required ? */
827 /* XXX: t_avdp not to be required for sync, only added for tusb
828 * this indirectly necessitates requirement of t_avdp_r and
829 * t_avdp_w instead of having a single t_avdp
831 temp
= max_t(u32
, temp
, gpmc_t
->clk_activation
+ dev_t
->t_avdh
);
832 temp
= max_t(u32
, gpmc_t
->adv_on
+ gpmc_ticks_to_ps(1), temp
);
834 gpmc_t
->adv_rd_off
= gpmc_round_ps_to_ticks(temp
);
837 temp
= dev_t
->t_oeasu
; /* XXX: remove this ? */
839 temp
= max_t(u32
, temp
, gpmc_t
->clk_activation
+ dev_t
->t_ach
);
840 temp
= max_t(u32
, temp
, gpmc_t
->adv_rd_off
+
841 gpmc_ticks_to_ps(dev_t
->cyc_aavdh_oe
));
843 gpmc_t
->oe_on
= gpmc_round_ps_to_ticks(temp
);
846 /* XXX: any scope for improvement ?, by combining oe_on
847 * and clk_activation, need to check whether
848 * access = clk_activation + round to sync clk ?
850 temp
= max_t(u32
, dev_t
->t_iaa
, dev_t
->cyc_iaa
* gpmc_t
->sync_clk
);
851 temp
+= gpmc_t
->clk_activation
;
853 temp
= max_t(u32
, temp
, gpmc_t
->oe_on
+
854 gpmc_ticks_to_ps(dev_t
->cyc_oe
));
855 gpmc_t
->access
= gpmc_round_ps_to_ticks(temp
);
857 gpmc_t
->oe_off
= gpmc_t
->access
+ gpmc_ticks_to_ps(1);
858 gpmc_t
->cs_rd_off
= gpmc_t
->oe_off
;
861 temp
= max_t(u32
, dev_t
->t_cez_r
, dev_t
->t_oez
);
862 temp
= gpmc_round_ps_to_sync_clk(temp
, gpmc_t
->sync_clk
) +
864 /* XXX: barter t_ce_rdyz with t_cez_r ? */
865 if (dev_t
->t_ce_rdyz
)
866 temp
= max_t(u32
, temp
, gpmc_t
->cs_rd_off
+ dev_t
->t_ce_rdyz
);
867 gpmc_t
->rd_cycle
= gpmc_round_ps_to_ticks(temp
);
872 static int gpmc_calc_sync_write_timings(struct gpmc_timings
*gpmc_t
,
873 struct gpmc_device_timings
*dev_t
,
879 temp
= dev_t
->t_avdp_w
;
881 temp
= max_t(u32
, temp
,
882 gpmc_t
->clk_activation
+ dev_t
->t_avdh
);
883 temp
= max_t(u32
, gpmc_t
->adv_on
+ gpmc_ticks_to_ps(1), temp
);
885 gpmc_t
->adv_wr_off
= gpmc_round_ps_to_ticks(temp
);
887 /* wr_data_mux_bus */
888 temp
= max_t(u32
, dev_t
->t_weasu
,
889 gpmc_t
->clk_activation
+ dev_t
->t_rdyo
);
890 /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
891 * and in that case remember to handle we_on properly
894 temp
= max_t(u32
, temp
,
895 gpmc_t
->adv_wr_off
+ dev_t
->t_aavdh
);
896 temp
= max_t(u32
, temp
, gpmc_t
->adv_wr_off
+
897 gpmc_ticks_to_ps(dev_t
->cyc_aavdh_we
));
899 gpmc_t
->wr_data_mux_bus
= gpmc_round_ps_to_ticks(temp
);
902 if (gpmc_capability
& GPMC_HAS_WR_DATA_MUX_BUS
)
903 gpmc_t
->we_on
= gpmc_round_ps_to_ticks(dev_t
->t_weasu
);
905 gpmc_t
->we_on
= gpmc_t
->wr_data_mux_bus
;
908 /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
909 gpmc_t
->wr_access
= gpmc_t
->access
;
912 temp
= gpmc_t
->we_on
+ dev_t
->t_wpl
;
913 temp
= max_t(u32
, temp
,
914 gpmc_t
->wr_access
+ gpmc_ticks_to_ps(1));
915 temp
= max_t(u32
, temp
,
916 gpmc_t
->we_on
+ gpmc_ticks_to_ps(dev_t
->cyc_wpl
));
917 gpmc_t
->we_off
= gpmc_round_ps_to_ticks(temp
);
919 gpmc_t
->cs_wr_off
= gpmc_round_ps_to_ticks(gpmc_t
->we_off
+
923 temp
= gpmc_round_ps_to_sync_clk(dev_t
->t_cez_w
, gpmc_t
->sync_clk
);
924 temp
+= gpmc_t
->wr_access
;
925 /* XXX: barter t_ce_rdyz with t_cez_w ? */
926 if (dev_t
->t_ce_rdyz
)
927 temp
= max_t(u32
, temp
,
928 gpmc_t
->cs_wr_off
+ dev_t
->t_ce_rdyz
);
929 gpmc_t
->wr_cycle
= gpmc_round_ps_to_ticks(temp
);
934 static int gpmc_calc_async_read_timings(struct gpmc_timings
*gpmc_t
,
935 struct gpmc_device_timings
*dev_t
,
941 temp
= dev_t
->t_avdp_r
;
943 temp
= max_t(u32
, gpmc_t
->adv_on
+ gpmc_ticks_to_ps(1), temp
);
944 gpmc_t
->adv_rd_off
= gpmc_round_ps_to_ticks(temp
);
947 temp
= dev_t
->t_oeasu
;
949 temp
= max_t(u32
, temp
,
950 gpmc_t
->adv_rd_off
+ dev_t
->t_aavdh
);
951 gpmc_t
->oe_on
= gpmc_round_ps_to_ticks(temp
);
954 temp
= max_t(u32
, dev_t
->t_iaa
, /* XXX: remove t_iaa in async ? */
955 gpmc_t
->oe_on
+ dev_t
->t_oe
);
956 temp
= max_t(u32
, temp
,
957 gpmc_t
->cs_on
+ dev_t
->t_ce
);
958 temp
= max_t(u32
, temp
,
959 gpmc_t
->adv_on
+ dev_t
->t_aa
);
960 gpmc_t
->access
= gpmc_round_ps_to_ticks(temp
);
962 gpmc_t
->oe_off
= gpmc_t
->access
+ gpmc_ticks_to_ps(1);
963 gpmc_t
->cs_rd_off
= gpmc_t
->oe_off
;
966 temp
= max_t(u32
, dev_t
->t_rd_cycle
,
967 gpmc_t
->cs_rd_off
+ dev_t
->t_cez_r
);
968 temp
= max_t(u32
, temp
, gpmc_t
->oe_off
+ dev_t
->t_oez
);
969 gpmc_t
->rd_cycle
= gpmc_round_ps_to_ticks(temp
);
974 static int gpmc_calc_async_write_timings(struct gpmc_timings
*gpmc_t
,
975 struct gpmc_device_timings
*dev_t
,
981 temp
= dev_t
->t_avdp_w
;
983 temp
= max_t(u32
, gpmc_t
->adv_on
+ gpmc_ticks_to_ps(1), temp
);
984 gpmc_t
->adv_wr_off
= gpmc_round_ps_to_ticks(temp
);
986 /* wr_data_mux_bus */
987 temp
= dev_t
->t_weasu
;
989 temp
= max_t(u32
, temp
, gpmc_t
->adv_wr_off
+ dev_t
->t_aavdh
);
990 temp
= max_t(u32
, temp
, gpmc_t
->adv_wr_off
+
991 gpmc_ticks_to_ps(dev_t
->cyc_aavdh_we
));
993 gpmc_t
->wr_data_mux_bus
= gpmc_round_ps_to_ticks(temp
);
996 if (gpmc_capability
& GPMC_HAS_WR_DATA_MUX_BUS
)
997 gpmc_t
->we_on
= gpmc_round_ps_to_ticks(dev_t
->t_weasu
);
999 gpmc_t
->we_on
= gpmc_t
->wr_data_mux_bus
;
1002 temp
= gpmc_t
->we_on
+ dev_t
->t_wpl
;
1003 gpmc_t
->we_off
= gpmc_round_ps_to_ticks(temp
);
1005 gpmc_t
->cs_wr_off
= gpmc_round_ps_to_ticks(gpmc_t
->we_off
+
1009 temp
= max_t(u32
, dev_t
->t_wr_cycle
,
1010 gpmc_t
->cs_wr_off
+ dev_t
->t_cez_w
);
1011 gpmc_t
->wr_cycle
= gpmc_round_ps_to_ticks(temp
);
1016 static int gpmc_calc_sync_common_timings(struct gpmc_timings
*gpmc_t
,
1017 struct gpmc_device_timings
*dev_t
)
1021 gpmc_t
->sync_clk
= gpmc_calc_divider(dev_t
->clk
) *
1022 gpmc_get_fclk_period();
1024 gpmc_t
->page_burst_access
= gpmc_round_ps_to_sync_clk(
1028 temp
= max_t(u32
, dev_t
->t_ces
, dev_t
->t_avds
);
1029 gpmc_t
->clk_activation
= gpmc_round_ps_to_ticks(temp
);
1031 if (gpmc_calc_divider(gpmc_t
->sync_clk
) != 1)
1034 if (dev_t
->ce_xdelay
)
1035 gpmc_t
->bool_timings
.cs_extra_delay
= true;
1036 if (dev_t
->avd_xdelay
)
1037 gpmc_t
->bool_timings
.adv_extra_delay
= true;
1038 if (dev_t
->oe_xdelay
)
1039 gpmc_t
->bool_timings
.oe_extra_delay
= true;
1040 if (dev_t
->we_xdelay
)
1041 gpmc_t
->bool_timings
.we_extra_delay
= true;
1046 static int gpmc_calc_common_timings(struct gpmc_timings
*gpmc_t
,
1047 struct gpmc_device_timings
*dev_t
,
1053 gpmc_t
->cs_on
= gpmc_round_ps_to_ticks(dev_t
->t_ceasu
);
1056 temp
= dev_t
->t_avdasu
;
1057 if (dev_t
->t_ce_avd
)
1058 temp
= max_t(u32
, temp
,
1059 gpmc_t
->cs_on
+ dev_t
->t_ce_avd
);
1060 gpmc_t
->adv_on
= gpmc_round_ps_to_ticks(temp
);
1063 gpmc_calc_sync_common_timings(gpmc_t
, dev_t
);
1068 /* TODO: remove this function once all peripherals are confirmed to
1069 * work with generic timing. Simultaneously gpmc_cs_set_timings()
1070 * has to be modified to handle timings in ps instead of ns
1072 static void gpmc_convert_ps_to_ns(struct gpmc_timings
*t
)
1075 t
->cs_rd_off
/= 1000;
1076 t
->cs_wr_off
/= 1000;
1078 t
->adv_rd_off
/= 1000;
1079 t
->adv_wr_off
/= 1000;
1084 t
->page_burst_access
/= 1000;
1086 t
->rd_cycle
/= 1000;
1087 t
->wr_cycle
/= 1000;
1088 t
->bus_turnaround
/= 1000;
1089 t
->cycle2cycle_delay
/= 1000;
1090 t
->wait_monitoring
/= 1000;
1091 t
->clk_activation
/= 1000;
1092 t
->wr_access
/= 1000;
1093 t
->wr_data_mux_bus
/= 1000;
1096 int gpmc_calc_timings(struct gpmc_timings
*gpmc_t
,
1097 struct gpmc_settings
*gpmc_s
,
1098 struct gpmc_device_timings
*dev_t
)
1100 bool mux
= false, sync
= false;
1103 mux
= gpmc_s
->mux_add_data
? true : false;
1104 sync
= (gpmc_s
->sync_read
|| gpmc_s
->sync_write
);
1107 memset(gpmc_t
, 0, sizeof(*gpmc_t
));
1109 gpmc_calc_common_timings(gpmc_t
, dev_t
, sync
);
1111 if (gpmc_s
&& gpmc_s
->sync_read
)
1112 gpmc_calc_sync_read_timings(gpmc_t
, dev_t
, mux
);
1114 gpmc_calc_async_read_timings(gpmc_t
, dev_t
, mux
);
1116 if (gpmc_s
&& gpmc_s
->sync_write
)
1117 gpmc_calc_sync_write_timings(gpmc_t
, dev_t
, mux
);
1119 gpmc_calc_async_write_timings(gpmc_t
, dev_t
, mux
);
1121 /* TODO: remove, see function definition */
1122 gpmc_convert_ps_to_ns(gpmc_t
);
1128 * gpmc_cs_program_settings - programs non-timing related settings
1129 * @cs: GPMC chip-select to program
1130 * @p: pointer to GPMC settings structure
1132 * Programs non-timing related settings for a GPMC chip-select, such as
1133 * bus-width, burst configuration, etc. Function should be called once
1134 * for each chip-select that is being used and must be called before
1135 * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1136 * register will be initialised to zero by this function. Returns 0 on
1137 * success and appropriate negative error code on failure.
1139 int gpmc_cs_program_settings(int cs
, struct gpmc_settings
*p
)
1143 if ((!p
->device_width
) || (p
->device_width
> GPMC_DEVWIDTH_16BIT
)) {
1144 pr_err("%s: invalid width %d!", __func__
, p
->device_width
);
1148 /* Address-data multiplexing not supported for NAND devices */
1149 if (p
->device_nand
&& p
->mux_add_data
) {
1150 pr_err("%s: invalid configuration!\n", __func__
);
1154 if ((p
->mux_add_data
> GPMC_MUX_AD
) ||
1155 ((p
->mux_add_data
== GPMC_MUX_AAD
) &&
1156 !(gpmc_capability
& GPMC_HAS_MUX_AAD
))) {
1157 pr_err("%s: invalid multiplex configuration!\n", __func__
);
1161 /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1162 if (p
->burst_read
|| p
->burst_write
) {
1163 switch (p
->burst_len
) {
1169 pr_err("%s: invalid page/burst-length (%d)\n",
1170 __func__
, p
->burst_len
);
1175 if ((p
->wait_on_read
|| p
->wait_on_write
) &&
1176 (p
->wait_pin
> gpmc_nr_waitpins
)) {
1177 pr_err("%s: invalid wait-pin (%d)\n", __func__
, p
->wait_pin
);
1181 config1
= GPMC_CONFIG1_DEVICESIZE((p
->device_width
- 1));
1184 config1
|= GPMC_CONFIG1_READTYPE_SYNC
;
1186 config1
|= GPMC_CONFIG1_WRITETYPE_SYNC
;
1187 if (p
->wait_on_read
)
1188 config1
|= GPMC_CONFIG1_WAIT_READ_MON
;
1189 if (p
->wait_on_write
)
1190 config1
|= GPMC_CONFIG1_WAIT_WRITE_MON
;
1191 if (p
->wait_on_read
|| p
->wait_on_write
)
1192 config1
|= GPMC_CONFIG1_WAIT_PIN_SEL(p
->wait_pin
);
1194 config1
|= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND
);
1195 if (p
->mux_add_data
)
1196 config1
|= GPMC_CONFIG1_MUXTYPE(p
->mux_add_data
);
1198 config1
|= GPMC_CONFIG1_READMULTIPLE_SUPP
;
1200 config1
|= GPMC_CONFIG1_WRITEMULTIPLE_SUPP
;
1201 if (p
->burst_read
|| p
->burst_write
) {
1202 config1
|= GPMC_CONFIG1_PAGE_LEN(p
->burst_len
>> 3);
1203 config1
|= p
->burst_wrap
? GPMC_CONFIG1_WRAPBURST_SUPP
: 0;
1206 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG1
, config1
);
1212 static struct of_device_id gpmc_dt_ids
[] = {
1213 { .compatible
= "ti,omap2420-gpmc" },
1214 { .compatible
= "ti,omap2430-gpmc" },
1215 { .compatible
= "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */
1216 { .compatible
= "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */
1217 { .compatible
= "ti,am3352-gpmc" }, /* am335x devices */
1220 MODULE_DEVICE_TABLE(of
, gpmc_dt_ids
);
1223 * gpmc_read_settings_dt - read gpmc settings from device-tree
1224 * @np: pointer to device-tree node for a gpmc child device
1225 * @p: pointer to gpmc settings structure
1227 * Reads the GPMC settings for a GPMC child device from device-tree and
1228 * stores them in the GPMC settings structure passed. The GPMC settings
1229 * structure is initialised to zero by this function and so any
1230 * previously stored settings will be cleared.
1232 void gpmc_read_settings_dt(struct device_node
*np
, struct gpmc_settings
*p
)
1234 memset(p
, 0, sizeof(struct gpmc_settings
));
1236 p
->sync_read
= of_property_read_bool(np
, "gpmc,sync-read");
1237 p
->sync_write
= of_property_read_bool(np
, "gpmc,sync-write");
1238 p
->device_nand
= of_property_read_bool(np
, "gpmc,device-nand");
1239 of_property_read_u32(np
, "gpmc,device-width", &p
->device_width
);
1240 of_property_read_u32(np
, "gpmc,mux-add-data", &p
->mux_add_data
);
1242 if (!of_property_read_u32(np
, "gpmc,burst-length", &p
->burst_len
)) {
1243 p
->burst_wrap
= of_property_read_bool(np
, "gpmc,burst-wrap");
1244 p
->burst_read
= of_property_read_bool(np
, "gpmc,burst-read");
1245 p
->burst_write
= of_property_read_bool(np
, "gpmc,burst-write");
1246 if (!p
->burst_read
&& !p
->burst_write
)
1247 pr_warn("%s: page/burst-length set but not used!\n",
1251 if (!of_property_read_u32(np
, "gpmc,wait-pin", &p
->wait_pin
)) {
1252 p
->wait_on_read
= of_property_read_bool(np
,
1253 "gpmc,wait-on-read");
1254 p
->wait_on_write
= of_property_read_bool(np
,
1255 "gpmc,wait-on-write");
1256 if (!p
->wait_on_read
&& !p
->wait_on_write
)
1257 pr_warn("%s: read/write wait monitoring not enabled!\n",
1262 static void __maybe_unused
gpmc_read_timings_dt(struct device_node
*np
,
1263 struct gpmc_timings
*gpmc_t
)
1265 struct gpmc_bool_timings
*p
;
1270 memset(gpmc_t
, 0, sizeof(*gpmc_t
));
1272 /* minimum clock period for syncronous mode */
1273 of_property_read_u32(np
, "gpmc,sync-clk-ps", &gpmc_t
->sync_clk
);
1275 /* chip select timtings */
1276 of_property_read_u32(np
, "gpmc,cs-on-ns", &gpmc_t
->cs_on
);
1277 of_property_read_u32(np
, "gpmc,cs-rd-off-ns", &gpmc_t
->cs_rd_off
);
1278 of_property_read_u32(np
, "gpmc,cs-wr-off-ns", &gpmc_t
->cs_wr_off
);
1280 /* ADV signal timings */
1281 of_property_read_u32(np
, "gpmc,adv-on-ns", &gpmc_t
->adv_on
);
1282 of_property_read_u32(np
, "gpmc,adv-rd-off-ns", &gpmc_t
->adv_rd_off
);
1283 of_property_read_u32(np
, "gpmc,adv-wr-off-ns", &gpmc_t
->adv_wr_off
);
1285 /* WE signal timings */
1286 of_property_read_u32(np
, "gpmc,we-on-ns", &gpmc_t
->we_on
);
1287 of_property_read_u32(np
, "gpmc,we-off-ns", &gpmc_t
->we_off
);
1289 /* OE signal timings */
1290 of_property_read_u32(np
, "gpmc,oe-on-ns", &gpmc_t
->oe_on
);
1291 of_property_read_u32(np
, "gpmc,oe-off-ns", &gpmc_t
->oe_off
);
1293 /* access and cycle timings */
1294 of_property_read_u32(np
, "gpmc,page-burst-access-ns",
1295 &gpmc_t
->page_burst_access
);
1296 of_property_read_u32(np
, "gpmc,access-ns", &gpmc_t
->access
);
1297 of_property_read_u32(np
, "gpmc,rd-cycle-ns", &gpmc_t
->rd_cycle
);
1298 of_property_read_u32(np
, "gpmc,wr-cycle-ns", &gpmc_t
->wr_cycle
);
1299 of_property_read_u32(np
, "gpmc,bus-turnaround-ns",
1300 &gpmc_t
->bus_turnaround
);
1301 of_property_read_u32(np
, "gpmc,cycle2cycle-delay-ns",
1302 &gpmc_t
->cycle2cycle_delay
);
1303 of_property_read_u32(np
, "gpmc,wait-monitoring-ns",
1304 &gpmc_t
->wait_monitoring
);
1305 of_property_read_u32(np
, "gpmc,clk-activation-ns",
1306 &gpmc_t
->clk_activation
);
1308 /* only applicable to OMAP3+ */
1309 of_property_read_u32(np
, "gpmc,wr-access-ns", &gpmc_t
->wr_access
);
1310 of_property_read_u32(np
, "gpmc,wr-data-mux-bus-ns",
1311 &gpmc_t
->wr_data_mux_bus
);
1313 /* bool timing parameters */
1314 p
= &gpmc_t
->bool_timings
;
1316 p
->cycle2cyclediffcsen
=
1317 of_property_read_bool(np
, "gpmc,cycle2cycle-diffcsen");
1318 p
->cycle2cyclesamecsen
=
1319 of_property_read_bool(np
, "gpmc,cycle2cycle-samecsen");
1320 p
->we_extra_delay
= of_property_read_bool(np
, "gpmc,we-extra-delay");
1321 p
->oe_extra_delay
= of_property_read_bool(np
, "gpmc,oe-extra-delay");
1322 p
->adv_extra_delay
= of_property_read_bool(np
, "gpmc,adv-extra-delay");
1323 p
->cs_extra_delay
= of_property_read_bool(np
, "gpmc,cs-extra-delay");
1324 p
->time_para_granularity
=
1325 of_property_read_bool(np
, "gpmc,time-para-granularity");
1328 #ifdef CONFIG_MTD_NAND
1330 static const char * const nand_ecc_opts
[] = {
1331 [OMAP_ECC_HAMMING_CODE_DEFAULT
] = "sw",
1332 [OMAP_ECC_HAMMING_CODE_HW
] = "hw",
1333 [OMAP_ECC_HAMMING_CODE_HW_ROMCODE
] = "hw-romcode",
1334 [OMAP_ECC_BCH4_CODE_HW
] = "bch4",
1335 [OMAP_ECC_BCH8_CODE_HW
] = "bch8",
1338 static int gpmc_probe_nand_child(struct platform_device
*pdev
,
1339 struct device_node
*child
)
1343 struct gpmc_timings gpmc_t
;
1344 struct omap_nand_platform_data
*gpmc_nand_data
;
1346 if (of_property_read_u32(child
, "reg", &val
) < 0) {
1347 dev_err(&pdev
->dev
, "%s has no 'reg' property\n",
1352 gpmc_nand_data
= devm_kzalloc(&pdev
->dev
, sizeof(*gpmc_nand_data
),
1354 if (!gpmc_nand_data
)
1357 gpmc_nand_data
->cs
= val
;
1358 gpmc_nand_data
->of_node
= child
;
1360 if (!of_property_read_string(child
, "ti,nand-ecc-opt", &s
))
1361 for (val
= 0; val
< ARRAY_SIZE(nand_ecc_opts
); val
++)
1362 if (!strcasecmp(s
, nand_ecc_opts
[val
])) {
1363 gpmc_nand_data
->ecc_opt
= val
;
1367 val
= of_get_nand_bus_width(child
);
1369 gpmc_nand_data
->devsize
= NAND_BUSWIDTH_16
;
1371 gpmc_read_timings_dt(child
, &gpmc_t
);
1372 gpmc_nand_init(gpmc_nand_data
, &gpmc_t
);
1377 static int gpmc_probe_nand_child(struct platform_device
*pdev
,
1378 struct device_node
*child
)
1384 #ifdef CONFIG_MTD_ONENAND
1385 static int gpmc_probe_onenand_child(struct platform_device
*pdev
,
1386 struct device_node
*child
)
1389 struct omap_onenand_platform_data
*gpmc_onenand_data
;
1391 if (of_property_read_u32(child
, "reg", &val
) < 0) {
1392 dev_err(&pdev
->dev
, "%s has no 'reg' property\n",
1397 gpmc_onenand_data
= devm_kzalloc(&pdev
->dev
, sizeof(*gpmc_onenand_data
),
1399 if (!gpmc_onenand_data
)
1402 gpmc_onenand_data
->cs
= val
;
1403 gpmc_onenand_data
->of_node
= child
;
1404 gpmc_onenand_data
->dma_channel
= -1;
1406 if (!of_property_read_u32(child
, "dma-channel", &val
))
1407 gpmc_onenand_data
->dma_channel
= val
;
1409 gpmc_onenand_init(gpmc_onenand_data
);
1414 static int gpmc_probe_onenand_child(struct platform_device
*pdev
,
1415 struct device_node
*child
)
1422 * gpmc_probe_nor_child - configures the gpmc for a nor device
1423 * @pdev: pointer to gpmc platform device
1424 * @child: pointer to device-tree node for nor device
1426 * Allocates and configures a GPMC chip-select for a NOR flash device.
1427 * Returns 0 on success and appropriate negative error code on failure.
1429 static int gpmc_probe_nor_child(struct platform_device
*pdev
,
1430 struct device_node
*child
)
1432 struct gpmc_settings gpmc_s
;
1433 struct gpmc_timings gpmc_t
;
1434 struct resource res
;
1438 if (of_property_read_u32(child
, "reg", &cs
) < 0) {
1439 dev_err(&pdev
->dev
, "%s has no 'reg' property\n",
1444 if (of_address_to_resource(child
, 0, &res
) < 0) {
1445 dev_err(&pdev
->dev
, "%s has malformed 'reg' property\n",
1450 ret
= gpmc_cs_request(cs
, resource_size(&res
), &base
);
1452 dev_err(&pdev
->dev
, "cannot request GPMC CS %d\n", cs
);
1457 * FIXME: gpmc_cs_request() will map the CS to an arbitary
1458 * location in the gpmc address space. When booting with
1459 * device-tree we want the NOR flash to be mapped to the
1460 * location specified in the device-tree blob. So remap the
1461 * CS to this location. Once DT migration is complete should
1462 * just make gpmc_cs_request() map a specific address.
1464 ret
= gpmc_cs_remap(cs
, res
.start
);
1466 dev_err(&pdev
->dev
, "cannot remap GPMC CS %d to 0x%x\n",
1471 gpmc_read_settings_dt(child
, &gpmc_s
);
1473 ret
= of_property_read_u32(child
, "bank-width", &gpmc_s
.device_width
);
1477 ret
= gpmc_cs_program_settings(cs
, &gpmc_s
);
1481 gpmc_read_timings_dt(child
, &gpmc_t
);
1482 gpmc_cs_set_timings(cs
, &gpmc_t
);
1484 if (of_platform_device_create(child
, NULL
, &pdev
->dev
))
1487 dev_err(&pdev
->dev
, "failed to create gpmc child %s\n", child
->name
);
1495 static int gpmc_probe_dt(struct platform_device
*pdev
)
1498 struct device_node
*child
;
1499 const struct of_device_id
*of_id
=
1500 of_match_device(gpmc_dt_ids
, &pdev
->dev
);
1505 ret
= of_property_read_u32(pdev
->dev
.of_node
, "gpmc,num-waitpins",
1508 pr_err("%s: number of wait pins not found!\n", __func__
);
1512 for_each_node_by_name(child
, "nand") {
1513 ret
= gpmc_probe_nand_child(pdev
, child
);
1520 for_each_node_by_name(child
, "onenand") {
1521 ret
= gpmc_probe_onenand_child(pdev
, child
);
1528 for_each_node_by_name(child
, "nor") {
1529 ret
= gpmc_probe_nor_child(pdev
, child
);
1539 static int gpmc_probe_dt(struct platform_device
*pdev
)
1545 static int gpmc_probe(struct platform_device
*pdev
)
1549 struct resource
*res
;
1551 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1555 phys_base
= res
->start
;
1556 mem_size
= resource_size(res
);
1558 gpmc_base
= devm_ioremap_resource(&pdev
->dev
, res
);
1559 if (IS_ERR(gpmc_base
))
1560 return PTR_ERR(gpmc_base
);
1562 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
1564 dev_warn(&pdev
->dev
, "Failed to get resource: irq\n");
1566 gpmc_irq
= res
->start
;
1568 gpmc_l3_clk
= clk_get(&pdev
->dev
, "fck");
1569 if (IS_ERR(gpmc_l3_clk
)) {
1570 dev_err(&pdev
->dev
, "error: clk_get\n");
1572 return PTR_ERR(gpmc_l3_clk
);
1575 clk_prepare_enable(gpmc_l3_clk
);
1577 gpmc_dev
= &pdev
->dev
;
1579 l
= gpmc_read_reg(GPMC_REVISION
);
1582 * FIXME: Once device-tree migration is complete the below flags
1583 * should be populated based upon the device-tree compatible
1584 * string. For now just use the IP revision. OMAP3+ devices have
1585 * the wr_access and wr_data_mux_bus register fields. OMAP4+
1586 * devices support the addr-addr-data multiplex protocol.
1588 * GPMC IP revisions:
1591 * - OMAP44xx/54xx/AM335x = 6.0
1593 if (GPMC_REVISION_MAJOR(l
) > 0x4)
1594 gpmc_capability
= GPMC_HAS_WR_ACCESS
| GPMC_HAS_WR_DATA_MUX_BUS
;
1595 if (GPMC_REVISION_MAJOR(l
) > 0x5)
1596 gpmc_capability
|= GPMC_HAS_MUX_AAD
;
1597 dev_info(gpmc_dev
, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l
),
1598 GPMC_REVISION_MINOR(l
));
1600 rc
= gpmc_mem_init();
1602 clk_disable_unprepare(gpmc_l3_clk
);
1603 clk_put(gpmc_l3_clk
);
1604 dev_err(gpmc_dev
, "failed to reserve memory\n");
1608 if (gpmc_setup_irq() < 0)
1609 dev_warn(gpmc_dev
, "gpmc_setup_irq failed\n");
1611 /* Now the GPMC is initialised, unreserve the chip-selects */
1614 if (!pdev
->dev
.of_node
)
1615 gpmc_nr_waitpins
= GPMC_NR_WAITPINS
;
1617 rc
= gpmc_probe_dt(pdev
);
1619 clk_disable_unprepare(gpmc_l3_clk
);
1620 clk_put(gpmc_l3_clk
);
1621 dev_err(gpmc_dev
, "failed to probe DT parameters\n");
1628 static int gpmc_remove(struct platform_device
*pdev
)
1636 static struct platform_driver gpmc_driver
= {
1637 .probe
= gpmc_probe
,
1638 .remove
= gpmc_remove
,
1640 .name
= DEVICE_NAME
,
1641 .owner
= THIS_MODULE
,
1642 .of_match_table
= of_match_ptr(gpmc_dt_ids
),
1646 static __init
int gpmc_init(void)
1648 return platform_driver_register(&gpmc_driver
);
1651 static __exit
void gpmc_exit(void)
1653 platform_driver_unregister(&gpmc_driver
);
1657 omap_postcore_initcall(gpmc_init
);
1658 module_exit(gpmc_exit
);
1660 static int __init
omap_gpmc_init(void)
1662 struct omap_hwmod
*oh
;
1663 struct platform_device
*pdev
;
1664 char *oh_name
= "gpmc";
1667 * if the board boots up with a populated DT, do not
1668 * manually add the device from this initcall
1670 if (of_have_populated_dt())
1673 oh
= omap_hwmod_lookup(oh_name
);
1675 pr_err("Could not look up %s\n", oh_name
);
1679 pdev
= omap_device_build(DEVICE_NAME
, -1, oh
, NULL
, 0);
1680 WARN(IS_ERR(pdev
), "could not build omap_device for %s\n", oh_name
);
1682 return IS_ERR(pdev
) ? PTR_ERR(pdev
) : 0;
1684 omap_postcore_initcall(omap_gpmc_init
);
1686 static irqreturn_t
gpmc_handle_irq(int irq
, void *dev
)
1691 regval
= gpmc_read_reg(GPMC_IRQSTATUS
);
1696 for (i
= 0; i
< GPMC_NR_IRQ
; i
++)
1697 if (regval
& gpmc_client_irq
[i
].bitmask
)
1698 generic_handle_irq(gpmc_client_irq
[i
].irq
);
1700 gpmc_write_reg(GPMC_IRQSTATUS
, regval
);
1705 #ifdef CONFIG_ARCH_OMAP3
1706 static struct omap3_gpmc_regs gpmc_context
;
1708 void omap3_gpmc_save_context(void)
1712 gpmc_context
.sysconfig
= gpmc_read_reg(GPMC_SYSCONFIG
);
1713 gpmc_context
.irqenable
= gpmc_read_reg(GPMC_IRQENABLE
);
1714 gpmc_context
.timeout_ctrl
= gpmc_read_reg(GPMC_TIMEOUT_CONTROL
);
1715 gpmc_context
.config
= gpmc_read_reg(GPMC_CONFIG
);
1716 gpmc_context
.prefetch_config1
= gpmc_read_reg(GPMC_PREFETCH_CONFIG1
);
1717 gpmc_context
.prefetch_config2
= gpmc_read_reg(GPMC_PREFETCH_CONFIG2
);
1718 gpmc_context
.prefetch_control
= gpmc_read_reg(GPMC_PREFETCH_CONTROL
);
1719 for (i
= 0; i
< GPMC_CS_NUM
; i
++) {
1720 gpmc_context
.cs_context
[i
].is_valid
= gpmc_cs_mem_enabled(i
);
1721 if (gpmc_context
.cs_context
[i
].is_valid
) {
1722 gpmc_context
.cs_context
[i
].config1
=
1723 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG1
);
1724 gpmc_context
.cs_context
[i
].config2
=
1725 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG2
);
1726 gpmc_context
.cs_context
[i
].config3
=
1727 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG3
);
1728 gpmc_context
.cs_context
[i
].config4
=
1729 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG4
);
1730 gpmc_context
.cs_context
[i
].config5
=
1731 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG5
);
1732 gpmc_context
.cs_context
[i
].config6
=
1733 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG6
);
1734 gpmc_context
.cs_context
[i
].config7
=
1735 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG7
);
1740 void omap3_gpmc_restore_context(void)
1744 gpmc_write_reg(GPMC_SYSCONFIG
, gpmc_context
.sysconfig
);
1745 gpmc_write_reg(GPMC_IRQENABLE
, gpmc_context
.irqenable
);
1746 gpmc_write_reg(GPMC_TIMEOUT_CONTROL
, gpmc_context
.timeout_ctrl
);
1747 gpmc_write_reg(GPMC_CONFIG
, gpmc_context
.config
);
1748 gpmc_write_reg(GPMC_PREFETCH_CONFIG1
, gpmc_context
.prefetch_config1
);
1749 gpmc_write_reg(GPMC_PREFETCH_CONFIG2
, gpmc_context
.prefetch_config2
);
1750 gpmc_write_reg(GPMC_PREFETCH_CONTROL
, gpmc_context
.prefetch_control
);
1751 for (i
= 0; i
< GPMC_CS_NUM
; i
++) {
1752 if (gpmc_context
.cs_context
[i
].is_valid
) {
1753 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG1
,
1754 gpmc_context
.cs_context
[i
].config1
);
1755 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG2
,
1756 gpmc_context
.cs_context
[i
].config2
);
1757 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG3
,
1758 gpmc_context
.cs_context
[i
].config3
);
1759 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG4
,
1760 gpmc_context
.cs_context
[i
].config4
);
1761 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG5
,
1762 gpmc_context
.cs_context
[i
].config5
);
1763 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG6
,
1764 gpmc_context
.cs_context
[i
].config6
);
1765 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG7
,
1766 gpmc_context
.cs_context
[i
].config7
);
1770 #endif /* CONFIG_ARCH_OMAP3 */