2 * GPMC support functions
4 * Copyright (C) 2005-2006 Nokia Corporation
8 * Copyright (C) 2009 Texas Instruments
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/irq.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
22 #include <linux/ioport.h>
23 #include <linux/spinlock.h>
25 #include <linux/module.h>
26 #include <linux/interrupt.h>
27 #include <linux/platform_device.h>
29 #include <linux/of_address.h>
30 #include <linux/of_mtd.h>
31 #include <linux/of_device.h>
32 #include <linux/mtd/nand.h>
34 #include <linux/platform_data/mtd-nand-omap2.h>
36 #include <asm/mach-types.h>
40 #include "omap_device.h"
42 #include "gpmc-nand.h"
43 #include "gpmc-onenand.h"
45 #define DEVICE_NAME "omap-gpmc"
47 /* GPMC register offsets */
48 #define GPMC_REVISION 0x00
49 #define GPMC_SYSCONFIG 0x10
50 #define GPMC_SYSSTATUS 0x14
51 #define GPMC_IRQSTATUS 0x18
52 #define GPMC_IRQENABLE 0x1c
53 #define GPMC_TIMEOUT_CONTROL 0x40
54 #define GPMC_ERR_ADDRESS 0x44
55 #define GPMC_ERR_TYPE 0x48
56 #define GPMC_CONFIG 0x50
57 #define GPMC_STATUS 0x54
58 #define GPMC_PREFETCH_CONFIG1 0x1e0
59 #define GPMC_PREFETCH_CONFIG2 0x1e4
60 #define GPMC_PREFETCH_CONTROL 0x1ec
61 #define GPMC_PREFETCH_STATUS 0x1f0
62 #define GPMC_ECC_CONFIG 0x1f4
63 #define GPMC_ECC_CONTROL 0x1f8
64 #define GPMC_ECC_SIZE_CONFIG 0x1fc
65 #define GPMC_ECC1_RESULT 0x200
66 #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
67 #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
68 #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
69 #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
71 /* GPMC ECC control settings */
72 #define GPMC_ECC_CTRL_ECCCLEAR 0x100
73 #define GPMC_ECC_CTRL_ECCDISABLE 0x000
74 #define GPMC_ECC_CTRL_ECCREG1 0x001
75 #define GPMC_ECC_CTRL_ECCREG2 0x002
76 #define GPMC_ECC_CTRL_ECCREG3 0x003
77 #define GPMC_ECC_CTRL_ECCREG4 0x004
78 #define GPMC_ECC_CTRL_ECCREG5 0x005
79 #define GPMC_ECC_CTRL_ECCREG6 0x006
80 #define GPMC_ECC_CTRL_ECCREG7 0x007
81 #define GPMC_ECC_CTRL_ECCREG8 0x008
82 #define GPMC_ECC_CTRL_ECCREG9 0x009
84 #define GPMC_CONFIG2_CSEXTRADELAY BIT(7)
85 #define GPMC_CONFIG3_ADVEXTRADELAY BIT(7)
86 #define GPMC_CONFIG4_OEEXTRADELAY BIT(7)
87 #define GPMC_CONFIG4_WEEXTRADELAY BIT(23)
88 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6)
89 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7)
91 #define GPMC_CS0_OFFSET 0x60
92 #define GPMC_CS_SIZE 0x30
93 #define GPMC_BCH_SIZE 0x10
95 #define GPMC_MEM_END 0x3FFFFFFF
97 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
98 #define GPMC_SECTION_SHIFT 28 /* 128 MB */
100 #define CS_NUM_SHIFT 24
101 #define ENABLE_PREFETCH (0x1 << 7)
102 #define DMA_MPU_MODE 2
104 #define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf)
105 #define GPMC_REVISION_MINOR(l) (l & 0xf)
107 #define GPMC_HAS_WR_ACCESS 0x1
108 #define GPMC_HAS_WR_DATA_MUX_BUS 0x2
109 #define GPMC_HAS_MUX_AAD 0x4
111 #define GPMC_NR_WAITPINS 4
113 /* XXX: Only NAND irq has been considered,currently these are the only ones used
115 #define GPMC_NR_IRQ 2
117 struct gpmc_client_irq
{
122 /* Structure to save gpmc cs context */
123 struct gpmc_cs_config
{
135 * Structure to save/restore gpmc context
136 * to support core off on OMAP3
138 struct omap3_gpmc_regs
{
143 u32 prefetch_config1
;
144 u32 prefetch_config2
;
145 u32 prefetch_control
;
146 struct gpmc_cs_config cs_context
[GPMC_CS_NUM
];
149 static struct gpmc_client_irq gpmc_client_irq
[GPMC_NR_IRQ
];
150 static struct irq_chip gpmc_irq_chip
;
151 static unsigned gpmc_irq_start
;
153 static struct resource gpmc_mem_root
;
154 static struct resource gpmc_cs_mem
[GPMC_CS_NUM
];
155 static DEFINE_SPINLOCK(gpmc_mem_lock
);
156 /* Define chip-selects as reserved by default until probe completes */
157 static unsigned int gpmc_cs_map
= ((1 << GPMC_CS_NUM
) - 1);
158 static unsigned int gpmc_nr_waitpins
;
159 static struct device
*gpmc_dev
;
161 static resource_size_t phys_base
, mem_size
;
162 static unsigned gpmc_capability
;
163 static void __iomem
*gpmc_base
;
165 static struct clk
*gpmc_l3_clk
;
167 static irqreturn_t
gpmc_handle_irq(int irq
, void *dev
);
169 static void gpmc_write_reg(int idx
, u32 val
)
171 __raw_writel(val
, gpmc_base
+ idx
);
174 static u32
gpmc_read_reg(int idx
)
176 return __raw_readl(gpmc_base
+ idx
);
179 void gpmc_cs_write_reg(int cs
, int idx
, u32 val
)
181 void __iomem
*reg_addr
;
183 reg_addr
= gpmc_base
+ GPMC_CS0_OFFSET
+ (cs
* GPMC_CS_SIZE
) + idx
;
184 __raw_writel(val
, reg_addr
);
187 static u32
gpmc_cs_read_reg(int cs
, int idx
)
189 void __iomem
*reg_addr
;
191 reg_addr
= gpmc_base
+ GPMC_CS0_OFFSET
+ (cs
* GPMC_CS_SIZE
) + idx
;
192 return __raw_readl(reg_addr
);
195 /* TODO: Add support for gpmc_fck to clock framework and use it */
196 static unsigned long gpmc_get_fclk_period(void)
198 unsigned long rate
= clk_get_rate(gpmc_l3_clk
);
201 printk(KERN_WARNING
"gpmc_l3_clk not enabled\n");
206 rate
= 1000000000 / rate
; /* In picoseconds */
211 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns
)
213 unsigned long tick_ps
;
215 /* Calculate in picosecs to yield more exact results */
216 tick_ps
= gpmc_get_fclk_period();
218 return (time_ns
* 1000 + tick_ps
- 1) / tick_ps
;
221 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps
)
223 unsigned long tick_ps
;
225 /* Calculate in picosecs to yield more exact results */
226 tick_ps
= gpmc_get_fclk_period();
228 return (time_ps
+ tick_ps
- 1) / tick_ps
;
231 unsigned int gpmc_ticks_to_ns(unsigned int ticks
)
233 return ticks
* gpmc_get_fclk_period() / 1000;
236 static unsigned int gpmc_ticks_to_ps(unsigned int ticks
)
238 return ticks
* gpmc_get_fclk_period();
241 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps
)
243 unsigned long ticks
= gpmc_ps_to_ticks(time_ps
);
245 return ticks
* gpmc_get_fclk_period();
248 static inline void gpmc_cs_modify_reg(int cs
, int reg
, u32 mask
, bool value
)
252 l
= gpmc_cs_read_reg(cs
, reg
);
257 gpmc_cs_write_reg(cs
, reg
, l
);
260 static void gpmc_cs_bool_timings(int cs
, const struct gpmc_bool_timings
*p
)
262 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG1
,
263 GPMC_CONFIG1_TIME_PARA_GRAN
,
264 p
->time_para_granularity
);
265 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG2
,
266 GPMC_CONFIG2_CSEXTRADELAY
, p
->cs_extra_delay
);
267 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG3
,
268 GPMC_CONFIG3_ADVEXTRADELAY
, p
->adv_extra_delay
);
269 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG4
,
270 GPMC_CONFIG4_OEEXTRADELAY
, p
->oe_extra_delay
);
271 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG4
,
272 GPMC_CONFIG4_OEEXTRADELAY
, p
->we_extra_delay
);
273 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG6
,
274 GPMC_CONFIG6_CYCLE2CYCLESAMECSEN
,
275 p
->cycle2cyclesamecsen
);
276 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG6
,
277 GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN
,
278 p
->cycle2cyclediffcsen
);
282 static int set_gpmc_timing_reg(int cs
, int reg
, int st_bit
, int end_bit
,
283 int time
, const char *name
)
285 static int set_gpmc_timing_reg(int cs
, int reg
, int st_bit
, int end_bit
,
290 int ticks
, mask
, nr_bits
;
295 ticks
= gpmc_ns_to_ticks(time
);
296 nr_bits
= end_bit
- st_bit
+ 1;
297 if (ticks
>= 1 << nr_bits
) {
299 printk(KERN_INFO
"GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
300 cs
, name
, time
, ticks
, 1 << nr_bits
);
305 mask
= (1 << nr_bits
) - 1;
306 l
= gpmc_cs_read_reg(cs
, reg
);
309 "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
310 cs
, name
, ticks
, gpmc_get_fclk_period() * ticks
/ 1000,
311 (l
>> st_bit
) & mask
, time
);
313 l
&= ~(mask
<< st_bit
);
314 l
|= ticks
<< st_bit
;
315 gpmc_cs_write_reg(cs
, reg
, l
);
321 #define GPMC_SET_ONE(reg, st, end, field) \
322 if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
323 t->field, #field) < 0) \
326 #define GPMC_SET_ONE(reg, st, end, field) \
327 if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
331 int gpmc_calc_divider(unsigned int sync_clk
)
336 l
= sync_clk
+ (gpmc_get_fclk_period() - 1);
337 div
= l
/ gpmc_get_fclk_period();
346 int gpmc_cs_set_timings(int cs
, const struct gpmc_timings
*t
)
351 div
= gpmc_calc_divider(t
->sync_clk
);
355 GPMC_SET_ONE(GPMC_CS_CONFIG2
, 0, 3, cs_on
);
356 GPMC_SET_ONE(GPMC_CS_CONFIG2
, 8, 12, cs_rd_off
);
357 GPMC_SET_ONE(GPMC_CS_CONFIG2
, 16, 20, cs_wr_off
);
359 GPMC_SET_ONE(GPMC_CS_CONFIG3
, 0, 3, adv_on
);
360 GPMC_SET_ONE(GPMC_CS_CONFIG3
, 8, 12, adv_rd_off
);
361 GPMC_SET_ONE(GPMC_CS_CONFIG3
, 16, 20, adv_wr_off
);
363 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 0, 3, oe_on
);
364 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 8, 12, oe_off
);
365 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 16, 19, we_on
);
366 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 24, 28, we_off
);
368 GPMC_SET_ONE(GPMC_CS_CONFIG5
, 0, 4, rd_cycle
);
369 GPMC_SET_ONE(GPMC_CS_CONFIG5
, 8, 12, wr_cycle
);
370 GPMC_SET_ONE(GPMC_CS_CONFIG5
, 16, 20, access
);
372 GPMC_SET_ONE(GPMC_CS_CONFIG5
, 24, 27, page_burst_access
);
374 GPMC_SET_ONE(GPMC_CS_CONFIG6
, 0, 3, bus_turnaround
);
375 GPMC_SET_ONE(GPMC_CS_CONFIG6
, 8, 11, cycle2cycle_delay
);
377 GPMC_SET_ONE(GPMC_CS_CONFIG1
, 18, 19, wait_monitoring
);
378 GPMC_SET_ONE(GPMC_CS_CONFIG1
, 25, 26, clk_activation
);
380 if (gpmc_capability
& GPMC_HAS_WR_DATA_MUX_BUS
)
381 GPMC_SET_ONE(GPMC_CS_CONFIG6
, 16, 19, wr_data_mux_bus
);
382 if (gpmc_capability
& GPMC_HAS_WR_ACCESS
)
383 GPMC_SET_ONE(GPMC_CS_CONFIG6
, 24, 28, wr_access
);
385 /* caller is expected to have initialized CONFIG1 to cover
386 * at least sync vs async
388 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG1
);
389 if (l
& (GPMC_CONFIG1_READTYPE_SYNC
| GPMC_CONFIG1_WRITETYPE_SYNC
)) {
391 printk(KERN_INFO
"GPMC CS%d CLK period is %lu ns (div %d)\n",
392 cs
, (div
* gpmc_get_fclk_period()) / 1000, div
);
396 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG1
, l
);
399 gpmc_cs_bool_timings(cs
, &t
->bool_timings
);
404 static int gpmc_cs_enable_mem(int cs
, u32 base
, u32 size
)
410 * Ensure that base address is aligned on a
411 * boundary equal to or greater than size.
413 if (base
& (size
- 1))
416 mask
= (1 << GPMC_SECTION_SHIFT
) - size
;
417 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
419 l
= (base
>> GPMC_CHUNK_SHIFT
) & 0x3f;
421 l
|= ((mask
>> GPMC_CHUNK_SHIFT
) & 0x0f) << 8;
422 l
|= GPMC_CONFIG7_CSVALID
;
423 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG7
, l
);
428 static void gpmc_cs_disable_mem(int cs
)
432 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
433 l
&= ~GPMC_CONFIG7_CSVALID
;
434 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG7
, l
);
437 static void gpmc_cs_get_memconf(int cs
, u32
*base
, u32
*size
)
442 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
443 *base
= (l
& 0x3f) << GPMC_CHUNK_SHIFT
;
444 mask
= (l
>> 8) & 0x0f;
445 *size
= (1 << GPMC_SECTION_SHIFT
) - (mask
<< GPMC_CHUNK_SHIFT
);
448 static int gpmc_cs_mem_enabled(int cs
)
452 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
453 return l
& GPMC_CONFIG7_CSVALID
;
456 static void gpmc_cs_set_reserved(int cs
, int reserved
)
458 gpmc_cs_map
&= ~(1 << cs
);
459 gpmc_cs_map
|= (reserved
? 1 : 0) << cs
;
462 static bool gpmc_cs_reserved(int cs
)
464 return gpmc_cs_map
& (1 << cs
);
467 static unsigned long gpmc_mem_align(unsigned long size
)
471 size
= (size
- 1) >> (GPMC_CHUNK_SHIFT
- 1);
472 order
= GPMC_CHUNK_SHIFT
- 1;
481 static int gpmc_cs_insert_mem(int cs
, unsigned long base
, unsigned long size
)
483 struct resource
*res
= &gpmc_cs_mem
[cs
];
486 size
= gpmc_mem_align(size
);
487 spin_lock(&gpmc_mem_lock
);
489 res
->end
= base
+ size
- 1;
490 r
= request_resource(&gpmc_mem_root
, res
);
491 spin_unlock(&gpmc_mem_lock
);
496 static int gpmc_cs_delete_mem(int cs
)
498 struct resource
*res
= &gpmc_cs_mem
[cs
];
501 spin_lock(&gpmc_mem_lock
);
502 r
= release_resource(&gpmc_cs_mem
[cs
]);
505 spin_unlock(&gpmc_mem_lock
);
511 * gpmc_cs_remap - remaps a chip-select physical base address
512 * @cs: chip-select to remap
513 * @base: physical base address to re-map chip-select to
515 * Re-maps a chip-select to a new physical base address specified by
516 * "base". Returns 0 on success and appropriate negative error code
519 static int gpmc_cs_remap(int cs
, u32 base
)
524 if (cs
> GPMC_CS_NUM
)
526 gpmc_cs_get_memconf(cs
, &old_base
, &size
);
527 if (base
== old_base
)
529 gpmc_cs_disable_mem(cs
);
530 ret
= gpmc_cs_delete_mem(cs
);
533 ret
= gpmc_cs_insert_mem(cs
, base
, size
);
536 ret
= gpmc_cs_enable_mem(cs
, base
, size
);
543 int gpmc_cs_request(int cs
, unsigned long size
, unsigned long *base
)
545 struct resource
*res
= &gpmc_cs_mem
[cs
];
548 if (cs
> GPMC_CS_NUM
)
551 size
= gpmc_mem_align(size
);
552 if (size
> (1 << GPMC_SECTION_SHIFT
))
555 spin_lock(&gpmc_mem_lock
);
556 if (gpmc_cs_reserved(cs
)) {
560 if (gpmc_cs_mem_enabled(cs
))
561 r
= adjust_resource(res
, res
->start
& ~(size
- 1), size
);
563 r
= allocate_resource(&gpmc_mem_root
, res
, size
, 0, ~0,
568 r
= gpmc_cs_enable_mem(cs
, res
->start
, resource_size(res
));
570 release_resource(res
);
575 gpmc_cs_set_reserved(cs
, 1);
577 spin_unlock(&gpmc_mem_lock
);
580 EXPORT_SYMBOL(gpmc_cs_request
);
582 void gpmc_cs_free(int cs
)
584 spin_lock(&gpmc_mem_lock
);
585 if (cs
>= GPMC_CS_NUM
|| cs
< 0 || !gpmc_cs_reserved(cs
)) {
586 printk(KERN_ERR
"Trying to free non-reserved GPMC CS%d\n", cs
);
588 spin_unlock(&gpmc_mem_lock
);
591 gpmc_cs_disable_mem(cs
);
592 release_resource(&gpmc_cs_mem
[cs
]);
593 gpmc_cs_set_reserved(cs
, 0);
594 spin_unlock(&gpmc_mem_lock
);
596 EXPORT_SYMBOL(gpmc_cs_free
);
599 * gpmc_configure - write request to configure gpmc
601 * @wval: value to write
602 * @return status of the operation
604 int gpmc_configure(int cmd
, int wval
)
609 case GPMC_ENABLE_IRQ
:
610 gpmc_write_reg(GPMC_IRQENABLE
, wval
);
613 case GPMC_SET_IRQ_STATUS
:
614 gpmc_write_reg(GPMC_IRQSTATUS
, wval
);
618 regval
= gpmc_read_reg(GPMC_CONFIG
);
620 regval
&= ~GPMC_CONFIG_WRITEPROTECT
; /* WP is ON */
622 regval
|= GPMC_CONFIG_WRITEPROTECT
; /* WP is OFF */
623 gpmc_write_reg(GPMC_CONFIG
, regval
);
627 pr_err("%s: command not supported\n", __func__
);
633 EXPORT_SYMBOL(gpmc_configure
);
635 void gpmc_update_nand_reg(struct gpmc_nand_regs
*reg
, int cs
)
639 reg
->gpmc_status
= gpmc_base
+ GPMC_STATUS
;
640 reg
->gpmc_nand_command
= gpmc_base
+ GPMC_CS0_OFFSET
+
641 GPMC_CS_NAND_COMMAND
+ GPMC_CS_SIZE
* cs
;
642 reg
->gpmc_nand_address
= gpmc_base
+ GPMC_CS0_OFFSET
+
643 GPMC_CS_NAND_ADDRESS
+ GPMC_CS_SIZE
* cs
;
644 reg
->gpmc_nand_data
= gpmc_base
+ GPMC_CS0_OFFSET
+
645 GPMC_CS_NAND_DATA
+ GPMC_CS_SIZE
* cs
;
646 reg
->gpmc_prefetch_config1
= gpmc_base
+ GPMC_PREFETCH_CONFIG1
;
647 reg
->gpmc_prefetch_config2
= gpmc_base
+ GPMC_PREFETCH_CONFIG2
;
648 reg
->gpmc_prefetch_control
= gpmc_base
+ GPMC_PREFETCH_CONTROL
;
649 reg
->gpmc_prefetch_status
= gpmc_base
+ GPMC_PREFETCH_STATUS
;
650 reg
->gpmc_ecc_config
= gpmc_base
+ GPMC_ECC_CONFIG
;
651 reg
->gpmc_ecc_control
= gpmc_base
+ GPMC_ECC_CONTROL
;
652 reg
->gpmc_ecc_size_config
= gpmc_base
+ GPMC_ECC_SIZE_CONFIG
;
653 reg
->gpmc_ecc1_result
= gpmc_base
+ GPMC_ECC1_RESULT
;
655 for (i
= 0; i
< GPMC_BCH_NUM_REMAINDER
; i
++) {
656 reg
->gpmc_bch_result0
[i
] = gpmc_base
+ GPMC_ECC_BCH_RESULT_0
+
658 reg
->gpmc_bch_result1
[i
] = gpmc_base
+ GPMC_ECC_BCH_RESULT_1
+
660 reg
->gpmc_bch_result2
[i
] = gpmc_base
+ GPMC_ECC_BCH_RESULT_2
+
662 reg
->gpmc_bch_result3
[i
] = gpmc_base
+ GPMC_ECC_BCH_RESULT_3
+
667 int gpmc_get_client_irq(unsigned irq_config
)
671 if (hweight32(irq_config
) > 1)
674 for (i
= 0; i
< GPMC_NR_IRQ
; i
++)
675 if (gpmc_client_irq
[i
].bitmask
& irq_config
)
676 return gpmc_client_irq
[i
].irq
;
681 static int gpmc_irq_endis(unsigned irq
, bool endis
)
686 for (i
= 0; i
< GPMC_NR_IRQ
; i
++)
687 if (irq
== gpmc_client_irq
[i
].irq
) {
688 regval
= gpmc_read_reg(GPMC_IRQENABLE
);
690 regval
|= gpmc_client_irq
[i
].bitmask
;
692 regval
&= ~gpmc_client_irq
[i
].bitmask
;
693 gpmc_write_reg(GPMC_IRQENABLE
, regval
);
700 static void gpmc_irq_disable(struct irq_data
*p
)
702 gpmc_irq_endis(p
->irq
, false);
705 static void gpmc_irq_enable(struct irq_data
*p
)
707 gpmc_irq_endis(p
->irq
, true);
710 static void gpmc_irq_noop(struct irq_data
*data
) { }
712 static unsigned int gpmc_irq_noop_ret(struct irq_data
*data
) { return 0; }
714 static int gpmc_setup_irq(void)
722 gpmc_irq_start
= irq_alloc_descs(-1, 0, GPMC_NR_IRQ
, 0);
723 if (gpmc_irq_start
< 0) {
724 pr_err("irq_alloc_descs failed\n");
725 return gpmc_irq_start
;
728 gpmc_irq_chip
.name
= "gpmc";
729 gpmc_irq_chip
.irq_startup
= gpmc_irq_noop_ret
;
730 gpmc_irq_chip
.irq_enable
= gpmc_irq_enable
;
731 gpmc_irq_chip
.irq_disable
= gpmc_irq_disable
;
732 gpmc_irq_chip
.irq_shutdown
= gpmc_irq_noop
;
733 gpmc_irq_chip
.irq_ack
= gpmc_irq_noop
;
734 gpmc_irq_chip
.irq_mask
= gpmc_irq_noop
;
735 gpmc_irq_chip
.irq_unmask
= gpmc_irq_noop
;
737 gpmc_client_irq
[0].bitmask
= GPMC_IRQ_FIFOEVENTENABLE
;
738 gpmc_client_irq
[1].bitmask
= GPMC_IRQ_COUNT_EVENT
;
740 for (i
= 0; i
< GPMC_NR_IRQ
; i
++) {
741 gpmc_client_irq
[i
].irq
= gpmc_irq_start
+ i
;
742 irq_set_chip_and_handler(gpmc_client_irq
[i
].irq
,
743 &gpmc_irq_chip
, handle_simple_irq
);
744 set_irq_flags(gpmc_client_irq
[i
].irq
,
745 IRQF_VALID
| IRQF_NOAUTOEN
);
748 /* Disable interrupts */
749 gpmc_write_reg(GPMC_IRQENABLE
, 0);
751 /* clear interrupts */
752 regval
= gpmc_read_reg(GPMC_IRQSTATUS
);
753 gpmc_write_reg(GPMC_IRQSTATUS
, regval
);
755 return request_irq(gpmc_irq
, gpmc_handle_irq
, 0, "gpmc", NULL
);
758 static int gpmc_free_irq(void)
763 free_irq(gpmc_irq
, NULL
);
765 for (i
= 0; i
< GPMC_NR_IRQ
; i
++) {
766 irq_set_handler(gpmc_client_irq
[i
].irq
, NULL
);
767 irq_set_chip(gpmc_client_irq
[i
].irq
, &no_irq_chip
);
768 irq_modify_status(gpmc_client_irq
[i
].irq
, 0, 0);
771 irq_free_descs(gpmc_irq_start
, GPMC_NR_IRQ
);
776 static void gpmc_mem_exit(void)
780 for (cs
= 0; cs
< GPMC_CS_NUM
; cs
++) {
781 if (!gpmc_cs_mem_enabled(cs
))
783 gpmc_cs_delete_mem(cs
);
788 static void gpmc_mem_init(void)
793 * The first 1MB of GPMC address space is typically mapped to
794 * the internal ROM. Never allocate the first page, to
795 * facilitate bug detection; even if we didn't boot from ROM.
797 gpmc_mem_root
.start
= SZ_1M
;
798 gpmc_mem_root
.end
= GPMC_MEM_END
;
800 /* Reserve all regions that has been set up by bootloader */
801 for (cs
= 0; cs
< GPMC_CS_NUM
; cs
++) {
804 if (!gpmc_cs_mem_enabled(cs
))
806 gpmc_cs_get_memconf(cs
, &base
, &size
);
807 if (gpmc_cs_insert_mem(cs
, base
, size
)) {
808 pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
809 __func__
, cs
, base
, base
+ size
);
810 gpmc_cs_disable_mem(cs
);
815 static u32
gpmc_round_ps_to_sync_clk(u32 time_ps
, u32 sync_clk
)
820 div
= gpmc_calc_divider(sync_clk
);
821 temp
= gpmc_ps_to_ticks(time_ps
);
822 temp
= (temp
+ div
- 1) / div
;
823 return gpmc_ticks_to_ps(temp
* div
);
826 /* XXX: can the cycles be avoided ? */
827 static int gpmc_calc_sync_read_timings(struct gpmc_timings
*gpmc_t
,
828 struct gpmc_device_timings
*dev_t
,
834 temp
= dev_t
->t_avdp_r
;
835 /* XXX: mux check required ? */
837 /* XXX: t_avdp not to be required for sync, only added for tusb
838 * this indirectly necessitates requirement of t_avdp_r and
839 * t_avdp_w instead of having a single t_avdp
841 temp
= max_t(u32
, temp
, gpmc_t
->clk_activation
+ dev_t
->t_avdh
);
842 temp
= max_t(u32
, gpmc_t
->adv_on
+ gpmc_ticks_to_ps(1), temp
);
844 gpmc_t
->adv_rd_off
= gpmc_round_ps_to_ticks(temp
);
847 temp
= dev_t
->t_oeasu
; /* XXX: remove this ? */
849 temp
= max_t(u32
, temp
, gpmc_t
->clk_activation
+ dev_t
->t_ach
);
850 temp
= max_t(u32
, temp
, gpmc_t
->adv_rd_off
+
851 gpmc_ticks_to_ps(dev_t
->cyc_aavdh_oe
));
853 gpmc_t
->oe_on
= gpmc_round_ps_to_ticks(temp
);
856 /* XXX: any scope for improvement ?, by combining oe_on
857 * and clk_activation, need to check whether
858 * access = clk_activation + round to sync clk ?
860 temp
= max_t(u32
, dev_t
->t_iaa
, dev_t
->cyc_iaa
* gpmc_t
->sync_clk
);
861 temp
+= gpmc_t
->clk_activation
;
863 temp
= max_t(u32
, temp
, gpmc_t
->oe_on
+
864 gpmc_ticks_to_ps(dev_t
->cyc_oe
));
865 gpmc_t
->access
= gpmc_round_ps_to_ticks(temp
);
867 gpmc_t
->oe_off
= gpmc_t
->access
+ gpmc_ticks_to_ps(1);
868 gpmc_t
->cs_rd_off
= gpmc_t
->oe_off
;
871 temp
= max_t(u32
, dev_t
->t_cez_r
, dev_t
->t_oez
);
872 temp
= gpmc_round_ps_to_sync_clk(temp
, gpmc_t
->sync_clk
) +
874 /* XXX: barter t_ce_rdyz with t_cez_r ? */
875 if (dev_t
->t_ce_rdyz
)
876 temp
= max_t(u32
, temp
, gpmc_t
->cs_rd_off
+ dev_t
->t_ce_rdyz
);
877 gpmc_t
->rd_cycle
= gpmc_round_ps_to_ticks(temp
);
882 static int gpmc_calc_sync_write_timings(struct gpmc_timings
*gpmc_t
,
883 struct gpmc_device_timings
*dev_t
,
889 temp
= dev_t
->t_avdp_w
;
891 temp
= max_t(u32
, temp
,
892 gpmc_t
->clk_activation
+ dev_t
->t_avdh
);
893 temp
= max_t(u32
, gpmc_t
->adv_on
+ gpmc_ticks_to_ps(1), temp
);
895 gpmc_t
->adv_wr_off
= gpmc_round_ps_to_ticks(temp
);
897 /* wr_data_mux_bus */
898 temp
= max_t(u32
, dev_t
->t_weasu
,
899 gpmc_t
->clk_activation
+ dev_t
->t_rdyo
);
900 /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
901 * and in that case remember to handle we_on properly
904 temp
= max_t(u32
, temp
,
905 gpmc_t
->adv_wr_off
+ dev_t
->t_aavdh
);
906 temp
= max_t(u32
, temp
, gpmc_t
->adv_wr_off
+
907 gpmc_ticks_to_ps(dev_t
->cyc_aavdh_we
));
909 gpmc_t
->wr_data_mux_bus
= gpmc_round_ps_to_ticks(temp
);
912 if (gpmc_capability
& GPMC_HAS_WR_DATA_MUX_BUS
)
913 gpmc_t
->we_on
= gpmc_round_ps_to_ticks(dev_t
->t_weasu
);
915 gpmc_t
->we_on
= gpmc_t
->wr_data_mux_bus
;
918 /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
919 gpmc_t
->wr_access
= gpmc_t
->access
;
922 temp
= gpmc_t
->we_on
+ dev_t
->t_wpl
;
923 temp
= max_t(u32
, temp
,
924 gpmc_t
->wr_access
+ gpmc_ticks_to_ps(1));
925 temp
= max_t(u32
, temp
,
926 gpmc_t
->we_on
+ gpmc_ticks_to_ps(dev_t
->cyc_wpl
));
927 gpmc_t
->we_off
= gpmc_round_ps_to_ticks(temp
);
929 gpmc_t
->cs_wr_off
= gpmc_round_ps_to_ticks(gpmc_t
->we_off
+
933 temp
= gpmc_round_ps_to_sync_clk(dev_t
->t_cez_w
, gpmc_t
->sync_clk
);
934 temp
+= gpmc_t
->wr_access
;
935 /* XXX: barter t_ce_rdyz with t_cez_w ? */
936 if (dev_t
->t_ce_rdyz
)
937 temp
= max_t(u32
, temp
,
938 gpmc_t
->cs_wr_off
+ dev_t
->t_ce_rdyz
);
939 gpmc_t
->wr_cycle
= gpmc_round_ps_to_ticks(temp
);
944 static int gpmc_calc_async_read_timings(struct gpmc_timings
*gpmc_t
,
945 struct gpmc_device_timings
*dev_t
,
951 temp
= dev_t
->t_avdp_r
;
953 temp
= max_t(u32
, gpmc_t
->adv_on
+ gpmc_ticks_to_ps(1), temp
);
954 gpmc_t
->adv_rd_off
= gpmc_round_ps_to_ticks(temp
);
957 temp
= dev_t
->t_oeasu
;
959 temp
= max_t(u32
, temp
,
960 gpmc_t
->adv_rd_off
+ dev_t
->t_aavdh
);
961 gpmc_t
->oe_on
= gpmc_round_ps_to_ticks(temp
);
964 temp
= max_t(u32
, dev_t
->t_iaa
, /* XXX: remove t_iaa in async ? */
965 gpmc_t
->oe_on
+ dev_t
->t_oe
);
966 temp
= max_t(u32
, temp
,
967 gpmc_t
->cs_on
+ dev_t
->t_ce
);
968 temp
= max_t(u32
, temp
,
969 gpmc_t
->adv_on
+ dev_t
->t_aa
);
970 gpmc_t
->access
= gpmc_round_ps_to_ticks(temp
);
972 gpmc_t
->oe_off
= gpmc_t
->access
+ gpmc_ticks_to_ps(1);
973 gpmc_t
->cs_rd_off
= gpmc_t
->oe_off
;
976 temp
= max_t(u32
, dev_t
->t_rd_cycle
,
977 gpmc_t
->cs_rd_off
+ dev_t
->t_cez_r
);
978 temp
= max_t(u32
, temp
, gpmc_t
->oe_off
+ dev_t
->t_oez
);
979 gpmc_t
->rd_cycle
= gpmc_round_ps_to_ticks(temp
);
984 static int gpmc_calc_async_write_timings(struct gpmc_timings
*gpmc_t
,
985 struct gpmc_device_timings
*dev_t
,
991 temp
= dev_t
->t_avdp_w
;
993 temp
= max_t(u32
, gpmc_t
->adv_on
+ gpmc_ticks_to_ps(1), temp
);
994 gpmc_t
->adv_wr_off
= gpmc_round_ps_to_ticks(temp
);
996 /* wr_data_mux_bus */
997 temp
= dev_t
->t_weasu
;
999 temp
= max_t(u32
, temp
, gpmc_t
->adv_wr_off
+ dev_t
->t_aavdh
);
1000 temp
= max_t(u32
, temp
, gpmc_t
->adv_wr_off
+
1001 gpmc_ticks_to_ps(dev_t
->cyc_aavdh_we
));
1003 gpmc_t
->wr_data_mux_bus
= gpmc_round_ps_to_ticks(temp
);
1006 if (gpmc_capability
& GPMC_HAS_WR_DATA_MUX_BUS
)
1007 gpmc_t
->we_on
= gpmc_round_ps_to_ticks(dev_t
->t_weasu
);
1009 gpmc_t
->we_on
= gpmc_t
->wr_data_mux_bus
;
1012 temp
= gpmc_t
->we_on
+ dev_t
->t_wpl
;
1013 gpmc_t
->we_off
= gpmc_round_ps_to_ticks(temp
);
1015 gpmc_t
->cs_wr_off
= gpmc_round_ps_to_ticks(gpmc_t
->we_off
+
1019 temp
= max_t(u32
, dev_t
->t_wr_cycle
,
1020 gpmc_t
->cs_wr_off
+ dev_t
->t_cez_w
);
1021 gpmc_t
->wr_cycle
= gpmc_round_ps_to_ticks(temp
);
1026 static int gpmc_calc_sync_common_timings(struct gpmc_timings
*gpmc_t
,
1027 struct gpmc_device_timings
*dev_t
)
1031 gpmc_t
->sync_clk
= gpmc_calc_divider(dev_t
->clk
) *
1032 gpmc_get_fclk_period();
1034 gpmc_t
->page_burst_access
= gpmc_round_ps_to_sync_clk(
1038 temp
= max_t(u32
, dev_t
->t_ces
, dev_t
->t_avds
);
1039 gpmc_t
->clk_activation
= gpmc_round_ps_to_ticks(temp
);
1041 if (gpmc_calc_divider(gpmc_t
->sync_clk
) != 1)
1044 if (dev_t
->ce_xdelay
)
1045 gpmc_t
->bool_timings
.cs_extra_delay
= true;
1046 if (dev_t
->avd_xdelay
)
1047 gpmc_t
->bool_timings
.adv_extra_delay
= true;
1048 if (dev_t
->oe_xdelay
)
1049 gpmc_t
->bool_timings
.oe_extra_delay
= true;
1050 if (dev_t
->we_xdelay
)
1051 gpmc_t
->bool_timings
.we_extra_delay
= true;
1056 static int gpmc_calc_common_timings(struct gpmc_timings
*gpmc_t
,
1057 struct gpmc_device_timings
*dev_t
,
1063 gpmc_t
->cs_on
= gpmc_round_ps_to_ticks(dev_t
->t_ceasu
);
1066 temp
= dev_t
->t_avdasu
;
1067 if (dev_t
->t_ce_avd
)
1068 temp
= max_t(u32
, temp
,
1069 gpmc_t
->cs_on
+ dev_t
->t_ce_avd
);
1070 gpmc_t
->adv_on
= gpmc_round_ps_to_ticks(temp
);
1073 gpmc_calc_sync_common_timings(gpmc_t
, dev_t
);
1078 /* TODO: remove this function once all peripherals are confirmed to
1079 * work with generic timing. Simultaneously gpmc_cs_set_timings()
1080 * has to be modified to handle timings in ps instead of ns
1082 static void gpmc_convert_ps_to_ns(struct gpmc_timings
*t
)
1085 t
->cs_rd_off
/= 1000;
1086 t
->cs_wr_off
/= 1000;
1088 t
->adv_rd_off
/= 1000;
1089 t
->adv_wr_off
/= 1000;
1094 t
->page_burst_access
/= 1000;
1096 t
->rd_cycle
/= 1000;
1097 t
->wr_cycle
/= 1000;
1098 t
->bus_turnaround
/= 1000;
1099 t
->cycle2cycle_delay
/= 1000;
1100 t
->wait_monitoring
/= 1000;
1101 t
->clk_activation
/= 1000;
1102 t
->wr_access
/= 1000;
1103 t
->wr_data_mux_bus
/= 1000;
1106 int gpmc_calc_timings(struct gpmc_timings
*gpmc_t
,
1107 struct gpmc_settings
*gpmc_s
,
1108 struct gpmc_device_timings
*dev_t
)
1110 bool mux
= false, sync
= false;
1113 mux
= gpmc_s
->mux_add_data
? true : false;
1114 sync
= (gpmc_s
->sync_read
|| gpmc_s
->sync_write
);
1117 memset(gpmc_t
, 0, sizeof(*gpmc_t
));
1119 gpmc_calc_common_timings(gpmc_t
, dev_t
, sync
);
1121 if (gpmc_s
&& gpmc_s
->sync_read
)
1122 gpmc_calc_sync_read_timings(gpmc_t
, dev_t
, mux
);
1124 gpmc_calc_async_read_timings(gpmc_t
, dev_t
, mux
);
1126 if (gpmc_s
&& gpmc_s
->sync_write
)
1127 gpmc_calc_sync_write_timings(gpmc_t
, dev_t
, mux
);
1129 gpmc_calc_async_write_timings(gpmc_t
, dev_t
, mux
);
1131 /* TODO: remove, see function definition */
1132 gpmc_convert_ps_to_ns(gpmc_t
);
1138 * gpmc_cs_program_settings - programs non-timing related settings
1139 * @cs: GPMC chip-select to program
1140 * @p: pointer to GPMC settings structure
1142 * Programs non-timing related settings for a GPMC chip-select, such as
1143 * bus-width, burst configuration, etc. Function should be called once
1144 * for each chip-select that is being used and must be called before
1145 * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1146 * register will be initialised to zero by this function. Returns 0 on
1147 * success and appropriate negative error code on failure.
1149 int gpmc_cs_program_settings(int cs
, struct gpmc_settings
*p
)
1153 if ((!p
->device_width
) || (p
->device_width
> GPMC_DEVWIDTH_16BIT
)) {
1154 pr_err("%s: invalid width %d!", __func__
, p
->device_width
);
1158 /* Address-data multiplexing not supported for NAND devices */
1159 if (p
->device_nand
&& p
->mux_add_data
) {
1160 pr_err("%s: invalid configuration!\n", __func__
);
1164 if ((p
->mux_add_data
> GPMC_MUX_AD
) ||
1165 ((p
->mux_add_data
== GPMC_MUX_AAD
) &&
1166 !(gpmc_capability
& GPMC_HAS_MUX_AAD
))) {
1167 pr_err("%s: invalid multiplex configuration!\n", __func__
);
1171 /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1172 if (p
->burst_read
|| p
->burst_write
) {
1173 switch (p
->burst_len
) {
1179 pr_err("%s: invalid page/burst-length (%d)\n",
1180 __func__
, p
->burst_len
);
1185 if ((p
->wait_on_read
|| p
->wait_on_write
) &&
1186 (p
->wait_pin
> gpmc_nr_waitpins
)) {
1187 pr_err("%s: invalid wait-pin (%d)\n", __func__
, p
->wait_pin
);
1191 config1
= GPMC_CONFIG1_DEVICESIZE((p
->device_width
- 1));
1194 config1
|= GPMC_CONFIG1_READTYPE_SYNC
;
1196 config1
|= GPMC_CONFIG1_WRITETYPE_SYNC
;
1197 if (p
->wait_on_read
)
1198 config1
|= GPMC_CONFIG1_WAIT_READ_MON
;
1199 if (p
->wait_on_write
)
1200 config1
|= GPMC_CONFIG1_WAIT_WRITE_MON
;
1201 if (p
->wait_on_read
|| p
->wait_on_write
)
1202 config1
|= GPMC_CONFIG1_WAIT_PIN_SEL(p
->wait_pin
);
1204 config1
|= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND
);
1205 if (p
->mux_add_data
)
1206 config1
|= GPMC_CONFIG1_MUXTYPE(p
->mux_add_data
);
1208 config1
|= GPMC_CONFIG1_READMULTIPLE_SUPP
;
1210 config1
|= GPMC_CONFIG1_WRITEMULTIPLE_SUPP
;
1211 if (p
->burst_read
|| p
->burst_write
) {
1212 config1
|= GPMC_CONFIG1_PAGE_LEN(p
->burst_len
>> 3);
1213 config1
|= p
->burst_wrap
? GPMC_CONFIG1_WRAPBURST_SUPP
: 0;
1216 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG1
, config1
);
1222 static struct of_device_id gpmc_dt_ids
[] = {
1223 { .compatible
= "ti,omap2420-gpmc" },
1224 { .compatible
= "ti,omap2430-gpmc" },
1225 { .compatible
= "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */
1226 { .compatible
= "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */
1227 { .compatible
= "ti,am3352-gpmc" }, /* am335x devices */
1230 MODULE_DEVICE_TABLE(of
, gpmc_dt_ids
);
1233 * gpmc_read_settings_dt - read gpmc settings from device-tree
1234 * @np: pointer to device-tree node for a gpmc child device
1235 * @p: pointer to gpmc settings structure
1237 * Reads the GPMC settings for a GPMC child device from device-tree and
1238 * stores them in the GPMC settings structure passed. The GPMC settings
1239 * structure is initialised to zero by this function and so any
1240 * previously stored settings will be cleared.
1242 void gpmc_read_settings_dt(struct device_node
*np
, struct gpmc_settings
*p
)
1244 memset(p
, 0, sizeof(struct gpmc_settings
));
1246 p
->sync_read
= of_property_read_bool(np
, "gpmc,sync-read");
1247 p
->sync_write
= of_property_read_bool(np
, "gpmc,sync-write");
1248 p
->device_nand
= of_property_read_bool(np
, "gpmc,device-nand");
1249 of_property_read_u32(np
, "gpmc,device-width", &p
->device_width
);
1250 of_property_read_u32(np
, "gpmc,mux-add-data", &p
->mux_add_data
);
1252 if (!of_property_read_u32(np
, "gpmc,burst-length", &p
->burst_len
)) {
1253 p
->burst_wrap
= of_property_read_bool(np
, "gpmc,burst-wrap");
1254 p
->burst_read
= of_property_read_bool(np
, "gpmc,burst-read");
1255 p
->burst_write
= of_property_read_bool(np
, "gpmc,burst-write");
1256 if (!p
->burst_read
&& !p
->burst_write
)
1257 pr_warn("%s: page/burst-length set but not used!\n",
1261 if (!of_property_read_u32(np
, "gpmc,wait-pin", &p
->wait_pin
)) {
1262 p
->wait_on_read
= of_property_read_bool(np
,
1263 "gpmc,wait-on-read");
1264 p
->wait_on_write
= of_property_read_bool(np
,
1265 "gpmc,wait-on-write");
1266 if (!p
->wait_on_read
&& !p
->wait_on_write
)
1267 pr_warn("%s: read/write wait monitoring not enabled!\n",
1272 static void __maybe_unused
gpmc_read_timings_dt(struct device_node
*np
,
1273 struct gpmc_timings
*gpmc_t
)
1275 struct gpmc_bool_timings
*p
;
1280 memset(gpmc_t
, 0, sizeof(*gpmc_t
));
1282 /* minimum clock period for syncronous mode */
1283 of_property_read_u32(np
, "gpmc,sync-clk-ps", &gpmc_t
->sync_clk
);
1285 /* chip select timtings */
1286 of_property_read_u32(np
, "gpmc,cs-on-ns", &gpmc_t
->cs_on
);
1287 of_property_read_u32(np
, "gpmc,cs-rd-off-ns", &gpmc_t
->cs_rd_off
);
1288 of_property_read_u32(np
, "gpmc,cs-wr-off-ns", &gpmc_t
->cs_wr_off
);
1290 /* ADV signal timings */
1291 of_property_read_u32(np
, "gpmc,adv-on-ns", &gpmc_t
->adv_on
);
1292 of_property_read_u32(np
, "gpmc,adv-rd-off-ns", &gpmc_t
->adv_rd_off
);
1293 of_property_read_u32(np
, "gpmc,adv-wr-off-ns", &gpmc_t
->adv_wr_off
);
1295 /* WE signal timings */
1296 of_property_read_u32(np
, "gpmc,we-on-ns", &gpmc_t
->we_on
);
1297 of_property_read_u32(np
, "gpmc,we-off-ns", &gpmc_t
->we_off
);
1299 /* OE signal timings */
1300 of_property_read_u32(np
, "gpmc,oe-on-ns", &gpmc_t
->oe_on
);
1301 of_property_read_u32(np
, "gpmc,oe-off-ns", &gpmc_t
->oe_off
);
1303 /* access and cycle timings */
1304 of_property_read_u32(np
, "gpmc,page-burst-access-ns",
1305 &gpmc_t
->page_burst_access
);
1306 of_property_read_u32(np
, "gpmc,access-ns", &gpmc_t
->access
);
1307 of_property_read_u32(np
, "gpmc,rd-cycle-ns", &gpmc_t
->rd_cycle
);
1308 of_property_read_u32(np
, "gpmc,wr-cycle-ns", &gpmc_t
->wr_cycle
);
1309 of_property_read_u32(np
, "gpmc,bus-turnaround-ns",
1310 &gpmc_t
->bus_turnaround
);
1311 of_property_read_u32(np
, "gpmc,cycle2cycle-delay-ns",
1312 &gpmc_t
->cycle2cycle_delay
);
1313 of_property_read_u32(np
, "gpmc,wait-monitoring-ns",
1314 &gpmc_t
->wait_monitoring
);
1315 of_property_read_u32(np
, "gpmc,clk-activation-ns",
1316 &gpmc_t
->clk_activation
);
1318 /* only applicable to OMAP3+ */
1319 of_property_read_u32(np
, "gpmc,wr-access-ns", &gpmc_t
->wr_access
);
1320 of_property_read_u32(np
, "gpmc,wr-data-mux-bus-ns",
1321 &gpmc_t
->wr_data_mux_bus
);
1323 /* bool timing parameters */
1324 p
= &gpmc_t
->bool_timings
;
1326 p
->cycle2cyclediffcsen
=
1327 of_property_read_bool(np
, "gpmc,cycle2cycle-diffcsen");
1328 p
->cycle2cyclesamecsen
=
1329 of_property_read_bool(np
, "gpmc,cycle2cycle-samecsen");
1330 p
->we_extra_delay
= of_property_read_bool(np
, "gpmc,we-extra-delay");
1331 p
->oe_extra_delay
= of_property_read_bool(np
, "gpmc,oe-extra-delay");
1332 p
->adv_extra_delay
= of_property_read_bool(np
, "gpmc,adv-extra-delay");
1333 p
->cs_extra_delay
= of_property_read_bool(np
, "gpmc,cs-extra-delay");
1334 p
->time_para_granularity
=
1335 of_property_read_bool(np
, "gpmc,time-para-granularity");
1338 #ifdef CONFIG_MTD_NAND
1340 static const char * const nand_ecc_opts
[] = {
1341 [OMAP_ECC_HAMMING_CODE_DEFAULT
] = "sw",
1342 [OMAP_ECC_HAMMING_CODE_HW
] = "hw",
1343 [OMAP_ECC_HAMMING_CODE_HW_ROMCODE
] = "hw-romcode",
1344 [OMAP_ECC_BCH4_CODE_HW
] = "bch4",
1345 [OMAP_ECC_BCH8_CODE_HW
] = "bch8",
1348 static int gpmc_probe_nand_child(struct platform_device
*pdev
,
1349 struct device_node
*child
)
1353 struct gpmc_timings gpmc_t
;
1354 struct omap_nand_platform_data
*gpmc_nand_data
;
1356 if (of_property_read_u32(child
, "reg", &val
) < 0) {
1357 dev_err(&pdev
->dev
, "%s has no 'reg' property\n",
1362 gpmc_nand_data
= devm_kzalloc(&pdev
->dev
, sizeof(*gpmc_nand_data
),
1364 if (!gpmc_nand_data
)
1367 gpmc_nand_data
->cs
= val
;
1368 gpmc_nand_data
->of_node
= child
;
1370 if (!of_property_read_string(child
, "ti,nand-ecc-opt", &s
))
1371 for (val
= 0; val
< ARRAY_SIZE(nand_ecc_opts
); val
++)
1372 if (!strcasecmp(s
, nand_ecc_opts
[val
])) {
1373 gpmc_nand_data
->ecc_opt
= val
;
1377 val
= of_get_nand_bus_width(child
);
1379 gpmc_nand_data
->devsize
= NAND_BUSWIDTH_16
;
1381 gpmc_read_timings_dt(child
, &gpmc_t
);
1382 gpmc_nand_init(gpmc_nand_data
, &gpmc_t
);
1387 static int gpmc_probe_nand_child(struct platform_device
*pdev
,
1388 struct device_node
*child
)
1394 #ifdef CONFIG_MTD_ONENAND
1395 static int gpmc_probe_onenand_child(struct platform_device
*pdev
,
1396 struct device_node
*child
)
1399 struct omap_onenand_platform_data
*gpmc_onenand_data
;
1401 if (of_property_read_u32(child
, "reg", &val
) < 0) {
1402 dev_err(&pdev
->dev
, "%s has no 'reg' property\n",
1407 gpmc_onenand_data
= devm_kzalloc(&pdev
->dev
, sizeof(*gpmc_onenand_data
),
1409 if (!gpmc_onenand_data
)
1412 gpmc_onenand_data
->cs
= val
;
1413 gpmc_onenand_data
->of_node
= child
;
1414 gpmc_onenand_data
->dma_channel
= -1;
1416 if (!of_property_read_u32(child
, "dma-channel", &val
))
1417 gpmc_onenand_data
->dma_channel
= val
;
1419 gpmc_onenand_init(gpmc_onenand_data
);
1424 static int gpmc_probe_onenand_child(struct platform_device
*pdev
,
1425 struct device_node
*child
)
1432 * gpmc_probe_generic_child - configures the gpmc for a child device
1433 * @pdev: pointer to gpmc platform device
1434 * @child: pointer to device-tree node for child device
1436 * Allocates and configures a GPMC chip-select for a child device.
1437 * Returns 0 on success and appropriate negative error code on failure.
1439 static int gpmc_probe_generic_child(struct platform_device
*pdev
,
1440 struct device_node
*child
)
1442 struct gpmc_settings gpmc_s
;
1443 struct gpmc_timings gpmc_t
;
1444 struct resource res
;
1448 if (of_property_read_u32(child
, "reg", &cs
) < 0) {
1449 dev_err(&pdev
->dev
, "%s has no 'reg' property\n",
1454 if (of_address_to_resource(child
, 0, &res
) < 0) {
1455 dev_err(&pdev
->dev
, "%s has malformed 'reg' property\n",
1460 ret
= gpmc_cs_request(cs
, resource_size(&res
), &base
);
1462 dev_err(&pdev
->dev
, "cannot request GPMC CS %d\n", cs
);
1467 * FIXME: gpmc_cs_request() will map the CS to an arbitary
1468 * location in the gpmc address space. When booting with
1469 * device-tree we want the NOR flash to be mapped to the
1470 * location specified in the device-tree blob. So remap the
1471 * CS to this location. Once DT migration is complete should
1472 * just make gpmc_cs_request() map a specific address.
1474 ret
= gpmc_cs_remap(cs
, res
.start
);
1476 dev_err(&pdev
->dev
, "cannot remap GPMC CS %d to 0x%x\n",
1481 gpmc_read_settings_dt(child
, &gpmc_s
);
1483 ret
= of_property_read_u32(child
, "bank-width", &gpmc_s
.device_width
);
1487 ret
= gpmc_cs_program_settings(cs
, &gpmc_s
);
1491 gpmc_read_timings_dt(child
, &gpmc_t
);
1492 gpmc_cs_set_timings(cs
, &gpmc_t
);
1494 if (of_platform_device_create(child
, NULL
, &pdev
->dev
))
1497 dev_err(&pdev
->dev
, "failed to create gpmc child %s\n", child
->name
);
1506 static int gpmc_probe_dt(struct platform_device
*pdev
)
1509 struct device_node
*child
;
1510 const struct of_device_id
*of_id
=
1511 of_match_device(gpmc_dt_ids
, &pdev
->dev
);
1516 ret
= of_property_read_u32(pdev
->dev
.of_node
, "gpmc,num-waitpins",
1519 pr_err("%s: number of wait pins not found!\n", __func__
);
1523 for_each_node_by_name(child
, "nand") {
1524 ret
= gpmc_probe_nand_child(pdev
, child
);
1531 for_each_node_by_name(child
, "onenand") {
1532 ret
= gpmc_probe_onenand_child(pdev
, child
);
1539 for_each_node_by_name(child
, "nor") {
1540 ret
= gpmc_probe_generic_child(pdev
, child
);
1547 for_each_node_by_name(child
, "ethernet") {
1548 ret
= gpmc_probe_generic_child(pdev
, child
);
1558 static int gpmc_probe_dt(struct platform_device
*pdev
)
1564 static int gpmc_probe(struct platform_device
*pdev
)
1568 struct resource
*res
;
1570 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1574 phys_base
= res
->start
;
1575 mem_size
= resource_size(res
);
1577 gpmc_base
= devm_ioremap_resource(&pdev
->dev
, res
);
1578 if (IS_ERR(gpmc_base
))
1579 return PTR_ERR(gpmc_base
);
1581 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
1583 dev_warn(&pdev
->dev
, "Failed to get resource: irq\n");
1585 gpmc_irq
= res
->start
;
1587 gpmc_l3_clk
= clk_get(&pdev
->dev
, "fck");
1588 if (IS_ERR(gpmc_l3_clk
)) {
1589 dev_err(&pdev
->dev
, "error: clk_get\n");
1591 return PTR_ERR(gpmc_l3_clk
);
1594 clk_prepare_enable(gpmc_l3_clk
);
1596 gpmc_dev
= &pdev
->dev
;
1598 l
= gpmc_read_reg(GPMC_REVISION
);
1601 * FIXME: Once device-tree migration is complete the below flags
1602 * should be populated based upon the device-tree compatible
1603 * string. For now just use the IP revision. OMAP3+ devices have
1604 * the wr_access and wr_data_mux_bus register fields. OMAP4+
1605 * devices support the addr-addr-data multiplex protocol.
1607 * GPMC IP revisions:
1610 * - OMAP44xx/54xx/AM335x = 6.0
1612 if (GPMC_REVISION_MAJOR(l
) > 0x4)
1613 gpmc_capability
= GPMC_HAS_WR_ACCESS
| GPMC_HAS_WR_DATA_MUX_BUS
;
1614 if (GPMC_REVISION_MAJOR(l
) > 0x5)
1615 gpmc_capability
|= GPMC_HAS_MUX_AAD
;
1616 dev_info(gpmc_dev
, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l
),
1617 GPMC_REVISION_MINOR(l
));
1621 if (gpmc_setup_irq() < 0)
1622 dev_warn(gpmc_dev
, "gpmc_setup_irq failed\n");
1624 /* Now the GPMC is initialised, unreserve the chip-selects */
1627 if (!pdev
->dev
.of_node
)
1628 gpmc_nr_waitpins
= GPMC_NR_WAITPINS
;
1630 rc
= gpmc_probe_dt(pdev
);
1632 clk_disable_unprepare(gpmc_l3_clk
);
1633 clk_put(gpmc_l3_clk
);
1634 dev_err(gpmc_dev
, "failed to probe DT parameters\n");
1641 static int gpmc_remove(struct platform_device
*pdev
)
1649 static struct platform_driver gpmc_driver
= {
1650 .probe
= gpmc_probe
,
1651 .remove
= gpmc_remove
,
1653 .name
= DEVICE_NAME
,
1654 .owner
= THIS_MODULE
,
1655 .of_match_table
= of_match_ptr(gpmc_dt_ids
),
1659 static __init
int gpmc_init(void)
1661 return platform_driver_register(&gpmc_driver
);
1664 static __exit
void gpmc_exit(void)
1666 platform_driver_unregister(&gpmc_driver
);
1670 omap_postcore_initcall(gpmc_init
);
1671 module_exit(gpmc_exit
);
1673 static int __init
omap_gpmc_init(void)
1675 struct omap_hwmod
*oh
;
1676 struct platform_device
*pdev
;
1677 char *oh_name
= "gpmc";
1680 * if the board boots up with a populated DT, do not
1681 * manually add the device from this initcall
1683 if (of_have_populated_dt())
1686 oh
= omap_hwmod_lookup(oh_name
);
1688 pr_err("Could not look up %s\n", oh_name
);
1692 pdev
= omap_device_build(DEVICE_NAME
, -1, oh
, NULL
, 0);
1693 WARN(IS_ERR(pdev
), "could not build omap_device for %s\n", oh_name
);
1695 return IS_ERR(pdev
) ? PTR_ERR(pdev
) : 0;
1697 omap_postcore_initcall(omap_gpmc_init
);
1699 static irqreturn_t
gpmc_handle_irq(int irq
, void *dev
)
1704 regval
= gpmc_read_reg(GPMC_IRQSTATUS
);
1709 for (i
= 0; i
< GPMC_NR_IRQ
; i
++)
1710 if (regval
& gpmc_client_irq
[i
].bitmask
)
1711 generic_handle_irq(gpmc_client_irq
[i
].irq
);
1713 gpmc_write_reg(GPMC_IRQSTATUS
, regval
);
1718 #ifdef CONFIG_ARCH_OMAP3
1719 static struct omap3_gpmc_regs gpmc_context
;
1721 void omap3_gpmc_save_context(void)
1725 gpmc_context
.sysconfig
= gpmc_read_reg(GPMC_SYSCONFIG
);
1726 gpmc_context
.irqenable
= gpmc_read_reg(GPMC_IRQENABLE
);
1727 gpmc_context
.timeout_ctrl
= gpmc_read_reg(GPMC_TIMEOUT_CONTROL
);
1728 gpmc_context
.config
= gpmc_read_reg(GPMC_CONFIG
);
1729 gpmc_context
.prefetch_config1
= gpmc_read_reg(GPMC_PREFETCH_CONFIG1
);
1730 gpmc_context
.prefetch_config2
= gpmc_read_reg(GPMC_PREFETCH_CONFIG2
);
1731 gpmc_context
.prefetch_control
= gpmc_read_reg(GPMC_PREFETCH_CONTROL
);
1732 for (i
= 0; i
< GPMC_CS_NUM
; i
++) {
1733 gpmc_context
.cs_context
[i
].is_valid
= gpmc_cs_mem_enabled(i
);
1734 if (gpmc_context
.cs_context
[i
].is_valid
) {
1735 gpmc_context
.cs_context
[i
].config1
=
1736 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG1
);
1737 gpmc_context
.cs_context
[i
].config2
=
1738 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG2
);
1739 gpmc_context
.cs_context
[i
].config3
=
1740 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG3
);
1741 gpmc_context
.cs_context
[i
].config4
=
1742 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG4
);
1743 gpmc_context
.cs_context
[i
].config5
=
1744 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG5
);
1745 gpmc_context
.cs_context
[i
].config6
=
1746 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG6
);
1747 gpmc_context
.cs_context
[i
].config7
=
1748 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG7
);
1753 void omap3_gpmc_restore_context(void)
1757 gpmc_write_reg(GPMC_SYSCONFIG
, gpmc_context
.sysconfig
);
1758 gpmc_write_reg(GPMC_IRQENABLE
, gpmc_context
.irqenable
);
1759 gpmc_write_reg(GPMC_TIMEOUT_CONTROL
, gpmc_context
.timeout_ctrl
);
1760 gpmc_write_reg(GPMC_CONFIG
, gpmc_context
.config
);
1761 gpmc_write_reg(GPMC_PREFETCH_CONFIG1
, gpmc_context
.prefetch_config1
);
1762 gpmc_write_reg(GPMC_PREFETCH_CONFIG2
, gpmc_context
.prefetch_config2
);
1763 gpmc_write_reg(GPMC_PREFETCH_CONTROL
, gpmc_context
.prefetch_control
);
1764 for (i
= 0; i
< GPMC_CS_NUM
; i
++) {
1765 if (gpmc_context
.cs_context
[i
].is_valid
) {
1766 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG1
,
1767 gpmc_context
.cs_context
[i
].config1
);
1768 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG2
,
1769 gpmc_context
.cs_context
[i
].config2
);
1770 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG3
,
1771 gpmc_context
.cs_context
[i
].config3
);
1772 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG4
,
1773 gpmc_context
.cs_context
[i
].config4
);
1774 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG5
,
1775 gpmc_context
.cs_context
[i
].config5
);
1776 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG6
,
1777 gpmc_context
.cs_context
[i
].config6
);
1778 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG7
,
1779 gpmc_context
.cs_context
[i
].config7
);
1783 #endif /* CONFIG_ARCH_OMAP3 */