2 * GPMC support functions
4 * Copyright (C) 2005-2006 Nokia Corporation
8 * Copyright (C) 2009 Texas Instruments
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/irq.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
22 #include <linux/ioport.h>
23 #include <linux/spinlock.h>
25 #include <linux/module.h>
26 #include <linux/interrupt.h>
27 #include <linux/platform_device.h>
29 #include <asm/mach-types.h>
30 #include <plat/gpmc.h>
33 #include <plat/gpmc.h>
34 #include <plat/sdrc.h>
35 #include <plat/omap_device.h>
40 #define DEVICE_NAME "omap-gpmc"
42 /* GPMC register offsets */
43 #define GPMC_REVISION 0x00
44 #define GPMC_SYSCONFIG 0x10
45 #define GPMC_SYSSTATUS 0x14
46 #define GPMC_IRQSTATUS 0x18
47 #define GPMC_IRQENABLE 0x1c
48 #define GPMC_TIMEOUT_CONTROL 0x40
49 #define GPMC_ERR_ADDRESS 0x44
50 #define GPMC_ERR_TYPE 0x48
51 #define GPMC_CONFIG 0x50
52 #define GPMC_STATUS 0x54
53 #define GPMC_PREFETCH_CONFIG1 0x1e0
54 #define GPMC_PREFETCH_CONFIG2 0x1e4
55 #define GPMC_PREFETCH_CONTROL 0x1ec
56 #define GPMC_PREFETCH_STATUS 0x1f0
57 #define GPMC_ECC_CONFIG 0x1f4
58 #define GPMC_ECC_CONTROL 0x1f8
59 #define GPMC_ECC_SIZE_CONFIG 0x1fc
60 #define GPMC_ECC1_RESULT 0x200
61 #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
63 /* GPMC ECC control settings */
64 #define GPMC_ECC_CTRL_ECCCLEAR 0x100
65 #define GPMC_ECC_CTRL_ECCDISABLE 0x000
66 #define GPMC_ECC_CTRL_ECCREG1 0x001
67 #define GPMC_ECC_CTRL_ECCREG2 0x002
68 #define GPMC_ECC_CTRL_ECCREG3 0x003
69 #define GPMC_ECC_CTRL_ECCREG4 0x004
70 #define GPMC_ECC_CTRL_ECCREG5 0x005
71 #define GPMC_ECC_CTRL_ECCREG6 0x006
72 #define GPMC_ECC_CTRL_ECCREG7 0x007
73 #define GPMC_ECC_CTRL_ECCREG8 0x008
74 #define GPMC_ECC_CTRL_ECCREG9 0x009
76 #define GPMC_CS0_OFFSET 0x60
77 #define GPMC_CS_SIZE 0x30
79 #define GPMC_MEM_START 0x00000000
80 #define GPMC_MEM_END 0x3FFFFFFF
81 #define BOOT_ROM_SPACE 0x100000 /* 1MB */
83 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
84 #define GPMC_SECTION_SHIFT 28 /* 128 MB */
86 #define CS_NUM_SHIFT 24
87 #define ENABLE_PREFETCH (0x1 << 7)
88 #define DMA_MPU_MODE 2
90 #define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf)
91 #define GPMC_REVISION_MINOR(l) (l & 0xf)
93 #define GPMC_HAS_WR_ACCESS 0x1
94 #define GPMC_HAS_WR_DATA_MUX_BUS 0x2
96 /* XXX: Only NAND irq has been considered,currently these are the only ones used
100 struct gpmc_client_irq
{
105 /* Structure to save gpmc cs context */
106 struct gpmc_cs_config
{
118 * Structure to save/restore gpmc context
119 * to support core off on OMAP3
121 struct omap3_gpmc_regs
{
126 u32 prefetch_config1
;
127 u32 prefetch_config2
;
128 u32 prefetch_control
;
129 struct gpmc_cs_config cs_context
[GPMC_CS_NUM
];
132 static struct gpmc_client_irq gpmc_client_irq
[GPMC_NR_IRQ
];
133 static struct irq_chip gpmc_irq_chip
;
134 static unsigned gpmc_irq_start
;
136 static struct resource gpmc_mem_root
;
137 static struct resource gpmc_cs_mem
[GPMC_CS_NUM
];
138 static DEFINE_SPINLOCK(gpmc_mem_lock
);
139 static unsigned int gpmc_cs_map
; /* flag for cs which are initialized */
140 static int gpmc_ecc_used
= -EINVAL
; /* cs using ecc engine */
141 static struct device
*gpmc_dev
;
143 static resource_size_t phys_base
, mem_size
;
144 static unsigned gpmc_capability
;
145 static void __iomem
*gpmc_base
;
147 static struct clk
*gpmc_l3_clk
;
149 static irqreturn_t
gpmc_handle_irq(int irq
, void *dev
);
151 static void gpmc_write_reg(int idx
, u32 val
)
153 __raw_writel(val
, gpmc_base
+ idx
);
156 static u32
gpmc_read_reg(int idx
)
158 return __raw_readl(gpmc_base
+ idx
);
161 static void gpmc_cs_write_byte(int cs
, int idx
, u8 val
)
163 void __iomem
*reg_addr
;
165 reg_addr
= gpmc_base
+ GPMC_CS0_OFFSET
+ (cs
* GPMC_CS_SIZE
) + idx
;
166 __raw_writeb(val
, reg_addr
);
169 static u8
gpmc_cs_read_byte(int cs
, int idx
)
171 void __iomem
*reg_addr
;
173 reg_addr
= gpmc_base
+ GPMC_CS0_OFFSET
+ (cs
* GPMC_CS_SIZE
) + idx
;
174 return __raw_readb(reg_addr
);
177 void gpmc_cs_write_reg(int cs
, int idx
, u32 val
)
179 void __iomem
*reg_addr
;
181 reg_addr
= gpmc_base
+ GPMC_CS0_OFFSET
+ (cs
* GPMC_CS_SIZE
) + idx
;
182 __raw_writel(val
, reg_addr
);
185 u32
gpmc_cs_read_reg(int cs
, int idx
)
187 void __iomem
*reg_addr
;
189 reg_addr
= gpmc_base
+ GPMC_CS0_OFFSET
+ (cs
* GPMC_CS_SIZE
) + idx
;
190 return __raw_readl(reg_addr
);
193 /* TODO: Add support for gpmc_fck to clock framework and use it */
194 unsigned long gpmc_get_fclk_period(void)
196 unsigned long rate
= clk_get_rate(gpmc_l3_clk
);
199 printk(KERN_WARNING
"gpmc_l3_clk not enabled\n");
204 rate
= 1000000000 / rate
; /* In picoseconds */
209 unsigned int gpmc_ns_to_ticks(unsigned int time_ns
)
211 unsigned long tick_ps
;
213 /* Calculate in picosecs to yield more exact results */
214 tick_ps
= gpmc_get_fclk_period();
216 return (time_ns
* 1000 + tick_ps
- 1) / tick_ps
;
219 unsigned int gpmc_ps_to_ticks(unsigned int time_ps
)
221 unsigned long tick_ps
;
223 /* Calculate in picosecs to yield more exact results */
224 tick_ps
= gpmc_get_fclk_period();
226 return (time_ps
+ tick_ps
- 1) / tick_ps
;
229 unsigned int gpmc_ticks_to_ns(unsigned int ticks
)
231 return ticks
* gpmc_get_fclk_period() / 1000;
234 unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns
)
236 unsigned long ticks
= gpmc_ns_to_ticks(time_ns
);
238 return ticks
* gpmc_get_fclk_period() / 1000;
242 static int set_gpmc_timing_reg(int cs
, int reg
, int st_bit
, int end_bit
,
243 int time
, const char *name
)
245 static int set_gpmc_timing_reg(int cs
, int reg
, int st_bit
, int end_bit
,
250 int ticks
, mask
, nr_bits
;
255 ticks
= gpmc_ns_to_ticks(time
);
256 nr_bits
= end_bit
- st_bit
+ 1;
257 if (ticks
>= 1 << nr_bits
) {
259 printk(KERN_INFO
"GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
260 cs
, name
, time
, ticks
, 1 << nr_bits
);
265 mask
= (1 << nr_bits
) - 1;
266 l
= gpmc_cs_read_reg(cs
, reg
);
269 "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
270 cs
, name
, ticks
, gpmc_get_fclk_period() * ticks
/ 1000,
271 (l
>> st_bit
) & mask
, time
);
273 l
&= ~(mask
<< st_bit
);
274 l
|= ticks
<< st_bit
;
275 gpmc_cs_write_reg(cs
, reg
, l
);
281 #define GPMC_SET_ONE(reg, st, end, field) \
282 if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
283 t->field, #field) < 0) \
286 #define GPMC_SET_ONE(reg, st, end, field) \
287 if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
291 int gpmc_cs_calc_divider(int cs
, unsigned int sync_clk
)
296 l
= sync_clk
+ (gpmc_get_fclk_period() - 1);
297 div
= l
/ gpmc_get_fclk_period();
306 int gpmc_cs_set_timings(int cs
, const struct gpmc_timings
*t
)
311 div
= gpmc_cs_calc_divider(cs
, t
->sync_clk
);
315 GPMC_SET_ONE(GPMC_CS_CONFIG2
, 0, 3, cs_on
);
316 GPMC_SET_ONE(GPMC_CS_CONFIG2
, 8, 12, cs_rd_off
);
317 GPMC_SET_ONE(GPMC_CS_CONFIG2
, 16, 20, cs_wr_off
);
319 GPMC_SET_ONE(GPMC_CS_CONFIG3
, 0, 3, adv_on
);
320 GPMC_SET_ONE(GPMC_CS_CONFIG3
, 8, 12, adv_rd_off
);
321 GPMC_SET_ONE(GPMC_CS_CONFIG3
, 16, 20, adv_wr_off
);
323 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 0, 3, oe_on
);
324 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 8, 12, oe_off
);
325 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 16, 19, we_on
);
326 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 24, 28, we_off
);
328 GPMC_SET_ONE(GPMC_CS_CONFIG5
, 0, 4, rd_cycle
);
329 GPMC_SET_ONE(GPMC_CS_CONFIG5
, 8, 12, wr_cycle
);
330 GPMC_SET_ONE(GPMC_CS_CONFIG5
, 16, 20, access
);
332 GPMC_SET_ONE(GPMC_CS_CONFIG5
, 24, 27, page_burst_access
);
334 if (gpmc_capability
& GPMC_HAS_WR_DATA_MUX_BUS
)
335 GPMC_SET_ONE(GPMC_CS_CONFIG6
, 16, 19, wr_data_mux_bus
);
336 if (gpmc_capability
& GPMC_HAS_WR_ACCESS
)
337 GPMC_SET_ONE(GPMC_CS_CONFIG6
, 24, 28, wr_access
);
339 /* caller is expected to have initialized CONFIG1 to cover
340 * at least sync vs async
342 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG1
);
343 if (l
& (GPMC_CONFIG1_READTYPE_SYNC
| GPMC_CONFIG1_WRITETYPE_SYNC
)) {
345 printk(KERN_INFO
"GPMC CS%d CLK period is %lu ns (div %d)\n",
346 cs
, (div
* gpmc_get_fclk_period()) / 1000, div
);
350 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG1
, l
);
356 static void gpmc_cs_enable_mem(int cs
, u32 base
, u32 size
)
361 mask
= (1 << GPMC_SECTION_SHIFT
) - size
;
362 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
364 l
= (base
>> GPMC_CHUNK_SHIFT
) & 0x3f;
366 l
|= ((mask
>> GPMC_CHUNK_SHIFT
) & 0x0f) << 8;
367 l
|= GPMC_CONFIG7_CSVALID
;
368 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG7
, l
);
371 static void gpmc_cs_disable_mem(int cs
)
375 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
376 l
&= ~GPMC_CONFIG7_CSVALID
;
377 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG7
, l
);
380 static void gpmc_cs_get_memconf(int cs
, u32
*base
, u32
*size
)
385 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
386 *base
= (l
& 0x3f) << GPMC_CHUNK_SHIFT
;
387 mask
= (l
>> 8) & 0x0f;
388 *size
= (1 << GPMC_SECTION_SHIFT
) - (mask
<< GPMC_CHUNK_SHIFT
);
391 static int gpmc_cs_mem_enabled(int cs
)
395 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
396 return l
& GPMC_CONFIG7_CSVALID
;
399 int gpmc_cs_set_reserved(int cs
, int reserved
)
401 if (cs
> GPMC_CS_NUM
)
404 gpmc_cs_map
&= ~(1 << cs
);
405 gpmc_cs_map
|= (reserved
? 1 : 0) << cs
;
410 int gpmc_cs_reserved(int cs
)
412 if (cs
> GPMC_CS_NUM
)
415 return gpmc_cs_map
& (1 << cs
);
418 static unsigned long gpmc_mem_align(unsigned long size
)
422 size
= (size
- 1) >> (GPMC_CHUNK_SHIFT
- 1);
423 order
= GPMC_CHUNK_SHIFT
- 1;
432 static int gpmc_cs_insert_mem(int cs
, unsigned long base
, unsigned long size
)
434 struct resource
*res
= &gpmc_cs_mem
[cs
];
437 size
= gpmc_mem_align(size
);
438 spin_lock(&gpmc_mem_lock
);
440 res
->end
= base
+ size
- 1;
441 r
= request_resource(&gpmc_mem_root
, res
);
442 spin_unlock(&gpmc_mem_lock
);
447 static int gpmc_cs_delete_mem(int cs
)
449 struct resource
*res
= &gpmc_cs_mem
[cs
];
452 spin_lock(&gpmc_mem_lock
);
453 r
= release_resource(&gpmc_cs_mem
[cs
]);
456 spin_unlock(&gpmc_mem_lock
);
461 int gpmc_cs_request(int cs
, unsigned long size
, unsigned long *base
)
463 struct resource
*res
= &gpmc_cs_mem
[cs
];
466 if (cs
> GPMC_CS_NUM
)
469 size
= gpmc_mem_align(size
);
470 if (size
> (1 << GPMC_SECTION_SHIFT
))
473 spin_lock(&gpmc_mem_lock
);
474 if (gpmc_cs_reserved(cs
)) {
478 if (gpmc_cs_mem_enabled(cs
))
479 r
= adjust_resource(res
, res
->start
& ~(size
- 1), size
);
481 r
= allocate_resource(&gpmc_mem_root
, res
, size
, 0, ~0,
486 gpmc_cs_enable_mem(cs
, res
->start
, resource_size(res
));
488 gpmc_cs_set_reserved(cs
, 1);
490 spin_unlock(&gpmc_mem_lock
);
493 EXPORT_SYMBOL(gpmc_cs_request
);
495 void gpmc_cs_free(int cs
)
497 spin_lock(&gpmc_mem_lock
);
498 if (cs
>= GPMC_CS_NUM
|| cs
< 0 || !gpmc_cs_reserved(cs
)) {
499 printk(KERN_ERR
"Trying to free non-reserved GPMC CS%d\n", cs
);
501 spin_unlock(&gpmc_mem_lock
);
504 gpmc_cs_disable_mem(cs
);
505 release_resource(&gpmc_cs_mem
[cs
]);
506 gpmc_cs_set_reserved(cs
, 0);
507 spin_unlock(&gpmc_mem_lock
);
509 EXPORT_SYMBOL(gpmc_cs_free
);
512 * gpmc_read_status - read access request to get the different gpmc status
516 int gpmc_read_status(int cmd
)
518 int status
= -EINVAL
;
522 case GPMC_GET_IRQ_STATUS
:
523 status
= gpmc_read_reg(GPMC_IRQSTATUS
);
526 case GPMC_PREFETCH_FIFO_CNT
:
527 regval
= gpmc_read_reg(GPMC_PREFETCH_STATUS
);
528 status
= GPMC_PREFETCH_STATUS_FIFO_CNT(regval
);
531 case GPMC_PREFETCH_COUNT
:
532 regval
= gpmc_read_reg(GPMC_PREFETCH_STATUS
);
533 status
= GPMC_PREFETCH_STATUS_COUNT(regval
);
536 case GPMC_STATUS_BUFFER
:
537 regval
= gpmc_read_reg(GPMC_STATUS
);
538 /* 1 : buffer is available to write */
539 status
= regval
& GPMC_STATUS_BUFF_EMPTY
;
543 printk(KERN_ERR
"gpmc_read_status: Not supported\n");
547 EXPORT_SYMBOL(gpmc_read_status
);
550 * gpmc_cs_configure - write request to configure gpmc
551 * @cs: chip select number
553 * @wval: value to write
554 * @return status of the operation
556 int gpmc_cs_configure(int cs
, int cmd
, int wval
)
562 case GPMC_ENABLE_IRQ
:
563 gpmc_write_reg(GPMC_IRQENABLE
, wval
);
566 case GPMC_SET_IRQ_STATUS
:
567 gpmc_write_reg(GPMC_IRQSTATUS
, wval
);
571 regval
= gpmc_read_reg(GPMC_CONFIG
);
573 regval
&= ~GPMC_CONFIG_WRITEPROTECT
; /* WP is ON */
575 regval
|= GPMC_CONFIG_WRITEPROTECT
; /* WP is OFF */
576 gpmc_write_reg(GPMC_CONFIG
, regval
);
579 case GPMC_CONFIG_RDY_BSY
:
580 regval
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG1
);
582 regval
|= WR_RD_PIN_MONITORING
;
584 regval
&= ~WR_RD_PIN_MONITORING
;
585 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG1
, regval
);
588 case GPMC_CONFIG_DEV_SIZE
:
589 regval
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG1
);
591 /* clear 2 target bits */
592 regval
&= ~GPMC_CONFIG1_DEVICESIZE(3);
594 /* set the proper value */
595 regval
|= GPMC_CONFIG1_DEVICESIZE(wval
);
597 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG1
, regval
);
600 case GPMC_CONFIG_DEV_TYPE
:
601 regval
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG1
);
602 regval
|= GPMC_CONFIG1_DEVICETYPE(wval
);
603 if (wval
== GPMC_DEVICETYPE_NOR
)
604 regval
|= GPMC_CONFIG1_MUXADDDATA
;
605 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG1
, regval
);
609 printk(KERN_ERR
"gpmc_configure_cs: Not supported\n");
615 EXPORT_SYMBOL(gpmc_cs_configure
);
618 * gpmc_nand_read - nand specific read access request
619 * @cs: chip select number
622 int gpmc_nand_read(int cs
, int cmd
)
628 rval
= gpmc_cs_read_byte(cs
, GPMC_CS_NAND_DATA
);
632 printk(KERN_ERR
"gpmc_read_nand_ctrl: Not supported\n");
636 EXPORT_SYMBOL(gpmc_nand_read
);
639 * gpmc_nand_write - nand specific write request
640 * @cs: chip select number
642 * @wval: value to write
644 int gpmc_nand_write(int cs
, int cmd
, int wval
)
649 case GPMC_NAND_COMMAND
:
650 gpmc_cs_write_byte(cs
, GPMC_CS_NAND_COMMAND
, wval
);
653 case GPMC_NAND_ADDRESS
:
654 gpmc_cs_write_byte(cs
, GPMC_CS_NAND_ADDRESS
, wval
);
658 gpmc_cs_write_byte(cs
, GPMC_CS_NAND_DATA
, wval
);
661 printk(KERN_ERR
"gpmc_write_nand_ctrl: Not supported\n");
666 EXPORT_SYMBOL(gpmc_nand_write
);
671 * gpmc_prefetch_enable - configures and starts prefetch transfer
672 * @cs: cs (chip select) number
673 * @fifo_th: fifo threshold to be used for read/ write
674 * @dma_mode: dma mode enable (1) or disable (0)
675 * @u32_count: number of bytes to be transferred
676 * @is_write: prefetch read(0) or write post(1) mode
678 int gpmc_prefetch_enable(int cs
, int fifo_th
, int dma_mode
,
679 unsigned int u32_count
, int is_write
)
682 if (fifo_th
> PREFETCH_FIFOTHRESHOLD_MAX
) {
683 pr_err("gpmc: fifo threshold is not supported\n");
685 } else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL
))) {
686 /* Set the amount of bytes to be prefetched */
687 gpmc_write_reg(GPMC_PREFETCH_CONFIG2
, u32_count
);
689 /* Set dma/mpu mode, the prefetch read / post write and
690 * enable the engine. Set which cs is has requested for.
692 gpmc_write_reg(GPMC_PREFETCH_CONFIG1
, ((cs
<< CS_NUM_SHIFT
) |
693 PREFETCH_FIFOTHRESHOLD(fifo_th
) |
695 (dma_mode
<< DMA_MPU_MODE
) |
698 /* Start the prefetch engine */
699 gpmc_write_reg(GPMC_PREFETCH_CONTROL
, 0x1);
706 EXPORT_SYMBOL(gpmc_prefetch_enable
);
709 * gpmc_prefetch_reset - disables and stops the prefetch engine
711 int gpmc_prefetch_reset(int cs
)
715 /* check if the same module/cs is trying to reset */
716 config1
= gpmc_read_reg(GPMC_PREFETCH_CONFIG1
);
717 if (((config1
>> CS_NUM_SHIFT
) & 0x7) != cs
)
720 /* Stop the PFPW engine */
721 gpmc_write_reg(GPMC_PREFETCH_CONTROL
, 0x0);
723 /* Reset/disable the PFPW engine */
724 gpmc_write_reg(GPMC_PREFETCH_CONFIG1
, 0x0);
728 EXPORT_SYMBOL(gpmc_prefetch_reset
);
730 void gpmc_update_nand_reg(struct gpmc_nand_regs
*reg
, int cs
)
732 reg
->gpmc_status
= gpmc_base
+ GPMC_STATUS
;
733 reg
->gpmc_nand_command
= gpmc_base
+ GPMC_CS0_OFFSET
+
734 GPMC_CS_NAND_COMMAND
+ GPMC_CS_SIZE
* cs
;
735 reg
->gpmc_nand_address
= gpmc_base
+ GPMC_CS0_OFFSET
+
736 GPMC_CS_NAND_ADDRESS
+ GPMC_CS_SIZE
* cs
;
737 reg
->gpmc_nand_data
= gpmc_base
+ GPMC_CS0_OFFSET
+
738 GPMC_CS_NAND_DATA
+ GPMC_CS_SIZE
* cs
;
739 reg
->gpmc_prefetch_config1
= gpmc_base
+ GPMC_PREFETCH_CONFIG1
;
740 reg
->gpmc_prefetch_config2
= gpmc_base
+ GPMC_PREFETCH_CONFIG2
;
741 reg
->gpmc_prefetch_control
= gpmc_base
+ GPMC_PREFETCH_CONTROL
;
742 reg
->gpmc_prefetch_status
= gpmc_base
+ GPMC_PREFETCH_STATUS
;
743 reg
->gpmc_ecc_config
= gpmc_base
+ GPMC_ECC_CONFIG
;
744 reg
->gpmc_ecc_control
= gpmc_base
+ GPMC_ECC_CONTROL
;
745 reg
->gpmc_ecc_size_config
= gpmc_base
+ GPMC_ECC_SIZE_CONFIG
;
746 reg
->gpmc_ecc1_result
= gpmc_base
+ GPMC_ECC1_RESULT
;
747 reg
->gpmc_bch_result0
= gpmc_base
+ GPMC_ECC_BCH_RESULT_0
;
750 int gpmc_get_client_irq(unsigned irq_config
)
754 if (hweight32(irq_config
) > 1)
757 for (i
= 0; i
< GPMC_NR_IRQ
; i
++)
758 if (gpmc_client_irq
[i
].bitmask
& irq_config
)
759 return gpmc_client_irq
[i
].irq
;
764 static int gpmc_irq_endis(unsigned irq
, bool endis
)
769 for (i
= 0; i
< GPMC_NR_IRQ
; i
++)
770 if (irq
== gpmc_client_irq
[i
].irq
) {
771 regval
= gpmc_read_reg(GPMC_IRQENABLE
);
773 regval
|= gpmc_client_irq
[i
].bitmask
;
775 regval
&= ~gpmc_client_irq
[i
].bitmask
;
776 gpmc_write_reg(GPMC_IRQENABLE
, regval
);
783 static void gpmc_irq_disable(struct irq_data
*p
)
785 gpmc_irq_endis(p
->irq
, false);
788 static void gpmc_irq_enable(struct irq_data
*p
)
790 gpmc_irq_endis(p
->irq
, true);
793 static void gpmc_irq_noop(struct irq_data
*data
) { }
795 static unsigned int gpmc_irq_noop_ret(struct irq_data
*data
) { return 0; }
797 static int gpmc_setup_irq(void)
805 gpmc_irq_start
= irq_alloc_descs(-1, 0, GPMC_NR_IRQ
, 0);
806 if (IS_ERR_VALUE(gpmc_irq_start
)) {
807 pr_err("irq_alloc_descs failed\n");
808 return gpmc_irq_start
;
811 gpmc_irq_chip
.name
= "gpmc";
812 gpmc_irq_chip
.irq_startup
= gpmc_irq_noop_ret
;
813 gpmc_irq_chip
.irq_enable
= gpmc_irq_enable
;
814 gpmc_irq_chip
.irq_disable
= gpmc_irq_disable
;
815 gpmc_irq_chip
.irq_shutdown
= gpmc_irq_noop
;
816 gpmc_irq_chip
.irq_ack
= gpmc_irq_noop
;
817 gpmc_irq_chip
.irq_mask
= gpmc_irq_noop
;
818 gpmc_irq_chip
.irq_unmask
= gpmc_irq_noop
;
820 gpmc_client_irq
[0].bitmask
= GPMC_IRQ_FIFOEVENTENABLE
;
821 gpmc_client_irq
[1].bitmask
= GPMC_IRQ_COUNT_EVENT
;
823 for (i
= 0; i
< GPMC_NR_IRQ
; i
++) {
824 gpmc_client_irq
[i
].irq
= gpmc_irq_start
+ i
;
825 irq_set_chip_and_handler(gpmc_client_irq
[i
].irq
,
826 &gpmc_irq_chip
, handle_simple_irq
);
827 set_irq_flags(gpmc_client_irq
[i
].irq
,
828 IRQF_VALID
| IRQF_NOAUTOEN
);
831 /* Disable interrupts */
832 gpmc_write_reg(GPMC_IRQENABLE
, 0);
834 /* clear interrupts */
835 regval
= gpmc_read_reg(GPMC_IRQSTATUS
);
836 gpmc_write_reg(GPMC_IRQSTATUS
, regval
);
838 return request_irq(gpmc_irq
, gpmc_handle_irq
, 0, "gpmc", NULL
);
841 static __devexit
int gpmc_free_irq(void)
846 free_irq(gpmc_irq
, NULL
);
848 for (i
= 0; i
< GPMC_NR_IRQ
; i
++) {
849 irq_set_handler(gpmc_client_irq
[i
].irq
, NULL
);
850 irq_set_chip(gpmc_client_irq
[i
].irq
, &no_irq_chip
);
851 irq_modify_status(gpmc_client_irq
[i
].irq
, 0, 0);
854 irq_free_descs(gpmc_irq_start
, GPMC_NR_IRQ
);
859 static void __devexit
gpmc_mem_exit(void)
863 for (cs
= 0; cs
< GPMC_CS_NUM
; cs
++) {
864 if (!gpmc_cs_mem_enabled(cs
))
866 gpmc_cs_delete_mem(cs
);
871 static void __devinit
gpmc_mem_init(void)
874 unsigned long boot_rom_space
= 0;
876 /* never allocate the first page, to facilitate bug detection;
877 * even if we didn't boot from ROM.
879 boot_rom_space
= BOOT_ROM_SPACE
;
880 /* In apollon the CS0 is mapped as 0x0000 0000 */
881 if (machine_is_omap_apollon())
883 gpmc_mem_root
.start
= GPMC_MEM_START
+ boot_rom_space
;
884 gpmc_mem_root
.end
= GPMC_MEM_END
;
886 /* Reserve all regions that has been set up by bootloader */
887 for (cs
= 0; cs
< GPMC_CS_NUM
; cs
++) {
890 if (!gpmc_cs_mem_enabled(cs
))
892 gpmc_cs_get_memconf(cs
, &base
, &size
);
893 if (gpmc_cs_insert_mem(cs
, base
, size
) < 0)
898 static __devinit
int gpmc_probe(struct platform_device
*pdev
)
901 struct resource
*res
;
903 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
907 phys_base
= res
->start
;
908 mem_size
= resource_size(res
);
910 gpmc_base
= devm_request_and_ioremap(&pdev
->dev
, res
);
912 dev_err(&pdev
->dev
, "error: request memory / ioremap\n");
913 return -EADDRNOTAVAIL
;
916 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
918 dev_warn(&pdev
->dev
, "Failed to get resource: irq\n");
920 gpmc_irq
= res
->start
;
922 gpmc_l3_clk
= clk_get(&pdev
->dev
, "fck");
923 if (IS_ERR(gpmc_l3_clk
)) {
924 dev_err(&pdev
->dev
, "error: clk_get\n");
926 return PTR_ERR(gpmc_l3_clk
);
929 clk_prepare_enable(gpmc_l3_clk
);
931 gpmc_dev
= &pdev
->dev
;
933 l
= gpmc_read_reg(GPMC_REVISION
);
934 if (GPMC_REVISION_MAJOR(l
) > 0x4)
935 gpmc_capability
= GPMC_HAS_WR_ACCESS
| GPMC_HAS_WR_DATA_MUX_BUS
;
936 dev_info(gpmc_dev
, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l
),
937 GPMC_REVISION_MINOR(l
));
941 if (IS_ERR_VALUE(gpmc_setup_irq()))
942 dev_warn(gpmc_dev
, "gpmc_setup_irq failed\n");
947 static __devexit
int gpmc_remove(struct platform_device
*pdev
)
955 static struct platform_driver gpmc_driver
= {
957 .remove
= __devexit_p(gpmc_remove
),
960 .owner
= THIS_MODULE
,
964 static __init
int gpmc_init(void)
966 return platform_driver_register(&gpmc_driver
);
969 static __exit
void gpmc_exit(void)
971 platform_driver_unregister(&gpmc_driver
);
975 postcore_initcall(gpmc_init
);
976 module_exit(gpmc_exit
);
978 static int __init
omap_gpmc_init(void)
980 struct omap_hwmod
*oh
;
981 struct platform_device
*pdev
;
982 char *oh_name
= "gpmc";
984 oh
= omap_hwmod_lookup(oh_name
);
986 pr_err("Could not look up %s\n", oh_name
);
990 pdev
= omap_device_build(DEVICE_NAME
, -1, oh
, NULL
, 0, NULL
, 0, 0);
991 WARN(IS_ERR(pdev
), "could not build omap_device for %s\n", oh_name
);
993 return IS_ERR(pdev
) ? PTR_ERR(pdev
) : 0;
995 postcore_initcall(omap_gpmc_init
);
997 static irqreturn_t
gpmc_handle_irq(int irq
, void *dev
)
1002 regval
= gpmc_read_reg(GPMC_IRQSTATUS
);
1007 for (i
= 0; i
< GPMC_NR_IRQ
; i
++)
1008 if (regval
& gpmc_client_irq
[i
].bitmask
)
1009 generic_handle_irq(gpmc_client_irq
[i
].irq
);
1011 gpmc_write_reg(GPMC_IRQSTATUS
, regval
);
1016 #ifdef CONFIG_ARCH_OMAP3
1017 static struct omap3_gpmc_regs gpmc_context
;
1019 void omap3_gpmc_save_context(void)
1023 gpmc_context
.sysconfig
= gpmc_read_reg(GPMC_SYSCONFIG
);
1024 gpmc_context
.irqenable
= gpmc_read_reg(GPMC_IRQENABLE
);
1025 gpmc_context
.timeout_ctrl
= gpmc_read_reg(GPMC_TIMEOUT_CONTROL
);
1026 gpmc_context
.config
= gpmc_read_reg(GPMC_CONFIG
);
1027 gpmc_context
.prefetch_config1
= gpmc_read_reg(GPMC_PREFETCH_CONFIG1
);
1028 gpmc_context
.prefetch_config2
= gpmc_read_reg(GPMC_PREFETCH_CONFIG2
);
1029 gpmc_context
.prefetch_control
= gpmc_read_reg(GPMC_PREFETCH_CONTROL
);
1030 for (i
= 0; i
< GPMC_CS_NUM
; i
++) {
1031 gpmc_context
.cs_context
[i
].is_valid
= gpmc_cs_mem_enabled(i
);
1032 if (gpmc_context
.cs_context
[i
].is_valid
) {
1033 gpmc_context
.cs_context
[i
].config1
=
1034 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG1
);
1035 gpmc_context
.cs_context
[i
].config2
=
1036 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG2
);
1037 gpmc_context
.cs_context
[i
].config3
=
1038 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG3
);
1039 gpmc_context
.cs_context
[i
].config4
=
1040 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG4
);
1041 gpmc_context
.cs_context
[i
].config5
=
1042 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG5
);
1043 gpmc_context
.cs_context
[i
].config6
=
1044 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG6
);
1045 gpmc_context
.cs_context
[i
].config7
=
1046 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG7
);
1051 void omap3_gpmc_restore_context(void)
1055 gpmc_write_reg(GPMC_SYSCONFIG
, gpmc_context
.sysconfig
);
1056 gpmc_write_reg(GPMC_IRQENABLE
, gpmc_context
.irqenable
);
1057 gpmc_write_reg(GPMC_TIMEOUT_CONTROL
, gpmc_context
.timeout_ctrl
);
1058 gpmc_write_reg(GPMC_CONFIG
, gpmc_context
.config
);
1059 gpmc_write_reg(GPMC_PREFETCH_CONFIG1
, gpmc_context
.prefetch_config1
);
1060 gpmc_write_reg(GPMC_PREFETCH_CONFIG2
, gpmc_context
.prefetch_config2
);
1061 gpmc_write_reg(GPMC_PREFETCH_CONTROL
, gpmc_context
.prefetch_control
);
1062 for (i
= 0; i
< GPMC_CS_NUM
; i
++) {
1063 if (gpmc_context
.cs_context
[i
].is_valid
) {
1064 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG1
,
1065 gpmc_context
.cs_context
[i
].config1
);
1066 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG2
,
1067 gpmc_context
.cs_context
[i
].config2
);
1068 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG3
,
1069 gpmc_context
.cs_context
[i
].config3
);
1070 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG4
,
1071 gpmc_context
.cs_context
[i
].config4
);
1072 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG5
,
1073 gpmc_context
.cs_context
[i
].config5
);
1074 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG6
,
1075 gpmc_context
.cs_context
[i
].config6
);
1076 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG7
,
1077 gpmc_context
.cs_context
[i
].config7
);
1081 #endif /* CONFIG_ARCH_OMAP3 */
1084 * gpmc_enable_hwecc - enable hardware ecc functionality
1085 * @cs: chip select number
1086 * @mode: read/write mode
1087 * @dev_width: device bus width(1 for x16, 0 for x8)
1088 * @ecc_size: bytes for which ECC will be generated
1090 int gpmc_enable_hwecc(int cs
, int mode
, int dev_width
, int ecc_size
)
1094 /* check if ecc module is in used */
1095 if (gpmc_ecc_used
!= -EINVAL
)
1100 /* clear ecc and enable bits */
1101 gpmc_write_reg(GPMC_ECC_CONTROL
,
1102 GPMC_ECC_CTRL_ECCCLEAR
|
1103 GPMC_ECC_CTRL_ECCREG1
);
1105 /* program ecc and result sizes */
1106 val
= ((((ecc_size
>> 1) - 1) << 22) | (0x0000000F));
1107 gpmc_write_reg(GPMC_ECC_SIZE_CONFIG
, val
);
1111 case GPMC_ECC_WRITE
:
1112 gpmc_write_reg(GPMC_ECC_CONTROL
,
1113 GPMC_ECC_CTRL_ECCCLEAR
|
1114 GPMC_ECC_CTRL_ECCREG1
);
1116 case GPMC_ECC_READSYN
:
1117 gpmc_write_reg(GPMC_ECC_CONTROL
,
1118 GPMC_ECC_CTRL_ECCCLEAR
|
1119 GPMC_ECC_CTRL_ECCDISABLE
);
1122 printk(KERN_INFO
"Error: Unrecognized Mode[%d]!\n", mode
);
1126 /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
1127 val
= (dev_width
<< 7) | (cs
<< 1) | (0x1);
1128 gpmc_write_reg(GPMC_ECC_CONFIG
, val
);
1131 EXPORT_SYMBOL_GPL(gpmc_enable_hwecc
);
1134 * gpmc_calculate_ecc - generate non-inverted ecc bytes
1135 * @cs: chip select number
1136 * @dat: data pointer over which ecc is computed
1137 * @ecc_code: ecc code buffer
1139 * Using non-inverted ECC is considered ugly since writing a blank
1140 * page (padding) will clear the ECC bytes. This is not a problem as long
1141 * no one is trying to write data on the seemingly unused page. Reading
1142 * an erased page will produce an ECC mismatch between generated and read
1143 * ECC bytes that has to be dealt with separately.
1145 int gpmc_calculate_ecc(int cs
, const u_char
*dat
, u_char
*ecc_code
)
1147 unsigned int val
= 0x0;
1149 if (gpmc_ecc_used
!= cs
)
1152 /* read ecc result */
1153 val
= gpmc_read_reg(GPMC_ECC1_RESULT
);
1154 *ecc_code
++ = val
; /* P128e, ..., P1e */
1155 *ecc_code
++ = val
>> 16; /* P128o, ..., P1o */
1156 /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
1157 *ecc_code
++ = ((val
>> 8) & 0x0f) | ((val
>> 20) & 0xf0);
1159 gpmc_ecc_used
= -EINVAL
;
1162 EXPORT_SYMBOL_GPL(gpmc_calculate_ecc
);
1164 #ifdef CONFIG_ARCH_OMAP3
1167 * gpmc_init_hwecc_bch - initialize hardware BCH ecc functionality
1168 * @cs: chip select number
1169 * @nsectors: how many 512-byte sectors to process
1170 * @nerrors: how many errors to correct per sector (4 or 8)
1172 * This function must be executed before any call to gpmc_enable_hwecc_bch.
1174 int gpmc_init_hwecc_bch(int cs
, int nsectors
, int nerrors
)
1176 /* check if ecc module is in use */
1177 if (gpmc_ecc_used
!= -EINVAL
)
1180 /* support only OMAP3 class */
1181 if (!cpu_is_omap34xx()) {
1182 printk(KERN_ERR
"BCH ecc is not supported on this CPU\n");
1187 * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1.
1188 * Other chips may be added if confirmed to work.
1190 if ((nerrors
== 4) &&
1191 (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) {
1192 printk(KERN_ERR
"BCH 4-bit mode is not supported on this CPU\n");
1198 printk(KERN_ERR
"BCH cannot process %d sectors (max is 8)\n",
1205 EXPORT_SYMBOL_GPL(gpmc_init_hwecc_bch
);
1208 * gpmc_enable_hwecc_bch - enable hardware BCH ecc functionality
1209 * @cs: chip select number
1210 * @mode: read/write mode
1211 * @dev_width: device bus width(1 for x16, 0 for x8)
1212 * @nsectors: how many 512-byte sectors to process
1213 * @nerrors: how many errors to correct per sector (4 or 8)
1215 int gpmc_enable_hwecc_bch(int cs
, int mode
, int dev_width
, int nsectors
,
1220 /* check if ecc module is in use */
1221 if (gpmc_ecc_used
!= -EINVAL
)
1226 /* clear ecc and enable bits */
1227 gpmc_write_reg(GPMC_ECC_CONTROL
, 0x1);
1230 * When using BCH, sector size is hardcoded to 512 bytes.
1231 * Here we are using wrapping mode 6 both for reading and writing, with:
1232 * size0 = 0 (no additional protected byte in spare area)
1233 * size1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
1235 gpmc_write_reg(GPMC_ECC_SIZE_CONFIG
, (32 << 22) | (0 << 12));
1237 /* BCH configuration */
1238 val
= ((1 << 16) | /* enable BCH */
1239 (((nerrors
== 8) ? 1 : 0) << 12) | /* 8 or 4 bits */
1240 (0x06 << 8) | /* wrap mode = 6 */
1241 (dev_width
<< 7) | /* bus width */
1242 (((nsectors
-1) & 0x7) << 4) | /* number of sectors */
1243 (cs
<< 1) | /* ECC CS */
1244 (0x1)); /* enable ECC */
1246 gpmc_write_reg(GPMC_ECC_CONFIG
, val
);
1247 gpmc_write_reg(GPMC_ECC_CONTROL
, 0x101);
1250 EXPORT_SYMBOL_GPL(gpmc_enable_hwecc_bch
);
1253 * gpmc_calculate_ecc_bch4 - Generate 7 ecc bytes per sector of 512 data bytes
1254 * @cs: chip select number
1255 * @dat: The pointer to data on which ecc is computed
1256 * @ecc: The ecc output buffer
1258 int gpmc_calculate_ecc_bch4(int cs
, const u_char
*dat
, u_char
*ecc
)
1261 unsigned long nsectors
, reg
, val1
, val2
;
1263 if (gpmc_ecc_used
!= cs
)
1266 nsectors
= ((gpmc_read_reg(GPMC_ECC_CONFIG
) >> 4) & 0x7) + 1;
1268 for (i
= 0; i
< nsectors
; i
++) {
1270 reg
= GPMC_ECC_BCH_RESULT_0
+ 16*i
;
1272 /* Read hw-computed remainder */
1273 val1
= gpmc_read_reg(reg
+ 0);
1274 val2
= gpmc_read_reg(reg
+ 4);
1277 * Add constant polynomial to remainder, in order to get an ecc
1278 * sequence of 0xFFs for a buffer filled with 0xFFs; and
1279 * left-justify the resulting polynomial.
1281 *ecc
++ = 0x28 ^ ((val2
>> 12) & 0xFF);
1282 *ecc
++ = 0x13 ^ ((val2
>> 4) & 0xFF);
1283 *ecc
++ = 0xcc ^ (((val2
& 0xF) << 4)|((val1
>> 28) & 0xF));
1284 *ecc
++ = 0x39 ^ ((val1
>> 20) & 0xFF);
1285 *ecc
++ = 0x96 ^ ((val1
>> 12) & 0xFF);
1286 *ecc
++ = 0xac ^ ((val1
>> 4) & 0xFF);
1287 *ecc
++ = 0x7f ^ ((val1
& 0xF) << 4);
1290 gpmc_ecc_used
= -EINVAL
;
1293 EXPORT_SYMBOL_GPL(gpmc_calculate_ecc_bch4
);
1296 * gpmc_calculate_ecc_bch8 - Generate 13 ecc bytes per block of 512 data bytes
1297 * @cs: chip select number
1298 * @dat: The pointer to data on which ecc is computed
1299 * @ecc: The ecc output buffer
1301 int gpmc_calculate_ecc_bch8(int cs
, const u_char
*dat
, u_char
*ecc
)
1304 unsigned long nsectors
, reg
, val1
, val2
, val3
, val4
;
1306 if (gpmc_ecc_used
!= cs
)
1309 nsectors
= ((gpmc_read_reg(GPMC_ECC_CONFIG
) >> 4) & 0x7) + 1;
1311 for (i
= 0; i
< nsectors
; i
++) {
1313 reg
= GPMC_ECC_BCH_RESULT_0
+ 16*i
;
1315 /* Read hw-computed remainder */
1316 val1
= gpmc_read_reg(reg
+ 0);
1317 val2
= gpmc_read_reg(reg
+ 4);
1318 val3
= gpmc_read_reg(reg
+ 8);
1319 val4
= gpmc_read_reg(reg
+ 12);
1322 * Add constant polynomial to remainder, in order to get an ecc
1323 * sequence of 0xFFs for a buffer filled with 0xFFs.
1325 *ecc
++ = 0xef ^ (val4
& 0xFF);
1326 *ecc
++ = 0x51 ^ ((val3
>> 24) & 0xFF);
1327 *ecc
++ = 0x2e ^ ((val3
>> 16) & 0xFF);
1328 *ecc
++ = 0x09 ^ ((val3
>> 8) & 0xFF);
1329 *ecc
++ = 0xed ^ (val3
& 0xFF);
1330 *ecc
++ = 0x93 ^ ((val2
>> 24) & 0xFF);
1331 *ecc
++ = 0x9a ^ ((val2
>> 16) & 0xFF);
1332 *ecc
++ = 0xc2 ^ ((val2
>> 8) & 0xFF);
1333 *ecc
++ = 0x97 ^ (val2
& 0xFF);
1334 *ecc
++ = 0x79 ^ ((val1
>> 24) & 0xFF);
1335 *ecc
++ = 0xe5 ^ ((val1
>> 16) & 0xFF);
1336 *ecc
++ = 0x24 ^ ((val1
>> 8) & 0xFF);
1337 *ecc
++ = 0xb5 ^ (val1
& 0xFF);
1340 gpmc_ecc_used
= -EINVAL
;
1343 EXPORT_SYMBOL_GPL(gpmc_calculate_ecc_bch8
);
1345 #endif /* CONFIG_ARCH_OMAP3 */