2 * linux/arch/arm/mach-omap2/hsmmc.c
4 * Copyright (C) 2007-2008 Texas Instruments
5 * Copyright (C) 2008 Nokia Corporation
6 * Author: Texas Instruments
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/slab.h>
14 #include <linux/string.h>
15 #include <linux/delay.h>
16 #include <mach/hardware.h>
17 #include <plat/control.h>
19 #include <plat/omap-pm.h>
23 #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
25 static u16 control_pbias_offset
;
26 static u16 control_devconf1_offset
;
27 static u16 control_mmc1
;
29 #define HSMMC_NAME_LEN 9
31 static struct hsmmc_controller
{
32 char name
[HSMMC_NAME_LEN
+ 1];
33 } hsmmc
[OMAP34XX_NR_MMC
];
35 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
37 static int hsmmc_get_context_loss(struct device
*dev
)
39 return omap_pm_get_dev_context_loss_count(dev
);
43 #define hsmmc_get_context_loss NULL
46 static void omap_hsmmc1_before_set_reg(struct device
*dev
, int slot
,
47 int power_on
, int vdd
)
50 struct omap_mmc_platform_data
*mmc
= dev
->platform_data
;
52 if (mmc
->slots
[0].remux
)
53 mmc
->slots
[0].remux(dev
, slot
, power_on
);
56 * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
57 * card with Vcc regulator (from twl4030 or whatever). OMAP has both
58 * 1.8V and 3.0V modes, controlled by the PBIAS register.
60 * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
61 * is most naturally TWL VSIM; those pins also use PBIAS.
63 * FIXME handle VMMC1A as needed ...
66 if (cpu_is_omap2430()) {
67 reg
= omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1
);
68 if ((1 << vdd
) >= MMC_VDD_30_31
)
69 reg
|= OMAP243X_MMC1_ACTIVE_OVERWRITE
;
71 reg
&= ~OMAP243X_MMC1_ACTIVE_OVERWRITE
;
72 omap_ctrl_writel(reg
, OMAP243X_CONTROL_DEVCONF1
);
75 if (mmc
->slots
[0].internal_clock
) {
76 reg
= omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0
);
77 reg
|= OMAP2_MMCSDIO1ADPCLKISEL
;
78 omap_ctrl_writel(reg
, OMAP2_CONTROL_DEVCONF0
);
81 reg
= omap_ctrl_readl(control_pbias_offset
);
82 if (cpu_is_omap3630()) {
83 /* Set MMC I/O to 52Mhz */
84 prog_io
= omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1
);
85 prog_io
|= OMAP3630_PRG_SDMMC1_SPEEDCTRL
;
86 omap_ctrl_writel(prog_io
, OMAP343X_CONTROL_PROG_IO1
);
88 reg
|= OMAP2_PBIASSPEEDCTRL0
;
90 reg
&= ~OMAP2_PBIASLITEPWRDNZ0
;
91 omap_ctrl_writel(reg
, control_pbias_offset
);
93 reg
= omap_ctrl_readl(control_pbias_offset
);
94 reg
&= ~OMAP2_PBIASLITEPWRDNZ0
;
95 omap_ctrl_writel(reg
, control_pbias_offset
);
99 static void omap_hsmmc1_after_set_reg(struct device
*dev
, int slot
,
100 int power_on
, int vdd
)
104 /* 100ms delay required for PBIAS configuration */
108 reg
= omap_ctrl_readl(control_pbias_offset
);
109 reg
|= (OMAP2_PBIASLITEPWRDNZ0
| OMAP2_PBIASSPEEDCTRL0
);
110 if ((1 << vdd
) <= MMC_VDD_165_195
)
111 reg
&= ~OMAP2_PBIASLITEVMODE0
;
113 reg
|= OMAP2_PBIASLITEVMODE0
;
114 omap_ctrl_writel(reg
, control_pbias_offset
);
116 reg
= omap_ctrl_readl(control_pbias_offset
);
117 reg
|= (OMAP2_PBIASSPEEDCTRL0
| OMAP2_PBIASLITEPWRDNZ0
|
118 OMAP2_PBIASLITEVMODE0
);
119 omap_ctrl_writel(reg
, control_pbias_offset
);
123 static void omap4_hsmmc1_before_set_reg(struct device
*dev
, int slot
,
124 int power_on
, int vdd
)
129 * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
130 * card with Vcc regulator (from twl4030 or whatever). OMAP has both
131 * 1.8V and 3.0V modes, controlled by the PBIAS register.
133 * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
134 * is most naturally TWL VSIM; those pins also use PBIAS.
136 * FIXME handle VMMC1A as needed ...
138 reg
= omap_ctrl_readl(control_pbias_offset
);
139 reg
&= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ
| OMAP4_MMC1_PWRDNZ
|
140 OMAP4_USBC1_ICUSB_PWRDNZ
);
141 omap_ctrl_writel(reg
, control_pbias_offset
);
144 static void omap4_hsmmc1_after_set_reg(struct device
*dev
, int slot
,
145 int power_on
, int vdd
)
150 reg
= omap_ctrl_readl(control_pbias_offset
);
151 reg
|= OMAP4_MMC1_PBIASLITE_PWRDNZ
;
152 if ((1 << vdd
) <= MMC_VDD_165_195
)
153 reg
&= ~OMAP4_MMC1_PBIASLITE_VMODE
;
155 reg
|= OMAP4_MMC1_PBIASLITE_VMODE
;
156 reg
|= (OMAP4_MMC1_PBIASLITE_PWRDNZ
| OMAP4_MMC1_PWRDNZ
|
157 OMAP4_USBC1_ICUSB_PWRDNZ
);
158 omap_ctrl_writel(reg
, control_pbias_offset
);
159 /* 4 microsec delay for comparator to generate an error*/
161 reg
= omap_ctrl_readl(control_pbias_offset
);
162 if (reg
& OMAP4_MMC1_PBIASLITE_VMODE_ERROR
) {
163 pr_err("Pbias Voltage is not same as LDO\n");
164 /* Caution : On VMODE_ERROR Power Down MMC IO */
165 reg
&= ~(OMAP4_MMC1_PWRDNZ
| OMAP4_USBC1_ICUSB_PWRDNZ
);
166 omap_ctrl_writel(reg
, control_pbias_offset
);
169 reg
= omap_ctrl_readl(control_pbias_offset
);
170 reg
|= (OMAP4_MMC1_PBIASLITE_PWRDNZ
|
171 OMAP4_MMC1_PBIASLITE_VMODE
| OMAP4_MMC1_PWRDNZ
|
172 OMAP4_USBC1_ICUSB_PWRDNZ
);
173 omap_ctrl_writel(reg
, control_pbias_offset
);
177 static void hsmmc23_before_set_reg(struct device
*dev
, int slot
,
178 int power_on
, int vdd
)
180 struct omap_mmc_platform_data
*mmc
= dev
->platform_data
;
182 if (mmc
->slots
[0].remux
)
183 mmc
->slots
[0].remux(dev
, slot
, power_on
);
186 /* Only MMC2 supports a CLKIN */
187 if (mmc
->slots
[0].internal_clock
) {
190 reg
= omap_ctrl_readl(control_devconf1_offset
);
191 reg
|= OMAP2_MMCSDIO2ADPCLKISEL
;
192 omap_ctrl_writel(reg
, control_devconf1_offset
);
197 static int nop_mmc_set_power(struct device
*dev
, int slot
, int power_on
,
203 static struct omap_mmc_platform_data
*hsmmc_data
[OMAP34XX_NR_MMC
] __initdata
;
205 void __init
omap2_hsmmc_init(struct omap2_hsmmc_info
*controllers
)
207 struct omap2_hsmmc_info
*c
;
208 int nr_hsmmc
= ARRAY_SIZE(hsmmc_data
);
212 if (!cpu_is_omap44xx()) {
213 if (cpu_is_omap2430()) {
214 control_pbias_offset
= OMAP243X_CONTROL_PBIAS_LITE
;
215 control_devconf1_offset
= OMAP243X_CONTROL_DEVCONF1
;
217 control_pbias_offset
= OMAP343X_CONTROL_PBIAS_LITE
;
218 control_devconf1_offset
= OMAP343X_CONTROL_DEVCONF1
;
221 control_pbias_offset
= OMAP44XX_CONTROL_PBIAS_LITE
;
222 control_mmc1
= OMAP44XX_CONTROL_MMC1
;
223 reg
= omap_ctrl_readl(control_mmc1
);
224 reg
|= (OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0
|
225 OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1
);
226 reg
&= ~(OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2
|
227 OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3
);
228 reg
|= (OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL
|
229 OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL
|
230 OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL
);
231 omap_ctrl_writel(reg
, control_mmc1
);
234 for (c
= controllers
; c
->mmc
; c
++) {
235 struct hsmmc_controller
*hc
= hsmmc
+ c
->mmc
- 1;
236 struct omap_mmc_platform_data
*mmc
= hsmmc_data
[c
->mmc
- 1];
238 if (!c
->mmc
|| c
->mmc
> nr_hsmmc
) {
239 pr_debug("MMC%d: no such controller\n", c
->mmc
);
243 pr_debug("MMC%d: already configured\n", c
->mmc
);
247 mmc
= kzalloc(sizeof(struct omap_mmc_platform_data
),
250 pr_err("Cannot allocate memory for mmc device!\n");
255 strncpy(hc
->name
, c
->name
, HSMMC_NAME_LEN
);
257 snprintf(hc
->name
, ARRAY_SIZE(hc
->name
),
258 "mmc%islot%i", c
->mmc
, 1);
259 mmc
->slots
[0].name
= hc
->name
;
261 mmc
->slots
[0].wires
= c
->wires
;
262 mmc
->slots
[0].internal_clock
= !c
->ext_clock
;
263 mmc
->dma_mask
= 0xffffffff;
265 mmc
->get_context_loss_count
= hsmmc_get_context_loss
;
267 mmc
->slots
[0].switch_pin
= c
->gpio_cd
;
268 mmc
->slots
[0].gpio_wp
= c
->gpio_wp
;
270 mmc
->slots
[0].remux
= c
->remux
;
271 mmc
->slots
[0].init_card
= c
->init_card
;
274 mmc
->slots
[0].cover
= 1;
277 mmc
->slots
[0].nonremovable
= 1;
280 mmc
->slots
[0].power_saving
= 1;
283 mmc
->slots
[0].no_off
= 1;
285 if (c
->vcc_aux_disable_is_sleep
)
286 mmc
->slots
[0].vcc_aux_disable_is_sleep
= 1;
288 /* NOTE: MMC slots should have a Vcc regulator set up.
289 * This may be from a TWL4030-family chip, another
290 * controllable regulator, or a fixed supply.
292 * temporary HACK: ocr_mask instead of fixed supply
294 mmc
->slots
[0].ocr_mask
= c
->ocr_mask
;
296 if (cpu_is_omap3517() || cpu_is_omap3505())
297 mmc
->slots
[0].set_power
= nop_mmc_set_power
;
299 mmc
->slots
[0].features
|= HSMMC_HAS_PBIAS
;
303 if (mmc
->slots
[0].features
& HSMMC_HAS_PBIAS
) {
304 /* on-chip level shifting via PBIAS0/PBIAS1 */
305 if (cpu_is_omap44xx()) {
306 mmc
->slots
[0].before_set_reg
=
307 omap4_hsmmc1_before_set_reg
;
308 mmc
->slots
[0].after_set_reg
=
309 omap4_hsmmc1_after_set_reg
;
311 mmc
->slots
[0].before_set_reg
=
312 omap_hsmmc1_before_set_reg
;
313 mmc
->slots
[0].after_set_reg
=
314 omap_hsmmc1_after_set_reg
;
318 /* Omap3630 HSMMC1 supports only 4-bit */
319 if (cpu_is_omap3630() && c
->wires
> 4) {
321 mmc
->slots
[0].wires
= c
->wires
;
327 if (c
->transceiver
&& c
->wires
> 4)
331 if (mmc
->slots
[0].features
& HSMMC_HAS_PBIAS
) {
332 /* off-chip level shifting, or none */
333 mmc
->slots
[0].before_set_reg
= hsmmc23_before_set_reg
;
334 mmc
->slots
[0].after_set_reg
= NULL
;
338 pr_err("MMC%d configuration not supported!\n", c
->mmc
);
342 hsmmc_data
[c
->mmc
- 1] = mmc
;
345 omap2_init_mmc(hsmmc_data
, OMAP34XX_NR_MMC
);
347 /* pass the device nodes back to board setup code */
348 for (c
= controllers
; c
->mmc
; c
++) {
349 struct omap_mmc_platform_data
*mmc
= hsmmc_data
[c
->mmc
- 1];
351 if (!c
->mmc
|| c
->mmc
> nr_hsmmc
)
357 for (i
= 0; i
< nr_hsmmc
; i
++)
358 kfree(hsmmc_data
[i
]);