2 * linux/arch/arm/mach-omap2/id.c
4 * OMAP2 CPU identification code
6 * Copyright (C) 2005 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com>
9 * Copyright (C) 2009-11 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
21 #include <linux/random.h>
22 #include <linux/slab.h>
25 #include <linux/sys_soc.h>
28 #include <asm/cputype.h>
37 #define OMAP4_SILICON_TYPE_STANDARD 0x01
38 #define OMAP4_SILICON_TYPE_PERFORMANCE 0x02
40 #define OMAP_SOC_MAX_NAME_LENGTH 16
42 static unsigned int omap_revision
;
43 static char soc_name
[OMAP_SOC_MAX_NAME_LENGTH
];
44 static char soc_rev
[OMAP_SOC_MAX_NAME_LENGTH
];
47 unsigned int omap_rev(void)
49 WARN_ON_ONCE(!omap_revision
|| omap_revision
== -1);
52 EXPORT_SYMBOL(omap_rev
);
56 static u32 val
= OMAP2_DEVICETYPE_MASK
;
58 if (val
< OMAP2_DEVICETYPE_MASK
)
61 if (soc_is_omap24xx()) {
62 val
= omap_ctrl_readl(OMAP24XX_CONTROL_STATUS
);
63 } else if (soc_is_ti81xx()) {
64 val
= omap_ctrl_readl(TI81XX_CONTROL_STATUS
);
65 } else if (soc_is_am33xx() || soc_is_am43xx()) {
66 val
= omap_ctrl_readl(AM33XX_CONTROL_STATUS
);
67 } else if (soc_is_omap34xx()) {
68 val
= omap_ctrl_readl(OMAP343X_CONTROL_STATUS
);
69 } else if (soc_is_omap44xx()) {
70 val
= omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS
);
71 } else if (soc_is_omap54xx() || soc_is_dra7xx()) {
72 val
= omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS
);
73 val
&= OMAP5_DEVICETYPE_MASK
;
77 pr_err("Cannot detect omap type!\n");
81 val
&= OMAP2_DEVICETYPE_MASK
;
87 EXPORT_SYMBOL(omap_type
);
90 /*----------------------------------------------------------------------------*/
92 #define OMAP_TAP_IDCODE 0x0204
93 #define OMAP_TAP_DIE_ID_0 0x0218
94 #define OMAP_TAP_DIE_ID_1 0x021C
95 #define OMAP_TAP_DIE_ID_2 0x0220
96 #define OMAP_TAP_DIE_ID_3 0x0224
98 #define OMAP_TAP_DIE_ID_44XX_0 0x0200
99 #define OMAP_TAP_DIE_ID_44XX_1 0x0208
100 #define OMAP_TAP_DIE_ID_44XX_2 0x020c
101 #define OMAP_TAP_DIE_ID_44XX_3 0x0210
103 #define read_tap_reg(reg) readl_relaxed(tap_base + (reg))
106 u16 hawkeye
; /* Silicon type (Hawkeye id) */
107 u8 dev
; /* Device type from production_id reg */
108 u32 type
; /* Combined type id copied to omap_revision */
111 /* Register values to detect the OMAP version */
112 static struct omap_id omap_ids
[] __initdata
= {
113 { .hawkeye
= 0xb5d9, .dev
= 0x0, .type
= 0x24200024 },
114 { .hawkeye
= 0xb5d9, .dev
= 0x1, .type
= 0x24201024 },
115 { .hawkeye
= 0xb5d9, .dev
= 0x2, .type
= 0x24202024 },
116 { .hawkeye
= 0xb5d9, .dev
= 0x4, .type
= 0x24220024 },
117 { .hawkeye
= 0xb5d9, .dev
= 0x8, .type
= 0x24230024 },
118 { .hawkeye
= 0xb68a, .dev
= 0x0, .type
= 0x24300024 },
121 static void __iomem
*tap_base
;
122 static u16 tap_prod_id
;
124 void omap_get_die_id(struct omap_die_id
*odi
)
126 if (soc_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
127 odi
->id_0
= read_tap_reg(OMAP_TAP_DIE_ID_44XX_0
);
128 odi
->id_1
= read_tap_reg(OMAP_TAP_DIE_ID_44XX_1
);
129 odi
->id_2
= read_tap_reg(OMAP_TAP_DIE_ID_44XX_2
);
130 odi
->id_3
= read_tap_reg(OMAP_TAP_DIE_ID_44XX_3
);
134 odi
->id_0
= read_tap_reg(OMAP_TAP_DIE_ID_0
);
135 odi
->id_1
= read_tap_reg(OMAP_TAP_DIE_ID_1
);
136 odi
->id_2
= read_tap_reg(OMAP_TAP_DIE_ID_2
);
137 odi
->id_3
= read_tap_reg(OMAP_TAP_DIE_ID_3
);
140 static int __init
omap_feed_randpool(void)
142 struct omap_die_id odi
;
144 /* Throw the die ID into the entropy pool at boot */
145 omap_get_die_id(&odi
);
146 add_device_randomness(&odi
, sizeof(odi
));
149 omap_device_initcall(omap_feed_randpool
);
151 void __init
omap2xxx_check_revision(void)
157 struct omap_die_id odi
;
159 idcode
= read_tap_reg(OMAP_TAP_IDCODE
);
160 prod_id
= read_tap_reg(tap_prod_id
);
161 hawkeye
= (idcode
>> 12) & 0xffff;
162 rev
= (idcode
>> 28) & 0x0f;
163 dev_type
= (prod_id
>> 16) & 0x0f;
164 omap_get_die_id(&odi
);
166 pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
167 idcode
, rev
, hawkeye
, (idcode
>> 1) & 0x7ff);
168 pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi
.id_0
);
169 pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
170 odi
.id_1
, (odi
.id_1
>> 28) & 0xf);
171 pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi
.id_2
);
172 pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi
.id_3
);
173 pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
176 /* Check hawkeye ids */
177 for (i
= 0; i
< ARRAY_SIZE(omap_ids
); i
++) {
178 if (hawkeye
== omap_ids
[i
].hawkeye
)
182 if (i
== ARRAY_SIZE(omap_ids
)) {
183 printk(KERN_ERR
"Unknown OMAP CPU id\n");
187 for (j
= i
; j
< ARRAY_SIZE(omap_ids
); j
++) {
188 if (dev_type
== omap_ids
[j
].dev
)
192 if (j
== ARRAY_SIZE(omap_ids
)) {
193 pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n",
194 omap_ids
[i
].type
>> 16);
198 sprintf(soc_name
, "OMAP%04x", omap_rev() >> 16);
199 sprintf(soc_rev
, "ES%x", (omap_rev() >> 12) & 0xf);
201 pr_info("%s", soc_name
);
202 if ((omap_rev() >> 8) & 0x0f)
203 pr_info("%s", soc_rev
);
207 #define OMAP3_SHOW_FEATURE(feat) \
208 if (omap3_has_ ##feat()) \
211 static void __init
omap3_cpuinfo(void)
213 const char *cpu_name
;
216 * OMAP3430 and OMAP3530 are assumed to be same.
218 * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
219 * on available features. Upon detection, update the CPU id
220 * and CPU class bits.
222 if (soc_is_omap3630()) {
223 cpu_name
= "OMAP3630";
224 } else if (soc_is_am35xx()) {
225 cpu_name
= (omap3_has_sgx()) ? "AM3517" : "AM3505";
226 } else if (soc_is_ti816x()) {
228 } else if (soc_is_am335x()) {
230 } else if (soc_is_am437x()) {
232 } else if (soc_is_ti814x()) {
234 } else if (omap3_has_iva() && omap3_has_sgx()) {
235 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
236 cpu_name
= "OMAP3430/3530";
237 } else if (omap3_has_iva()) {
238 cpu_name
= "OMAP3525";
239 } else if (omap3_has_sgx()) {
240 cpu_name
= "OMAP3515";
242 cpu_name
= "OMAP3503";
245 sprintf(soc_name
, "%s", cpu_name
);
247 /* Print verbose information */
248 pr_info("%s %s (", soc_name
, soc_rev
);
250 OMAP3_SHOW_FEATURE(l2cache
);
251 OMAP3_SHOW_FEATURE(iva
);
252 OMAP3_SHOW_FEATURE(sgx
);
253 OMAP3_SHOW_FEATURE(neon
);
254 OMAP3_SHOW_FEATURE(isp
);
255 OMAP3_SHOW_FEATURE(192mhz_clk
);
260 #define OMAP3_CHECK_FEATURE(status,feat) \
261 if (((status & OMAP3_ ##feat## _MASK) \
262 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \
263 omap_features |= OMAP3_HAS_ ##feat; \
266 void __init
omap3xxx_check_features(void)
272 status
= omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS
);
274 OMAP3_CHECK_FEATURE(status
, L2CACHE
);
275 OMAP3_CHECK_FEATURE(status
, IVA
);
276 OMAP3_CHECK_FEATURE(status
, SGX
);
277 OMAP3_CHECK_FEATURE(status
, NEON
);
278 OMAP3_CHECK_FEATURE(status
, ISP
);
279 if (soc_is_omap3630())
280 omap_features
|= OMAP3_HAS_192MHZ_CLK
;
281 if (soc_is_omap3430() || soc_is_omap3630())
282 omap_features
|= OMAP3_HAS_IO_WAKEUP
;
283 if (soc_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1
||
284 omap_rev() == OMAP3430_REV_ES3_1_2
)
285 omap_features
|= OMAP3_HAS_IO_CHAIN_CTRL
;
287 omap_features
|= OMAP3_HAS_SDRC
;
291 * - The am35x Chip ID register has bits 12, 7:5, and 3:2 marked as
292 * reserved and therefore return 0 when read. Unfortunately,
293 * OMAP3_CHECK_FEATURE() will interpret some of those zeroes to
294 * mean that a feature is present even though it isn't so clear
295 * the incorrectly set feature bits.
298 omap_features
&= ~(OMAP3_HAS_IVA
| OMAP3_HAS_ISP
);
301 * TODO: Get additional info (where applicable)
302 * e.g. Size of L2 cache.
308 void __init
omap4xxx_check_features(void)
313 (read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1
) >> 16) & 0x03;
315 if (si_type
== OMAP4_SILICON_TYPE_PERFORMANCE
)
316 omap_features
= OMAP4_HAS_PERF_SILICON
;
319 void __init
ti81xx_check_features(void)
321 omap_features
= OMAP3_HAS_NEON
;
325 void __init
am33xx_check_features(void)
329 omap_features
= OMAP3_HAS_NEON
;
331 status
= omap_ctrl_readl(AM33XX_DEV_FEATURE
);
332 if (status
& AM33XX_SGX_MASK
)
333 omap_features
|= OMAP3_HAS_SGX
;
338 void __init
omap3xxx_check_revision(void)
346 * We cannot access revision registers on ES1.0.
347 * If the processor type is Cortex-A8 and the revision is 0x0
348 * it means its Cortex r0p0 which is 3430 ES1.0.
350 cpuid
= read_cpuid_id();
351 if ((((cpuid
>> 4) & 0xfff) == 0xc08) && ((cpuid
& 0xf) == 0x0)) {
352 omap_revision
= OMAP3430_REV_ES1_0
;
358 * Detection for 34xx ES2.0 and above can be done with just
359 * hawkeye and rev. See TRM 1.5.2 Device Identification.
360 * Note that rev does not map directly to our defined processor
361 * revision numbers as ES1.0 uses value 0.
363 idcode
= read_tap_reg(OMAP_TAP_IDCODE
);
364 hawkeye
= (idcode
>> 12) & 0xffff;
365 rev
= (idcode
>> 28) & 0xff;
369 /* Handle 34xx/35xx devices */
371 case 0: /* Take care of early samples */
373 omap_revision
= OMAP3430_REV_ES2_0
;
377 omap_revision
= OMAP3430_REV_ES2_1
;
381 omap_revision
= OMAP3430_REV_ES3_0
;
385 omap_revision
= OMAP3430_REV_ES3_1
;
391 /* Use the latest known revision as default */
392 omap_revision
= OMAP3430_REV_ES3_1_2
;
398 * Handle OMAP/AM 3505/3517 devices
400 * Set the device to be OMAP3517 here. Actual device
401 * is identified later based on the features.
405 omap_revision
= AM35XX_REV_ES1_0
;
411 omap_revision
= AM35XX_REV_ES1_1
;
416 /* Handle 36xx devices */
419 case 0: /* Take care of early samples */
420 omap_revision
= OMAP3630_REV_ES1_0
;
424 omap_revision
= OMAP3630_REV_ES1_1
;
430 omap_revision
= OMAP3630_REV_ES1_2
;
437 omap_revision
= TI8168_REV_ES1_0
;
441 omap_revision
= TI8168_REV_ES1_1
;
445 omap_revision
= TI8168_REV_ES2_0
;
451 omap_revision
= TI8168_REV_ES2_1
;
458 omap_revision
= AM335X_REV_ES1_0
;
462 omap_revision
= AM335X_REV_ES2_0
;
468 omap_revision
= AM335X_REV_ES2_1
;
476 omap_revision
= AM437X_REV_ES1_0
;
480 omap_revision
= AM437X_REV_ES1_1
;
486 omap_revision
= AM437X_REV_ES1_2
;
497 omap_revision
= TI8148_REV_ES1_0
;
501 omap_revision
= TI8148_REV_ES2_0
;
507 omap_revision
= TI8148_REV_ES2_1
;
513 /* Unknown default to latest silicon rev as default */
514 omap_revision
= OMAP3630_REV_ES1_2
;
516 pr_warn("Warning: unknown chip type: hawkeye %04x, assuming OMAP3630ES1.2\n",
519 sprintf(soc_rev
, "ES%s", cpu_rev
);
522 void __init
omap4xxx_check_revision(void)
529 * The IC rev detection is done with hawkeye and rev.
530 * Note that rev does not map directly to defined processor
531 * revision numbers as ES1.0 uses value 0.
533 idcode
= read_tap_reg(OMAP_TAP_IDCODE
);
534 hawkeye
= (idcode
>> 12) & 0xffff;
535 rev
= (idcode
>> 28) & 0xf;
538 * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
539 * Use ARM register to detect the correct ES version
541 if (!rev
&& (hawkeye
!= 0xb94e) && (hawkeye
!= 0xb975)) {
542 idcode
= read_cpuid_id();
543 rev
= (idcode
& 0xf) - 1;
550 omap_revision
= OMAP4430_REV_ES1_0
;
554 omap_revision
= OMAP4430_REV_ES2_0
;
560 omap_revision
= OMAP4430_REV_ES2_1
;
563 omap_revision
= OMAP4430_REV_ES2_2
;
567 omap_revision
= OMAP4430_REV_ES2_3
;
573 omap_revision
= OMAP4460_REV_ES1_0
;
577 omap_revision
= OMAP4460_REV_ES1_1
;
585 omap_revision
= OMAP4470_REV_ES1_0
;
590 /* Unknown default to latest silicon rev as default */
591 omap_revision
= OMAP4430_REV_ES2_3
;
594 sprintf(soc_name
, "OMAP%04x", omap_rev() >> 16);
595 sprintf(soc_rev
, "ES%d.%d", (omap_rev() >> 12) & 0xf,
596 (omap_rev() >> 8) & 0xf);
597 pr_info("%s %s\n", soc_name
, soc_rev
);
600 void __init
omap5xxx_check_revision(void)
606 idcode
= read_tap_reg(OMAP_TAP_IDCODE
);
607 hawkeye
= (idcode
>> 12) & 0xffff;
608 rev
= (idcode
>> 28) & 0xff;
613 /* No support for ES1.0 Test chip */
617 omap_revision
= OMAP5430_REV_ES2_0
;
624 /* No support for ES1.0 Test chip */
628 omap_revision
= OMAP5432_REV_ES2_0
;
633 /* Unknown default to latest silicon rev as default*/
634 omap_revision
= OMAP5430_REV_ES2_0
;
637 sprintf(soc_name
, "OMAP%04x", omap_rev() >> 16);
638 sprintf(soc_rev
, "ES%d.0", (omap_rev() >> 12) & 0xf);
640 pr_info("%s %s\n", soc_name
, soc_rev
);
643 void __init
dra7xxx_check_revision(void)
649 idcode
= read_tap_reg(OMAP_TAP_IDCODE
);
650 hawkeye
= (idcode
>> 12) & 0xffff;
651 rev
= (idcode
>> 28) & 0xff;
656 omap_revision
= DRA752_REV_ES1_0
;
659 omap_revision
= DRA752_REV_ES1_1
;
663 omap_revision
= DRA752_REV_ES2_0
;
671 omap_revision
= DRA722_REV_ES1_0
;
675 omap_revision
= DRA722_REV_ES2_0
;
681 /* Unknown default to latest silicon rev as default*/
682 pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%x)\n",
683 __func__
, idcode
, hawkeye
, rev
);
684 omap_revision
= DRA752_REV_ES2_0
;
687 sprintf(soc_name
, "DRA%03x", omap_rev() >> 16);
688 sprintf(soc_rev
, "ES%d.%d", (omap_rev() >> 12) & 0xf,
689 (omap_rev() >> 8) & 0xf);
691 pr_info("%s %s\n", soc_name
, soc_rev
);
695 * Set up things for map_io and processor detection later on. Gets called
696 * pretty much first thing from board init. For multi-omap, this gets
697 * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
698 * detect the exact revision later on in omap2_detect_revision() once map_io
701 void __init
omap2_set_globals_tap(u32
class, void __iomem
*tap
)
703 omap_revision
= class;
706 /* XXX What is this intended to do? */
707 if (soc_is_omap34xx())
708 tap_prod_id
= 0x0210;
710 tap_prod_id
= 0x0208;
713 #ifdef CONFIG_SOC_BUS
715 static const char * const omap_types
[] = {
716 [OMAP2_DEVICE_TYPE_TEST
] = "TST",
717 [OMAP2_DEVICE_TYPE_EMU
] = "EMU",
718 [OMAP2_DEVICE_TYPE_SEC
] = "HS",
719 [OMAP2_DEVICE_TYPE_GP
] = "GP",
720 [OMAP2_DEVICE_TYPE_BAD
] = "BAD",
723 static const char * __init
omap_get_family(void)
725 if (soc_is_omap24xx())
726 return kasprintf(GFP_KERNEL
, "OMAP2");
727 else if (soc_is_omap34xx())
728 return kasprintf(GFP_KERNEL
, "OMAP3");
729 else if (soc_is_omap44xx())
730 return kasprintf(GFP_KERNEL
, "OMAP4");
731 else if (soc_is_omap54xx())
732 return kasprintf(GFP_KERNEL
, "OMAP5");
733 else if (soc_is_am33xx() || soc_is_am335x())
734 return kasprintf(GFP_KERNEL
, "AM33xx");
735 else if (soc_is_am43xx())
736 return kasprintf(GFP_KERNEL
, "AM43xx");
737 else if (soc_is_dra7xx())
738 return kasprintf(GFP_KERNEL
, "DRA7");
740 return kasprintf(GFP_KERNEL
, "Unknown");
743 static ssize_t
omap_get_type(struct device
*dev
,
744 struct device_attribute
*attr
,
747 return sprintf(buf
, "%s\n", omap_types
[omap_type()]);
750 static struct device_attribute omap_soc_attr
=
751 __ATTR(type
, S_IRUGO
, omap_get_type
, NULL
);
753 void __init
omap_soc_device_init(void)
755 struct device
*parent
;
756 struct soc_device
*soc_dev
;
757 struct soc_device_attribute
*soc_dev_attr
;
759 soc_dev_attr
= kzalloc(sizeof(*soc_dev_attr
), GFP_KERNEL
);
763 soc_dev_attr
->machine
= soc_name
;
764 soc_dev_attr
->family
= omap_get_family();
765 soc_dev_attr
->revision
= soc_rev
;
767 soc_dev
= soc_device_register(soc_dev_attr
);
768 if (IS_ERR(soc_dev
)) {
773 parent
= soc_device_to_device(soc_dev
);
774 device_create_file(parent
, &omap_soc_attr
);
776 #endif /* CONFIG_SOC_BUS */