2 * linux/arch/arm/mach-omap2/id.c
4 * OMAP2 CPU identification code
6 * Copyright (C) 2005 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com>
9 * Copyright (C) 2009-11 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
22 #include <asm/cputype.h>
24 #include <plat/common.h>
31 static unsigned int omap_revision
;
35 unsigned int omap_rev(void)
39 EXPORT_SYMBOL(omap_rev
);
45 if (cpu_is_omap24xx()) {
46 val
= omap_ctrl_readl(OMAP24XX_CONTROL_STATUS
);
47 } else if (cpu_is_omap34xx()) {
48 val
= omap_ctrl_readl(OMAP343X_CONTROL_STATUS
);
49 } else if (cpu_is_omap44xx()) {
50 val
= omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS
);
52 pr_err("Cannot detect omap type!\n");
56 val
&= OMAP2_DEVICETYPE_MASK
;
62 EXPORT_SYMBOL(omap_type
);
65 /*----------------------------------------------------------------------------*/
67 #define OMAP_TAP_IDCODE 0x0204
68 #define OMAP_TAP_DIE_ID_0 0x0218
69 #define OMAP_TAP_DIE_ID_1 0x021C
70 #define OMAP_TAP_DIE_ID_2 0x0220
71 #define OMAP_TAP_DIE_ID_3 0x0224
73 #define OMAP_TAP_DIE_ID_44XX_0 0x0200
74 #define OMAP_TAP_DIE_ID_44XX_1 0x0208
75 #define OMAP_TAP_DIE_ID_44XX_2 0x020c
76 #define OMAP_TAP_DIE_ID_44XX_3 0x0210
78 #define read_tap_reg(reg) __raw_readl(tap_base + (reg))
81 u16 hawkeye
; /* Silicon type (Hawkeye id) */
82 u8 dev
; /* Device type from production_id reg */
83 u32 type
; /* Combined type id copied to omap_revision */
86 /* Register values to detect the OMAP version */
87 static struct omap_id omap_ids
[] __initdata
= {
88 { .hawkeye
= 0xb5d9, .dev
= 0x0, .type
= 0x24200024 },
89 { .hawkeye
= 0xb5d9, .dev
= 0x1, .type
= 0x24201024 },
90 { .hawkeye
= 0xb5d9, .dev
= 0x2, .type
= 0x24202024 },
91 { .hawkeye
= 0xb5d9, .dev
= 0x4, .type
= 0x24220024 },
92 { .hawkeye
= 0xb5d9, .dev
= 0x8, .type
= 0x24230024 },
93 { .hawkeye
= 0xb68a, .dev
= 0x0, .type
= 0x24300024 },
96 static void __iomem
*tap_base
;
97 static u16 tap_prod_id
;
99 void omap_get_die_id(struct omap_die_id
*odi
)
101 if (cpu_is_omap44xx()) {
102 odi
->id_0
= read_tap_reg(OMAP_TAP_DIE_ID_44XX_0
);
103 odi
->id_1
= read_tap_reg(OMAP_TAP_DIE_ID_44XX_1
);
104 odi
->id_2
= read_tap_reg(OMAP_TAP_DIE_ID_44XX_2
);
105 odi
->id_3
= read_tap_reg(OMAP_TAP_DIE_ID_44XX_3
);
109 odi
->id_0
= read_tap_reg(OMAP_TAP_DIE_ID_0
);
110 odi
->id_1
= read_tap_reg(OMAP_TAP_DIE_ID_1
);
111 odi
->id_2
= read_tap_reg(OMAP_TAP_DIE_ID_2
);
112 odi
->id_3
= read_tap_reg(OMAP_TAP_DIE_ID_3
);
115 static void __init
omap24xx_check_revision(void)
121 struct omap_die_id odi
;
123 idcode
= read_tap_reg(OMAP_TAP_IDCODE
);
124 prod_id
= read_tap_reg(tap_prod_id
);
125 hawkeye
= (idcode
>> 12) & 0xffff;
126 rev
= (idcode
>> 28) & 0x0f;
127 dev_type
= (prod_id
>> 16) & 0x0f;
128 omap_get_die_id(&odi
);
130 pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
131 idcode
, rev
, hawkeye
, (idcode
>> 1) & 0x7ff);
132 pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi
.id_0
);
133 pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
134 odi
.id_1
, (odi
.id_1
>> 28) & 0xf);
135 pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi
.id_2
);
136 pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi
.id_3
);
137 pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
140 /* Check hawkeye ids */
141 for (i
= 0; i
< ARRAY_SIZE(omap_ids
); i
++) {
142 if (hawkeye
== omap_ids
[i
].hawkeye
)
146 if (i
== ARRAY_SIZE(omap_ids
)) {
147 printk(KERN_ERR
"Unknown OMAP CPU id\n");
151 for (j
= i
; j
< ARRAY_SIZE(omap_ids
); j
++) {
152 if (dev_type
== omap_ids
[j
].dev
)
156 if (j
== ARRAY_SIZE(omap_ids
)) {
157 printk(KERN_ERR
"Unknown OMAP device type. "
158 "Handling it as OMAP%04x\n",
159 omap_ids
[i
].type
>> 16);
163 pr_info("OMAP%04x", omap_rev() >> 16);
164 if ((omap_rev() >> 8) & 0x0f)
165 pr_info("ES%x", (omap_rev() >> 12) & 0xf);
169 #define OMAP3_CHECK_FEATURE(status,feat) \
170 if (((status & OMAP3_ ##feat## _MASK) \
171 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \
172 omap_features |= OMAP3_HAS_ ##feat; \
175 static void __init
omap3_check_features(void)
181 status
= omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS
);
183 OMAP3_CHECK_FEATURE(status
, L2CACHE
);
184 OMAP3_CHECK_FEATURE(status
, IVA
);
185 OMAP3_CHECK_FEATURE(status
, SGX
);
186 OMAP3_CHECK_FEATURE(status
, NEON
);
187 OMAP3_CHECK_FEATURE(status
, ISP
);
188 if (cpu_is_omap3630())
189 omap_features
|= OMAP3_HAS_192MHZ_CLK
;
190 if (!cpu_is_omap3505() && !cpu_is_omap3517())
191 omap_features
|= OMAP3_HAS_IO_WAKEUP
;
193 omap_features
|= OMAP3_HAS_SDRC
;
196 * TODO: Get additional info (where applicable)
197 * e.g. Size of L2 cache.
201 static void __init
omap4_check_features(void)
205 if (cpu_is_omap443x())
206 omap_features
|= OMAP4_HAS_MPU_1GHZ
;
209 if (cpu_is_omap446x()) {
211 read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1
);
212 switch ((si_type
& (3 << 16)) >> 16) {
214 /* High performance device */
215 omap_features
|= OMAP4_HAS_MPU_1_5GHZ
;
219 /* Standard device */
220 omap_features
|= OMAP4_HAS_MPU_1_2GHZ
;
226 static void __init
ti816x_check_features(void)
228 omap_features
= OMAP3_HAS_NEON
;
231 static void __init
omap3_check_revision(const char **cpu_rev
)
238 * We cannot access revision registers on ES1.0.
239 * If the processor type is Cortex-A8 and the revision is 0x0
240 * it means its Cortex r0p0 which is 3430 ES1.0.
242 cpuid
= read_cpuid(CPUID_ID
);
243 if ((((cpuid
>> 4) & 0xfff) == 0xc08) && ((cpuid
& 0xf) == 0x0)) {
244 omap_revision
= OMAP3430_REV_ES1_0
;
250 * Detection for 34xx ES2.0 and above can be done with just
251 * hawkeye and rev. See TRM 1.5.2 Device Identification.
252 * Note that rev does not map directly to our defined processor
253 * revision numbers as ES1.0 uses value 0.
255 idcode
= read_tap_reg(OMAP_TAP_IDCODE
);
256 hawkeye
= (idcode
>> 12) & 0xffff;
257 rev
= (idcode
>> 28) & 0xff;
261 /* Handle 34xx/35xx devices */
263 case 0: /* Take care of early samples */
265 omap_revision
= OMAP3430_REV_ES2_0
;
269 omap_revision
= OMAP3430_REV_ES2_1
;
273 omap_revision
= OMAP3430_REV_ES3_0
;
277 omap_revision
= OMAP3430_REV_ES3_1
;
283 /* Use the latest known revision as default */
284 omap_revision
= OMAP3430_REV_ES3_1_2
;
290 * Handle OMAP/AM 3505/3517 devices
292 * Set the device to be OMAP3517 here. Actual device
293 * is identified later based on the features.
297 omap_revision
= OMAP3517_REV_ES1_0
;
303 omap_revision
= OMAP3517_REV_ES1_1
;
308 /* Handle 36xx devices */
311 case 0: /* Take care of early samples */
312 omap_revision
= OMAP3630_REV_ES1_0
;
316 omap_revision
= OMAP3630_REV_ES1_1
;
322 omap_revision
= OMAP3630_REV_ES1_2
;
329 omap_revision
= TI8168_REV_ES1_0
;
335 omap_revision
= TI8168_REV_ES1_1
;
341 /* Unknown default to latest silicon rev as default */
342 omap_revision
= OMAP3630_REV_ES1_2
;
344 pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
348 static void __init
omap4_check_revision(void)
355 * The IC rev detection is done with hawkeye and rev.
356 * Note that rev does not map directly to defined processor
357 * revision numbers as ES1.0 uses value 0.
359 idcode
= read_tap_reg(OMAP_TAP_IDCODE
);
360 hawkeye
= (idcode
>> 12) & 0xffff;
361 rev
= (idcode
>> 28) & 0xf;
364 * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
365 * Use ARM register to detect the correct ES version
367 if (!rev
&& (hawkeye
!= 0xb94e)) {
368 idcode
= read_cpuid(CPUID_ID
);
369 rev
= (idcode
& 0xf) - 1;
376 omap_revision
= OMAP4430_REV_ES1_0
;
380 omap_revision
= OMAP4430_REV_ES2_0
;
386 omap_revision
= OMAP4430_REV_ES2_1
;
390 omap_revision
= OMAP4430_REV_ES2_2
;
397 omap_revision
= OMAP4460_REV_ES1_0
;
402 /* Unknown default to latest silicon rev as default */
403 omap_revision
= OMAP4430_REV_ES2_2
;
406 pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
407 ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
410 #define OMAP3_SHOW_FEATURE(feat) \
411 if (omap3_has_ ##feat()) \
414 static void __init
omap3_cpuinfo(const char *cpu_rev
)
416 const char *cpu_name
;
419 * OMAP3430 and OMAP3530 are assumed to be same.
421 * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
422 * on available features. Upon detection, update the CPU id
423 * and CPU class bits.
425 if (cpu_is_omap3630()) {
426 cpu_name
= "OMAP3630";
427 } else if (cpu_is_omap3517()) {
429 cpu_name
= (omap3_has_sgx()) ? "AM3517" : "AM3505";
430 } else if (cpu_is_ti816x()) {
432 } else if (omap3_has_iva() && omap3_has_sgx()) {
433 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
434 cpu_name
= "OMAP3430/3530";
435 } else if (omap3_has_iva()) {
436 cpu_name
= "OMAP3525";
437 } else if (omap3_has_sgx()) {
438 cpu_name
= "OMAP3515";
440 cpu_name
= "OMAP3503";
443 /* Print verbose information */
444 pr_info("%s ES%s (", cpu_name
, cpu_rev
);
446 OMAP3_SHOW_FEATURE(l2cache
);
447 OMAP3_SHOW_FEATURE(iva
);
448 OMAP3_SHOW_FEATURE(sgx
);
449 OMAP3_SHOW_FEATURE(neon
);
450 OMAP3_SHOW_FEATURE(isp
);
451 OMAP3_SHOW_FEATURE(192mhz_clk
);
457 * Try to detect the exact revision of the omap we're running on
459 void __init
omap2_check_revision(void)
464 * At this point we have an idea about the processor revision set
465 * earlier with omap2_set_globals_tap().
467 if (cpu_is_omap24xx()) {
468 omap24xx_check_revision();
469 } else if (cpu_is_omap34xx()) {
470 omap3_check_revision(&cpu_rev
);
472 /* TI816X doesn't have feature register */
473 if (!cpu_is_ti816x())
474 omap3_check_features();
476 ti816x_check_features();
478 omap3_cpuinfo(cpu_rev
);
480 } else if (cpu_is_omap44xx()) {
481 omap4_check_revision();
482 omap4_check_features();
485 pr_err("OMAP revision unknown, please fix!\n");
490 * Set up things for map_io and processor detection later on. Gets called
491 * pretty much first thing from board init. For multi-omap, this gets
492 * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
493 * detect the exact revision later on in omap2_detect_revision() once map_io
496 void __init
omap2_set_globals_tap(struct omap_globals
*omap2_globals
)
498 omap_revision
= omap2_globals
->class;
499 tap_base
= omap2_globals
->tap
;
501 if (cpu_is_omap34xx())
502 tap_prod_id
= 0x0210;
504 tap_prod_id
= 0x0208;