2 * linux/arch/arm/mach-omap2/id.c
4 * OMAP2 CPU identification code
6 * Copyright (C) 2005 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com>
9 * Copyright (C) 2009-11 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
22 #include <asm/cputype.h>
31 static unsigned int omap_revision
;
32 static const char *cpu_rev
;
35 unsigned int omap_rev(void)
39 EXPORT_SYMBOL(omap_rev
);
45 if (cpu_is_omap24xx()) {
46 val
= omap_ctrl_readl(OMAP24XX_CONTROL_STATUS
);
47 } else if (soc_is_am33xx()) {
48 val
= omap_ctrl_readl(AM33XX_CONTROL_STATUS
);
49 } else if (cpu_is_omap34xx()) {
50 val
= omap_ctrl_readl(OMAP343X_CONTROL_STATUS
);
51 } else if (cpu_is_omap44xx()) {
52 val
= omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS
);
53 } else if (soc_is_omap54xx()) {
54 val
= omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS
);
55 val
&= OMAP5_DEVICETYPE_MASK
;
59 pr_err("Cannot detect omap type!\n");
63 val
&= OMAP2_DEVICETYPE_MASK
;
69 EXPORT_SYMBOL(omap_type
);
72 /*----------------------------------------------------------------------------*/
74 #define OMAP_TAP_IDCODE 0x0204
75 #define OMAP_TAP_DIE_ID_0 0x0218
76 #define OMAP_TAP_DIE_ID_1 0x021C
77 #define OMAP_TAP_DIE_ID_2 0x0220
78 #define OMAP_TAP_DIE_ID_3 0x0224
80 #define OMAP_TAP_DIE_ID_44XX_0 0x0200
81 #define OMAP_TAP_DIE_ID_44XX_1 0x0208
82 #define OMAP_TAP_DIE_ID_44XX_2 0x020c
83 #define OMAP_TAP_DIE_ID_44XX_3 0x0210
85 #define read_tap_reg(reg) __raw_readl(tap_base + (reg))
88 u16 hawkeye
; /* Silicon type (Hawkeye id) */
89 u8 dev
; /* Device type from production_id reg */
90 u32 type
; /* Combined type id copied to omap_revision */
93 /* Register values to detect the OMAP version */
94 static struct omap_id omap_ids
[] __initdata
= {
95 { .hawkeye
= 0xb5d9, .dev
= 0x0, .type
= 0x24200024 },
96 { .hawkeye
= 0xb5d9, .dev
= 0x1, .type
= 0x24201024 },
97 { .hawkeye
= 0xb5d9, .dev
= 0x2, .type
= 0x24202024 },
98 { .hawkeye
= 0xb5d9, .dev
= 0x4, .type
= 0x24220024 },
99 { .hawkeye
= 0xb5d9, .dev
= 0x8, .type
= 0x24230024 },
100 { .hawkeye
= 0xb68a, .dev
= 0x0, .type
= 0x24300024 },
103 static void __iomem
*tap_base
;
104 static u16 tap_prod_id
;
106 void omap_get_die_id(struct omap_die_id
*odi
)
108 if (cpu_is_omap44xx() || soc_is_omap54xx()) {
109 odi
->id_0
= read_tap_reg(OMAP_TAP_DIE_ID_44XX_0
);
110 odi
->id_1
= read_tap_reg(OMAP_TAP_DIE_ID_44XX_1
);
111 odi
->id_2
= read_tap_reg(OMAP_TAP_DIE_ID_44XX_2
);
112 odi
->id_3
= read_tap_reg(OMAP_TAP_DIE_ID_44XX_3
);
116 odi
->id_0
= read_tap_reg(OMAP_TAP_DIE_ID_0
);
117 odi
->id_1
= read_tap_reg(OMAP_TAP_DIE_ID_1
);
118 odi
->id_2
= read_tap_reg(OMAP_TAP_DIE_ID_2
);
119 odi
->id_3
= read_tap_reg(OMAP_TAP_DIE_ID_3
);
122 void __init
omap2xxx_check_revision(void)
128 struct omap_die_id odi
;
130 idcode
= read_tap_reg(OMAP_TAP_IDCODE
);
131 prod_id
= read_tap_reg(tap_prod_id
);
132 hawkeye
= (idcode
>> 12) & 0xffff;
133 rev
= (idcode
>> 28) & 0x0f;
134 dev_type
= (prod_id
>> 16) & 0x0f;
135 omap_get_die_id(&odi
);
137 pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
138 idcode
, rev
, hawkeye
, (idcode
>> 1) & 0x7ff);
139 pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi
.id_0
);
140 pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
141 odi
.id_1
, (odi
.id_1
>> 28) & 0xf);
142 pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi
.id_2
);
143 pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi
.id_3
);
144 pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
147 /* Check hawkeye ids */
148 for (i
= 0; i
< ARRAY_SIZE(omap_ids
); i
++) {
149 if (hawkeye
== omap_ids
[i
].hawkeye
)
153 if (i
== ARRAY_SIZE(omap_ids
)) {
154 printk(KERN_ERR
"Unknown OMAP CPU id\n");
158 for (j
= i
; j
< ARRAY_SIZE(omap_ids
); j
++) {
159 if (dev_type
== omap_ids
[j
].dev
)
163 if (j
== ARRAY_SIZE(omap_ids
)) {
164 printk(KERN_ERR
"Unknown OMAP device type. "
165 "Handling it as OMAP%04x\n",
166 omap_ids
[i
].type
>> 16);
170 pr_info("OMAP%04x", omap_rev() >> 16);
171 if ((omap_rev() >> 8) & 0x0f)
172 pr_info("ES%x", (omap_rev() >> 12) & 0xf);
176 #define OMAP3_SHOW_FEATURE(feat) \
177 if (omap3_has_ ##feat()) \
180 static void __init
omap3_cpuinfo(void)
182 const char *cpu_name
;
185 * OMAP3430 and OMAP3530 are assumed to be same.
187 * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
188 * on available features. Upon detection, update the CPU id
189 * and CPU class bits.
191 if (cpu_is_omap3630()) {
192 cpu_name
= "OMAP3630";
193 } else if (soc_is_am35xx()) {
194 cpu_name
= (omap3_has_sgx()) ? "AM3517" : "AM3505";
195 } else if (cpu_is_ti816x()) {
197 } else if (soc_is_am335x()) {
199 } else if (cpu_is_ti814x()) {
201 } else if (omap3_has_iva() && omap3_has_sgx()) {
202 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
203 cpu_name
= "OMAP3430/3530";
204 } else if (omap3_has_iva()) {
205 cpu_name
= "OMAP3525";
206 } else if (omap3_has_sgx()) {
207 cpu_name
= "OMAP3515";
209 cpu_name
= "OMAP3503";
212 /* Print verbose information */
213 pr_info("%s ES%s (", cpu_name
, cpu_rev
);
215 OMAP3_SHOW_FEATURE(l2cache
);
216 OMAP3_SHOW_FEATURE(iva
);
217 OMAP3_SHOW_FEATURE(sgx
);
218 OMAP3_SHOW_FEATURE(neon
);
219 OMAP3_SHOW_FEATURE(isp
);
220 OMAP3_SHOW_FEATURE(192mhz_clk
);
225 #define OMAP3_CHECK_FEATURE(status,feat) \
226 if (((status & OMAP3_ ##feat## _MASK) \
227 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \
228 omap_features |= OMAP3_HAS_ ##feat; \
231 void __init
omap3xxx_check_features(void)
237 status
= omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS
);
239 OMAP3_CHECK_FEATURE(status
, L2CACHE
);
240 OMAP3_CHECK_FEATURE(status
, IVA
);
241 OMAP3_CHECK_FEATURE(status
, SGX
);
242 OMAP3_CHECK_FEATURE(status
, NEON
);
243 OMAP3_CHECK_FEATURE(status
, ISP
);
244 if (cpu_is_omap3630())
245 omap_features
|= OMAP3_HAS_192MHZ_CLK
;
246 if (cpu_is_omap3430() || cpu_is_omap3630())
247 omap_features
|= OMAP3_HAS_IO_WAKEUP
;
248 if (cpu_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1
||
249 omap_rev() == OMAP3430_REV_ES3_1_2
)
250 omap_features
|= OMAP3_HAS_IO_CHAIN_CTRL
;
252 omap_features
|= OMAP3_HAS_SDRC
;
256 * - The am35x Chip ID register has bits 12, 7:5, and 3:2 marked as
257 * reserved and therefore return 0 when read. Unfortunately,
258 * OMAP3_CHECK_FEATURE() will interpret some of those zeroes to
259 * mean that a feature is present even though it isn't so clear
260 * the incorrectly set feature bits.
263 omap_features
&= ~(OMAP3_HAS_IVA
| OMAP3_HAS_ISP
);
266 * TODO: Get additional info (where applicable)
267 * e.g. Size of L2 cache.
273 void __init
omap4xxx_check_features(void)
277 if (cpu_is_omap443x())
278 omap_features
|= OMAP4_HAS_MPU_1GHZ
;
281 if (cpu_is_omap446x()) {
283 read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1
);
284 switch ((si_type
& (3 << 16)) >> 16) {
286 /* High performance device */
287 omap_features
|= OMAP4_HAS_MPU_1_5GHZ
;
291 /* Standard device */
292 omap_features
|= OMAP4_HAS_MPU_1_2GHZ
;
298 void __init
ti81xx_check_features(void)
300 omap_features
= OMAP3_HAS_NEON
;
304 void __init
omap3xxx_check_revision(void)
311 * We cannot access revision registers on ES1.0.
312 * If the processor type is Cortex-A8 and the revision is 0x0
313 * it means its Cortex r0p0 which is 3430 ES1.0.
315 cpuid
= read_cpuid(CPUID_ID
);
316 if ((((cpuid
>> 4) & 0xfff) == 0xc08) && ((cpuid
& 0xf) == 0x0)) {
317 omap_revision
= OMAP3430_REV_ES1_0
;
323 * Detection for 34xx ES2.0 and above can be done with just
324 * hawkeye and rev. See TRM 1.5.2 Device Identification.
325 * Note that rev does not map directly to our defined processor
326 * revision numbers as ES1.0 uses value 0.
328 idcode
= read_tap_reg(OMAP_TAP_IDCODE
);
329 hawkeye
= (idcode
>> 12) & 0xffff;
330 rev
= (idcode
>> 28) & 0xff;
334 /* Handle 34xx/35xx devices */
336 case 0: /* Take care of early samples */
338 omap_revision
= OMAP3430_REV_ES2_0
;
342 omap_revision
= OMAP3430_REV_ES2_1
;
346 omap_revision
= OMAP3430_REV_ES3_0
;
350 omap_revision
= OMAP3430_REV_ES3_1
;
356 /* Use the latest known revision as default */
357 omap_revision
= OMAP3430_REV_ES3_1_2
;
363 * Handle OMAP/AM 3505/3517 devices
365 * Set the device to be OMAP3517 here. Actual device
366 * is identified later based on the features.
370 omap_revision
= AM35XX_REV_ES1_0
;
376 omap_revision
= AM35XX_REV_ES1_1
;
381 /* Handle 36xx devices */
384 case 0: /* Take care of early samples */
385 omap_revision
= OMAP3630_REV_ES1_0
;
389 omap_revision
= OMAP3630_REV_ES1_1
;
395 omap_revision
= OMAP3630_REV_ES1_2
;
402 omap_revision
= TI8168_REV_ES1_0
;
408 omap_revision
= TI8168_REV_ES1_1
;
414 omap_revision
= AM335X_REV_ES1_0
;
422 omap_revision
= TI8148_REV_ES1_0
;
426 omap_revision
= TI8148_REV_ES2_0
;
432 omap_revision
= TI8148_REV_ES2_1
;
438 /* Unknown default to latest silicon rev as default */
439 omap_revision
= OMAP3630_REV_ES1_2
;
441 pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
445 void __init
omap4xxx_check_revision(void)
452 * The IC rev detection is done with hawkeye and rev.
453 * Note that rev does not map directly to defined processor
454 * revision numbers as ES1.0 uses value 0.
456 idcode
= read_tap_reg(OMAP_TAP_IDCODE
);
457 hawkeye
= (idcode
>> 12) & 0xffff;
458 rev
= (idcode
>> 28) & 0xf;
461 * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
462 * Use ARM register to detect the correct ES version
464 if (!rev
&& (hawkeye
!= 0xb94e) && (hawkeye
!= 0xb975)) {
465 idcode
= read_cpuid(CPUID_ID
);
466 rev
= (idcode
& 0xf) - 1;
473 omap_revision
= OMAP4430_REV_ES1_0
;
477 omap_revision
= OMAP4430_REV_ES2_0
;
483 omap_revision
= OMAP4430_REV_ES2_1
;
486 omap_revision
= OMAP4430_REV_ES2_2
;
490 omap_revision
= OMAP4430_REV_ES2_3
;
496 omap_revision
= OMAP4460_REV_ES1_0
;
500 omap_revision
= OMAP4460_REV_ES1_1
;
508 omap_revision
= OMAP4470_REV_ES1_0
;
513 /* Unknown default to latest silicon rev as default */
514 omap_revision
= OMAP4430_REV_ES2_3
;
517 pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
518 ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
521 void __init
omap5xxx_check_revision(void)
527 idcode
= read_tap_reg(OMAP_TAP_IDCODE
);
528 hawkeye
= (idcode
>> 12) & 0xffff;
529 rev
= (idcode
>> 28) & 0xff;
535 omap_revision
= OMAP5430_REV_ES1_0
;
543 omap_revision
= OMAP5432_REV_ES1_0
;
548 /* Unknown default to latest silicon rev as default*/
549 omap_revision
= OMAP5430_REV_ES1_0
;
552 pr_info("OMAP%04x ES%d.0\n",
553 omap_rev() >> 16, ((omap_rev() >> 12) & 0xf));
557 * Set up things for map_io and processor detection later on. Gets called
558 * pretty much first thing from board init. For multi-omap, this gets
559 * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
560 * detect the exact revision later on in omap2_detect_revision() once map_io
563 void __init
omap2_set_globals_tap(struct omap_globals
*omap2_globals
)
565 omap_revision
= omap2_globals
->class;
566 tap_base
= omap2_globals
->tap
;
568 if (cpu_is_omap34xx())
569 tap_prod_id
= 0x0210;
571 tap_prod_id
= 0x0208;