arch/arm/mach-omap2/irq.c

   1 /*
   2  * linux/arch/arm/mach-omap2/irq.c
   3  *
   4  * Interrupt handler for OMAP2 boards.
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Author: Paul Mundt <paul.mundt@nokia.com>
   8  *
   9  * This file is subject to the terms and conditions of the GNU General Public
  10  * License. See the file "COPYING" in the main directory of this archive
  11  * for more details.
  12  */
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18
  19 #include <asm/exception.h>
  20 #include <asm/mach/irq.h>
  21 #include <linux/irqdomain.h>
  22 #include <linux/of.h>
  23 #include <linux/of_address.h>
  24 #include <linux/of_irq.h>
  25
  26 #include "soc.h"
  27 #include "iomap.h"
  28 #include "common.h"
  29 #include "../../drivers/irqchip/irqchip.h"
  30
  31 /* selected INTC register offsets */
  32
  33 #define INTC_REVISION           0x0000
  34 #define INTC_SYSCONFIG          0x0010
  35 #define INTC_SYSSTATUS          0x0014
  36 #define INTC_SIR                0x0040
  37 #define INTC_CONTROL            0x0048
  38 #define INTC_PROTECTION         0x004C
  39 #define INTC_IDLE               0x0050
  40 #define INTC_THRESHOLD          0x0068
  41 #define INTC_MIR0               0x0084
  42 #define INTC_MIR_CLEAR0         0x0088
  43 #define INTC_MIR_SET0           0x008c
  44 #define INTC_PENDING_IRQ0       0x0098
  45 #define INTC_PENDING_IRQ1       0x00b8
  46 #define INTC_PENDING_IRQ2       0x00d8
  47 #define INTC_PENDING_IRQ3       0x00f8
  48 #define INTC_ILR0               0x0100
  49
  50 #define ACTIVEIRQ_MASK          0x7f    /* omap2/3 active interrupt bits */
  51 #define INTCPS_NR_ILR_REGS      128
  52 #define INTCPS_NR_MIR_REGS      3
  53
  54 /*
  55  * OMAP2 has a number of different interrupt controllers, each interrupt
  56  * controller is identified as its own "bank". Register definitions are
  57  * fairly consistent for each bank, but not all registers are implemented
  58  * for each bank.. when in doubt, consult the TRM.
  59  */
  60
  61 /* Structure to save interrupt controller context */
  62 struct omap_intc_regs {
  63         u32 sysconfig;
  64         u32 protection;
  65         u32 idle;
  66         u32 threshold;
  67         u32 ilr[INTCPS_NR_ILR_REGS];
  68         u32 mir[INTCPS_NR_MIR_REGS];
  69 };
  70 static struct omap_intc_regs intc_context;
  71
  72 static struct irq_domain *domain;
  73 static void __iomem *omap_irq_base;
  74 static int omap_nr_irqs = 96;
  75
  76 /* INTC bank register get/set */
  77 static void intc_writel(u32 reg, u32 val)
  78 {
  79         writel_relaxed(val, omap_irq_base + reg);
  80 }
  81
  82 static u32 intc_readl(u32 reg)
  83 {
  84         return readl_relaxed(omap_irq_base + reg);
  85 }
  86
  87 void omap_intc_save_context(void)
  88 {
  89         int i;
  90
  91         intc_context.sysconfig =
  92                 intc_readl(INTC_SYSCONFIG);
  93         intc_context.protection =
  94                 intc_readl(INTC_PROTECTION);
  95         intc_context.idle =
  96                 intc_readl(INTC_IDLE);
  97         intc_context.threshold =
  98                 intc_readl(INTC_THRESHOLD);
  99
 100         for (i = 0; i < omap_nr_irqs; i++)
 101                 intc_context.ilr[i] =
 102                         intc_readl((INTC_ILR0 + 0x4 * i));
 103         for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
 104                 intc_context.mir[i] =
 105                         intc_readl(INTC_MIR0 + (0x20 * i));
 106 }
 107
 108 void omap_intc_restore_context(void)
 109 {
 110         int i;
 111
 112         intc_writel(INTC_SYSCONFIG, intc_context.sysconfig);
 113         intc_writel(INTC_PROTECTION, intc_context.protection);
 114         intc_writel(INTC_IDLE, intc_context.idle);
 115         intc_writel(INTC_THRESHOLD, intc_context.threshold);
 116
 117         for (i = 0; i < omap_nr_irqs; i++)
 118                 intc_writel(INTC_ILR0 + 0x4 * i,
 119                                 intc_context.ilr[i]);
 120
 121         for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
 122                 intc_writel(INTC_MIR0 + 0x20 * i,
 123                         intc_context.mir[i]);
 124         /* MIRs are saved and restore with other PRCM registers */
 125 }
 126
 127 void omap3_intc_prepare_idle(void)
 128 {
 129         /*
 130          * Disable autoidle as it can stall interrupt controller,
 131          * cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
 132          */
 133         intc_writel(INTC_SYSCONFIG, 0);
 134 }
 135
 136 void omap3_intc_resume_idle(void)
 137 {
 138         /* Re-enable autoidle */
 139         intc_writel(INTC_SYSCONFIG, 1);
 140 }
 141
 142 /* XXX: FIQ and additional INTC support (only MPU at the moment) */
 143 static void omap_ack_irq(struct irq_data *d)
 144 {
 145         intc_writel(INTC_CONTROL, 0x1);
 146 }
 147
 148 static void omap_mask_ack_irq(struct irq_data *d)
 149 {
 150         irq_gc_mask_disable_reg(d);
 151         omap_ack_irq(d);
 152 }
 153
 154 static void __init omap_irq_soft_reset(void)
 155 {
 156         unsigned long tmp;
 157
 158         tmp = intc_readl(INTC_REVISION) & 0xff;
 159
 160         pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n",
 161                 omap_irq_base, tmp >> 4, tmp & 0xf, omap_nr_irqs);
 162
 163         tmp = intc_readl(INTC_SYSCONFIG);
 164         tmp |= 1 << 1;  /* soft reset */
 165         intc_writel(INTC_SYSCONFIG, tmp);
 166
 167         while (!(intc_readl(INTC_SYSSTATUS) & 0x1))
 168                 /* Wait for reset to complete */;
 169
 170         /* Enable autoidle */
 171         intc_writel(INTC_SYSCONFIG, 1 << 0);
 172 }
 173
 174 int omap_irq_pending(void)
 175 {
 176         int irq;
 177
 178         for (irq = 0; irq < omap_nr_irqs; irq += 32)
 179                 if (intc_readl(INTC_PENDING_IRQ0 +
 180                                         ((irq >> 5) << 5)))
 181                         return 1;
 182         return 0;
 183 }
 184
 185 void omap3_intc_suspend(void)
 186 {
 187         /* A pending interrupt would prevent OMAP from entering suspend */
 188         omap_ack_irq(NULL);
 189 }
 190
 191 static __init void
 192 omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
 193 {
 194         struct irq_chip_generic *gc;
 195         struct irq_chip_type *ct;
 196
 197         gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
 198                                         handle_level_irq);
 199         ct = gc->chip_types;
 200         ct->chip.irq_ack = omap_mask_ack_irq;
 201         ct->chip.irq_mask = irq_gc_mask_disable_reg;
 202         ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
 203         ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;
 204
 205         ct->regs.enable = INTC_MIR_CLEAR0;
 206         ct->regs.disable = INTC_MIR_SET0;
 207         irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
 208                                 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
 209 }
 210
 211 static void __init omap_init_irq(u32 base, int nr_irqs,
 212                                  struct device_node *node)
 213 {
 214         int j, irq_base;
 215
 216         omap_irq_base = ioremap(base, SZ_4K);
 217         if (WARN_ON(!omap_irq_base))
 218                 return;
 219
 220         omap_nr_irqs = nr_irqs;
 221
 222         irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
 223         if (irq_base < 0) {
 224                 pr_warn("Couldn't allocate IRQ numbers\n");
 225                 irq_base = 0;
 226         }
 227
 228         domain = irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
 229                         &irq_domain_simple_ops, NULL);
 230
 231         omap_irq_soft_reset();
 232
 233         for (j = 0; j < omap_nr_irqs; j += 32)
 234                 omap_alloc_gc(omap_irq_base + j, j + irq_base, 32);
 235 }
 236
 237 void __init omap2_init_irq(void)
 238 {
 239         omap_init_irq(OMAP24XX_IC_BASE, 96, NULL);
 240 }
 241
 242 void __init omap3_init_irq(void)
 243 {
 244         omap_init_irq(OMAP34XX_IC_BASE, 96, NULL);
 245 }
 246
 247 void __init ti81xx_init_irq(void)
 248 {
 249         omap_init_irq(OMAP34XX_IC_BASE, 128, NULL);
 250 }
 251
 252 static inline void omap_intc_handle_irq(struct pt_regs *regs)
 253 {
 254         u32 irqnr;
 255         int handled_irq = 0;
 256
 257         do {
 258                 irqnr = intc_readl(INTC_PENDING_IRQ0);
 259                 if (irqnr)
 260                         goto out;
 261
 262                 irqnr = intc_readl(INTC_PENDING_IRQ1);
 263                 if (irqnr)
 264                         goto out;
 265
 266                 irqnr = intc_readl(INTC_PENDING_IRQ2);
 267 #if IS_ENABLED(CONFIG_SOC_TI81XX) || IS_ENABLED(CONFIG_SOC_AM33XX)
 268                 if (irqnr)
 269                         goto out;
 270                 irqnr = intc_readl(INTC_PENDING_IRQ3);
 271 #endif
 272
 273 out:
 274                 if (!irqnr)
 275                         break;
 276
 277                 irqnr = intc_readl(INTC_SIR);
 278                 irqnr &= ACTIVEIRQ_MASK;
 279
 280                 if (irqnr) {
 281                         irqnr = irq_find_mapping(domain, irqnr);
 282                         handle_IRQ(irqnr, regs);
 283                         handled_irq = 1;
 284                 }
 285         } while (irqnr);
 286
 287         /* If an irq is masked or deasserted while active, we will
 288          * keep ending up here with no irq handled. So remove it from
 289          * the INTC with an ack.*/
 290         if (!handled_irq)
 291                 omap_ack_irq(NULL);
 292 }
 293
 294 asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs)
 295 {
 296         omap_intc_handle_irq(regs);
 297 }
 298
 299 static int __init intc_of_init(struct device_node *node,
 300                              struct device_node *parent)
 301 {
 302         struct resource res;
 303         u32 nr_irq = 96;
 304
 305         if (WARN_ON(!node))
 306                 return -ENODEV;
 307
 308         if (of_address_to_resource(node, 0, &res)) {
 309                 WARN(1, "unable to get intc registers\n");
 310                 return -EINVAL;
 311         }
 312
 313         if (of_property_read_u32(node, "ti,intc-size", &nr_irq))
 314                 pr_warn("unable to get intc-size, default to %d\n", nr_irq);
 315
 316         omap_init_irq(res.start, nr_irq, of_node_get(node));
 317
 318         set_handle_irq(omap2_intc_handle_irq);
 319
 320         return 0;
 321 }
 322
 323 IRQCHIP_DECLARE(omap2_intc, "ti,omap2-intc", intc_of_init);
 324 IRQCHIP_DECLARE(omap3_intc, "ti,omap3-intc", intc_of_init);
 325 IRQCHIP_DECLARE(am33xx_intc, "ti,am33xx-intc", intc_of_init);
 326
 327 asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs)
 328 {
 329         omap_intc_handle_irq(regs);
 330 }