arch/arm/mach-omap2/irq.c

   1 /*
   2  * linux/arch/arm/mach-omap2/irq.c
   3  *
   4  * Interrupt handler for OMAP2 boards.
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Author: Paul Mundt <paul.mundt@nokia.com>
   8  *
   9  * This file is subject to the terms and conditions of the GNU General Public
  10  * License. See the file "COPYING" in the main directory of this archive
  11  * for more details.
  12  */
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18
  19 #include <asm/exception.h>
  20 #include <asm/mach/irq.h>
  21 #include <linux/irqdomain.h>
  22 #include <linux/of.h>
  23 #include <linux/of_address.h>
  24 #include <linux/of_irq.h>
  25
  26 #include "soc.h"
  27 #include "iomap.h"
  28 #include "common.h"
  29
  30 /* selected INTC register offsets */
  31
  32 #define INTC_REVISION           0x0000
  33 #define INTC_SYSCONFIG          0x0010
  34 #define INTC_SYSSTATUS          0x0014
  35 #define INTC_SIR                0x0040
  36 #define INTC_CONTROL            0x0048
  37 #define INTC_PROTECTION         0x004C
  38 #define INTC_IDLE               0x0050
  39 #define INTC_THRESHOLD          0x0068
  40 #define INTC_MIR0               0x0084
  41 #define INTC_MIR_CLEAR0         0x0088
  42 #define INTC_MIR_SET0           0x008c
  43 #define INTC_PENDING_IRQ0       0x0098
  44 #define INTC_ILR0               0x0100
  45 /* Number of IRQ state bits in each MIR register */
  46 #define IRQ_BITS_PER_REG        32
  47
  48 #define OMAP2_IRQ_BASE          OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
  49 #define OMAP3_IRQ_BASE          OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
  50 #define INTCPS_SIR_IRQ_OFFSET   0x0040  /* omap2/3 active interrupt offset */
  51 #define ACTIVEIRQ_MASK          0x7f    /* omap2/3 active interrupt bits */
  52 #define INTCPS_NR_MIR_REGS      3
  53 #define INTCPS_NR_IRQS          96
  54
  55 /*
  56  * OMAP2 has a number of different interrupt controllers, each interrupt
  57  * controller is identified as its own "bank". Register definitions are
  58  * fairly consistent for each bank, but not all registers are implemented
  59  * for each bank.. when in doubt, consult the TRM.
  60  */
  61 static struct omap_irq_bank {
  62         void __iomem *base_reg;
  63         unsigned int nr_irqs;
  64 } __attribute__ ((aligned(4))) irq_banks[] = {
  65         {
  66                 /* MPU INTC */
  67                 .nr_irqs        = 96,
  68         },
  69 };
  70
  71 static struct irq_domain *domain;
  72 static void __iomem *omap_irq_base;
  73
  74 /* Structure to save interrupt controller context */
  75 struct omap3_intc_regs {
  76         u32 sysconfig;
  77         u32 protection;
  78         u32 idle;
  79         u32 threshold;
  80         u32 ilr[INTCPS_NR_IRQS];
  81         u32 mir[INTCPS_NR_MIR_REGS];
  82 };
  83
  84 /* INTC bank register get/set */
  85
  86 static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
  87 {
  88         writel_relaxed(val, bank->base_reg + reg);
  89 }
  90
  91 static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
  92 {
  93         return readl_relaxed(bank->base_reg + reg);
  94 }
  95
  96 /* XXX: FIQ and additional INTC support (only MPU at the moment) */
  97 static void omap_ack_irq(struct irq_data *d)
  98 {
  99         intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
 100 }
 101
 102 static void omap_mask_ack_irq(struct irq_data *d)
 103 {
 104         irq_gc_mask_disable_reg(d);
 105         omap_ack_irq(d);
 106 }
 107
 108 static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
 109 {
 110         unsigned long tmp;
 111
 112         tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
 113         pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n",
 114                 bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
 115
 116         tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
 117         tmp |= 1 << 1;  /* soft reset */
 118         intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);
 119
 120         while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
 121                 /* Wait for reset to complete */;
 122
 123         /* Enable autoidle */
 124         intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
 125 }
 126
 127 int omap_irq_pending(void)
 128 {
 129         int i;
 130
 131         for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
 132                 struct omap_irq_bank *bank = irq_banks + i;
 133                 int irq;
 134
 135                 for (irq = 0; irq < bank->nr_irqs; irq += 32)
 136                         if (intc_bank_read_reg(bank, INTC_PENDING_IRQ0 +
 137                                                ((irq >> 5) << 5)))
 138                                 return 1;
 139         }
 140         return 0;
 141 }
 142
 143 static __init void
 144 omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
 145 {
 146         struct irq_chip_generic *gc;
 147         struct irq_chip_type *ct;
 148
 149         gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
 150                                         handle_level_irq);
 151         ct = gc->chip_types;
 152         ct->chip.irq_ack = omap_mask_ack_irq;
 153         ct->chip.irq_mask = irq_gc_mask_disable_reg;
 154         ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
 155         ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;
 156
 157         ct->regs.enable = INTC_MIR_CLEAR0;
 158         ct->regs.disable = INTC_MIR_SET0;
 159         irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
 160                                 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
 161 }
 162
 163 static void __init omap_init_irq(u32 base, int nr_irqs,
 164                                  struct device_node *node)
 165 {
 166         unsigned long nr_of_irqs = 0;
 167         unsigned int nr_banks = 0;
 168         int i, j, irq_base;
 169
 170         omap_irq_base = ioremap(base, SZ_4K);
 171         if (WARN_ON(!omap_irq_base))
 172                 return;
 173
 174         irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
 175         if (irq_base < 0) {
 176                 pr_warn("Couldn't allocate IRQ numbers\n");
 177                 irq_base = 0;
 178         }
 179
 180         domain = irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
 181                                        &irq_domain_simple_ops, NULL);
 182
 183         for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
 184                 struct omap_irq_bank *bank = irq_banks + i;
 185
 186                 bank->nr_irqs = nr_irqs;
 187
 188                 /* Static mapping, never released */
 189                 bank->base_reg = ioremap(base, SZ_4K);
 190                 if (!bank->base_reg) {
 191                         pr_err("Could not ioremap irq bank%i\n", i);
 192                         continue;
 193                 }
 194
 195                 omap_irq_bank_init_one(bank);
 196
 197                 for (j = 0; j < bank->nr_irqs; j += 32)
 198                         omap_alloc_gc(bank->base_reg + j, j + irq_base, 32);
 199
 200                 nr_of_irqs += bank->nr_irqs;
 201                 nr_banks++;
 202         }
 203
 204         pr_info("Total of %ld interrupts on %d active controller%s\n",
 205                 nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
 206 }
 207
 208 void __init omap2_init_irq(void)
 209 {
 210         omap_init_irq(OMAP24XX_IC_BASE, 96, NULL);
 211 }
 212
 213 void __init omap3_init_irq(void)
 214 {
 215         omap_init_irq(OMAP34XX_IC_BASE, 96, NULL);
 216 }
 217
 218 void __init ti81xx_init_irq(void)
 219 {
 220         omap_init_irq(OMAP34XX_IC_BASE, 128, NULL);
 221 }
 222
 223 static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs)
 224 {
 225         u32 irqnr;
 226         int handled_irq = 0;
 227
 228         do {
 229                 irqnr = readl_relaxed(base_addr + 0x98);
 230                 if (irqnr)
 231                         goto out;
 232
 233                 irqnr = readl_relaxed(base_addr + 0xb8);
 234                 if (irqnr)
 235                         goto out;
 236
 237                 irqnr = readl_relaxed(base_addr + 0xd8);
 238 #if IS_ENABLED(CONFIG_SOC_TI81XX) || IS_ENABLED(CONFIG_SOC_AM33XX)
 239                 if (irqnr)
 240                         goto out;
 241                 irqnr = readl_relaxed(base_addr + 0xf8);
 242 #endif
 243
 244 out:
 245                 if (!irqnr)
 246                         break;
 247
 248                 irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);
 249                 irqnr &= ACTIVEIRQ_MASK;
 250
 251                 if (irqnr) {
 252                         irqnr = irq_find_mapping(domain, irqnr);
 253                         handle_IRQ(irqnr, regs);
 254                         handled_irq = 1;
 255                 }
 256         } while (irqnr);
 257
 258         /* If an irq is masked or deasserted while active, we will
 259          * keep ending up here with no irq handled. So remove it from
 260          * the INTC with an ack.*/
 261         if (!handled_irq)
 262                 omap_ack_irq(NULL);
 263 }
 264
 265 asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs)
 266 {
 267         void __iomem *base_addr = OMAP2_IRQ_BASE;
 268         omap_intc_handle_irq(base_addr, regs);
 269 }
 270
 271 int __init intc_of_init(struct device_node *node,
 272                              struct device_node *parent)
 273 {
 274         struct resource res;
 275         u32 nr_irq = 96;
 276
 277         if (WARN_ON(!node))
 278                 return -ENODEV;
 279
 280         if (of_address_to_resource(node, 0, &res)) {
 281                 WARN(1, "unable to get intc registers\n");
 282                 return -EINVAL;
 283         }
 284
 285         if (of_property_read_u32(node, "ti,intc-size", &nr_irq))
 286                 pr_warn("unable to get intc-size, default to %d\n", nr_irq);
 287
 288         omap_init_irq(res.start, nr_irq, of_node_get(node));
 289
 290         return 0;
 291 }
 292
 293 static const struct of_device_id irq_match[] __initconst = {
 294         { .compatible = "ti,omap2-intc", .data = intc_of_init, },
 295         { }
 296 };
 297
 298 void __init omap_intc_of_init(void)
 299 {
 300         of_irq_init(irq_match);
 301 }
 302
 303 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
 304 static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
 305
 306 void omap_intc_save_context(void)
 307 {
 308         int ind = 0, i = 0;
 309         for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
 310                 struct omap_irq_bank *bank = irq_banks + ind;
 311                 intc_context[ind].sysconfig =
 312                         intc_bank_read_reg(bank, INTC_SYSCONFIG);
 313                 intc_context[ind].protection =
 314                         intc_bank_read_reg(bank, INTC_PROTECTION);
 315                 intc_context[ind].idle =
 316                         intc_bank_read_reg(bank, INTC_IDLE);
 317                 intc_context[ind].threshold =
 318                         intc_bank_read_reg(bank, INTC_THRESHOLD);
 319                 for (i = 0; i < INTCPS_NR_IRQS; i++)
 320                         intc_context[ind].ilr[i] =
 321                                 intc_bank_read_reg(bank, (0x100 + 0x4*i));
 322                 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
 323                         intc_context[ind].mir[i] =
 324                                 intc_bank_read_reg(&irq_banks[0], INTC_MIR0 +
 325                                 (0x20 * i));
 326         }
 327 }
 328
 329 void omap_intc_restore_context(void)
 330 {
 331         int ind = 0, i = 0;
 332
 333         for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
 334                 struct omap_irq_bank *bank = irq_banks + ind;
 335                 intc_bank_write_reg(intc_context[ind].sysconfig,
 336                                         bank, INTC_SYSCONFIG);
 337                 intc_bank_write_reg(intc_context[ind].sysconfig,
 338                                         bank, INTC_SYSCONFIG);
 339                 intc_bank_write_reg(intc_context[ind].protection,
 340                                         bank, INTC_PROTECTION);
 341                 intc_bank_write_reg(intc_context[ind].idle,
 342                                         bank, INTC_IDLE);
 343                 intc_bank_write_reg(intc_context[ind].threshold,
 344                                         bank, INTC_THRESHOLD);
 345                 for (i = 0; i < INTCPS_NR_IRQS; i++)
 346                         intc_bank_write_reg(intc_context[ind].ilr[i],
 347                                 bank, (0x100 + 0x4*i));
 348                 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
 349                         intc_bank_write_reg(intc_context[ind].mir[i],
 350                                  &irq_banks[0], INTC_MIR0 + (0x20 * i));
 351         }
 352         /* MIRs are saved and restore with other PRCM registers */
 353 }
 354
 355 void omap3_intc_suspend(void)
 356 {
 357         /* A pending interrupt would prevent OMAP from entering suspend */
 358         omap_ack_irq(NULL);
 359 }
 360
 361 void omap3_intc_prepare_idle(void)
 362 {
 363         /*
 364          * Disable autoidle as it can stall interrupt controller,
 365          * cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
 366          */
 367         intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG);
 368 }
 369
 370 void omap3_intc_resume_idle(void)
 371 {
 372         /* Re-enable autoidle */
 373         intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
 374 }
 375
 376 asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs)
 377 {
 378         void __iomem *base_addr = OMAP3_IRQ_BASE;
 379         omap_intc_handle_irq(base_addr, regs);
 380 }
 381 #endif /* CONFIG_ARCH_OMAP3 */