2 * Mailbox reservation modules for OMAP2/3
4 * Copyright (C) 2006-2009 Nokia Corporation
5 * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
13 #include <linux/module.h>
14 #include <linux/clk.h>
15 #include <linux/err.h>
16 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
21 #include <plat/mailbox.h>
23 #define MAILBOX_REVISION 0x000
24 #define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
25 #define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
26 #define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
27 #define MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
28 #define MAILBOX_IRQENABLE(u) (0x104 + 8 * (u))
30 #define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 0x10 * (u))
31 #define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 0x10 * (u))
32 #define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 0x10 * (u))
34 #define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m)))
35 #define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))
37 #define MBOX_REG_SIZE 0x120
39 #define OMAP4_MBOX_REG_SIZE 0x130
41 #define MBOX_NR_REGS (MBOX_REG_SIZE / sizeof(u32))
42 #define OMAP4_MBOX_NR_REGS (OMAP4_MBOX_REG_SIZE / sizeof(u32))
44 static void __iomem
*mbox_base
;
46 struct omap_mbox2_fifo
{
48 unsigned long fifo_stat
;
49 unsigned long msg_stat
;
52 struct omap_mbox2_priv
{
53 struct omap_mbox2_fifo tx_fifo
;
54 struct omap_mbox2_fifo rx_fifo
;
55 unsigned long irqenable
;
56 unsigned long irqstatus
;
59 u32 ctx
[OMAP4_MBOX_NR_REGS
];
60 unsigned long irqdisable
;
63 static void omap2_mbox_enable_irq(struct omap_mbox
*mbox
,
64 omap_mbox_type_t irq
);
66 static inline unsigned int mbox_read_reg(size_t ofs
)
68 return __raw_readl(mbox_base
+ ofs
);
71 static inline void mbox_write_reg(u32 val
, size_t ofs
)
73 __raw_writel(val
, mbox_base
+ ofs
);
76 /* Mailbox H/W preparations */
77 static int omap2_mbox_startup(struct omap_mbox
*mbox
)
81 pm_runtime_enable(mbox
->dev
->parent
);
82 pm_runtime_get_sync(mbox
->dev
->parent
);
84 l
= mbox_read_reg(MAILBOX_REVISION
);
85 pr_debug("omap mailbox rev %d.%d\n", (l
& 0xf0) >> 4, (l
& 0x0f));
90 static void omap2_mbox_shutdown(struct omap_mbox
*mbox
)
92 pm_runtime_put_sync(mbox
->dev
->parent
);
93 pm_runtime_disable(mbox
->dev
->parent
);
96 /* Mailbox FIFO handle functions */
97 static mbox_msg_t
omap2_mbox_fifo_read(struct omap_mbox
*mbox
)
99 struct omap_mbox2_fifo
*fifo
=
100 &((struct omap_mbox2_priv
*)mbox
->priv
)->rx_fifo
;
101 return (mbox_msg_t
) mbox_read_reg(fifo
->msg
);
104 static void omap2_mbox_fifo_write(struct omap_mbox
*mbox
, mbox_msg_t msg
)
106 struct omap_mbox2_fifo
*fifo
=
107 &((struct omap_mbox2_priv
*)mbox
->priv
)->tx_fifo
;
108 mbox_write_reg(msg
, fifo
->msg
);
111 static int omap2_mbox_fifo_empty(struct omap_mbox
*mbox
)
113 struct omap_mbox2_fifo
*fifo
=
114 &((struct omap_mbox2_priv
*)mbox
->priv
)->rx_fifo
;
115 return (mbox_read_reg(fifo
->msg_stat
) == 0);
118 static int omap2_mbox_fifo_full(struct omap_mbox
*mbox
)
120 struct omap_mbox2_fifo
*fifo
=
121 &((struct omap_mbox2_priv
*)mbox
->priv
)->tx_fifo
;
122 return mbox_read_reg(fifo
->fifo_stat
);
125 /* Mailbox IRQ handle functions */
126 static void omap2_mbox_enable_irq(struct omap_mbox
*mbox
,
127 omap_mbox_type_t irq
)
129 struct omap_mbox2_priv
*p
= mbox
->priv
;
130 u32 l
, bit
= (irq
== IRQ_TX
) ? p
->notfull_bit
: p
->newmsg_bit
;
132 l
= mbox_read_reg(p
->irqenable
);
134 mbox_write_reg(l
, p
->irqenable
);
137 static void omap2_mbox_disable_irq(struct omap_mbox
*mbox
,
138 omap_mbox_type_t irq
)
140 struct omap_mbox2_priv
*p
= mbox
->priv
;
141 u32 bit
= (irq
== IRQ_TX
) ? p
->notfull_bit
: p
->newmsg_bit
;
143 if (!cpu_is_omap44xx())
144 bit
= mbox_read_reg(p
->irqdisable
) & ~bit
;
146 mbox_write_reg(bit
, p
->irqdisable
);
149 static void omap2_mbox_ack_irq(struct omap_mbox
*mbox
,
150 omap_mbox_type_t irq
)
152 struct omap_mbox2_priv
*p
= mbox
->priv
;
153 u32 bit
= (irq
== IRQ_TX
) ? p
->notfull_bit
: p
->newmsg_bit
;
155 mbox_write_reg(bit
, p
->irqstatus
);
157 /* Flush posted write for irq status to avoid spurious interrupts */
158 mbox_read_reg(p
->irqstatus
);
161 static int omap2_mbox_is_irq(struct omap_mbox
*mbox
,
162 omap_mbox_type_t irq
)
164 struct omap_mbox2_priv
*p
= mbox
->priv
;
165 u32 bit
= (irq
== IRQ_TX
) ? p
->notfull_bit
: p
->newmsg_bit
;
166 u32 enable
= mbox_read_reg(p
->irqenable
);
167 u32 status
= mbox_read_reg(p
->irqstatus
);
169 return (int)(enable
& status
& bit
);
172 static void omap2_mbox_save_ctx(struct omap_mbox
*mbox
)
175 struct omap_mbox2_priv
*p
= mbox
->priv
;
177 if (cpu_is_omap44xx())
178 nr_regs
= OMAP4_MBOX_NR_REGS
;
180 nr_regs
= MBOX_NR_REGS
;
181 for (i
= 0; i
< nr_regs
; i
++) {
182 p
->ctx
[i
] = mbox_read_reg(i
* sizeof(u32
));
184 dev_dbg(mbox
->dev
, "%s: [%02x] %08x\n", __func__
,
189 static void omap2_mbox_restore_ctx(struct omap_mbox
*mbox
)
192 struct omap_mbox2_priv
*p
= mbox
->priv
;
194 if (cpu_is_omap44xx())
195 nr_regs
= OMAP4_MBOX_NR_REGS
;
197 nr_regs
= MBOX_NR_REGS
;
198 for (i
= 0; i
< nr_regs
; i
++) {
199 mbox_write_reg(p
->ctx
[i
], i
* sizeof(u32
));
201 dev_dbg(mbox
->dev
, "%s: [%02x] %08x\n", __func__
,
206 static struct omap_mbox_ops omap2_mbox_ops
= {
207 .type
= OMAP_MBOX_TYPE2
,
208 .startup
= omap2_mbox_startup
,
209 .shutdown
= omap2_mbox_shutdown
,
210 .fifo_read
= omap2_mbox_fifo_read
,
211 .fifo_write
= omap2_mbox_fifo_write
,
212 .fifo_empty
= omap2_mbox_fifo_empty
,
213 .fifo_full
= omap2_mbox_fifo_full
,
214 .enable_irq
= omap2_mbox_enable_irq
,
215 .disable_irq
= omap2_mbox_disable_irq
,
216 .ack_irq
= omap2_mbox_ack_irq
,
217 .is_irq
= omap2_mbox_is_irq
,
218 .save_ctx
= omap2_mbox_save_ctx
,
219 .restore_ctx
= omap2_mbox_restore_ctx
,
223 * MAILBOX 0: ARM -> DSP,
224 * MAILBOX 1: ARM <- DSP.
225 * MAILBOX 2: ARM -> IVA,
226 * MAILBOX 3: ARM <- IVA.
229 /* FIXME: the following structs should be filled automatically by the user id */
231 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP2)
233 static struct omap_mbox2_priv omap2_mbox_dsp_priv
= {
235 .msg
= MAILBOX_MESSAGE(0),
236 .fifo_stat
= MAILBOX_FIFOSTATUS(0),
239 .msg
= MAILBOX_MESSAGE(1),
240 .msg_stat
= MAILBOX_MSGSTATUS(1),
242 .irqenable
= MAILBOX_IRQENABLE(0),
243 .irqstatus
= MAILBOX_IRQSTATUS(0),
244 .notfull_bit
= MAILBOX_IRQ_NOTFULL(0),
245 .newmsg_bit
= MAILBOX_IRQ_NEWMSG(1),
246 .irqdisable
= MAILBOX_IRQENABLE(0),
249 struct omap_mbox mbox_dsp_info
= {
251 .ops
= &omap2_mbox_ops
,
252 .priv
= &omap2_mbox_dsp_priv
,
256 #if defined(CONFIG_ARCH_OMAP3)
257 struct omap_mbox
*omap3_mboxes
[] = { &mbox_dsp_info
, NULL
};
260 #if defined(CONFIG_SOC_OMAP2420)
262 static struct omap_mbox2_priv omap2_mbox_iva_priv
= {
264 .msg
= MAILBOX_MESSAGE(2),
265 .fifo_stat
= MAILBOX_FIFOSTATUS(2),
268 .msg
= MAILBOX_MESSAGE(3),
269 .msg_stat
= MAILBOX_MSGSTATUS(3),
271 .irqenable
= MAILBOX_IRQENABLE(3),
272 .irqstatus
= MAILBOX_IRQSTATUS(3),
273 .notfull_bit
= MAILBOX_IRQ_NOTFULL(2),
274 .newmsg_bit
= MAILBOX_IRQ_NEWMSG(3),
275 .irqdisable
= MAILBOX_IRQENABLE(3),
278 static struct omap_mbox mbox_iva_info
= {
280 .ops
= &omap2_mbox_ops
,
281 .priv
= &omap2_mbox_iva_priv
,
285 #ifdef CONFIG_ARCH_OMAP2
286 struct omap_mbox
*omap2_mboxes
[] = {
288 #ifdef CONFIG_SOC_OMAP2420
295 #if defined(CONFIG_ARCH_OMAP4)
297 static struct omap_mbox2_priv omap2_mbox_1_priv
= {
299 .msg
= MAILBOX_MESSAGE(0),
300 .fifo_stat
= MAILBOX_FIFOSTATUS(0),
303 .msg
= MAILBOX_MESSAGE(1),
304 .msg_stat
= MAILBOX_MSGSTATUS(1),
306 .irqenable
= OMAP4_MAILBOX_IRQENABLE(0),
307 .irqstatus
= OMAP4_MAILBOX_IRQSTATUS(0),
308 .notfull_bit
= MAILBOX_IRQ_NOTFULL(0),
309 .newmsg_bit
= MAILBOX_IRQ_NEWMSG(1),
310 .irqdisable
= OMAP4_MAILBOX_IRQENABLE_CLR(0),
313 struct omap_mbox mbox_1_info
= {
315 .ops
= &omap2_mbox_ops
,
316 .priv
= &omap2_mbox_1_priv
,
319 static struct omap_mbox2_priv omap2_mbox_2_priv
= {
321 .msg
= MAILBOX_MESSAGE(3),
322 .fifo_stat
= MAILBOX_FIFOSTATUS(3),
325 .msg
= MAILBOX_MESSAGE(2),
326 .msg_stat
= MAILBOX_MSGSTATUS(2),
328 .irqenable
= OMAP4_MAILBOX_IRQENABLE(0),
329 .irqstatus
= OMAP4_MAILBOX_IRQSTATUS(0),
330 .notfull_bit
= MAILBOX_IRQ_NOTFULL(3),
331 .newmsg_bit
= MAILBOX_IRQ_NEWMSG(2),
332 .irqdisable
= OMAP4_MAILBOX_IRQENABLE_CLR(0),
335 struct omap_mbox mbox_2_info
= {
337 .ops
= &omap2_mbox_ops
,
338 .priv
= &omap2_mbox_2_priv
,
341 struct omap_mbox
*omap4_mboxes
[] = { &mbox_1_info
, &mbox_2_info
, NULL
};
344 static int __devinit
omap2_mbox_probe(struct platform_device
*pdev
)
346 struct resource
*mem
;
348 struct omap_mbox
**list
;
352 #if defined(CONFIG_ARCH_OMAP3)
353 else if (cpu_is_omap34xx()) {
356 list
[0]->irq
= platform_get_irq(pdev
, 0);
359 #if defined(CONFIG_ARCH_OMAP2)
360 else if (cpu_is_omap2430()) {
363 list
[0]->irq
= platform_get_irq(pdev
, 0);
364 } else if (cpu_is_omap2420()) {
367 list
[0]->irq
= platform_get_irq_byname(pdev
, "dsp");
368 list
[1]->irq
= platform_get_irq_byname(pdev
, "iva");
371 #if defined(CONFIG_ARCH_OMAP4)
372 else if (cpu_is_omap44xx()) {
375 list
[0]->irq
= list
[1]->irq
= platform_get_irq(pdev
, 0);
379 pr_err("%s: platform not supported\n", __func__
);
383 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
384 mbox_base
= ioremap(mem
->start
, resource_size(mem
));
388 ret
= omap_mbox_register(&pdev
->dev
, list
);
397 static int __devexit
omap2_mbox_remove(struct platform_device
*pdev
)
399 omap_mbox_unregister();
404 static struct platform_driver omap2_mbox_driver
= {
405 .probe
= omap2_mbox_probe
,
406 .remove
= __devexit_p(omap2_mbox_remove
),
408 .name
= "omap-mailbox",
412 static int __init
omap2_mbox_init(void)
414 return platform_driver_register(&omap2_mbox_driver
);
417 static void __exit
omap2_mbox_exit(void)
419 platform_driver_unregister(&omap2_mbox_driver
);
422 module_init(omap2_mbox_init
);
423 module_exit(omap2_mbox_exit
);
425 MODULE_LICENSE("GPL v2");
426 MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions");
427 MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
428 MODULE_AUTHOR("Paul Mundt");
429 MODULE_ALIAS("platform:omap2-mailbox");