2 * OMAP MPUSS low power code
4 * Copyright (C) 2011 Texas Instruments, Inc.
5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
7 * OMAP4430 MPUSS mainly consists of dual Cortex-A9 with per-CPU
8 * Local timer and Watchdog, GIC, SCU, PL310 L2 cache controller,
9 * CPU0 and CPU1 LPRM modules.
10 * CPU0, CPU1 and MPUSS each have there own power domain and
11 * hence multiple low power combinations of MPUSS are possible.
13 * The CPU0 and CPU1 can't support Closed switch Retention (CSWR)
14 * because the mode is not supported by hw constraints of dormant
15 * mode. While waking up from the dormant mode, a reset signal
16 * to the Cortex-A9 processor must be asserted by the external
19 * With architectural inputs and hardware recommendations, only
20 * below modes are supported from power gain vs latency point of view.
23 * ----------------------------------------------
25 * ON(Inactive) OFF ON(Inactive)
28 * OFF OFF OFF(Device OFF *TBD)
29 * ----------------------------------------------
31 * Note: CPU0 is the master core and it is the last CPU to go down
32 * and first to wake-up when MPUSS low power states are excercised
35 * This program is free software; you can redistribute it and/or modify
36 * it under the terms of the GNU General Public License version 2 as
37 * published by the Free Software Foundation.
40 #include <linux/kernel.h>
42 #include <linux/errno.h>
43 #include <linux/linkage.h>
44 #include <linux/smp.h>
46 #include <asm/cacheflush.h>
47 #include <asm/tlbflush.h>
48 #include <asm/smp_scu.h>
49 #include <asm/pgalloc.h>
50 #include <asm/suspend.h>
51 #include <asm/hardware/cache-l2x0.h>
56 #include "omap4-sar-layout.h"
58 #include "prcm_mpu44xx.h"
59 #include "prminst44xx.h"
62 #include "prm-regbits-44xx.h"
66 struct omap4_cpu_pm_info
{
67 struct powerdomain
*pwrdm
;
68 void __iomem
*scu_sar_addr
;
69 void __iomem
*wkup_sar_addr
;
70 void __iomem
*l2x0_sar_addr
;
71 void (*secondary_startup
)(void);
74 static DEFINE_PER_CPU(struct omap4_cpu_pm_info
, omap4_pm_info
);
75 static struct powerdomain
*mpuss_pd
;
76 static void __iomem
*sar_base
;
79 * Program the wakeup routine address for the CPU0 and CPU1
80 * used for OFF or DORMANT wakeup.
82 static inline void set_cpu_wakeup_addr(unsigned int cpu_id
, u32 addr
)
84 struct omap4_cpu_pm_info
*pm_info
= &per_cpu(omap4_pm_info
, cpu_id
);
86 __raw_writel(addr
, pm_info
->wkup_sar_addr
);
90 * Store the SCU power status value to scratchpad memory
92 static void scu_pwrst_prepare(unsigned int cpu_id
, unsigned int cpu_state
)
94 struct omap4_cpu_pm_info
*pm_info
= &per_cpu(omap4_pm_info
, cpu_id
);
99 scu_pwr_st
= SCU_PM_DORMANT
;
101 case PWRDM_POWER_OFF
:
102 scu_pwr_st
= SCU_PM_POWEROFF
;
105 case PWRDM_POWER_INACTIVE
:
107 scu_pwr_st
= SCU_PM_NORMAL
;
111 __raw_writel(scu_pwr_st
, pm_info
->scu_sar_addr
);
114 /* Helper functions for MPUSS OSWR */
115 static inline void mpuss_clear_prev_logic_pwrst(void)
119 reg
= omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION
,
120 OMAP4430_PRM_MPU_INST
, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET
);
121 omap4_prminst_write_inst_reg(reg
, OMAP4430_PRM_PARTITION
,
122 OMAP4430_PRM_MPU_INST
, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET
);
125 static inline void cpu_clear_prev_logic_pwrst(unsigned int cpu_id
)
130 reg
= omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST
,
131 OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET
);
132 omap4_prcm_mpu_write_inst_reg(reg
, OMAP4430_PRCM_MPU_CPU1_INST
,
133 OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET
);
135 reg
= omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST
,
136 OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET
);
137 omap4_prcm_mpu_write_inst_reg(reg
, OMAP4430_PRCM_MPU_CPU0_INST
,
138 OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET
);
143 * omap4_mpuss_read_prev_context_state:
144 * Function returns the MPUSS previous context state
146 u32
omap4_mpuss_read_prev_context_state(void)
150 reg
= omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION
,
151 OMAP4430_PRM_MPU_INST
, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET
);
152 reg
&= OMAP4430_LOSTCONTEXT_DFF_MASK
;
157 * Store the CPU cluster state for L2X0 low power operations.
159 static void l2x0_pwrst_prepare(unsigned int cpu_id
, unsigned int save_state
)
161 struct omap4_cpu_pm_info
*pm_info
= &per_cpu(omap4_pm_info
, cpu_id
);
163 __raw_writel(save_state
, pm_info
->l2x0_sar_addr
);
167 * Save the L2X0 AUXCTRL and POR value to SAR memory. Its used to
168 * in every restore MPUSS OFF path.
170 #ifdef CONFIG_CACHE_L2X0
171 static void save_l2x0_context(void)
174 void __iomem
*l2x0_base
= omap4_get_l2cache_base();
176 val
= __raw_readl(l2x0_base
+ L2X0_AUX_CTRL
);
177 __raw_writel(val
, sar_base
+ L2X0_AUXCTRL_OFFSET
);
178 val
= __raw_readl(l2x0_base
+ L2X0_PREFETCH_CTRL
);
179 __raw_writel(val
, sar_base
+ L2X0_PREFETCH_CTRL_OFFSET
);
182 static void save_l2x0_context(void)
187 * omap4_enter_lowpower: OMAP4 MPUSS Low Power Entry Function
188 * The purpose of this function is to manage low power programming
189 * of OMAP4 MPUSS subsystem
191 * @power_state: Low power state.
193 * MPUSS states for the context save:
195 * 0 - Nothing lost and no need to save: MPUSS INACTIVE
196 * 1 - CPUx L1 and logic lost: MPUSS CSWR
197 * 2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
198 * 3 - CPUx L1 and logic lost + GIC + L2 lost: DEVICE OFF
200 int omap4_enter_lowpower(unsigned int cpu
, unsigned int power_state
)
202 struct omap4_cpu_pm_info
*pm_info
= &per_cpu(omap4_pm_info
, cpu
);
203 unsigned int save_state
= 0;
204 unsigned int wakeup_cpu
;
206 if (omap_rev() == OMAP4430_REV_ES1_0
)
209 switch (power_state
) {
211 case PWRDM_POWER_INACTIVE
:
214 case PWRDM_POWER_OFF
:
217 case PWRDM_POWER_RET
:
220 * CPUx CSWR is invalid hardware state. Also CPUx OSWR
221 * doesn't make much scense, since logic is lost and $L1
222 * needs to be cleaned because of coherency. This makes
223 * CPUx OSWR equivalent to CPUX OFF and hence not supported
229 pwrdm_pre_transition(NULL
);
232 * Check MPUSS next state and save interrupt controller if needed.
233 * In MPUSS OSWR or device OFF, interrupt controller contest is lost.
235 mpuss_clear_prev_logic_pwrst();
236 if ((pwrdm_read_next_pwrst(mpuss_pd
) == PWRDM_POWER_RET
) &&
237 (pwrdm_read_logic_retst(mpuss_pd
) == PWRDM_POWER_OFF
))
240 cpu_clear_prev_logic_pwrst(cpu
);
241 pwrdm_set_next_pwrst(pm_info
->pwrdm
, power_state
);
242 set_cpu_wakeup_addr(cpu
, virt_to_phys(omap4_cpu_resume
));
243 scu_pwrst_prepare(cpu
, power_state
);
244 l2x0_pwrst_prepare(cpu
, save_state
);
247 * Call low level function with targeted low power state.
249 cpu_suspend(save_state
, omap4_finish_suspend
);
252 * Restore the CPUx power state to ON otherwise CPUx
253 * power domain can transitions to programmed low power
254 * state while doing WFI outside the low powe code. On
255 * secure devices, CPUx does WFI which can result in
258 wakeup_cpu
= smp_processor_id();
259 pwrdm_set_next_pwrst(pm_info
->pwrdm
, PWRDM_POWER_ON
);
261 pwrdm_post_transition(NULL
);
267 * omap4_hotplug_cpu: OMAP4 CPU hotplug entry
269 * @power_state: CPU low power state.
271 int __cpuinit
omap4_hotplug_cpu(unsigned int cpu
, unsigned int power_state
)
273 struct omap4_cpu_pm_info
*pm_info
= &per_cpu(omap4_pm_info
, cpu
);
274 unsigned int cpu_state
= 0;
276 if (omap_rev() == OMAP4430_REV_ES1_0
)
279 if (power_state
== PWRDM_POWER_OFF
)
282 pwrdm_clear_all_prev_pwrst(pm_info
->pwrdm
);
283 pwrdm_set_next_pwrst(pm_info
->pwrdm
, power_state
);
284 set_cpu_wakeup_addr(cpu
, virt_to_phys(pm_info
->secondary_startup
));
285 scu_pwrst_prepare(cpu
, power_state
);
288 * CPU never retuns back if targeted power state is OFF mode.
289 * CPU ONLINE follows normal CPU ONLINE ptah via
290 * omap_secondary_startup().
292 omap4_finish_suspend(cpu_state
);
294 pwrdm_set_next_pwrst(pm_info
->pwrdm
, PWRDM_POWER_ON
);
300 * Initialise OMAP4 MPUSS
302 int __init
omap4_mpuss_init(void)
304 struct omap4_cpu_pm_info
*pm_info
;
306 if (omap_rev() == OMAP4430_REV_ES1_0
) {
307 WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
311 sar_base
= omap4_get_sar_ram_base();
313 /* Initilaise per CPU PM information */
314 pm_info
= &per_cpu(omap4_pm_info
, 0x0);
315 pm_info
->scu_sar_addr
= sar_base
+ SCU_OFFSET0
;
316 pm_info
->wkup_sar_addr
= sar_base
+ CPU0_WAKEUP_NS_PA_ADDR_OFFSET
;
317 pm_info
->l2x0_sar_addr
= sar_base
+ L2X0_SAVE_OFFSET0
;
318 pm_info
->pwrdm
= pwrdm_lookup("cpu0_pwrdm");
319 if (!pm_info
->pwrdm
) {
320 pr_err("Lookup failed for CPU0 pwrdm\n");
324 /* Clear CPU previous power domain state */
325 pwrdm_clear_all_prev_pwrst(pm_info
->pwrdm
);
326 cpu_clear_prev_logic_pwrst(0);
328 /* Initialise CPU0 power domain state to ON */
329 pwrdm_set_next_pwrst(pm_info
->pwrdm
, PWRDM_POWER_ON
);
331 pm_info
= &per_cpu(omap4_pm_info
, 0x1);
332 pm_info
->scu_sar_addr
= sar_base
+ SCU_OFFSET1
;
333 pm_info
->wkup_sar_addr
= sar_base
+ CPU1_WAKEUP_NS_PA_ADDR_OFFSET
;
334 pm_info
->l2x0_sar_addr
= sar_base
+ L2X0_SAVE_OFFSET1
;
335 if (cpu_is_omap446x())
336 pm_info
->secondary_startup
= omap_secondary_startup_4460
;
338 pm_info
->secondary_startup
= omap_secondary_startup
;
340 pm_info
->pwrdm
= pwrdm_lookup("cpu1_pwrdm");
341 if (!pm_info
->pwrdm
) {
342 pr_err("Lookup failed for CPU1 pwrdm\n");
346 /* Clear CPU previous power domain state */
347 pwrdm_clear_all_prev_pwrst(pm_info
->pwrdm
);
348 cpu_clear_prev_logic_pwrst(1);
350 /* Initialise CPU1 power domain state to ON */
351 pwrdm_set_next_pwrst(pm_info
->pwrdm
, PWRDM_POWER_ON
);
353 mpuss_pd
= pwrdm_lookup("mpu_pwrdm");
355 pr_err("Failed to lookup MPUSS power domain\n");
358 pwrdm_clear_all_prev_pwrst(mpuss_pd
);
359 mpuss_clear_prev_logic_pwrst();
361 /* Save device type on scratchpad for low level code to use */
362 if (omap_type() != OMAP2_DEVICE_TYPE_GP
)
363 __raw_writel(1, sar_base
+ OMAP_TYPE_OFFSET
);
365 __raw_writel(0, sar_base
+ OMAP_TYPE_OFFSET
);