arch/arm/mach-omap2/omap-smp.c

   1 /*
   2  * OMAP4 SMP source file. It contains platform specific functions
   3  * needed for the linux smp kernel.
   4  *
   5  * Copyright (C) 2009 Texas Instruments, Inc.
   6  *
   7  * Author:
   8  *      Santosh Shilimkar <santosh.shilimkar@ti.com>
   9  *
  10  * Platform file needed for the OMAP4 SMP. This file is based on arm
  11  * realview smp platform.
  12  * * Copyright (c) 2002 ARM Limited.
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License version 2 as
  16  * published by the Free Software Foundation.
  17  */
  18 #include <linux/init.h>
  19 #include <linux/device.h>
  20 #include <linux/smp.h>
  21 #include <linux/io.h>
  22 #include <linux/irqchip/arm-gic.h>
  23
  24 #include <asm/smp_scu.h>
  25
  26 #include "omap-secure.h"
  27 #include "omap-wakeupgen.h"
  28 #include <asm/cputype.h>
  29
  30 #include "soc.h"
  31 #include "iomap.h"
  32 #include "common.h"
  33 #include "clockdomain.h"
  34 #include "pm.h"
  35
  36 #define CPU_MASK                0xff0ffff0
  37 #define CPU_CORTEX_A9           0x410FC090
  38 #define CPU_CORTEX_A15          0x410FC0F0
  39
  40 #define OMAP5_CORE_COUNT        0x2
  41
  42 /* SCU base address */
  43 static void __iomem *scu_base;
  44
  45 static DEFINE_SPINLOCK(boot_lock);
  46
  47 void __iomem *omap4_get_scu_base(void)
  48 {
  49         return scu_base;
  50 }
  51
  52 static void omap4_secondary_init(unsigned int cpu)
  53 {
  54         /*
  55          * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
  56          * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA
  57          * init and for CPU1, a secure PPA API provided. CPU0 must be ON
  58          * while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+.
  59          * OMAP443X GP devices- SMP bit isn't accessible.
  60          * OMAP446X GP devices - SMP bit access is enabled on both CPUs.
  61          */
  62         if (cpu_is_omap443x() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
  63                 omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX,
  64                                                         4, 0, 0, 0, 0, 0);
  65
  66         /*
  67          * Configure the CNTFRQ register for the secondary cpu's which
  68          * indicates the frequency of the cpu local timers.
  69          */
  70         if (soc_is_omap54xx() || soc_is_dra7xx())
  71                 set_cntfreq();
  72
  73         /*
  74          * Synchronise with the boot thread.
  75          */
  76         spin_lock(&boot_lock);
  77         spin_unlock(&boot_lock);
  78 }
  79
  80 static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
  81 {
  82         static struct clockdomain *cpu1_clkdm;
  83         static bool booted;
  84         static struct powerdomain *cpu1_pwrdm;
  85         void __iomem *base = omap_get_wakeupgen_base();
  86
  87         /*
  88          * Set synchronisation state between this boot processor
  89          * and the secondary one
  90          */
  91         spin_lock(&boot_lock);
  92
  93         /*
  94          * Update the AuxCoreBoot0 with boot state for secondary core.
  95          * omap4_secondary_startup() routine will hold the secondary core till
  96          * the AuxCoreBoot1 register is updated with cpu state
  97          * A barrier is added to ensure that write buffer is drained
  98          */
  99         if (omap_secure_apis_support())
 100                 omap_modify_auxcoreboot0(0x200, 0xfffffdff);
 101         else
 102                 writel_relaxed(0x20, base + OMAP_AUX_CORE_BOOT_0);
 103
 104         if (!cpu1_clkdm && !cpu1_pwrdm) {
 105                 cpu1_clkdm = clkdm_lookup("mpu1_clkdm");
 106                 cpu1_pwrdm = pwrdm_lookup("cpu1_pwrdm");
 107         }
 108
 109         /*
 110          * The SGI(Software Generated Interrupts) are not wakeup capable
 111          * from low power states. This is known limitation on OMAP4 and
 112          * needs to be worked around by using software forced clockdomain
 113          * wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to
 114          * software force wakeup. The clockdomain is then put back to
 115          * hardware supervised mode.
 116          * More details can be found in OMAP4430 TRM - Version J
 117          * Section :
 118          *      4.3.4.2 Power States of CPU0 and CPU1
 119          */
 120         if (booted && cpu1_pwrdm && cpu1_clkdm) {
 121                 /*
 122                  * GIC distributor control register has changed between
 123                  * CortexA9 r1pX and r2pX. The Control Register secure
 124                  * banked version is now composed of 2 bits:
 125                  * bit 0 == Secure Enable
 126                  * bit 1 == Non-Secure Enable
 127                  * The Non-Secure banked register has not changed
 128                  * Because the ROM Code is based on the r1pX GIC, the CPU1
 129                  * GIC restoration will cause a problem to CPU0 Non-Secure SW.
 130                  * The workaround must be:
 131                  * 1) Before doing the CPU1 wakeup, CPU0 must disable
 132                  * the GIC distributor
 133                  * 2) CPU1 must re-enable the GIC distributor on
 134                  * it's wakeup path.
 135                  */
 136                 if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) {
 137                         local_irq_disable();
 138                         gic_dist_disable();
 139                 }
 140
 141                 /*
 142                  * Ensure that CPU power state is set to ON to avoid CPU
 143                  * powerdomain transition on wfi
 144                  */
 145                 clkdm_wakeup(cpu1_clkdm);
 146                 omap_set_pwrdm_state(cpu1_pwrdm, PWRDM_POWER_ON);
 147                 clkdm_allow_idle(cpu1_clkdm);
 148
 149                 if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) {
 150                         while (gic_dist_disabled()) {
 151                                 udelay(1);
 152                                 cpu_relax();
 153                         }
 154                         gic_timer_retrigger();
 155                         local_irq_enable();
 156                 }
 157         } else {
 158                 dsb_sev();
 159                 booted = true;
 160         }
 161
 162         arch_send_wakeup_ipi_mask(cpumask_of(cpu));
 163
 164         /*
 165          * Now the secondary core is starting up let it run its
 166          * calibrations, then wait for it to finish
 167          */
 168         spin_unlock(&boot_lock);
 169
 170         return 0;
 171 }
 172
 173 /*
 174  * Initialise the CPU possible map early - this describes the CPUs
 175  * which may be present or become present in the system.
 176  */
 177 static void __init omap4_smp_init_cpus(void)
 178 {
 179         unsigned int i = 0, ncores = 1, cpu_id;
 180
 181         /* Use ARM cpuid check here, as SoC detection will not work so early */
 182         cpu_id = read_cpuid_id() & CPU_MASK;
 183         if (cpu_id == CPU_CORTEX_A9) {
 184                 /*
 185                  * Currently we can't call ioremap here because
 186                  * SoC detection won't work until after init_early.
 187                  */
 188                 scu_base =  OMAP2_L4_IO_ADDRESS(scu_a9_get_base());
 189                 BUG_ON(!scu_base);
 190                 ncores = scu_get_core_count(scu_base);
 191         } else if (cpu_id == CPU_CORTEX_A15) {
 192                 ncores = OMAP5_CORE_COUNT;
 193         }
 194
 195         /* sanity check */
 196         if (ncores > nr_cpu_ids) {
 197                 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
 198                         ncores, nr_cpu_ids);
 199                 ncores = nr_cpu_ids;
 200         }
 201
 202         for (i = 0; i < ncores; i++)
 203                 set_cpu_possible(i, true);
 204 }
 205
 206 static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
 207 {
 208         void *startup_addr = omap4_secondary_startup;
 209         void __iomem *base = omap_get_wakeupgen_base();
 210
 211         /*
 212          * Initialise the SCU and wake up the secondary core using
 213          * wakeup_secondary().
 214          */
 215         if (scu_base)
 216                 scu_enable(scu_base);
 217
 218         if (cpu_is_omap446x())
 219                 startup_addr = omap4460_secondary_startup;
 220
 221         /*
 222          * Write the address of secondary startup routine into the
 223          * AuxCoreBoot1 where ROM code will jump and start executing
 224          * on secondary core once out of WFE
 225          * A barrier is added to ensure that write buffer is drained
 226          */
 227         if (omap_secure_apis_support())
 228                 omap_auxcoreboot_addr(virt_to_phys(startup_addr));
 229         else
 230                 writel_relaxed(virt_to_phys(omap5_secondary_startup),
 231                                base + OMAP_AUX_CORE_BOOT_1);
 232
 233 }
 234
 235 struct smp_operations omap4_smp_ops __initdata = {
 236         .smp_init_cpus          = omap4_smp_init_cpus,
 237         .smp_prepare_cpus       = omap4_smp_prepare_cpus,
 238         .smp_secondary_init     = omap4_secondary_init,
 239         .smp_boot_secondary     = omap4_boot_secondary,
 240 #ifdef CONFIG_HOTPLUG_CPU
 241         .cpu_die                = omap4_cpu_die,
 242 #endif
 243 };