arch/arm/mach-omap2/omap-smp.c

   1 /*
   2  * OMAP4 SMP source file. It contains platform specific fucntions
   3  * needed for the linux smp kernel.
   4  *
   5  * Copyright (C) 2009 Texas Instruments, Inc.
   6  *
   7  * Author:
   8  *      Santosh Shilimkar <santosh.shilimkar@ti.com>
   9  *
  10  * Platform file needed for the OMAP4 SMP. This file is based on arm
  11  * realview smp platform.
  12  * * Copyright (c) 2002 ARM Limited.
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License version 2 as
  16  * published by the Free Software Foundation.
  17  */
  18 #include <linux/init.h>
  19 #include <linux/device.h>
  20 #include <linux/smp.h>
  21 #include <linux/io.h>
  22
  23 #include <asm/cacheflush.h>
  24 #include <asm/hardware/gic.h>
  25 #include <asm/smp_scu.h>
  26
  27 #include <mach/hardware.h>
  28 #include <mach/omap-secure.h>
  29 #include <mach/omap-wakeupgen.h>
  30 #include <asm/cputype.h>
  31
  32 #include "iomap.h"
  33 #include "common.h"
  34 #include "clockdomain.h"
  35
  36 #define CPU_MASK                0xff0ffff0
  37 #define CPU_CORTEX_A9           0x410FC090
  38 #define CPU_CORTEX_A15          0x410FC0F0
  39
  40 #define OMAP5_CORE_COUNT        0x2
  41
  42 /* SCU base address */
  43 static void __iomem *scu_base;
  44
  45 static DEFINE_SPINLOCK(boot_lock);
  46
  47 void __iomem *omap4_get_scu_base(void)
  48 {
  49         return scu_base;
  50 }
  51
  52 void __cpuinit platform_secondary_init(unsigned int cpu)
  53 {
  54         /*
  55          * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
  56          * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA
  57          * init and for CPU1, a secure PPA API provided. CPU0 must be ON
  58          * while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+.
  59          * OMAP443X GP devices- SMP bit isn't accessible.
  60          * OMAP446X GP devices - SMP bit access is enabled on both CPUs.
  61          */
  62         if (cpu_is_omap443x() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
  63                 omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX,
  64                                                         4, 0, 0, 0, 0, 0);
  65
  66         /*
  67          * If any interrupts are already enabled for the primary
  68          * core (e.g. timer irq), then they will not have been enabled
  69          * for us: do so
  70          */
  71         gic_secondary_init(0);
  72
  73         /*
  74          * Synchronise with the boot thread.
  75          */
  76         spin_lock(&boot_lock);
  77         spin_unlock(&boot_lock);
  78 }
  79
  80 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
  81 {
  82         static struct clockdomain *cpu1_clkdm;
  83         static bool booted;
  84         void __iomem *base = omap_get_wakeupgen_base();
  85
  86         /*
  87          * Set synchronisation state between this boot processor
  88          * and the secondary one
  89          */
  90         spin_lock(&boot_lock);
  91
  92         /*
  93          * Update the AuxCoreBoot0 with boot state for secondary core.
  94          * omap_secondary_startup() routine will hold the secondary core till
  95          * the AuxCoreBoot1 register is updated with cpu state
  96          * A barrier is added to ensure that write buffer is drained
  97          */
  98         if (omap_secure_apis_support())
  99                 omap_modify_auxcoreboot0(0x200, 0xfffffdff);
 100         else
 101                 __raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0);
 102
 103         flush_cache_all();
 104         smp_wmb();
 105
 106         if (!cpu1_clkdm)
 107                 cpu1_clkdm = clkdm_lookup("mpu1_clkdm");
 108
 109         /*
 110          * The SGI(Software Generated Interrupts) are not wakeup capable
 111          * from low power states. This is known limitation on OMAP4 and
 112          * needs to be worked around by using software forced clockdomain
 113          * wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to
 114          * software force wakeup. The clockdomain is then put back to
 115          * hardware supervised mode.
 116          * More details can be found in OMAP4430 TRM - Version J
 117          * Section :
 118          *      4.3.4.2 Power States of CPU0 and CPU1
 119          */
 120         if (booted) {
 121                 clkdm_wakeup(cpu1_clkdm);
 122                 clkdm_allow_idle(cpu1_clkdm);
 123         } else {
 124                 dsb_sev();
 125                 booted = true;
 126         }
 127
 128         gic_raise_softirq(cpumask_of(cpu), 0);
 129
 130         /*
 131          * Now the secondary core is starting up let it run its
 132          * calibrations, then wait for it to finish
 133          */
 134         spin_unlock(&boot_lock);
 135
 136         return 0;
 137 }
 138
 139 static void __init wakeup_secondary(void)
 140 {
 141         void __iomem *base = omap_get_wakeupgen_base();
 142         /*
 143          * Write the address of secondary startup routine into the
 144          * AuxCoreBoot1 where ROM code will jump and start executing
 145          * on secondary core once out of WFE
 146          * A barrier is added to ensure that write buffer is drained
 147          */
 148         if (omap_secure_apis_support())
 149                 omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
 150         else
 151                 __raw_writel(virt_to_phys(omap5_secondary_startup),
 152                                                 base + OMAP_AUX_CORE_BOOT_1);
 153
 154         smp_wmb();
 155
 156         /*
 157          * Send a 'sev' to wake the secondary core from WFE.
 158          * Drain the outstanding writes to memory
 159          */
 160         dsb_sev();
 161         mb();
 162 }
 163
 164 /*
 165  * Initialise the CPU possible map early - this describes the CPUs
 166  * which may be present or become present in the system.
 167  */
 168 void __init smp_init_cpus(void)
 169 {
 170         unsigned int i = 0, ncores = 1, cpu_id;
 171
 172         /* Use ARM cpuid check here, as SoC detection will not work so early */
 173         cpu_id = read_cpuid(CPUID_ID) & CPU_MASK;
 174         if (cpu_id == CPU_CORTEX_A9) {
 175                 /*
 176                  * Currently we can't call ioremap here because
 177                  * SoC detection won't work until after init_early.
 178                  */
 179                 scu_base =  OMAP2_L4_IO_ADDRESS(OMAP44XX_SCU_BASE);
 180                 BUG_ON(!scu_base);
 181                 ncores = scu_get_core_count(scu_base);
 182         } else if (cpu_id == CPU_CORTEX_A15) {
 183                 ncores = OMAP5_CORE_COUNT;
 184         }
 185
 186         /* sanity check */
 187         if (ncores > nr_cpu_ids) {
 188                 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
 189                         ncores, nr_cpu_ids);
 190                 ncores = nr_cpu_ids;
 191         }
 192
 193         for (i = 0; i < ncores; i++)
 194                 set_cpu_possible(i, true);
 195
 196         set_smp_cross_call(gic_raise_softirq);
 197 }
 198
 199 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 200 {
 201
 202         /*
 203          * Initialise the SCU and wake up the secondary core using
 204          * wakeup_secondary().
 205          */
 206         if (scu_base)
 207                 scu_enable(scu_base);
 208         wakeup_secondary();
 209 }