2 * OMAP4 specific common source file.
4 * Copyright (C) 2010 Texas Instruments, Inc.
6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
9 * This program is free software,you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/init.h>
17 #include <linux/irq.h>
18 #include <linux/irqchip.h>
19 #include <linux/platform_device.h>
20 #include <linux/memblock.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_platform.h>
23 #include <linux/export.h>
24 #include <linux/irqchip/arm-gic.h>
25 #include <linux/irqchip/irq-crossbar.h>
26 #include <linux/of_address.h>
27 #include <linux/reboot.h>
29 #include <asm/hardware/cache-l2x0.h>
30 #include <asm/mach/map.h>
31 #include <asm/memblock.h>
32 #include <asm/smp_twd.h>
34 #include "omap-wakeupgen.h"
39 #include "prminst44xx.h"
40 #include "prcm_mpu44xx.h"
41 #include "omap4-sar-layout.h"
42 #include "omap-secure.h"
45 #ifdef CONFIG_CACHE_L2X0
46 static void __iomem
*l2cache_base
;
49 static void __iomem
*sar_ram_base
;
50 static void __iomem
*gic_dist_base_addr
;
51 static void __iomem
*twd_base
;
53 #define IRQ_LOCALTIMER 29
55 #ifdef CONFIG_OMAP4_ERRATA_I688
56 /* Used to implement memory barrier on DRAM path */
57 #define OMAP4_DRAM_BARRIER_VA 0xfe600000
59 void __iomem
*dram_sync
, *sram_sync
;
61 static phys_addr_t paddr
;
64 void omap_bus_sync(void)
66 if (dram_sync
&& sram_sync
) {
67 writel_relaxed(readl_relaxed(dram_sync
), dram_sync
);
68 writel_relaxed(readl_relaxed(sram_sync
), sram_sync
);
72 EXPORT_SYMBOL(omap_bus_sync
);
74 /* Steal one page physical memory for barrier implementation */
75 int __init
omap_barrier_reserve_memblock(void)
78 size
= ALIGN(PAGE_SIZE
, SZ_1M
);
79 paddr
= arm_memblock_steal(size
, SZ_1M
);
84 void __init
omap_barriers_init(void)
86 struct map_desc dram_io_desc
[1];
88 dram_io_desc
[0].virtual = OMAP4_DRAM_BARRIER_VA
;
89 dram_io_desc
[0].pfn
= __phys_to_pfn(paddr
);
90 dram_io_desc
[0].length
= size
;
91 dram_io_desc
[0].type
= MT_MEMORY_RW_SO
;
92 iotable_init(dram_io_desc
, ARRAY_SIZE(dram_io_desc
));
93 dram_sync
= (void __iomem
*) dram_io_desc
[0].virtual;
94 sram_sync
= (void __iomem
*) OMAP4_SRAM_VA
;
96 pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
97 (long long) paddr
, dram_io_desc
[0].virtual);
101 void __init
omap_barriers_init(void)
105 void gic_dist_disable(void)
107 if (gic_dist_base_addr
)
108 writel_relaxed(0x0, gic_dist_base_addr
+ GIC_DIST_CTRL
);
111 void gic_dist_enable(void)
113 if (gic_dist_base_addr
)
114 writel_relaxed(0x1, gic_dist_base_addr
+ GIC_DIST_CTRL
);
117 bool gic_dist_disabled(void)
119 return !(readl_relaxed(gic_dist_base_addr
+ GIC_DIST_CTRL
) & 0x1);
122 void gic_timer_retrigger(void)
124 u32 twd_int
= readl_relaxed(twd_base
+ TWD_TIMER_INTSTAT
);
125 u32 gic_int
= readl_relaxed(gic_dist_base_addr
+ GIC_DIST_PENDING_SET
);
126 u32 twd_ctrl
= readl_relaxed(twd_base
+ TWD_TIMER_CONTROL
);
128 if (twd_int
&& !(gic_int
& BIT(IRQ_LOCALTIMER
))) {
130 * The local timer interrupt got lost while the distributor was
131 * disabled. Ack the pending interrupt, and retrigger it.
133 pr_warn("%s: lost localtimer interrupt\n", __func__
);
134 writel_relaxed(1, twd_base
+ TWD_TIMER_INTSTAT
);
135 if (!(twd_ctrl
& TWD_TIMER_CONTROL_PERIODIC
)) {
136 writel_relaxed(1, twd_base
+ TWD_TIMER_COUNTER
);
137 twd_ctrl
|= TWD_TIMER_CONTROL_ENABLE
;
138 writel_relaxed(twd_ctrl
, twd_base
+ TWD_TIMER_CONTROL
);
143 #ifdef CONFIG_CACHE_L2X0
145 void __iomem
*omap4_get_l2cache_base(void)
150 static void omap4_l2c310_write_sec(unsigned long val
, unsigned reg
)
156 smc_op
= OMAP4_MON_L2X0_CTRL_INDEX
;
160 smc_op
= OMAP4_MON_L2X0_AUXCTRL_INDEX
;
163 case L2X0_DEBUG_CTRL
:
164 smc_op
= OMAP4_MON_L2X0_DBG_CTRL_INDEX
;
167 case L310_PREFETCH_CTRL
:
168 smc_op
= OMAP4_MON_L2X0_PREFETCH_INDEX
;
171 case L310_POWER_CTRL
:
172 pr_info_once("OMAP L2C310: ROM does not support power control setting\n");
176 WARN_ONCE(1, "OMAP L2C310: ignoring write to reg 0x%x\n", reg
);
180 omap_smc1(smc_op
, val
);
183 int __init
omap_l2_cache_init(void)
187 /* Static mapping, never released */
188 l2cache_base
= ioremap(OMAP44XX_L2CACHE_BASE
, SZ_4K
);
189 if (WARN_ON(!l2cache_base
))
192 /* 16-way associativity, parity disabled, way size - 64KB (es2.0 +) */
193 aux_ctrl
= L2C_AUX_CTRL_SHARED_OVERRIDE
|
194 L310_AUX_CTRL_DATA_PREFETCH
|
195 L310_AUX_CTRL_INSTR_PREFETCH
;
197 outer_cache
.write_sec
= omap4_l2c310_write_sec
;
198 if (of_have_populated_dt())
199 l2x0_of_init(aux_ctrl
, 0xcf9fffff);
201 l2x0_init(l2cache_base
, aux_ctrl
, 0xcf9fffff);
207 void __iomem
*omap4_get_sar_ram_base(void)
213 * SAR RAM used to save and restore the HW
214 * context in low power modes
216 static int __init
omap4_sar_ram_init(void)
218 unsigned long sar_base
;
221 * To avoid code running on other OMAPs in
224 if (cpu_is_omap44xx())
225 sar_base
= OMAP44XX_SAR_RAM_BASE
;
226 else if (soc_is_omap54xx())
227 sar_base
= OMAP54XX_SAR_RAM_BASE
;
231 /* Static mapping, never released */
232 sar_ram_base
= ioremap(sar_base
, SZ_16K
);
233 if (WARN_ON(!sar_ram_base
))
238 omap_early_initcall(omap4_sar_ram_init
);
240 void __init
omap_gic_of_init(void)
242 struct device_node
*np
;
244 /* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */
245 if (!cpu_is_omap446x())
246 goto skip_errata_init
;
248 np
= of_find_compatible_node(NULL
, NULL
, "arm,cortex-a9-gic");
249 gic_dist_base_addr
= of_iomap(np
, 0);
250 WARN_ON(!gic_dist_base_addr
);
252 np
= of_find_compatible_node(NULL
, NULL
, "arm,cortex-a9-twd-timer");
253 twd_base
= of_iomap(np
, 0);
257 omap_wakeupgen_init();
258 #ifdef CONFIG_IRQ_CROSSBAR