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OMAP2430: hwmod data: Add USBOTG
[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_2430_data.c
1 /*
2 * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
3 *
4 * Copyright (C) 2009-2010 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * XXX handle crossbar/shared link difference for L3?
12 * XXX these should be marked initdata for multi-OMAP kernels
13 */
14 #include <plat/omap_hwmod.h>
15 #include <mach/irqs.h>
16 #include <plat/cpu.h>
17 #include <plat/dma.h>
18 #include <plat/serial.h>
19 #include <plat/i2c.h>
20 #include <plat/gpio.h>
21
22 #include "omap_hwmod_common_data.h"
23
24 #include "prm-regbits-24xx.h"
25 #include "cm-regbits-24xx.h"
26 #include "wd_timer.h"
27
28 /*
29 * OMAP2430 hardware module integration data
30 *
31 * ALl of the data in this section should be autogeneratable from the
32 * TI hardware database or other technical documentation. Data that
33 * is driver-specific or driver-kernel integration-specific belongs
34 * elsewhere.
35 */
36
37 static struct omap_hwmod omap2430_mpu_hwmod;
38 static struct omap_hwmod omap2430_iva_hwmod;
39 static struct omap_hwmod omap2430_l3_main_hwmod;
40 static struct omap_hwmod omap2430_l4_core_hwmod;
41 static struct omap_hwmod omap2430_wd_timer2_hwmod;
42 static struct omap_hwmod omap2430_gpio1_hwmod;
43 static struct omap_hwmod omap2430_gpio2_hwmod;
44 static struct omap_hwmod omap2430_gpio3_hwmod;
45 static struct omap_hwmod omap2430_gpio4_hwmod;
46 static struct omap_hwmod omap2430_gpio5_hwmod;
47 static struct omap_hwmod omap2430_dma_system_hwmod;
48
49 /* L3 -> L4_CORE interface */
50 static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
51 .master = &omap2430_l3_main_hwmod,
52 .slave = &omap2430_l4_core_hwmod,
53 .user = OCP_USER_MPU | OCP_USER_SDMA,
54 };
55
56 /* MPU -> L3 interface */
57 static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = {
58 .master = &omap2430_mpu_hwmod,
59 .slave = &omap2430_l3_main_hwmod,
60 .user = OCP_USER_MPU,
61 };
62
63 /* Slave interfaces on the L3 interconnect */
64 static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = {
65 &omap2430_mpu__l3_main,
66 };
67
68 /* Master interfaces on the L3 interconnect */
69 static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = {
70 &omap2430_l3_main__l4_core,
71 };
72
73 /* L3 */
74 static struct omap_hwmod omap2430_l3_main_hwmod = {
75 .name = "l3_main",
76 .class = &l3_hwmod_class,
77 .masters = omap2430_l3_main_masters,
78 .masters_cnt = ARRAY_SIZE(omap2430_l3_main_masters),
79 .slaves = omap2430_l3_main_slaves,
80 .slaves_cnt = ARRAY_SIZE(omap2430_l3_main_slaves),
81 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
82 .flags = HWMOD_NO_IDLEST,
83 };
84
85 static struct omap_hwmod omap2430_l4_wkup_hwmod;
86 static struct omap_hwmod omap2430_uart1_hwmod;
87 static struct omap_hwmod omap2430_uart2_hwmod;
88 static struct omap_hwmod omap2430_uart3_hwmod;
89 static struct omap_hwmod omap2430_i2c1_hwmod;
90 static struct omap_hwmod omap2430_i2c2_hwmod;
91
92 static struct omap_hwmod omap2430_usbhsotg_hwmod;
93
94 /* l3_core -> usbhsotg interface */
95 static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
96 .master = &omap2430_usbhsotg_hwmod,
97 .slave = &omap2430_l3_main_hwmod,
98 .clk = "core_l3_ck",
99 .user = OCP_USER_MPU,
100 };
101
102 /* I2C IP block address space length (in bytes) */
103 #define OMAP2_I2C_AS_LEN 128
104
105 /* L4 CORE -> I2C1 interface */
106 static struct omap_hwmod_addr_space omap2430_i2c1_addr_space[] = {
107 {
108 .pa_start = 0x48070000,
109 .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
110 .flags = ADDR_TYPE_RT,
111 },
112 };
113
114 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
115 .master = &omap2430_l4_core_hwmod,
116 .slave = &omap2430_i2c1_hwmod,
117 .clk = "i2c1_ick",
118 .addr = omap2430_i2c1_addr_space,
119 .addr_cnt = ARRAY_SIZE(omap2430_i2c1_addr_space),
120 .user = OCP_USER_MPU | OCP_USER_SDMA,
121 };
122
123 /* L4 CORE -> I2C2 interface */
124 static struct omap_hwmod_addr_space omap2430_i2c2_addr_space[] = {
125 {
126 .pa_start = 0x48072000,
127 .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
128 .flags = ADDR_TYPE_RT,
129 },
130 };
131
132 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
133 .master = &omap2430_l4_core_hwmod,
134 .slave = &omap2430_i2c2_hwmod,
135 .clk = "i2c2_ick",
136 .addr = omap2430_i2c2_addr_space,
137 .addr_cnt = ARRAY_SIZE(omap2430_i2c2_addr_space),
138 .user = OCP_USER_MPU | OCP_USER_SDMA,
139 };
140
141 /* L4_CORE -> L4_WKUP interface */
142 static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
143 .master = &omap2430_l4_core_hwmod,
144 .slave = &omap2430_l4_wkup_hwmod,
145 .user = OCP_USER_MPU | OCP_USER_SDMA,
146 };
147
148 /* L4 CORE -> UART1 interface */
149 static struct omap_hwmod_addr_space omap2430_uart1_addr_space[] = {
150 {
151 .pa_start = OMAP2_UART1_BASE,
152 .pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
153 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
154 },
155 };
156
157 static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
158 .master = &omap2430_l4_core_hwmod,
159 .slave = &omap2430_uart1_hwmod,
160 .clk = "uart1_ick",
161 .addr = omap2430_uart1_addr_space,
162 .addr_cnt = ARRAY_SIZE(omap2430_uart1_addr_space),
163 .user = OCP_USER_MPU | OCP_USER_SDMA,
164 };
165
166 /* L4 CORE -> UART2 interface */
167 static struct omap_hwmod_addr_space omap2430_uart2_addr_space[] = {
168 {
169 .pa_start = OMAP2_UART2_BASE,
170 .pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
171 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
172 },
173 };
174
175 static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
176 .master = &omap2430_l4_core_hwmod,
177 .slave = &omap2430_uart2_hwmod,
178 .clk = "uart2_ick",
179 .addr = omap2430_uart2_addr_space,
180 .addr_cnt = ARRAY_SIZE(omap2430_uart2_addr_space),
181 .user = OCP_USER_MPU | OCP_USER_SDMA,
182 };
183
184 /* L4 PER -> UART3 interface */
185 static struct omap_hwmod_addr_space omap2430_uart3_addr_space[] = {
186 {
187 .pa_start = OMAP2_UART3_BASE,
188 .pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
189 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
190 },
191 };
192
193 static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
194 .master = &omap2430_l4_core_hwmod,
195 .slave = &omap2430_uart3_hwmod,
196 .clk = "uart3_ick",
197 .addr = omap2430_uart3_addr_space,
198 .addr_cnt = ARRAY_SIZE(omap2430_uart3_addr_space),
199 .user = OCP_USER_MPU | OCP_USER_SDMA,
200 };
201
202 /*
203 * usbhsotg interface data
204 */
205 static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
206 {
207 .pa_start = OMAP243X_HS_BASE,
208 .pa_end = OMAP243X_HS_BASE + SZ_4K - 1,
209 .flags = ADDR_TYPE_RT
210 },
211 };
212
213 /* l4_core ->usbhsotg interface */
214 static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
215 .master = &omap2430_l4_core_hwmod,
216 .slave = &omap2430_usbhsotg_hwmod,
217 .clk = "usb_l4_ick",
218 .addr = omap2430_usbhsotg_addrs,
219 .addr_cnt = ARRAY_SIZE(omap2430_usbhsotg_addrs),
220 .user = OCP_USER_MPU,
221 };
222
223 static struct omap_hwmod_ocp_if *omap2430_usbhsotg_masters[] = {
224 &omap2430_usbhsotg__l3,
225 };
226
227 static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = {
228 &omap2430_l4_core__usbhsotg,
229 };
230
231 /* Slave interfaces on the L4_CORE interconnect */
232 static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
233 &omap2430_l3_main__l4_core,
234 };
235
236 /* Master interfaces on the L4_CORE interconnect */
237 static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = {
238 &omap2430_l4_core__l4_wkup,
239 };
240
241 /* L4 CORE */
242 static struct omap_hwmod omap2430_l4_core_hwmod = {
243 .name = "l4_core",
244 .class = &l4_hwmod_class,
245 .masters = omap2430_l4_core_masters,
246 .masters_cnt = ARRAY_SIZE(omap2430_l4_core_masters),
247 .slaves = omap2430_l4_core_slaves,
248 .slaves_cnt = ARRAY_SIZE(omap2430_l4_core_slaves),
249 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
250 .flags = HWMOD_NO_IDLEST,
251 };
252
253 /* Slave interfaces on the L4_WKUP interconnect */
254 static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = {
255 &omap2430_l4_core__l4_wkup,
256 &omap2_l4_core__uart1,
257 &omap2_l4_core__uart2,
258 &omap2_l4_core__uart3,
259 };
260
261 /* Master interfaces on the L4_WKUP interconnect */
262 static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
263 };
264
265 /* L4 WKUP */
266 static struct omap_hwmod omap2430_l4_wkup_hwmod = {
267 .name = "l4_wkup",
268 .class = &l4_hwmod_class,
269 .masters = omap2430_l4_wkup_masters,
270 .masters_cnt = ARRAY_SIZE(omap2430_l4_wkup_masters),
271 .slaves = omap2430_l4_wkup_slaves,
272 .slaves_cnt = ARRAY_SIZE(omap2430_l4_wkup_slaves),
273 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
274 .flags = HWMOD_NO_IDLEST,
275 };
276
277 /* Master interfaces on the MPU device */
278 static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = {
279 &omap2430_mpu__l3_main,
280 };
281
282 /* MPU */
283 static struct omap_hwmod omap2430_mpu_hwmod = {
284 .name = "mpu",
285 .class = &mpu_hwmod_class,
286 .main_clk = "mpu_ck",
287 .masters = omap2430_mpu_masters,
288 .masters_cnt = ARRAY_SIZE(omap2430_mpu_masters),
289 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
290 };
291
292 /*
293 * IVA2_1 interface data
294 */
295
296 /* IVA2 <- L3 interface */
297 static struct omap_hwmod_ocp_if omap2430_l3__iva = {
298 .master = &omap2430_l3_main_hwmod,
299 .slave = &omap2430_iva_hwmod,
300 .clk = "dsp_fck",
301 .user = OCP_USER_MPU | OCP_USER_SDMA,
302 };
303
304 static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = {
305 &omap2430_l3__iva,
306 };
307
308 /*
309 * IVA2 (IVA2)
310 */
311
312 static struct omap_hwmod omap2430_iva_hwmod = {
313 .name = "iva",
314 .class = &iva_hwmod_class,
315 .masters = omap2430_iva_masters,
316 .masters_cnt = ARRAY_SIZE(omap2430_iva_masters),
317 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
318 };
319
320 /* l4_wkup -> wd_timer2 */
321 static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
322 {
323 .pa_start = 0x49016000,
324 .pa_end = 0x4901607f,
325 .flags = ADDR_TYPE_RT
326 },
327 };
328
329 static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
330 .master = &omap2430_l4_wkup_hwmod,
331 .slave = &omap2430_wd_timer2_hwmod,
332 .clk = "mpu_wdt_ick",
333 .addr = omap2430_wd_timer2_addrs,
334 .addr_cnt = ARRAY_SIZE(omap2430_wd_timer2_addrs),
335 .user = OCP_USER_MPU | OCP_USER_SDMA,
336 };
337
338 /*
339 * 'wd_timer' class
340 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
341 * overflow condition
342 */
343
344 static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = {
345 .rev_offs = 0x0,
346 .sysc_offs = 0x0010,
347 .syss_offs = 0x0014,
348 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
349 SYSC_HAS_AUTOIDLE),
350 .sysc_fields = &omap_hwmod_sysc_type1,
351 };
352
353 static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = {
354 .name = "wd_timer",
355 .sysc = &omap2430_wd_timer_sysc,
356 .pre_shutdown = &omap2_wd_timer_disable
357 };
358
359 /* wd_timer2 */
360 static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
361 &omap2430_l4_wkup__wd_timer2,
362 };
363
364 static struct omap_hwmod omap2430_wd_timer2_hwmod = {
365 .name = "wd_timer2",
366 .class = &omap2430_wd_timer_hwmod_class,
367 .main_clk = "mpu_wdt_fck",
368 .prcm = {
369 .omap2 = {
370 .prcm_reg_id = 1,
371 .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
372 .module_offs = WKUP_MOD,
373 .idlest_reg_id = 1,
374 .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
375 },
376 },
377 .slaves = omap2430_wd_timer2_slaves,
378 .slaves_cnt = ARRAY_SIZE(omap2430_wd_timer2_slaves),
379 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
380 };
381
382 /* UART */
383
384 static struct omap_hwmod_class_sysconfig uart_sysc = {
385 .rev_offs = 0x50,
386 .sysc_offs = 0x54,
387 .syss_offs = 0x58,
388 .sysc_flags = (SYSC_HAS_SIDLEMODE |
389 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
390 SYSC_HAS_AUTOIDLE),
391 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
392 .sysc_fields = &omap_hwmod_sysc_type1,
393 };
394
395 static struct omap_hwmod_class uart_class = {
396 .name = "uart",
397 .sysc = &uart_sysc,
398 };
399
400 /* UART1 */
401
402 static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
403 { .irq = INT_24XX_UART1_IRQ, },
404 };
405
406 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
407 { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
408 { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
409 };
410
411 static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
412 &omap2_l4_core__uart1,
413 };
414
415 static struct omap_hwmod omap2430_uart1_hwmod = {
416 .name = "uart1",
417 .mpu_irqs = uart1_mpu_irqs,
418 .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs),
419 .sdma_reqs = uart1_sdma_reqs,
420 .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
421 .main_clk = "uart1_fck",
422 .prcm = {
423 .omap2 = {
424 .module_offs = CORE_MOD,
425 .prcm_reg_id = 1,
426 .module_bit = OMAP24XX_EN_UART1_SHIFT,
427 .idlest_reg_id = 1,
428 .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
429 },
430 },
431 .slaves = omap2430_uart1_slaves,
432 .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves),
433 .class = &uart_class,
434 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
435 };
436
437 /* UART2 */
438
439 static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
440 { .irq = INT_24XX_UART2_IRQ, },
441 };
442
443 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
444 { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
445 { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
446 };
447
448 static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = {
449 &omap2_l4_core__uart2,
450 };
451
452 static struct omap_hwmod omap2430_uart2_hwmod = {
453 .name = "uart2",
454 .mpu_irqs = uart2_mpu_irqs,
455 .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs),
456 .sdma_reqs = uart2_sdma_reqs,
457 .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
458 .main_clk = "uart2_fck",
459 .prcm = {
460 .omap2 = {
461 .module_offs = CORE_MOD,
462 .prcm_reg_id = 1,
463 .module_bit = OMAP24XX_EN_UART2_SHIFT,
464 .idlest_reg_id = 1,
465 .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
466 },
467 },
468 .slaves = omap2430_uart2_slaves,
469 .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves),
470 .class = &uart_class,
471 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
472 };
473
474 /* UART3 */
475
476 static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
477 { .irq = INT_24XX_UART3_IRQ, },
478 };
479
480 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
481 { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
482 { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
483 };
484
485 static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = {
486 &omap2_l4_core__uart3,
487 };
488
489 static struct omap_hwmod omap2430_uart3_hwmod = {
490 .name = "uart3",
491 .mpu_irqs = uart3_mpu_irqs,
492 .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs),
493 .sdma_reqs = uart3_sdma_reqs,
494 .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
495 .main_clk = "uart3_fck",
496 .prcm = {
497 .omap2 = {
498 .module_offs = CORE_MOD,
499 .prcm_reg_id = 2,
500 .module_bit = OMAP24XX_EN_UART3_SHIFT,
501 .idlest_reg_id = 2,
502 .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
503 },
504 },
505 .slaves = omap2430_uart3_slaves,
506 .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves),
507 .class = &uart_class,
508 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
509 };
510
511 /* I2C common */
512 static struct omap_hwmod_class_sysconfig i2c_sysc = {
513 .rev_offs = 0x00,
514 .sysc_offs = 0x20,
515 .syss_offs = 0x10,
516 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
517 .sysc_fields = &omap_hwmod_sysc_type1,
518 };
519
520 static struct omap_hwmod_class i2c_class = {
521 .name = "i2c",
522 .sysc = &i2c_sysc,
523 };
524
525 static struct omap_i2c_dev_attr i2c_dev_attr = {
526 .fifo_depth = 8, /* bytes */
527 };
528
529 /* I2C1 */
530
531 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
532 { .irq = INT_24XX_I2C1_IRQ, },
533 };
534
535 static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
536 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
537 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
538 };
539
540 static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
541 &omap2430_l4_core__i2c1,
542 };
543
544 static struct omap_hwmod omap2430_i2c1_hwmod = {
545 .name = "i2c1",
546 .mpu_irqs = i2c1_mpu_irqs,
547 .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs),
548 .sdma_reqs = i2c1_sdma_reqs,
549 .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
550 .main_clk = "i2chs1_fck",
551 .prcm = {
552 .omap2 = {
553 /*
554 * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
555 * I2CHS IP's do not follow the usual pattern.
556 * prcm_reg_id alone cannot be used to program
557 * the iclk and fclk. Needs to be handled using
558 * additonal flags when clk handling is moved
559 * to hwmod framework.
560 */
561 .module_offs = CORE_MOD,
562 .prcm_reg_id = 1,
563 .module_bit = OMAP2430_EN_I2CHS1_SHIFT,
564 .idlest_reg_id = 1,
565 .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
566 },
567 },
568 .slaves = omap2430_i2c1_slaves,
569 .slaves_cnt = ARRAY_SIZE(omap2430_i2c1_slaves),
570 .class = &i2c_class,
571 .dev_attr = &i2c_dev_attr,
572 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
573 };
574
575 /* I2C2 */
576
577 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
578 { .irq = INT_24XX_I2C2_IRQ, },
579 };
580
581 static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
582 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
583 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
584 };
585
586 static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
587 &omap2430_l4_core__i2c2,
588 };
589
590 static struct omap_hwmod omap2430_i2c2_hwmod = {
591 .name = "i2c2",
592 .mpu_irqs = i2c2_mpu_irqs,
593 .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs),
594 .sdma_reqs = i2c2_sdma_reqs,
595 .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
596 .main_clk = "i2chs2_fck",
597 .prcm = {
598 .omap2 = {
599 .module_offs = CORE_MOD,
600 .prcm_reg_id = 1,
601 .module_bit = OMAP2430_EN_I2CHS2_SHIFT,
602 .idlest_reg_id = 1,
603 .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
604 },
605 },
606 .slaves = omap2430_i2c2_slaves,
607 .slaves_cnt = ARRAY_SIZE(omap2430_i2c2_slaves),
608 .class = &i2c_class,
609 .dev_attr = &i2c_dev_attr,
610 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
611 };
612
613 /* l4_wkup -> gpio1 */
614 static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
615 {
616 .pa_start = 0x4900C000,
617 .pa_end = 0x4900C1ff,
618 .flags = ADDR_TYPE_RT
619 },
620 };
621
622 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
623 .master = &omap2430_l4_wkup_hwmod,
624 .slave = &omap2430_gpio1_hwmod,
625 .clk = "gpios_ick",
626 .addr = omap2430_gpio1_addr_space,
627 .addr_cnt = ARRAY_SIZE(omap2430_gpio1_addr_space),
628 .user = OCP_USER_MPU | OCP_USER_SDMA,
629 };
630
631 /* l4_wkup -> gpio2 */
632 static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
633 {
634 .pa_start = 0x4900E000,
635 .pa_end = 0x4900E1ff,
636 .flags = ADDR_TYPE_RT
637 },
638 };
639
640 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
641 .master = &omap2430_l4_wkup_hwmod,
642 .slave = &omap2430_gpio2_hwmod,
643 .clk = "gpios_ick",
644 .addr = omap2430_gpio2_addr_space,
645 .addr_cnt = ARRAY_SIZE(omap2430_gpio2_addr_space),
646 .user = OCP_USER_MPU | OCP_USER_SDMA,
647 };
648
649 /* l4_wkup -> gpio3 */
650 static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
651 {
652 .pa_start = 0x49010000,
653 .pa_end = 0x490101ff,
654 .flags = ADDR_TYPE_RT
655 },
656 };
657
658 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
659 .master = &omap2430_l4_wkup_hwmod,
660 .slave = &omap2430_gpio3_hwmod,
661 .clk = "gpios_ick",
662 .addr = omap2430_gpio3_addr_space,
663 .addr_cnt = ARRAY_SIZE(omap2430_gpio3_addr_space),
664 .user = OCP_USER_MPU | OCP_USER_SDMA,
665 };
666
667 /* l4_wkup -> gpio4 */
668 static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
669 {
670 .pa_start = 0x49012000,
671 .pa_end = 0x490121ff,
672 .flags = ADDR_TYPE_RT
673 },
674 };
675
676 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
677 .master = &omap2430_l4_wkup_hwmod,
678 .slave = &omap2430_gpio4_hwmod,
679 .clk = "gpios_ick",
680 .addr = omap2430_gpio4_addr_space,
681 .addr_cnt = ARRAY_SIZE(omap2430_gpio4_addr_space),
682 .user = OCP_USER_MPU | OCP_USER_SDMA,
683 };
684
685 /* l4_core -> gpio5 */
686 static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
687 {
688 .pa_start = 0x480B6000,
689 .pa_end = 0x480B61ff,
690 .flags = ADDR_TYPE_RT
691 },
692 };
693
694 static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
695 .master = &omap2430_l4_core_hwmod,
696 .slave = &omap2430_gpio5_hwmod,
697 .clk = "gpio5_ick",
698 .addr = omap2430_gpio5_addr_space,
699 .addr_cnt = ARRAY_SIZE(omap2430_gpio5_addr_space),
700 .user = OCP_USER_MPU | OCP_USER_SDMA,
701 };
702
703 /* gpio dev_attr */
704 static struct omap_gpio_dev_attr gpio_dev_attr = {
705 .bank_width = 32,
706 .dbck_flag = false,
707 };
708
709 static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = {
710 .rev_offs = 0x0000,
711 .sysc_offs = 0x0010,
712 .syss_offs = 0x0014,
713 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
714 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
715 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
716 .sysc_fields = &omap_hwmod_sysc_type1,
717 };
718
719 /*
720 * 'gpio' class
721 * general purpose io module
722 */
723 static struct omap_hwmod_class omap243x_gpio_hwmod_class = {
724 .name = "gpio",
725 .sysc = &omap243x_gpio_sysc,
726 .rev = 0,
727 };
728
729 /* gpio1 */
730 static struct omap_hwmod_irq_info omap243x_gpio1_irqs[] = {
731 { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
732 };
733
734 static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
735 &omap2430_l4_wkup__gpio1,
736 };
737
738 static struct omap_hwmod omap2430_gpio1_hwmod = {
739 .name = "gpio1",
740 .mpu_irqs = omap243x_gpio1_irqs,
741 .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio1_irqs),
742 .main_clk = "gpios_fck",
743 .prcm = {
744 .omap2 = {
745 .prcm_reg_id = 1,
746 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
747 .module_offs = WKUP_MOD,
748 .idlest_reg_id = 1,
749 .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT,
750 },
751 },
752 .slaves = omap2430_gpio1_slaves,
753 .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves),
754 .class = &omap243x_gpio_hwmod_class,
755 .dev_attr = &gpio_dev_attr,
756 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
757 };
758
759 /* gpio2 */
760 static struct omap_hwmod_irq_info omap243x_gpio2_irqs[] = {
761 { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
762 };
763
764 static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
765 &omap2430_l4_wkup__gpio2,
766 };
767
768 static struct omap_hwmod omap2430_gpio2_hwmod = {
769 .name = "gpio2",
770 .mpu_irqs = omap243x_gpio2_irqs,
771 .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio2_irqs),
772 .main_clk = "gpios_fck",
773 .prcm = {
774 .omap2 = {
775 .prcm_reg_id = 1,
776 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
777 .module_offs = WKUP_MOD,
778 .idlest_reg_id = 1,
779 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
780 },
781 },
782 .slaves = omap2430_gpio2_slaves,
783 .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves),
784 .class = &omap243x_gpio_hwmod_class,
785 .dev_attr = &gpio_dev_attr,
786 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
787 };
788
789 /* gpio3 */
790 static struct omap_hwmod_irq_info omap243x_gpio3_irqs[] = {
791 { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
792 };
793
794 static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
795 &omap2430_l4_wkup__gpio3,
796 };
797
798 static struct omap_hwmod omap2430_gpio3_hwmod = {
799 .name = "gpio3",
800 .mpu_irqs = omap243x_gpio3_irqs,
801 .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio3_irqs),
802 .main_clk = "gpios_fck",
803 .prcm = {
804 .omap2 = {
805 .prcm_reg_id = 1,
806 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
807 .module_offs = WKUP_MOD,
808 .idlest_reg_id = 1,
809 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
810 },
811 },
812 .slaves = omap2430_gpio3_slaves,
813 .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves),
814 .class = &omap243x_gpio_hwmod_class,
815 .dev_attr = &gpio_dev_attr,
816 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
817 };
818
819 /* gpio4 */
820 static struct omap_hwmod_irq_info omap243x_gpio4_irqs[] = {
821 { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
822 };
823
824 static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
825 &omap2430_l4_wkup__gpio4,
826 };
827
828 static struct omap_hwmod omap2430_gpio4_hwmod = {
829 .name = "gpio4",
830 .mpu_irqs = omap243x_gpio4_irqs,
831 .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio4_irqs),
832 .main_clk = "gpios_fck",
833 .prcm = {
834 .omap2 = {
835 .prcm_reg_id = 1,
836 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
837 .module_offs = WKUP_MOD,
838 .idlest_reg_id = 1,
839 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
840 },
841 },
842 .slaves = omap2430_gpio4_slaves,
843 .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves),
844 .class = &omap243x_gpio_hwmod_class,
845 .dev_attr = &gpio_dev_attr,
846 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
847 };
848
849 /* gpio5 */
850 static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
851 { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
852 };
853
854 static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = {
855 &omap2430_l4_core__gpio5,
856 };
857
858 static struct omap_hwmod omap2430_gpio5_hwmod = {
859 .name = "gpio5",
860 .mpu_irqs = omap243x_gpio5_irqs,
861 .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio5_irqs),
862 .main_clk = "gpio5_fck",
863 .prcm = {
864 .omap2 = {
865 .prcm_reg_id = 2,
866 .module_bit = OMAP2430_EN_GPIO5_SHIFT,
867 .module_offs = CORE_MOD,
868 .idlest_reg_id = 2,
869 .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
870 },
871 },
872 .slaves = omap2430_gpio5_slaves,
873 .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves),
874 .class = &omap243x_gpio_hwmod_class,
875 .dev_attr = &gpio_dev_attr,
876 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
877 };
878
879 /* dma_system */
880 static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = {
881 .rev_offs = 0x0000,
882 .sysc_offs = 0x002c,
883 .syss_offs = 0x0028,
884 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
885 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
886 SYSC_HAS_AUTOIDLE),
887 .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
888 .sysc_fields = &omap_hwmod_sysc_type1,
889 };
890
891 static struct omap_hwmod_class omap2430_dma_hwmod_class = {
892 .name = "dma",
893 .sysc = &omap2430_dma_sysc,
894 };
895
896 /* dma attributes */
897 static struct omap_dma_dev_attr dma_dev_attr = {
898 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
899 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
900 .lch_count = 32,
901 };
902
903 static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = {
904 { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
905 { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
906 { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
907 { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
908 };
909
910 static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = {
911 {
912 .pa_start = 0x48056000,
913 .pa_end = 0x4a0560ff,
914 .flags = ADDR_TYPE_RT
915 },
916 };
917
918 /* dma_system -> L3 */
919 static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
920 .master = &omap2430_dma_system_hwmod,
921 .slave = &omap2430_l3_main_hwmod,
922 .clk = "core_l3_ck",
923 .user = OCP_USER_MPU | OCP_USER_SDMA,
924 };
925
926 /* dma_system master ports */
927 static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = {
928 &omap2430_dma_system__l3,
929 };
930
931 /* l4_core -> dma_system */
932 static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
933 .master = &omap2430_l4_core_hwmod,
934 .slave = &omap2430_dma_system_hwmod,
935 .clk = "sdma_ick",
936 .addr = omap2430_dma_system_addrs,
937 .addr_cnt = ARRAY_SIZE(omap2430_dma_system_addrs),
938 .user = OCP_USER_MPU | OCP_USER_SDMA,
939 };
940
941 /* dma_system slave ports */
942 static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = {
943 &omap2430_l4_core__dma_system,
944 };
945
946 static struct omap_hwmod omap2430_dma_system_hwmod = {
947 .name = "dma",
948 .class = &omap2430_dma_hwmod_class,
949 .mpu_irqs = omap2430_dma_system_irqs,
950 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_dma_system_irqs),
951 .main_clk = "core_l3_ck",
952 .slaves = omap2430_dma_system_slaves,
953 .slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves),
954 .masters = omap2430_dma_system_masters,
955 .masters_cnt = ARRAY_SIZE(omap2430_dma_system_masters),
956 .dev_attr = &dma_dev_attr,
957 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
958 .flags = HWMOD_NO_IDLEST,
959 };
960
961 /*
962 * usbhsotg
963 */
964 static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
965 .rev_offs = 0x0400,
966 .sysc_offs = 0x0404,
967 .syss_offs = 0x0408,
968 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
969 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
970 SYSC_HAS_AUTOIDLE),
971 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
972 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
973 .sysc_fields = &omap_hwmod_sysc_type1,
974 };
975
976 static struct omap_hwmod_class usbotg_class = {
977 .name = "usbotg",
978 .sysc = &omap2430_usbhsotg_sysc,
979 };
980
981 /* usb_otg_hs */
982 static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
983
984 { .name = "mc", .irq = 92 },
985 { .name = "dma", .irq = 93 },
986 };
987
988 static struct omap_hwmod omap2430_usbhsotg_hwmod = {
989 .name = "usb_otg_hs",
990 .mpu_irqs = omap2430_usbhsotg_mpu_irqs,
991 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_usbhsotg_mpu_irqs),
992 .main_clk = "usbhs_ick",
993 .prcm = {
994 .omap2 = {
995 .prcm_reg_id = 1,
996 .module_bit = OMAP2430_EN_USBHS_MASK,
997 .module_offs = CORE_MOD,
998 .idlest_reg_id = 1,
999 .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
1000 },
1001 },
1002 .masters = omap2430_usbhsotg_masters,
1003 .masters_cnt = ARRAY_SIZE(omap2430_usbhsotg_masters),
1004 .slaves = omap2430_usbhsotg_slaves,
1005 .slaves_cnt = ARRAY_SIZE(omap2430_usbhsotg_slaves),
1006 .class = &usbotg_class,
1007 /*
1008 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
1009 * broken when autoidle is enabled
1010 * workaround is to disable the autoidle bit at module level.
1011 */
1012 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
1013 | HWMOD_SWSUP_MSTANDBY,
1014 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
1015 };
1016
1017 static __initdata struct omap_hwmod *omap2430_hwmods[] = {
1018 &omap2430_l3_main_hwmod,
1019 &omap2430_l4_core_hwmod,
1020 &omap2430_l4_wkup_hwmod,
1021 &omap2430_mpu_hwmod,
1022 &omap2430_iva_hwmod,
1023 &omap2430_wd_timer2_hwmod,
1024 &omap2430_uart1_hwmod,
1025 &omap2430_uart2_hwmod,
1026 &omap2430_uart3_hwmod,
1027 &omap2430_i2c1_hwmod,
1028 &omap2430_i2c2_hwmod,
1029
1030 /* gpio class */
1031 &omap2430_gpio1_hwmod,
1032 &omap2430_gpio2_hwmod,
1033 &omap2430_gpio3_hwmod,
1034 &omap2430_gpio4_hwmod,
1035 &omap2430_gpio5_hwmod,
1036
1037 /* dma_system class*/
1038 &omap2430_dma_system_hwmod,
1039
1040 /* usbotg class*/
1041 &omap2430_usbhsotg_hwmod,
1042 NULL,
1043 };
1044
1045 int __init omap2430_hwmod_init(void)
1046 {
1047 return omap_hwmod_init(omap2430_hwmods);
1048 }
Linux kernel - Deliverables
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