arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c

   1 /*
   2  * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
   3  *
   4  * Copyright (C) 2011 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11 #include <plat/omap_hwmod.h>
  12 #include <plat/serial.h>
  13 #include <plat/gpio.h>
  14 #include <plat/dma.h>
  15 #include <plat/dmtimer.h>
  16 #include <plat/mcspi.h>
  17
  18 #include <mach/irqs.h>
  19
  20 #include "omap_hwmod_common_data.h"
  21 #include "cm-regbits-24xx.h"
  22 #include "prm-regbits-24xx.h"
  23 #include "wd_timer.h"
  24
  25 struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
  26         { .irq = 48, },
  27         { .irq = -1 }
  28 };
  29
  30 struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
  31         { .name = "dispc", .dma_req = 5 },
  32         { .dma_req = -1 }
  33 };
  34
  35 /*
  36  * 'dispc' class
  37  * display controller
  38  */
  39
  40 static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
  41         .rev_offs       = 0x0000,
  42         .sysc_offs      = 0x0010,
  43         .syss_offs      = 0x0014,
  44         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
  45                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
  46         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  47                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
  48         .sysc_fields    = &omap_hwmod_sysc_type1,
  49 };
  50
  51 struct omap_hwmod_class omap2_dispc_hwmod_class = {
  52         .name   = "dispc",
  53         .sysc   = &omap2_dispc_sysc,
  54 };
  55
  56 /* OMAP2xxx Timer Common */
  57 static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
  58         .rev_offs       = 0x0000,
  59         .sysc_offs      = 0x0010,
  60         .syss_offs      = 0x0014,
  61         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
  62                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  63                            SYSC_HAS_AUTOIDLE),
  64         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  65         .sysc_fields    = &omap_hwmod_sysc_type1,
  66 };
  67
  68 struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
  69         .name   = "timer",
  70         .sysc   = &omap2xxx_timer_sysc,
  71 };
  72
  73 /*
  74  * 'wd_timer' class
  75  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
  76  * overflow condition
  77  */
  78
  79 static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
  80         .rev_offs       = 0x0000,
  81         .sysc_offs      = 0x0010,
  82         .syss_offs      = 0x0014,
  83         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
  84                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
  85         .sysc_fields    = &omap_hwmod_sysc_type1,
  86 };
  87
  88 struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
  89         .name           = "wd_timer",
  90         .sysc           = &omap2xxx_wd_timer_sysc,
  91         .pre_shutdown   = &omap2_wd_timer_disable,
  92         .reset          = &omap2_wd_timer_reset,
  93 };
  94
  95 /*
  96  * 'gpio' class
  97  * general purpose io module
  98  */
  99 static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
 100         .rev_offs       = 0x0000,
 101         .sysc_offs      = 0x0010,
 102         .syss_offs      = 0x0014,
 103         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 104                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 105                            SYSS_HAS_RESET_STATUS),
 106         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 107         .sysc_fields    = &omap_hwmod_sysc_type1,
 108 };
 109
 110 struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
 111         .name = "gpio",
 112         .sysc = &omap2xxx_gpio_sysc,
 113         .rev = 0,
 114 };
 115
 116 /* system dma */
 117 static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
 118         .rev_offs       = 0x0000,
 119         .sysc_offs      = 0x002c,
 120         .syss_offs      = 0x0028,
 121         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
 122                            SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
 123                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 124         .idlemodes      = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 125         .sysc_fields    = &omap_hwmod_sysc_type1,
 126 };
 127
 128 struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
 129         .name   = "dma",
 130         .sysc   = &omap2xxx_dma_sysc,
 131 };
 132
 133 /*
 134  * 'mailbox' class
 135  * mailbox module allowing communication between the on-chip processors
 136  * using a queued mailbox-interrupt mechanism.
 137  */
 138
 139 static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
 140         .rev_offs       = 0x000,
 141         .sysc_offs      = 0x010,
 142         .syss_offs      = 0x014,
 143         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 144                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 145         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 146         .sysc_fields    = &omap_hwmod_sysc_type1,
 147 };
 148
 149 struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
 150         .name   = "mailbox",
 151         .sysc   = &omap2xxx_mailbox_sysc,
 152 };
 153
 154 /*
 155  * 'mcspi' class
 156  * multichannel serial port interface (mcspi) / master/slave synchronous serial
 157  * bus
 158  */
 159
 160 static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
 161         .rev_offs       = 0x0000,
 162         .sysc_offs      = 0x0010,
 163         .syss_offs      = 0x0014,
 164         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 165                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 166                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 167         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 168         .sysc_fields    = &omap_hwmod_sysc_type1,
 169 };
 170
 171 struct omap_hwmod_class omap2xxx_mcspi_class = {
 172         .name   = "mcspi",
 173         .sysc   = &omap2xxx_mcspi_sysc,
 174         .rev    = OMAP2_MCSPI_REV,
 175 };
 176
 177 /*
 178  * IP blocks
 179  */
 180
 181 /* L3 */
 182 struct omap_hwmod omap2xxx_l3_main_hwmod = {
 183         .name           = "l3_main",
 184         .class          = &l3_hwmod_class,
 185         .flags          = HWMOD_NO_IDLEST,
 186 };
 187
 188 /* L4 CORE */
 189 struct omap_hwmod omap2xxx_l4_core_hwmod = {
 190         .name           = "l4_core",
 191         .class          = &l4_hwmod_class,
 192         .flags          = HWMOD_NO_IDLEST,
 193 };
 194
 195 /* L4 WKUP */
 196 struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
 197         .name           = "l4_wkup",
 198         .class          = &l4_hwmod_class,
 199         .flags          = HWMOD_NO_IDLEST,
 200 };
 201
 202 /* MPU */
 203 struct omap_hwmod omap2xxx_mpu_hwmod = {
 204         .name           = "mpu",
 205         .class          = &mpu_hwmod_class,
 206         .main_clk       = "mpu_ck",
 207 };
 208
 209 /* IVA2 */
 210 struct omap_hwmod omap2xxx_iva_hwmod = {
 211         .name           = "iva",
 212         .class          = &iva_hwmod_class,
 213 };
 214
 215 /* always-on timers dev attribute */
 216 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 217         .timer_capability       = OMAP_TIMER_ALWON,
 218 };
 219
 220 /* pwm timers dev attribute */
 221 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 222         .timer_capability       = OMAP_TIMER_HAS_PWM,
 223 };
 224
 225 /* timer1 */
 226
 227 struct omap_hwmod omap2xxx_timer1_hwmod = {
 228         .name           = "timer1",
 229         .mpu_irqs       = omap2_timer1_mpu_irqs,
 230         .main_clk       = "gpt1_fck",
 231         .prcm           = {
 232                 .omap2 = {
 233                         .prcm_reg_id = 1,
 234                         .module_bit = OMAP24XX_EN_GPT1_SHIFT,
 235                         .module_offs = WKUP_MOD,
 236                         .idlest_reg_id = 1,
 237                         .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
 238                 },
 239         },
 240         .dev_attr       = &capability_alwon_dev_attr,
 241         .class          = &omap2xxx_timer_hwmod_class,
 242 };
 243
 244 /* timer2 */
 245
 246 struct omap_hwmod omap2xxx_timer2_hwmod = {
 247         .name           = "timer2",
 248         .mpu_irqs       = omap2_timer2_mpu_irqs,
 249         .main_clk       = "gpt2_fck",
 250         .prcm           = {
 251                 .omap2 = {
 252                         .prcm_reg_id = 1,
 253                         .module_bit = OMAP24XX_EN_GPT2_SHIFT,
 254                         .module_offs = CORE_MOD,
 255                         .idlest_reg_id = 1,
 256                         .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
 257                 },
 258         },
 259         .class          = &omap2xxx_timer_hwmod_class,
 260 };
 261
 262 /* timer3 */
 263
 264 struct omap_hwmod omap2xxx_timer3_hwmod = {
 265         .name           = "timer3",
 266         .mpu_irqs       = omap2_timer3_mpu_irqs,
 267         .main_clk       = "gpt3_fck",
 268         .prcm           = {
 269                 .omap2 = {
 270                         .prcm_reg_id = 1,
 271                         .module_bit = OMAP24XX_EN_GPT3_SHIFT,
 272                         .module_offs = CORE_MOD,
 273                         .idlest_reg_id = 1,
 274                         .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
 275                 },
 276         },
 277         .class          = &omap2xxx_timer_hwmod_class,
 278 };
 279
 280 /* timer4 */
 281
 282 struct omap_hwmod omap2xxx_timer4_hwmod = {
 283         .name           = "timer4",
 284         .mpu_irqs       = omap2_timer4_mpu_irqs,
 285         .main_clk       = "gpt4_fck",
 286         .prcm           = {
 287                 .omap2 = {
 288                         .prcm_reg_id = 1,
 289                         .module_bit = OMAP24XX_EN_GPT4_SHIFT,
 290                         .module_offs = CORE_MOD,
 291                         .idlest_reg_id = 1,
 292                         .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
 293                 },
 294         },
 295         .class          = &omap2xxx_timer_hwmod_class,
 296 };
 297
 298 /* timer5 */
 299
 300 struct omap_hwmod omap2xxx_timer5_hwmod = {
 301         .name           = "timer5",
 302         .mpu_irqs       = omap2_timer5_mpu_irqs,
 303         .main_clk       = "gpt5_fck",
 304         .prcm           = {
 305                 .omap2 = {
 306                         .prcm_reg_id = 1,
 307                         .module_bit = OMAP24XX_EN_GPT5_SHIFT,
 308                         .module_offs = CORE_MOD,
 309                         .idlest_reg_id = 1,
 310                         .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
 311                 },
 312         },
 313         .class          = &omap2xxx_timer_hwmod_class,
 314 };
 315
 316 /* timer6 */
 317
 318 struct omap_hwmod omap2xxx_timer6_hwmod = {
 319         .name           = "timer6",
 320         .mpu_irqs       = omap2_timer6_mpu_irqs,
 321         .main_clk       = "gpt6_fck",
 322         .prcm           = {
 323                 .omap2 = {
 324                         .prcm_reg_id = 1,
 325                         .module_bit = OMAP24XX_EN_GPT6_SHIFT,
 326                         .module_offs = CORE_MOD,
 327                         .idlest_reg_id = 1,
 328                         .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
 329                 },
 330         },
 331         .class          = &omap2xxx_timer_hwmod_class,
 332 };
 333
 334 /* timer7 */
 335
 336 struct omap_hwmod omap2xxx_timer7_hwmod = {
 337         .name           = "timer7",
 338         .mpu_irqs       = omap2_timer7_mpu_irqs,
 339         .main_clk       = "gpt7_fck",
 340         .prcm           = {
 341                 .omap2 = {
 342                         .prcm_reg_id = 1,
 343                         .module_bit = OMAP24XX_EN_GPT7_SHIFT,
 344                         .module_offs = CORE_MOD,
 345                         .idlest_reg_id = 1,
 346                         .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
 347                 },
 348         },
 349         .class          = &omap2xxx_timer_hwmod_class,
 350 };
 351
 352 /* timer8 */
 353
 354 struct omap_hwmod omap2xxx_timer8_hwmod = {
 355         .name           = "timer8",
 356         .mpu_irqs       = omap2_timer8_mpu_irqs,
 357         .main_clk       = "gpt8_fck",
 358         .prcm           = {
 359                 .omap2 = {
 360                         .prcm_reg_id = 1,
 361                         .module_bit = OMAP24XX_EN_GPT8_SHIFT,
 362                         .module_offs = CORE_MOD,
 363                         .idlest_reg_id = 1,
 364                         .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
 365                 },
 366         },
 367         .class          = &omap2xxx_timer_hwmod_class,
 368 };
 369
 370 /* timer9 */
 371
 372 struct omap_hwmod omap2xxx_timer9_hwmod = {
 373         .name           = "timer9",
 374         .mpu_irqs       = omap2_timer9_mpu_irqs,
 375         .main_clk       = "gpt9_fck",
 376         .prcm           = {
 377                 .omap2 = {
 378                         .prcm_reg_id = 1,
 379                         .module_bit = OMAP24XX_EN_GPT9_SHIFT,
 380                         .module_offs = CORE_MOD,
 381                         .idlest_reg_id = 1,
 382                         .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
 383                 },
 384         },
 385         .dev_attr       = &capability_pwm_dev_attr,
 386         .class          = &omap2xxx_timer_hwmod_class,
 387 };
 388
 389 /* timer10 */
 390
 391 struct omap_hwmod omap2xxx_timer10_hwmod = {
 392         .name           = "timer10",
 393         .mpu_irqs       = omap2_timer10_mpu_irqs,
 394         .main_clk       = "gpt10_fck",
 395         .prcm           = {
 396                 .omap2 = {
 397                         .prcm_reg_id = 1,
 398                         .module_bit = OMAP24XX_EN_GPT10_SHIFT,
 399                         .module_offs = CORE_MOD,
 400                         .idlest_reg_id = 1,
 401                         .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
 402                 },
 403         },
 404         .dev_attr       = &capability_pwm_dev_attr,
 405         .class          = &omap2xxx_timer_hwmod_class,
 406 };
 407
 408 /* timer11 */
 409
 410 struct omap_hwmod omap2xxx_timer11_hwmod = {
 411         .name           = "timer11",
 412         .mpu_irqs       = omap2_timer11_mpu_irqs,
 413         .main_clk       = "gpt11_fck",
 414         .prcm           = {
 415                 .omap2 = {
 416                         .prcm_reg_id = 1,
 417                         .module_bit = OMAP24XX_EN_GPT11_SHIFT,
 418                         .module_offs = CORE_MOD,
 419                         .idlest_reg_id = 1,
 420                         .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
 421                 },
 422         },
 423         .dev_attr       = &capability_pwm_dev_attr,
 424         .class          = &omap2xxx_timer_hwmod_class,
 425 };
 426
 427 /* timer12 */
 428
 429 struct omap_hwmod omap2xxx_timer12_hwmod = {
 430         .name           = "timer12",
 431         .mpu_irqs       = omap2xxx_timer12_mpu_irqs,
 432         .main_clk       = "gpt12_fck",
 433         .prcm           = {
 434                 .omap2 = {
 435                         .prcm_reg_id = 1,
 436                         .module_bit = OMAP24XX_EN_GPT12_SHIFT,
 437                         .module_offs = CORE_MOD,
 438                         .idlest_reg_id = 1,
 439                         .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
 440                 },
 441         },
 442         .dev_attr       = &capability_pwm_dev_attr,
 443         .class          = &omap2xxx_timer_hwmod_class,
 444 };
 445
 446 /* wd_timer2 */
 447 struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
 448         .name           = "wd_timer2",
 449         .class          = &omap2xxx_wd_timer_hwmod_class,
 450         .main_clk       = "mpu_wdt_fck",
 451         .prcm           = {
 452                 .omap2 = {
 453                         .prcm_reg_id = 1,
 454                         .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
 455                         .module_offs = WKUP_MOD,
 456                         .idlest_reg_id = 1,
 457                         .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
 458                 },
 459         },
 460 };
 461
 462 /* UART1 */
 463
 464 struct omap_hwmod omap2xxx_uart1_hwmod = {
 465         .name           = "uart1",
 466         .mpu_irqs       = omap2_uart1_mpu_irqs,
 467         .sdma_reqs      = omap2_uart1_sdma_reqs,
 468         .main_clk       = "uart1_fck",
 469         .prcm           = {
 470                 .omap2 = {
 471                         .module_offs = CORE_MOD,
 472                         .prcm_reg_id = 1,
 473                         .module_bit = OMAP24XX_EN_UART1_SHIFT,
 474                         .idlest_reg_id = 1,
 475                         .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
 476                 },
 477         },
 478         .class          = &omap2_uart_class,
 479 };
 480
 481 /* UART2 */
 482
 483 struct omap_hwmod omap2xxx_uart2_hwmod = {
 484         .name           = "uart2",
 485         .mpu_irqs       = omap2_uart2_mpu_irqs,
 486         .sdma_reqs      = omap2_uart2_sdma_reqs,
 487         .main_clk       = "uart2_fck",
 488         .prcm           = {
 489                 .omap2 = {
 490                         .module_offs = CORE_MOD,
 491                         .prcm_reg_id = 1,
 492                         .module_bit = OMAP24XX_EN_UART2_SHIFT,
 493                         .idlest_reg_id = 1,
 494                         .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
 495                 },
 496         },
 497         .class          = &omap2_uart_class,
 498 };
 499
 500 /* UART3 */
 501
 502 struct omap_hwmod omap2xxx_uart3_hwmod = {
 503         .name           = "uart3",
 504         .mpu_irqs       = omap2_uart3_mpu_irqs,
 505         .sdma_reqs      = omap2_uart3_sdma_reqs,
 506         .main_clk       = "uart3_fck",
 507         .prcm           = {
 508                 .omap2 = {
 509                         .module_offs = CORE_MOD,
 510                         .prcm_reg_id = 2,
 511                         .module_bit = OMAP24XX_EN_UART3_SHIFT,
 512                         .idlest_reg_id = 2,
 513                         .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
 514                 },
 515         },
 516         .class          = &omap2_uart_class,
 517 };
 518
 519 /* dss */
 520
 521 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 522         /*
 523          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
 524          * driver does not use these clocks.
 525          */
 526         { .role = "tv_clk", .clk = "dss_54m_fck" },
 527         { .role = "sys_clk", .clk = "dss2_fck" },
 528 };
 529
 530 struct omap_hwmod omap2xxx_dss_core_hwmod = {
 531         .name           = "dss_core",
 532         .class          = &omap2_dss_hwmod_class,
 533         .main_clk       = "dss1_fck", /* instead of dss_fck */
 534         .sdma_reqs      = omap2xxx_dss_sdma_chs,
 535         .prcm           = {
 536                 .omap2 = {
 537                         .prcm_reg_id = 1,
 538                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 539                         .module_offs = CORE_MOD,
 540                         .idlest_reg_id = 1,
 541                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
 542                 },
 543         },
 544         .opt_clks       = dss_opt_clks,
 545         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 546         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 547 };
 548
 549 struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
 550         .name           = "dss_dispc",
 551         .class          = &omap2_dispc_hwmod_class,
 552         .mpu_irqs       = omap2_dispc_irqs,
 553         .main_clk       = "dss1_fck",
 554         .prcm           = {
 555                 .omap2 = {
 556                         .prcm_reg_id = 1,
 557                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 558                         .module_offs = CORE_MOD,
 559                         .idlest_reg_id = 1,
 560                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
 561                 },
 562         },
 563         .flags          = HWMOD_NO_IDLEST,
 564         .dev_attr       = &omap2_3_dss_dispc_dev_attr
 565 };
 566
 567 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 568         { .role = "ick", .clk = "dss_ick" },
 569 };
 570
 571 struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
 572         .name           = "dss_rfbi",
 573         .class          = &omap2_rfbi_hwmod_class,
 574         .main_clk       = "dss1_fck",
 575         .prcm           = {
 576                 .omap2 = {
 577                         .prcm_reg_id = 1,
 578                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 579                         .module_offs = CORE_MOD,
 580                 },
 581         },
 582         .opt_clks       = dss_rfbi_opt_clks,
 583         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 584         .flags          = HWMOD_NO_IDLEST,
 585 };
 586
 587 struct omap_hwmod omap2xxx_dss_venc_hwmod = {
 588         .name           = "dss_venc",
 589         .class          = &omap2_venc_hwmod_class,
 590         .main_clk       = "dss_54m_fck",
 591         .prcm           = {
 592                 .omap2 = {
 593                         .prcm_reg_id = 1,
 594                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 595                         .module_offs = CORE_MOD,
 596                 },
 597         },
 598         .flags          = HWMOD_NO_IDLEST,
 599 };
 600
 601 /* gpio dev_attr */
 602 struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {
 603         .bank_width = 32,
 604         .dbck_flag = false,
 605 };
 606
 607 /* gpio1 */
 608 struct omap_hwmod omap2xxx_gpio1_hwmod = {
 609         .name           = "gpio1",
 610         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 611         .mpu_irqs       = omap2_gpio1_irqs,
 612         .main_clk       = "gpios_fck",
 613         .prcm           = {
 614                 .omap2 = {
 615                         .prcm_reg_id = 1,
 616                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
 617                         .module_offs = WKUP_MOD,
 618                         .idlest_reg_id = 1,
 619                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 620                 },
 621         },
 622         .class          = &omap2xxx_gpio_hwmod_class,
 623         .dev_attr       = &omap2xxx_gpio_dev_attr,
 624 };
 625
 626 /* gpio2 */
 627 struct omap_hwmod omap2xxx_gpio2_hwmod = {
 628         .name           = "gpio2",
 629         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 630         .mpu_irqs       = omap2_gpio2_irqs,
 631         .main_clk       = "gpios_fck",
 632         .prcm           = {
 633                 .omap2 = {
 634                         .prcm_reg_id = 1,
 635                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
 636                         .module_offs = WKUP_MOD,
 637                         .idlest_reg_id = 1,
 638                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 639                 },
 640         },
 641         .class          = &omap2xxx_gpio_hwmod_class,
 642         .dev_attr       = &omap2xxx_gpio_dev_attr,
 643 };
 644
 645 /* gpio3 */
 646 struct omap_hwmod omap2xxx_gpio3_hwmod = {
 647         .name           = "gpio3",
 648         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 649         .mpu_irqs       = omap2_gpio3_irqs,
 650         .main_clk       = "gpios_fck",
 651         .prcm           = {
 652                 .omap2 = {
 653                         .prcm_reg_id = 1,
 654                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
 655                         .module_offs = WKUP_MOD,
 656                         .idlest_reg_id = 1,
 657                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 658                 },
 659         },
 660         .class          = &omap2xxx_gpio_hwmod_class,
 661         .dev_attr       = &omap2xxx_gpio_dev_attr,
 662 };
 663
 664 /* gpio4 */
 665 struct omap_hwmod omap2xxx_gpio4_hwmod = {
 666         .name           = "gpio4",
 667         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 668         .mpu_irqs       = omap2_gpio4_irqs,
 669         .main_clk       = "gpios_fck",
 670         .prcm           = {
 671                 .omap2 = {
 672                         .prcm_reg_id = 1,
 673                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
 674                         .module_offs = WKUP_MOD,
 675                         .idlest_reg_id = 1,
 676                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 677                 },
 678         },
 679         .class          = &omap2xxx_gpio_hwmod_class,
 680         .dev_attr       = &omap2xxx_gpio_dev_attr,
 681 };
 682
 683 /* mcspi1 */
 684 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
 685         .num_chipselect = 4,
 686 };
 687
 688 struct omap_hwmod omap2xxx_mcspi1_hwmod = {
 689         .name           = "mcspi1",
 690         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
 691         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
 692         .main_clk       = "mcspi1_fck",
 693         .prcm           = {
 694                 .omap2 = {
 695                         .module_offs = CORE_MOD,
 696                         .prcm_reg_id = 1,
 697                         .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
 698                         .idlest_reg_id = 1,
 699                         .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
 700                 },
 701         },
 702         .class          = &omap2xxx_mcspi_class,
 703         .dev_attr       = &omap_mcspi1_dev_attr,
 704 };
 705
 706 /* mcspi2 */
 707 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
 708         .num_chipselect = 2,
 709 };
 710
 711 struct omap_hwmod omap2xxx_mcspi2_hwmod = {
 712         .name           = "mcspi2",
 713         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
 714         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
 715         .main_clk       = "mcspi2_fck",
 716         .prcm           = {
 717                 .omap2 = {
 718                         .module_offs = CORE_MOD,
 719                         .prcm_reg_id = 1,
 720                         .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
 721                         .idlest_reg_id = 1,
 722                         .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
 723                 },
 724         },
 725         .class          = &omap2xxx_mcspi_class,
 726         .dev_attr       = &omap_mcspi2_dev_attr,
 727 };
 728
 729
 730 static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
 731         .name   = "counter",
 732 };
 733
 734 struct omap_hwmod omap2xxx_counter_32k_hwmod = {
 735         .name           = "counter_32k",
 736         .main_clk       = "func_32k_ck",
 737         .prcm           = {
 738                 .omap2  = {
 739                         .module_offs = WKUP_MOD,
 740                         .prcm_reg_id = 1,
 741                         .module_bit = OMAP24XX_ST_32KSYNC_SHIFT,
 742                         .idlest_reg_id = 1,
 743                         .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
 744                 },
 745         },
 746         .class          = &omap2xxx_counter_hwmod_class,
 747 };