3 * Copyright (C) 2013 Texas Instruments Incorporated
5 * Hwmod common for AM335x and AM43x
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/platform_data/gpio-omap.h>
18 #include <linux/platform_data/hsmmc-omap.h>
19 #include <linux/platform_data/spi-omap2-mcspi.h>
20 #include "omap_hwmod.h"
25 #include "omap_hwmod_33xx_43xx_common_data.h"
29 #define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
30 #define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
31 #define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
35 * instance(s): l3_main, l3_s, l3_instr
37 static struct omap_hwmod_class am33xx_l3_hwmod_class
= {
41 struct omap_hwmod am33xx_l3_main_hwmod
= {
43 .class = &am33xx_l3_hwmod_class
,
44 .clkdm_name
= "l3_clkdm",
45 .flags
= HWMOD_INIT_NO_IDLE
,
46 .main_clk
= "l3_gclk",
49 .modulemode
= MODULEMODE_SWCTRL
,
55 struct omap_hwmod am33xx_l3_s_hwmod
= {
57 .class = &am33xx_l3_hwmod_class
,
58 .clkdm_name
= "l3s_clkdm",
62 struct omap_hwmod am33xx_l3_instr_hwmod
= {
64 .class = &am33xx_l3_hwmod_class
,
65 .clkdm_name
= "l3_clkdm",
66 .flags
= HWMOD_INIT_NO_IDLE
,
67 .main_clk
= "l3_gclk",
70 .modulemode
= MODULEMODE_SWCTRL
,
77 * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
79 struct omap_hwmod_class am33xx_l4_hwmod_class
= {
84 struct omap_hwmod am33xx_l4_ls_hwmod
= {
86 .class = &am33xx_l4_hwmod_class
,
87 .clkdm_name
= "l4ls_clkdm",
88 .flags
= HWMOD_INIT_NO_IDLE
,
89 .main_clk
= "l4ls_gclk",
92 .modulemode
= MODULEMODE_SWCTRL
,
98 struct omap_hwmod am33xx_l4_wkup_hwmod
= {
100 .class = &am33xx_l4_hwmod_class
,
101 .clkdm_name
= "l4_wkup_clkdm",
102 .flags
= HWMOD_INIT_NO_IDLE
,
105 .modulemode
= MODULEMODE_SWCTRL
,
113 static struct omap_hwmod_class am33xx_mpu_hwmod_class
= {
117 struct omap_hwmod am33xx_mpu_hwmod
= {
119 .class = &am33xx_mpu_hwmod_class
,
120 .clkdm_name
= "mpu_clkdm",
121 .flags
= HWMOD_INIT_NO_IDLE
,
122 .main_clk
= "dpll_mpu_m2_ck",
125 .modulemode
= MODULEMODE_SWCTRL
,
132 * Wakeup controller sub-system under wakeup domain
134 struct omap_hwmod_class am33xx_wkup_m3_hwmod_class
= {
140 * Programmable Real-Time Unit and Industrial Communication Subsystem
142 static struct omap_hwmod_class am33xx_pruss_hwmod_class
= {
146 static struct omap_hwmod_rst_info am33xx_pruss_resets
[] = {
147 { .name
= "pruss", .rst_shift
= 1 },
151 /* Pseudo hwmod for reset control purpose only */
152 struct omap_hwmod am33xx_pruss_hwmod
= {
154 .class = &am33xx_pruss_hwmod_class
,
155 .clkdm_name
= "pruss_ocp_clkdm",
156 .main_clk
= "pruss_ocp_gclk",
159 .modulemode
= MODULEMODE_SWCTRL
,
162 .rst_lines
= am33xx_pruss_resets
,
163 .rst_lines_cnt
= ARRAY_SIZE(am33xx_pruss_resets
),
167 /* Pseudo hwmod for reset control purpose only */
168 static struct omap_hwmod_class am33xx_gfx_hwmod_class
= {
172 static struct omap_hwmod_rst_info am33xx_gfx_resets
[] = {
173 { .name
= "gfx", .rst_shift
= 0, .st_shift
= 0},
176 struct omap_hwmod am33xx_gfx_hwmod
= {
178 .class = &am33xx_gfx_hwmod_class
,
179 .clkdm_name
= "gfx_l3_clkdm",
180 .main_clk
= "gfx_fck_div_ck",
183 .modulemode
= MODULEMODE_SWCTRL
,
186 .rst_lines
= am33xx_gfx_resets
,
187 .rst_lines_cnt
= ARRAY_SIZE(am33xx_gfx_resets
),
192 * power and reset manager (whole prcm infrastructure)
194 static struct omap_hwmod_class am33xx_prcm_hwmod_class
= {
199 struct omap_hwmod am33xx_prcm_hwmod
= {
201 .class = &am33xx_prcm_hwmod_class
,
202 .clkdm_name
= "l4_wkup_clkdm",
209 static struct omap_hwmod_class_sysconfig am33xx_emif_sysc
= {
213 struct omap_hwmod_class am33xx_emif_hwmod_class
= {
215 .sysc
= &am33xx_emif_sysc
,
221 static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc
= {
225 .sysc_flags
= SYSS_HAS_RESET_STATUS
,
228 static struct omap_hwmod_class am33xx_aes0_hwmod_class
= {
230 .sysc
= &am33xx_aes0_sysc
,
233 struct omap_hwmod am33xx_aes0_hwmod
= {
235 .class = &am33xx_aes0_hwmod_class
,
236 .clkdm_name
= "l3_clkdm",
237 .main_clk
= "aes0_fck",
240 .modulemode
= MODULEMODE_SWCTRL
,
245 /* sha0 HIB2 (the 'P' (public) device) */
246 static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc
= {
250 .sysc_flags
= SYSS_HAS_RESET_STATUS
,
253 static struct omap_hwmod_class am33xx_sha0_hwmod_class
= {
255 .sysc
= &am33xx_sha0_sysc
,
258 struct omap_hwmod am33xx_sha0_hwmod
= {
260 .class = &am33xx_sha0_hwmod_class
,
261 .clkdm_name
= "l3_clkdm",
262 .main_clk
= "l3_gclk",
265 .modulemode
= MODULEMODE_SWCTRL
,
271 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class
= {
275 struct omap_hwmod am33xx_ocmcram_hwmod
= {
277 .class = &am33xx_ocmcram_hwmod_class
,
278 .clkdm_name
= "l3_clkdm",
279 .flags
= HWMOD_INIT_NO_IDLE
,
280 .main_clk
= "l3_gclk",
283 .modulemode
= MODULEMODE_SWCTRL
,
288 /* 'smartreflex' class */
289 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class
= {
290 .name
= "smartreflex",
294 struct omap_hwmod am33xx_smartreflex0_hwmod
= {
295 .name
= "smartreflex0",
296 .class = &am33xx_smartreflex_hwmod_class
,
297 .clkdm_name
= "l4_wkup_clkdm",
298 .main_clk
= "smartreflex0_fck",
301 .modulemode
= MODULEMODE_SWCTRL
,
307 struct omap_hwmod am33xx_smartreflex1_hwmod
= {
308 .name
= "smartreflex1",
309 .class = &am33xx_smartreflex_hwmod_class
,
310 .clkdm_name
= "l4_wkup_clkdm",
311 .main_clk
= "smartreflex1_fck",
314 .modulemode
= MODULEMODE_SWCTRL
,
320 * 'control' module class
322 struct omap_hwmod_class am33xx_control_hwmod_class
= {
328 * cpsw/cpgmac sub system
330 static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc
= {
334 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_MIDLEMODE
|
335 SYSS_HAS_RESET_STATUS
),
336 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| MSTANDBY_FORCE
|
338 .sysc_fields
= &omap_hwmod_sysc_type3
,
341 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class
= {
343 .sysc
= &am33xx_cpgmac_sysc
,
346 struct omap_hwmod am33xx_cpgmac0_hwmod
= {
348 .class = &am33xx_cpgmac0_hwmod_class
,
349 .clkdm_name
= "cpsw_125mhz_clkdm",
350 .flags
= (HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
),
351 .main_clk
= "cpsw_125mhz_gclk",
355 .modulemode
= MODULEMODE_SWCTRL
,
363 static struct omap_hwmod_class am33xx_mdio_hwmod_class
= {
364 .name
= "davinci_mdio",
367 struct omap_hwmod am33xx_mdio_hwmod
= {
368 .name
= "davinci_mdio",
369 .class = &am33xx_mdio_hwmod_class
,
370 .clkdm_name
= "cpsw_125mhz_clkdm",
371 .main_clk
= "cpsw_125mhz_gclk",
377 static struct omap_hwmod_class am33xx_dcan_hwmod_class
= {
382 struct omap_hwmod am33xx_dcan0_hwmod
= {
384 .class = &am33xx_dcan_hwmod_class
,
385 .clkdm_name
= "l4ls_clkdm",
386 .main_clk
= "dcan0_fck",
389 .modulemode
= MODULEMODE_SWCTRL
,
395 struct omap_hwmod am33xx_dcan1_hwmod
= {
397 .class = &am33xx_dcan_hwmod_class
,
398 .clkdm_name
= "l4ls_clkdm",
399 .main_clk
= "dcan1_fck",
402 .modulemode
= MODULEMODE_SWCTRL
,
408 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc
= {
412 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
413 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
|
414 SYSS_HAS_RESET_STATUS
),
415 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
416 .sysc_fields
= &omap_hwmod_sysc_type1
,
419 static struct omap_hwmod_class am33xx_elm_hwmod_class
= {
421 .sysc
= &am33xx_elm_sysc
,
424 struct omap_hwmod am33xx_elm_hwmod
= {
426 .class = &am33xx_elm_hwmod_class
,
427 .clkdm_name
= "l4ls_clkdm",
428 .main_clk
= "l4ls_gclk",
431 .modulemode
= MODULEMODE_SWCTRL
,
437 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc
= {
440 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_MIDLEMODE
),
441 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
442 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
443 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
444 .sysc_fields
= &omap_hwmod_sysc_type2
,
447 struct omap_hwmod_class am33xx_epwmss_hwmod_class
= {
449 .sysc
= &am33xx_epwmss_sysc
,
453 struct omap_hwmod am33xx_epwmss0_hwmod
= {
455 .class = &am33xx_epwmss_hwmod_class
,
456 .clkdm_name
= "l4ls_clkdm",
457 .main_clk
= "l4ls_gclk",
460 .modulemode
= MODULEMODE_SWCTRL
,
466 struct omap_hwmod am33xx_epwmss1_hwmod
= {
468 .class = &am33xx_epwmss_hwmod_class
,
469 .clkdm_name
= "l4ls_clkdm",
470 .main_clk
= "l4ls_gclk",
473 .modulemode
= MODULEMODE_SWCTRL
,
479 struct omap_hwmod am33xx_epwmss2_hwmod
= {
481 .class = &am33xx_epwmss_hwmod_class
,
482 .clkdm_name
= "l4ls_clkdm",
483 .main_clk
= "l4ls_gclk",
486 .modulemode
= MODULEMODE_SWCTRL
,
492 * 'gpio' class: for gpio 0,1,2,3
494 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc
= {
498 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
499 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
500 SYSS_HAS_RESET_STATUS
),
501 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
503 .sysc_fields
= &omap_hwmod_sysc_type1
,
506 struct omap_hwmod_class am33xx_gpio_hwmod_class
= {
508 .sysc
= &am33xx_gpio_sysc
,
512 struct omap_gpio_dev_attr gpio_dev_attr
= {
518 static struct omap_hwmod_opt_clk gpio1_opt_clks
[] = {
519 { .role
= "dbclk", .clk
= "gpio1_dbclk" },
522 struct omap_hwmod am33xx_gpio1_hwmod
= {
524 .class = &am33xx_gpio_hwmod_class
,
525 .clkdm_name
= "l4ls_clkdm",
526 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
527 .main_clk
= "l4ls_gclk",
530 .modulemode
= MODULEMODE_SWCTRL
,
533 .opt_clks
= gpio1_opt_clks
,
534 .opt_clks_cnt
= ARRAY_SIZE(gpio1_opt_clks
),
535 .dev_attr
= &gpio_dev_attr
,
539 static struct omap_hwmod_opt_clk gpio2_opt_clks
[] = {
540 { .role
= "dbclk", .clk
= "gpio2_dbclk" },
543 struct omap_hwmod am33xx_gpio2_hwmod
= {
545 .class = &am33xx_gpio_hwmod_class
,
546 .clkdm_name
= "l4ls_clkdm",
547 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
548 .main_clk
= "l4ls_gclk",
551 .modulemode
= MODULEMODE_SWCTRL
,
554 .opt_clks
= gpio2_opt_clks
,
555 .opt_clks_cnt
= ARRAY_SIZE(gpio2_opt_clks
),
556 .dev_attr
= &gpio_dev_attr
,
560 static struct omap_hwmod_opt_clk gpio3_opt_clks
[] = {
561 { .role
= "dbclk", .clk
= "gpio3_dbclk" },
564 struct omap_hwmod am33xx_gpio3_hwmod
= {
566 .class = &am33xx_gpio_hwmod_class
,
567 .clkdm_name
= "l4ls_clkdm",
568 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
569 .main_clk
= "l4ls_gclk",
572 .modulemode
= MODULEMODE_SWCTRL
,
575 .opt_clks
= gpio3_opt_clks
,
576 .opt_clks_cnt
= ARRAY_SIZE(gpio3_opt_clks
),
577 .dev_attr
= &gpio_dev_attr
,
581 static struct omap_hwmod_class_sysconfig gpmc_sysc
= {
585 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SIDLEMODE
|
586 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
587 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
588 .sysc_fields
= &omap_hwmod_sysc_type1
,
591 static struct omap_hwmod_class am33xx_gpmc_hwmod_class
= {
596 struct omap_hwmod am33xx_gpmc_hwmod
= {
598 .class = &am33xx_gpmc_hwmod_class
,
599 .clkdm_name
= "l3s_clkdm",
600 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
601 .flags
= DEBUG_OMAP_GPMC_HWMOD_FLAGS
,
602 .main_clk
= "l3s_gclk",
605 .modulemode
= MODULEMODE_SWCTRL
,
611 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc
= {
614 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
615 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
616 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
617 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
619 .sysc_fields
= &omap_hwmod_sysc_type1
,
622 static struct omap_hwmod_class i2c_class
= {
624 .sysc
= &am33xx_i2c_sysc
,
625 .rev
= OMAP_I2C_IP_VERSION_2
,
626 .reset
= &omap_i2c_reset
,
629 static struct omap_i2c_dev_attr i2c_dev_attr
= {
630 .flags
= OMAP_I2C_FLAG_BUS_SHIFT_NONE
,
634 struct omap_hwmod am33xx_i2c1_hwmod
= {
637 .clkdm_name
= "l4_wkup_clkdm",
638 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
639 .main_clk
= "dpll_per_m2_div4_wkupdm_ck",
642 .modulemode
= MODULEMODE_SWCTRL
,
645 .dev_attr
= &i2c_dev_attr
,
649 struct omap_hwmod am33xx_i2c2_hwmod
= {
652 .clkdm_name
= "l4ls_clkdm",
653 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
654 .main_clk
= "dpll_per_m2_div4_ck",
657 .modulemode
= MODULEMODE_SWCTRL
,
660 .dev_attr
= &i2c_dev_attr
,
664 struct omap_hwmod am33xx_i2c3_hwmod
= {
667 .clkdm_name
= "l4ls_clkdm",
668 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
669 .main_clk
= "dpll_per_m2_div4_ck",
672 .modulemode
= MODULEMODE_SWCTRL
,
675 .dev_attr
= &i2c_dev_attr
,
680 * mailbox module allowing communication between the on-chip processors using a
681 * queued mailbox-interrupt mechanism.
683 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc
= {
686 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
688 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
689 .sysc_fields
= &omap_hwmod_sysc_type2
,
692 static struct omap_hwmod_class am33xx_mailbox_hwmod_class
= {
694 .sysc
= &am33xx_mailbox_sysc
,
697 struct omap_hwmod am33xx_mailbox_hwmod
= {
699 .class = &am33xx_mailbox_hwmod_class
,
700 .clkdm_name
= "l4ls_clkdm",
701 .main_clk
= "l4ls_gclk",
704 .modulemode
= MODULEMODE_SWCTRL
,
712 static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc
= {
715 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
716 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
717 .sysc_fields
= &omap_hwmod_sysc_type3
,
720 static struct omap_hwmod_class am33xx_mcasp_hwmod_class
= {
722 .sysc
= &am33xx_mcasp_sysc
,
726 struct omap_hwmod am33xx_mcasp0_hwmod
= {
728 .class = &am33xx_mcasp_hwmod_class
,
729 .clkdm_name
= "l3s_clkdm",
730 .main_clk
= "mcasp0_fck",
733 .modulemode
= MODULEMODE_SWCTRL
,
739 struct omap_hwmod am33xx_mcasp1_hwmod
= {
741 .class = &am33xx_mcasp_hwmod_class
,
742 .clkdm_name
= "l3s_clkdm",
743 .main_clk
= "mcasp1_fck",
746 .modulemode
= MODULEMODE_SWCTRL
,
752 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc
= {
756 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
757 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
758 SYSC_HAS_AUTOIDLE
| SYSS_HAS_RESET_STATUS
),
759 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
760 .sysc_fields
= &omap_hwmod_sysc_type1
,
763 static struct omap_hwmod_class am33xx_mmc_hwmod_class
= {
765 .sysc
= &am33xx_mmc_sysc
,
769 static struct omap_hsmmc_dev_attr am33xx_mmc0_dev_attr
= {
770 .flags
= OMAP_HSMMC_SUPPORTS_DUAL_VOLT
,
773 struct omap_hwmod am33xx_mmc0_hwmod
= {
775 .class = &am33xx_mmc_hwmod_class
,
776 .clkdm_name
= "l4ls_clkdm",
777 .main_clk
= "mmc_clk",
780 .modulemode
= MODULEMODE_SWCTRL
,
783 .dev_attr
= &am33xx_mmc0_dev_attr
,
787 static struct omap_hsmmc_dev_attr am33xx_mmc1_dev_attr
= {
788 .flags
= OMAP_HSMMC_SUPPORTS_DUAL_VOLT
,
791 struct omap_hwmod am33xx_mmc1_hwmod
= {
793 .class = &am33xx_mmc_hwmod_class
,
794 .clkdm_name
= "l4ls_clkdm",
795 .main_clk
= "mmc_clk",
798 .modulemode
= MODULEMODE_SWCTRL
,
801 .dev_attr
= &am33xx_mmc1_dev_attr
,
805 static struct omap_hsmmc_dev_attr am33xx_mmc2_dev_attr
= {
806 .flags
= OMAP_HSMMC_SUPPORTS_DUAL_VOLT
,
808 struct omap_hwmod am33xx_mmc2_hwmod
= {
810 .class = &am33xx_mmc_hwmod_class
,
811 .clkdm_name
= "l3s_clkdm",
812 .main_clk
= "mmc_clk",
815 .modulemode
= MODULEMODE_SWCTRL
,
818 .dev_attr
= &am33xx_mmc2_dev_attr
,
825 static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc
= {
828 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
829 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
|
830 SIDLE_SMART
| SIDLE_SMART_WKUP
),
831 .sysc_fields
= &omap_hwmod_sysc_type3
,
834 static struct omap_hwmod_class am33xx_rtc_hwmod_class
= {
836 .sysc
= &am33xx_rtc_sysc
,
837 .unlock
= &omap_hwmod_rtc_unlock
,
838 .lock
= &omap_hwmod_rtc_lock
,
841 struct omap_hwmod am33xx_rtc_hwmod
= {
843 .class = &am33xx_rtc_hwmod_class
,
844 .clkdm_name
= "l4_rtc_clkdm",
845 .main_clk
= "clk_32768_ck",
848 .modulemode
= MODULEMODE_SWCTRL
,
854 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc
= {
858 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
859 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
|
860 SYSS_HAS_RESET_STATUS
),
861 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
862 .sysc_fields
= &omap_hwmod_sysc_type1
,
865 struct omap_hwmod_class am33xx_spi_hwmod_class
= {
867 .sysc
= &am33xx_mcspi_sysc
,
868 .rev
= OMAP4_MCSPI_REV
,
872 struct omap2_mcspi_dev_attr mcspi_attrib
= {
875 struct omap_hwmod am33xx_spi0_hwmod
= {
877 .class = &am33xx_spi_hwmod_class
,
878 .clkdm_name
= "l4ls_clkdm",
879 .main_clk
= "dpll_per_m2_div4_ck",
882 .modulemode
= MODULEMODE_SWCTRL
,
885 .dev_attr
= &mcspi_attrib
,
889 struct omap_hwmod am33xx_spi1_hwmod
= {
891 .class = &am33xx_spi_hwmod_class
,
892 .clkdm_name
= "l4ls_clkdm",
893 .main_clk
= "dpll_per_m2_div4_ck",
896 .modulemode
= MODULEMODE_SWCTRL
,
899 .dev_attr
= &mcspi_attrib
,
904 * spinlock provides hardware assistance for synchronizing the
905 * processes running on multiple processors
908 static struct omap_hwmod_class_sysconfig am33xx_spinlock_sysc
= {
912 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
913 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
914 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
915 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
916 .sysc_fields
= &omap_hwmod_sysc_type1
,
919 static struct omap_hwmod_class am33xx_spinlock_hwmod_class
= {
921 .sysc
= &am33xx_spinlock_sysc
,
924 struct omap_hwmod am33xx_spinlock_hwmod
= {
926 .class = &am33xx_spinlock_hwmod_class
,
927 .clkdm_name
= "l4ls_clkdm",
928 .main_clk
= "l4ls_gclk",
931 .modulemode
= MODULEMODE_SWCTRL
,
936 /* 'timer 2-7' class */
937 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc
= {
941 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
942 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
944 .sysc_fields
= &omap_hwmod_sysc_type2
,
947 struct omap_hwmod_class am33xx_timer_hwmod_class
= {
949 .sysc
= &am33xx_timer_sysc
,
953 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc
= {
957 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
958 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
|
959 SYSS_HAS_RESET_STATUS
),
960 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
961 .sysc_fields
= &omap_hwmod_sysc_type1
,
964 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class
= {
966 .sysc
= &am33xx_timer1ms_sysc
,
969 struct omap_hwmod am33xx_timer1_hwmod
= {
971 .class = &am33xx_timer1ms_hwmod_class
,
972 .clkdm_name
= "l4_wkup_clkdm",
973 .main_clk
= "timer1_fck",
976 .modulemode
= MODULEMODE_SWCTRL
,
981 struct omap_hwmod am33xx_timer2_hwmod
= {
983 .class = &am33xx_timer_hwmod_class
,
984 .clkdm_name
= "l4ls_clkdm",
985 .main_clk
= "timer2_fck",
988 .modulemode
= MODULEMODE_SWCTRL
,
993 struct omap_hwmod am33xx_timer3_hwmod
= {
995 .class = &am33xx_timer_hwmod_class
,
996 .clkdm_name
= "l4ls_clkdm",
997 .main_clk
= "timer3_fck",
1000 .modulemode
= MODULEMODE_SWCTRL
,
1005 struct omap_hwmod am33xx_timer4_hwmod
= {
1007 .class = &am33xx_timer_hwmod_class
,
1008 .clkdm_name
= "l4ls_clkdm",
1009 .main_clk
= "timer4_fck",
1012 .modulemode
= MODULEMODE_SWCTRL
,
1017 struct omap_hwmod am33xx_timer5_hwmod
= {
1019 .class = &am33xx_timer_hwmod_class
,
1020 .clkdm_name
= "l4ls_clkdm",
1021 .main_clk
= "timer5_fck",
1024 .modulemode
= MODULEMODE_SWCTRL
,
1029 struct omap_hwmod am33xx_timer6_hwmod
= {
1031 .class = &am33xx_timer_hwmod_class
,
1032 .clkdm_name
= "l4ls_clkdm",
1033 .main_clk
= "timer6_fck",
1036 .modulemode
= MODULEMODE_SWCTRL
,
1041 struct omap_hwmod am33xx_timer7_hwmod
= {
1043 .class = &am33xx_timer_hwmod_class
,
1044 .clkdm_name
= "l4ls_clkdm",
1045 .main_clk
= "timer7_fck",
1048 .modulemode
= MODULEMODE_SWCTRL
,
1054 static struct omap_hwmod_class am33xx_tpcc_hwmod_class
= {
1058 struct omap_hwmod am33xx_tpcc_hwmod
= {
1060 .class = &am33xx_tpcc_hwmod_class
,
1061 .clkdm_name
= "l3_clkdm",
1062 .main_clk
= "l3_gclk",
1065 .modulemode
= MODULEMODE_SWCTRL
,
1070 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc
= {
1073 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
1074 SYSC_HAS_MIDLEMODE
),
1075 .idlemodes
= (SIDLE_FORCE
| SIDLE_SMART
| MSTANDBY_FORCE
),
1076 .sysc_fields
= &omap_hwmod_sysc_type2
,
1080 static struct omap_hwmod_class am33xx_tptc_hwmod_class
= {
1082 .sysc
= &am33xx_tptc_sysc
,
1086 struct omap_hwmod am33xx_tptc0_hwmod
= {
1088 .class = &am33xx_tptc_hwmod_class
,
1089 .clkdm_name
= "l3_clkdm",
1090 .flags
= HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
,
1091 .main_clk
= "l3_gclk",
1094 .modulemode
= MODULEMODE_SWCTRL
,
1100 struct omap_hwmod am33xx_tptc1_hwmod
= {
1102 .class = &am33xx_tptc_hwmod_class
,
1103 .clkdm_name
= "l3_clkdm",
1104 .flags
= (HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
),
1105 .main_clk
= "l3_gclk",
1108 .modulemode
= MODULEMODE_SWCTRL
,
1114 struct omap_hwmod am33xx_tptc2_hwmod
= {
1116 .class = &am33xx_tptc_hwmod_class
,
1117 .clkdm_name
= "l3_clkdm",
1118 .flags
= (HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
),
1119 .main_clk
= "l3_gclk",
1122 .modulemode
= MODULEMODE_SWCTRL
,
1128 static struct omap_hwmod_class_sysconfig uart_sysc
= {
1132 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_ENAWAKEUP
|
1133 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
),
1134 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1136 .sysc_fields
= &omap_hwmod_sysc_type1
,
1139 static struct omap_hwmod_class uart_class
= {
1144 struct omap_hwmod am33xx_uart1_hwmod
= {
1146 .class = &uart_class
,
1147 .clkdm_name
= "l4_wkup_clkdm",
1148 .flags
= DEBUG_AM33XXUART1_FLAGS
| HWMOD_SWSUP_SIDLE_ACT
,
1149 .main_clk
= "dpll_per_m2_div4_wkupdm_ck",
1152 .modulemode
= MODULEMODE_SWCTRL
,
1157 struct omap_hwmod am33xx_uart2_hwmod
= {
1159 .class = &uart_class
,
1160 .clkdm_name
= "l4ls_clkdm",
1161 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
1162 .main_clk
= "dpll_per_m2_div4_ck",
1165 .modulemode
= MODULEMODE_SWCTRL
,
1171 struct omap_hwmod am33xx_uart3_hwmod
= {
1173 .class = &uart_class
,
1174 .clkdm_name
= "l4ls_clkdm",
1175 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
1176 .main_clk
= "dpll_per_m2_div4_ck",
1179 .modulemode
= MODULEMODE_SWCTRL
,
1184 struct omap_hwmod am33xx_uart4_hwmod
= {
1186 .class = &uart_class
,
1187 .clkdm_name
= "l4ls_clkdm",
1188 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
1189 .main_clk
= "dpll_per_m2_div4_ck",
1192 .modulemode
= MODULEMODE_SWCTRL
,
1197 struct omap_hwmod am33xx_uart5_hwmod
= {
1199 .class = &uart_class
,
1200 .clkdm_name
= "l4ls_clkdm",
1201 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
1202 .main_clk
= "dpll_per_m2_div4_ck",
1205 .modulemode
= MODULEMODE_SWCTRL
,
1210 struct omap_hwmod am33xx_uart6_hwmod
= {
1212 .class = &uart_class
,
1213 .clkdm_name
= "l4ls_clkdm",
1214 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
1215 .main_clk
= "dpll_per_m2_div4_ck",
1218 .modulemode
= MODULEMODE_SWCTRL
,
1223 /* 'wd_timer' class */
1224 static struct omap_hwmod_class_sysconfig wdt_sysc
= {
1228 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_SIDLEMODE
|
1229 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1230 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1232 .sysc_fields
= &omap_hwmod_sysc_type1
,
1235 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class
= {
1238 .pre_shutdown
= &omap2_wd_timer_disable
,
1242 * XXX: device.c file uses hardcoded name for watchdog timer
1243 * driver "wd_timer2, so we are also using same name as of now...
1245 struct omap_hwmod am33xx_wd_timer1_hwmod
= {
1246 .name
= "wd_timer2",
1247 .class = &am33xx_wd_timer_hwmod_class
,
1248 .clkdm_name
= "l4_wkup_clkdm",
1249 .flags
= HWMOD_SWSUP_SIDLE
,
1250 .main_clk
= "wdt1_fck",
1253 .modulemode
= MODULEMODE_SWCTRL
,
1258 static void omap_hwmod_am33xx_clkctrl(void)
1260 CLKCTRL(am33xx_uart2_hwmod
, AM33XX_CM_PER_UART1_CLKCTRL_OFFSET
);
1261 CLKCTRL(am33xx_uart3_hwmod
, AM33XX_CM_PER_UART2_CLKCTRL_OFFSET
);
1262 CLKCTRL(am33xx_uart4_hwmod
, AM33XX_CM_PER_UART3_CLKCTRL_OFFSET
);
1263 CLKCTRL(am33xx_uart5_hwmod
, AM33XX_CM_PER_UART4_CLKCTRL_OFFSET
);
1264 CLKCTRL(am33xx_uart6_hwmod
, AM33XX_CM_PER_UART5_CLKCTRL_OFFSET
);
1265 CLKCTRL(am33xx_dcan0_hwmod
, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET
);
1266 CLKCTRL(am33xx_dcan1_hwmod
, AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET
);
1267 CLKCTRL(am33xx_elm_hwmod
, AM33XX_CM_PER_ELM_CLKCTRL_OFFSET
);
1268 CLKCTRL(am33xx_epwmss0_hwmod
, AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET
);
1269 CLKCTRL(am33xx_epwmss1_hwmod
, AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET
);
1270 CLKCTRL(am33xx_epwmss2_hwmod
, AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET
);
1271 CLKCTRL(am33xx_gpio1_hwmod
, AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET
);
1272 CLKCTRL(am33xx_gpio2_hwmod
, AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET
);
1273 CLKCTRL(am33xx_gpio3_hwmod
, AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET
);
1274 CLKCTRL(am33xx_i2c2_hwmod
, AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET
);
1275 CLKCTRL(am33xx_i2c3_hwmod
, AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET
);
1276 CLKCTRL(am33xx_mailbox_hwmod
, AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET
);
1277 CLKCTRL(am33xx_mcasp0_hwmod
, AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET
);
1278 CLKCTRL(am33xx_mcasp1_hwmod
, AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET
);
1279 CLKCTRL(am33xx_mmc0_hwmod
, AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET
);
1280 CLKCTRL(am33xx_mmc1_hwmod
, AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET
);
1281 CLKCTRL(am33xx_spi0_hwmod
, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET
);
1282 CLKCTRL(am33xx_spi1_hwmod
, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET
);
1283 CLKCTRL(am33xx_spinlock_hwmod
, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET
);
1284 CLKCTRL(am33xx_timer2_hwmod
, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET
);
1285 CLKCTRL(am33xx_timer3_hwmod
, AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET
);
1286 CLKCTRL(am33xx_timer4_hwmod
, AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET
);
1287 CLKCTRL(am33xx_timer5_hwmod
, AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET
);
1288 CLKCTRL(am33xx_timer6_hwmod
, AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET
);
1289 CLKCTRL(am33xx_timer7_hwmod
, AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET
);
1290 CLKCTRL(am33xx_smartreflex0_hwmod
,
1291 AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET
);
1292 CLKCTRL(am33xx_smartreflex1_hwmod
,
1293 AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET
);
1294 CLKCTRL(am33xx_uart1_hwmod
, AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET
);
1295 CLKCTRL(am33xx_timer1_hwmod
, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET
);
1296 CLKCTRL(am33xx_i2c1_hwmod
, AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET
);
1297 CLKCTRL(am33xx_wd_timer1_hwmod
, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET
);
1298 CLKCTRL(am33xx_rtc_hwmod
, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET
);
1299 CLKCTRL(am33xx_mmc2_hwmod
, AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET
);
1300 CLKCTRL(am33xx_gpmc_hwmod
, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET
);
1301 CLKCTRL(am33xx_l4_ls_hwmod
, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET
);
1302 CLKCTRL(am33xx_l4_wkup_hwmod
, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET
);
1303 CLKCTRL(am33xx_l3_main_hwmod
, AM33XX_CM_PER_L3_CLKCTRL_OFFSET
);
1304 CLKCTRL(am33xx_tpcc_hwmod
, AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET
);
1305 CLKCTRL(am33xx_tptc0_hwmod
, AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET
);
1306 CLKCTRL(am33xx_tptc1_hwmod
, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET
);
1307 CLKCTRL(am33xx_tptc2_hwmod
, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET
);
1308 CLKCTRL(am33xx_gfx_hwmod
, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET
);
1309 CLKCTRL(am33xx_cpgmac0_hwmod
, AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET
);
1310 CLKCTRL(am33xx_pruss_hwmod
, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET
);
1311 CLKCTRL(am33xx_mpu_hwmod
, AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET
);
1312 CLKCTRL(am33xx_l3_instr_hwmod
, AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET
);
1313 CLKCTRL(am33xx_ocmcram_hwmod
, AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET
);
1314 CLKCTRL(am33xx_sha0_hwmod
, AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET
);
1315 CLKCTRL(am33xx_aes0_hwmod
, AM33XX_CM_PER_AES0_CLKCTRL_OFFSET
);
1318 static void omap_hwmod_am33xx_rst(void)
1320 RSTCTRL(am33xx_pruss_hwmod
, AM33XX_RM_PER_RSTCTRL_OFFSET
);
1321 RSTCTRL(am33xx_gfx_hwmod
, AM33XX_RM_GFX_RSTCTRL_OFFSET
);
1322 RSTST(am33xx_gfx_hwmod
, AM33XX_RM_GFX_RSTST_OFFSET
);
1325 void omap_hwmod_am33xx_reg(void)
1327 omap_hwmod_am33xx_clkctrl();
1328 omap_hwmod_am33xx_rst();
1331 static void omap_hwmod_am43xx_clkctrl(void)
1333 CLKCTRL(am33xx_uart2_hwmod
, AM43XX_CM_PER_UART1_CLKCTRL_OFFSET
);
1334 CLKCTRL(am33xx_uart3_hwmod
, AM43XX_CM_PER_UART2_CLKCTRL_OFFSET
);
1335 CLKCTRL(am33xx_uart4_hwmod
, AM43XX_CM_PER_UART3_CLKCTRL_OFFSET
);
1336 CLKCTRL(am33xx_uart5_hwmod
, AM43XX_CM_PER_UART4_CLKCTRL_OFFSET
);
1337 CLKCTRL(am33xx_uart6_hwmod
, AM43XX_CM_PER_UART5_CLKCTRL_OFFSET
);
1338 CLKCTRL(am33xx_dcan0_hwmod
, AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET
);
1339 CLKCTRL(am33xx_dcan1_hwmod
, AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET
);
1340 CLKCTRL(am33xx_elm_hwmod
, AM43XX_CM_PER_ELM_CLKCTRL_OFFSET
);
1341 CLKCTRL(am33xx_epwmss0_hwmod
, AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET
);
1342 CLKCTRL(am33xx_epwmss1_hwmod
, AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET
);
1343 CLKCTRL(am33xx_epwmss2_hwmod
, AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET
);
1344 CLKCTRL(am33xx_gpio1_hwmod
, AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET
);
1345 CLKCTRL(am33xx_gpio2_hwmod
, AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET
);
1346 CLKCTRL(am33xx_gpio3_hwmod
, AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET
);
1347 CLKCTRL(am33xx_i2c2_hwmod
, AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET
);
1348 CLKCTRL(am33xx_i2c3_hwmod
, AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET
);
1349 CLKCTRL(am33xx_mailbox_hwmod
, AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET
);
1350 CLKCTRL(am33xx_mcasp0_hwmod
, AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET
);
1351 CLKCTRL(am33xx_mcasp1_hwmod
, AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET
);
1352 CLKCTRL(am33xx_mmc0_hwmod
, AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET
);
1353 CLKCTRL(am33xx_mmc1_hwmod
, AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET
);
1354 CLKCTRL(am33xx_spi0_hwmod
, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET
);
1355 CLKCTRL(am33xx_spi1_hwmod
, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET
);
1356 CLKCTRL(am33xx_spinlock_hwmod
, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET
);
1357 CLKCTRL(am33xx_timer2_hwmod
, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET
);
1358 CLKCTRL(am33xx_timer3_hwmod
, AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET
);
1359 CLKCTRL(am33xx_timer4_hwmod
, AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET
);
1360 CLKCTRL(am33xx_timer5_hwmod
, AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET
);
1361 CLKCTRL(am33xx_timer6_hwmod
, AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET
);
1362 CLKCTRL(am33xx_timer7_hwmod
, AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET
);
1363 CLKCTRL(am33xx_smartreflex0_hwmod
,
1364 AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET
);
1365 CLKCTRL(am33xx_smartreflex1_hwmod
,
1366 AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET
);
1367 CLKCTRL(am33xx_uart1_hwmod
, AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET
);
1368 CLKCTRL(am33xx_timer1_hwmod
, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET
);
1369 CLKCTRL(am33xx_i2c1_hwmod
, AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET
);
1370 CLKCTRL(am33xx_wd_timer1_hwmod
, AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET
);
1371 CLKCTRL(am33xx_rtc_hwmod
, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET
);
1372 CLKCTRL(am33xx_mmc2_hwmod
, AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET
);
1373 CLKCTRL(am33xx_gpmc_hwmod
, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET
);
1374 CLKCTRL(am33xx_l4_ls_hwmod
, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET
);
1375 CLKCTRL(am33xx_l4_wkup_hwmod
, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET
);
1376 CLKCTRL(am33xx_l3_main_hwmod
, AM43XX_CM_PER_L3_CLKCTRL_OFFSET
);
1377 CLKCTRL(am33xx_tpcc_hwmod
, AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET
);
1378 CLKCTRL(am33xx_tptc0_hwmod
, AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET
);
1379 CLKCTRL(am33xx_tptc1_hwmod
, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET
);
1380 CLKCTRL(am33xx_tptc2_hwmod
, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET
);
1381 CLKCTRL(am33xx_gfx_hwmod
, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET
);
1382 CLKCTRL(am33xx_cpgmac0_hwmod
, AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET
);
1383 CLKCTRL(am33xx_pruss_hwmod
, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET
);
1384 CLKCTRL(am33xx_mpu_hwmod
, AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET
);
1385 CLKCTRL(am33xx_l3_instr_hwmod
, AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET
);
1386 CLKCTRL(am33xx_ocmcram_hwmod
, AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET
);
1387 CLKCTRL(am33xx_sha0_hwmod
, AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET
);
1388 CLKCTRL(am33xx_aes0_hwmod
, AM43XX_CM_PER_AES0_CLKCTRL_OFFSET
);
1391 static void omap_hwmod_am43xx_rst(void)
1393 RSTCTRL(am33xx_pruss_hwmod
, AM43XX_RM_PER_RSTCTRL_OFFSET
);
1394 RSTCTRL(am33xx_gfx_hwmod
, AM43XX_RM_GFX_RSTCTRL_OFFSET
);
1395 RSTST(am33xx_pruss_hwmod
, AM43XX_RM_PER_RSTST_OFFSET
);
1396 RSTST(am33xx_gfx_hwmod
, AM43XX_RM_GFX_RSTST_OFFSET
);
1399 void omap_hwmod_am43xx_reg(void)
1401 omap_hwmod_am43xx_clkctrl();
1402 omap_hwmod_am43xx_rst();