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ARM: OMAP2+: hwmod: AM335x/AM43x: move common data
[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_33xx_43xx_ipblock_data.c
1 /*
2 *
3 * Copyright (C) 2013 Texas Instruments Incorporated
4 *
5 * Hwmod common for AM335x and AM43x
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <linux/platform_data/gpio-omap.h>
18 #include <linux/platform_data/spi-omap2-mcspi.h>
19 #include "omap_hwmod.h"
20 #include "i2c.h"
21 #include "mmc.h"
22 #include "wd_timer.h"
23 #include "cm33xx.h"
24 #include "prm33xx.h"
25 #include "omap_hwmod_33xx_43xx_common_data.h"
26
27 /*
28 * 'l3' class
29 * instance(s): l3_main, l3_s, l3_instr
30 */
31 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
32 .name = "l3",
33 };
34
35 struct omap_hwmod am33xx_l3_main_hwmod = {
36 .name = "l3_main",
37 .class = &am33xx_l3_hwmod_class,
38 .clkdm_name = "l3_clkdm",
39 .flags = HWMOD_INIT_NO_IDLE,
40 .main_clk = "l3_gclk",
41 .prcm = {
42 .omap4 = {
43 .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
44 .modulemode = MODULEMODE_SWCTRL,
45 },
46 },
47 };
48
49 /* l3_s */
50 struct omap_hwmod am33xx_l3_s_hwmod = {
51 .name = "l3_s",
52 .class = &am33xx_l3_hwmod_class,
53 .clkdm_name = "l3s_clkdm",
54 };
55
56 /* l3_instr */
57 struct omap_hwmod am33xx_l3_instr_hwmod = {
58 .name = "l3_instr",
59 .class = &am33xx_l3_hwmod_class,
60 .clkdm_name = "l3_clkdm",
61 .flags = HWMOD_INIT_NO_IDLE,
62 .main_clk = "l3_gclk",
63 .prcm = {
64 .omap4 = {
65 .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
66 .modulemode = MODULEMODE_SWCTRL,
67 },
68 },
69 };
70
71 /*
72 * 'l4' class
73 * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
74 */
75 struct omap_hwmod_class am33xx_l4_hwmod_class = {
76 .name = "l4",
77 };
78
79 /* l4_ls */
80 struct omap_hwmod am33xx_l4_ls_hwmod = {
81 .name = "l4_ls",
82 .class = &am33xx_l4_hwmod_class,
83 .clkdm_name = "l4ls_clkdm",
84 .flags = HWMOD_INIT_NO_IDLE,
85 .main_clk = "l4ls_gclk",
86 .prcm = {
87 .omap4 = {
88 .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
89 .modulemode = MODULEMODE_SWCTRL,
90 },
91 },
92 };
93
94 /* l4_wkup */
95 struct omap_hwmod am33xx_l4_wkup_hwmod = {
96 .name = "l4_wkup",
97 .class = &am33xx_l4_hwmod_class,
98 .clkdm_name = "l4_wkup_clkdm",
99 .flags = HWMOD_INIT_NO_IDLE,
100 .prcm = {
101 .omap4 = {
102 .clkctrl_offs = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
103 .modulemode = MODULEMODE_SWCTRL,
104 },
105 },
106 };
107
108 /*
109 * 'mpu' class
110 */
111 static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
112 .name = "mpu",
113 };
114
115 struct omap_hwmod am33xx_mpu_hwmod = {
116 .name = "mpu",
117 .class = &am33xx_mpu_hwmod_class,
118 .clkdm_name = "mpu_clkdm",
119 .flags = HWMOD_INIT_NO_IDLE,
120 .main_clk = "dpll_mpu_m2_ck",
121 .prcm = {
122 .omap4 = {
123 .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
124 .modulemode = MODULEMODE_SWCTRL,
125 },
126 },
127 };
128
129 /*
130 * 'wakeup m3' class
131 * Wakeup controller sub-system under wakeup domain
132 */
133 struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
134 .name = "wkup_m3",
135 };
136
137 /*
138 * 'pru-icss' class
139 * Programmable Real-Time Unit and Industrial Communication Subsystem
140 */
141 static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
142 .name = "pruss",
143 };
144
145 static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
146 { .name = "pruss", .rst_shift = 1 },
147 };
148
149 /* pru-icss */
150 /* Pseudo hwmod for reset control purpose only */
151 struct omap_hwmod am33xx_pruss_hwmod = {
152 .name = "pruss",
153 .class = &am33xx_pruss_hwmod_class,
154 .clkdm_name = "pruss_ocp_clkdm",
155 .main_clk = "pruss_ocp_gclk",
156 .prcm = {
157 .omap4 = {
158 .clkctrl_offs = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
159 .rstctrl_offs = AM33XX_RM_PER_RSTCTRL_OFFSET,
160 .modulemode = MODULEMODE_SWCTRL,
161 },
162 },
163 .rst_lines = am33xx_pruss_resets,
164 .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
165 };
166
167 /* gfx */
168 /* Pseudo hwmod for reset control purpose only */
169 static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
170 .name = "gfx",
171 };
172
173 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
174 { .name = "gfx", .rst_shift = 0, .st_shift = 0},
175 };
176
177 struct omap_hwmod am33xx_gfx_hwmod = {
178 .name = "gfx",
179 .class = &am33xx_gfx_hwmod_class,
180 .clkdm_name = "gfx_l3_clkdm",
181 .main_clk = "gfx_fck_div_ck",
182 .prcm = {
183 .omap4 = {
184 .clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
185 .rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET,
186 .rstst_offs = AM33XX_RM_GFX_RSTST_OFFSET,
187 .modulemode = MODULEMODE_SWCTRL,
188 },
189 },
190 .rst_lines = am33xx_gfx_resets,
191 .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets),
192 };
193
194 /*
195 * 'prcm' class
196 * power and reset manager (whole prcm infrastructure)
197 */
198 static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
199 .name = "prcm",
200 };
201
202 /* prcm */
203 struct omap_hwmod am33xx_prcm_hwmod = {
204 .name = "prcm",
205 .class = &am33xx_prcm_hwmod_class,
206 .clkdm_name = "l4_wkup_clkdm",
207 };
208
209 /*
210 * 'aes0' class
211 */
212 static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
213 .rev_offs = 0x80,
214 .sysc_offs = 0x84,
215 .syss_offs = 0x88,
216 .sysc_flags = SYSS_HAS_RESET_STATUS,
217 };
218
219 static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
220 .name = "aes0",
221 .sysc = &am33xx_aes0_sysc,
222 };
223
224 struct omap_hwmod am33xx_aes0_hwmod = {
225 .name = "aes",
226 .class = &am33xx_aes0_hwmod_class,
227 .clkdm_name = "l3_clkdm",
228 .main_clk = "aes0_fck",
229 .prcm = {
230 .omap4 = {
231 .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
232 .modulemode = MODULEMODE_SWCTRL,
233 },
234 },
235 };
236
237 /* sha0 HIB2 (the 'P' (public) device) */
238 static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
239 .rev_offs = 0x100,
240 .sysc_offs = 0x110,
241 .syss_offs = 0x114,
242 .sysc_flags = SYSS_HAS_RESET_STATUS,
243 };
244
245 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
246 .name = "sha0",
247 .sysc = &am33xx_sha0_sysc,
248 };
249
250 struct omap_hwmod am33xx_sha0_hwmod = {
251 .name = "sham",
252 .class = &am33xx_sha0_hwmod_class,
253 .clkdm_name = "l3_clkdm",
254 .main_clk = "l3_gclk",
255 .prcm = {
256 .omap4 = {
257 .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
258 .modulemode = MODULEMODE_SWCTRL,
259 },
260 },
261 };
262
263 /* ocmcram */
264 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
265 .name = "ocmcram",
266 };
267
268 struct omap_hwmod am33xx_ocmcram_hwmod = {
269 .name = "ocmcram",
270 .class = &am33xx_ocmcram_hwmod_class,
271 .clkdm_name = "l3_clkdm",
272 .flags = HWMOD_INIT_NO_IDLE,
273 .main_clk = "l3_gclk",
274 .prcm = {
275 .omap4 = {
276 .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
277 .modulemode = MODULEMODE_SWCTRL,
278 },
279 },
280 };
281
282 /* 'smartreflex' class */
283 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
284 .name = "smartreflex",
285 };
286
287 /* smartreflex0 */
288 struct omap_hwmod am33xx_smartreflex0_hwmod = {
289 .name = "smartreflex0",
290 .class = &am33xx_smartreflex_hwmod_class,
291 .clkdm_name = "l4_wkup_clkdm",
292 .main_clk = "smartreflex0_fck",
293 .prcm = {
294 .omap4 = {
295 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
296 .modulemode = MODULEMODE_SWCTRL,
297 },
298 },
299 };
300
301 /* smartreflex1 */
302 struct omap_hwmod am33xx_smartreflex1_hwmod = {
303 .name = "smartreflex1",
304 .class = &am33xx_smartreflex_hwmod_class,
305 .clkdm_name = "l4_wkup_clkdm",
306 .main_clk = "smartreflex1_fck",
307 .prcm = {
308 .omap4 = {
309 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
310 .modulemode = MODULEMODE_SWCTRL,
311 },
312 },
313 };
314
315 /*
316 * 'control' module class
317 */
318 struct omap_hwmod_class am33xx_control_hwmod_class = {
319 .name = "control",
320 };
321
322 /*
323 * 'cpgmac' class
324 * cpsw/cpgmac sub system
325 */
326 static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
327 .rev_offs = 0x0,
328 .sysc_offs = 0x8,
329 .syss_offs = 0x4,
330 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
331 SYSS_HAS_RESET_STATUS),
332 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
333 MSTANDBY_NO),
334 .sysc_fields = &omap_hwmod_sysc_type3,
335 };
336
337 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
338 .name = "cpgmac0",
339 .sysc = &am33xx_cpgmac_sysc,
340 };
341
342 struct omap_hwmod am33xx_cpgmac0_hwmod = {
343 .name = "cpgmac0",
344 .class = &am33xx_cpgmac0_hwmod_class,
345 .clkdm_name = "cpsw_125mhz_clkdm",
346 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
347 .main_clk = "cpsw_125mhz_gclk",
348 .mpu_rt_idx = 1,
349 .prcm = {
350 .omap4 = {
351 .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
352 .modulemode = MODULEMODE_SWCTRL,
353 },
354 },
355 };
356
357 /*
358 * mdio class
359 */
360 static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
361 .name = "davinci_mdio",
362 };
363
364 struct omap_hwmod am33xx_mdio_hwmod = {
365 .name = "davinci_mdio",
366 .class = &am33xx_mdio_hwmod_class,
367 .clkdm_name = "cpsw_125mhz_clkdm",
368 .main_clk = "cpsw_125mhz_gclk",
369 };
370
371 /*
372 * dcan class
373 */
374 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
375 .name = "d_can",
376 };
377
378 /* dcan0 */
379 struct omap_hwmod am33xx_dcan0_hwmod = {
380 .name = "d_can0",
381 .class = &am33xx_dcan_hwmod_class,
382 .clkdm_name = "l4ls_clkdm",
383 .main_clk = "dcan0_fck",
384 .prcm = {
385 .omap4 = {
386 .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
387 .modulemode = MODULEMODE_SWCTRL,
388 },
389 },
390 };
391
392 /* dcan1 */
393 struct omap_hwmod am33xx_dcan1_hwmod = {
394 .name = "d_can1",
395 .class = &am33xx_dcan_hwmod_class,
396 .clkdm_name = "l4ls_clkdm",
397 .main_clk = "dcan1_fck",
398 .prcm = {
399 .omap4 = {
400 .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
401 .modulemode = MODULEMODE_SWCTRL,
402 },
403 },
404 };
405
406 /* elm */
407 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
408 .rev_offs = 0x0000,
409 .sysc_offs = 0x0010,
410 .syss_offs = 0x0014,
411 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
412 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
413 SYSS_HAS_RESET_STATUS),
414 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
415 .sysc_fields = &omap_hwmod_sysc_type1,
416 };
417
418 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
419 .name = "elm",
420 .sysc = &am33xx_elm_sysc,
421 };
422
423 struct omap_hwmod am33xx_elm_hwmod = {
424 .name = "elm",
425 .class = &am33xx_elm_hwmod_class,
426 .clkdm_name = "l4ls_clkdm",
427 .main_clk = "l4ls_gclk",
428 .prcm = {
429 .omap4 = {
430 .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
431 .modulemode = MODULEMODE_SWCTRL,
432 },
433 },
434 };
435
436 /* pwmss */
437 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
438 .rev_offs = 0x0,
439 .sysc_offs = 0x4,
440 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
441 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
442 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
443 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
444 .sysc_fields = &omap_hwmod_sysc_type2,
445 };
446
447 struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
448 .name = "epwmss",
449 .sysc = &am33xx_epwmss_sysc,
450 };
451
452 static struct omap_hwmod_class am33xx_ecap_hwmod_class = {
453 .name = "ecap",
454 };
455
456 static struct omap_hwmod_class am33xx_eqep_hwmod_class = {
457 .name = "eqep",
458 };
459
460 struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = {
461 .name = "ehrpwm",
462 };
463
464 /* epwmss0 */
465 struct omap_hwmod am33xx_epwmss0_hwmod = {
466 .name = "epwmss0",
467 .class = &am33xx_epwmss_hwmod_class,
468 .clkdm_name = "l4ls_clkdm",
469 .main_clk = "l4ls_gclk",
470 .prcm = {
471 .omap4 = {
472 .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
473 .modulemode = MODULEMODE_SWCTRL,
474 },
475 },
476 };
477
478 /* ecap0 */
479 struct omap_hwmod am33xx_ecap0_hwmod = {
480 .name = "ecap0",
481 .class = &am33xx_ecap_hwmod_class,
482 .clkdm_name = "l4ls_clkdm",
483 .main_clk = "l4ls_gclk",
484 };
485
486 /* eqep0 */
487 struct omap_hwmod am33xx_eqep0_hwmod = {
488 .name = "eqep0",
489 .class = &am33xx_eqep_hwmod_class,
490 .clkdm_name = "l4ls_clkdm",
491 .main_clk = "l4ls_gclk",
492 };
493
494 /* ehrpwm0 */
495 struct omap_hwmod am33xx_ehrpwm0_hwmod = {
496 .name = "ehrpwm0",
497 .class = &am33xx_ehrpwm_hwmod_class,
498 .clkdm_name = "l4ls_clkdm",
499 .main_clk = "l4ls_gclk",
500 };
501
502 /* epwmss1 */
503 struct omap_hwmod am33xx_epwmss1_hwmod = {
504 .name = "epwmss1",
505 .class = &am33xx_epwmss_hwmod_class,
506 .clkdm_name = "l4ls_clkdm",
507 .main_clk = "l4ls_gclk",
508 .prcm = {
509 .omap4 = {
510 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
511 .modulemode = MODULEMODE_SWCTRL,
512 },
513 },
514 };
515
516 /* ecap1 */
517 struct omap_hwmod am33xx_ecap1_hwmod = {
518 .name = "ecap1",
519 .class = &am33xx_ecap_hwmod_class,
520 .clkdm_name = "l4ls_clkdm",
521 .main_clk = "l4ls_gclk",
522 };
523
524 /* eqep1 */
525 struct omap_hwmod am33xx_eqep1_hwmod = {
526 .name = "eqep1",
527 .class = &am33xx_eqep_hwmod_class,
528 .clkdm_name = "l4ls_clkdm",
529 .main_clk = "l4ls_gclk",
530 };
531
532 /* ehrpwm1 */
533 struct omap_hwmod am33xx_ehrpwm1_hwmod = {
534 .name = "ehrpwm1",
535 .class = &am33xx_ehrpwm_hwmod_class,
536 .clkdm_name = "l4ls_clkdm",
537 .main_clk = "l4ls_gclk",
538 };
539
540 /* epwmss2 */
541 struct omap_hwmod am33xx_epwmss2_hwmod = {
542 .name = "epwmss2",
543 .class = &am33xx_epwmss_hwmod_class,
544 .clkdm_name = "l4ls_clkdm",
545 .main_clk = "l4ls_gclk",
546 .prcm = {
547 .omap4 = {
548 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
549 .modulemode = MODULEMODE_SWCTRL,
550 },
551 },
552 };
553
554 /* ecap2 */
555 struct omap_hwmod am33xx_ecap2_hwmod = {
556 .name = "ecap2",
557 .class = &am33xx_ecap_hwmod_class,
558 .clkdm_name = "l4ls_clkdm",
559 .main_clk = "l4ls_gclk",
560 };
561
562 /* eqep2 */
563 struct omap_hwmod am33xx_eqep2_hwmod = {
564 .name = "eqep2",
565 .class = &am33xx_eqep_hwmod_class,
566 .clkdm_name = "l4ls_clkdm",
567 .main_clk = "l4ls_gclk",
568 };
569
570 /* ehrpwm2 */
571 struct omap_hwmod am33xx_ehrpwm2_hwmod = {
572 .name = "ehrpwm2",
573 .class = &am33xx_ehrpwm_hwmod_class,
574 .clkdm_name = "l4ls_clkdm",
575 .main_clk = "l4ls_gclk",
576 };
577
578 /*
579 * 'gpio' class: for gpio 0,1,2,3
580 */
581 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
582 .rev_offs = 0x0000,
583 .sysc_offs = 0x0010,
584 .syss_offs = 0x0114,
585 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
586 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
587 SYSS_HAS_RESET_STATUS),
588 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
589 SIDLE_SMART_WKUP),
590 .sysc_fields = &omap_hwmod_sysc_type1,
591 };
592
593 struct omap_hwmod_class am33xx_gpio_hwmod_class = {
594 .name = "gpio",
595 .sysc = &am33xx_gpio_sysc,
596 .rev = 2,
597 };
598
599 struct omap_gpio_dev_attr gpio_dev_attr = {
600 .bank_width = 32,
601 .dbck_flag = true,
602 };
603
604 /* gpio1 */
605 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
606 { .role = "dbclk", .clk = "gpio1_dbclk" },
607 };
608
609 struct omap_hwmod am33xx_gpio1_hwmod = {
610 .name = "gpio2",
611 .class = &am33xx_gpio_hwmod_class,
612 .clkdm_name = "l4ls_clkdm",
613 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
614 .main_clk = "l4ls_gclk",
615 .prcm = {
616 .omap4 = {
617 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
618 .modulemode = MODULEMODE_SWCTRL,
619 },
620 },
621 .opt_clks = gpio1_opt_clks,
622 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
623 .dev_attr = &gpio_dev_attr,
624 };
625
626 /* gpio2 */
627 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
628 { .role = "dbclk", .clk = "gpio2_dbclk" },
629 };
630
631 struct omap_hwmod am33xx_gpio2_hwmod = {
632 .name = "gpio3",
633 .class = &am33xx_gpio_hwmod_class,
634 .clkdm_name = "l4ls_clkdm",
635 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
636 .main_clk = "l4ls_gclk",
637 .prcm = {
638 .omap4 = {
639 .clkctrl_offs = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
640 .modulemode = MODULEMODE_SWCTRL,
641 },
642 },
643 .opt_clks = gpio2_opt_clks,
644 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
645 .dev_attr = &gpio_dev_attr,
646 };
647
648 /* gpio3 */
649 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
650 { .role = "dbclk", .clk = "gpio3_dbclk" },
651 };
652
653 struct omap_hwmod am33xx_gpio3_hwmod = {
654 .name = "gpio4",
655 .class = &am33xx_gpio_hwmod_class,
656 .clkdm_name = "l4ls_clkdm",
657 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
658 .main_clk = "l4ls_gclk",
659 .prcm = {
660 .omap4 = {
661 .clkctrl_offs = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
662 .modulemode = MODULEMODE_SWCTRL,
663 },
664 },
665 .opt_clks = gpio3_opt_clks,
666 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
667 .dev_attr = &gpio_dev_attr,
668 };
669
670 /* gpmc */
671 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
672 .rev_offs = 0x0,
673 .sysc_offs = 0x10,
674 .syss_offs = 0x14,
675 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
676 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
677 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
678 .sysc_fields = &omap_hwmod_sysc_type1,
679 };
680
681 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
682 .name = "gpmc",
683 .sysc = &gpmc_sysc,
684 };
685
686 struct omap_hwmod am33xx_gpmc_hwmod = {
687 .name = "gpmc",
688 .class = &am33xx_gpmc_hwmod_class,
689 .clkdm_name = "l3s_clkdm",
690 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
691 .main_clk = "l3s_gclk",
692 .prcm = {
693 .omap4 = {
694 .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
695 .modulemode = MODULEMODE_SWCTRL,
696 },
697 },
698 };
699
700 /* 'i2c' class */
701 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
702 .sysc_offs = 0x0010,
703 .syss_offs = 0x0090,
704 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
705 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
706 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
707 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
708 SIDLE_SMART_WKUP),
709 .sysc_fields = &omap_hwmod_sysc_type1,
710 };
711
712 static struct omap_hwmod_class i2c_class = {
713 .name = "i2c",
714 .sysc = &am33xx_i2c_sysc,
715 .rev = OMAP_I2C_IP_VERSION_2,
716 .reset = &omap_i2c_reset,
717 };
718
719 static struct omap_i2c_dev_attr i2c_dev_attr = {
720 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
721 };
722
723 /* i2c1 */
724 struct omap_hwmod am33xx_i2c1_hwmod = {
725 .name = "i2c1",
726 .class = &i2c_class,
727 .clkdm_name = "l4_wkup_clkdm",
728 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
729 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
730 .prcm = {
731 .omap4 = {
732 .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
733 .modulemode = MODULEMODE_SWCTRL,
734 },
735 },
736 .dev_attr = &i2c_dev_attr,
737 };
738
739 /* i2c1 */
740 struct omap_hwmod am33xx_i2c2_hwmod = {
741 .name = "i2c2",
742 .class = &i2c_class,
743 .clkdm_name = "l4ls_clkdm",
744 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
745 .main_clk = "dpll_per_m2_div4_ck",
746 .prcm = {
747 .omap4 = {
748 .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
749 .modulemode = MODULEMODE_SWCTRL,
750 },
751 },
752 .dev_attr = &i2c_dev_attr,
753 };
754
755 /* i2c3 */
756 struct omap_hwmod am33xx_i2c3_hwmod = {
757 .name = "i2c3",
758 .class = &i2c_class,
759 .clkdm_name = "l4ls_clkdm",
760 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
761 .main_clk = "dpll_per_m2_div4_ck",
762 .prcm = {
763 .omap4 = {
764 .clkctrl_offs = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
765 .modulemode = MODULEMODE_SWCTRL,
766 },
767 },
768 .dev_attr = &i2c_dev_attr,
769 };
770
771 /*
772 * 'mailbox' class
773 * mailbox module allowing communication between the on-chip processors using a
774 * queued mailbox-interrupt mechanism.
775 */
776 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
777 .rev_offs = 0x0000,
778 .sysc_offs = 0x0010,
779 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
780 SYSC_HAS_SOFTRESET),
781 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
782 .sysc_fields = &omap_hwmod_sysc_type2,
783 };
784
785 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
786 .name = "mailbox",
787 .sysc = &am33xx_mailbox_sysc,
788 };
789
790 struct omap_hwmod am33xx_mailbox_hwmod = {
791 .name = "mailbox",
792 .class = &am33xx_mailbox_hwmod_class,
793 .clkdm_name = "l4ls_clkdm",
794 .main_clk = "l4ls_gclk",
795 .prcm = {
796 .omap4 = {
797 .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
798 .modulemode = MODULEMODE_SWCTRL,
799 },
800 },
801 };
802
803 /*
804 * 'mcasp' class
805 */
806 static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
807 .rev_offs = 0x0,
808 .sysc_offs = 0x4,
809 .sysc_flags = SYSC_HAS_SIDLEMODE,
810 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
811 .sysc_fields = &omap_hwmod_sysc_type3,
812 };
813
814 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
815 .name = "mcasp",
816 .sysc = &am33xx_mcasp_sysc,
817 };
818
819 /* mcasp0 */
820 struct omap_hwmod am33xx_mcasp0_hwmod = {
821 .name = "mcasp0",
822 .class = &am33xx_mcasp_hwmod_class,
823 .clkdm_name = "l3s_clkdm",
824 .main_clk = "mcasp0_fck",
825 .prcm = {
826 .omap4 = {
827 .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
828 .modulemode = MODULEMODE_SWCTRL,
829 },
830 },
831 };
832
833 /* mcasp1 */
834 struct omap_hwmod am33xx_mcasp1_hwmod = {
835 .name = "mcasp1",
836 .class = &am33xx_mcasp_hwmod_class,
837 .clkdm_name = "l3s_clkdm",
838 .main_clk = "mcasp1_fck",
839 .prcm = {
840 .omap4 = {
841 .clkctrl_offs = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
842 .modulemode = MODULEMODE_SWCTRL,
843 },
844 },
845 };
846
847 /* 'mmc' class */
848 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
849 .rev_offs = 0x1fc,
850 .sysc_offs = 0x10,
851 .syss_offs = 0x14,
852 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
853 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
854 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
855 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
856 .sysc_fields = &omap_hwmod_sysc_type1,
857 };
858
859 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
860 .name = "mmc",
861 .sysc = &am33xx_mmc_sysc,
862 };
863
864 /* mmc0 */
865 static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
866 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
867 };
868
869 struct omap_hwmod am33xx_mmc0_hwmod = {
870 .name = "mmc1",
871 .class = &am33xx_mmc_hwmod_class,
872 .clkdm_name = "l4ls_clkdm",
873 .main_clk = "mmc_clk",
874 .prcm = {
875 .omap4 = {
876 .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
877 .modulemode = MODULEMODE_SWCTRL,
878 },
879 },
880 .dev_attr = &am33xx_mmc0_dev_attr,
881 };
882
883 /* mmc1 */
884 static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
885 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
886 };
887
888 struct omap_hwmod am33xx_mmc1_hwmod = {
889 .name = "mmc2",
890 .class = &am33xx_mmc_hwmod_class,
891 .clkdm_name = "l4ls_clkdm",
892 .main_clk = "mmc_clk",
893 .prcm = {
894 .omap4 = {
895 .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
896 .modulemode = MODULEMODE_SWCTRL,
897 },
898 },
899 .dev_attr = &am33xx_mmc1_dev_attr,
900 };
901
902 /* mmc2 */
903 static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
904 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
905 };
906 struct omap_hwmod am33xx_mmc2_hwmod = {
907 .name = "mmc3",
908 .class = &am33xx_mmc_hwmod_class,
909 .clkdm_name = "l3s_clkdm",
910 .main_clk = "mmc_clk",
911 .prcm = {
912 .omap4 = {
913 .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
914 .modulemode = MODULEMODE_SWCTRL,
915 },
916 },
917 .dev_attr = &am33xx_mmc2_dev_attr,
918 };
919
920 /*
921 * 'rtc' class
922 * rtc subsystem
923 */
924 static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
925 .rev_offs = 0x0074,
926 .sysc_offs = 0x0078,
927 .sysc_flags = SYSC_HAS_SIDLEMODE,
928 .idlemodes = (SIDLE_FORCE | SIDLE_NO |
929 SIDLE_SMART | SIDLE_SMART_WKUP),
930 .sysc_fields = &omap_hwmod_sysc_type3,
931 };
932
933 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
934 .name = "rtc",
935 .sysc = &am33xx_rtc_sysc,
936 };
937
938 struct omap_hwmod am33xx_rtc_hwmod = {
939 .name = "rtc",
940 .class = &am33xx_rtc_hwmod_class,
941 .clkdm_name = "l4_rtc_clkdm",
942 .main_clk = "clk_32768_ck",
943 .prcm = {
944 .omap4 = {
945 .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
946 .modulemode = MODULEMODE_SWCTRL,
947 },
948 },
949 };
950
951 /* 'spi' class */
952 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
953 .rev_offs = 0x0000,
954 .sysc_offs = 0x0110,
955 .syss_offs = 0x0114,
956 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
957 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
958 SYSS_HAS_RESET_STATUS),
959 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
960 .sysc_fields = &omap_hwmod_sysc_type1,
961 };
962
963 struct omap_hwmod_class am33xx_spi_hwmod_class = {
964 .name = "mcspi",
965 .sysc = &am33xx_mcspi_sysc,
966 .rev = OMAP4_MCSPI_REV,
967 };
968
969 /* spi0 */
970 struct omap2_mcspi_dev_attr mcspi_attrib = {
971 .num_chipselect = 2,
972 };
973 struct omap_hwmod am33xx_spi0_hwmod = {
974 .name = "spi0",
975 .class = &am33xx_spi_hwmod_class,
976 .clkdm_name = "l4ls_clkdm",
977 .main_clk = "dpll_per_m2_div4_ck",
978 .prcm = {
979 .omap4 = {
980 .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
981 .modulemode = MODULEMODE_SWCTRL,
982 },
983 },
984 .dev_attr = &mcspi_attrib,
985 };
986
987 /* spi1 */
988 struct omap_hwmod am33xx_spi1_hwmod = {
989 .name = "spi1",
990 .class = &am33xx_spi_hwmod_class,
991 .clkdm_name = "l4ls_clkdm",
992 .main_clk = "dpll_per_m2_div4_ck",
993 .prcm = {
994 .omap4 = {
995 .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
996 .modulemode = MODULEMODE_SWCTRL,
997 },
998 },
999 .dev_attr = &mcspi_attrib,
1000 };
1001
1002 /*
1003 * 'spinlock' class
1004 * spinlock provides hardware assistance for synchronizing the
1005 * processes running on multiple processors
1006 */
1007
1008 static struct omap_hwmod_class_sysconfig am33xx_spinlock_sysc = {
1009 .rev_offs = 0x0000,
1010 .sysc_offs = 0x0010,
1011 .syss_offs = 0x0014,
1012 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1013 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1014 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1015 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1016 .sysc_fields = &omap_hwmod_sysc_type1,
1017 };
1018
1019 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
1020 .name = "spinlock",
1021 .sysc = &am33xx_spinlock_sysc,
1022 };
1023
1024 struct omap_hwmod am33xx_spinlock_hwmod = {
1025 .name = "spinlock",
1026 .class = &am33xx_spinlock_hwmod_class,
1027 .clkdm_name = "l4ls_clkdm",
1028 .main_clk = "l4ls_gclk",
1029 .prcm = {
1030 .omap4 = {
1031 .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
1032 .modulemode = MODULEMODE_SWCTRL,
1033 },
1034 },
1035 };
1036
1037 /* 'timer 2-7' class */
1038 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1039 .rev_offs = 0x0000,
1040 .sysc_offs = 0x0010,
1041 .syss_offs = 0x0014,
1042 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1043 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1044 SIDLE_SMART_WKUP),
1045 .sysc_fields = &omap_hwmod_sysc_type2,
1046 };
1047
1048 struct omap_hwmod_class am33xx_timer_hwmod_class = {
1049 .name = "timer",
1050 .sysc = &am33xx_timer_sysc,
1051 };
1052
1053 /* timer1 1ms */
1054 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
1055 .rev_offs = 0x0000,
1056 .sysc_offs = 0x0010,
1057 .syss_offs = 0x0014,
1058 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1059 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1060 SYSS_HAS_RESET_STATUS),
1061 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1062 .sysc_fields = &omap_hwmod_sysc_type1,
1063 };
1064
1065 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
1066 .name = "timer",
1067 .sysc = &am33xx_timer1ms_sysc,
1068 };
1069
1070 struct omap_hwmod am33xx_timer1_hwmod = {
1071 .name = "timer1",
1072 .class = &am33xx_timer1ms_hwmod_class,
1073 .clkdm_name = "l4_wkup_clkdm",
1074 .main_clk = "timer1_fck",
1075 .prcm = {
1076 .omap4 = {
1077 .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
1078 .modulemode = MODULEMODE_SWCTRL,
1079 },
1080 },
1081 };
1082
1083 struct omap_hwmod am33xx_timer2_hwmod = {
1084 .name = "timer2",
1085 .class = &am33xx_timer_hwmod_class,
1086 .clkdm_name = "l4ls_clkdm",
1087 .main_clk = "timer2_fck",
1088 .prcm = {
1089 .omap4 = {
1090 .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
1091 .modulemode = MODULEMODE_SWCTRL,
1092 },
1093 },
1094 };
1095
1096 struct omap_hwmod am33xx_timer3_hwmod = {
1097 .name = "timer3",
1098 .class = &am33xx_timer_hwmod_class,
1099 .clkdm_name = "l4ls_clkdm",
1100 .main_clk = "timer3_fck",
1101 .prcm = {
1102 .omap4 = {
1103 .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
1104 .modulemode = MODULEMODE_SWCTRL,
1105 },
1106 },
1107 };
1108
1109 struct omap_hwmod am33xx_timer4_hwmod = {
1110 .name = "timer4",
1111 .class = &am33xx_timer_hwmod_class,
1112 .clkdm_name = "l4ls_clkdm",
1113 .main_clk = "timer4_fck",
1114 .prcm = {
1115 .omap4 = {
1116 .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
1117 .modulemode = MODULEMODE_SWCTRL,
1118 },
1119 },
1120 };
1121
1122 struct omap_hwmod am33xx_timer5_hwmod = {
1123 .name = "timer5",
1124 .class = &am33xx_timer_hwmod_class,
1125 .clkdm_name = "l4ls_clkdm",
1126 .main_clk = "timer5_fck",
1127 .prcm = {
1128 .omap4 = {
1129 .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
1130 .modulemode = MODULEMODE_SWCTRL,
1131 },
1132 },
1133 };
1134
1135 struct omap_hwmod am33xx_timer6_hwmod = {
1136 .name = "timer6",
1137 .class = &am33xx_timer_hwmod_class,
1138 .clkdm_name = "l4ls_clkdm",
1139 .main_clk = "timer6_fck",
1140 .prcm = {
1141 .omap4 = {
1142 .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
1143 .modulemode = MODULEMODE_SWCTRL,
1144 },
1145 },
1146 };
1147
1148 struct omap_hwmod am33xx_timer7_hwmod = {
1149 .name = "timer7",
1150 .class = &am33xx_timer_hwmod_class,
1151 .clkdm_name = "l4ls_clkdm",
1152 .main_clk = "timer7_fck",
1153 .prcm = {
1154 .omap4 = {
1155 .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
1156 .modulemode = MODULEMODE_SWCTRL,
1157 },
1158 },
1159 };
1160
1161 /* tpcc */
1162 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1163 .name = "tpcc",
1164 };
1165
1166 struct omap_hwmod am33xx_tpcc_hwmod = {
1167 .name = "tpcc",
1168 .class = &am33xx_tpcc_hwmod_class,
1169 .clkdm_name = "l3_clkdm",
1170 .main_clk = "l3_gclk",
1171 .prcm = {
1172 .omap4 = {
1173 .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
1174 .modulemode = MODULEMODE_SWCTRL,
1175 },
1176 },
1177 };
1178
1179 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
1180 .rev_offs = 0x0,
1181 .sysc_offs = 0x10,
1182 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1183 SYSC_HAS_MIDLEMODE),
1184 .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
1185 .sysc_fields = &omap_hwmod_sysc_type2,
1186 };
1187
1188 /* 'tptc' class */
1189 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1190 .name = "tptc",
1191 .sysc = &am33xx_tptc_sysc,
1192 };
1193
1194 /* tptc0 */
1195 struct omap_hwmod am33xx_tptc0_hwmod = {
1196 .name = "tptc0",
1197 .class = &am33xx_tptc_hwmod_class,
1198 .clkdm_name = "l3_clkdm",
1199 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1200 .main_clk = "l3_gclk",
1201 .prcm = {
1202 .omap4 = {
1203 .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
1204 .modulemode = MODULEMODE_SWCTRL,
1205 },
1206 },
1207 };
1208
1209 /* tptc1 */
1210 struct omap_hwmod am33xx_tptc1_hwmod = {
1211 .name = "tptc1",
1212 .class = &am33xx_tptc_hwmod_class,
1213 .clkdm_name = "l3_clkdm",
1214 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1215 .main_clk = "l3_gclk",
1216 .prcm = {
1217 .omap4 = {
1218 .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
1219 .modulemode = MODULEMODE_SWCTRL,
1220 },
1221 },
1222 };
1223
1224 /* tptc2 */
1225 struct omap_hwmod am33xx_tptc2_hwmod = {
1226 .name = "tptc2",
1227 .class = &am33xx_tptc_hwmod_class,
1228 .clkdm_name = "l3_clkdm",
1229 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1230 .main_clk = "l3_gclk",
1231 .prcm = {
1232 .omap4 = {
1233 .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
1234 .modulemode = MODULEMODE_SWCTRL,
1235 },
1236 },
1237 };
1238
1239 /* 'uart' class */
1240 static struct omap_hwmod_class_sysconfig uart_sysc = {
1241 .rev_offs = 0x50,
1242 .sysc_offs = 0x54,
1243 .syss_offs = 0x58,
1244 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1245 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1246 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1247 SIDLE_SMART_WKUP),
1248 .sysc_fields = &omap_hwmod_sysc_type1,
1249 };
1250
1251 static struct omap_hwmod_class uart_class = {
1252 .name = "uart",
1253 .sysc = &uart_sysc,
1254 };
1255
1256 struct omap_hwmod am33xx_uart1_hwmod = {
1257 .name = "uart1",
1258 .class = &uart_class,
1259 .clkdm_name = "l4_wkup_clkdm",
1260 .flags = DEBUG_AM33XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
1261 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
1262 .prcm = {
1263 .omap4 = {
1264 .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
1265 .modulemode = MODULEMODE_SWCTRL,
1266 },
1267 },
1268 };
1269
1270 struct omap_hwmod am33xx_uart2_hwmod = {
1271 .name = "uart2",
1272 .class = &uart_class,
1273 .clkdm_name = "l4ls_clkdm",
1274 .flags = HWMOD_SWSUP_SIDLE_ACT,
1275 .main_clk = "dpll_per_m2_div4_ck",
1276 .prcm = {
1277 .omap4 = {
1278 .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
1279 .modulemode = MODULEMODE_SWCTRL,
1280 },
1281 },
1282 };
1283
1284 /* uart3 */
1285 struct omap_hwmod am33xx_uart3_hwmod = {
1286 .name = "uart3",
1287 .class = &uart_class,
1288 .clkdm_name = "l4ls_clkdm",
1289 .flags = HWMOD_SWSUP_SIDLE_ACT,
1290 .main_clk = "dpll_per_m2_div4_ck",
1291 .prcm = {
1292 .omap4 = {
1293 .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
1294 .modulemode = MODULEMODE_SWCTRL,
1295 },
1296 },
1297 };
1298
1299 struct omap_hwmod am33xx_uart4_hwmod = {
1300 .name = "uart4",
1301 .class = &uart_class,
1302 .clkdm_name = "l4ls_clkdm",
1303 .flags = HWMOD_SWSUP_SIDLE_ACT,
1304 .main_clk = "dpll_per_m2_div4_ck",
1305 .prcm = {
1306 .omap4 = {
1307 .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
1308 .modulemode = MODULEMODE_SWCTRL,
1309 },
1310 },
1311 };
1312
1313 struct omap_hwmod am33xx_uart5_hwmod = {
1314 .name = "uart5",
1315 .class = &uart_class,
1316 .clkdm_name = "l4ls_clkdm",
1317 .flags = HWMOD_SWSUP_SIDLE_ACT,
1318 .main_clk = "dpll_per_m2_div4_ck",
1319 .prcm = {
1320 .omap4 = {
1321 .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
1322 .modulemode = MODULEMODE_SWCTRL,
1323 },
1324 },
1325 };
1326
1327 struct omap_hwmod am33xx_uart6_hwmod = {
1328 .name = "uart6",
1329 .class = &uart_class,
1330 .clkdm_name = "l4ls_clkdm",
1331 .flags = HWMOD_SWSUP_SIDLE_ACT,
1332 .main_clk = "dpll_per_m2_div4_ck",
1333 .prcm = {
1334 .omap4 = {
1335 .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
1336 .modulemode = MODULEMODE_SWCTRL,
1337 },
1338 },
1339 };
1340
1341 /* 'wd_timer' class */
1342 static struct omap_hwmod_class_sysconfig wdt_sysc = {
1343 .rev_offs = 0x0,
1344 .sysc_offs = 0x10,
1345 .syss_offs = 0x14,
1346 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1347 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1348 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1349 SIDLE_SMART_WKUP),
1350 .sysc_fields = &omap_hwmod_sysc_type1,
1351 };
1352
1353 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
1354 .name = "wd_timer",
1355 .sysc = &wdt_sysc,
1356 .pre_shutdown = &omap2_wd_timer_disable,
1357 };
1358
1359 /*
1360 * XXX: device.c file uses hardcoded name for watchdog timer
1361 * driver "wd_timer2, so we are also using same name as of now...
1362 */
1363 struct omap_hwmod am33xx_wd_timer1_hwmod = {
1364 .name = "wd_timer2",
1365 .class = &am33xx_wd_timer_hwmod_class,
1366 .clkdm_name = "l4_wkup_clkdm",
1367 .flags = HWMOD_SWSUP_SIDLE,
1368 .main_clk = "wdt1_fck",
1369 .prcm = {
1370 .omap4 = {
1371 .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
1372 .modulemode = MODULEMODE_SWCTRL,
1373 },
1374 },
1375 };
Linux kernel - Deliverables
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