2 * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
4 * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
6 * This file is automatically generated from the AM33XX hardware databases.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/i2c-omap.h>
19 #include "omap_hwmod.h"
20 #include <linux/platform_data/gpio-omap.h>
21 #include <linux/platform_data/spi-omap2-mcspi.h>
23 #include "omap_hwmod_common_data.h"
28 #include "prm-regbits-33xx.h"
41 static struct omap_hwmod_class_sysconfig am33xx_emif_sysc
= {
45 static struct omap_hwmod_class am33xx_emif_hwmod_class
= {
47 .sysc
= &am33xx_emif_sysc
,
51 static struct omap_hwmod am33xx_emif_hwmod
= {
53 .class = &am33xx_emif_hwmod_class
,
54 .clkdm_name
= "l3_clkdm",
55 .flags
= (HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
),
56 .main_clk
= "dpll_ddr_m2_div2_ck",
59 .clkctrl_offs
= AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET
,
60 .modulemode
= MODULEMODE_SWCTRL
,
67 * instance(s): l3_main, l3_s, l3_instr
69 static struct omap_hwmod_class am33xx_l3_hwmod_class
= {
73 static struct omap_hwmod am33xx_l3_main_hwmod
= {
75 .class = &am33xx_l3_hwmod_class
,
76 .clkdm_name
= "l3_clkdm",
77 .flags
= (HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
),
78 .main_clk
= "l3_gclk",
81 .clkctrl_offs
= AM33XX_CM_PER_L3_CLKCTRL_OFFSET
,
82 .modulemode
= MODULEMODE_SWCTRL
,
88 static struct omap_hwmod am33xx_l3_s_hwmod
= {
90 .class = &am33xx_l3_hwmod_class
,
91 .clkdm_name
= "l3s_clkdm",
95 static struct omap_hwmod am33xx_l3_instr_hwmod
= {
97 .class = &am33xx_l3_hwmod_class
,
98 .clkdm_name
= "l3_clkdm",
99 .flags
= (HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
),
100 .main_clk
= "l3_gclk",
103 .clkctrl_offs
= AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET
,
104 .modulemode
= MODULEMODE_SWCTRL
,
111 * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
113 static struct omap_hwmod_class am33xx_l4_hwmod_class
= {
118 static struct omap_hwmod am33xx_l4_ls_hwmod
= {
120 .class = &am33xx_l4_hwmod_class
,
121 .clkdm_name
= "l4ls_clkdm",
122 .flags
= (HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
),
123 .main_clk
= "l4ls_gclk",
126 .clkctrl_offs
= AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET
,
127 .modulemode
= MODULEMODE_SWCTRL
,
133 static struct omap_hwmod am33xx_l4_hs_hwmod
= {
135 .class = &am33xx_l4_hwmod_class
,
136 .clkdm_name
= "l4hs_clkdm",
137 .flags
= (HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
),
138 .main_clk
= "l4hs_gclk",
141 .clkctrl_offs
= AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET
,
142 .modulemode
= MODULEMODE_SWCTRL
,
149 static struct omap_hwmod am33xx_l4_wkup_hwmod
= {
151 .class = &am33xx_l4_hwmod_class
,
152 .clkdm_name
= "l4_wkup_clkdm",
153 .flags
= (HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
),
156 .clkctrl_offs
= AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET
,
157 .modulemode
= MODULEMODE_SWCTRL
,
165 static struct omap_hwmod_class am33xx_mpu_hwmod_class
= {
169 static struct omap_hwmod am33xx_mpu_hwmod
= {
171 .class = &am33xx_mpu_hwmod_class
,
172 .clkdm_name
= "mpu_clkdm",
173 .flags
= (HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
),
174 .main_clk
= "dpll_mpu_m2_ck",
177 .clkctrl_offs
= AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET
,
178 .modulemode
= MODULEMODE_SWCTRL
,
185 * Wakeup controller sub-system under wakeup domain
187 static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class
= {
191 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets
[] = {
192 { .name
= "wkup_m3", .rst_shift
= 3, .st_shift
= 5 },
196 static struct omap_hwmod am33xx_wkup_m3_hwmod
= {
198 .class = &am33xx_wkup_m3_hwmod_class
,
199 .clkdm_name
= "l4_wkup_aon_clkdm",
200 /* Keep hardreset asserted */
201 .flags
= HWMOD_INIT_NO_RESET
| HWMOD_NO_IDLEST
,
202 .main_clk
= "dpll_core_m4_div2_ck",
205 .clkctrl_offs
= AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET
,
206 .rstctrl_offs
= AM33XX_RM_WKUP_RSTCTRL_OFFSET
,
207 .rstst_offs
= AM33XX_RM_WKUP_RSTST_OFFSET
,
208 .modulemode
= MODULEMODE_SWCTRL
,
211 .rst_lines
= am33xx_wkup_m3_resets
,
212 .rst_lines_cnt
= ARRAY_SIZE(am33xx_wkup_m3_resets
),
217 * Programmable Real-Time Unit and Industrial Communication Subsystem
219 static struct omap_hwmod_class am33xx_pruss_hwmod_class
= {
223 static struct omap_hwmod_rst_info am33xx_pruss_resets
[] = {
224 { .name
= "pruss", .rst_shift
= 1 },
228 /* Pseudo hwmod for reset control purpose only */
229 static struct omap_hwmod am33xx_pruss_hwmod
= {
231 .class = &am33xx_pruss_hwmod_class
,
232 .clkdm_name
= "pruss_ocp_clkdm",
233 .main_clk
= "pruss_ocp_gclk",
236 .clkctrl_offs
= AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET
,
237 .rstctrl_offs
= AM33XX_RM_PER_RSTCTRL_OFFSET
,
238 .modulemode
= MODULEMODE_SWCTRL
,
241 .rst_lines
= am33xx_pruss_resets
,
242 .rst_lines_cnt
= ARRAY_SIZE(am33xx_pruss_resets
),
246 /* Pseudo hwmod for reset control purpose only */
247 static struct omap_hwmod_class am33xx_gfx_hwmod_class
= {
251 static struct omap_hwmod_rst_info am33xx_gfx_resets
[] = {
252 { .name
= "gfx", .rst_shift
= 0, .st_shift
= 0},
255 static struct omap_hwmod am33xx_gfx_hwmod
= {
257 .class = &am33xx_gfx_hwmod_class
,
258 .clkdm_name
= "gfx_l3_clkdm",
259 .main_clk
= "gfx_fck_div_ck",
262 .clkctrl_offs
= AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET
,
263 .rstctrl_offs
= AM33XX_RM_GFX_RSTCTRL_OFFSET
,
264 .rstst_offs
= AM33XX_RM_GFX_RSTST_OFFSET
,
265 .modulemode
= MODULEMODE_SWCTRL
,
268 .rst_lines
= am33xx_gfx_resets
,
269 .rst_lines_cnt
= ARRAY_SIZE(am33xx_gfx_resets
),
274 * power and reset manager (whole prcm infrastructure)
276 static struct omap_hwmod_class am33xx_prcm_hwmod_class
= {
281 static struct omap_hwmod am33xx_prcm_hwmod
= {
283 .class = &am33xx_prcm_hwmod_class
,
284 .clkdm_name
= "l4_wkup_clkdm",
289 * TouchScreen Controller (Anolog-To-Digital Converter)
291 static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc
= {
294 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
295 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
297 .sysc_fields
= &omap_hwmod_sysc_type2
,
300 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class
= {
302 .sysc
= &am33xx_adc_tsc_sysc
,
305 static struct omap_hwmod am33xx_adc_tsc_hwmod
= {
307 .class = &am33xx_adc_tsc_hwmod_class
,
308 .clkdm_name
= "l4_wkup_clkdm",
309 .main_clk
= "adc_tsc_fck",
312 .clkctrl_offs
= AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET
,
313 .modulemode
= MODULEMODE_SWCTRL
,
319 * Modules omap_hwmod structures
321 * The following IPs are excluded for the moment because:
322 * - They do not need an explicit SW control using omap_hwmod API.
323 * - They still need to be validated with the driver
324 * properly adapted to omap_hwmod / omap_device
326 * - cEFUSE (doesn't fall under any ocp_if)
334 static struct omap_hwmod_class am33xx_cefuse_hwmod_class
= {
338 static struct omap_hwmod am33xx_cefuse_hwmod
= {
340 .class = &am33xx_cefuse_hwmod_class
,
341 .clkdm_name
= "l4_cefuse_clkdm",
342 .main_clk
= "cefuse_fck",
345 .clkctrl_offs
= AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET
,
346 .modulemode
= MODULEMODE_SWCTRL
,
354 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class
= {
358 static struct omap_hwmod am33xx_clkdiv32k_hwmod
= {
360 .class = &am33xx_clkdiv32k_hwmod_class
,
361 .clkdm_name
= "clk_24mhz_clkdm",
362 .main_clk
= "clkdiv32k_ick",
365 .clkctrl_offs
= AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET
,
366 .modulemode
= MODULEMODE_SWCTRL
,
372 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class
= {
376 static struct omap_hwmod am33xx_ocpwp_hwmod
= {
378 .class = &am33xx_ocpwp_hwmod_class
,
379 .clkdm_name
= "l4ls_clkdm",
380 .main_clk
= "l4ls_gclk",
383 .clkctrl_offs
= AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET
,
384 .modulemode
= MODULEMODE_SWCTRL
,
393 static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc
= {
397 .sysc_flags
= SYSS_HAS_RESET_STATUS
,
400 static struct omap_hwmod_class am33xx_aes0_hwmod_class
= {
402 .sysc
= &am33xx_aes0_sysc
,
405 static struct omap_hwmod am33xx_aes0_hwmod
= {
407 .class = &am33xx_aes0_hwmod_class
,
408 .clkdm_name
= "l3_clkdm",
409 .main_clk
= "aes0_fck",
412 .clkctrl_offs
= AM33XX_CM_PER_AES0_CLKCTRL_OFFSET
,
413 .modulemode
= MODULEMODE_SWCTRL
,
418 /* sha0 HIB2 (the 'P' (public) device) */
419 static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc
= {
423 .sysc_flags
= SYSS_HAS_RESET_STATUS
,
426 static struct omap_hwmod_class am33xx_sha0_hwmod_class
= {
428 .sysc
= &am33xx_sha0_sysc
,
431 static struct omap_hwmod am33xx_sha0_hwmod
= {
433 .class = &am33xx_sha0_hwmod_class
,
434 .clkdm_name
= "l3_clkdm",
435 .main_clk
= "l3_gclk",
438 .clkctrl_offs
= AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET
,
439 .modulemode
= MODULEMODE_SWCTRL
,
445 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class
= {
449 static struct omap_hwmod am33xx_ocmcram_hwmod
= {
451 .class = &am33xx_ocmcram_hwmod_class
,
452 .clkdm_name
= "l3_clkdm",
453 .flags
= (HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
),
454 .main_clk
= "l3_gclk",
457 .clkctrl_offs
= AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET
,
458 .modulemode
= MODULEMODE_SWCTRL
,
467 static struct omap_hwmod_opt_clk debugss_opt_clks
[] = {
468 { .role
= "dbg_sysclk", .clk
= "dbg_sysclk_ck" },
469 { .role
= "dbg_clka", .clk
= "dbg_clka_ck" },
472 static struct omap_hwmod_class am33xx_debugss_hwmod_class
= {
476 static struct omap_hwmod am33xx_debugss_hwmod
= {
478 .class = &am33xx_debugss_hwmod_class
,
479 .clkdm_name
= "l3_aon_clkdm",
480 .main_clk
= "trace_clk_div_ck",
483 .clkctrl_offs
= AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET
,
484 .modulemode
= MODULEMODE_SWCTRL
,
487 .opt_clks
= debugss_opt_clks
,
488 .opt_clks_cnt
= ARRAY_SIZE(debugss_opt_clks
),
491 /* 'smartreflex' class */
492 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class
= {
493 .name
= "smartreflex",
497 static struct omap_hwmod am33xx_smartreflex0_hwmod
= {
498 .name
= "smartreflex0",
499 .class = &am33xx_smartreflex_hwmod_class
,
500 .clkdm_name
= "l4_wkup_clkdm",
501 .main_clk
= "smartreflex0_fck",
504 .clkctrl_offs
= AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET
,
505 .modulemode
= MODULEMODE_SWCTRL
,
511 static struct omap_hwmod am33xx_smartreflex1_hwmod
= {
512 .name
= "smartreflex1",
513 .class = &am33xx_smartreflex_hwmod_class
,
514 .clkdm_name
= "l4_wkup_clkdm",
515 .main_clk
= "smartreflex1_fck",
518 .clkctrl_offs
= AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET
,
519 .modulemode
= MODULEMODE_SWCTRL
,
525 * 'control' module class
527 static struct omap_hwmod_class am33xx_control_hwmod_class
= {
531 static struct omap_hwmod am33xx_control_hwmod
= {
533 .class = &am33xx_control_hwmod_class
,
534 .clkdm_name
= "l4_wkup_clkdm",
535 .flags
= (HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
),
536 .main_clk
= "dpll_core_m4_div2_ck",
539 .clkctrl_offs
= AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET
,
540 .modulemode
= MODULEMODE_SWCTRL
,
547 * cpsw/cpgmac sub system
549 static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc
= {
553 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_MIDLEMODE
|
554 SYSS_HAS_RESET_STATUS
),
555 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| MSTANDBY_FORCE
|
557 .sysc_fields
= &omap_hwmod_sysc_type3
,
560 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class
= {
562 .sysc
= &am33xx_cpgmac_sysc
,
565 static struct omap_hwmod am33xx_cpgmac0_hwmod
= {
567 .class = &am33xx_cpgmac0_hwmod_class
,
568 .clkdm_name
= "cpsw_125mhz_clkdm",
569 .flags
= (HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
),
570 .main_clk
= "cpsw_125mhz_gclk",
574 .clkctrl_offs
= AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET
,
575 .modulemode
= MODULEMODE_SWCTRL
,
583 static struct omap_hwmod_class am33xx_mdio_hwmod_class
= {
584 .name
= "davinci_mdio",
587 static struct omap_hwmod am33xx_mdio_hwmod
= {
588 .name
= "davinci_mdio",
589 .class = &am33xx_mdio_hwmod_class
,
590 .clkdm_name
= "cpsw_125mhz_clkdm",
591 .main_clk
= "cpsw_125mhz_gclk",
597 static struct omap_hwmod_class am33xx_dcan_hwmod_class
= {
602 static struct omap_hwmod am33xx_dcan0_hwmod
= {
604 .class = &am33xx_dcan_hwmod_class
,
605 .clkdm_name
= "l4ls_clkdm",
606 .main_clk
= "dcan0_fck",
609 .clkctrl_offs
= AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET
,
610 .modulemode
= MODULEMODE_SWCTRL
,
616 static struct omap_hwmod am33xx_dcan1_hwmod
= {
618 .class = &am33xx_dcan_hwmod_class
,
619 .clkdm_name
= "l4ls_clkdm",
620 .main_clk
= "dcan1_fck",
623 .clkctrl_offs
= AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET
,
624 .modulemode
= MODULEMODE_SWCTRL
,
630 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc
= {
634 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
635 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
|
636 SYSS_HAS_RESET_STATUS
),
637 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
638 .sysc_fields
= &omap_hwmod_sysc_type1
,
641 static struct omap_hwmod_class am33xx_elm_hwmod_class
= {
643 .sysc
= &am33xx_elm_sysc
,
646 static struct omap_hwmod am33xx_elm_hwmod
= {
648 .class = &am33xx_elm_hwmod_class
,
649 .clkdm_name
= "l4ls_clkdm",
650 .main_clk
= "l4ls_gclk",
653 .clkctrl_offs
= AM33XX_CM_PER_ELM_CLKCTRL_OFFSET
,
654 .modulemode
= MODULEMODE_SWCTRL
,
660 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc
= {
663 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_MIDLEMODE
),
664 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
665 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
666 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
667 .sysc_fields
= &omap_hwmod_sysc_type2
,
670 static struct omap_hwmod_class am33xx_epwmss_hwmod_class
= {
672 .sysc
= &am33xx_epwmss_sysc
,
675 static struct omap_hwmod_class am33xx_ecap_hwmod_class
= {
679 static struct omap_hwmod_class am33xx_eqep_hwmod_class
= {
683 static struct omap_hwmod_class am33xx_ehrpwm_hwmod_class
= {
688 static struct omap_hwmod am33xx_epwmss0_hwmod
= {
690 .class = &am33xx_epwmss_hwmod_class
,
691 .clkdm_name
= "l4ls_clkdm",
692 .main_clk
= "l4ls_gclk",
695 .clkctrl_offs
= AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET
,
696 .modulemode
= MODULEMODE_SWCTRL
,
702 static struct omap_hwmod am33xx_ecap0_hwmod
= {
704 .class = &am33xx_ecap_hwmod_class
,
705 .clkdm_name
= "l4ls_clkdm",
706 .main_clk
= "l4ls_gclk",
710 static struct omap_hwmod am33xx_eqep0_hwmod
= {
712 .class = &am33xx_eqep_hwmod_class
,
713 .clkdm_name
= "l4ls_clkdm",
714 .main_clk
= "l4ls_gclk",
718 static struct omap_hwmod am33xx_ehrpwm0_hwmod
= {
720 .class = &am33xx_ehrpwm_hwmod_class
,
721 .clkdm_name
= "l4ls_clkdm",
722 .main_clk
= "l4ls_gclk",
726 static struct omap_hwmod am33xx_epwmss1_hwmod
= {
728 .class = &am33xx_epwmss_hwmod_class
,
729 .clkdm_name
= "l4ls_clkdm",
730 .main_clk
= "l4ls_gclk",
733 .clkctrl_offs
= AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET
,
734 .modulemode
= MODULEMODE_SWCTRL
,
740 static struct omap_hwmod am33xx_ecap1_hwmod
= {
742 .class = &am33xx_ecap_hwmod_class
,
743 .clkdm_name
= "l4ls_clkdm",
744 .main_clk
= "l4ls_gclk",
748 static struct omap_hwmod am33xx_eqep1_hwmod
= {
750 .class = &am33xx_eqep_hwmod_class
,
751 .clkdm_name
= "l4ls_clkdm",
752 .main_clk
= "l4ls_gclk",
756 static struct omap_hwmod am33xx_ehrpwm1_hwmod
= {
758 .class = &am33xx_ehrpwm_hwmod_class
,
759 .clkdm_name
= "l4ls_clkdm",
760 .main_clk
= "l4ls_gclk",
764 static struct omap_hwmod am33xx_epwmss2_hwmod
= {
766 .class = &am33xx_epwmss_hwmod_class
,
767 .clkdm_name
= "l4ls_clkdm",
768 .main_clk
= "l4ls_gclk",
771 .clkctrl_offs
= AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET
,
772 .modulemode
= MODULEMODE_SWCTRL
,
778 static struct omap_hwmod am33xx_ecap2_hwmod
= {
780 .class = &am33xx_ecap_hwmod_class
,
781 .clkdm_name
= "l4ls_clkdm",
782 .main_clk
= "l4ls_gclk",
786 static struct omap_hwmod am33xx_eqep2_hwmod
= {
788 .class = &am33xx_eqep_hwmod_class
,
789 .clkdm_name
= "l4ls_clkdm",
790 .main_clk
= "l4ls_gclk",
794 static struct omap_hwmod am33xx_ehrpwm2_hwmod
= {
796 .class = &am33xx_ehrpwm_hwmod_class
,
797 .clkdm_name
= "l4ls_clkdm",
798 .main_clk
= "l4ls_gclk",
802 * 'gpio' class: for gpio 0,1,2,3
804 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc
= {
808 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
809 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
810 SYSS_HAS_RESET_STATUS
),
811 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
813 .sysc_fields
= &omap_hwmod_sysc_type1
,
816 static struct omap_hwmod_class am33xx_gpio_hwmod_class
= {
818 .sysc
= &am33xx_gpio_sysc
,
822 static struct omap_gpio_dev_attr gpio_dev_attr
= {
828 static struct omap_hwmod_opt_clk gpio0_opt_clks
[] = {
829 { .role
= "dbclk", .clk
= "gpio0_dbclk" },
832 static struct omap_hwmod am33xx_gpio0_hwmod
= {
834 .class = &am33xx_gpio_hwmod_class
,
835 .clkdm_name
= "l4_wkup_clkdm",
836 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
837 .main_clk
= "dpll_core_m4_div2_ck",
840 .clkctrl_offs
= AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET
,
841 .modulemode
= MODULEMODE_SWCTRL
,
844 .opt_clks
= gpio0_opt_clks
,
845 .opt_clks_cnt
= ARRAY_SIZE(gpio0_opt_clks
),
846 .dev_attr
= &gpio_dev_attr
,
850 static struct omap_hwmod_opt_clk gpio1_opt_clks
[] = {
851 { .role
= "dbclk", .clk
= "gpio1_dbclk" },
854 static struct omap_hwmod am33xx_gpio1_hwmod
= {
856 .class = &am33xx_gpio_hwmod_class
,
857 .clkdm_name
= "l4ls_clkdm",
858 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
859 .main_clk
= "l4ls_gclk",
862 .clkctrl_offs
= AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET
,
863 .modulemode
= MODULEMODE_SWCTRL
,
866 .opt_clks
= gpio1_opt_clks
,
867 .opt_clks_cnt
= ARRAY_SIZE(gpio1_opt_clks
),
868 .dev_attr
= &gpio_dev_attr
,
872 static struct omap_hwmod_opt_clk gpio2_opt_clks
[] = {
873 { .role
= "dbclk", .clk
= "gpio2_dbclk" },
876 static struct omap_hwmod am33xx_gpio2_hwmod
= {
878 .class = &am33xx_gpio_hwmod_class
,
879 .clkdm_name
= "l4ls_clkdm",
880 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
881 .main_clk
= "l4ls_gclk",
884 .clkctrl_offs
= AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET
,
885 .modulemode
= MODULEMODE_SWCTRL
,
888 .opt_clks
= gpio2_opt_clks
,
889 .opt_clks_cnt
= ARRAY_SIZE(gpio2_opt_clks
),
890 .dev_attr
= &gpio_dev_attr
,
894 static struct omap_hwmod_opt_clk gpio3_opt_clks
[] = {
895 { .role
= "dbclk", .clk
= "gpio3_dbclk" },
898 static struct omap_hwmod am33xx_gpio3_hwmod
= {
900 .class = &am33xx_gpio_hwmod_class
,
901 .clkdm_name
= "l4ls_clkdm",
902 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
903 .main_clk
= "l4ls_gclk",
906 .clkctrl_offs
= AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET
,
907 .modulemode
= MODULEMODE_SWCTRL
,
910 .opt_clks
= gpio3_opt_clks
,
911 .opt_clks_cnt
= ARRAY_SIZE(gpio3_opt_clks
),
912 .dev_attr
= &gpio_dev_attr
,
916 static struct omap_hwmod_class_sysconfig gpmc_sysc
= {
920 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SIDLEMODE
|
921 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
922 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
923 .sysc_fields
= &omap_hwmod_sysc_type1
,
926 static struct omap_hwmod_class am33xx_gpmc_hwmod_class
= {
931 static struct omap_hwmod am33xx_gpmc_hwmod
= {
933 .class = &am33xx_gpmc_hwmod_class
,
934 .clkdm_name
= "l3s_clkdm",
935 .flags
= (HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
),
936 .main_clk
= "l3s_gclk",
939 .clkctrl_offs
= AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET
,
940 .modulemode
= MODULEMODE_SWCTRL
,
946 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc
= {
949 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
950 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
951 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
952 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
954 .sysc_fields
= &omap_hwmod_sysc_type1
,
957 static struct omap_hwmod_class i2c_class
= {
959 .sysc
= &am33xx_i2c_sysc
,
960 .rev
= OMAP_I2C_IP_VERSION_2
,
961 .reset
= &omap_i2c_reset
,
964 static struct omap_i2c_dev_attr i2c_dev_attr
= {
965 .flags
= OMAP_I2C_FLAG_BUS_SHIFT_NONE
,
969 static struct omap_hwmod am33xx_i2c1_hwmod
= {
972 .clkdm_name
= "l4_wkup_clkdm",
973 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
974 .main_clk
= "dpll_per_m2_div4_wkupdm_ck",
977 .clkctrl_offs
= AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET
,
978 .modulemode
= MODULEMODE_SWCTRL
,
981 .dev_attr
= &i2c_dev_attr
,
985 static struct omap_hwmod am33xx_i2c2_hwmod
= {
988 .clkdm_name
= "l4ls_clkdm",
989 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
990 .main_clk
= "dpll_per_m2_div4_ck",
993 .clkctrl_offs
= AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET
,
994 .modulemode
= MODULEMODE_SWCTRL
,
997 .dev_attr
= &i2c_dev_attr
,
1001 static struct omap_hwmod am33xx_i2c3_hwmod
= {
1003 .class = &i2c_class
,
1004 .clkdm_name
= "l4ls_clkdm",
1005 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1006 .main_clk
= "dpll_per_m2_div4_ck",
1009 .clkctrl_offs
= AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET
,
1010 .modulemode
= MODULEMODE_SWCTRL
,
1013 .dev_attr
= &i2c_dev_attr
,
1018 static struct omap_hwmod_class_sysconfig lcdc_sysc
= {
1021 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_MIDLEMODE
),
1022 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1023 .sysc_fields
= &omap_hwmod_sysc_type2
,
1026 static struct omap_hwmod_class am33xx_lcdc_hwmod_class
= {
1031 static struct omap_hwmod am33xx_lcdc_hwmod
= {
1033 .class = &am33xx_lcdc_hwmod_class
,
1034 .clkdm_name
= "lcdc_clkdm",
1035 .flags
= HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
,
1036 .main_clk
= "lcd_gclk",
1039 .clkctrl_offs
= AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET
,
1040 .modulemode
= MODULEMODE_SWCTRL
,
1047 * mailbox module allowing communication between the on-chip processors using a
1048 * queued mailbox-interrupt mechanism.
1050 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc
= {
1052 .sysc_offs
= 0x0010,
1053 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
1054 SYSC_HAS_SOFTRESET
),
1055 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1056 .sysc_fields
= &omap_hwmod_sysc_type2
,
1059 static struct omap_hwmod_class am33xx_mailbox_hwmod_class
= {
1061 .sysc
= &am33xx_mailbox_sysc
,
1064 static struct omap_hwmod am33xx_mailbox_hwmod
= {
1066 .class = &am33xx_mailbox_hwmod_class
,
1067 .clkdm_name
= "l4ls_clkdm",
1068 .main_clk
= "l4ls_gclk",
1071 .clkctrl_offs
= AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET
,
1072 .modulemode
= MODULEMODE_SWCTRL
,
1080 static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc
= {
1083 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
1084 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1085 .sysc_fields
= &omap_hwmod_sysc_type3
,
1088 static struct omap_hwmod_class am33xx_mcasp_hwmod_class
= {
1090 .sysc
= &am33xx_mcasp_sysc
,
1094 static struct omap_hwmod am33xx_mcasp0_hwmod
= {
1096 .class = &am33xx_mcasp_hwmod_class
,
1097 .clkdm_name
= "l3s_clkdm",
1098 .main_clk
= "mcasp0_fck",
1101 .clkctrl_offs
= AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET
,
1102 .modulemode
= MODULEMODE_SWCTRL
,
1108 static struct omap_hwmod am33xx_mcasp1_hwmod
= {
1110 .class = &am33xx_mcasp_hwmod_class
,
1111 .clkdm_name
= "l3s_clkdm",
1112 .main_clk
= "mcasp1_fck",
1115 .clkctrl_offs
= AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET
,
1116 .modulemode
= MODULEMODE_SWCTRL
,
1122 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc
= {
1126 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
1127 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
1128 SYSC_HAS_AUTOIDLE
| SYSS_HAS_RESET_STATUS
),
1129 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1130 .sysc_fields
= &omap_hwmod_sysc_type1
,
1133 static struct omap_hwmod_class am33xx_mmc_hwmod_class
= {
1135 .sysc
= &am33xx_mmc_sysc
,
1139 static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr
= {
1140 .flags
= OMAP_HSMMC_SUPPORTS_DUAL_VOLT
,
1143 static struct omap_hwmod am33xx_mmc0_hwmod
= {
1145 .class = &am33xx_mmc_hwmod_class
,
1146 .clkdm_name
= "l4ls_clkdm",
1147 .main_clk
= "mmc_clk",
1150 .clkctrl_offs
= AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET
,
1151 .modulemode
= MODULEMODE_SWCTRL
,
1154 .dev_attr
= &am33xx_mmc0_dev_attr
,
1158 static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr
= {
1159 .flags
= OMAP_HSMMC_SUPPORTS_DUAL_VOLT
,
1162 static struct omap_hwmod am33xx_mmc1_hwmod
= {
1164 .class = &am33xx_mmc_hwmod_class
,
1165 .clkdm_name
= "l4ls_clkdm",
1166 .main_clk
= "mmc_clk",
1169 .clkctrl_offs
= AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET
,
1170 .modulemode
= MODULEMODE_SWCTRL
,
1173 .dev_attr
= &am33xx_mmc1_dev_attr
,
1177 static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr
= {
1178 .flags
= OMAP_HSMMC_SUPPORTS_DUAL_VOLT
,
1180 static struct omap_hwmod am33xx_mmc2_hwmod
= {
1182 .class = &am33xx_mmc_hwmod_class
,
1183 .clkdm_name
= "l3s_clkdm",
1184 .main_clk
= "mmc_clk",
1187 .clkctrl_offs
= AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET
,
1188 .modulemode
= MODULEMODE_SWCTRL
,
1191 .dev_attr
= &am33xx_mmc2_dev_attr
,
1198 static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc
= {
1200 .sysc_offs
= 0x0078,
1201 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
1202 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
|
1203 SIDLE_SMART
| SIDLE_SMART_WKUP
),
1204 .sysc_fields
= &omap_hwmod_sysc_type3
,
1207 static struct omap_hwmod_class am33xx_rtc_hwmod_class
= {
1209 .sysc
= &am33xx_rtc_sysc
,
1212 static struct omap_hwmod am33xx_rtc_hwmod
= {
1214 .class = &am33xx_rtc_hwmod_class
,
1215 .clkdm_name
= "l4_rtc_clkdm",
1216 .main_clk
= "clk_32768_ck",
1219 .clkctrl_offs
= AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET
,
1220 .modulemode
= MODULEMODE_SWCTRL
,
1226 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc
= {
1228 .sysc_offs
= 0x0110,
1229 .syss_offs
= 0x0114,
1230 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
1231 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
|
1232 SYSS_HAS_RESET_STATUS
),
1233 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1234 .sysc_fields
= &omap_hwmod_sysc_type1
,
1237 static struct omap_hwmod_class am33xx_spi_hwmod_class
= {
1239 .sysc
= &am33xx_mcspi_sysc
,
1240 .rev
= OMAP4_MCSPI_REV
,
1244 static struct omap2_mcspi_dev_attr mcspi_attrib
= {
1245 .num_chipselect
= 2,
1247 static struct omap_hwmod am33xx_spi0_hwmod
= {
1249 .class = &am33xx_spi_hwmod_class
,
1250 .clkdm_name
= "l4ls_clkdm",
1251 .main_clk
= "dpll_per_m2_div4_ck",
1254 .clkctrl_offs
= AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET
,
1255 .modulemode
= MODULEMODE_SWCTRL
,
1258 .dev_attr
= &mcspi_attrib
,
1262 static struct omap_hwmod am33xx_spi1_hwmod
= {
1264 .class = &am33xx_spi_hwmod_class
,
1265 .clkdm_name
= "l4ls_clkdm",
1266 .main_clk
= "dpll_per_m2_div4_ck",
1269 .clkctrl_offs
= AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET
,
1270 .modulemode
= MODULEMODE_SWCTRL
,
1273 .dev_attr
= &mcspi_attrib
,
1278 * spinlock provides hardware assistance for synchronizing the
1279 * processes running on multiple processors
1282 static struct omap_hwmod_class_sysconfig am33xx_spinlock_sysc
= {
1284 .sysc_offs
= 0x0010,
1285 .syss_offs
= 0x0014,
1286 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
1287 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
1288 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1289 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1290 .sysc_fields
= &omap_hwmod_sysc_type1
,
1293 static struct omap_hwmod_class am33xx_spinlock_hwmod_class
= {
1295 .sysc
= &am33xx_spinlock_sysc
,
1298 static struct omap_hwmod am33xx_spinlock_hwmod
= {
1300 .class = &am33xx_spinlock_hwmod_class
,
1301 .clkdm_name
= "l4ls_clkdm",
1302 .main_clk
= "l4ls_gclk",
1305 .clkctrl_offs
= AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET
,
1306 .modulemode
= MODULEMODE_SWCTRL
,
1311 /* 'timer 2-7' class */
1312 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc
= {
1314 .sysc_offs
= 0x0010,
1315 .syss_offs
= 0x0014,
1316 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1317 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1319 .sysc_fields
= &omap_hwmod_sysc_type2
,
1322 static struct omap_hwmod_class am33xx_timer_hwmod_class
= {
1324 .sysc
= &am33xx_timer_sysc
,
1328 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc
= {
1330 .sysc_offs
= 0x0010,
1331 .syss_offs
= 0x0014,
1332 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
1333 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
|
1334 SYSS_HAS_RESET_STATUS
),
1335 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1336 .sysc_fields
= &omap_hwmod_sysc_type1
,
1339 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class
= {
1341 .sysc
= &am33xx_timer1ms_sysc
,
1344 static struct omap_hwmod am33xx_timer1_hwmod
= {
1346 .class = &am33xx_timer1ms_hwmod_class
,
1347 .clkdm_name
= "l4_wkup_clkdm",
1348 .main_clk
= "timer1_fck",
1351 .clkctrl_offs
= AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET
,
1352 .modulemode
= MODULEMODE_SWCTRL
,
1357 static struct omap_hwmod am33xx_timer2_hwmod
= {
1359 .class = &am33xx_timer_hwmod_class
,
1360 .clkdm_name
= "l4ls_clkdm",
1361 .main_clk
= "timer2_fck",
1364 .clkctrl_offs
= AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET
,
1365 .modulemode
= MODULEMODE_SWCTRL
,
1370 static struct omap_hwmod am33xx_timer3_hwmod
= {
1372 .class = &am33xx_timer_hwmod_class
,
1373 .clkdm_name
= "l4ls_clkdm",
1374 .main_clk
= "timer3_fck",
1377 .clkctrl_offs
= AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET
,
1378 .modulemode
= MODULEMODE_SWCTRL
,
1383 static struct omap_hwmod am33xx_timer4_hwmod
= {
1385 .class = &am33xx_timer_hwmod_class
,
1386 .clkdm_name
= "l4ls_clkdm",
1387 .main_clk
= "timer4_fck",
1390 .clkctrl_offs
= AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET
,
1391 .modulemode
= MODULEMODE_SWCTRL
,
1396 static struct omap_hwmod am33xx_timer5_hwmod
= {
1398 .class = &am33xx_timer_hwmod_class
,
1399 .clkdm_name
= "l4ls_clkdm",
1400 .main_clk
= "timer5_fck",
1403 .clkctrl_offs
= AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET
,
1404 .modulemode
= MODULEMODE_SWCTRL
,
1409 static struct omap_hwmod am33xx_timer6_hwmod
= {
1411 .class = &am33xx_timer_hwmod_class
,
1412 .clkdm_name
= "l4ls_clkdm",
1413 .main_clk
= "timer6_fck",
1416 .clkctrl_offs
= AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET
,
1417 .modulemode
= MODULEMODE_SWCTRL
,
1422 static struct omap_hwmod am33xx_timer7_hwmod
= {
1424 .class = &am33xx_timer_hwmod_class
,
1425 .clkdm_name
= "l4ls_clkdm",
1426 .main_clk
= "timer7_fck",
1429 .clkctrl_offs
= AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET
,
1430 .modulemode
= MODULEMODE_SWCTRL
,
1436 static struct omap_hwmod_class am33xx_tpcc_hwmod_class
= {
1440 static struct omap_hwmod am33xx_tpcc_hwmod
= {
1442 .class = &am33xx_tpcc_hwmod_class
,
1443 .clkdm_name
= "l3_clkdm",
1444 .main_clk
= "l3_gclk",
1447 .clkctrl_offs
= AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET
,
1448 .modulemode
= MODULEMODE_SWCTRL
,
1453 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc
= {
1456 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
1457 SYSC_HAS_MIDLEMODE
),
1458 .idlemodes
= (SIDLE_FORCE
| SIDLE_SMART
| MSTANDBY_FORCE
),
1459 .sysc_fields
= &omap_hwmod_sysc_type2
,
1463 static struct omap_hwmod_class am33xx_tptc_hwmod_class
= {
1465 .sysc
= &am33xx_tptc_sysc
,
1469 static struct omap_hwmod am33xx_tptc0_hwmod
= {
1471 .class = &am33xx_tptc_hwmod_class
,
1472 .clkdm_name
= "l3_clkdm",
1473 .flags
= HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
,
1474 .main_clk
= "l3_gclk",
1477 .clkctrl_offs
= AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET
,
1478 .modulemode
= MODULEMODE_SWCTRL
,
1484 static struct omap_hwmod am33xx_tptc1_hwmod
= {
1486 .class = &am33xx_tptc_hwmod_class
,
1487 .clkdm_name
= "l3_clkdm",
1488 .flags
= (HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
),
1489 .main_clk
= "l3_gclk",
1492 .clkctrl_offs
= AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET
,
1493 .modulemode
= MODULEMODE_SWCTRL
,
1499 static struct omap_hwmod am33xx_tptc2_hwmod
= {
1501 .class = &am33xx_tptc_hwmod_class
,
1502 .clkdm_name
= "l3_clkdm",
1503 .flags
= (HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
),
1504 .main_clk
= "l3_gclk",
1507 .clkctrl_offs
= AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET
,
1508 .modulemode
= MODULEMODE_SWCTRL
,
1514 static struct omap_hwmod_class_sysconfig uart_sysc
= {
1518 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_ENAWAKEUP
|
1519 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
),
1520 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1522 .sysc_fields
= &omap_hwmod_sysc_type1
,
1525 static struct omap_hwmod_class uart_class
= {
1531 static struct omap_hwmod am33xx_uart1_hwmod
= {
1533 .class = &uart_class
,
1534 .clkdm_name
= "l4_wkup_clkdm",
1535 .flags
= DEBUG_AM33XXUART1_FLAGS
| HWMOD_SWSUP_SIDLE_ACT
,
1536 .main_clk
= "dpll_per_m2_div4_wkupdm_ck",
1539 .clkctrl_offs
= AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET
,
1540 .modulemode
= MODULEMODE_SWCTRL
,
1545 static struct omap_hwmod am33xx_uart2_hwmod
= {
1547 .class = &uart_class
,
1548 .clkdm_name
= "l4ls_clkdm",
1549 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
1550 .main_clk
= "dpll_per_m2_div4_ck",
1553 .clkctrl_offs
= AM33XX_CM_PER_UART1_CLKCTRL_OFFSET
,
1554 .modulemode
= MODULEMODE_SWCTRL
,
1560 static struct omap_hwmod am33xx_uart3_hwmod
= {
1562 .class = &uart_class
,
1563 .clkdm_name
= "l4ls_clkdm",
1564 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
1565 .main_clk
= "dpll_per_m2_div4_ck",
1568 .clkctrl_offs
= AM33XX_CM_PER_UART2_CLKCTRL_OFFSET
,
1569 .modulemode
= MODULEMODE_SWCTRL
,
1574 static struct omap_hwmod am33xx_uart4_hwmod
= {
1576 .class = &uart_class
,
1577 .clkdm_name
= "l4ls_clkdm",
1578 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
1579 .main_clk
= "dpll_per_m2_div4_ck",
1582 .clkctrl_offs
= AM33XX_CM_PER_UART3_CLKCTRL_OFFSET
,
1583 .modulemode
= MODULEMODE_SWCTRL
,
1588 static struct omap_hwmod am33xx_uart5_hwmod
= {
1590 .class = &uart_class
,
1591 .clkdm_name
= "l4ls_clkdm",
1592 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
1593 .main_clk
= "dpll_per_m2_div4_ck",
1596 .clkctrl_offs
= AM33XX_CM_PER_UART4_CLKCTRL_OFFSET
,
1597 .modulemode
= MODULEMODE_SWCTRL
,
1602 static struct omap_hwmod am33xx_uart6_hwmod
= {
1604 .class = &uart_class
,
1605 .clkdm_name
= "l4ls_clkdm",
1606 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
1607 .main_clk
= "dpll_per_m2_div4_ck",
1610 .clkctrl_offs
= AM33XX_CM_PER_UART5_CLKCTRL_OFFSET
,
1611 .modulemode
= MODULEMODE_SWCTRL
,
1616 /* 'wd_timer' class */
1617 static struct omap_hwmod_class_sysconfig wdt_sysc
= {
1621 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_SIDLEMODE
|
1622 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1623 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1625 .sysc_fields
= &omap_hwmod_sysc_type1
,
1628 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class
= {
1631 .pre_shutdown
= &omap2_wd_timer_disable
,
1635 * XXX: device.c file uses hardcoded name for watchdog timer
1636 * driver "wd_timer2, so we are also using same name as of now...
1638 static struct omap_hwmod am33xx_wd_timer1_hwmod
= {
1639 .name
= "wd_timer2",
1640 .class = &am33xx_wd_timer_hwmod_class
,
1641 .clkdm_name
= "l4_wkup_clkdm",
1642 .flags
= HWMOD_SWSUP_SIDLE
,
1643 .main_clk
= "wdt1_fck",
1646 .clkctrl_offs
= AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET
,
1647 .modulemode
= MODULEMODE_SWCTRL
,
1654 * high-speed on-the-go universal serial bus (usb_otg) controller
1656 static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc
= {
1659 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_MIDLEMODE
),
1660 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1661 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
1662 .sysc_fields
= &omap_hwmod_sysc_type2
,
1665 static struct omap_hwmod_class am33xx_usbotg_class
= {
1667 .sysc
= &am33xx_usbhsotg_sysc
,
1670 static struct omap_hwmod am33xx_usbss_hwmod
= {
1671 .name
= "usb_otg_hs",
1672 .class = &am33xx_usbotg_class
,
1673 .clkdm_name
= "l3s_clkdm",
1674 .flags
= HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
,
1675 .main_clk
= "usbotg_fck",
1678 .clkctrl_offs
= AM33XX_CM_PER_USB0_CLKCTRL_OFFSET
,
1679 .modulemode
= MODULEMODE_SWCTRL
,
1689 static struct omap_hwmod_addr_space am33xx_emif_addrs
[] = {
1691 .pa_start
= 0x4c000000,
1692 .pa_end
= 0x4c000fff,
1693 .flags
= ADDR_TYPE_RT
1697 /* l3 main -> emif */
1698 static struct omap_hwmod_ocp_if am33xx_l3_main__emif
= {
1699 .master
= &am33xx_l3_main_hwmod
,
1700 .slave
= &am33xx_emif_hwmod
,
1701 .clk
= "dpll_core_m4_ck",
1702 .addr
= am33xx_emif_addrs
,
1703 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1706 /* mpu -> l3 main */
1707 static struct omap_hwmod_ocp_if am33xx_mpu__l3_main
= {
1708 .master
= &am33xx_mpu_hwmod
,
1709 .slave
= &am33xx_l3_main_hwmod
,
1710 .clk
= "dpll_mpu_m2_ck",
1711 .user
= OCP_USER_MPU
,
1714 /* l3 main -> l4 hs */
1715 static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs
= {
1716 .master
= &am33xx_l3_main_hwmod
,
1717 .slave
= &am33xx_l4_hs_hwmod
,
1719 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1722 /* l3 main -> l3 s */
1723 static struct omap_hwmod_ocp_if am33xx_l3_main__l3_s
= {
1724 .master
= &am33xx_l3_main_hwmod
,
1725 .slave
= &am33xx_l3_s_hwmod
,
1727 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1730 /* l3 s -> l4 per/ls */
1731 static struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls
= {
1732 .master
= &am33xx_l3_s_hwmod
,
1733 .slave
= &am33xx_l4_ls_hwmod
,
1735 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1738 /* l3 s -> l4 wkup */
1739 static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup
= {
1740 .master
= &am33xx_l3_s_hwmod
,
1741 .slave
= &am33xx_l4_wkup_hwmod
,
1743 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1746 /* l3 main -> l3 instr */
1747 static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr
= {
1748 .master
= &am33xx_l3_main_hwmod
,
1749 .slave
= &am33xx_l3_instr_hwmod
,
1751 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1755 static struct omap_hwmod_ocp_if am33xx_mpu__prcm
= {
1756 .master
= &am33xx_mpu_hwmod
,
1757 .slave
= &am33xx_prcm_hwmod
,
1758 .clk
= "dpll_mpu_m2_ck",
1759 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1762 /* l3 s -> l3 main*/
1763 static struct omap_hwmod_ocp_if am33xx_l3_s__l3_main
= {
1764 .master
= &am33xx_l3_s_hwmod
,
1765 .slave
= &am33xx_l3_main_hwmod
,
1767 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1770 /* pru-icss -> l3 main */
1771 static struct omap_hwmod_ocp_if am33xx_pruss__l3_main
= {
1772 .master
= &am33xx_pruss_hwmod
,
1773 .slave
= &am33xx_l3_main_hwmod
,
1775 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1778 /* wkup m3 -> l4 wkup */
1779 static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup
= {
1780 .master
= &am33xx_wkup_m3_hwmod
,
1781 .slave
= &am33xx_l4_wkup_hwmod
,
1782 .clk
= "dpll_core_m4_div2_ck",
1783 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1786 /* gfx -> l3 main */
1787 static struct omap_hwmod_ocp_if am33xx_gfx__l3_main
= {
1788 .master
= &am33xx_gfx_hwmod
,
1789 .slave
= &am33xx_l3_main_hwmod
,
1790 .clk
= "dpll_core_m4_ck",
1791 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1794 /* l4 wkup -> wkup m3 */
1795 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3
= {
1796 .master
= &am33xx_l4_wkup_hwmod
,
1797 .slave
= &am33xx_wkup_m3_hwmod
,
1798 .clk
= "dpll_core_m4_div2_ck",
1799 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1802 /* l4 hs -> pru-icss */
1803 static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss
= {
1804 .master
= &am33xx_l4_hs_hwmod
,
1805 .slave
= &am33xx_pruss_hwmod
,
1806 .clk
= "dpll_core_m4_ck",
1807 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1810 /* l3 main -> gfx */
1811 static struct omap_hwmod_ocp_if am33xx_l3_main__gfx
= {
1812 .master
= &am33xx_l3_main_hwmod
,
1813 .slave
= &am33xx_gfx_hwmod
,
1814 .clk
= "dpll_core_m4_ck",
1815 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1818 /* l3_main -> debugss */
1819 static struct omap_hwmod_addr_space am33xx_debugss_addrs
[] = {
1821 .pa_start
= 0x4b000000,
1822 .pa_end
= 0x4b000000 + SZ_16M
- 1,
1823 .flags
= ADDR_TYPE_RT
1828 static struct omap_hwmod_ocp_if am33xx_l3_main__debugss
= {
1829 .master
= &am33xx_l3_main_hwmod
,
1830 .slave
= &am33xx_debugss_hwmod
,
1831 .clk
= "dpll_core_m4_ck",
1832 .addr
= am33xx_debugss_addrs
,
1833 .user
= OCP_USER_MPU
,
1836 /* l4 wkup -> smartreflex0 */
1837 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0
= {
1838 .master
= &am33xx_l4_wkup_hwmod
,
1839 .slave
= &am33xx_smartreflex0_hwmod
,
1840 .clk
= "dpll_core_m4_div2_ck",
1841 .user
= OCP_USER_MPU
,
1844 /* l4 wkup -> smartreflex1 */
1845 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1
= {
1846 .master
= &am33xx_l4_wkup_hwmod
,
1847 .slave
= &am33xx_smartreflex1_hwmod
,
1848 .clk
= "dpll_core_m4_div2_ck",
1849 .user
= OCP_USER_MPU
,
1852 /* l4 wkup -> control */
1853 static struct omap_hwmod_ocp_if am33xx_l4_wkup__control
= {
1854 .master
= &am33xx_l4_wkup_hwmod
,
1855 .slave
= &am33xx_control_hwmod
,
1856 .clk
= "dpll_core_m4_div2_ck",
1857 .user
= OCP_USER_MPU
,
1860 /* l4 wkup -> rtc */
1861 static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc
= {
1862 .master
= &am33xx_l4_wkup_hwmod
,
1863 .slave
= &am33xx_rtc_hwmod
,
1864 .clk
= "clkdiv32k_ick",
1865 .user
= OCP_USER_MPU
,
1868 /* l4 per/ls -> DCAN0 */
1869 static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0
= {
1870 .master
= &am33xx_l4_ls_hwmod
,
1871 .slave
= &am33xx_dcan0_hwmod
,
1873 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1876 /* l4 per/ls -> DCAN1 */
1877 static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1
= {
1878 .master
= &am33xx_l4_ls_hwmod
,
1879 .slave
= &am33xx_dcan1_hwmod
,
1881 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1884 /* l4 per/ls -> GPIO2 */
1885 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1
= {
1886 .master
= &am33xx_l4_ls_hwmod
,
1887 .slave
= &am33xx_gpio1_hwmod
,
1889 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1892 /* l4 per/ls -> gpio3 */
1893 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2
= {
1894 .master
= &am33xx_l4_ls_hwmod
,
1895 .slave
= &am33xx_gpio2_hwmod
,
1897 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1900 /* l4 per/ls -> gpio4 */
1901 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3
= {
1902 .master
= &am33xx_l4_ls_hwmod
,
1903 .slave
= &am33xx_gpio3_hwmod
,
1905 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1908 /* L4 WKUP -> I2C1 */
1909 static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1
= {
1910 .master
= &am33xx_l4_wkup_hwmod
,
1911 .slave
= &am33xx_i2c1_hwmod
,
1912 .clk
= "dpll_core_m4_div2_ck",
1913 .user
= OCP_USER_MPU
,
1916 /* L4 WKUP -> GPIO1 */
1917 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0
= {
1918 .master
= &am33xx_l4_wkup_hwmod
,
1919 .slave
= &am33xx_gpio0_hwmod
,
1920 .clk
= "dpll_core_m4_div2_ck",
1921 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1924 /* L4 WKUP -> ADC_TSC */
1925 static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs
[] = {
1927 .pa_start
= 0x44E0D000,
1928 .pa_end
= 0x44E0D000 + SZ_8K
- 1,
1929 .flags
= ADDR_TYPE_RT
1934 static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc
= {
1935 .master
= &am33xx_l4_wkup_hwmod
,
1936 .slave
= &am33xx_adc_tsc_hwmod
,
1937 .clk
= "dpll_core_m4_div2_ck",
1938 .addr
= am33xx_adc_tsc_addrs
,
1939 .user
= OCP_USER_MPU
,
1942 static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0
= {
1943 .master
= &am33xx_l4_hs_hwmod
,
1944 .slave
= &am33xx_cpgmac0_hwmod
,
1945 .clk
= "cpsw_125mhz_gclk",
1946 .user
= OCP_USER_MPU
,
1949 static struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio
= {
1950 .master
= &am33xx_cpgmac0_hwmod
,
1951 .slave
= &am33xx_mdio_hwmod
,
1952 .user
= OCP_USER_MPU
,
1955 static struct omap_hwmod_addr_space am33xx_elm_addr_space
[] = {
1957 .pa_start
= 0x48080000,
1958 .pa_end
= 0x48080000 + SZ_8K
- 1,
1959 .flags
= ADDR_TYPE_RT
1964 static struct omap_hwmod_ocp_if am33xx_l4_ls__elm
= {
1965 .master
= &am33xx_l4_ls_hwmod
,
1966 .slave
= &am33xx_elm_hwmod
,
1968 .addr
= am33xx_elm_addr_space
,
1969 .user
= OCP_USER_MPU
,
1972 static struct omap_hwmod_addr_space am33xx_epwmss0_addr_space
[] = {
1974 .pa_start
= 0x48300000,
1975 .pa_end
= 0x48300000 + SZ_16
- 1,
1976 .flags
= ADDR_TYPE_RT
1981 static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0
= {
1982 .master
= &am33xx_l4_ls_hwmod
,
1983 .slave
= &am33xx_epwmss0_hwmod
,
1985 .addr
= am33xx_epwmss0_addr_space
,
1986 .user
= OCP_USER_MPU
,
1989 static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0
= {
1990 .master
= &am33xx_epwmss0_hwmod
,
1991 .slave
= &am33xx_ecap0_hwmod
,
1993 .user
= OCP_USER_MPU
,
1996 static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0
= {
1997 .master
= &am33xx_epwmss0_hwmod
,
1998 .slave
= &am33xx_eqep0_hwmod
,
2000 .user
= OCP_USER_MPU
,
2003 static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0
= {
2004 .master
= &am33xx_epwmss0_hwmod
,
2005 .slave
= &am33xx_ehrpwm0_hwmod
,
2007 .user
= OCP_USER_MPU
,
2011 static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space
[] = {
2013 .pa_start
= 0x48302000,
2014 .pa_end
= 0x48302000 + SZ_16
- 1,
2015 .flags
= ADDR_TYPE_RT
2020 static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1
= {
2021 .master
= &am33xx_l4_ls_hwmod
,
2022 .slave
= &am33xx_epwmss1_hwmod
,
2024 .addr
= am33xx_epwmss1_addr_space
,
2025 .user
= OCP_USER_MPU
,
2028 static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1
= {
2029 .master
= &am33xx_epwmss1_hwmod
,
2030 .slave
= &am33xx_ecap1_hwmod
,
2032 .user
= OCP_USER_MPU
,
2035 static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1
= {
2036 .master
= &am33xx_epwmss1_hwmod
,
2037 .slave
= &am33xx_eqep1_hwmod
,
2039 .user
= OCP_USER_MPU
,
2042 static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1
= {
2043 .master
= &am33xx_epwmss1_hwmod
,
2044 .slave
= &am33xx_ehrpwm1_hwmod
,
2046 .user
= OCP_USER_MPU
,
2049 static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space
[] = {
2051 .pa_start
= 0x48304000,
2052 .pa_end
= 0x48304000 + SZ_16
- 1,
2053 .flags
= ADDR_TYPE_RT
2058 static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2
= {
2059 .master
= &am33xx_l4_ls_hwmod
,
2060 .slave
= &am33xx_epwmss2_hwmod
,
2062 .addr
= am33xx_epwmss2_addr_space
,
2063 .user
= OCP_USER_MPU
,
2066 static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2
= {
2067 .master
= &am33xx_epwmss2_hwmod
,
2068 .slave
= &am33xx_ecap2_hwmod
,
2070 .user
= OCP_USER_MPU
,
2073 static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2
= {
2074 .master
= &am33xx_epwmss2_hwmod
,
2075 .slave
= &am33xx_eqep2_hwmod
,
2077 .user
= OCP_USER_MPU
,
2080 static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2
= {
2081 .master
= &am33xx_epwmss2_hwmod
,
2082 .slave
= &am33xx_ehrpwm2_hwmod
,
2084 .user
= OCP_USER_MPU
,
2087 /* l3s cfg -> gpmc */
2088 static struct omap_hwmod_addr_space am33xx_gpmc_addr_space
[] = {
2090 .pa_start
= 0x50000000,
2091 .pa_end
= 0x50000000 + SZ_8K
- 1,
2092 .flags
= ADDR_TYPE_RT
,
2097 static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc
= {
2098 .master
= &am33xx_l3_s_hwmod
,
2099 .slave
= &am33xx_gpmc_hwmod
,
2101 .addr
= am33xx_gpmc_addr_space
,
2102 .user
= OCP_USER_MPU
,
2106 static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2
= {
2107 .master
= &am33xx_l4_ls_hwmod
,
2108 .slave
= &am33xx_i2c2_hwmod
,
2110 .user
= OCP_USER_MPU
,
2113 static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3
= {
2114 .master
= &am33xx_l4_ls_hwmod
,
2115 .slave
= &am33xx_i2c3_hwmod
,
2117 .user
= OCP_USER_MPU
,
2120 static struct omap_hwmod_addr_space am33xx_lcdc_addr_space
[] = {
2122 .pa_start
= 0x4830E000,
2123 .pa_end
= 0x4830E000 + SZ_8K
- 1,
2124 .flags
= ADDR_TYPE_RT
,
2129 static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc
= {
2130 .master
= &am33xx_l3_main_hwmod
,
2131 .slave
= &am33xx_lcdc_hwmod
,
2132 .clk
= "dpll_core_m4_ck",
2133 .addr
= am33xx_lcdc_addr_space
,
2134 .user
= OCP_USER_MPU
,
2137 static struct omap_hwmod_addr_space am33xx_mailbox_addrs
[] = {
2139 .pa_start
= 0x480C8000,
2140 .pa_end
= 0x480C8000 + (SZ_4K
- 1),
2141 .flags
= ADDR_TYPE_RT
2146 /* l4 ls -> mailbox */
2147 static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox
= {
2148 .master
= &am33xx_l4_ls_hwmod
,
2149 .slave
= &am33xx_mailbox_hwmod
,
2151 .addr
= am33xx_mailbox_addrs
,
2152 .user
= OCP_USER_MPU
,
2155 /* l4 ls -> spinlock */
2156 static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock
= {
2157 .master
= &am33xx_l4_ls_hwmod
,
2158 .slave
= &am33xx_spinlock_hwmod
,
2160 .user
= OCP_USER_MPU
,
2163 /* l4 ls -> mcasp0 */
2164 static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space
[] = {
2166 .pa_start
= 0x48038000,
2167 .pa_end
= 0x48038000 + SZ_8K
- 1,
2168 .flags
= ADDR_TYPE_RT
2173 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0
= {
2174 .master
= &am33xx_l4_ls_hwmod
,
2175 .slave
= &am33xx_mcasp0_hwmod
,
2177 .addr
= am33xx_mcasp0_addr_space
,
2178 .user
= OCP_USER_MPU
,
2181 /* l4 ls -> mcasp1 */
2182 static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space
[] = {
2184 .pa_start
= 0x4803C000,
2185 .pa_end
= 0x4803C000 + SZ_8K
- 1,
2186 .flags
= ADDR_TYPE_RT
2191 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1
= {
2192 .master
= &am33xx_l4_ls_hwmod
,
2193 .slave
= &am33xx_mcasp1_hwmod
,
2195 .addr
= am33xx_mcasp1_addr_space
,
2196 .user
= OCP_USER_MPU
,
2200 static struct omap_hwmod_addr_space am33xx_mmc0_addr_space
[] = {
2202 .pa_start
= 0x48060100,
2203 .pa_end
= 0x48060100 + SZ_4K
- 1,
2204 .flags
= ADDR_TYPE_RT
,
2209 static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0
= {
2210 .master
= &am33xx_l4_ls_hwmod
,
2211 .slave
= &am33xx_mmc0_hwmod
,
2213 .addr
= am33xx_mmc0_addr_space
,
2214 .user
= OCP_USER_MPU
,
2218 static struct omap_hwmod_addr_space am33xx_mmc1_addr_space
[] = {
2220 .pa_start
= 0x481d8100,
2221 .pa_end
= 0x481d8100 + SZ_4K
- 1,
2222 .flags
= ADDR_TYPE_RT
,
2227 static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1
= {
2228 .master
= &am33xx_l4_ls_hwmod
,
2229 .slave
= &am33xx_mmc1_hwmod
,
2231 .addr
= am33xx_mmc1_addr_space
,
2232 .user
= OCP_USER_MPU
,
2236 static struct omap_hwmod_addr_space am33xx_mmc2_addr_space
[] = {
2238 .pa_start
= 0x47810100,
2239 .pa_end
= 0x47810100 + SZ_64K
- 1,
2240 .flags
= ADDR_TYPE_RT
,
2245 static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2
= {
2246 .master
= &am33xx_l3_s_hwmod
,
2247 .slave
= &am33xx_mmc2_hwmod
,
2249 .addr
= am33xx_mmc2_addr_space
,
2250 .user
= OCP_USER_MPU
,
2253 /* l4 ls -> mcspi0 */
2254 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0
= {
2255 .master
= &am33xx_l4_ls_hwmod
,
2256 .slave
= &am33xx_spi0_hwmod
,
2258 .user
= OCP_USER_MPU
,
2261 /* l4 ls -> mcspi1 */
2262 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1
= {
2263 .master
= &am33xx_l4_ls_hwmod
,
2264 .slave
= &am33xx_spi1_hwmod
,
2266 .user
= OCP_USER_MPU
,
2269 /* l4 wkup -> timer1 */
2270 static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1
= {
2271 .master
= &am33xx_l4_wkup_hwmod
,
2272 .slave
= &am33xx_timer1_hwmod
,
2273 .clk
= "dpll_core_m4_div2_ck",
2274 .user
= OCP_USER_MPU
,
2277 /* l4 per -> timer2 */
2278 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2
= {
2279 .master
= &am33xx_l4_ls_hwmod
,
2280 .slave
= &am33xx_timer2_hwmod
,
2282 .user
= OCP_USER_MPU
,
2285 /* l4 per -> timer3 */
2286 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3
= {
2287 .master
= &am33xx_l4_ls_hwmod
,
2288 .slave
= &am33xx_timer3_hwmod
,
2290 .user
= OCP_USER_MPU
,
2293 /* l4 per -> timer4 */
2294 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4
= {
2295 .master
= &am33xx_l4_ls_hwmod
,
2296 .slave
= &am33xx_timer4_hwmod
,
2298 .user
= OCP_USER_MPU
,
2301 /* l4 per -> timer5 */
2302 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5
= {
2303 .master
= &am33xx_l4_ls_hwmod
,
2304 .slave
= &am33xx_timer5_hwmod
,
2306 .user
= OCP_USER_MPU
,
2309 /* l4 per -> timer6 */
2310 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6
= {
2311 .master
= &am33xx_l4_ls_hwmod
,
2312 .slave
= &am33xx_timer6_hwmod
,
2314 .user
= OCP_USER_MPU
,
2317 /* l4 per -> timer7 */
2318 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7
= {
2319 .master
= &am33xx_l4_ls_hwmod
,
2320 .slave
= &am33xx_timer7_hwmod
,
2322 .user
= OCP_USER_MPU
,
2325 /* l3 main -> tpcc */
2326 static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc
= {
2327 .master
= &am33xx_l3_main_hwmod
,
2328 .slave
= &am33xx_tpcc_hwmod
,
2330 .user
= OCP_USER_MPU
,
2333 /* l3 main -> tpcc0 */
2334 static struct omap_hwmod_addr_space am33xx_tptc0_addr_space
[] = {
2336 .pa_start
= 0x49800000,
2337 .pa_end
= 0x49800000 + SZ_8K
- 1,
2338 .flags
= ADDR_TYPE_RT
,
2343 static struct omap_hwmod_ocp_if am33xx_l3_main__tptc0
= {
2344 .master
= &am33xx_l3_main_hwmod
,
2345 .slave
= &am33xx_tptc0_hwmod
,
2347 .addr
= am33xx_tptc0_addr_space
,
2348 .user
= OCP_USER_MPU
,
2351 /* l3 main -> tpcc1 */
2352 static struct omap_hwmod_addr_space am33xx_tptc1_addr_space
[] = {
2354 .pa_start
= 0x49900000,
2355 .pa_end
= 0x49900000 + SZ_8K
- 1,
2356 .flags
= ADDR_TYPE_RT
,
2361 static struct omap_hwmod_ocp_if am33xx_l3_main__tptc1
= {
2362 .master
= &am33xx_l3_main_hwmod
,
2363 .slave
= &am33xx_tptc1_hwmod
,
2365 .addr
= am33xx_tptc1_addr_space
,
2366 .user
= OCP_USER_MPU
,
2369 /* l3 main -> tpcc2 */
2370 static struct omap_hwmod_addr_space am33xx_tptc2_addr_space
[] = {
2372 .pa_start
= 0x49a00000,
2373 .pa_end
= 0x49a00000 + SZ_8K
- 1,
2374 .flags
= ADDR_TYPE_RT
,
2379 static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2
= {
2380 .master
= &am33xx_l3_main_hwmod
,
2381 .slave
= &am33xx_tptc2_hwmod
,
2383 .addr
= am33xx_tptc2_addr_space
,
2384 .user
= OCP_USER_MPU
,
2387 /* l4 wkup -> uart1 */
2388 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1
= {
2389 .master
= &am33xx_l4_wkup_hwmod
,
2390 .slave
= &am33xx_uart1_hwmod
,
2391 .clk
= "dpll_core_m4_div2_ck",
2392 .user
= OCP_USER_MPU
,
2395 /* l4 ls -> uart2 */
2396 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2
= {
2397 .master
= &am33xx_l4_ls_hwmod
,
2398 .slave
= &am33xx_uart2_hwmod
,
2400 .user
= OCP_USER_MPU
,
2403 /* l4 ls -> uart3 */
2404 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3
= {
2405 .master
= &am33xx_l4_ls_hwmod
,
2406 .slave
= &am33xx_uart3_hwmod
,
2408 .user
= OCP_USER_MPU
,
2411 /* l4 ls -> uart4 */
2412 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4
= {
2413 .master
= &am33xx_l4_ls_hwmod
,
2414 .slave
= &am33xx_uart4_hwmod
,
2416 .user
= OCP_USER_MPU
,
2419 /* l4 ls -> uart5 */
2420 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5
= {
2421 .master
= &am33xx_l4_ls_hwmod
,
2422 .slave
= &am33xx_uart5_hwmod
,
2424 .user
= OCP_USER_MPU
,
2427 /* l4 ls -> uart6 */
2428 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6
= {
2429 .master
= &am33xx_l4_ls_hwmod
,
2430 .slave
= &am33xx_uart6_hwmod
,
2432 .user
= OCP_USER_MPU
,
2435 /* l4 wkup -> wd_timer1 */
2436 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1
= {
2437 .master
= &am33xx_l4_wkup_hwmod
,
2438 .slave
= &am33xx_wd_timer1_hwmod
,
2439 .clk
= "dpll_core_m4_div2_ck",
2440 .user
= OCP_USER_MPU
,
2444 /* l3 s -> USBSS interface */
2445 static struct omap_hwmod_ocp_if am33xx_l3_s__usbss
= {
2446 .master
= &am33xx_l3_s_hwmod
,
2447 .slave
= &am33xx_usbss_hwmod
,
2449 .user
= OCP_USER_MPU
,
2450 .flags
= OCPIF_SWSUP_IDLE
,
2453 /* l3 main -> ocmc */
2454 static struct omap_hwmod_ocp_if am33xx_l3_main__ocmc
= {
2455 .master
= &am33xx_l3_main_hwmod
,
2456 .slave
= &am33xx_ocmcram_hwmod
,
2457 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2460 /* l3 main -> sha0 HIB2 */
2461 static struct omap_hwmod_addr_space am33xx_sha0_addrs
[] = {
2463 .pa_start
= 0x53100000,
2464 .pa_end
= 0x53100000 + SZ_512
- 1,
2465 .flags
= ADDR_TYPE_RT
2470 static struct omap_hwmod_ocp_if am33xx_l3_main__sha0
= {
2471 .master
= &am33xx_l3_main_hwmod
,
2472 .slave
= &am33xx_sha0_hwmod
,
2474 .addr
= am33xx_sha0_addrs
,
2475 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2478 /* l3 main -> AES0 HIB2 */
2479 static struct omap_hwmod_addr_space am33xx_aes0_addrs
[] = {
2481 .pa_start
= 0x53500000,
2482 .pa_end
= 0x53500000 + SZ_1M
- 1,
2483 .flags
= ADDR_TYPE_RT
2488 static struct omap_hwmod_ocp_if am33xx_l3_main__aes0
= {
2489 .master
= &am33xx_l3_main_hwmod
,
2490 .slave
= &am33xx_aes0_hwmod
,
2492 .addr
= am33xx_aes0_addrs
,
2493 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2496 static struct omap_hwmod_ocp_if
*am33xx_hwmod_ocp_ifs
[] __initdata
= {
2497 &am33xx_l3_main__emif
,
2498 &am33xx_mpu__l3_main
,
2500 &am33xx_l3_s__l4_ls
,
2501 &am33xx_l3_s__l4_wkup
,
2502 &am33xx_l3_main__l4_hs
,
2503 &am33xx_l3_main__l3_s
,
2504 &am33xx_l3_main__l3_instr
,
2505 &am33xx_l3_main__gfx
,
2506 &am33xx_l3_s__l3_main
,
2507 &am33xx_pruss__l3_main
,
2508 &am33xx_wkup_m3__l4_wkup
,
2509 &am33xx_gfx__l3_main
,
2510 &am33xx_l3_main__debugss
,
2511 &am33xx_l4_wkup__wkup_m3
,
2512 &am33xx_l4_wkup__control
,
2513 &am33xx_l4_wkup__smartreflex0
,
2514 &am33xx_l4_wkup__smartreflex1
,
2515 &am33xx_l4_wkup__uart1
,
2516 &am33xx_l4_wkup__timer1
,
2517 &am33xx_l4_wkup__rtc
,
2518 &am33xx_l4_wkup__i2c1
,
2519 &am33xx_l4_wkup__gpio0
,
2520 &am33xx_l4_wkup__adc_tsc
,
2521 &am33xx_l4_wkup__wd_timer1
,
2522 &am33xx_l4_hs__pruss
,
2523 &am33xx_l4_per__dcan0
,
2524 &am33xx_l4_per__dcan1
,
2525 &am33xx_l4_per__gpio1
,
2526 &am33xx_l4_per__gpio2
,
2527 &am33xx_l4_per__gpio3
,
2528 &am33xx_l4_per__i2c2
,
2529 &am33xx_l4_per__i2c3
,
2530 &am33xx_l4_per__mailbox
,
2531 &am33xx_l4_ls__mcasp0
,
2532 &am33xx_l4_ls__mcasp1
,
2533 &am33xx_l4_ls__mmc0
,
2534 &am33xx_l4_ls__mmc1
,
2536 &am33xx_l4_ls__timer2
,
2537 &am33xx_l4_ls__timer3
,
2538 &am33xx_l4_ls__timer4
,
2539 &am33xx_l4_ls__timer5
,
2540 &am33xx_l4_ls__timer6
,
2541 &am33xx_l4_ls__timer7
,
2542 &am33xx_l3_main__tpcc
,
2543 &am33xx_l4_ls__uart2
,
2544 &am33xx_l4_ls__uart3
,
2545 &am33xx_l4_ls__uart4
,
2546 &am33xx_l4_ls__uart5
,
2547 &am33xx_l4_ls__uart6
,
2548 &am33xx_l4_ls__spinlock
,
2550 &am33xx_l4_ls__epwmss0
,
2551 &am33xx_epwmss0__ecap0
,
2552 &am33xx_epwmss0__eqep0
,
2553 &am33xx_epwmss0__ehrpwm0
,
2554 &am33xx_l4_ls__epwmss1
,
2555 &am33xx_epwmss1__ecap1
,
2556 &am33xx_epwmss1__eqep1
,
2557 &am33xx_epwmss1__ehrpwm1
,
2558 &am33xx_l4_ls__epwmss2
,
2559 &am33xx_epwmss2__ecap2
,
2560 &am33xx_epwmss2__eqep2
,
2561 &am33xx_epwmss2__ehrpwm2
,
2563 &am33xx_l3_main__lcdc
,
2564 &am33xx_l4_ls__mcspi0
,
2565 &am33xx_l4_ls__mcspi1
,
2566 &am33xx_l3_main__tptc0
,
2567 &am33xx_l3_main__tptc1
,
2568 &am33xx_l3_main__tptc2
,
2569 &am33xx_l3_main__ocmc
,
2570 &am33xx_l3_s__usbss
,
2571 &am33xx_l4_hs__cpgmac0
,
2572 &am33xx_cpgmac0__mdio
,
2573 &am33xx_l3_main__sha0
,
2574 &am33xx_l3_main__aes0
,
2578 int __init
am33xx_hwmod_init(void)
2581 return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs
);