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ARM: OMAP: AM33xx hwmod: Corrects PWM subsystem HWMOD entries
[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_33xx_data.c
1 /*
2 * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
3 *
4 * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is automatically generated from the AM33XX hardware databases.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <linux/i2c-omap.h>
18
19 #include "omap_hwmod.h"
20 #include <linux/platform_data/gpio-omap.h>
21 #include <linux/platform_data/spi-omap2-mcspi.h>
22
23 #include "omap_hwmod_common_data.h"
24
25 #include "control.h"
26 #include "cm33xx.h"
27 #include "prm33xx.h"
28 #include "prm-regbits-33xx.h"
29 #include "i2c.h"
30 #include "mmc.h"
31
32 /*
33 * IP blocks
34 */
35
36 /*
37 * 'emif_fw' class
38 * instance(s): emif_fw
39 */
40 static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
41 .name = "emif_fw",
42 };
43
44 /* emif_fw */
45 static struct omap_hwmod am33xx_emif_fw_hwmod = {
46 .name = "emif_fw",
47 .class = &am33xx_emif_fw_hwmod_class,
48 .clkdm_name = "l4fw_clkdm",
49 .main_clk = "l4fw_gclk",
50 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
51 .prcm = {
52 .omap4 = {
53 .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
54 .modulemode = MODULEMODE_SWCTRL,
55 },
56 },
57 };
58
59 /*
60 * 'emif' class
61 * instance(s): emif
62 */
63 static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
64 .rev_offs = 0x0000,
65 };
66
67 static struct omap_hwmod_class am33xx_emif_hwmod_class = {
68 .name = "emif",
69 .sysc = &am33xx_emif_sysc,
70 };
71
72 static struct omap_hwmod_irq_info am33xx_emif_irqs[] = {
73 { .name = "ddrerr0", .irq = 101 + OMAP_INTC_START, },
74 { .irq = -1 },
75 };
76
77 /* emif */
78 static struct omap_hwmod am33xx_emif_hwmod = {
79 .name = "emif",
80 .class = &am33xx_emif_hwmod_class,
81 .clkdm_name = "l3_clkdm",
82 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
83 .mpu_irqs = am33xx_emif_irqs,
84 .main_clk = "dpll_ddr_m2_div2_ck",
85 .prcm = {
86 .omap4 = {
87 .clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
88 .modulemode = MODULEMODE_SWCTRL,
89 },
90 },
91 };
92
93 /*
94 * 'l3' class
95 * instance(s): l3_main, l3_s, l3_instr
96 */
97 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
98 .name = "l3",
99 };
100
101 /* l3_main (l3_fast) */
102 static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = {
103 { .name = "l3debug", .irq = 9 + OMAP_INTC_START, },
104 { .name = "l3appint", .irq = 10 + OMAP_INTC_START, },
105 { .irq = -1 },
106 };
107
108 static struct omap_hwmod am33xx_l3_main_hwmod = {
109 .name = "l3_main",
110 .class = &am33xx_l3_hwmod_class,
111 .clkdm_name = "l3_clkdm",
112 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
113 .mpu_irqs = am33xx_l3_main_irqs,
114 .main_clk = "l3_gclk",
115 .prcm = {
116 .omap4 = {
117 .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
118 .modulemode = MODULEMODE_SWCTRL,
119 },
120 },
121 };
122
123 /* l3_s */
124 static struct omap_hwmod am33xx_l3_s_hwmod = {
125 .name = "l3_s",
126 .class = &am33xx_l3_hwmod_class,
127 .clkdm_name = "l3s_clkdm",
128 };
129
130 /* l3_instr */
131 static struct omap_hwmod am33xx_l3_instr_hwmod = {
132 .name = "l3_instr",
133 .class = &am33xx_l3_hwmod_class,
134 .clkdm_name = "l3_clkdm",
135 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
136 .main_clk = "l3_gclk",
137 .prcm = {
138 .omap4 = {
139 .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
140 .modulemode = MODULEMODE_SWCTRL,
141 },
142 },
143 };
144
145 /*
146 * 'l4' class
147 * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
148 */
149 static struct omap_hwmod_class am33xx_l4_hwmod_class = {
150 .name = "l4",
151 };
152
153 /* l4_ls */
154 static struct omap_hwmod am33xx_l4_ls_hwmod = {
155 .name = "l4_ls",
156 .class = &am33xx_l4_hwmod_class,
157 .clkdm_name = "l4ls_clkdm",
158 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
159 .main_clk = "l4ls_gclk",
160 .prcm = {
161 .omap4 = {
162 .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
163 .modulemode = MODULEMODE_SWCTRL,
164 },
165 },
166 };
167
168 /* l4_hs */
169 static struct omap_hwmod am33xx_l4_hs_hwmod = {
170 .name = "l4_hs",
171 .class = &am33xx_l4_hwmod_class,
172 .clkdm_name = "l4hs_clkdm",
173 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
174 .main_clk = "l4hs_gclk",
175 .prcm = {
176 .omap4 = {
177 .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
178 .modulemode = MODULEMODE_SWCTRL,
179 },
180 },
181 };
182
183
184 /* l4_wkup */
185 static struct omap_hwmod am33xx_l4_wkup_hwmod = {
186 .name = "l4_wkup",
187 .class = &am33xx_l4_hwmod_class,
188 .clkdm_name = "l4_wkup_clkdm",
189 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
190 .prcm = {
191 .omap4 = {
192 .clkctrl_offs = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
193 .modulemode = MODULEMODE_SWCTRL,
194 },
195 },
196 };
197
198 /* l4_fw */
199 static struct omap_hwmod am33xx_l4_fw_hwmod = {
200 .name = "l4_fw",
201 .class = &am33xx_l4_hwmod_class,
202 .clkdm_name = "l4fw_clkdm",
203 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
204 .prcm = {
205 .omap4 = {
206 .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
207 .modulemode = MODULEMODE_SWCTRL,
208 },
209 },
210 };
211
212 /*
213 * 'mpu' class
214 */
215 static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
216 .name = "mpu",
217 };
218
219 /* mpu */
220 static struct omap_hwmod_irq_info am33xx_mpu_irqs[] = {
221 { .name = "emuint", .irq = 0 + OMAP_INTC_START, },
222 { .name = "commtx", .irq = 1 + OMAP_INTC_START, },
223 { .name = "commrx", .irq = 2 + OMAP_INTC_START, },
224 { .name = "bench", .irq = 3 + OMAP_INTC_START, },
225 { .irq = -1 },
226 };
227
228 static struct omap_hwmod am33xx_mpu_hwmod = {
229 .name = "mpu",
230 .class = &am33xx_mpu_hwmod_class,
231 .clkdm_name = "mpu_clkdm",
232 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
233 .mpu_irqs = am33xx_mpu_irqs,
234 .main_clk = "dpll_mpu_m2_ck",
235 .prcm = {
236 .omap4 = {
237 .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
238 .modulemode = MODULEMODE_SWCTRL,
239 },
240 },
241 };
242
243 /*
244 * 'wakeup m3' class
245 * Wakeup controller sub-system under wakeup domain
246 */
247 static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
248 .name = "wkup_m3",
249 };
250
251 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
252 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
253 };
254
255 static struct omap_hwmod_irq_info am33xx_wkup_m3_irqs[] = {
256 { .name = "txev", .irq = 78 + OMAP_INTC_START, },
257 { .irq = -1 },
258 };
259
260 /* wkup_m3 */
261 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
262 .name = "wkup_m3",
263 .class = &am33xx_wkup_m3_hwmod_class,
264 .clkdm_name = "l4_wkup_aon_clkdm",
265 .flags = HWMOD_INIT_NO_RESET, /* Keep hardreset asserted */
266 .mpu_irqs = am33xx_wkup_m3_irqs,
267 .main_clk = "dpll_core_m4_div2_ck",
268 .prcm = {
269 .omap4 = {
270 .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
271 .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
272 .rstst_offs = AM33XX_RM_WKUP_RSTST_OFFSET,
273 .modulemode = MODULEMODE_SWCTRL,
274 },
275 },
276 .rst_lines = am33xx_wkup_m3_resets,
277 .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
278 };
279
280 /*
281 * 'pru-icss' class
282 * Programmable Real-Time Unit and Industrial Communication Subsystem
283 */
284 static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
285 .name = "pruss",
286 };
287
288 static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
289 { .name = "pruss", .rst_shift = 1 },
290 };
291
292 static struct omap_hwmod_irq_info am33xx_pruss_irqs[] = {
293 { .name = "evtout0", .irq = 20 + OMAP_INTC_START, },
294 { .name = "evtout1", .irq = 21 + OMAP_INTC_START, },
295 { .name = "evtout2", .irq = 22 + OMAP_INTC_START, },
296 { .name = "evtout3", .irq = 23 + OMAP_INTC_START, },
297 { .name = "evtout4", .irq = 24 + OMAP_INTC_START, },
298 { .name = "evtout5", .irq = 25 + OMAP_INTC_START, },
299 { .name = "evtout6", .irq = 26 + OMAP_INTC_START, },
300 { .name = "evtout7", .irq = 27 + OMAP_INTC_START, },
301 { .irq = -1 },
302 };
303
304 /* pru-icss */
305 /* Pseudo hwmod for reset control purpose only */
306 static struct omap_hwmod am33xx_pruss_hwmod = {
307 .name = "pruss",
308 .class = &am33xx_pruss_hwmod_class,
309 .clkdm_name = "pruss_ocp_clkdm",
310 .mpu_irqs = am33xx_pruss_irqs,
311 .main_clk = "pruss_ocp_gclk",
312 .prcm = {
313 .omap4 = {
314 .clkctrl_offs = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
315 .rstctrl_offs = AM33XX_RM_PER_RSTCTRL_OFFSET,
316 .modulemode = MODULEMODE_SWCTRL,
317 },
318 },
319 .rst_lines = am33xx_pruss_resets,
320 .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
321 };
322
323 /* gfx */
324 /* Pseudo hwmod for reset control purpose only */
325 static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
326 .name = "gfx",
327 };
328
329 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
330 { .name = "gfx", .rst_shift = 0 },
331 };
332
333 static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
334 { .name = "gfxint", .irq = 37 + OMAP_INTC_START, },
335 { .irq = -1 },
336 };
337
338 static struct omap_hwmod am33xx_gfx_hwmod = {
339 .name = "gfx",
340 .class = &am33xx_gfx_hwmod_class,
341 .clkdm_name = "gfx_l3_clkdm",
342 .mpu_irqs = am33xx_gfx_irqs,
343 .main_clk = "gfx_fck_div_ck",
344 .prcm = {
345 .omap4 = {
346 .clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
347 .rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET,
348 .modulemode = MODULEMODE_SWCTRL,
349 },
350 },
351 .rst_lines = am33xx_gfx_resets,
352 .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets),
353 };
354
355 /*
356 * 'prcm' class
357 * power and reset manager (whole prcm infrastructure)
358 */
359 static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
360 .name = "prcm",
361 };
362
363 /* prcm */
364 static struct omap_hwmod am33xx_prcm_hwmod = {
365 .name = "prcm",
366 .class = &am33xx_prcm_hwmod_class,
367 .clkdm_name = "l4_wkup_clkdm",
368 };
369
370 /*
371 * 'adc/tsc' class
372 * TouchScreen Controller (Anolog-To-Digital Converter)
373 */
374 static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
375 .rev_offs = 0x00,
376 .sysc_offs = 0x10,
377 .sysc_flags = SYSC_HAS_SIDLEMODE,
378 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
379 SIDLE_SMART_WKUP),
380 .sysc_fields = &omap_hwmod_sysc_type2,
381 };
382
383 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
384 .name = "adc_tsc",
385 .sysc = &am33xx_adc_tsc_sysc,
386 };
387
388 static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
389 { .irq = 16 + OMAP_INTC_START, },
390 { .irq = -1 },
391 };
392
393 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
394 .name = "adc_tsc",
395 .class = &am33xx_adc_tsc_hwmod_class,
396 .clkdm_name = "l4_wkup_clkdm",
397 .mpu_irqs = am33xx_adc_tsc_irqs,
398 .main_clk = "adc_tsc_fck",
399 .prcm = {
400 .omap4 = {
401 .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
402 .modulemode = MODULEMODE_SWCTRL,
403 },
404 },
405 };
406
407 /*
408 * Modules omap_hwmod structures
409 *
410 * The following IPs are excluded for the moment because:
411 * - They do not need an explicit SW control using omap_hwmod API.
412 * - They still need to be validated with the driver
413 * properly adapted to omap_hwmod / omap_device
414 *
415 * - cEFUSE (doesn't fall under any ocp_if)
416 * - clkdiv32k
417 * - debugss
418 * - ocp watch point
419 * - aes0
420 * - sha0
421 */
422 #if 0
423 /*
424 * 'cefuse' class
425 */
426 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
427 .name = "cefuse",
428 };
429
430 static struct omap_hwmod am33xx_cefuse_hwmod = {
431 .name = "cefuse",
432 .class = &am33xx_cefuse_hwmod_class,
433 .clkdm_name = "l4_cefuse_clkdm",
434 .main_clk = "cefuse_fck",
435 .prcm = {
436 .omap4 = {
437 .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
438 .modulemode = MODULEMODE_SWCTRL,
439 },
440 },
441 };
442
443 /*
444 * 'clkdiv32k' class
445 */
446 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
447 .name = "clkdiv32k",
448 };
449
450 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
451 .name = "clkdiv32k",
452 .class = &am33xx_clkdiv32k_hwmod_class,
453 .clkdm_name = "clk_24mhz_clkdm",
454 .main_clk = "clkdiv32k_ick",
455 .prcm = {
456 .omap4 = {
457 .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
458 .modulemode = MODULEMODE_SWCTRL,
459 },
460 },
461 };
462
463 /*
464 * 'debugss' class
465 * debug sub system
466 */
467 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
468 .name = "debugss",
469 };
470
471 static struct omap_hwmod am33xx_debugss_hwmod = {
472 .name = "debugss",
473 .class = &am33xx_debugss_hwmod_class,
474 .clkdm_name = "l3_aon_clkdm",
475 .main_clk = "debugss_ick",
476 .prcm = {
477 .omap4 = {
478 .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
479 .modulemode = MODULEMODE_SWCTRL,
480 },
481 },
482 };
483
484 /* ocpwp */
485 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
486 .name = "ocpwp",
487 };
488
489 static struct omap_hwmod am33xx_ocpwp_hwmod = {
490 .name = "ocpwp",
491 .class = &am33xx_ocpwp_hwmod_class,
492 .clkdm_name = "l4ls_clkdm",
493 .main_clk = "l4ls_gclk",
494 .prcm = {
495 .omap4 = {
496 .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
497 .modulemode = MODULEMODE_SWCTRL,
498 },
499 },
500 };
501
502 /*
503 * 'aes' class
504 */
505 static struct omap_hwmod_class am33xx_aes_hwmod_class = {
506 .name = "aes",
507 };
508
509 static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
510 { .irq = 102 + OMAP_INTC_START, },
511 { .irq = -1 },
512 };
513
514 static struct omap_hwmod am33xx_aes0_hwmod = {
515 .name = "aes0",
516 .class = &am33xx_aes_hwmod_class,
517 .clkdm_name = "l3_clkdm",
518 .mpu_irqs = am33xx_aes0_irqs,
519 .main_clk = "l3_gclk",
520 .prcm = {
521 .omap4 = {
522 .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
523 .modulemode = MODULEMODE_SWCTRL,
524 },
525 },
526 };
527
528 /* sha0 */
529 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
530 .name = "sha0",
531 };
532
533 static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
534 { .irq = 108 + OMAP_INTC_START, },
535 { .irq = -1 },
536 };
537
538 static struct omap_hwmod am33xx_sha0_hwmod = {
539 .name = "sha0",
540 .class = &am33xx_sha0_hwmod_class,
541 .clkdm_name = "l3_clkdm",
542 .mpu_irqs = am33xx_sha0_irqs,
543 .main_clk = "l3_gclk",
544 .prcm = {
545 .omap4 = {
546 .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
547 .modulemode = MODULEMODE_SWCTRL,
548 },
549 },
550 };
551
552 #endif
553
554 /* ocmcram */
555 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
556 .name = "ocmcram",
557 };
558
559 static struct omap_hwmod am33xx_ocmcram_hwmod = {
560 .name = "ocmcram",
561 .class = &am33xx_ocmcram_hwmod_class,
562 .clkdm_name = "l3_clkdm",
563 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
564 .main_clk = "l3_gclk",
565 .prcm = {
566 .omap4 = {
567 .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
568 .modulemode = MODULEMODE_SWCTRL,
569 },
570 },
571 };
572
573 /* 'smartreflex' class */
574 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
575 .name = "smartreflex",
576 };
577
578 /* smartreflex0 */
579 static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
580 { .irq = 120 + OMAP_INTC_START, },
581 { .irq = -1 },
582 };
583
584 static struct omap_hwmod am33xx_smartreflex0_hwmod = {
585 .name = "smartreflex0",
586 .class = &am33xx_smartreflex_hwmod_class,
587 .clkdm_name = "l4_wkup_clkdm",
588 .mpu_irqs = am33xx_smartreflex0_irqs,
589 .main_clk = "smartreflex0_fck",
590 .prcm = {
591 .omap4 = {
592 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
593 .modulemode = MODULEMODE_SWCTRL,
594 },
595 },
596 };
597
598 /* smartreflex1 */
599 static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
600 { .irq = 121 + OMAP_INTC_START, },
601 { .irq = -1 },
602 };
603
604 static struct omap_hwmod am33xx_smartreflex1_hwmod = {
605 .name = "smartreflex1",
606 .class = &am33xx_smartreflex_hwmod_class,
607 .clkdm_name = "l4_wkup_clkdm",
608 .mpu_irqs = am33xx_smartreflex1_irqs,
609 .main_clk = "smartreflex1_fck",
610 .prcm = {
611 .omap4 = {
612 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
613 .modulemode = MODULEMODE_SWCTRL,
614 },
615 },
616 };
617
618 /*
619 * 'control' module class
620 */
621 static struct omap_hwmod_class am33xx_control_hwmod_class = {
622 .name = "control",
623 };
624
625 static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
626 { .irq = 8 + OMAP_INTC_START, },
627 { .irq = -1 },
628 };
629
630 static struct omap_hwmod am33xx_control_hwmod = {
631 .name = "control",
632 .class = &am33xx_control_hwmod_class,
633 .clkdm_name = "l4_wkup_clkdm",
634 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
635 .mpu_irqs = am33xx_control_irqs,
636 .main_clk = "dpll_core_m4_div2_ck",
637 .prcm = {
638 .omap4 = {
639 .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
640 .modulemode = MODULEMODE_SWCTRL,
641 },
642 },
643 };
644
645 /*
646 * 'cpgmac' class
647 * cpsw/cpgmac sub system
648 */
649 static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
650 .rev_offs = 0x0,
651 .sysc_offs = 0x8,
652 .syss_offs = 0x4,
653 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
654 SYSS_HAS_RESET_STATUS),
655 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
656 MSTANDBY_NO),
657 .sysc_fields = &omap_hwmod_sysc_type3,
658 };
659
660 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
661 .name = "cpgmac0",
662 .sysc = &am33xx_cpgmac_sysc,
663 };
664
665 static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
666 { .name = "c0_rx_thresh_pend", .irq = 40 + OMAP_INTC_START, },
667 { .name = "c0_rx_pend", .irq = 41 + OMAP_INTC_START, },
668 { .name = "c0_tx_pend", .irq = 42 + OMAP_INTC_START, },
669 { .name = "c0_misc_pend", .irq = 43 + OMAP_INTC_START, },
670 { .irq = -1 },
671 };
672
673 static struct omap_hwmod am33xx_cpgmac0_hwmod = {
674 .name = "cpgmac0",
675 .class = &am33xx_cpgmac0_hwmod_class,
676 .clkdm_name = "cpsw_125mhz_clkdm",
677 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
678 .mpu_irqs = am33xx_cpgmac0_irqs,
679 .main_clk = "cpsw_125mhz_gclk",
680 .prcm = {
681 .omap4 = {
682 .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
683 .modulemode = MODULEMODE_SWCTRL,
684 },
685 },
686 };
687
688 /*
689 * mdio class
690 */
691 static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
692 .name = "davinci_mdio",
693 };
694
695 static struct omap_hwmod am33xx_mdio_hwmod = {
696 .name = "davinci_mdio",
697 .class = &am33xx_mdio_hwmod_class,
698 .clkdm_name = "cpsw_125mhz_clkdm",
699 .main_clk = "cpsw_125mhz_gclk",
700 };
701
702 /*
703 * dcan class
704 */
705 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
706 .name = "d_can",
707 };
708
709 /* dcan0 */
710 static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
711 { .name = "d_can_ms", .irq = 52 + OMAP_INTC_START, },
712 { .name = "d_can_mo", .irq = 53 + OMAP_INTC_START, },
713 { .irq = -1 },
714 };
715
716 static struct omap_hwmod am33xx_dcan0_hwmod = {
717 .name = "d_can0",
718 .class = &am33xx_dcan_hwmod_class,
719 .clkdm_name = "l4ls_clkdm",
720 .mpu_irqs = am33xx_dcan0_irqs,
721 .main_clk = "dcan0_fck",
722 .prcm = {
723 .omap4 = {
724 .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
725 .modulemode = MODULEMODE_SWCTRL,
726 },
727 },
728 };
729
730 /* dcan1 */
731 static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
732 { .name = "d_can_ms", .irq = 55 + OMAP_INTC_START, },
733 { .name = "d_can_mo", .irq = 56 + OMAP_INTC_START, },
734 { .irq = -1 },
735 };
736 static struct omap_hwmod am33xx_dcan1_hwmod = {
737 .name = "d_can1",
738 .class = &am33xx_dcan_hwmod_class,
739 .clkdm_name = "l4ls_clkdm",
740 .mpu_irqs = am33xx_dcan1_irqs,
741 .main_clk = "dcan1_fck",
742 .prcm = {
743 .omap4 = {
744 .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
745 .modulemode = MODULEMODE_SWCTRL,
746 },
747 },
748 };
749
750 /* elm */
751 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
752 .rev_offs = 0x0000,
753 .sysc_offs = 0x0010,
754 .syss_offs = 0x0014,
755 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
756 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
757 SYSS_HAS_RESET_STATUS),
758 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
759 .sysc_fields = &omap_hwmod_sysc_type1,
760 };
761
762 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
763 .name = "elm",
764 .sysc = &am33xx_elm_sysc,
765 };
766
767 static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
768 { .irq = 4 + OMAP_INTC_START, },
769 { .irq = -1 },
770 };
771
772 static struct omap_hwmod am33xx_elm_hwmod = {
773 .name = "elm",
774 .class = &am33xx_elm_hwmod_class,
775 .clkdm_name = "l4ls_clkdm",
776 .mpu_irqs = am33xx_elm_irqs,
777 .main_clk = "l4ls_gclk",
778 .prcm = {
779 .omap4 = {
780 .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
781 .modulemode = MODULEMODE_SWCTRL,
782 },
783 },
784 };
785
786 /*
787 * 'epwmss' class: ehrpwm0,1,2 eqep0,1,2 ecap0,1,2
788 */
789 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
790 .rev_offs = 0x0,
791 .sysc_offs = 0x4,
792 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
793 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
794 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
795 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
796 .sysc_fields = &omap_hwmod_sysc_type2,
797 };
798
799 static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
800 .name = "epwmss",
801 .sysc = &am33xx_epwmss_sysc,
802 };
803
804 /* ehrpwm0 */
805 static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
806 { .name = "int", .irq = 86 + OMAP_INTC_START, },
807 { .name = "tzint", .irq = 58 + OMAP_INTC_START, },
808 { .irq = -1 },
809 };
810
811 static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
812 .name = "ehrpwm0",
813 .class = &am33xx_epwmss_hwmod_class,
814 .clkdm_name = "l4ls_clkdm",
815 .mpu_irqs = am33xx_ehrpwm0_irqs,
816 .main_clk = "l4ls_gclk",
817 .prcm = {
818 .omap4 = {
819 .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
820 .modulemode = MODULEMODE_SWCTRL,
821 },
822 },
823 };
824
825 /* ehrpwm1 */
826 static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
827 { .name = "int", .irq = 87 + OMAP_INTC_START, },
828 { .name = "tzint", .irq = 59 + OMAP_INTC_START, },
829 { .irq = -1 },
830 };
831
832 static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
833 .name = "ehrpwm1",
834 .class = &am33xx_epwmss_hwmod_class,
835 .clkdm_name = "l4ls_clkdm",
836 .mpu_irqs = am33xx_ehrpwm1_irqs,
837 .main_clk = "l4ls_gclk",
838 .prcm = {
839 .omap4 = {
840 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
841 .modulemode = MODULEMODE_SWCTRL,
842 },
843 },
844 };
845
846 /* ehrpwm2 */
847 static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
848 { .name = "int", .irq = 39 + OMAP_INTC_START, },
849 { .name = "tzint", .irq = 60 + OMAP_INTC_START, },
850 { .irq = -1 },
851 };
852
853 static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
854 .name = "ehrpwm2",
855 .class = &am33xx_epwmss_hwmod_class,
856 .clkdm_name = "l4ls_clkdm",
857 .mpu_irqs = am33xx_ehrpwm2_irqs,
858 .main_clk = "l4ls_gclk",
859 .prcm = {
860 .omap4 = {
861 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
862 .modulemode = MODULEMODE_SWCTRL,
863 },
864 },
865 };
866
867 /* eqep0 */
868 static struct omap_hwmod_irq_info am33xx_eqep0_irqs[] = {
869 { .irq = 79 + OMAP_INTC_START, },
870 { .irq = -1 },
871 };
872
873 static struct omap_hwmod am33xx_eqep0_hwmod = {
874 .name = "eqep0",
875 .class = &am33xx_epwmss_hwmod_class,
876 .clkdm_name = "l4ls_clkdm",
877 .mpu_irqs = am33xx_eqep0_irqs,
878 .main_clk = "l4ls_gclk",
879 .prcm = {
880 .omap4 = {
881 .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
882 .modulemode = MODULEMODE_SWCTRL,
883 },
884 },
885 };
886
887 /* eqep1 */
888 static struct omap_hwmod_irq_info am33xx_eqep1_irqs[] = {
889 { .irq = 88 + OMAP_INTC_START, },
890 { .irq = -1 },
891 };
892
893 static struct omap_hwmod am33xx_eqep1_hwmod = {
894 .name = "eqep1",
895 .class = &am33xx_epwmss_hwmod_class,
896 .clkdm_name = "l4ls_clkdm",
897 .mpu_irqs = am33xx_eqep1_irqs,
898 .main_clk = "l4ls_gclk",
899 .prcm = {
900 .omap4 = {
901 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
902 .modulemode = MODULEMODE_SWCTRL,
903 },
904 },
905 };
906
907 /* eqep2 */
908 static struct omap_hwmod_irq_info am33xx_eqep2_irqs[] = {
909 { .irq = 89 + OMAP_INTC_START, },
910 { .irq = -1 },
911 };
912
913 static struct omap_hwmod am33xx_eqep2_hwmod = {
914 .name = "eqep2",
915 .class = &am33xx_epwmss_hwmod_class,
916 .clkdm_name = "l4ls_clkdm",
917 .mpu_irqs = am33xx_eqep2_irqs,
918 .main_clk = "l4ls_gclk",
919 .prcm = {
920 .omap4 = {
921 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
922 .modulemode = MODULEMODE_SWCTRL,
923 },
924 },
925 };
926
927 /* ecap0 */
928 static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
929 { .irq = 31 + OMAP_INTC_START, },
930 { .irq = -1 },
931 };
932
933 static struct omap_hwmod am33xx_ecap0_hwmod = {
934 .name = "ecap0",
935 .class = &am33xx_epwmss_hwmod_class,
936 .clkdm_name = "l4ls_clkdm",
937 .mpu_irqs = am33xx_ecap0_irqs,
938 .main_clk = "l4ls_gclk",
939 .prcm = {
940 .omap4 = {
941 .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
942 .modulemode = MODULEMODE_SWCTRL,
943 },
944 },
945 };
946
947 /* ecap1 */
948 static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
949 { .irq = 47 + OMAP_INTC_START, },
950 { .irq = -1 },
951 };
952
953 static struct omap_hwmod am33xx_ecap1_hwmod = {
954 .name = "ecap1",
955 .class = &am33xx_epwmss_hwmod_class,
956 .clkdm_name = "l4ls_clkdm",
957 .mpu_irqs = am33xx_ecap1_irqs,
958 .main_clk = "l4ls_gclk",
959 .prcm = {
960 .omap4 = {
961 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
962 .modulemode = MODULEMODE_SWCTRL,
963 },
964 },
965 };
966
967 /* ecap2 */
968 static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
969 { .irq = 61 + OMAP_INTC_START, },
970 { .irq = -1 },
971 };
972
973 static struct omap_hwmod am33xx_ecap2_hwmod = {
974 .name = "ecap2",
975 .mpu_irqs = am33xx_ecap2_irqs,
976 .class = &am33xx_epwmss_hwmod_class,
977 .clkdm_name = "l4ls_clkdm",
978 .main_clk = "l4ls_gclk",
979 .prcm = {
980 .omap4 = {
981 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
982 .modulemode = MODULEMODE_SWCTRL,
983 },
984 },
985 };
986
987 /*
988 * 'gpio' class: for gpio 0,1,2,3
989 */
990 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
991 .rev_offs = 0x0000,
992 .sysc_offs = 0x0010,
993 .syss_offs = 0x0114,
994 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
995 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
996 SYSS_HAS_RESET_STATUS),
997 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
998 SIDLE_SMART_WKUP),
999 .sysc_fields = &omap_hwmod_sysc_type1,
1000 };
1001
1002 static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
1003 .name = "gpio",
1004 .sysc = &am33xx_gpio_sysc,
1005 .rev = 2,
1006 };
1007
1008 static struct omap_gpio_dev_attr gpio_dev_attr = {
1009 .bank_width = 32,
1010 .dbck_flag = true,
1011 };
1012
1013 /* gpio0 */
1014 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
1015 { .role = "dbclk", .clk = "gpio0_dbclk" },
1016 };
1017
1018 static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
1019 { .irq = 96 + OMAP_INTC_START, },
1020 { .irq = -1 },
1021 };
1022
1023 static struct omap_hwmod am33xx_gpio0_hwmod = {
1024 .name = "gpio1",
1025 .class = &am33xx_gpio_hwmod_class,
1026 .clkdm_name = "l4_wkup_clkdm",
1027 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1028 .mpu_irqs = am33xx_gpio0_irqs,
1029 .main_clk = "dpll_core_m4_div2_ck",
1030 .prcm = {
1031 .omap4 = {
1032 .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
1033 .modulemode = MODULEMODE_SWCTRL,
1034 },
1035 },
1036 .opt_clks = gpio0_opt_clks,
1037 .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
1038 .dev_attr = &gpio_dev_attr,
1039 };
1040
1041 /* gpio1 */
1042 static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
1043 { .irq = 98 + OMAP_INTC_START, },
1044 { .irq = -1 },
1045 };
1046
1047 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1048 { .role = "dbclk", .clk = "gpio1_dbclk" },
1049 };
1050
1051 static struct omap_hwmod am33xx_gpio1_hwmod = {
1052 .name = "gpio2",
1053 .class = &am33xx_gpio_hwmod_class,
1054 .clkdm_name = "l4ls_clkdm",
1055 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1056 .mpu_irqs = am33xx_gpio1_irqs,
1057 .main_clk = "l4ls_gclk",
1058 .prcm = {
1059 .omap4 = {
1060 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
1061 .modulemode = MODULEMODE_SWCTRL,
1062 },
1063 },
1064 .opt_clks = gpio1_opt_clks,
1065 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1066 .dev_attr = &gpio_dev_attr,
1067 };
1068
1069 /* gpio2 */
1070 static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
1071 { .irq = 32 + OMAP_INTC_START, },
1072 { .irq = -1 },
1073 };
1074
1075 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1076 { .role = "dbclk", .clk = "gpio2_dbclk" },
1077 };
1078
1079 static struct omap_hwmod am33xx_gpio2_hwmod = {
1080 .name = "gpio3",
1081 .class = &am33xx_gpio_hwmod_class,
1082 .clkdm_name = "l4ls_clkdm",
1083 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1084 .mpu_irqs = am33xx_gpio2_irqs,
1085 .main_clk = "l4ls_gclk",
1086 .prcm = {
1087 .omap4 = {
1088 .clkctrl_offs = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
1089 .modulemode = MODULEMODE_SWCTRL,
1090 },
1091 },
1092 .opt_clks = gpio2_opt_clks,
1093 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1094 .dev_attr = &gpio_dev_attr,
1095 };
1096
1097 /* gpio3 */
1098 static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
1099 { .irq = 62 + OMAP_INTC_START, },
1100 { .irq = -1 },
1101 };
1102
1103 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1104 { .role = "dbclk", .clk = "gpio3_dbclk" },
1105 };
1106
1107 static struct omap_hwmod am33xx_gpio3_hwmod = {
1108 .name = "gpio4",
1109 .class = &am33xx_gpio_hwmod_class,
1110 .clkdm_name = "l4ls_clkdm",
1111 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1112 .mpu_irqs = am33xx_gpio3_irqs,
1113 .main_clk = "l4ls_gclk",
1114 .prcm = {
1115 .omap4 = {
1116 .clkctrl_offs = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
1117 .modulemode = MODULEMODE_SWCTRL,
1118 },
1119 },
1120 .opt_clks = gpio3_opt_clks,
1121 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1122 .dev_attr = &gpio_dev_attr,
1123 };
1124
1125 /* gpmc */
1126 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
1127 .rev_offs = 0x0,
1128 .sysc_offs = 0x10,
1129 .syss_offs = 0x14,
1130 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1131 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1132 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1133 .sysc_fields = &omap_hwmod_sysc_type1,
1134 };
1135
1136 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
1137 .name = "gpmc",
1138 .sysc = &gpmc_sysc,
1139 };
1140
1141 static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = {
1142 { .irq = 100 + OMAP_INTC_START, },
1143 { .irq = -1 },
1144 };
1145
1146 static struct omap_hwmod am33xx_gpmc_hwmod = {
1147 .name = "gpmc",
1148 .class = &am33xx_gpmc_hwmod_class,
1149 .clkdm_name = "l3s_clkdm",
1150 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1151 .mpu_irqs = am33xx_gpmc_irqs,
1152 .main_clk = "l3s_gclk",
1153 .prcm = {
1154 .omap4 = {
1155 .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
1156 .modulemode = MODULEMODE_SWCTRL,
1157 },
1158 },
1159 };
1160
1161 /* 'i2c' class */
1162 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
1163 .sysc_offs = 0x0010,
1164 .syss_offs = 0x0090,
1165 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1166 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1167 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1168 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1169 SIDLE_SMART_WKUP),
1170 .sysc_fields = &omap_hwmod_sysc_type1,
1171 };
1172
1173 static struct omap_hwmod_class i2c_class = {
1174 .name = "i2c",
1175 .sysc = &am33xx_i2c_sysc,
1176 .rev = OMAP_I2C_IP_VERSION_2,
1177 .reset = &omap_i2c_reset,
1178 };
1179
1180 static struct omap_i2c_dev_attr i2c_dev_attr = {
1181 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1182 };
1183
1184 /* i2c1 */
1185 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1186 { .irq = 70 + OMAP_INTC_START, },
1187 { .irq = -1 },
1188 };
1189
1190 static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
1191 { .name = "tx", .dma_req = 0, },
1192 { .name = "rx", .dma_req = 0, },
1193 { .dma_req = -1 }
1194 };
1195
1196 static struct omap_hwmod am33xx_i2c1_hwmod = {
1197 .name = "i2c1",
1198 .class = &i2c_class,
1199 .clkdm_name = "l4_wkup_clkdm",
1200 .mpu_irqs = i2c1_mpu_irqs,
1201 .sdma_reqs = i2c1_edma_reqs,
1202 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1203 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
1204 .prcm = {
1205 .omap4 = {
1206 .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
1207 .modulemode = MODULEMODE_SWCTRL,
1208 },
1209 },
1210 .dev_attr = &i2c_dev_attr,
1211 };
1212
1213 /* i2c1 */
1214 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1215 { .irq = 71 + OMAP_INTC_START, },
1216 { .irq = -1 },
1217 };
1218
1219 static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
1220 { .name = "tx", .dma_req = 0, },
1221 { .name = "rx", .dma_req = 0, },
1222 { .dma_req = -1 }
1223 };
1224
1225 static struct omap_hwmod am33xx_i2c2_hwmod = {
1226 .name = "i2c2",
1227 .class = &i2c_class,
1228 .clkdm_name = "l4ls_clkdm",
1229 .mpu_irqs = i2c2_mpu_irqs,
1230 .sdma_reqs = i2c2_edma_reqs,
1231 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1232 .main_clk = "dpll_per_m2_div4_ck",
1233 .prcm = {
1234 .omap4 = {
1235 .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
1236 .modulemode = MODULEMODE_SWCTRL,
1237 },
1238 },
1239 .dev_attr = &i2c_dev_attr,
1240 };
1241
1242 /* i2c3 */
1243 static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
1244 { .name = "tx", .dma_req = 0, },
1245 { .name = "rx", .dma_req = 0, },
1246 { .dma_req = -1 }
1247 };
1248
1249 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1250 { .irq = 30 + OMAP_INTC_START, },
1251 { .irq = -1 },
1252 };
1253
1254 static struct omap_hwmod am33xx_i2c3_hwmod = {
1255 .name = "i2c3",
1256 .class = &i2c_class,
1257 .clkdm_name = "l4ls_clkdm",
1258 .mpu_irqs = i2c3_mpu_irqs,
1259 .sdma_reqs = i2c3_edma_reqs,
1260 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1261 .main_clk = "dpll_per_m2_div4_ck",
1262 .prcm = {
1263 .omap4 = {
1264 .clkctrl_offs = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
1265 .modulemode = MODULEMODE_SWCTRL,
1266 },
1267 },
1268 .dev_attr = &i2c_dev_attr,
1269 };
1270
1271
1272 /* lcdc */
1273 static struct omap_hwmod_class_sysconfig lcdc_sysc = {
1274 .rev_offs = 0x0,
1275 .sysc_offs = 0x54,
1276 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
1277 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1278 .sysc_fields = &omap_hwmod_sysc_type2,
1279 };
1280
1281 static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
1282 .name = "lcdc",
1283 .sysc = &lcdc_sysc,
1284 };
1285
1286 static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
1287 { .irq = 36 + OMAP_INTC_START, },
1288 { .irq = -1 },
1289 };
1290
1291 static struct omap_hwmod am33xx_lcdc_hwmod = {
1292 .name = "lcdc",
1293 .class = &am33xx_lcdc_hwmod_class,
1294 .clkdm_name = "lcdc_clkdm",
1295 .mpu_irqs = am33xx_lcdc_irqs,
1296 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1297 .main_clk = "lcd_gclk",
1298 .prcm = {
1299 .omap4 = {
1300 .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
1301 .modulemode = MODULEMODE_SWCTRL,
1302 },
1303 },
1304 };
1305
1306 /*
1307 * 'mailbox' class
1308 * mailbox module allowing communication between the on-chip processors using a
1309 * queued mailbox-interrupt mechanism.
1310 */
1311 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
1312 .rev_offs = 0x0000,
1313 .sysc_offs = 0x0010,
1314 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1315 SYSC_HAS_SOFTRESET),
1316 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1317 .sysc_fields = &omap_hwmod_sysc_type2,
1318 };
1319
1320 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
1321 .name = "mailbox",
1322 .sysc = &am33xx_mailbox_sysc,
1323 };
1324
1325 static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
1326 { .irq = 77 + OMAP_INTC_START, },
1327 { .irq = -1 },
1328 };
1329
1330 static struct omap_hwmod am33xx_mailbox_hwmod = {
1331 .name = "mailbox",
1332 .class = &am33xx_mailbox_hwmod_class,
1333 .clkdm_name = "l4ls_clkdm",
1334 .mpu_irqs = am33xx_mailbox_irqs,
1335 .main_clk = "l4ls_gclk",
1336 .prcm = {
1337 .omap4 = {
1338 .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
1339 .modulemode = MODULEMODE_SWCTRL,
1340 },
1341 },
1342 };
1343
1344 /*
1345 * 'mcasp' class
1346 */
1347 static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
1348 .rev_offs = 0x0,
1349 .sysc_offs = 0x4,
1350 .sysc_flags = SYSC_HAS_SIDLEMODE,
1351 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1352 .sysc_fields = &omap_hwmod_sysc_type3,
1353 };
1354
1355 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
1356 .name = "mcasp",
1357 .sysc = &am33xx_mcasp_sysc,
1358 };
1359
1360 /* mcasp0 */
1361 static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
1362 { .name = "ax", .irq = 80 + OMAP_INTC_START, },
1363 { .name = "ar", .irq = 81 + OMAP_INTC_START, },
1364 { .irq = -1 },
1365 };
1366
1367 static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = {
1368 { .name = "tx", .dma_req = 8, },
1369 { .name = "rx", .dma_req = 9, },
1370 { .dma_req = -1 }
1371 };
1372
1373 static struct omap_hwmod am33xx_mcasp0_hwmod = {
1374 .name = "mcasp0",
1375 .class = &am33xx_mcasp_hwmod_class,
1376 .clkdm_name = "l3s_clkdm",
1377 .mpu_irqs = am33xx_mcasp0_irqs,
1378 .sdma_reqs = am33xx_mcasp0_edma_reqs,
1379 .main_clk = "mcasp0_fck",
1380 .prcm = {
1381 .omap4 = {
1382 .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
1383 .modulemode = MODULEMODE_SWCTRL,
1384 },
1385 },
1386 };
1387
1388 /* mcasp1 */
1389 static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
1390 { .name = "ax", .irq = 82 + OMAP_INTC_START, },
1391 { .name = "ar", .irq = 83 + OMAP_INTC_START, },
1392 { .irq = -1 },
1393 };
1394
1395 static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = {
1396 { .name = "tx", .dma_req = 10, },
1397 { .name = "rx", .dma_req = 11, },
1398 { .dma_req = -1 }
1399 };
1400
1401 static struct omap_hwmod am33xx_mcasp1_hwmod = {
1402 .name = "mcasp1",
1403 .class = &am33xx_mcasp_hwmod_class,
1404 .clkdm_name = "l3s_clkdm",
1405 .mpu_irqs = am33xx_mcasp1_irqs,
1406 .sdma_reqs = am33xx_mcasp1_edma_reqs,
1407 .main_clk = "mcasp1_fck",
1408 .prcm = {
1409 .omap4 = {
1410 .clkctrl_offs = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
1411 .modulemode = MODULEMODE_SWCTRL,
1412 },
1413 },
1414 };
1415
1416 /* 'mmc' class */
1417 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
1418 .rev_offs = 0x1fc,
1419 .sysc_offs = 0x10,
1420 .syss_offs = 0x14,
1421 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1422 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1423 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1424 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1425 .sysc_fields = &omap_hwmod_sysc_type1,
1426 };
1427
1428 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
1429 .name = "mmc",
1430 .sysc = &am33xx_mmc_sysc,
1431 };
1432
1433 /* mmc0 */
1434 static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
1435 { .irq = 64 + OMAP_INTC_START, },
1436 { .irq = -1 },
1437 };
1438
1439 static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
1440 { .name = "tx", .dma_req = 24, },
1441 { .name = "rx", .dma_req = 25, },
1442 { .dma_req = -1 }
1443 };
1444
1445 static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
1446 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1447 };
1448
1449 static struct omap_hwmod am33xx_mmc0_hwmod = {
1450 .name = "mmc1",
1451 .class = &am33xx_mmc_hwmod_class,
1452 .clkdm_name = "l4ls_clkdm",
1453 .mpu_irqs = am33xx_mmc0_irqs,
1454 .sdma_reqs = am33xx_mmc0_edma_reqs,
1455 .main_clk = "mmc_clk",
1456 .prcm = {
1457 .omap4 = {
1458 .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
1459 .modulemode = MODULEMODE_SWCTRL,
1460 },
1461 },
1462 .dev_attr = &am33xx_mmc0_dev_attr,
1463 };
1464
1465 /* mmc1 */
1466 static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
1467 { .irq = 28 + OMAP_INTC_START, },
1468 { .irq = -1 },
1469 };
1470
1471 static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
1472 { .name = "tx", .dma_req = 2, },
1473 { .name = "rx", .dma_req = 3, },
1474 { .dma_req = -1 }
1475 };
1476
1477 static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
1478 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1479 };
1480
1481 static struct omap_hwmod am33xx_mmc1_hwmod = {
1482 .name = "mmc2",
1483 .class = &am33xx_mmc_hwmod_class,
1484 .clkdm_name = "l4ls_clkdm",
1485 .mpu_irqs = am33xx_mmc1_irqs,
1486 .sdma_reqs = am33xx_mmc1_edma_reqs,
1487 .main_clk = "mmc_clk",
1488 .prcm = {
1489 .omap4 = {
1490 .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
1491 .modulemode = MODULEMODE_SWCTRL,
1492 },
1493 },
1494 .dev_attr = &am33xx_mmc1_dev_attr,
1495 };
1496
1497 /* mmc2 */
1498 static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
1499 { .irq = 29 + OMAP_INTC_START, },
1500 { .irq = -1 },
1501 };
1502
1503 static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
1504 { .name = "tx", .dma_req = 64, },
1505 { .name = "rx", .dma_req = 65, },
1506 { .dma_req = -1 }
1507 };
1508
1509 static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
1510 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1511 };
1512 static struct omap_hwmod am33xx_mmc2_hwmod = {
1513 .name = "mmc3",
1514 .class = &am33xx_mmc_hwmod_class,
1515 .clkdm_name = "l3s_clkdm",
1516 .mpu_irqs = am33xx_mmc2_irqs,
1517 .sdma_reqs = am33xx_mmc2_edma_reqs,
1518 .main_clk = "mmc_clk",
1519 .prcm = {
1520 .omap4 = {
1521 .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
1522 .modulemode = MODULEMODE_SWCTRL,
1523 },
1524 },
1525 .dev_attr = &am33xx_mmc2_dev_attr,
1526 };
1527
1528 /*
1529 * 'rtc' class
1530 * rtc subsystem
1531 */
1532 static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
1533 .rev_offs = 0x0074,
1534 .sysc_offs = 0x0078,
1535 .sysc_flags = SYSC_HAS_SIDLEMODE,
1536 .idlemodes = (SIDLE_FORCE | SIDLE_NO |
1537 SIDLE_SMART | SIDLE_SMART_WKUP),
1538 .sysc_fields = &omap_hwmod_sysc_type3,
1539 };
1540
1541 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
1542 .name = "rtc",
1543 .sysc = &am33xx_rtc_sysc,
1544 };
1545
1546 static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
1547 { .name = "rtcint", .irq = 75 + OMAP_INTC_START, },
1548 { .name = "rtcalarmint", .irq = 76 + OMAP_INTC_START, },
1549 { .irq = -1 },
1550 };
1551
1552 static struct omap_hwmod am33xx_rtc_hwmod = {
1553 .name = "rtc",
1554 .class = &am33xx_rtc_hwmod_class,
1555 .clkdm_name = "l4_rtc_clkdm",
1556 .mpu_irqs = am33xx_rtc_irqs,
1557 .main_clk = "clk_32768_ck",
1558 .prcm = {
1559 .omap4 = {
1560 .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
1561 .modulemode = MODULEMODE_SWCTRL,
1562 },
1563 },
1564 };
1565
1566 /* 'spi' class */
1567 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
1568 .rev_offs = 0x0000,
1569 .sysc_offs = 0x0110,
1570 .syss_offs = 0x0114,
1571 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1572 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1573 SYSS_HAS_RESET_STATUS),
1574 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1575 .sysc_fields = &omap_hwmod_sysc_type1,
1576 };
1577
1578 static struct omap_hwmod_class am33xx_spi_hwmod_class = {
1579 .name = "mcspi",
1580 .sysc = &am33xx_mcspi_sysc,
1581 .rev = OMAP4_MCSPI_REV,
1582 };
1583
1584 /* spi0 */
1585 static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
1586 { .irq = 65 + OMAP_INTC_START, },
1587 { .irq = -1 },
1588 };
1589
1590 static struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = {
1591 { .name = "rx0", .dma_req = 17 },
1592 { .name = "tx0", .dma_req = 16 },
1593 { .name = "rx1", .dma_req = 19 },
1594 { .name = "tx1", .dma_req = 18 },
1595 { .dma_req = -1 }
1596 };
1597
1598 static struct omap2_mcspi_dev_attr mcspi_attrib = {
1599 .num_chipselect = 2,
1600 };
1601 static struct omap_hwmod am33xx_spi0_hwmod = {
1602 .name = "spi0",
1603 .class = &am33xx_spi_hwmod_class,
1604 .clkdm_name = "l4ls_clkdm",
1605 .mpu_irqs = am33xx_spi0_irqs,
1606 .sdma_reqs = am33xx_mcspi0_edma_reqs,
1607 .main_clk = "dpll_per_m2_div4_ck",
1608 .prcm = {
1609 .omap4 = {
1610 .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
1611 .modulemode = MODULEMODE_SWCTRL,
1612 },
1613 },
1614 .dev_attr = &mcspi_attrib,
1615 };
1616
1617 /* spi1 */
1618 static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
1619 { .irq = 125 + OMAP_INTC_START, },
1620 { .irq = -1 },
1621 };
1622
1623 static struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = {
1624 { .name = "rx0", .dma_req = 43 },
1625 { .name = "tx0", .dma_req = 42 },
1626 { .name = "rx1", .dma_req = 45 },
1627 { .name = "tx1", .dma_req = 44 },
1628 { .dma_req = -1 }
1629 };
1630
1631 static struct omap_hwmod am33xx_spi1_hwmod = {
1632 .name = "spi1",
1633 .class = &am33xx_spi_hwmod_class,
1634 .clkdm_name = "l4ls_clkdm",
1635 .mpu_irqs = am33xx_spi1_irqs,
1636 .sdma_reqs = am33xx_mcspi1_edma_reqs,
1637 .main_clk = "dpll_per_m2_div4_ck",
1638 .prcm = {
1639 .omap4 = {
1640 .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
1641 .modulemode = MODULEMODE_SWCTRL,
1642 },
1643 },
1644 .dev_attr = &mcspi_attrib,
1645 };
1646
1647 /*
1648 * 'spinlock' class
1649 * spinlock provides hardware assistance for synchronizing the
1650 * processes running on multiple processors
1651 */
1652 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
1653 .name = "spinlock",
1654 };
1655
1656 static struct omap_hwmod am33xx_spinlock_hwmod = {
1657 .name = "spinlock",
1658 .class = &am33xx_spinlock_hwmod_class,
1659 .clkdm_name = "l4ls_clkdm",
1660 .main_clk = "l4ls_gclk",
1661 .prcm = {
1662 .omap4 = {
1663 .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
1664 .modulemode = MODULEMODE_SWCTRL,
1665 },
1666 },
1667 };
1668
1669 /* 'timer 2-7' class */
1670 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1671 .rev_offs = 0x0000,
1672 .sysc_offs = 0x0010,
1673 .syss_offs = 0x0014,
1674 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1675 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1676 SIDLE_SMART_WKUP),
1677 .sysc_fields = &omap_hwmod_sysc_type2,
1678 };
1679
1680 static struct omap_hwmod_class am33xx_timer_hwmod_class = {
1681 .name = "timer",
1682 .sysc = &am33xx_timer_sysc,
1683 };
1684
1685 /* timer1 1ms */
1686 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
1687 .rev_offs = 0x0000,
1688 .sysc_offs = 0x0010,
1689 .syss_offs = 0x0014,
1690 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1691 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1692 SYSS_HAS_RESET_STATUS),
1693 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1694 .sysc_fields = &omap_hwmod_sysc_type1,
1695 };
1696
1697 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
1698 .name = "timer",
1699 .sysc = &am33xx_timer1ms_sysc,
1700 };
1701
1702 static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
1703 { .irq = 67 + OMAP_INTC_START, },
1704 { .irq = -1 },
1705 };
1706
1707 static struct omap_hwmod am33xx_timer1_hwmod = {
1708 .name = "timer1",
1709 .class = &am33xx_timer1ms_hwmod_class,
1710 .clkdm_name = "l4_wkup_clkdm",
1711 .mpu_irqs = am33xx_timer1_irqs,
1712 .main_clk = "timer1_fck",
1713 .prcm = {
1714 .omap4 = {
1715 .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
1716 .modulemode = MODULEMODE_SWCTRL,
1717 },
1718 },
1719 };
1720
1721 static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
1722 { .irq = 68 + OMAP_INTC_START, },
1723 { .irq = -1 },
1724 };
1725
1726 static struct omap_hwmod am33xx_timer2_hwmod = {
1727 .name = "timer2",
1728 .class = &am33xx_timer_hwmod_class,
1729 .clkdm_name = "l4ls_clkdm",
1730 .mpu_irqs = am33xx_timer2_irqs,
1731 .main_clk = "timer2_fck",
1732 .prcm = {
1733 .omap4 = {
1734 .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
1735 .modulemode = MODULEMODE_SWCTRL,
1736 },
1737 },
1738 };
1739
1740 static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
1741 { .irq = 69 + OMAP_INTC_START, },
1742 { .irq = -1 },
1743 };
1744
1745 static struct omap_hwmod am33xx_timer3_hwmod = {
1746 .name = "timer3",
1747 .class = &am33xx_timer_hwmod_class,
1748 .clkdm_name = "l4ls_clkdm",
1749 .mpu_irqs = am33xx_timer3_irqs,
1750 .main_clk = "timer3_fck",
1751 .prcm = {
1752 .omap4 = {
1753 .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
1754 .modulemode = MODULEMODE_SWCTRL,
1755 },
1756 },
1757 };
1758
1759 static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
1760 { .irq = 92 + OMAP_INTC_START, },
1761 { .irq = -1 },
1762 };
1763
1764 static struct omap_hwmod am33xx_timer4_hwmod = {
1765 .name = "timer4",
1766 .class = &am33xx_timer_hwmod_class,
1767 .clkdm_name = "l4ls_clkdm",
1768 .mpu_irqs = am33xx_timer4_irqs,
1769 .main_clk = "timer4_fck",
1770 .prcm = {
1771 .omap4 = {
1772 .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
1773 .modulemode = MODULEMODE_SWCTRL,
1774 },
1775 },
1776 };
1777
1778 static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
1779 { .irq = 93 + OMAP_INTC_START, },
1780 { .irq = -1 },
1781 };
1782
1783 static struct omap_hwmod am33xx_timer5_hwmod = {
1784 .name = "timer5",
1785 .class = &am33xx_timer_hwmod_class,
1786 .clkdm_name = "l4ls_clkdm",
1787 .mpu_irqs = am33xx_timer5_irqs,
1788 .main_clk = "timer5_fck",
1789 .prcm = {
1790 .omap4 = {
1791 .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
1792 .modulemode = MODULEMODE_SWCTRL,
1793 },
1794 },
1795 };
1796
1797 static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
1798 { .irq = 94 + OMAP_INTC_START, },
1799 { .irq = -1 },
1800 };
1801
1802 static struct omap_hwmod am33xx_timer6_hwmod = {
1803 .name = "timer6",
1804 .class = &am33xx_timer_hwmod_class,
1805 .clkdm_name = "l4ls_clkdm",
1806 .mpu_irqs = am33xx_timer6_irqs,
1807 .main_clk = "timer6_fck",
1808 .prcm = {
1809 .omap4 = {
1810 .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
1811 .modulemode = MODULEMODE_SWCTRL,
1812 },
1813 },
1814 };
1815
1816 static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
1817 { .irq = 95 + OMAP_INTC_START, },
1818 { .irq = -1 },
1819 };
1820
1821 static struct omap_hwmod am33xx_timer7_hwmod = {
1822 .name = "timer7",
1823 .class = &am33xx_timer_hwmod_class,
1824 .clkdm_name = "l4ls_clkdm",
1825 .mpu_irqs = am33xx_timer7_irqs,
1826 .main_clk = "timer7_fck",
1827 .prcm = {
1828 .omap4 = {
1829 .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
1830 .modulemode = MODULEMODE_SWCTRL,
1831 },
1832 },
1833 };
1834
1835 /* tpcc */
1836 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1837 .name = "tpcc",
1838 };
1839
1840 static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
1841 { .name = "edma0", .irq = 12 + OMAP_INTC_START, },
1842 { .name = "edma0_mperr", .irq = 13 + OMAP_INTC_START, },
1843 { .name = "edma0_err", .irq = 14 + OMAP_INTC_START, },
1844 { .irq = -1 },
1845 };
1846
1847 static struct omap_hwmod am33xx_tpcc_hwmod = {
1848 .name = "tpcc",
1849 .class = &am33xx_tpcc_hwmod_class,
1850 .clkdm_name = "l3_clkdm",
1851 .mpu_irqs = am33xx_tpcc_irqs,
1852 .main_clk = "l3_gclk",
1853 .prcm = {
1854 .omap4 = {
1855 .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
1856 .modulemode = MODULEMODE_SWCTRL,
1857 },
1858 },
1859 };
1860
1861 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
1862 .rev_offs = 0x0,
1863 .sysc_offs = 0x10,
1864 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1865 SYSC_HAS_MIDLEMODE),
1866 .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
1867 .sysc_fields = &omap_hwmod_sysc_type2,
1868 };
1869
1870 /* 'tptc' class */
1871 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1872 .name = "tptc",
1873 .sysc = &am33xx_tptc_sysc,
1874 };
1875
1876 /* tptc0 */
1877 static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
1878 { .irq = 112 + OMAP_INTC_START, },
1879 { .irq = -1 },
1880 };
1881
1882 static struct omap_hwmod am33xx_tptc0_hwmod = {
1883 .name = "tptc0",
1884 .class = &am33xx_tptc_hwmod_class,
1885 .clkdm_name = "l3_clkdm",
1886 .mpu_irqs = am33xx_tptc0_irqs,
1887 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1888 .main_clk = "l3_gclk",
1889 .prcm = {
1890 .omap4 = {
1891 .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
1892 .modulemode = MODULEMODE_SWCTRL,
1893 },
1894 },
1895 };
1896
1897 /* tptc1 */
1898 static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
1899 { .irq = 113 + OMAP_INTC_START, },
1900 { .irq = -1 },
1901 };
1902
1903 static struct omap_hwmod am33xx_tptc1_hwmod = {
1904 .name = "tptc1",
1905 .class = &am33xx_tptc_hwmod_class,
1906 .clkdm_name = "l3_clkdm",
1907 .mpu_irqs = am33xx_tptc1_irqs,
1908 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1909 .main_clk = "l3_gclk",
1910 .prcm = {
1911 .omap4 = {
1912 .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
1913 .modulemode = MODULEMODE_SWCTRL,
1914 },
1915 },
1916 };
1917
1918 /* tptc2 */
1919 static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
1920 { .irq = 114 + OMAP_INTC_START, },
1921 { .irq = -1 },
1922 };
1923
1924 static struct omap_hwmod am33xx_tptc2_hwmod = {
1925 .name = "tptc2",
1926 .class = &am33xx_tptc_hwmod_class,
1927 .clkdm_name = "l3_clkdm",
1928 .mpu_irqs = am33xx_tptc2_irqs,
1929 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1930 .main_clk = "l3_gclk",
1931 .prcm = {
1932 .omap4 = {
1933 .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
1934 .modulemode = MODULEMODE_SWCTRL,
1935 },
1936 },
1937 };
1938
1939 /* 'uart' class */
1940 static struct omap_hwmod_class_sysconfig uart_sysc = {
1941 .rev_offs = 0x50,
1942 .sysc_offs = 0x54,
1943 .syss_offs = 0x58,
1944 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1945 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1946 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1947 SIDLE_SMART_WKUP),
1948 .sysc_fields = &omap_hwmod_sysc_type1,
1949 };
1950
1951 static struct omap_hwmod_class uart_class = {
1952 .name = "uart",
1953 .sysc = &uart_sysc,
1954 };
1955
1956 /* uart1 */
1957 static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
1958 { .name = "tx", .dma_req = 26, },
1959 { .name = "rx", .dma_req = 27, },
1960 { .dma_req = -1 }
1961 };
1962
1963 static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
1964 { .irq = 72 + OMAP_INTC_START, },
1965 { .irq = -1 },
1966 };
1967
1968 static struct omap_hwmod am33xx_uart1_hwmod = {
1969 .name = "uart1",
1970 .class = &uart_class,
1971 .clkdm_name = "l4_wkup_clkdm",
1972 .mpu_irqs = am33xx_uart1_irqs,
1973 .sdma_reqs = uart1_edma_reqs,
1974 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
1975 .prcm = {
1976 .omap4 = {
1977 .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
1978 .modulemode = MODULEMODE_SWCTRL,
1979 },
1980 },
1981 };
1982
1983 static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
1984 { .irq = 73 + OMAP_INTC_START, },
1985 { .irq = -1 },
1986 };
1987
1988 static struct omap_hwmod am33xx_uart2_hwmod = {
1989 .name = "uart2",
1990 .class = &uart_class,
1991 .clkdm_name = "l4ls_clkdm",
1992 .mpu_irqs = am33xx_uart2_irqs,
1993 .sdma_reqs = uart1_edma_reqs,
1994 .main_clk = "dpll_per_m2_div4_ck",
1995 .prcm = {
1996 .omap4 = {
1997 .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
1998 .modulemode = MODULEMODE_SWCTRL,
1999 },
2000 },
2001 };
2002
2003 /* uart3 */
2004 static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
2005 { .name = "tx", .dma_req = 30, },
2006 { .name = "rx", .dma_req = 31, },
2007 { .dma_req = -1 }
2008 };
2009
2010 static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
2011 { .irq = 74 + OMAP_INTC_START, },
2012 { .irq = -1 },
2013 };
2014
2015 static struct omap_hwmod am33xx_uart3_hwmod = {
2016 .name = "uart3",
2017 .class = &uart_class,
2018 .clkdm_name = "l4ls_clkdm",
2019 .mpu_irqs = am33xx_uart3_irqs,
2020 .sdma_reqs = uart3_edma_reqs,
2021 .main_clk = "dpll_per_m2_div4_ck",
2022 .prcm = {
2023 .omap4 = {
2024 .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
2025 .modulemode = MODULEMODE_SWCTRL,
2026 },
2027 },
2028 };
2029
2030 static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
2031 { .irq = 44 + OMAP_INTC_START, },
2032 { .irq = -1 },
2033 };
2034
2035 static struct omap_hwmod am33xx_uart4_hwmod = {
2036 .name = "uart4",
2037 .class = &uart_class,
2038 .clkdm_name = "l4ls_clkdm",
2039 .mpu_irqs = am33xx_uart4_irqs,
2040 .sdma_reqs = uart1_edma_reqs,
2041 .main_clk = "dpll_per_m2_div4_ck",
2042 .prcm = {
2043 .omap4 = {
2044 .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
2045 .modulemode = MODULEMODE_SWCTRL,
2046 },
2047 },
2048 };
2049
2050 static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
2051 { .irq = 45 + OMAP_INTC_START, },
2052 { .irq = -1 },
2053 };
2054
2055 static struct omap_hwmod am33xx_uart5_hwmod = {
2056 .name = "uart5",
2057 .class = &uart_class,
2058 .clkdm_name = "l4ls_clkdm",
2059 .mpu_irqs = am33xx_uart5_irqs,
2060 .sdma_reqs = uart1_edma_reqs,
2061 .main_clk = "dpll_per_m2_div4_ck",
2062 .prcm = {
2063 .omap4 = {
2064 .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
2065 .modulemode = MODULEMODE_SWCTRL,
2066 },
2067 },
2068 };
2069
2070 static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
2071 { .irq = 46 + OMAP_INTC_START, },
2072 { .irq = -1 },
2073 };
2074
2075 static struct omap_hwmod am33xx_uart6_hwmod = {
2076 .name = "uart6",
2077 .class = &uart_class,
2078 .clkdm_name = "l4ls_clkdm",
2079 .mpu_irqs = am33xx_uart6_irqs,
2080 .sdma_reqs = uart1_edma_reqs,
2081 .main_clk = "dpll_per_m2_div4_ck",
2082 .prcm = {
2083 .omap4 = {
2084 .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
2085 .modulemode = MODULEMODE_SWCTRL,
2086 },
2087 },
2088 };
2089
2090 /* 'wd_timer' class */
2091 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
2092 .name = "wd_timer",
2093 };
2094
2095 /*
2096 * XXX: device.c file uses hardcoded name for watchdog timer
2097 * driver "wd_timer2, so we are also using same name as of now...
2098 */
2099 static struct omap_hwmod am33xx_wd_timer1_hwmod = {
2100 .name = "wd_timer2",
2101 .class = &am33xx_wd_timer_hwmod_class,
2102 .clkdm_name = "l4_wkup_clkdm",
2103 .main_clk = "wdt1_fck",
2104 .prcm = {
2105 .omap4 = {
2106 .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
2107 .modulemode = MODULEMODE_SWCTRL,
2108 },
2109 },
2110 };
2111
2112 /*
2113 * 'usb_otg' class
2114 * high-speed on-the-go universal serial bus (usb_otg) controller
2115 */
2116 static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
2117 .rev_offs = 0x0,
2118 .sysc_offs = 0x10,
2119 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
2120 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2121 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2122 .sysc_fields = &omap_hwmod_sysc_type2,
2123 };
2124
2125 static struct omap_hwmod_class am33xx_usbotg_class = {
2126 .name = "usbotg",
2127 .sysc = &am33xx_usbhsotg_sysc,
2128 };
2129
2130 static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
2131 { .name = "usbss-irq", .irq = 17 + OMAP_INTC_START, },
2132 { .name = "musb0-irq", .irq = 18 + OMAP_INTC_START, },
2133 { .name = "musb1-irq", .irq = 19 + OMAP_INTC_START, },
2134 { .irq = -1, },
2135 };
2136
2137 static struct omap_hwmod am33xx_usbss_hwmod = {
2138 .name = "usb_otg_hs",
2139 .class = &am33xx_usbotg_class,
2140 .clkdm_name = "l3s_clkdm",
2141 .mpu_irqs = am33xx_usbss_mpu_irqs,
2142 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2143 .main_clk = "usbotg_fck",
2144 .prcm = {
2145 .omap4 = {
2146 .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
2147 .modulemode = MODULEMODE_SWCTRL,
2148 },
2149 },
2150 };
2151
2152
2153 /*
2154 * Interfaces
2155 */
2156
2157 /* l4 fw -> emif fw */
2158 static struct omap_hwmod_ocp_if am33xx_l4_fw__emif_fw = {
2159 .master = &am33xx_l4_fw_hwmod,
2160 .slave = &am33xx_emif_fw_hwmod,
2161 .clk = "l4fw_gclk",
2162 .user = OCP_USER_MPU,
2163 };
2164
2165 static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
2166 {
2167 .pa_start = 0x4c000000,
2168 .pa_end = 0x4c000fff,
2169 .flags = ADDR_TYPE_RT
2170 },
2171 { }
2172 };
2173 /* l3 main -> emif */
2174 static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
2175 .master = &am33xx_l3_main_hwmod,
2176 .slave = &am33xx_emif_hwmod,
2177 .clk = "dpll_core_m4_ck",
2178 .addr = am33xx_emif_addrs,
2179 .user = OCP_USER_MPU | OCP_USER_SDMA,
2180 };
2181
2182 /* mpu -> l3 main */
2183 static struct omap_hwmod_ocp_if am33xx_mpu__l3_main = {
2184 .master = &am33xx_mpu_hwmod,
2185 .slave = &am33xx_l3_main_hwmod,
2186 .clk = "dpll_mpu_m2_ck",
2187 .user = OCP_USER_MPU,
2188 };
2189
2190 /* l3 main -> l4 hs */
2191 static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
2192 .master = &am33xx_l3_main_hwmod,
2193 .slave = &am33xx_l4_hs_hwmod,
2194 .clk = "l3s_gclk",
2195 .user = OCP_USER_MPU | OCP_USER_SDMA,
2196 };
2197
2198 /* l3 main -> l3 s */
2199 static struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = {
2200 .master = &am33xx_l3_main_hwmod,
2201 .slave = &am33xx_l3_s_hwmod,
2202 .clk = "l3s_gclk",
2203 .user = OCP_USER_MPU | OCP_USER_SDMA,
2204 };
2205
2206 /* l3 s -> l4 per/ls */
2207 static struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = {
2208 .master = &am33xx_l3_s_hwmod,
2209 .slave = &am33xx_l4_ls_hwmod,
2210 .clk = "l3s_gclk",
2211 .user = OCP_USER_MPU | OCP_USER_SDMA,
2212 };
2213
2214 /* l3 s -> l4 wkup */
2215 static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
2216 .master = &am33xx_l3_s_hwmod,
2217 .slave = &am33xx_l4_wkup_hwmod,
2218 .clk = "l3s_gclk",
2219 .user = OCP_USER_MPU | OCP_USER_SDMA,
2220 };
2221
2222 /* l3 s -> l4 fw */
2223 static struct omap_hwmod_ocp_if am33xx_l3_s__l4_fw = {
2224 .master = &am33xx_l3_s_hwmod,
2225 .slave = &am33xx_l4_fw_hwmod,
2226 .clk = "l3s_gclk",
2227 .user = OCP_USER_MPU | OCP_USER_SDMA,
2228 };
2229
2230 /* l3 main -> l3 instr */
2231 static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
2232 .master = &am33xx_l3_main_hwmod,
2233 .slave = &am33xx_l3_instr_hwmod,
2234 .clk = "l3s_gclk",
2235 .user = OCP_USER_MPU | OCP_USER_SDMA,
2236 };
2237
2238 /* mpu -> prcm */
2239 static struct omap_hwmod_ocp_if am33xx_mpu__prcm = {
2240 .master = &am33xx_mpu_hwmod,
2241 .slave = &am33xx_prcm_hwmod,
2242 .clk = "dpll_mpu_m2_ck",
2243 .user = OCP_USER_MPU | OCP_USER_SDMA,
2244 };
2245
2246 /* l3 s -> l3 main*/
2247 static struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = {
2248 .master = &am33xx_l3_s_hwmod,
2249 .slave = &am33xx_l3_main_hwmod,
2250 .clk = "l3s_gclk",
2251 .user = OCP_USER_MPU | OCP_USER_SDMA,
2252 };
2253
2254 /* pru-icss -> l3 main */
2255 static struct omap_hwmod_ocp_if am33xx_pruss__l3_main = {
2256 .master = &am33xx_pruss_hwmod,
2257 .slave = &am33xx_l3_main_hwmod,
2258 .clk = "l3_gclk",
2259 .user = OCP_USER_MPU | OCP_USER_SDMA,
2260 };
2261
2262 /* wkup m3 -> l4 wkup */
2263 static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
2264 .master = &am33xx_wkup_m3_hwmod,
2265 .slave = &am33xx_l4_wkup_hwmod,
2266 .clk = "dpll_core_m4_div2_ck",
2267 .user = OCP_USER_MPU | OCP_USER_SDMA,
2268 };
2269
2270 /* gfx -> l3 main */
2271 static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
2272 .master = &am33xx_gfx_hwmod,
2273 .slave = &am33xx_l3_main_hwmod,
2274 .clk = "dpll_core_m4_ck",
2275 .user = OCP_USER_MPU | OCP_USER_SDMA,
2276 };
2277
2278 /* l4 wkup -> wkup m3 */
2279 static struct omap_hwmod_addr_space am33xx_wkup_m3_addrs[] = {
2280 {
2281 .name = "umem",
2282 .pa_start = 0x44d00000,
2283 .pa_end = 0x44d00000 + SZ_16K - 1,
2284 .flags = ADDR_TYPE_RT
2285 },
2286 {
2287 .name = "dmem",
2288 .pa_start = 0x44d80000,
2289 .pa_end = 0x44d80000 + SZ_8K - 1,
2290 .flags = ADDR_TYPE_RT
2291 },
2292 { }
2293 };
2294
2295 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
2296 .master = &am33xx_l4_wkup_hwmod,
2297 .slave = &am33xx_wkup_m3_hwmod,
2298 .clk = "dpll_core_m4_div2_ck",
2299 .addr = am33xx_wkup_m3_addrs,
2300 .user = OCP_USER_MPU | OCP_USER_SDMA,
2301 };
2302
2303 /* l4 hs -> pru-icss */
2304 static struct omap_hwmod_addr_space am33xx_pruss_addrs[] = {
2305 {
2306 .pa_start = 0x4a300000,
2307 .pa_end = 0x4a300000 + SZ_512K - 1,
2308 .flags = ADDR_TYPE_RT
2309 },
2310 { }
2311 };
2312
2313 static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
2314 .master = &am33xx_l4_hs_hwmod,
2315 .slave = &am33xx_pruss_hwmod,
2316 .clk = "dpll_core_m4_ck",
2317 .addr = am33xx_pruss_addrs,
2318 .user = OCP_USER_MPU | OCP_USER_SDMA,
2319 };
2320
2321 /* l3 main -> gfx */
2322 static struct omap_hwmod_addr_space am33xx_gfx_addrs[] = {
2323 {
2324 .pa_start = 0x56000000,
2325 .pa_end = 0x56000000 + SZ_16M - 1,
2326 .flags = ADDR_TYPE_RT
2327 },
2328 { }
2329 };
2330
2331 static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
2332 .master = &am33xx_l3_main_hwmod,
2333 .slave = &am33xx_gfx_hwmod,
2334 .clk = "dpll_core_m4_ck",
2335 .addr = am33xx_gfx_addrs,
2336 .user = OCP_USER_MPU | OCP_USER_SDMA,
2337 };
2338
2339 /* l4 wkup -> smartreflex0 */
2340 static struct omap_hwmod_addr_space am33xx_smartreflex0_addrs[] = {
2341 {
2342 .pa_start = 0x44e37000,
2343 .pa_end = 0x44e37000 + SZ_4K - 1,
2344 .flags = ADDR_TYPE_RT
2345 },
2346 { }
2347 };
2348
2349 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
2350 .master = &am33xx_l4_wkup_hwmod,
2351 .slave = &am33xx_smartreflex0_hwmod,
2352 .clk = "dpll_core_m4_div2_ck",
2353 .addr = am33xx_smartreflex0_addrs,
2354 .user = OCP_USER_MPU,
2355 };
2356
2357 /* l4 wkup -> smartreflex1 */
2358 static struct omap_hwmod_addr_space am33xx_smartreflex1_addrs[] = {
2359 {
2360 .pa_start = 0x44e39000,
2361 .pa_end = 0x44e39000 + SZ_4K - 1,
2362 .flags = ADDR_TYPE_RT
2363 },
2364 { }
2365 };
2366
2367 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
2368 .master = &am33xx_l4_wkup_hwmod,
2369 .slave = &am33xx_smartreflex1_hwmod,
2370 .clk = "dpll_core_m4_div2_ck",
2371 .addr = am33xx_smartreflex1_addrs,
2372 .user = OCP_USER_MPU,
2373 };
2374
2375 /* l4 wkup -> control */
2376 static struct omap_hwmod_addr_space am33xx_control_addrs[] = {
2377 {
2378 .pa_start = 0x44e10000,
2379 .pa_end = 0x44e10000 + SZ_8K - 1,
2380 .flags = ADDR_TYPE_RT
2381 },
2382 { }
2383 };
2384
2385 static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
2386 .master = &am33xx_l4_wkup_hwmod,
2387 .slave = &am33xx_control_hwmod,
2388 .clk = "dpll_core_m4_div2_ck",
2389 .addr = am33xx_control_addrs,
2390 .user = OCP_USER_MPU,
2391 };
2392
2393 /* l4 wkup -> rtc */
2394 static struct omap_hwmod_addr_space am33xx_rtc_addrs[] = {
2395 {
2396 .pa_start = 0x44e3e000,
2397 .pa_end = 0x44e3e000 + SZ_4K - 1,
2398 .flags = ADDR_TYPE_RT
2399 },
2400 { }
2401 };
2402
2403 static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
2404 .master = &am33xx_l4_wkup_hwmod,
2405 .slave = &am33xx_rtc_hwmod,
2406 .clk = "clkdiv32k_ick",
2407 .addr = am33xx_rtc_addrs,
2408 .user = OCP_USER_MPU,
2409 };
2410
2411 /* l4 per/ls -> DCAN0 */
2412 static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = {
2413 {
2414 .pa_start = 0x481CC000,
2415 .pa_end = 0x481CC000 + SZ_4K - 1,
2416 .flags = ADDR_TYPE_RT
2417 },
2418 { }
2419 };
2420
2421 static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
2422 .master = &am33xx_l4_ls_hwmod,
2423 .slave = &am33xx_dcan0_hwmod,
2424 .clk = "l4ls_gclk",
2425 .addr = am33xx_dcan0_addrs,
2426 .user = OCP_USER_MPU | OCP_USER_SDMA,
2427 };
2428
2429 /* l4 per/ls -> DCAN1 */
2430 static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = {
2431 {
2432 .pa_start = 0x481D0000,
2433 .pa_end = 0x481D0000 + SZ_4K - 1,
2434 .flags = ADDR_TYPE_RT
2435 },
2436 { }
2437 };
2438
2439 static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
2440 .master = &am33xx_l4_ls_hwmod,
2441 .slave = &am33xx_dcan1_hwmod,
2442 .clk = "l4ls_gclk",
2443 .addr = am33xx_dcan1_addrs,
2444 .user = OCP_USER_MPU | OCP_USER_SDMA,
2445 };
2446
2447 /* l4 per/ls -> GPIO2 */
2448 static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
2449 {
2450 .pa_start = 0x4804C000,
2451 .pa_end = 0x4804C000 + SZ_4K - 1,
2452 .flags = ADDR_TYPE_RT,
2453 },
2454 { }
2455 };
2456
2457 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
2458 .master = &am33xx_l4_ls_hwmod,
2459 .slave = &am33xx_gpio1_hwmod,
2460 .clk = "l4ls_gclk",
2461 .addr = am33xx_gpio1_addrs,
2462 .user = OCP_USER_MPU | OCP_USER_SDMA,
2463 };
2464
2465 /* l4 per/ls -> gpio3 */
2466 static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
2467 {
2468 .pa_start = 0x481AC000,
2469 .pa_end = 0x481AC000 + SZ_4K - 1,
2470 .flags = ADDR_TYPE_RT,
2471 },
2472 { }
2473 };
2474
2475 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
2476 .master = &am33xx_l4_ls_hwmod,
2477 .slave = &am33xx_gpio2_hwmod,
2478 .clk = "l4ls_gclk",
2479 .addr = am33xx_gpio2_addrs,
2480 .user = OCP_USER_MPU | OCP_USER_SDMA,
2481 };
2482
2483 /* l4 per/ls -> gpio4 */
2484 static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
2485 {
2486 .pa_start = 0x481AE000,
2487 .pa_end = 0x481AE000 + SZ_4K - 1,
2488 .flags = ADDR_TYPE_RT,
2489 },
2490 { }
2491 };
2492
2493 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
2494 .master = &am33xx_l4_ls_hwmod,
2495 .slave = &am33xx_gpio3_hwmod,
2496 .clk = "l4ls_gclk",
2497 .addr = am33xx_gpio3_addrs,
2498 .user = OCP_USER_MPU | OCP_USER_SDMA,
2499 };
2500
2501 /* L4 WKUP -> I2C1 */
2502 static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
2503 {
2504 .pa_start = 0x44E0B000,
2505 .pa_end = 0x44E0B000 + SZ_4K - 1,
2506 .flags = ADDR_TYPE_RT,
2507 },
2508 { }
2509 };
2510
2511 static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
2512 .master = &am33xx_l4_wkup_hwmod,
2513 .slave = &am33xx_i2c1_hwmod,
2514 .clk = "dpll_core_m4_div2_ck",
2515 .addr = am33xx_i2c1_addr_space,
2516 .user = OCP_USER_MPU,
2517 };
2518
2519 /* L4 WKUP -> GPIO1 */
2520 static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
2521 {
2522 .pa_start = 0x44E07000,
2523 .pa_end = 0x44E07000 + SZ_4K - 1,
2524 .flags = ADDR_TYPE_RT,
2525 },
2526 { }
2527 };
2528
2529 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
2530 .master = &am33xx_l4_wkup_hwmod,
2531 .slave = &am33xx_gpio0_hwmod,
2532 .clk = "dpll_core_m4_div2_ck",
2533 .addr = am33xx_gpio0_addrs,
2534 .user = OCP_USER_MPU | OCP_USER_SDMA,
2535 };
2536
2537 /* L4 WKUP -> ADC_TSC */
2538 static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
2539 {
2540 .pa_start = 0x44E0D000,
2541 .pa_end = 0x44E0D000 + SZ_8K - 1,
2542 .flags = ADDR_TYPE_RT
2543 },
2544 { }
2545 };
2546
2547 static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
2548 .master = &am33xx_l4_wkup_hwmod,
2549 .slave = &am33xx_adc_tsc_hwmod,
2550 .clk = "dpll_core_m4_div2_ck",
2551 .addr = am33xx_adc_tsc_addrs,
2552 .user = OCP_USER_MPU,
2553 };
2554
2555 static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
2556 /* cpsw ss */
2557 {
2558 .pa_start = 0x4a100000,
2559 .pa_end = 0x4a100000 + SZ_2K - 1,
2560 },
2561 /* cpsw wr */
2562 {
2563 .pa_start = 0x4a101200,
2564 .pa_end = 0x4a101200 + SZ_256 - 1,
2565 .flags = ADDR_TYPE_RT,
2566 },
2567 { }
2568 };
2569
2570 static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
2571 .master = &am33xx_l4_hs_hwmod,
2572 .slave = &am33xx_cpgmac0_hwmod,
2573 .clk = "cpsw_125mhz_gclk",
2574 .addr = am33xx_cpgmac0_addr_space,
2575 .user = OCP_USER_MPU,
2576 };
2577
2578 static struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
2579 {
2580 .pa_start = 0x4A101000,
2581 .pa_end = 0x4A101000 + SZ_256 - 1,
2582 },
2583 { }
2584 };
2585
2586 static struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
2587 .master = &am33xx_cpgmac0_hwmod,
2588 .slave = &am33xx_mdio_hwmod,
2589 .addr = am33xx_mdio_addr_space,
2590 .user = OCP_USER_MPU,
2591 };
2592
2593 static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
2594 {
2595 .pa_start = 0x48080000,
2596 .pa_end = 0x48080000 + SZ_8K - 1,
2597 .flags = ADDR_TYPE_RT
2598 },
2599 { }
2600 };
2601
2602 static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
2603 .master = &am33xx_l4_ls_hwmod,
2604 .slave = &am33xx_elm_hwmod,
2605 .clk = "l4ls_gclk",
2606 .addr = am33xx_elm_addr_space,
2607 .user = OCP_USER_MPU,
2608 };
2609
2610 /*
2611 * Splitting the resources to handle access of PWMSS config space
2612 * and module specific part independently
2613 */
2614 static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
2615 {
2616 .pa_start = 0x48300000,
2617 .pa_end = 0x48300000 + SZ_16 - 1,
2618 .flags = ADDR_TYPE_RT
2619 },
2620 {
2621 .pa_start = 0x48300200,
2622 .pa_end = 0x48300200 + SZ_128 - 1,
2623 },
2624 { }
2625 };
2626
2627 static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm0 = {
2628 .master = &am33xx_l4_ls_hwmod,
2629 .slave = &am33xx_ehrpwm0_hwmod,
2630 .clk = "l4ls_gclk",
2631 .addr = am33xx_ehrpwm0_addr_space,
2632 .user = OCP_USER_MPU,
2633 };
2634
2635 /*
2636 * Splitting the resources to handle access of PWMSS config space
2637 * and module specific part independently
2638 */
2639 static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
2640 {
2641 .pa_start = 0x48302000,
2642 .pa_end = 0x48302000 + SZ_16 - 1,
2643 .flags = ADDR_TYPE_RT
2644 },
2645 {
2646 .pa_start = 0x48302200,
2647 .pa_end = 0x48302200 + SZ_128 - 1,
2648 },
2649 { }
2650 };
2651
2652 static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm1 = {
2653 .master = &am33xx_l4_ls_hwmod,
2654 .slave = &am33xx_ehrpwm1_hwmod,
2655 .clk = "l4ls_gclk",
2656 .addr = am33xx_ehrpwm1_addr_space,
2657 .user = OCP_USER_MPU,
2658 };
2659
2660 /*
2661 * Splitting the resources to handle access of PWMSS config space
2662 * and module specific part independently
2663 */
2664 static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
2665 {
2666 .pa_start = 0x48304000,
2667 .pa_end = 0x48304000 + SZ_16 - 1,
2668 .flags = ADDR_TYPE_RT
2669 },
2670 {
2671 .pa_start = 0x48304200,
2672 .pa_end = 0x48304200 + SZ_128 - 1,
2673 },
2674 { }
2675 };
2676
2677 static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm2 = {
2678 .master = &am33xx_l4_ls_hwmod,
2679 .slave = &am33xx_ehrpwm2_hwmod,
2680 .clk = "l4ls_gclk",
2681 .addr = am33xx_ehrpwm2_addr_space,
2682 .user = OCP_USER_MPU,
2683 };
2684
2685 /*
2686 * Splitting the resources to handle access of PWMSS config space
2687 * and module specific part independently
2688 */
2689 static struct omap_hwmod_addr_space am33xx_eqep0_addr_space[] = {
2690 {
2691 .pa_start = 0x48300000,
2692 .pa_end = 0x48300000 + SZ_16 - 1,
2693 .flags = ADDR_TYPE_RT
2694 },
2695 {
2696 .pa_start = 0x48300180,
2697 .pa_end = 0x48300180 + SZ_128 - 1,
2698 },
2699 { }
2700 };
2701
2702 static struct omap_hwmod_ocp_if am33xx_l4_ls__eqep0 = {
2703 .master = &am33xx_l4_ls_hwmod,
2704 .slave = &am33xx_eqep0_hwmod,
2705 .clk = "l4ls_gclk",
2706 .addr = am33xx_eqep0_addr_space,
2707 .user = OCP_USER_MPU,
2708 };
2709
2710 /*
2711 * Splitting the resources to handle access of PWMSS config space
2712 * and module specific part independently
2713 */
2714 static struct omap_hwmod_addr_space am33xx_eqep1_addr_space[] = {
2715 {
2716 .pa_start = 0x48302000,
2717 .pa_end = 0x48302000 + SZ_16 - 1,
2718 .flags = ADDR_TYPE_RT
2719 },
2720 {
2721 .pa_start = 0x48302180,
2722 .pa_end = 0x48302180 + SZ_128 - 1,
2723 },
2724 { }
2725 };
2726
2727 static struct omap_hwmod_ocp_if am33xx_l4_ls__eqep1 = {
2728 .master = &am33xx_l4_ls_hwmod,
2729 .slave = &am33xx_eqep1_hwmod,
2730 .clk = "l4ls_gclk",
2731 .addr = am33xx_eqep1_addr_space,
2732 .user = OCP_USER_MPU,
2733 };
2734
2735 /*
2736 * Splitting the resources to handle access of PWMSS config space
2737 * and module specific part independently
2738 */
2739 static struct omap_hwmod_addr_space am33xx_eqep2_addr_space[] = {
2740 {
2741 .pa_start = 0x48304000,
2742 .pa_end = 0x48304000 + SZ_16 - 1,
2743 .flags = ADDR_TYPE_RT
2744 },
2745 {
2746 .pa_start = 0x48304180,
2747 .pa_end = 0x48304180 + SZ_128 - 1,
2748 },
2749 { }
2750 };
2751
2752 static struct omap_hwmod_ocp_if am33xx_l4_ls__eqep2 = {
2753 .master = &am33xx_l4_ls_hwmod,
2754 .slave = &am33xx_eqep2_hwmod,
2755 .clk = "l4ls_gclk",
2756 .addr = am33xx_eqep2_addr_space,
2757 .user = OCP_USER_MPU,
2758 };
2759
2760 /*
2761 * Splitting the resources to handle access of PWMSS config space
2762 * and module specific part independently
2763 */
2764 static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
2765 {
2766 .pa_start = 0x48300000,
2767 .pa_end = 0x48300000 + SZ_16 - 1,
2768 .flags = ADDR_TYPE_RT
2769 },
2770 {
2771 .pa_start = 0x48300100,
2772 .pa_end = 0x48300100 + SZ_128 - 1,
2773 },
2774 { }
2775 };
2776
2777 static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap0 = {
2778 .master = &am33xx_l4_ls_hwmod,
2779 .slave = &am33xx_ecap0_hwmod,
2780 .clk = "l4ls_gclk",
2781 .addr = am33xx_ecap0_addr_space,
2782 .user = OCP_USER_MPU,
2783 };
2784
2785 /*
2786 * Splitting the resources to handle access of PWMSS config space
2787 * and module specific part independently
2788 */
2789 static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
2790 {
2791 .pa_start = 0x48302000,
2792 .pa_end = 0x48302000 + SZ_16 - 1,
2793 .flags = ADDR_TYPE_RT
2794 },
2795 {
2796 .pa_start = 0x48302100,
2797 .pa_end = 0x48302100 + SZ_128 - 1,
2798 },
2799 { }
2800 };
2801
2802 static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap1 = {
2803 .master = &am33xx_l4_ls_hwmod,
2804 .slave = &am33xx_ecap1_hwmod,
2805 .clk = "l4ls_gclk",
2806 .addr = am33xx_ecap1_addr_space,
2807 .user = OCP_USER_MPU,
2808 };
2809
2810 /*
2811 * Splitting the resources to handle access of PWMSS config space
2812 * and module specific part independently
2813 */
2814 static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
2815 {
2816 .pa_start = 0x48304000,
2817 .pa_end = 0x48304000 + SZ_16 - 1,
2818 .flags = ADDR_TYPE_RT
2819 },
2820 {
2821 .pa_start = 0x48304100,
2822 .pa_end = 0x48304100 + SZ_128 - 1,
2823 },
2824 { }
2825 };
2826
2827 static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap2 = {
2828 .master = &am33xx_l4_ls_hwmod,
2829 .slave = &am33xx_ecap2_hwmod,
2830 .clk = "l4ls_gclk",
2831 .addr = am33xx_ecap2_addr_space,
2832 .user = OCP_USER_MPU,
2833 };
2834
2835 /* l3s cfg -> gpmc */
2836 static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
2837 {
2838 .pa_start = 0x50000000,
2839 .pa_end = 0x50000000 + SZ_8K - 1,
2840 .flags = ADDR_TYPE_RT,
2841 },
2842 { }
2843 };
2844
2845 static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
2846 .master = &am33xx_l3_s_hwmod,
2847 .slave = &am33xx_gpmc_hwmod,
2848 .clk = "l3s_gclk",
2849 .addr = am33xx_gpmc_addr_space,
2850 .user = OCP_USER_MPU,
2851 };
2852
2853 /* i2c2 */
2854 static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
2855 {
2856 .pa_start = 0x4802A000,
2857 .pa_end = 0x4802A000 + SZ_4K - 1,
2858 .flags = ADDR_TYPE_RT,
2859 },
2860 { }
2861 };
2862
2863 static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
2864 .master = &am33xx_l4_ls_hwmod,
2865 .slave = &am33xx_i2c2_hwmod,
2866 .clk = "l4ls_gclk",
2867 .addr = am33xx_i2c2_addr_space,
2868 .user = OCP_USER_MPU,
2869 };
2870
2871 static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
2872 {
2873 .pa_start = 0x4819C000,
2874 .pa_end = 0x4819C000 + SZ_4K - 1,
2875 .flags = ADDR_TYPE_RT
2876 },
2877 { }
2878 };
2879
2880 static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
2881 .master = &am33xx_l4_ls_hwmod,
2882 .slave = &am33xx_i2c3_hwmod,
2883 .clk = "l4ls_gclk",
2884 .addr = am33xx_i2c3_addr_space,
2885 .user = OCP_USER_MPU,
2886 };
2887
2888 static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
2889 {
2890 .pa_start = 0x4830E000,
2891 .pa_end = 0x4830E000 + SZ_8K - 1,
2892 .flags = ADDR_TYPE_RT,
2893 },
2894 { }
2895 };
2896
2897 static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
2898 .master = &am33xx_l3_main_hwmod,
2899 .slave = &am33xx_lcdc_hwmod,
2900 .clk = "dpll_core_m4_ck",
2901 .addr = am33xx_lcdc_addr_space,
2902 .user = OCP_USER_MPU,
2903 };
2904
2905 static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
2906 {
2907 .pa_start = 0x480C8000,
2908 .pa_end = 0x480C8000 + (SZ_4K - 1),
2909 .flags = ADDR_TYPE_RT
2910 },
2911 { }
2912 };
2913
2914 /* l4 ls -> mailbox */
2915 static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
2916 .master = &am33xx_l4_ls_hwmod,
2917 .slave = &am33xx_mailbox_hwmod,
2918 .clk = "l4ls_gclk",
2919 .addr = am33xx_mailbox_addrs,
2920 .user = OCP_USER_MPU,
2921 };
2922
2923 /* l4 ls -> spinlock */
2924 static struct omap_hwmod_addr_space am33xx_spinlock_addrs[] = {
2925 {
2926 .pa_start = 0x480Ca000,
2927 .pa_end = 0x480Ca000 + SZ_4K - 1,
2928 .flags = ADDR_TYPE_RT
2929 },
2930 { }
2931 };
2932
2933 static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
2934 .master = &am33xx_l4_ls_hwmod,
2935 .slave = &am33xx_spinlock_hwmod,
2936 .clk = "l4ls_gclk",
2937 .addr = am33xx_spinlock_addrs,
2938 .user = OCP_USER_MPU,
2939 };
2940
2941 /* l4 ls -> mcasp0 */
2942 static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
2943 {
2944 .pa_start = 0x48038000,
2945 .pa_end = 0x48038000 + SZ_8K - 1,
2946 .flags = ADDR_TYPE_RT
2947 },
2948 { }
2949 };
2950
2951 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
2952 .master = &am33xx_l4_ls_hwmod,
2953 .slave = &am33xx_mcasp0_hwmod,
2954 .clk = "l4ls_gclk",
2955 .addr = am33xx_mcasp0_addr_space,
2956 .user = OCP_USER_MPU,
2957 };
2958
2959 /* l3 s -> mcasp0 data */
2960 static struct omap_hwmod_addr_space am33xx_mcasp0_data_addr_space[] = {
2961 {
2962 .pa_start = 0x46000000,
2963 .pa_end = 0x46000000 + SZ_4M - 1,
2964 .flags = ADDR_TYPE_RT
2965 },
2966 { }
2967 };
2968
2969 static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp0_data = {
2970 .master = &am33xx_l3_s_hwmod,
2971 .slave = &am33xx_mcasp0_hwmod,
2972 .clk = "l3s_gclk",
2973 .addr = am33xx_mcasp0_data_addr_space,
2974 .user = OCP_USER_SDMA,
2975 };
2976
2977 /* l4 ls -> mcasp1 */
2978 static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
2979 {
2980 .pa_start = 0x4803C000,
2981 .pa_end = 0x4803C000 + SZ_8K - 1,
2982 .flags = ADDR_TYPE_RT
2983 },
2984 { }
2985 };
2986
2987 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
2988 .master = &am33xx_l4_ls_hwmod,
2989 .slave = &am33xx_mcasp1_hwmod,
2990 .clk = "l4ls_gclk",
2991 .addr = am33xx_mcasp1_addr_space,
2992 .user = OCP_USER_MPU,
2993 };
2994
2995 /* l3 s -> mcasp1 data */
2996 static struct omap_hwmod_addr_space am33xx_mcasp1_data_addr_space[] = {
2997 {
2998 .pa_start = 0x46400000,
2999 .pa_end = 0x46400000 + SZ_4M - 1,
3000 .flags = ADDR_TYPE_RT
3001 },
3002 { }
3003 };
3004
3005 static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp1_data = {
3006 .master = &am33xx_l3_s_hwmod,
3007 .slave = &am33xx_mcasp1_hwmod,
3008 .clk = "l3s_gclk",
3009 .addr = am33xx_mcasp1_data_addr_space,
3010 .user = OCP_USER_SDMA,
3011 };
3012
3013 /* l4 ls -> mmc0 */
3014 static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
3015 {
3016 .pa_start = 0x48060100,
3017 .pa_end = 0x48060100 + SZ_4K - 1,
3018 .flags = ADDR_TYPE_RT,
3019 },
3020 { }
3021 };
3022
3023 static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = {
3024 .master = &am33xx_l4_ls_hwmod,
3025 .slave = &am33xx_mmc0_hwmod,
3026 .clk = "l4ls_gclk",
3027 .addr = am33xx_mmc0_addr_space,
3028 .user = OCP_USER_MPU,
3029 };
3030
3031 /* l4 ls -> mmc1 */
3032 static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
3033 {
3034 .pa_start = 0x481d8100,
3035 .pa_end = 0x481d8100 + SZ_4K - 1,
3036 .flags = ADDR_TYPE_RT,
3037 },
3038 { }
3039 };
3040
3041 static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = {
3042 .master = &am33xx_l4_ls_hwmod,
3043 .slave = &am33xx_mmc1_hwmod,
3044 .clk = "l4ls_gclk",
3045 .addr = am33xx_mmc1_addr_space,
3046 .user = OCP_USER_MPU,
3047 };
3048
3049 /* l3 s -> mmc2 */
3050 static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
3051 {
3052 .pa_start = 0x47810100,
3053 .pa_end = 0x47810100 + SZ_64K - 1,
3054 .flags = ADDR_TYPE_RT,
3055 },
3056 { }
3057 };
3058
3059 static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
3060 .master = &am33xx_l3_s_hwmod,
3061 .slave = &am33xx_mmc2_hwmod,
3062 .clk = "l3s_gclk",
3063 .addr = am33xx_mmc2_addr_space,
3064 .user = OCP_USER_MPU,
3065 };
3066
3067 /* l4 ls -> mcspi0 */
3068 static struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
3069 {
3070 .pa_start = 0x48030000,
3071 .pa_end = 0x48030000 + SZ_1K - 1,
3072 .flags = ADDR_TYPE_RT,
3073 },
3074 { }
3075 };
3076
3077 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
3078 .master = &am33xx_l4_ls_hwmod,
3079 .slave = &am33xx_spi0_hwmod,
3080 .clk = "l4ls_gclk",
3081 .addr = am33xx_mcspi0_addr_space,
3082 .user = OCP_USER_MPU,
3083 };
3084
3085 /* l4 ls -> mcspi1 */
3086 static struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
3087 {
3088 .pa_start = 0x481A0000,
3089 .pa_end = 0x481A0000 + SZ_1K - 1,
3090 .flags = ADDR_TYPE_RT,
3091 },
3092 { }
3093 };
3094
3095 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
3096 .master = &am33xx_l4_ls_hwmod,
3097 .slave = &am33xx_spi1_hwmod,
3098 .clk = "l4ls_gclk",
3099 .addr = am33xx_mcspi1_addr_space,
3100 .user = OCP_USER_MPU,
3101 };
3102
3103 /* l4 wkup -> timer1 */
3104 static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
3105 {
3106 .pa_start = 0x44E31000,
3107 .pa_end = 0x44E31000 + SZ_1K - 1,
3108 .flags = ADDR_TYPE_RT
3109 },
3110 { }
3111 };
3112
3113 static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
3114 .master = &am33xx_l4_wkup_hwmod,
3115 .slave = &am33xx_timer1_hwmod,
3116 .clk = "dpll_core_m4_div2_ck",
3117 .addr = am33xx_timer1_addr_space,
3118 .user = OCP_USER_MPU,
3119 };
3120
3121 /* l4 per -> timer2 */
3122 static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
3123 {
3124 .pa_start = 0x48040000,
3125 .pa_end = 0x48040000 + SZ_1K - 1,
3126 .flags = ADDR_TYPE_RT
3127 },
3128 { }
3129 };
3130
3131 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
3132 .master = &am33xx_l4_ls_hwmod,
3133 .slave = &am33xx_timer2_hwmod,
3134 .clk = "l4ls_gclk",
3135 .addr = am33xx_timer2_addr_space,
3136 .user = OCP_USER_MPU,
3137 };
3138
3139 /* l4 per -> timer3 */
3140 static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
3141 {
3142 .pa_start = 0x48042000,
3143 .pa_end = 0x48042000 + SZ_1K - 1,
3144 .flags = ADDR_TYPE_RT
3145 },
3146 { }
3147 };
3148
3149 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
3150 .master = &am33xx_l4_ls_hwmod,
3151 .slave = &am33xx_timer3_hwmod,
3152 .clk = "l4ls_gclk",
3153 .addr = am33xx_timer3_addr_space,
3154 .user = OCP_USER_MPU,
3155 };
3156
3157 /* l4 per -> timer4 */
3158 static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
3159 {
3160 .pa_start = 0x48044000,
3161 .pa_end = 0x48044000 + SZ_1K - 1,
3162 .flags = ADDR_TYPE_RT
3163 },
3164 { }
3165 };
3166
3167 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
3168 .master = &am33xx_l4_ls_hwmod,
3169 .slave = &am33xx_timer4_hwmod,
3170 .clk = "l4ls_gclk",
3171 .addr = am33xx_timer4_addr_space,
3172 .user = OCP_USER_MPU,
3173 };
3174
3175 /* l4 per -> timer5 */
3176 static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
3177 {
3178 .pa_start = 0x48046000,
3179 .pa_end = 0x48046000 + SZ_1K - 1,
3180 .flags = ADDR_TYPE_RT
3181 },
3182 { }
3183 };
3184
3185 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
3186 .master = &am33xx_l4_ls_hwmod,
3187 .slave = &am33xx_timer5_hwmod,
3188 .clk = "l4ls_gclk",
3189 .addr = am33xx_timer5_addr_space,
3190 .user = OCP_USER_MPU,
3191 };
3192
3193 /* l4 per -> timer6 */
3194 static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
3195 {
3196 .pa_start = 0x48048000,
3197 .pa_end = 0x48048000 + SZ_1K - 1,
3198 .flags = ADDR_TYPE_RT
3199 },
3200 { }
3201 };
3202
3203 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
3204 .master = &am33xx_l4_ls_hwmod,
3205 .slave = &am33xx_timer6_hwmod,
3206 .clk = "l4ls_gclk",
3207 .addr = am33xx_timer6_addr_space,
3208 .user = OCP_USER_MPU,
3209 };
3210
3211 /* l4 per -> timer7 */
3212 static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
3213 {
3214 .pa_start = 0x4804A000,
3215 .pa_end = 0x4804A000 + SZ_1K - 1,
3216 .flags = ADDR_TYPE_RT
3217 },
3218 { }
3219 };
3220
3221 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
3222 .master = &am33xx_l4_ls_hwmod,
3223 .slave = &am33xx_timer7_hwmod,
3224 .clk = "l4ls_gclk",
3225 .addr = am33xx_timer7_addr_space,
3226 .user = OCP_USER_MPU,
3227 };
3228
3229 /* l3 main -> tpcc */
3230 static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
3231 {
3232 .pa_start = 0x49000000,
3233 .pa_end = 0x49000000 + SZ_32K - 1,
3234 .flags = ADDR_TYPE_RT
3235 },
3236 { }
3237 };
3238
3239 static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
3240 .master = &am33xx_l3_main_hwmod,
3241 .slave = &am33xx_tpcc_hwmod,
3242 .clk = "l3_gclk",
3243 .addr = am33xx_tpcc_addr_space,
3244 .user = OCP_USER_MPU,
3245 };
3246
3247 /* l3 main -> tpcc0 */
3248 static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
3249 {
3250 .pa_start = 0x49800000,
3251 .pa_end = 0x49800000 + SZ_8K - 1,
3252 .flags = ADDR_TYPE_RT,
3253 },
3254 { }
3255 };
3256
3257 static struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
3258 .master = &am33xx_l3_main_hwmod,
3259 .slave = &am33xx_tptc0_hwmod,
3260 .clk = "l3_gclk",
3261 .addr = am33xx_tptc0_addr_space,
3262 .user = OCP_USER_MPU,
3263 };
3264
3265 /* l3 main -> tpcc1 */
3266 static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
3267 {
3268 .pa_start = 0x49900000,
3269 .pa_end = 0x49900000 + SZ_8K - 1,
3270 .flags = ADDR_TYPE_RT,
3271 },
3272 { }
3273 };
3274
3275 static struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
3276 .master = &am33xx_l3_main_hwmod,
3277 .slave = &am33xx_tptc1_hwmod,
3278 .clk = "l3_gclk",
3279 .addr = am33xx_tptc1_addr_space,
3280 .user = OCP_USER_MPU,
3281 };
3282
3283 /* l3 main -> tpcc2 */
3284 static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
3285 {
3286 .pa_start = 0x49a00000,
3287 .pa_end = 0x49a00000 + SZ_8K - 1,
3288 .flags = ADDR_TYPE_RT,
3289 },
3290 { }
3291 };
3292
3293 static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
3294 .master = &am33xx_l3_main_hwmod,
3295 .slave = &am33xx_tptc2_hwmod,
3296 .clk = "l3_gclk",
3297 .addr = am33xx_tptc2_addr_space,
3298 .user = OCP_USER_MPU,
3299 };
3300
3301 /* l4 wkup -> uart1 */
3302 static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
3303 {
3304 .pa_start = 0x44E09000,
3305 .pa_end = 0x44E09000 + SZ_8K - 1,
3306 .flags = ADDR_TYPE_RT,
3307 },
3308 { }
3309 };
3310
3311 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
3312 .master = &am33xx_l4_wkup_hwmod,
3313 .slave = &am33xx_uart1_hwmod,
3314 .clk = "dpll_core_m4_div2_ck",
3315 .addr = am33xx_uart1_addr_space,
3316 .user = OCP_USER_MPU,
3317 };
3318
3319 /* l4 ls -> uart2 */
3320 static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
3321 {
3322 .pa_start = 0x48022000,
3323 .pa_end = 0x48022000 + SZ_8K - 1,
3324 .flags = ADDR_TYPE_RT,
3325 },
3326 { }
3327 };
3328
3329 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
3330 .master = &am33xx_l4_ls_hwmod,
3331 .slave = &am33xx_uart2_hwmod,
3332 .clk = "l4ls_gclk",
3333 .addr = am33xx_uart2_addr_space,
3334 .user = OCP_USER_MPU,
3335 };
3336
3337 /* l4 ls -> uart3 */
3338 static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
3339 {
3340 .pa_start = 0x48024000,
3341 .pa_end = 0x48024000 + SZ_8K - 1,
3342 .flags = ADDR_TYPE_RT,
3343 },
3344 { }
3345 };
3346
3347 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
3348 .master = &am33xx_l4_ls_hwmod,
3349 .slave = &am33xx_uart3_hwmod,
3350 .clk = "l4ls_gclk",
3351 .addr = am33xx_uart3_addr_space,
3352 .user = OCP_USER_MPU,
3353 };
3354
3355 /* l4 ls -> uart4 */
3356 static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
3357 {
3358 .pa_start = 0x481A6000,
3359 .pa_end = 0x481A6000 + SZ_8K - 1,
3360 .flags = ADDR_TYPE_RT,
3361 },
3362 { }
3363 };
3364
3365 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
3366 .master = &am33xx_l4_ls_hwmod,
3367 .slave = &am33xx_uart4_hwmod,
3368 .clk = "l4ls_gclk",
3369 .addr = am33xx_uart4_addr_space,
3370 .user = OCP_USER_MPU,
3371 };
3372
3373 /* l4 ls -> uart5 */
3374 static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
3375 {
3376 .pa_start = 0x481A8000,
3377 .pa_end = 0x481A8000 + SZ_8K - 1,
3378 .flags = ADDR_TYPE_RT,
3379 },
3380 { }
3381 };
3382
3383 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
3384 .master = &am33xx_l4_ls_hwmod,
3385 .slave = &am33xx_uart5_hwmod,
3386 .clk = "l4ls_gclk",
3387 .addr = am33xx_uart5_addr_space,
3388 .user = OCP_USER_MPU,
3389 };
3390
3391 /* l4 ls -> uart6 */
3392 static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
3393 {
3394 .pa_start = 0x481aa000,
3395 .pa_end = 0x481aa000 + SZ_8K - 1,
3396 .flags = ADDR_TYPE_RT,
3397 },
3398 { }
3399 };
3400
3401 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
3402 .master = &am33xx_l4_ls_hwmod,
3403 .slave = &am33xx_uart6_hwmod,
3404 .clk = "l4ls_gclk",
3405 .addr = am33xx_uart6_addr_space,
3406 .user = OCP_USER_MPU,
3407 };
3408
3409 /* l4 wkup -> wd_timer1 */
3410 static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
3411 {
3412 .pa_start = 0x44e35000,
3413 .pa_end = 0x44e35000 + SZ_4K - 1,
3414 .flags = ADDR_TYPE_RT
3415 },
3416 { }
3417 };
3418
3419 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
3420 .master = &am33xx_l4_wkup_hwmod,
3421 .slave = &am33xx_wd_timer1_hwmod,
3422 .clk = "dpll_core_m4_div2_ck",
3423 .addr = am33xx_wd_timer1_addrs,
3424 .user = OCP_USER_MPU,
3425 };
3426
3427 /* usbss */
3428 /* l3 s -> USBSS interface */
3429 static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
3430 {
3431 .name = "usbss",
3432 .pa_start = 0x47400000,
3433 .pa_end = 0x47400000 + SZ_4K - 1,
3434 .flags = ADDR_TYPE_RT
3435 },
3436 {
3437 .name = "musb0",
3438 .pa_start = 0x47401000,
3439 .pa_end = 0x47401000 + SZ_2K - 1,
3440 .flags = ADDR_TYPE_RT
3441 },
3442 {
3443 .name = "musb1",
3444 .pa_start = 0x47401800,
3445 .pa_end = 0x47401800 + SZ_2K - 1,
3446 .flags = ADDR_TYPE_RT
3447 },
3448 { }
3449 };
3450
3451 static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
3452 .master = &am33xx_l3_s_hwmod,
3453 .slave = &am33xx_usbss_hwmod,
3454 .clk = "l3s_gclk",
3455 .addr = am33xx_usbss_addr_space,
3456 .user = OCP_USER_MPU,
3457 .flags = OCPIF_SWSUP_IDLE,
3458 };
3459
3460 /* l3 main -> ocmc */
3461 static struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
3462 .master = &am33xx_l3_main_hwmod,
3463 .slave = &am33xx_ocmcram_hwmod,
3464 .user = OCP_USER_MPU | OCP_USER_SDMA,
3465 };
3466
3467 static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
3468 &am33xx_l4_fw__emif_fw,
3469 &am33xx_l3_main__emif,
3470 &am33xx_mpu__l3_main,
3471 &am33xx_mpu__prcm,
3472 &am33xx_l3_s__l4_ls,
3473 &am33xx_l3_s__l4_wkup,
3474 &am33xx_l3_s__l4_fw,
3475 &am33xx_l3_main__l4_hs,
3476 &am33xx_l3_main__l3_s,
3477 &am33xx_l3_main__l3_instr,
3478 &am33xx_l3_main__gfx,
3479 &am33xx_l3_s__l3_main,
3480 &am33xx_pruss__l3_main,
3481 &am33xx_wkup_m3__l4_wkup,
3482 &am33xx_gfx__l3_main,
3483 &am33xx_l4_wkup__wkup_m3,
3484 &am33xx_l4_wkup__control,
3485 &am33xx_l4_wkup__smartreflex0,
3486 &am33xx_l4_wkup__smartreflex1,
3487 &am33xx_l4_wkup__uart1,
3488 &am33xx_l4_wkup__timer1,
3489 &am33xx_l4_wkup__rtc,
3490 &am33xx_l4_wkup__i2c1,
3491 &am33xx_l4_wkup__gpio0,
3492 &am33xx_l4_wkup__adc_tsc,
3493 &am33xx_l4_wkup__wd_timer1,
3494 &am33xx_l4_hs__pruss,
3495 &am33xx_l4_per__dcan0,
3496 &am33xx_l4_per__dcan1,
3497 &am33xx_l4_per__gpio1,
3498 &am33xx_l4_per__gpio2,
3499 &am33xx_l4_per__gpio3,
3500 &am33xx_l4_per__i2c2,
3501 &am33xx_l4_per__i2c3,
3502 &am33xx_l4_per__mailbox,
3503 &am33xx_l4_ls__mcasp0,
3504 &am33xx_l3_s__mcasp0_data,
3505 &am33xx_l4_ls__mcasp1,
3506 &am33xx_l3_s__mcasp1_data,
3507 &am33xx_l4_ls__mmc0,
3508 &am33xx_l4_ls__mmc1,
3509 &am33xx_l3_s__mmc2,
3510 &am33xx_l4_ls__timer2,
3511 &am33xx_l4_ls__timer3,
3512 &am33xx_l4_ls__timer4,
3513 &am33xx_l4_ls__timer5,
3514 &am33xx_l4_ls__timer6,
3515 &am33xx_l4_ls__timer7,
3516 &am33xx_l3_main__tpcc,
3517 &am33xx_l4_ls__uart2,
3518 &am33xx_l4_ls__uart3,
3519 &am33xx_l4_ls__uart4,
3520 &am33xx_l4_ls__uart5,
3521 &am33xx_l4_ls__uart6,
3522 &am33xx_l4_ls__spinlock,
3523 &am33xx_l4_ls__elm,
3524 &am33xx_l4_ls__ehrpwm0,
3525 &am33xx_l4_ls__ehrpwm1,
3526 &am33xx_l4_ls__ehrpwm2,
3527 &am33xx_l4_ls__eqep0,
3528 &am33xx_l4_ls__eqep1,
3529 &am33xx_l4_ls__eqep2,
3530 &am33xx_l4_ls__ecap0,
3531 &am33xx_l4_ls__ecap1,
3532 &am33xx_l4_ls__ecap2,
3533 &am33xx_l3_s__gpmc,
3534 &am33xx_l3_main__lcdc,
3535 &am33xx_l4_ls__mcspi0,
3536 &am33xx_l4_ls__mcspi1,
3537 &am33xx_l3_main__tptc0,
3538 &am33xx_l3_main__tptc1,
3539 &am33xx_l3_main__tptc2,
3540 &am33xx_l3_main__ocmc,
3541 &am33xx_l3_s__usbss,
3542 &am33xx_l4_hs__cpgmac0,
3543 &am33xx_cpgmac0__mdio,
3544 NULL,
3545 };
3546
3547 int __init am33xx_hwmod_init(void)
3548 {
3549 omap_hwmod_init();
3550 return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
3551 }
Linux kernel - Deliverables
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