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0c65079c2b69b308a7ea45953adfbf6b1d461617
[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_3xxx_data.c
1 /*
2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
3 *
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
6 * Paul Walmsley
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * The data in this file should be completely autogeneratable from
13 * the TI hardware database or other technical documentation.
14 *
15 * XXX these should be marked initdata for multi-OMAP kernels
16 */
17 #include <plat/omap_hwmod.h>
18 #include <mach/irqs.h>
19 #include <plat/cpu.h>
20 #include <plat/dma.h>
21 #include <plat/serial.h>
22 #include <plat/l3_3xxx.h>
23 #include <plat/l4_3xxx.h>
24 #include <plat/i2c.h>
25 #include <plat/gpio.h>
26 #include <plat/mmc.h>
27 #include <plat/mcbsp.h>
28 #include <plat/mcspi.h>
29 #include <plat/dmtimer.h>
30
31 #include "omap_hwmod_common_data.h"
32
33 #include "smartreflex.h"
34 #include "prm-regbits-34xx.h"
35 #include "cm-regbits-34xx.h"
36 #include "wd_timer.h"
37 #include <mach/am35xx.h>
38
39 /*
40 * OMAP3xxx hardware module integration data
41 *
42 * All of the data in this section should be autogeneratable from the
43 * TI hardware database or other technical documentation. Data that
44 * is driver-specific or driver-kernel integration-specific belongs
45 * elsewhere.
46 */
47
48 /*
49 * IP blocks
50 */
51
52 /* L3 */
53 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
54 { .irq = INT_34XX_L3_DBG_IRQ },
55 { .irq = INT_34XX_L3_APP_IRQ },
56 { .irq = -1 }
57 };
58
59 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
60 .name = "l3_main",
61 .class = &l3_hwmod_class,
62 .mpu_irqs = omap3xxx_l3_main_irqs,
63 .flags = HWMOD_NO_IDLEST,
64 };
65
66 /* L4 CORE */
67 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
68 .name = "l4_core",
69 .class = &l4_hwmod_class,
70 .flags = HWMOD_NO_IDLEST,
71 };
72
73 /* L4 PER */
74 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
75 .name = "l4_per",
76 .class = &l4_hwmod_class,
77 .flags = HWMOD_NO_IDLEST,
78 };
79
80 /* L4 WKUP */
81 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
82 .name = "l4_wkup",
83 .class = &l4_hwmod_class,
84 .flags = HWMOD_NO_IDLEST,
85 };
86
87 /* L4 SEC */
88 static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
89 .name = "l4_sec",
90 .class = &l4_hwmod_class,
91 .flags = HWMOD_NO_IDLEST,
92 };
93
94 /* MPU */
95 static struct omap_hwmod omap3xxx_mpu_hwmod = {
96 .name = "mpu",
97 .class = &mpu_hwmod_class,
98 .main_clk = "arm_fck",
99 };
100
101 /* IVA2 (IVA2) */
102 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
103 { .name = "logic", .rst_shift = 0 },
104 { .name = "seq0", .rst_shift = 1 },
105 { .name = "seq1", .rst_shift = 2 },
106 };
107
108 static struct omap_hwmod omap3xxx_iva_hwmod = {
109 .name = "iva",
110 .class = &iva_hwmod_class,
111 .clkdm_name = "iva2_clkdm",
112 .rst_lines = omap3xxx_iva_resets,
113 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets),
114 .main_clk = "iva2_ck",
115 };
116
117 /* timer class */
118 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
119 .rev_offs = 0x0000,
120 .sysc_offs = 0x0010,
121 .syss_offs = 0x0014,
122 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
123 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
124 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
125 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
126 .sysc_fields = &omap_hwmod_sysc_type1,
127 };
128
129 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
130 .name = "timer",
131 .sysc = &omap3xxx_timer_1ms_sysc,
132 .rev = OMAP_TIMER_IP_VERSION_1,
133 };
134
135 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
136 .rev_offs = 0x0000,
137 .sysc_offs = 0x0010,
138 .syss_offs = 0x0014,
139 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
140 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
141 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
142 .sysc_fields = &omap_hwmod_sysc_type1,
143 };
144
145 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
146 .name = "timer",
147 .sysc = &omap3xxx_timer_sysc,
148 .rev = OMAP_TIMER_IP_VERSION_1,
149 };
150
151 /* secure timers dev attribute */
152 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
153 .timer_capability = OMAP_TIMER_SECURE,
154 };
155
156 /* always-on timers dev attribute */
157 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
158 .timer_capability = OMAP_TIMER_ALWON,
159 };
160
161 /* pwm timers dev attribute */
162 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
163 .timer_capability = OMAP_TIMER_HAS_PWM,
164 };
165
166 /* timer1 */
167 static struct omap_hwmod omap3xxx_timer1_hwmod = {
168 .name = "timer1",
169 .mpu_irqs = omap2_timer1_mpu_irqs,
170 .main_clk = "gpt1_fck",
171 .prcm = {
172 .omap2 = {
173 .prcm_reg_id = 1,
174 .module_bit = OMAP3430_EN_GPT1_SHIFT,
175 .module_offs = WKUP_MOD,
176 .idlest_reg_id = 1,
177 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
178 },
179 },
180 .dev_attr = &capability_alwon_dev_attr,
181 .class = &omap3xxx_timer_1ms_hwmod_class,
182 };
183
184 /* timer2 */
185 static struct omap_hwmod omap3xxx_timer2_hwmod = {
186 .name = "timer2",
187 .mpu_irqs = omap2_timer2_mpu_irqs,
188 .main_clk = "gpt2_fck",
189 .prcm = {
190 .omap2 = {
191 .prcm_reg_id = 1,
192 .module_bit = OMAP3430_EN_GPT2_SHIFT,
193 .module_offs = OMAP3430_PER_MOD,
194 .idlest_reg_id = 1,
195 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
196 },
197 },
198 .dev_attr = &capability_alwon_dev_attr,
199 .class = &omap3xxx_timer_1ms_hwmod_class,
200 };
201
202 /* timer3 */
203 static struct omap_hwmod omap3xxx_timer3_hwmod = {
204 .name = "timer3",
205 .mpu_irqs = omap2_timer3_mpu_irqs,
206 .main_clk = "gpt3_fck",
207 .prcm = {
208 .omap2 = {
209 .prcm_reg_id = 1,
210 .module_bit = OMAP3430_EN_GPT3_SHIFT,
211 .module_offs = OMAP3430_PER_MOD,
212 .idlest_reg_id = 1,
213 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
214 },
215 },
216 .dev_attr = &capability_alwon_dev_attr,
217 .class = &omap3xxx_timer_hwmod_class,
218 };
219
220 /* timer4 */
221 static struct omap_hwmod omap3xxx_timer4_hwmod = {
222 .name = "timer4",
223 .mpu_irqs = omap2_timer4_mpu_irqs,
224 .main_clk = "gpt4_fck",
225 .prcm = {
226 .omap2 = {
227 .prcm_reg_id = 1,
228 .module_bit = OMAP3430_EN_GPT4_SHIFT,
229 .module_offs = OMAP3430_PER_MOD,
230 .idlest_reg_id = 1,
231 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
232 },
233 },
234 .dev_attr = &capability_alwon_dev_attr,
235 .class = &omap3xxx_timer_hwmod_class,
236 };
237
238 /* timer5 */
239 static struct omap_hwmod omap3xxx_timer5_hwmod = {
240 .name = "timer5",
241 .mpu_irqs = omap2_timer5_mpu_irqs,
242 .main_clk = "gpt5_fck",
243 .prcm = {
244 .omap2 = {
245 .prcm_reg_id = 1,
246 .module_bit = OMAP3430_EN_GPT5_SHIFT,
247 .module_offs = OMAP3430_PER_MOD,
248 .idlest_reg_id = 1,
249 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
250 },
251 },
252 .dev_attr = &capability_alwon_dev_attr,
253 .class = &omap3xxx_timer_hwmod_class,
254 };
255
256 /* timer6 */
257 static struct omap_hwmod omap3xxx_timer6_hwmod = {
258 .name = "timer6",
259 .mpu_irqs = omap2_timer6_mpu_irqs,
260 .main_clk = "gpt6_fck",
261 .prcm = {
262 .omap2 = {
263 .prcm_reg_id = 1,
264 .module_bit = OMAP3430_EN_GPT6_SHIFT,
265 .module_offs = OMAP3430_PER_MOD,
266 .idlest_reg_id = 1,
267 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
268 },
269 },
270 .dev_attr = &capability_alwon_dev_attr,
271 .class = &omap3xxx_timer_hwmod_class,
272 };
273
274 /* timer7 */
275 static struct omap_hwmod omap3xxx_timer7_hwmod = {
276 .name = "timer7",
277 .mpu_irqs = omap2_timer7_mpu_irqs,
278 .main_clk = "gpt7_fck",
279 .prcm = {
280 .omap2 = {
281 .prcm_reg_id = 1,
282 .module_bit = OMAP3430_EN_GPT7_SHIFT,
283 .module_offs = OMAP3430_PER_MOD,
284 .idlest_reg_id = 1,
285 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
286 },
287 },
288 .dev_attr = &capability_alwon_dev_attr,
289 .class = &omap3xxx_timer_hwmod_class,
290 };
291
292 /* timer8 */
293 static struct omap_hwmod omap3xxx_timer8_hwmod = {
294 .name = "timer8",
295 .mpu_irqs = omap2_timer8_mpu_irqs,
296 .main_clk = "gpt8_fck",
297 .prcm = {
298 .omap2 = {
299 .prcm_reg_id = 1,
300 .module_bit = OMAP3430_EN_GPT8_SHIFT,
301 .module_offs = OMAP3430_PER_MOD,
302 .idlest_reg_id = 1,
303 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
304 },
305 },
306 .dev_attr = &capability_pwm_dev_attr,
307 .class = &omap3xxx_timer_hwmod_class,
308 };
309
310 /* timer9 */
311 static struct omap_hwmod omap3xxx_timer9_hwmod = {
312 .name = "timer9",
313 .mpu_irqs = omap2_timer9_mpu_irqs,
314 .main_clk = "gpt9_fck",
315 .prcm = {
316 .omap2 = {
317 .prcm_reg_id = 1,
318 .module_bit = OMAP3430_EN_GPT9_SHIFT,
319 .module_offs = OMAP3430_PER_MOD,
320 .idlest_reg_id = 1,
321 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
322 },
323 },
324 .dev_attr = &capability_pwm_dev_attr,
325 .class = &omap3xxx_timer_hwmod_class,
326 };
327
328 /* timer10 */
329 static struct omap_hwmod omap3xxx_timer10_hwmod = {
330 .name = "timer10",
331 .mpu_irqs = omap2_timer10_mpu_irqs,
332 .main_clk = "gpt10_fck",
333 .prcm = {
334 .omap2 = {
335 .prcm_reg_id = 1,
336 .module_bit = OMAP3430_EN_GPT10_SHIFT,
337 .module_offs = CORE_MOD,
338 .idlest_reg_id = 1,
339 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
340 },
341 },
342 .dev_attr = &capability_pwm_dev_attr,
343 .class = &omap3xxx_timer_1ms_hwmod_class,
344 };
345
346 /* timer11 */
347 static struct omap_hwmod omap3xxx_timer11_hwmod = {
348 .name = "timer11",
349 .mpu_irqs = omap2_timer11_mpu_irqs,
350 .main_clk = "gpt11_fck",
351 .prcm = {
352 .omap2 = {
353 .prcm_reg_id = 1,
354 .module_bit = OMAP3430_EN_GPT11_SHIFT,
355 .module_offs = CORE_MOD,
356 .idlest_reg_id = 1,
357 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
358 },
359 },
360 .dev_attr = &capability_pwm_dev_attr,
361 .class = &omap3xxx_timer_hwmod_class,
362 };
363
364 /* timer12 */
365 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
366 { .irq = 95, },
367 { .irq = -1 }
368 };
369
370 static struct omap_hwmod omap3xxx_timer12_hwmod = {
371 .name = "timer12",
372 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
373 .main_clk = "gpt12_fck",
374 .prcm = {
375 .omap2 = {
376 .prcm_reg_id = 1,
377 .module_bit = OMAP3430_EN_GPT12_SHIFT,
378 .module_offs = WKUP_MOD,
379 .idlest_reg_id = 1,
380 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
381 },
382 },
383 .dev_attr = &capability_secure_dev_attr,
384 .class = &omap3xxx_timer_hwmod_class,
385 };
386
387 /*
388 * 'wd_timer' class
389 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
390 * overflow condition
391 */
392
393 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
394 .rev_offs = 0x0000,
395 .sysc_offs = 0x0010,
396 .syss_offs = 0x0014,
397 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
398 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
399 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
400 SYSS_HAS_RESET_STATUS),
401 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
402 .sysc_fields = &omap_hwmod_sysc_type1,
403 };
404
405 /* I2C common */
406 static struct omap_hwmod_class_sysconfig i2c_sysc = {
407 .rev_offs = 0x00,
408 .sysc_offs = 0x20,
409 .syss_offs = 0x10,
410 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
411 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
412 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
413 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
414 .clockact = CLOCKACT_TEST_ICLK,
415 .sysc_fields = &omap_hwmod_sysc_type1,
416 };
417
418 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
419 .name = "wd_timer",
420 .sysc = &omap3xxx_wd_timer_sysc,
421 .pre_shutdown = &omap2_wd_timer_disable
422 };
423
424 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
425 .name = "wd_timer2",
426 .class = &omap3xxx_wd_timer_hwmod_class,
427 .main_clk = "wdt2_fck",
428 .prcm = {
429 .omap2 = {
430 .prcm_reg_id = 1,
431 .module_bit = OMAP3430_EN_WDT2_SHIFT,
432 .module_offs = WKUP_MOD,
433 .idlest_reg_id = 1,
434 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
435 },
436 },
437 /*
438 * XXX: Use software supervised mode, HW supervised smartidle seems to
439 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
440 */
441 .flags = HWMOD_SWSUP_SIDLE,
442 };
443
444 /* UART1 */
445 static struct omap_hwmod omap3xxx_uart1_hwmod = {
446 .name = "uart1",
447 .mpu_irqs = omap2_uart1_mpu_irqs,
448 .sdma_reqs = omap2_uart1_sdma_reqs,
449 .main_clk = "uart1_fck",
450 .prcm = {
451 .omap2 = {
452 .module_offs = CORE_MOD,
453 .prcm_reg_id = 1,
454 .module_bit = OMAP3430_EN_UART1_SHIFT,
455 .idlest_reg_id = 1,
456 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
457 },
458 },
459 .class = &omap2_uart_class,
460 };
461
462 /* UART2 */
463 static struct omap_hwmod omap3xxx_uart2_hwmod = {
464 .name = "uart2",
465 .mpu_irqs = omap2_uart2_mpu_irqs,
466 .sdma_reqs = omap2_uart2_sdma_reqs,
467 .main_clk = "uart2_fck",
468 .prcm = {
469 .omap2 = {
470 .module_offs = CORE_MOD,
471 .prcm_reg_id = 1,
472 .module_bit = OMAP3430_EN_UART2_SHIFT,
473 .idlest_reg_id = 1,
474 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
475 },
476 },
477 .class = &omap2_uart_class,
478 };
479
480 /* UART3 */
481 static struct omap_hwmod omap3xxx_uart3_hwmod = {
482 .name = "uart3",
483 .mpu_irqs = omap2_uart3_mpu_irqs,
484 .sdma_reqs = omap2_uart3_sdma_reqs,
485 .main_clk = "uart3_fck",
486 .prcm = {
487 .omap2 = {
488 .module_offs = OMAP3430_PER_MOD,
489 .prcm_reg_id = 1,
490 .module_bit = OMAP3430_EN_UART3_SHIFT,
491 .idlest_reg_id = 1,
492 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
493 },
494 },
495 .class = &omap2_uart_class,
496 };
497
498 /* UART4 */
499 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
500 { .irq = INT_36XX_UART4_IRQ, },
501 { .irq = -1 }
502 };
503
504 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
505 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
506 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
507 { .dma_req = -1 }
508 };
509
510 static struct omap_hwmod omap36xx_uart4_hwmod = {
511 .name = "uart4",
512 .mpu_irqs = uart4_mpu_irqs,
513 .sdma_reqs = uart4_sdma_reqs,
514 .main_clk = "uart4_fck",
515 .prcm = {
516 .omap2 = {
517 .module_offs = OMAP3430_PER_MOD,
518 .prcm_reg_id = 1,
519 .module_bit = OMAP3630_EN_UART4_SHIFT,
520 .idlest_reg_id = 1,
521 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
522 },
523 },
524 .class = &omap2_uart_class,
525 };
526
527 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
528 { .irq = INT_35XX_UART4_IRQ, },
529 };
530
531 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
532 { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
533 { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
534 };
535
536 static struct omap_hwmod am35xx_uart4_hwmod = {
537 .name = "uart4",
538 .mpu_irqs = am35xx_uart4_mpu_irqs,
539 .sdma_reqs = am35xx_uart4_sdma_reqs,
540 .main_clk = "uart4_fck",
541 .prcm = {
542 .omap2 = {
543 .module_offs = CORE_MOD,
544 .prcm_reg_id = 1,
545 .module_bit = OMAP3430_EN_UART4_SHIFT,
546 .idlest_reg_id = 1,
547 .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT,
548 },
549 },
550 .class = &omap2_uart_class,
551 };
552
553 static struct omap_hwmod_class i2c_class = {
554 .name = "i2c",
555 .sysc = &i2c_sysc,
556 .rev = OMAP_I2C_IP_VERSION_1,
557 .reset = &omap_i2c_reset,
558 };
559
560 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
561 { .name = "dispc", .dma_req = 5 },
562 { .name = "dsi1", .dma_req = 74 },
563 { .dma_req = -1 }
564 };
565
566 /* dss */
567 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
568 /*
569 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
570 * driver does not use these clocks.
571 */
572 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
573 { .role = "tv_clk", .clk = "dss_tv_fck" },
574 /* required only on OMAP3430 */
575 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
576 };
577
578 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
579 .name = "dss_core",
580 .class = &omap2_dss_hwmod_class,
581 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
582 .sdma_reqs = omap3xxx_dss_sdma_chs,
583 .prcm = {
584 .omap2 = {
585 .prcm_reg_id = 1,
586 .module_bit = OMAP3430_EN_DSS1_SHIFT,
587 .module_offs = OMAP3430_DSS_MOD,
588 .idlest_reg_id = 1,
589 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
590 },
591 },
592 .opt_clks = dss_opt_clks,
593 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
594 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
595 };
596
597 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
598 .name = "dss_core",
599 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
600 .class = &omap2_dss_hwmod_class,
601 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
602 .sdma_reqs = omap3xxx_dss_sdma_chs,
603 .prcm = {
604 .omap2 = {
605 .prcm_reg_id = 1,
606 .module_bit = OMAP3430_EN_DSS1_SHIFT,
607 .module_offs = OMAP3430_DSS_MOD,
608 .idlest_reg_id = 1,
609 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
610 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
611 },
612 },
613 .opt_clks = dss_opt_clks,
614 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
615 };
616
617 /*
618 * 'dispc' class
619 * display controller
620 */
621
622 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
623 .rev_offs = 0x0000,
624 .sysc_offs = 0x0010,
625 .syss_offs = 0x0014,
626 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
627 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
628 SYSC_HAS_ENAWAKEUP),
629 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
630 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
631 .sysc_fields = &omap_hwmod_sysc_type1,
632 };
633
634 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
635 .name = "dispc",
636 .sysc = &omap3_dispc_sysc,
637 };
638
639 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
640 .name = "dss_dispc",
641 .class = &omap3_dispc_hwmod_class,
642 .mpu_irqs = omap2_dispc_irqs,
643 .main_clk = "dss1_alwon_fck",
644 .prcm = {
645 .omap2 = {
646 .prcm_reg_id = 1,
647 .module_bit = OMAP3430_EN_DSS1_SHIFT,
648 .module_offs = OMAP3430_DSS_MOD,
649 },
650 },
651 .flags = HWMOD_NO_IDLEST,
652 .dev_attr = &omap2_3_dss_dispc_dev_attr
653 };
654
655 /*
656 * 'dsi' class
657 * display serial interface controller
658 */
659
660 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
661 .name = "dsi",
662 };
663
664 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
665 { .irq = 25 },
666 { .irq = -1 }
667 };
668
669 /* dss_dsi1 */
670 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
671 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
672 };
673
674 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
675 .name = "dss_dsi1",
676 .class = &omap3xxx_dsi_hwmod_class,
677 .mpu_irqs = omap3xxx_dsi1_irqs,
678 .main_clk = "dss1_alwon_fck",
679 .prcm = {
680 .omap2 = {
681 .prcm_reg_id = 1,
682 .module_bit = OMAP3430_EN_DSS1_SHIFT,
683 .module_offs = OMAP3430_DSS_MOD,
684 },
685 },
686 .opt_clks = dss_dsi1_opt_clks,
687 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
688 .flags = HWMOD_NO_IDLEST,
689 };
690
691 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
692 { .role = "ick", .clk = "dss_ick" },
693 };
694
695 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
696 .name = "dss_rfbi",
697 .class = &omap2_rfbi_hwmod_class,
698 .main_clk = "dss1_alwon_fck",
699 .prcm = {
700 .omap2 = {
701 .prcm_reg_id = 1,
702 .module_bit = OMAP3430_EN_DSS1_SHIFT,
703 .module_offs = OMAP3430_DSS_MOD,
704 },
705 },
706 .opt_clks = dss_rfbi_opt_clks,
707 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
708 .flags = HWMOD_NO_IDLEST,
709 };
710
711 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
712 /* required only on OMAP3430 */
713 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
714 };
715
716 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
717 .name = "dss_venc",
718 .class = &omap2_venc_hwmod_class,
719 .main_clk = "dss_tv_fck",
720 .prcm = {
721 .omap2 = {
722 .prcm_reg_id = 1,
723 .module_bit = OMAP3430_EN_DSS1_SHIFT,
724 .module_offs = OMAP3430_DSS_MOD,
725 },
726 },
727 .opt_clks = dss_venc_opt_clks,
728 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
729 .flags = HWMOD_NO_IDLEST,
730 };
731
732 /* I2C1 */
733 static struct omap_i2c_dev_attr i2c1_dev_attr = {
734 .fifo_depth = 8, /* bytes */
735 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
736 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
737 OMAP_I2C_FLAG_BUS_SHIFT_2,
738 };
739
740 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
741 .name = "i2c1",
742 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
743 .mpu_irqs = omap2_i2c1_mpu_irqs,
744 .sdma_reqs = omap2_i2c1_sdma_reqs,
745 .main_clk = "i2c1_fck",
746 .prcm = {
747 .omap2 = {
748 .module_offs = CORE_MOD,
749 .prcm_reg_id = 1,
750 .module_bit = OMAP3430_EN_I2C1_SHIFT,
751 .idlest_reg_id = 1,
752 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
753 },
754 },
755 .class = &i2c_class,
756 .dev_attr = &i2c1_dev_attr,
757 };
758
759 /* I2C2 */
760 static struct omap_i2c_dev_attr i2c2_dev_attr = {
761 .fifo_depth = 8, /* bytes */
762 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
763 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
764 OMAP_I2C_FLAG_BUS_SHIFT_2,
765 };
766
767 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
768 .name = "i2c2",
769 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
770 .mpu_irqs = omap2_i2c2_mpu_irqs,
771 .sdma_reqs = omap2_i2c2_sdma_reqs,
772 .main_clk = "i2c2_fck",
773 .prcm = {
774 .omap2 = {
775 .module_offs = CORE_MOD,
776 .prcm_reg_id = 1,
777 .module_bit = OMAP3430_EN_I2C2_SHIFT,
778 .idlest_reg_id = 1,
779 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
780 },
781 },
782 .class = &i2c_class,
783 .dev_attr = &i2c2_dev_attr,
784 };
785
786 /* I2C3 */
787 static struct omap_i2c_dev_attr i2c3_dev_attr = {
788 .fifo_depth = 64, /* bytes */
789 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
790 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
791 OMAP_I2C_FLAG_BUS_SHIFT_2,
792 };
793
794 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
795 { .irq = INT_34XX_I2C3_IRQ, },
796 { .irq = -1 }
797 };
798
799 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
800 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
801 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
802 { .dma_req = -1 }
803 };
804
805 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
806 .name = "i2c3",
807 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
808 .mpu_irqs = i2c3_mpu_irqs,
809 .sdma_reqs = i2c3_sdma_reqs,
810 .main_clk = "i2c3_fck",
811 .prcm = {
812 .omap2 = {
813 .module_offs = CORE_MOD,
814 .prcm_reg_id = 1,
815 .module_bit = OMAP3430_EN_I2C3_SHIFT,
816 .idlest_reg_id = 1,
817 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
818 },
819 },
820 .class = &i2c_class,
821 .dev_attr = &i2c3_dev_attr,
822 };
823
824 /*
825 * 'gpio' class
826 * general purpose io module
827 */
828
829 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
830 .rev_offs = 0x0000,
831 .sysc_offs = 0x0010,
832 .syss_offs = 0x0014,
833 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
834 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
835 SYSS_HAS_RESET_STATUS),
836 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
837 .sysc_fields = &omap_hwmod_sysc_type1,
838 };
839
840 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
841 .name = "gpio",
842 .sysc = &omap3xxx_gpio_sysc,
843 .rev = 1,
844 };
845
846 /* gpio_dev_attr */
847 static struct omap_gpio_dev_attr gpio_dev_attr = {
848 .bank_width = 32,
849 .dbck_flag = true,
850 };
851
852 /* gpio1 */
853 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
854 { .role = "dbclk", .clk = "gpio1_dbck", },
855 };
856
857 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
858 .name = "gpio1",
859 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
860 .mpu_irqs = omap2_gpio1_irqs,
861 .main_clk = "gpio1_ick",
862 .opt_clks = gpio1_opt_clks,
863 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
864 .prcm = {
865 .omap2 = {
866 .prcm_reg_id = 1,
867 .module_bit = OMAP3430_EN_GPIO1_SHIFT,
868 .module_offs = WKUP_MOD,
869 .idlest_reg_id = 1,
870 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
871 },
872 },
873 .class = &omap3xxx_gpio_hwmod_class,
874 .dev_attr = &gpio_dev_attr,
875 };
876
877 /* gpio2 */
878 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
879 { .role = "dbclk", .clk = "gpio2_dbck", },
880 };
881
882 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
883 .name = "gpio2",
884 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
885 .mpu_irqs = omap2_gpio2_irqs,
886 .main_clk = "gpio2_ick",
887 .opt_clks = gpio2_opt_clks,
888 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
889 .prcm = {
890 .omap2 = {
891 .prcm_reg_id = 1,
892 .module_bit = OMAP3430_EN_GPIO2_SHIFT,
893 .module_offs = OMAP3430_PER_MOD,
894 .idlest_reg_id = 1,
895 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
896 },
897 },
898 .class = &omap3xxx_gpio_hwmod_class,
899 .dev_attr = &gpio_dev_attr,
900 };
901
902 /* gpio3 */
903 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
904 { .role = "dbclk", .clk = "gpio3_dbck", },
905 };
906
907 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
908 .name = "gpio3",
909 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
910 .mpu_irqs = omap2_gpio3_irqs,
911 .main_clk = "gpio3_ick",
912 .opt_clks = gpio3_opt_clks,
913 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
914 .prcm = {
915 .omap2 = {
916 .prcm_reg_id = 1,
917 .module_bit = OMAP3430_EN_GPIO3_SHIFT,
918 .module_offs = OMAP3430_PER_MOD,
919 .idlest_reg_id = 1,
920 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
921 },
922 },
923 .class = &omap3xxx_gpio_hwmod_class,
924 .dev_attr = &gpio_dev_attr,
925 };
926
927 /* gpio4 */
928 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
929 { .role = "dbclk", .clk = "gpio4_dbck", },
930 };
931
932 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
933 .name = "gpio4",
934 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
935 .mpu_irqs = omap2_gpio4_irqs,
936 .main_clk = "gpio4_ick",
937 .opt_clks = gpio4_opt_clks,
938 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
939 .prcm = {
940 .omap2 = {
941 .prcm_reg_id = 1,
942 .module_bit = OMAP3430_EN_GPIO4_SHIFT,
943 .module_offs = OMAP3430_PER_MOD,
944 .idlest_reg_id = 1,
945 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
946 },
947 },
948 .class = &omap3xxx_gpio_hwmod_class,
949 .dev_attr = &gpio_dev_attr,
950 };
951
952 /* gpio5 */
953 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
954 { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
955 { .irq = -1 }
956 };
957
958 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
959 { .role = "dbclk", .clk = "gpio5_dbck", },
960 };
961
962 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
963 .name = "gpio5",
964 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
965 .mpu_irqs = omap3xxx_gpio5_irqs,
966 .main_clk = "gpio5_ick",
967 .opt_clks = gpio5_opt_clks,
968 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
969 .prcm = {
970 .omap2 = {
971 .prcm_reg_id = 1,
972 .module_bit = OMAP3430_EN_GPIO5_SHIFT,
973 .module_offs = OMAP3430_PER_MOD,
974 .idlest_reg_id = 1,
975 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
976 },
977 },
978 .class = &omap3xxx_gpio_hwmod_class,
979 .dev_attr = &gpio_dev_attr,
980 };
981
982 /* gpio6 */
983 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
984 { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
985 { .irq = -1 }
986 };
987
988 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
989 { .role = "dbclk", .clk = "gpio6_dbck", },
990 };
991
992 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
993 .name = "gpio6",
994 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
995 .mpu_irqs = omap3xxx_gpio6_irqs,
996 .main_clk = "gpio6_ick",
997 .opt_clks = gpio6_opt_clks,
998 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
999 .prcm = {
1000 .omap2 = {
1001 .prcm_reg_id = 1,
1002 .module_bit = OMAP3430_EN_GPIO6_SHIFT,
1003 .module_offs = OMAP3430_PER_MOD,
1004 .idlest_reg_id = 1,
1005 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
1006 },
1007 },
1008 .class = &omap3xxx_gpio_hwmod_class,
1009 .dev_attr = &gpio_dev_attr,
1010 };
1011
1012 /* dma attributes */
1013 static struct omap_dma_dev_attr dma_dev_attr = {
1014 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1015 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1016 .lch_count = 32,
1017 };
1018
1019 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1020 .rev_offs = 0x0000,
1021 .sysc_offs = 0x002c,
1022 .syss_offs = 0x0028,
1023 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1024 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1025 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
1026 SYSS_HAS_RESET_STATUS),
1027 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1028 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1029 .sysc_fields = &omap_hwmod_sysc_type1,
1030 };
1031
1032 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1033 .name = "dma",
1034 .sysc = &omap3xxx_dma_sysc,
1035 };
1036
1037 /* dma_system */
1038 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1039 .name = "dma",
1040 .class = &omap3xxx_dma_hwmod_class,
1041 .mpu_irqs = omap2_dma_system_irqs,
1042 .main_clk = "core_l3_ick",
1043 .prcm = {
1044 .omap2 = {
1045 .module_offs = CORE_MOD,
1046 .prcm_reg_id = 1,
1047 .module_bit = OMAP3430_ST_SDMA_SHIFT,
1048 .idlest_reg_id = 1,
1049 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
1050 },
1051 },
1052 .dev_attr = &dma_dev_attr,
1053 .flags = HWMOD_NO_IDLEST,
1054 };
1055
1056 /*
1057 * 'mcbsp' class
1058 * multi channel buffered serial port controller
1059 */
1060
1061 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
1062 .sysc_offs = 0x008c,
1063 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1064 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1065 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1066 .sysc_fields = &omap_hwmod_sysc_type1,
1067 .clockact = 0x2,
1068 };
1069
1070 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1071 .name = "mcbsp",
1072 .sysc = &omap3xxx_mcbsp_sysc,
1073 .rev = MCBSP_CONFIG_TYPE3,
1074 };
1075
1076 /* mcbsp1 */
1077 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
1078 { .name = "irq", .irq = 16 },
1079 { .name = "tx", .irq = 59 },
1080 { .name = "rx", .irq = 60 },
1081 { .irq = -1 }
1082 };
1083
1084 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1085 .name = "mcbsp1",
1086 .class = &omap3xxx_mcbsp_hwmod_class,
1087 .mpu_irqs = omap3xxx_mcbsp1_irqs,
1088 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
1089 .main_clk = "mcbsp1_fck",
1090 .prcm = {
1091 .omap2 = {
1092 .prcm_reg_id = 1,
1093 .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
1094 .module_offs = CORE_MOD,
1095 .idlest_reg_id = 1,
1096 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
1097 },
1098 },
1099 };
1100
1101 /* mcbsp2 */
1102 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
1103 { .name = "irq", .irq = 17 },
1104 { .name = "tx", .irq = 62 },
1105 { .name = "rx", .irq = 63 },
1106 { .irq = -1 }
1107 };
1108
1109 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1110 .sidetone = "mcbsp2_sidetone",
1111 };
1112
1113 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1114 .name = "mcbsp2",
1115 .class = &omap3xxx_mcbsp_hwmod_class,
1116 .mpu_irqs = omap3xxx_mcbsp2_irqs,
1117 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
1118 .main_clk = "mcbsp2_fck",
1119 .prcm = {
1120 .omap2 = {
1121 .prcm_reg_id = 1,
1122 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1123 .module_offs = OMAP3430_PER_MOD,
1124 .idlest_reg_id = 1,
1125 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1126 },
1127 },
1128 .dev_attr = &omap34xx_mcbsp2_dev_attr,
1129 };
1130
1131 /* mcbsp3 */
1132 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
1133 { .name = "irq", .irq = 22 },
1134 { .name = "tx", .irq = 89 },
1135 { .name = "rx", .irq = 90 },
1136 { .irq = -1 }
1137 };
1138
1139 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1140 .sidetone = "mcbsp3_sidetone",
1141 };
1142
1143 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1144 .name = "mcbsp3",
1145 .class = &omap3xxx_mcbsp_hwmod_class,
1146 .mpu_irqs = omap3xxx_mcbsp3_irqs,
1147 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
1148 .main_clk = "mcbsp3_fck",
1149 .prcm = {
1150 .omap2 = {
1151 .prcm_reg_id = 1,
1152 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1153 .module_offs = OMAP3430_PER_MOD,
1154 .idlest_reg_id = 1,
1155 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1156 },
1157 },
1158 .dev_attr = &omap34xx_mcbsp3_dev_attr,
1159 };
1160
1161 /* mcbsp4 */
1162 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
1163 { .name = "irq", .irq = 23 },
1164 { .name = "tx", .irq = 54 },
1165 { .name = "rx", .irq = 55 },
1166 { .irq = -1 }
1167 };
1168
1169 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
1170 { .name = "rx", .dma_req = 20 },
1171 { .name = "tx", .dma_req = 19 },
1172 { .dma_req = -1 }
1173 };
1174
1175 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1176 .name = "mcbsp4",
1177 .class = &omap3xxx_mcbsp_hwmod_class,
1178 .mpu_irqs = omap3xxx_mcbsp4_irqs,
1179 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
1180 .main_clk = "mcbsp4_fck",
1181 .prcm = {
1182 .omap2 = {
1183 .prcm_reg_id = 1,
1184 .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
1185 .module_offs = OMAP3430_PER_MOD,
1186 .idlest_reg_id = 1,
1187 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
1188 },
1189 },
1190 };
1191
1192 /* mcbsp5 */
1193 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
1194 { .name = "irq", .irq = 27 },
1195 { .name = "tx", .irq = 81 },
1196 { .name = "rx", .irq = 82 },
1197 { .irq = -1 }
1198 };
1199
1200 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
1201 { .name = "rx", .dma_req = 22 },
1202 { .name = "tx", .dma_req = 21 },
1203 { .dma_req = -1 }
1204 };
1205
1206 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1207 .name = "mcbsp5",
1208 .class = &omap3xxx_mcbsp_hwmod_class,
1209 .mpu_irqs = omap3xxx_mcbsp5_irqs,
1210 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
1211 .main_clk = "mcbsp5_fck",
1212 .prcm = {
1213 .omap2 = {
1214 .prcm_reg_id = 1,
1215 .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
1216 .module_offs = CORE_MOD,
1217 .idlest_reg_id = 1,
1218 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
1219 },
1220 },
1221 };
1222
1223 /* 'mcbsp sidetone' class */
1224 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
1225 .sysc_offs = 0x0010,
1226 .sysc_flags = SYSC_HAS_AUTOIDLE,
1227 .sysc_fields = &omap_hwmod_sysc_type1,
1228 };
1229
1230 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
1231 .name = "mcbsp_sidetone",
1232 .sysc = &omap3xxx_mcbsp_sidetone_sysc,
1233 };
1234
1235 /* mcbsp2_sidetone */
1236 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
1237 { .name = "irq", .irq = 4 },
1238 { .irq = -1 }
1239 };
1240
1241 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1242 .name = "mcbsp2_sidetone",
1243 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1244 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
1245 .main_clk = "mcbsp2_fck",
1246 .prcm = {
1247 .omap2 = {
1248 .prcm_reg_id = 1,
1249 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1250 .module_offs = OMAP3430_PER_MOD,
1251 .idlest_reg_id = 1,
1252 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1253 },
1254 },
1255 };
1256
1257 /* mcbsp3_sidetone */
1258 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
1259 { .name = "irq", .irq = 5 },
1260 { .irq = -1 }
1261 };
1262
1263 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1264 .name = "mcbsp3_sidetone",
1265 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1266 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
1267 .main_clk = "mcbsp3_fck",
1268 .prcm = {
1269 .omap2 = {
1270 .prcm_reg_id = 1,
1271 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1272 .module_offs = OMAP3430_PER_MOD,
1273 .idlest_reg_id = 1,
1274 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1275 },
1276 },
1277 };
1278
1279 /* SR common */
1280 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1281 .clkact_shift = 20,
1282 };
1283
1284 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1285 .sysc_offs = 0x24,
1286 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1287 .clockact = CLOCKACT_TEST_ICLK,
1288 .sysc_fields = &omap34xx_sr_sysc_fields,
1289 };
1290
1291 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1292 .name = "smartreflex",
1293 .sysc = &omap34xx_sr_sysc,
1294 .rev = 1,
1295 };
1296
1297 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
1298 .sidle_shift = 24,
1299 .enwkup_shift = 26,
1300 };
1301
1302 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1303 .sysc_offs = 0x38,
1304 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1305 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1306 SYSC_NO_CACHE),
1307 .sysc_fields = &omap36xx_sr_sysc_fields,
1308 };
1309
1310 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1311 .name = "smartreflex",
1312 .sysc = &omap36xx_sr_sysc,
1313 .rev = 2,
1314 };
1315
1316 /* SR1 */
1317 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1318 .sensor_voltdm_name = "mpu_iva",
1319 };
1320
1321 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
1322 { .irq = 18 },
1323 { .irq = -1 }
1324 };
1325
1326 static struct omap_hwmod omap34xx_sr1_hwmod = {
1327 .name = "sr1",
1328 .class = &omap34xx_smartreflex_hwmod_class,
1329 .main_clk = "sr1_fck",
1330 .prcm = {
1331 .omap2 = {
1332 .prcm_reg_id = 1,
1333 .module_bit = OMAP3430_EN_SR1_SHIFT,
1334 .module_offs = WKUP_MOD,
1335 .idlest_reg_id = 1,
1336 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1337 },
1338 },
1339 .dev_attr = &sr1_dev_attr,
1340 .mpu_irqs = omap3_smartreflex_mpu_irqs,
1341 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1342 };
1343
1344 static struct omap_hwmod omap36xx_sr1_hwmod = {
1345 .name = "sr1",
1346 .class = &omap36xx_smartreflex_hwmod_class,
1347 .main_clk = "sr1_fck",
1348 .prcm = {
1349 .omap2 = {
1350 .prcm_reg_id = 1,
1351 .module_bit = OMAP3430_EN_SR1_SHIFT,
1352 .module_offs = WKUP_MOD,
1353 .idlest_reg_id = 1,
1354 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1355 },
1356 },
1357 .dev_attr = &sr1_dev_attr,
1358 .mpu_irqs = omap3_smartreflex_mpu_irqs,
1359 };
1360
1361 /* SR2 */
1362 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1363 .sensor_voltdm_name = "core",
1364 };
1365
1366 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
1367 { .irq = 19 },
1368 { .irq = -1 }
1369 };
1370
1371 static struct omap_hwmod omap34xx_sr2_hwmod = {
1372 .name = "sr2",
1373 .class = &omap34xx_smartreflex_hwmod_class,
1374 .main_clk = "sr2_fck",
1375 .prcm = {
1376 .omap2 = {
1377 .prcm_reg_id = 1,
1378 .module_bit = OMAP3430_EN_SR2_SHIFT,
1379 .module_offs = WKUP_MOD,
1380 .idlest_reg_id = 1,
1381 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1382 },
1383 },
1384 .dev_attr = &sr2_dev_attr,
1385 .mpu_irqs = omap3_smartreflex_core_irqs,
1386 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1387 };
1388
1389 static struct omap_hwmod omap36xx_sr2_hwmod = {
1390 .name = "sr2",
1391 .class = &omap36xx_smartreflex_hwmod_class,
1392 .main_clk = "sr2_fck",
1393 .prcm = {
1394 .omap2 = {
1395 .prcm_reg_id = 1,
1396 .module_bit = OMAP3430_EN_SR2_SHIFT,
1397 .module_offs = WKUP_MOD,
1398 .idlest_reg_id = 1,
1399 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1400 },
1401 },
1402 .dev_attr = &sr2_dev_attr,
1403 .mpu_irqs = omap3_smartreflex_core_irqs,
1404 };
1405
1406 /*
1407 * 'mailbox' class
1408 * mailbox module allowing communication between the on-chip processors
1409 * using a queued mailbox-interrupt mechanism.
1410 */
1411
1412 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1413 .rev_offs = 0x000,
1414 .sysc_offs = 0x010,
1415 .syss_offs = 0x014,
1416 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1417 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1418 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1419 .sysc_fields = &omap_hwmod_sysc_type1,
1420 };
1421
1422 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1423 .name = "mailbox",
1424 .sysc = &omap3xxx_mailbox_sysc,
1425 };
1426
1427 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
1428 { .irq = 26 },
1429 { .irq = -1 }
1430 };
1431
1432 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1433 .name = "mailbox",
1434 .class = &omap3xxx_mailbox_hwmod_class,
1435 .mpu_irqs = omap3xxx_mailbox_irqs,
1436 .main_clk = "mailboxes_ick",
1437 .prcm = {
1438 .omap2 = {
1439 .prcm_reg_id = 1,
1440 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1441 .module_offs = CORE_MOD,
1442 .idlest_reg_id = 1,
1443 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1444 },
1445 },
1446 };
1447
1448 /*
1449 * 'mcspi' class
1450 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1451 * bus
1452 */
1453
1454 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1455 .rev_offs = 0x0000,
1456 .sysc_offs = 0x0010,
1457 .syss_offs = 0x0014,
1458 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1459 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1460 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1461 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1462 .sysc_fields = &omap_hwmod_sysc_type1,
1463 };
1464
1465 static struct omap_hwmod_class omap34xx_mcspi_class = {
1466 .name = "mcspi",
1467 .sysc = &omap34xx_mcspi_sysc,
1468 .rev = OMAP3_MCSPI_REV,
1469 };
1470
1471 /* mcspi1 */
1472 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1473 .num_chipselect = 4,
1474 };
1475
1476 static struct omap_hwmod omap34xx_mcspi1 = {
1477 .name = "mcspi1",
1478 .mpu_irqs = omap2_mcspi1_mpu_irqs,
1479 .sdma_reqs = omap2_mcspi1_sdma_reqs,
1480 .main_clk = "mcspi1_fck",
1481 .prcm = {
1482 .omap2 = {
1483 .module_offs = CORE_MOD,
1484 .prcm_reg_id = 1,
1485 .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
1486 .idlest_reg_id = 1,
1487 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1488 },
1489 },
1490 .class = &omap34xx_mcspi_class,
1491 .dev_attr = &omap_mcspi1_dev_attr,
1492 };
1493
1494 /* mcspi2 */
1495 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1496 .num_chipselect = 2,
1497 };
1498
1499 static struct omap_hwmod omap34xx_mcspi2 = {
1500 .name = "mcspi2",
1501 .mpu_irqs = omap2_mcspi2_mpu_irqs,
1502 .sdma_reqs = omap2_mcspi2_sdma_reqs,
1503 .main_clk = "mcspi2_fck",
1504 .prcm = {
1505 .omap2 = {
1506 .module_offs = CORE_MOD,
1507 .prcm_reg_id = 1,
1508 .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
1509 .idlest_reg_id = 1,
1510 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1511 },
1512 },
1513 .class = &omap34xx_mcspi_class,
1514 .dev_attr = &omap_mcspi2_dev_attr,
1515 };
1516
1517 /* mcspi3 */
1518 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
1519 { .name = "irq", .irq = 91 }, /* 91 */
1520 { .irq = -1 }
1521 };
1522
1523 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
1524 { .name = "tx0", .dma_req = 15 },
1525 { .name = "rx0", .dma_req = 16 },
1526 { .name = "tx1", .dma_req = 23 },
1527 { .name = "rx1", .dma_req = 24 },
1528 { .dma_req = -1 }
1529 };
1530
1531 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1532 .num_chipselect = 2,
1533 };
1534
1535 static struct omap_hwmod omap34xx_mcspi3 = {
1536 .name = "mcspi3",
1537 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
1538 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
1539 .main_clk = "mcspi3_fck",
1540 .prcm = {
1541 .omap2 = {
1542 .module_offs = CORE_MOD,
1543 .prcm_reg_id = 1,
1544 .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
1545 .idlest_reg_id = 1,
1546 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1547 },
1548 },
1549 .class = &omap34xx_mcspi_class,
1550 .dev_attr = &omap_mcspi3_dev_attr,
1551 };
1552
1553 /* mcspi4 */
1554 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
1555 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
1556 { .irq = -1 }
1557 };
1558
1559 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
1560 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
1561 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
1562 { .dma_req = -1 }
1563 };
1564
1565 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1566 .num_chipselect = 1,
1567 };
1568
1569 static struct omap_hwmod omap34xx_mcspi4 = {
1570 .name = "mcspi4",
1571 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
1572 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
1573 .main_clk = "mcspi4_fck",
1574 .prcm = {
1575 .omap2 = {
1576 .module_offs = CORE_MOD,
1577 .prcm_reg_id = 1,
1578 .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
1579 .idlest_reg_id = 1,
1580 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1581 },
1582 },
1583 .class = &omap34xx_mcspi_class,
1584 .dev_attr = &omap_mcspi4_dev_attr,
1585 };
1586
1587 /* usbhsotg */
1588 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1589 .rev_offs = 0x0400,
1590 .sysc_offs = 0x0404,
1591 .syss_offs = 0x0408,
1592 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1593 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1594 SYSC_HAS_AUTOIDLE),
1595 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1596 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1597 .sysc_fields = &omap_hwmod_sysc_type1,
1598 };
1599
1600 static struct omap_hwmod_class usbotg_class = {
1601 .name = "usbotg",
1602 .sysc = &omap3xxx_usbhsotg_sysc,
1603 };
1604
1605 /* usb_otg_hs */
1606 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
1607
1608 { .name = "mc", .irq = 92 },
1609 { .name = "dma", .irq = 93 },
1610 { .irq = -1 }
1611 };
1612
1613 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1614 .name = "usb_otg_hs",
1615 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
1616 .main_clk = "hsotgusb_ick",
1617 .prcm = {
1618 .omap2 = {
1619 .prcm_reg_id = 1,
1620 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1621 .module_offs = CORE_MOD,
1622 .idlest_reg_id = 1,
1623 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1624 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
1625 },
1626 },
1627 .class = &usbotg_class,
1628
1629 /*
1630 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
1631 * broken when autoidle is enabled
1632 * workaround is to disable the autoidle bit at module level.
1633 */
1634 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
1635 | HWMOD_SWSUP_MSTANDBY,
1636 };
1637
1638 /* usb_otg_hs */
1639 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
1640
1641 { .name = "mc", .irq = 71 },
1642 { .irq = -1 }
1643 };
1644
1645 static struct omap_hwmod_class am35xx_usbotg_class = {
1646 .name = "am35xx_usbotg",
1647 .sysc = NULL,
1648 };
1649
1650 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1651 .name = "am35x_otg_hs",
1652 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
1653 .main_clk = NULL,
1654 .prcm = {
1655 .omap2 = {
1656 },
1657 },
1658 .class = &am35xx_usbotg_class,
1659 };
1660
1661 /* MMC/SD/SDIO common */
1662 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1663 .rev_offs = 0x1fc,
1664 .sysc_offs = 0x10,
1665 .syss_offs = 0x14,
1666 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1667 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1668 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1669 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1670 .sysc_fields = &omap_hwmod_sysc_type1,
1671 };
1672
1673 static struct omap_hwmod_class omap34xx_mmc_class = {
1674 .name = "mmc",
1675 .sysc = &omap34xx_mmc_sysc,
1676 };
1677
1678 /* MMC/SD/SDIO1 */
1679
1680 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
1681 { .irq = 83, },
1682 { .irq = -1 }
1683 };
1684
1685 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
1686 { .name = "tx", .dma_req = 61, },
1687 { .name = "rx", .dma_req = 62, },
1688 { .dma_req = -1 }
1689 };
1690
1691 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1692 { .role = "dbck", .clk = "omap_32k_fck", },
1693 };
1694
1695 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1696 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1697 };
1698
1699 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1700 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
1701 .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1702 OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1703 };
1704
1705 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1706 .name = "mmc1",
1707 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
1708 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
1709 .opt_clks = omap34xx_mmc1_opt_clks,
1710 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1711 .main_clk = "mmchs1_fck",
1712 .prcm = {
1713 .omap2 = {
1714 .module_offs = CORE_MOD,
1715 .prcm_reg_id = 1,
1716 .module_bit = OMAP3430_EN_MMC1_SHIFT,
1717 .idlest_reg_id = 1,
1718 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1719 },
1720 },
1721 .dev_attr = &mmc1_pre_es3_dev_attr,
1722 .class = &omap34xx_mmc_class,
1723 };
1724
1725 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1726 .name = "mmc1",
1727 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
1728 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
1729 .opt_clks = omap34xx_mmc1_opt_clks,
1730 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1731 .main_clk = "mmchs1_fck",
1732 .prcm = {
1733 .omap2 = {
1734 .module_offs = CORE_MOD,
1735 .prcm_reg_id = 1,
1736 .module_bit = OMAP3430_EN_MMC1_SHIFT,
1737 .idlest_reg_id = 1,
1738 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1739 },
1740 },
1741 .dev_attr = &mmc1_dev_attr,
1742 .class = &omap34xx_mmc_class,
1743 };
1744
1745 /* MMC/SD/SDIO2 */
1746
1747 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
1748 { .irq = INT_24XX_MMC2_IRQ, },
1749 { .irq = -1 }
1750 };
1751
1752 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
1753 { .name = "tx", .dma_req = 47, },
1754 { .name = "rx", .dma_req = 48, },
1755 { .dma_req = -1 }
1756 };
1757
1758 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1759 { .role = "dbck", .clk = "omap_32k_fck", },
1760 };
1761
1762 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1763 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
1764 .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1765 };
1766
1767 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1768 .name = "mmc2",
1769 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
1770 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
1771 .opt_clks = omap34xx_mmc2_opt_clks,
1772 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1773 .main_clk = "mmchs2_fck",
1774 .prcm = {
1775 .omap2 = {
1776 .module_offs = CORE_MOD,
1777 .prcm_reg_id = 1,
1778 .module_bit = OMAP3430_EN_MMC2_SHIFT,
1779 .idlest_reg_id = 1,
1780 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1781 },
1782 },
1783 .dev_attr = &mmc2_pre_es3_dev_attr,
1784 .class = &omap34xx_mmc_class,
1785 };
1786
1787 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1788 .name = "mmc2",
1789 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
1790 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
1791 .opt_clks = omap34xx_mmc2_opt_clks,
1792 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1793 .main_clk = "mmchs2_fck",
1794 .prcm = {
1795 .omap2 = {
1796 .module_offs = CORE_MOD,
1797 .prcm_reg_id = 1,
1798 .module_bit = OMAP3430_EN_MMC2_SHIFT,
1799 .idlest_reg_id = 1,
1800 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1801 },
1802 },
1803 .class = &omap34xx_mmc_class,
1804 };
1805
1806 /* MMC/SD/SDIO3 */
1807
1808 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
1809 { .irq = 94, },
1810 { .irq = -1 }
1811 };
1812
1813 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
1814 { .name = "tx", .dma_req = 77, },
1815 { .name = "rx", .dma_req = 78, },
1816 { .dma_req = -1 }
1817 };
1818
1819 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1820 { .role = "dbck", .clk = "omap_32k_fck", },
1821 };
1822
1823 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1824 .name = "mmc3",
1825 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
1826 .sdma_reqs = omap34xx_mmc3_sdma_reqs,
1827 .opt_clks = omap34xx_mmc3_opt_clks,
1828 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1829 .main_clk = "mmchs3_fck",
1830 .prcm = {
1831 .omap2 = {
1832 .prcm_reg_id = 1,
1833 .module_bit = OMAP3430_EN_MMC3_SHIFT,
1834 .idlest_reg_id = 1,
1835 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1836 },
1837 },
1838 .class = &omap34xx_mmc_class,
1839 };
1840
1841 /*
1842 * 'usb_host_hs' class
1843 * high-speed multi-port usb host controller
1844 */
1845
1846 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1847 .rev_offs = 0x0000,
1848 .sysc_offs = 0x0010,
1849 .syss_offs = 0x0014,
1850 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1851 SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1852 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1853 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1854 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1855 .sysc_fields = &omap_hwmod_sysc_type1,
1856 };
1857
1858 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1859 .name = "usb_host_hs",
1860 .sysc = &omap3xxx_usb_host_hs_sysc,
1861 };
1862
1863 static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
1864 { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
1865 };
1866
1867 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
1868 { .name = "ohci-irq", .irq = 76 },
1869 { .name = "ehci-irq", .irq = 77 },
1870 { .irq = -1 }
1871 };
1872
1873 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1874 .name = "usb_host_hs",
1875 .class = &omap3xxx_usb_host_hs_hwmod_class,
1876 .clkdm_name = "l3_init_clkdm",
1877 .mpu_irqs = omap3xxx_usb_host_hs_irqs,
1878 .main_clk = "usbhost_48m_fck",
1879 .prcm = {
1880 .omap2 = {
1881 .module_offs = OMAP3430ES2_USBHOST_MOD,
1882 .prcm_reg_id = 1,
1883 .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
1884 .idlest_reg_id = 1,
1885 .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1886 .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
1887 },
1888 },
1889 .opt_clks = omap3xxx_usb_host_hs_opt_clks,
1890 .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
1891
1892 /*
1893 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1894 * id: i660
1895 *
1896 * Description:
1897 * In the following configuration :
1898 * - USBHOST module is set to smart-idle mode
1899 * - PRCM asserts idle_req to the USBHOST module ( This typically
1900 * happens when the system is going to a low power mode : all ports
1901 * have been suspended, the master part of the USBHOST module has
1902 * entered the standby state, and SW has cut the functional clocks)
1903 * - an USBHOST interrupt occurs before the module is able to answer
1904 * idle_ack, typically a remote wakeup IRQ.
1905 * Then the USB HOST module will enter a deadlock situation where it
1906 * is no more accessible nor functional.
1907 *
1908 * Workaround:
1909 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1910 */
1911
1912 /*
1913 * Errata: USB host EHCI may stall when entering smart-standby mode
1914 * Id: i571
1915 *
1916 * Description:
1917 * When the USBHOST module is set to smart-standby mode, and when it is
1918 * ready to enter the standby state (i.e. all ports are suspended and
1919 * all attached devices are in suspend mode), then it can wrongly assert
1920 * the Mstandby signal too early while there are still some residual OCP
1921 * transactions ongoing. If this condition occurs, the internal state
1922 * machine may go to an undefined state and the USB link may be stuck
1923 * upon the next resume.
1924 *
1925 * Workaround:
1926 * Don't use smart standby; use only force standby,
1927 * hence HWMOD_SWSUP_MSTANDBY
1928 */
1929
1930 /*
1931 * During system boot; If the hwmod framework resets the module
1932 * the module will have smart idle settings; which can lead to deadlock
1933 * (above Errata Id:i660); so, dont reset the module during boot;
1934 * Use HWMOD_INIT_NO_RESET.
1935 */
1936
1937 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
1938 HWMOD_INIT_NO_RESET,
1939 };
1940
1941 /*
1942 * 'usb_tll_hs' class
1943 * usb_tll_hs module is the adapter on the usb_host_hs ports
1944 */
1945 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
1946 .rev_offs = 0x0000,
1947 .sysc_offs = 0x0010,
1948 .syss_offs = 0x0014,
1949 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1950 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1951 SYSC_HAS_AUTOIDLE),
1952 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1953 .sysc_fields = &omap_hwmod_sysc_type1,
1954 };
1955
1956 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
1957 .name = "usb_tll_hs",
1958 .sysc = &omap3xxx_usb_tll_hs_sysc,
1959 };
1960
1961 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
1962 { .name = "tll-irq", .irq = 78 },
1963 { .irq = -1 }
1964 };
1965
1966 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
1967 .name = "usb_tll_hs",
1968 .class = &omap3xxx_usb_tll_hs_hwmod_class,
1969 .clkdm_name = "l3_init_clkdm",
1970 .mpu_irqs = omap3xxx_usb_tll_hs_irqs,
1971 .main_clk = "usbtll_fck",
1972 .prcm = {
1973 .omap2 = {
1974 .module_offs = CORE_MOD,
1975 .prcm_reg_id = 3,
1976 .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1977 .idlest_reg_id = 3,
1978 .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
1979 },
1980 },
1981 };
1982
1983 /*
1984 * interfaces
1985 */
1986
1987 /* L3 -> L4_CORE interface */
1988 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
1989 .master = &omap3xxx_l3_main_hwmod,
1990 .slave = &omap3xxx_l4_core_hwmod,
1991 .user = OCP_USER_MPU | OCP_USER_SDMA,
1992 };
1993
1994 /* L3 -> L4_PER interface */
1995 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
1996 .master = &omap3xxx_l3_main_hwmod,
1997 .slave = &omap3xxx_l4_per_hwmod,
1998 .user = OCP_USER_MPU | OCP_USER_SDMA,
1999 };
2000
2001 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
2002 {
2003 .pa_start = 0x68000000,
2004 .pa_end = 0x6800ffff,
2005 .flags = ADDR_TYPE_RT,
2006 },
2007 { }
2008 };
2009
2010 /* MPU -> L3 interface */
2011 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
2012 .master = &omap3xxx_mpu_hwmod,
2013 .slave = &omap3xxx_l3_main_hwmod,
2014 .addr = omap3xxx_l3_main_addrs,
2015 .user = OCP_USER_MPU,
2016 };
2017
2018 /* DSS -> l3 */
2019 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
2020 .master = &omap3430es1_dss_core_hwmod,
2021 .slave = &omap3xxx_l3_main_hwmod,
2022 .user = OCP_USER_MPU | OCP_USER_SDMA,
2023 };
2024
2025 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
2026 .master = &omap3xxx_dss_core_hwmod,
2027 .slave = &omap3xxx_l3_main_hwmod,
2028 .fw = {
2029 .omap2 = {
2030 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
2031 .flags = OMAP_FIREWALL_L3,
2032 }
2033 },
2034 .user = OCP_USER_MPU | OCP_USER_SDMA,
2035 };
2036
2037 /* l3_core -> usbhsotg interface */
2038 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
2039 .master = &omap3xxx_usbhsotg_hwmod,
2040 .slave = &omap3xxx_l3_main_hwmod,
2041 .clk = "core_l3_ick",
2042 .user = OCP_USER_MPU,
2043 };
2044
2045 /* l3_core -> am35xx_usbhsotg interface */
2046 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
2047 .master = &am35xx_usbhsotg_hwmod,
2048 .slave = &omap3xxx_l3_main_hwmod,
2049 .clk = "core_l3_ick",
2050 .user = OCP_USER_MPU,
2051 };
2052 /* L4_CORE -> L4_WKUP interface */
2053 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
2054 .master = &omap3xxx_l4_core_hwmod,
2055 .slave = &omap3xxx_l4_wkup_hwmod,
2056 .user = OCP_USER_MPU | OCP_USER_SDMA,
2057 };
2058
2059 /* L4 CORE -> MMC1 interface */
2060 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
2061 .master = &omap3xxx_l4_core_hwmod,
2062 .slave = &omap3xxx_pre_es3_mmc1_hwmod,
2063 .clk = "mmchs1_ick",
2064 .addr = omap2430_mmc1_addr_space,
2065 .user = OCP_USER_MPU | OCP_USER_SDMA,
2066 .flags = OMAP_FIREWALL_L4
2067 };
2068
2069 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
2070 .master = &omap3xxx_l4_core_hwmod,
2071 .slave = &omap3xxx_es3plus_mmc1_hwmod,
2072 .clk = "mmchs1_ick",
2073 .addr = omap2430_mmc1_addr_space,
2074 .user = OCP_USER_MPU | OCP_USER_SDMA,
2075 .flags = OMAP_FIREWALL_L4
2076 };
2077
2078 /* L4 CORE -> MMC2 interface */
2079 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
2080 .master = &omap3xxx_l4_core_hwmod,
2081 .slave = &omap3xxx_pre_es3_mmc2_hwmod,
2082 .clk = "mmchs2_ick",
2083 .addr = omap2430_mmc2_addr_space,
2084 .user = OCP_USER_MPU | OCP_USER_SDMA,
2085 .flags = OMAP_FIREWALL_L4
2086 };
2087
2088 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2089 .master = &omap3xxx_l4_core_hwmod,
2090 .slave = &omap3xxx_es3plus_mmc2_hwmod,
2091 .clk = "mmchs2_ick",
2092 .addr = omap2430_mmc2_addr_space,
2093 .user = OCP_USER_MPU | OCP_USER_SDMA,
2094 .flags = OMAP_FIREWALL_L4
2095 };
2096
2097 /* L4 CORE -> MMC3 interface */
2098 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
2099 {
2100 .pa_start = 0x480ad000,
2101 .pa_end = 0x480ad1ff,
2102 .flags = ADDR_TYPE_RT,
2103 },
2104 { }
2105 };
2106
2107 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2108 .master = &omap3xxx_l4_core_hwmod,
2109 .slave = &omap3xxx_mmc3_hwmod,
2110 .clk = "mmchs3_ick",
2111 .addr = omap3xxx_mmc3_addr_space,
2112 .user = OCP_USER_MPU | OCP_USER_SDMA,
2113 .flags = OMAP_FIREWALL_L4
2114 };
2115
2116 /* L4 CORE -> UART1 interface */
2117 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
2118 {
2119 .pa_start = OMAP3_UART1_BASE,
2120 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
2121 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2122 },
2123 { }
2124 };
2125
2126 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2127 .master = &omap3xxx_l4_core_hwmod,
2128 .slave = &omap3xxx_uart1_hwmod,
2129 .clk = "uart1_ick",
2130 .addr = omap3xxx_uart1_addr_space,
2131 .user = OCP_USER_MPU | OCP_USER_SDMA,
2132 };
2133
2134 /* L4 CORE -> UART2 interface */
2135 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
2136 {
2137 .pa_start = OMAP3_UART2_BASE,
2138 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
2139 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2140 },
2141 { }
2142 };
2143
2144 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2145 .master = &omap3xxx_l4_core_hwmod,
2146 .slave = &omap3xxx_uart2_hwmod,
2147 .clk = "uart2_ick",
2148 .addr = omap3xxx_uart2_addr_space,
2149 .user = OCP_USER_MPU | OCP_USER_SDMA,
2150 };
2151
2152 /* L4 PER -> UART3 interface */
2153 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
2154 {
2155 .pa_start = OMAP3_UART3_BASE,
2156 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
2157 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2158 },
2159 { }
2160 };
2161
2162 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2163 .master = &omap3xxx_l4_per_hwmod,
2164 .slave = &omap3xxx_uart3_hwmod,
2165 .clk = "uart3_ick",
2166 .addr = omap3xxx_uart3_addr_space,
2167 .user = OCP_USER_MPU | OCP_USER_SDMA,
2168 };
2169
2170 /* L4 PER -> UART4 interface */
2171 static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
2172 {
2173 .pa_start = OMAP3_UART4_BASE,
2174 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
2175 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2176 },
2177 { }
2178 };
2179
2180 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2181 .master = &omap3xxx_l4_per_hwmod,
2182 .slave = &omap36xx_uart4_hwmod,
2183 .clk = "uart4_ick",
2184 .addr = omap36xx_uart4_addr_space,
2185 .user = OCP_USER_MPU | OCP_USER_SDMA,
2186 };
2187
2188 /* AM35xx: L4 CORE -> UART4 interface */
2189 static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
2190 {
2191 .pa_start = OMAP3_UART4_AM35XX_BASE,
2192 .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
2193 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2194 },
2195 };
2196
2197 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2198 .master = &omap3xxx_l4_core_hwmod,
2199 .slave = &am35xx_uart4_hwmod,
2200 .clk = "uart4_ick",
2201 .addr = am35xx_uart4_addr_space,
2202 .user = OCP_USER_MPU | OCP_USER_SDMA,
2203 };
2204
2205 /* L4 CORE -> I2C1 interface */
2206 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2207 .master = &omap3xxx_l4_core_hwmod,
2208 .slave = &omap3xxx_i2c1_hwmod,
2209 .clk = "i2c1_ick",
2210 .addr = omap2_i2c1_addr_space,
2211 .fw = {
2212 .omap2 = {
2213 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
2214 .l4_prot_group = 7,
2215 .flags = OMAP_FIREWALL_L4,
2216 }
2217 },
2218 .user = OCP_USER_MPU | OCP_USER_SDMA,
2219 };
2220
2221 /* L4 CORE -> I2C2 interface */
2222 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2223 .master = &omap3xxx_l4_core_hwmod,
2224 .slave = &omap3xxx_i2c2_hwmod,
2225 .clk = "i2c2_ick",
2226 .addr = omap2_i2c2_addr_space,
2227 .fw = {
2228 .omap2 = {
2229 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
2230 .l4_prot_group = 7,
2231 .flags = OMAP_FIREWALL_L4,
2232 }
2233 },
2234 .user = OCP_USER_MPU | OCP_USER_SDMA,
2235 };
2236
2237 /* L4 CORE -> I2C3 interface */
2238 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
2239 {
2240 .pa_start = 0x48060000,
2241 .pa_end = 0x48060000 + SZ_128 - 1,
2242 .flags = ADDR_TYPE_RT,
2243 },
2244 { }
2245 };
2246
2247 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2248 .master = &omap3xxx_l4_core_hwmod,
2249 .slave = &omap3xxx_i2c3_hwmod,
2250 .clk = "i2c3_ick",
2251 .addr = omap3xxx_i2c3_addr_space,
2252 .fw = {
2253 .omap2 = {
2254 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
2255 .l4_prot_group = 7,
2256 .flags = OMAP_FIREWALL_L4,
2257 }
2258 },
2259 .user = OCP_USER_MPU | OCP_USER_SDMA,
2260 };
2261
2262 /* L4 CORE -> SR1 interface */
2263 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
2264 {
2265 .pa_start = OMAP34XX_SR1_BASE,
2266 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
2267 .flags = ADDR_TYPE_RT,
2268 },
2269 { }
2270 };
2271
2272 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2273 .master = &omap3xxx_l4_core_hwmod,
2274 .slave = &omap34xx_sr1_hwmod,
2275 .clk = "sr_l4_ick",
2276 .addr = omap3_sr1_addr_space,
2277 .user = OCP_USER_MPU,
2278 };
2279
2280 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2281 .master = &omap3xxx_l4_core_hwmod,
2282 .slave = &omap36xx_sr1_hwmod,
2283 .clk = "sr_l4_ick",
2284 .addr = omap3_sr1_addr_space,
2285 .user = OCP_USER_MPU,
2286 };
2287
2288 /* L4 CORE -> SR1 interface */
2289 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
2290 {
2291 .pa_start = OMAP34XX_SR2_BASE,
2292 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
2293 .flags = ADDR_TYPE_RT,
2294 },
2295 { }
2296 };
2297
2298 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2299 .master = &omap3xxx_l4_core_hwmod,
2300 .slave = &omap34xx_sr2_hwmod,
2301 .clk = "sr_l4_ick",
2302 .addr = omap3_sr2_addr_space,
2303 .user = OCP_USER_MPU,
2304 };
2305
2306 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2307 .master = &omap3xxx_l4_core_hwmod,
2308 .slave = &omap36xx_sr2_hwmod,
2309 .clk = "sr_l4_ick",
2310 .addr = omap3_sr2_addr_space,
2311 .user = OCP_USER_MPU,
2312 };
2313
2314 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
2315 {
2316 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
2317 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
2318 .flags = ADDR_TYPE_RT
2319 },
2320 { }
2321 };
2322
2323 /* l4_core -> usbhsotg */
2324 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2325 .master = &omap3xxx_l4_core_hwmod,
2326 .slave = &omap3xxx_usbhsotg_hwmod,
2327 .clk = "l4_ick",
2328 .addr = omap3xxx_usbhsotg_addrs,
2329 .user = OCP_USER_MPU,
2330 };
2331
2332 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
2333 {
2334 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
2335 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
2336 .flags = ADDR_TYPE_RT
2337 },
2338 { }
2339 };
2340
2341 /* l4_core -> usbhsotg */
2342 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2343 .master = &omap3xxx_l4_core_hwmod,
2344 .slave = &am35xx_usbhsotg_hwmod,
2345 .clk = "l4_ick",
2346 .addr = am35xx_usbhsotg_addrs,
2347 .user = OCP_USER_MPU,
2348 };
2349
2350 /* L4_WKUP -> L4_SEC interface */
2351 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2352 .master = &omap3xxx_l4_wkup_hwmod,
2353 .slave = &omap3xxx_l4_sec_hwmod,
2354 .user = OCP_USER_MPU | OCP_USER_SDMA,
2355 };
2356
2357 /* IVA2 <- L3 interface */
2358 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2359 .master = &omap3xxx_l3_main_hwmod,
2360 .slave = &omap3xxx_iva_hwmod,
2361 .clk = "core_l3_ick",
2362 .user = OCP_USER_MPU | OCP_USER_SDMA,
2363 };
2364
2365 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
2366 {
2367 .pa_start = 0x48318000,
2368 .pa_end = 0x48318000 + SZ_1K - 1,
2369 .flags = ADDR_TYPE_RT
2370 },
2371 { }
2372 };
2373
2374 /* l4_wkup -> timer1 */
2375 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2376 .master = &omap3xxx_l4_wkup_hwmod,
2377 .slave = &omap3xxx_timer1_hwmod,
2378 .clk = "gpt1_ick",
2379 .addr = omap3xxx_timer1_addrs,
2380 .user = OCP_USER_MPU | OCP_USER_SDMA,
2381 };
2382
2383 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
2384 {
2385 .pa_start = 0x49032000,
2386 .pa_end = 0x49032000 + SZ_1K - 1,
2387 .flags = ADDR_TYPE_RT
2388 },
2389 { }
2390 };
2391
2392 /* l4_per -> timer2 */
2393 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2394 .master = &omap3xxx_l4_per_hwmod,
2395 .slave = &omap3xxx_timer2_hwmod,
2396 .clk = "gpt2_ick",
2397 .addr = omap3xxx_timer2_addrs,
2398 .user = OCP_USER_MPU | OCP_USER_SDMA,
2399 };
2400
2401 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
2402 {
2403 .pa_start = 0x49034000,
2404 .pa_end = 0x49034000 + SZ_1K - 1,
2405 .flags = ADDR_TYPE_RT
2406 },
2407 { }
2408 };
2409
2410 /* l4_per -> timer3 */
2411 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2412 .master = &omap3xxx_l4_per_hwmod,
2413 .slave = &omap3xxx_timer3_hwmod,
2414 .clk = "gpt3_ick",
2415 .addr = omap3xxx_timer3_addrs,
2416 .user = OCP_USER_MPU | OCP_USER_SDMA,
2417 };
2418
2419 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
2420 {
2421 .pa_start = 0x49036000,
2422 .pa_end = 0x49036000 + SZ_1K - 1,
2423 .flags = ADDR_TYPE_RT
2424 },
2425 { }
2426 };
2427
2428 /* l4_per -> timer4 */
2429 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2430 .master = &omap3xxx_l4_per_hwmod,
2431 .slave = &omap3xxx_timer4_hwmod,
2432 .clk = "gpt4_ick",
2433 .addr = omap3xxx_timer4_addrs,
2434 .user = OCP_USER_MPU | OCP_USER_SDMA,
2435 };
2436
2437 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
2438 {
2439 .pa_start = 0x49038000,
2440 .pa_end = 0x49038000 + SZ_1K - 1,
2441 .flags = ADDR_TYPE_RT
2442 },
2443 { }
2444 };
2445
2446 /* l4_per -> timer5 */
2447 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2448 .master = &omap3xxx_l4_per_hwmod,
2449 .slave = &omap3xxx_timer5_hwmod,
2450 .clk = "gpt5_ick",
2451 .addr = omap3xxx_timer5_addrs,
2452 .user = OCP_USER_MPU | OCP_USER_SDMA,
2453 };
2454
2455 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
2456 {
2457 .pa_start = 0x4903A000,
2458 .pa_end = 0x4903A000 + SZ_1K - 1,
2459 .flags = ADDR_TYPE_RT
2460 },
2461 { }
2462 };
2463
2464 /* l4_per -> timer6 */
2465 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2466 .master = &omap3xxx_l4_per_hwmod,
2467 .slave = &omap3xxx_timer6_hwmod,
2468 .clk = "gpt6_ick",
2469 .addr = omap3xxx_timer6_addrs,
2470 .user = OCP_USER_MPU | OCP_USER_SDMA,
2471 };
2472
2473 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
2474 {
2475 .pa_start = 0x4903C000,
2476 .pa_end = 0x4903C000 + SZ_1K - 1,
2477 .flags = ADDR_TYPE_RT
2478 },
2479 { }
2480 };
2481
2482 /* l4_per -> timer7 */
2483 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2484 .master = &omap3xxx_l4_per_hwmod,
2485 .slave = &omap3xxx_timer7_hwmod,
2486 .clk = "gpt7_ick",
2487 .addr = omap3xxx_timer7_addrs,
2488 .user = OCP_USER_MPU | OCP_USER_SDMA,
2489 };
2490
2491 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
2492 {
2493 .pa_start = 0x4903E000,
2494 .pa_end = 0x4903E000 + SZ_1K - 1,
2495 .flags = ADDR_TYPE_RT
2496 },
2497 { }
2498 };
2499
2500 /* l4_per -> timer8 */
2501 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2502 .master = &omap3xxx_l4_per_hwmod,
2503 .slave = &omap3xxx_timer8_hwmod,
2504 .clk = "gpt8_ick",
2505 .addr = omap3xxx_timer8_addrs,
2506 .user = OCP_USER_MPU | OCP_USER_SDMA,
2507 };
2508
2509 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
2510 {
2511 .pa_start = 0x49040000,
2512 .pa_end = 0x49040000 + SZ_1K - 1,
2513 .flags = ADDR_TYPE_RT
2514 },
2515 { }
2516 };
2517
2518 /* l4_per -> timer9 */
2519 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2520 .master = &omap3xxx_l4_per_hwmod,
2521 .slave = &omap3xxx_timer9_hwmod,
2522 .clk = "gpt9_ick",
2523 .addr = omap3xxx_timer9_addrs,
2524 .user = OCP_USER_MPU | OCP_USER_SDMA,
2525 };
2526
2527 /* l4_core -> timer10 */
2528 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2529 .master = &omap3xxx_l4_core_hwmod,
2530 .slave = &omap3xxx_timer10_hwmod,
2531 .clk = "gpt10_ick",
2532 .addr = omap2_timer10_addrs,
2533 .user = OCP_USER_MPU | OCP_USER_SDMA,
2534 };
2535
2536 /* l4_core -> timer11 */
2537 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2538 .master = &omap3xxx_l4_core_hwmod,
2539 .slave = &omap3xxx_timer11_hwmod,
2540 .clk = "gpt11_ick",
2541 .addr = omap2_timer11_addrs,
2542 .user = OCP_USER_MPU | OCP_USER_SDMA,
2543 };
2544
2545 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
2546 {
2547 .pa_start = 0x48304000,
2548 .pa_end = 0x48304000 + SZ_1K - 1,
2549 .flags = ADDR_TYPE_RT
2550 },
2551 { }
2552 };
2553
2554 /* l4_core -> timer12 */
2555 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2556 .master = &omap3xxx_l4_sec_hwmod,
2557 .slave = &omap3xxx_timer12_hwmod,
2558 .clk = "gpt12_ick",
2559 .addr = omap3xxx_timer12_addrs,
2560 .user = OCP_USER_MPU | OCP_USER_SDMA,
2561 };
2562
2563 /* l4_wkup -> wd_timer2 */
2564 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
2565 {
2566 .pa_start = 0x48314000,
2567 .pa_end = 0x4831407f,
2568 .flags = ADDR_TYPE_RT
2569 },
2570 { }
2571 };
2572
2573 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2574 .master = &omap3xxx_l4_wkup_hwmod,
2575 .slave = &omap3xxx_wd_timer2_hwmod,
2576 .clk = "wdt2_ick",
2577 .addr = omap3xxx_wd_timer2_addrs,
2578 .user = OCP_USER_MPU | OCP_USER_SDMA,
2579 };
2580
2581 /* l4_core -> dss */
2582 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2583 .master = &omap3xxx_l4_core_hwmod,
2584 .slave = &omap3430es1_dss_core_hwmod,
2585 .clk = "dss_ick",
2586 .addr = omap2_dss_addrs,
2587 .fw = {
2588 .omap2 = {
2589 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2590 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2591 .flags = OMAP_FIREWALL_L4,
2592 }
2593 },
2594 .user = OCP_USER_MPU | OCP_USER_SDMA,
2595 };
2596
2597 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2598 .master = &omap3xxx_l4_core_hwmod,
2599 .slave = &omap3xxx_dss_core_hwmod,
2600 .clk = "dss_ick",
2601 .addr = omap2_dss_addrs,
2602 .fw = {
2603 .omap2 = {
2604 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2605 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2606 .flags = OMAP_FIREWALL_L4,
2607 }
2608 },
2609 .user = OCP_USER_MPU | OCP_USER_SDMA,
2610 };
2611
2612 /* l4_core -> dss_dispc */
2613 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2614 .master = &omap3xxx_l4_core_hwmod,
2615 .slave = &omap3xxx_dss_dispc_hwmod,
2616 .clk = "dss_ick",
2617 .addr = omap2_dss_dispc_addrs,
2618 .fw = {
2619 .omap2 = {
2620 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2621 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2622 .flags = OMAP_FIREWALL_L4,
2623 }
2624 },
2625 .user = OCP_USER_MPU | OCP_USER_SDMA,
2626 };
2627
2628 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
2629 {
2630 .pa_start = 0x4804FC00,
2631 .pa_end = 0x4804FFFF,
2632 .flags = ADDR_TYPE_RT
2633 },
2634 { }
2635 };
2636
2637 /* l4_core -> dss_dsi1 */
2638 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2639 .master = &omap3xxx_l4_core_hwmod,
2640 .slave = &omap3xxx_dss_dsi1_hwmod,
2641 .clk = "dss_ick",
2642 .addr = omap3xxx_dss_dsi1_addrs,
2643 .fw = {
2644 .omap2 = {
2645 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2646 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2647 .flags = OMAP_FIREWALL_L4,
2648 }
2649 },
2650 .user = OCP_USER_MPU | OCP_USER_SDMA,
2651 };
2652
2653 /* l4_core -> dss_rfbi */
2654 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2655 .master = &omap3xxx_l4_core_hwmod,
2656 .slave = &omap3xxx_dss_rfbi_hwmod,
2657 .clk = "dss_ick",
2658 .addr = omap2_dss_rfbi_addrs,
2659 .fw = {
2660 .omap2 = {
2661 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2662 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2663 .flags = OMAP_FIREWALL_L4,
2664 }
2665 },
2666 .user = OCP_USER_MPU | OCP_USER_SDMA,
2667 };
2668
2669 /* l4_core -> dss_venc */
2670 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2671 .master = &omap3xxx_l4_core_hwmod,
2672 .slave = &omap3xxx_dss_venc_hwmod,
2673 .clk = "dss_ick",
2674 .addr = omap2_dss_venc_addrs,
2675 .fw = {
2676 .omap2 = {
2677 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2678 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2679 .flags = OMAP_FIREWALL_L4,
2680 }
2681 },
2682 .flags = OCPIF_SWSUP_IDLE,
2683 .user = OCP_USER_MPU | OCP_USER_SDMA,
2684 };
2685
2686 /* l4_wkup -> gpio1 */
2687 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2688 {
2689 .pa_start = 0x48310000,
2690 .pa_end = 0x483101ff,
2691 .flags = ADDR_TYPE_RT
2692 },
2693 { }
2694 };
2695
2696 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2697 .master = &omap3xxx_l4_wkup_hwmod,
2698 .slave = &omap3xxx_gpio1_hwmod,
2699 .addr = omap3xxx_gpio1_addrs,
2700 .user = OCP_USER_MPU | OCP_USER_SDMA,
2701 };
2702
2703 /* l4_per -> gpio2 */
2704 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2705 {
2706 .pa_start = 0x49050000,
2707 .pa_end = 0x490501ff,
2708 .flags = ADDR_TYPE_RT
2709 },
2710 { }
2711 };
2712
2713 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2714 .master = &omap3xxx_l4_per_hwmod,
2715 .slave = &omap3xxx_gpio2_hwmod,
2716 .addr = omap3xxx_gpio2_addrs,
2717 .user = OCP_USER_MPU | OCP_USER_SDMA,
2718 };
2719
2720 /* l4_per -> gpio3 */
2721 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2722 {
2723 .pa_start = 0x49052000,
2724 .pa_end = 0x490521ff,
2725 .flags = ADDR_TYPE_RT
2726 },
2727 { }
2728 };
2729
2730 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2731 .master = &omap3xxx_l4_per_hwmod,
2732 .slave = &omap3xxx_gpio3_hwmod,
2733 .addr = omap3xxx_gpio3_addrs,
2734 .user = OCP_USER_MPU | OCP_USER_SDMA,
2735 };
2736
2737 /* l4_per -> gpio4 */
2738 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
2739 {
2740 .pa_start = 0x49054000,
2741 .pa_end = 0x490541ff,
2742 .flags = ADDR_TYPE_RT
2743 },
2744 { }
2745 };
2746
2747 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
2748 .master = &omap3xxx_l4_per_hwmod,
2749 .slave = &omap3xxx_gpio4_hwmod,
2750 .addr = omap3xxx_gpio4_addrs,
2751 .user = OCP_USER_MPU | OCP_USER_SDMA,
2752 };
2753
2754 /* l4_per -> gpio5 */
2755 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
2756 {
2757 .pa_start = 0x49056000,
2758 .pa_end = 0x490561ff,
2759 .flags = ADDR_TYPE_RT
2760 },
2761 { }
2762 };
2763
2764 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
2765 .master = &omap3xxx_l4_per_hwmod,
2766 .slave = &omap3xxx_gpio5_hwmod,
2767 .addr = omap3xxx_gpio5_addrs,
2768 .user = OCP_USER_MPU | OCP_USER_SDMA,
2769 };
2770
2771 /* l4_per -> gpio6 */
2772 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
2773 {
2774 .pa_start = 0x49058000,
2775 .pa_end = 0x490581ff,
2776 .flags = ADDR_TYPE_RT
2777 },
2778 { }
2779 };
2780
2781 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
2782 .master = &omap3xxx_l4_per_hwmod,
2783 .slave = &omap3xxx_gpio6_hwmod,
2784 .addr = omap3xxx_gpio6_addrs,
2785 .user = OCP_USER_MPU | OCP_USER_SDMA,
2786 };
2787
2788 /* dma_system -> L3 */
2789 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2790 .master = &omap3xxx_dma_system_hwmod,
2791 .slave = &omap3xxx_l3_main_hwmod,
2792 .clk = "core_l3_ick",
2793 .user = OCP_USER_MPU | OCP_USER_SDMA,
2794 };
2795
2796 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2797 {
2798 .pa_start = 0x48056000,
2799 .pa_end = 0x48056fff,
2800 .flags = ADDR_TYPE_RT
2801 },
2802 { }
2803 };
2804
2805 /* l4_cfg -> dma_system */
2806 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2807 .master = &omap3xxx_l4_core_hwmod,
2808 .slave = &omap3xxx_dma_system_hwmod,
2809 .clk = "core_l4_ick",
2810 .addr = omap3xxx_dma_system_addrs,
2811 .user = OCP_USER_MPU | OCP_USER_SDMA,
2812 };
2813
2814 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2815 {
2816 .name = "mpu",
2817 .pa_start = 0x48074000,
2818 .pa_end = 0x480740ff,
2819 .flags = ADDR_TYPE_RT
2820 },
2821 { }
2822 };
2823
2824 /* l4_core -> mcbsp1 */
2825 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2826 .master = &omap3xxx_l4_core_hwmod,
2827 .slave = &omap3xxx_mcbsp1_hwmod,
2828 .clk = "mcbsp1_ick",
2829 .addr = omap3xxx_mcbsp1_addrs,
2830 .user = OCP_USER_MPU | OCP_USER_SDMA,
2831 };
2832
2833 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2834 {
2835 .name = "mpu",
2836 .pa_start = 0x49022000,
2837 .pa_end = 0x490220ff,
2838 .flags = ADDR_TYPE_RT
2839 },
2840 { }
2841 };
2842
2843 /* l4_per -> mcbsp2 */
2844 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2845 .master = &omap3xxx_l4_per_hwmod,
2846 .slave = &omap3xxx_mcbsp2_hwmod,
2847 .clk = "mcbsp2_ick",
2848 .addr = omap3xxx_mcbsp2_addrs,
2849 .user = OCP_USER_MPU | OCP_USER_SDMA,
2850 };
2851
2852 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2853 {
2854 .name = "mpu",
2855 .pa_start = 0x49024000,
2856 .pa_end = 0x490240ff,
2857 .flags = ADDR_TYPE_RT
2858 },
2859 { }
2860 };
2861
2862 /* l4_per -> mcbsp3 */
2863 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2864 .master = &omap3xxx_l4_per_hwmod,
2865 .slave = &omap3xxx_mcbsp3_hwmod,
2866 .clk = "mcbsp3_ick",
2867 .addr = omap3xxx_mcbsp3_addrs,
2868 .user = OCP_USER_MPU | OCP_USER_SDMA,
2869 };
2870
2871 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2872 {
2873 .name = "mpu",
2874 .pa_start = 0x49026000,
2875 .pa_end = 0x490260ff,
2876 .flags = ADDR_TYPE_RT
2877 },
2878 { }
2879 };
2880
2881 /* l4_per -> mcbsp4 */
2882 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2883 .master = &omap3xxx_l4_per_hwmod,
2884 .slave = &omap3xxx_mcbsp4_hwmod,
2885 .clk = "mcbsp4_ick",
2886 .addr = omap3xxx_mcbsp4_addrs,
2887 .user = OCP_USER_MPU | OCP_USER_SDMA,
2888 };
2889
2890 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2891 {
2892 .name = "mpu",
2893 .pa_start = 0x48096000,
2894 .pa_end = 0x480960ff,
2895 .flags = ADDR_TYPE_RT
2896 },
2897 { }
2898 };
2899
2900 /* l4_core -> mcbsp5 */
2901 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2902 .master = &omap3xxx_l4_core_hwmod,
2903 .slave = &omap3xxx_mcbsp5_hwmod,
2904 .clk = "mcbsp5_ick",
2905 .addr = omap3xxx_mcbsp5_addrs,
2906 .user = OCP_USER_MPU | OCP_USER_SDMA,
2907 };
2908
2909 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2910 {
2911 .name = "sidetone",
2912 .pa_start = 0x49028000,
2913 .pa_end = 0x490280ff,
2914 .flags = ADDR_TYPE_RT
2915 },
2916 { }
2917 };
2918
2919 /* l4_per -> mcbsp2_sidetone */
2920 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2921 .master = &omap3xxx_l4_per_hwmod,
2922 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
2923 .clk = "mcbsp2_ick",
2924 .addr = omap3xxx_mcbsp2_sidetone_addrs,
2925 .user = OCP_USER_MPU,
2926 };
2927
2928 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2929 {
2930 .name = "sidetone",
2931 .pa_start = 0x4902A000,
2932 .pa_end = 0x4902A0ff,
2933 .flags = ADDR_TYPE_RT
2934 },
2935 { }
2936 };
2937
2938 /* l4_per -> mcbsp3_sidetone */
2939 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2940 .master = &omap3xxx_l4_per_hwmod,
2941 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
2942 .clk = "mcbsp3_ick",
2943 .addr = omap3xxx_mcbsp3_sidetone_addrs,
2944 .user = OCP_USER_MPU,
2945 };
2946
2947 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2948 {
2949 .pa_start = 0x48094000,
2950 .pa_end = 0x480941ff,
2951 .flags = ADDR_TYPE_RT,
2952 },
2953 { }
2954 };
2955
2956 /* l4_core -> mailbox */
2957 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2958 .master = &omap3xxx_l4_core_hwmod,
2959 .slave = &omap3xxx_mailbox_hwmod,
2960 .addr = omap3xxx_mailbox_addrs,
2961 .user = OCP_USER_MPU | OCP_USER_SDMA,
2962 };
2963
2964 /* l4 core -> mcspi1 interface */
2965 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2966 .master = &omap3xxx_l4_core_hwmod,
2967 .slave = &omap34xx_mcspi1,
2968 .clk = "mcspi1_ick",
2969 .addr = omap2_mcspi1_addr_space,
2970 .user = OCP_USER_MPU | OCP_USER_SDMA,
2971 };
2972
2973 /* l4 core -> mcspi2 interface */
2974 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2975 .master = &omap3xxx_l4_core_hwmod,
2976 .slave = &omap34xx_mcspi2,
2977 .clk = "mcspi2_ick",
2978 .addr = omap2_mcspi2_addr_space,
2979 .user = OCP_USER_MPU | OCP_USER_SDMA,
2980 };
2981
2982 /* l4 core -> mcspi3 interface */
2983 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2984 .master = &omap3xxx_l4_core_hwmod,
2985 .slave = &omap34xx_mcspi3,
2986 .clk = "mcspi3_ick",
2987 .addr = omap2430_mcspi3_addr_space,
2988 .user = OCP_USER_MPU | OCP_USER_SDMA,
2989 };
2990
2991 /* l4 core -> mcspi4 interface */
2992 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
2993 {
2994 .pa_start = 0x480ba000,
2995 .pa_end = 0x480ba0ff,
2996 .flags = ADDR_TYPE_RT,
2997 },
2998 { }
2999 };
3000
3001 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3002 .master = &omap3xxx_l4_core_hwmod,
3003 .slave = &omap34xx_mcspi4,
3004 .clk = "mcspi4_ick",
3005 .addr = omap34xx_mcspi4_addr_space,
3006 .user = OCP_USER_MPU | OCP_USER_SDMA,
3007 };
3008
3009 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3010 .master = &omap3xxx_usb_host_hs_hwmod,
3011 .slave = &omap3xxx_l3_main_hwmod,
3012 .clk = "core_l3_ick",
3013 .user = OCP_USER_MPU,
3014 };
3015
3016 static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3017 {
3018 .name = "uhh",
3019 .pa_start = 0x48064000,
3020 .pa_end = 0x480643ff,
3021 .flags = ADDR_TYPE_RT
3022 },
3023 {
3024 .name = "ohci",
3025 .pa_start = 0x48064400,
3026 .pa_end = 0x480647ff,
3027 },
3028 {
3029 .name = "ehci",
3030 .pa_start = 0x48064800,
3031 .pa_end = 0x48064cff,
3032 },
3033 {}
3034 };
3035
3036 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3037 .master = &omap3xxx_l4_core_hwmod,
3038 .slave = &omap3xxx_usb_host_hs_hwmod,
3039 .clk = "usbhost_ick",
3040 .addr = omap3xxx_usb_host_hs_addrs,
3041 .user = OCP_USER_MPU | OCP_USER_SDMA,
3042 };
3043
3044 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3045 {
3046 .name = "tll",
3047 .pa_start = 0x48062000,
3048 .pa_end = 0x48062fff,
3049 .flags = ADDR_TYPE_RT
3050 },
3051 {}
3052 };
3053
3054 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3055 .master = &omap3xxx_l4_core_hwmod,
3056 .slave = &omap3xxx_usb_tll_hs_hwmod,
3057 .clk = "usbtll_ick",
3058 .addr = omap3xxx_usb_tll_hs_addrs,
3059 .user = OCP_USER_MPU | OCP_USER_SDMA,
3060 };
3061
3062 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3063 &omap3xxx_l3_main__l4_core,
3064 &omap3xxx_l3_main__l4_per,
3065 &omap3xxx_mpu__l3_main,
3066 &omap3xxx_l4_core__l4_wkup,
3067 &omap3xxx_l4_core__mmc3,
3068 &omap3_l4_core__uart1,
3069 &omap3_l4_core__uart2,
3070 &omap3_l4_per__uart3,
3071 &omap3_l4_core__i2c1,
3072 &omap3_l4_core__i2c2,
3073 &omap3_l4_core__i2c3,
3074 &omap3xxx_l4_wkup__l4_sec,
3075 &omap3xxx_l4_wkup__timer1,
3076 &omap3xxx_l4_per__timer2,
3077 &omap3xxx_l4_per__timer3,
3078 &omap3xxx_l4_per__timer4,
3079 &omap3xxx_l4_per__timer5,
3080 &omap3xxx_l4_per__timer6,
3081 &omap3xxx_l4_per__timer7,
3082 &omap3xxx_l4_per__timer8,
3083 &omap3xxx_l4_per__timer9,
3084 &omap3xxx_l4_core__timer10,
3085 &omap3xxx_l4_core__timer11,
3086 &omap3xxx_l4_wkup__wd_timer2,
3087 &omap3xxx_l4_wkup__gpio1,
3088 &omap3xxx_l4_per__gpio2,
3089 &omap3xxx_l4_per__gpio3,
3090 &omap3xxx_l4_per__gpio4,
3091 &omap3xxx_l4_per__gpio5,
3092 &omap3xxx_l4_per__gpio6,
3093 &omap3xxx_dma_system__l3,
3094 &omap3xxx_l4_core__dma_system,
3095 &omap3xxx_l4_core__mcbsp1,
3096 &omap3xxx_l4_per__mcbsp2,
3097 &omap3xxx_l4_per__mcbsp3,
3098 &omap3xxx_l4_per__mcbsp4,
3099 &omap3xxx_l4_core__mcbsp5,
3100 &omap3xxx_l4_per__mcbsp2_sidetone,
3101 &omap3xxx_l4_per__mcbsp3_sidetone,
3102 &omap34xx_l4_core__mcspi1,
3103 &omap34xx_l4_core__mcspi2,
3104 &omap34xx_l4_core__mcspi3,
3105 &omap34xx_l4_core__mcspi4,
3106 NULL,
3107 };
3108
3109 /* GP-only hwmod links */
3110 static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = {
3111 &omap3xxx_l4_sec__timer12,
3112 NULL
3113 };
3114
3115 /* 3430ES1-only hwmod links */
3116 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
3117 &omap3430es1_dss__l3,
3118 &omap3430es1_l4_core__dss,
3119 NULL
3120 };
3121
3122 /* 3430ES2+-only hwmod links */
3123 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
3124 &omap3xxx_dss__l3,
3125 &omap3xxx_l4_core__dss,
3126 &omap3xxx_usbhsotg__l3,
3127 &omap3xxx_l4_core__usbhsotg,
3128 &omap3xxx_usb_host_hs__l3_main_2,
3129 &omap3xxx_l4_core__usb_host_hs,
3130 &omap3xxx_l4_core__usb_tll_hs,
3131 NULL
3132 };
3133
3134 /* <= 3430ES3-only hwmod links */
3135 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
3136 &omap3xxx_l4_core__pre_es3_mmc1,
3137 &omap3xxx_l4_core__pre_es3_mmc2,
3138 NULL
3139 };
3140
3141 /* 3430ES3+-only hwmod links */
3142 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3143 &omap3xxx_l4_core__es3plus_mmc1,
3144 &omap3xxx_l4_core__es3plus_mmc2,
3145 NULL
3146 };
3147
3148 /* 34xx-only hwmod links (all ES revisions) */
3149 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3150 &omap3xxx_l3__iva,
3151 &omap34xx_l4_core__sr1,
3152 &omap34xx_l4_core__sr2,
3153 &omap3xxx_l4_core__mailbox,
3154 NULL
3155 };
3156
3157 /* 36xx-only hwmod links (all ES revisions) */
3158 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3159 &omap3xxx_l3__iva,
3160 &omap36xx_l4_per__uart4,
3161 &omap3xxx_dss__l3,
3162 &omap3xxx_l4_core__dss,
3163 &omap36xx_l4_core__sr1,
3164 &omap36xx_l4_core__sr2,
3165 &omap3xxx_usbhsotg__l3,
3166 &omap3xxx_l4_core__usbhsotg,
3167 &omap3xxx_l4_core__mailbox,
3168 &omap3xxx_usb_host_hs__l3_main_2,
3169 &omap3xxx_l4_core__usb_host_hs,
3170 &omap3xxx_l4_core__usb_tll_hs,
3171 &omap3xxx_l4_core__es3plus_mmc1,
3172 &omap3xxx_l4_core__es3plus_mmc2,
3173 NULL
3174 };
3175
3176 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3177 &omap3xxx_dss__l3,
3178 &omap3xxx_l4_core__dss,
3179 &am35xx_usbhsotg__l3,
3180 &am35xx_l4_core__usbhsotg,
3181 &am35xx_l4_core__uart4,
3182 &omap3xxx_usb_host_hs__l3_main_2,
3183 &omap3xxx_l4_core__usb_host_hs,
3184 &omap3xxx_l4_core__usb_tll_hs,
3185 &omap3xxx_l4_core__es3plus_mmc1,
3186 &omap3xxx_l4_core__es3plus_mmc2,
3187 NULL
3188 };
3189
3190 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3191 &omap3xxx_l4_core__dss_dispc,
3192 &omap3xxx_l4_core__dss_dsi1,
3193 &omap3xxx_l4_core__dss_rfbi,
3194 &omap3xxx_l4_core__dss_venc,
3195 NULL
3196 };
3197
3198 int __init omap3xxx_hwmod_init(void)
3199 {
3200 int r;
3201 struct omap_hwmod_ocp_if **h = NULL;
3202 unsigned int rev;
3203
3204 /* Register hwmod links common to all OMAP3 */
3205 r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
3206 if (r < 0)
3207 return r;
3208
3209 /* Register GP-only hwmod links. */
3210 if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
3211 r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs);
3212 if (r < 0)
3213 return r;
3214 }
3215
3216 rev = omap_rev();
3217
3218 /*
3219 * Register hwmod links common to individual OMAP3 families, all
3220 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3221 * All possible revisions should be included in this conditional.
3222 */
3223 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3224 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3225 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3226 h = omap34xx_hwmod_ocp_ifs;
3227 } else if (rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1) {
3228 h = am35xx_hwmod_ocp_ifs;
3229 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3230 rev == OMAP3630_REV_ES1_2) {
3231 h = omap36xx_hwmod_ocp_ifs;
3232 } else {
3233 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3234 return -EINVAL;
3235 };
3236
3237 r = omap_hwmod_register_links(h);
3238 if (r < 0)
3239 return r;
3240
3241 /*
3242 * Register hwmod links specific to certain ES levels of a
3243 * particular family of silicon (e.g., 34xx ES1.0)
3244 */
3245 h = NULL;
3246 if (rev == OMAP3430_REV_ES1_0) {
3247 h = omap3430es1_hwmod_ocp_ifs;
3248 } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3249 rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3250 rev == OMAP3430_REV_ES3_1_2) {
3251 h = omap3430es2plus_hwmod_ocp_ifs;
3252 };
3253
3254 if (h) {
3255 r = omap_hwmod_register_links(h);
3256 if (r < 0)
3257 return r;
3258 }
3259
3260 h = NULL;
3261 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3262 rev == OMAP3430_REV_ES2_1) {
3263 h = omap3430_pre_es3_hwmod_ocp_ifs;
3264 } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3265 rev == OMAP3430_REV_ES3_1_2) {
3266 h = omap3430_es3plus_hwmod_ocp_ifs;
3267 };
3268
3269 if (h)
3270 r = omap_hwmod_register_links(h);
3271 if (r < 0)
3272 return r;
3273
3274 /*
3275 * DSS code presumes that dss_core hwmod is handled first,
3276 * _before_ any other DSS related hwmods so register common
3277 * DSS hwmod links last to ensure that dss_core is already
3278 * registered. Otherwise some change things may happen, for
3279 * ex. if dispc is handled before dss_core and DSS is enabled
3280 * in bootloader DISPC will be reset with outputs enabled
3281 * which sometimes leads to unrecoverable L3 error. XXX The
3282 * long-term fix to this is to ensure hwmods are set up in
3283 * dependency order in the hwmod core code.
3284 */
3285 r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
3286
3287 return r;
3288 }
Linux kernel - Deliverables
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