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Merge tag 'for-linus-docs-2012-05-02' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_3xxx_data.c
1 /*
2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
3 *
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
6 * Paul Walmsley
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * The data in this file should be completely autogeneratable from
13 * the TI hardware database or other technical documentation.
14 *
15 * XXX these should be marked initdata for multi-OMAP kernels
16 */
17
18 #include <linux/i2c-omap.h>
19 #include <linux/power/smartreflex.h>
20 #include <linux/platform_data/gpio-omap.h>
21
22 #include <linux/omap-dma.h>
23 #include "l3_3xxx.h"
24 #include "l4_3xxx.h"
25 #include <linux/platform_data/asoc-ti-mcbsp.h>
26 #include <linux/platform_data/spi-omap2-mcspi.h>
27 #include <linux/platform_data/iommu-omap.h>
28 #include <plat/dmtimer.h>
29
30 #include "am35xx.h"
31
32 #include "soc.h"
33 #include "omap_hwmod.h"
34 #include "omap_hwmod_common_data.h"
35 #include "prm-regbits-34xx.h"
36 #include "cm-regbits-34xx.h"
37
38 #include "dma.h"
39 #include "i2c.h"
40 #include "mmc.h"
41 #include "wd_timer.h"
42 #include "serial.h"
43
44 /*
45 * OMAP3xxx hardware module integration data
46 *
47 * All of the data in this section should be autogeneratable from the
48 * TI hardware database or other technical documentation. Data that
49 * is driver-specific or driver-kernel integration-specific belongs
50 * elsewhere.
51 */
52
53 /*
54 * IP blocks
55 */
56
57 /* L3 */
58 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
59 { .irq = 9 + OMAP_INTC_START, },
60 { .irq = 10 + OMAP_INTC_START, },
61 { .irq = -1 },
62 };
63
64 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
65 .name = "l3_main",
66 .class = &l3_hwmod_class,
67 .mpu_irqs = omap3xxx_l3_main_irqs,
68 .flags = HWMOD_NO_IDLEST,
69 };
70
71 /* L4 CORE */
72 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
73 .name = "l4_core",
74 .class = &l4_hwmod_class,
75 .flags = HWMOD_NO_IDLEST,
76 };
77
78 /* L4 PER */
79 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
80 .name = "l4_per",
81 .class = &l4_hwmod_class,
82 .flags = HWMOD_NO_IDLEST,
83 };
84
85 /* L4 WKUP */
86 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
87 .name = "l4_wkup",
88 .class = &l4_hwmod_class,
89 .flags = HWMOD_NO_IDLEST,
90 };
91
92 /* L4 SEC */
93 static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
94 .name = "l4_sec",
95 .class = &l4_hwmod_class,
96 .flags = HWMOD_NO_IDLEST,
97 };
98
99 /* MPU */
100 static struct omap_hwmod_irq_info omap3xxx_mpu_irqs[] = {
101 { .name = "pmu", .irq = 3 + OMAP_INTC_START },
102 { .irq = -1 }
103 };
104
105 static struct omap_hwmod omap3xxx_mpu_hwmod = {
106 .name = "mpu",
107 .mpu_irqs = omap3xxx_mpu_irqs,
108 .class = &mpu_hwmod_class,
109 .main_clk = "arm_fck",
110 };
111
112 /* IVA2 (IVA2) */
113 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
114 { .name = "logic", .rst_shift = 0, .st_shift = 8 },
115 { .name = "seq0", .rst_shift = 1, .st_shift = 9 },
116 { .name = "seq1", .rst_shift = 2, .st_shift = 10 },
117 };
118
119 static struct omap_hwmod omap3xxx_iva_hwmod = {
120 .name = "iva",
121 .class = &iva_hwmod_class,
122 .clkdm_name = "iva2_clkdm",
123 .rst_lines = omap3xxx_iva_resets,
124 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets),
125 .main_clk = "iva2_ck",
126 .prcm = {
127 .omap2 = {
128 .module_offs = OMAP3430_IVA2_MOD,
129 .prcm_reg_id = 1,
130 .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
131 .idlest_reg_id = 1,
132 .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
133 }
134 },
135 };
136
137 /*
138 * 'debugss' class
139 * debug and emulation sub system
140 */
141
142 static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = {
143 .name = "debugss",
144 };
145
146 /* debugss */
147 static struct omap_hwmod omap3xxx_debugss_hwmod = {
148 .name = "debugss",
149 .class = &omap3xxx_debugss_hwmod_class,
150 .clkdm_name = "emu_clkdm",
151 .main_clk = "emu_src_ck",
152 .flags = HWMOD_NO_IDLEST,
153 };
154
155 /* timer class */
156 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
157 .rev_offs = 0x0000,
158 .sysc_offs = 0x0010,
159 .syss_offs = 0x0014,
160 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
161 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
162 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
163 SYSS_HAS_RESET_STATUS),
164 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
165 .clockact = CLOCKACT_TEST_ICLK,
166 .sysc_fields = &omap_hwmod_sysc_type1,
167 };
168
169 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
170 .name = "timer",
171 .sysc = &omap3xxx_timer_sysc,
172 };
173
174 /* secure timers dev attribute */
175 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
176 .timer_capability = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE,
177 };
178
179 /* always-on timers dev attribute */
180 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
181 .timer_capability = OMAP_TIMER_ALWON,
182 };
183
184 /* pwm timers dev attribute */
185 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
186 .timer_capability = OMAP_TIMER_HAS_PWM,
187 };
188
189 /* timers with DSP interrupt dev attribute */
190 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
191 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
192 };
193
194 /* pwm timers with DSP interrupt dev attribute */
195 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
196 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
197 };
198
199 /* timer1 */
200 static struct omap_hwmod omap3xxx_timer1_hwmod = {
201 .name = "timer1",
202 .mpu_irqs = omap2_timer1_mpu_irqs,
203 .main_clk = "gpt1_fck",
204 .prcm = {
205 .omap2 = {
206 .prcm_reg_id = 1,
207 .module_bit = OMAP3430_EN_GPT1_SHIFT,
208 .module_offs = WKUP_MOD,
209 .idlest_reg_id = 1,
210 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
211 },
212 },
213 .dev_attr = &capability_alwon_dev_attr,
214 .class = &omap3xxx_timer_hwmod_class,
215 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
216 };
217
218 /* timer2 */
219 static struct omap_hwmod omap3xxx_timer2_hwmod = {
220 .name = "timer2",
221 .mpu_irqs = omap2_timer2_mpu_irqs,
222 .main_clk = "gpt2_fck",
223 .prcm = {
224 .omap2 = {
225 .prcm_reg_id = 1,
226 .module_bit = OMAP3430_EN_GPT2_SHIFT,
227 .module_offs = OMAP3430_PER_MOD,
228 .idlest_reg_id = 1,
229 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
230 },
231 },
232 .class = &omap3xxx_timer_hwmod_class,
233 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
234 };
235
236 /* timer3 */
237 static struct omap_hwmod omap3xxx_timer3_hwmod = {
238 .name = "timer3",
239 .mpu_irqs = omap2_timer3_mpu_irqs,
240 .main_clk = "gpt3_fck",
241 .prcm = {
242 .omap2 = {
243 .prcm_reg_id = 1,
244 .module_bit = OMAP3430_EN_GPT3_SHIFT,
245 .module_offs = OMAP3430_PER_MOD,
246 .idlest_reg_id = 1,
247 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
248 },
249 },
250 .class = &omap3xxx_timer_hwmod_class,
251 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
252 };
253
254 /* timer4 */
255 static struct omap_hwmod omap3xxx_timer4_hwmod = {
256 .name = "timer4",
257 .mpu_irqs = omap2_timer4_mpu_irqs,
258 .main_clk = "gpt4_fck",
259 .prcm = {
260 .omap2 = {
261 .prcm_reg_id = 1,
262 .module_bit = OMAP3430_EN_GPT4_SHIFT,
263 .module_offs = OMAP3430_PER_MOD,
264 .idlest_reg_id = 1,
265 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
266 },
267 },
268 .class = &omap3xxx_timer_hwmod_class,
269 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
270 };
271
272 /* timer5 */
273 static struct omap_hwmod omap3xxx_timer5_hwmod = {
274 .name = "timer5",
275 .mpu_irqs = omap2_timer5_mpu_irqs,
276 .main_clk = "gpt5_fck",
277 .prcm = {
278 .omap2 = {
279 .prcm_reg_id = 1,
280 .module_bit = OMAP3430_EN_GPT5_SHIFT,
281 .module_offs = OMAP3430_PER_MOD,
282 .idlest_reg_id = 1,
283 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
284 },
285 },
286 .dev_attr = &capability_dsp_dev_attr,
287 .class = &omap3xxx_timer_hwmod_class,
288 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
289 };
290
291 /* timer6 */
292 static struct omap_hwmod omap3xxx_timer6_hwmod = {
293 .name = "timer6",
294 .mpu_irqs = omap2_timer6_mpu_irqs,
295 .main_clk = "gpt6_fck",
296 .prcm = {
297 .omap2 = {
298 .prcm_reg_id = 1,
299 .module_bit = OMAP3430_EN_GPT6_SHIFT,
300 .module_offs = OMAP3430_PER_MOD,
301 .idlest_reg_id = 1,
302 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
303 },
304 },
305 .dev_attr = &capability_dsp_dev_attr,
306 .class = &omap3xxx_timer_hwmod_class,
307 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
308 };
309
310 /* timer7 */
311 static struct omap_hwmod omap3xxx_timer7_hwmod = {
312 .name = "timer7",
313 .mpu_irqs = omap2_timer7_mpu_irqs,
314 .main_clk = "gpt7_fck",
315 .prcm = {
316 .omap2 = {
317 .prcm_reg_id = 1,
318 .module_bit = OMAP3430_EN_GPT7_SHIFT,
319 .module_offs = OMAP3430_PER_MOD,
320 .idlest_reg_id = 1,
321 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
322 },
323 },
324 .dev_attr = &capability_dsp_dev_attr,
325 .class = &omap3xxx_timer_hwmod_class,
326 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
327 };
328
329 /* timer8 */
330 static struct omap_hwmod omap3xxx_timer8_hwmod = {
331 .name = "timer8",
332 .mpu_irqs = omap2_timer8_mpu_irqs,
333 .main_clk = "gpt8_fck",
334 .prcm = {
335 .omap2 = {
336 .prcm_reg_id = 1,
337 .module_bit = OMAP3430_EN_GPT8_SHIFT,
338 .module_offs = OMAP3430_PER_MOD,
339 .idlest_reg_id = 1,
340 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
341 },
342 },
343 .dev_attr = &capability_dsp_pwm_dev_attr,
344 .class = &omap3xxx_timer_hwmod_class,
345 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
346 };
347
348 /* timer9 */
349 static struct omap_hwmod omap3xxx_timer9_hwmod = {
350 .name = "timer9",
351 .mpu_irqs = omap2_timer9_mpu_irqs,
352 .main_clk = "gpt9_fck",
353 .prcm = {
354 .omap2 = {
355 .prcm_reg_id = 1,
356 .module_bit = OMAP3430_EN_GPT9_SHIFT,
357 .module_offs = OMAP3430_PER_MOD,
358 .idlest_reg_id = 1,
359 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
360 },
361 },
362 .dev_attr = &capability_pwm_dev_attr,
363 .class = &omap3xxx_timer_hwmod_class,
364 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
365 };
366
367 /* timer10 */
368 static struct omap_hwmod omap3xxx_timer10_hwmod = {
369 .name = "timer10",
370 .mpu_irqs = omap2_timer10_mpu_irqs,
371 .main_clk = "gpt10_fck",
372 .prcm = {
373 .omap2 = {
374 .prcm_reg_id = 1,
375 .module_bit = OMAP3430_EN_GPT10_SHIFT,
376 .module_offs = CORE_MOD,
377 .idlest_reg_id = 1,
378 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
379 },
380 },
381 .dev_attr = &capability_pwm_dev_attr,
382 .class = &omap3xxx_timer_hwmod_class,
383 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
384 };
385
386 /* timer11 */
387 static struct omap_hwmod omap3xxx_timer11_hwmod = {
388 .name = "timer11",
389 .mpu_irqs = omap2_timer11_mpu_irqs,
390 .main_clk = "gpt11_fck",
391 .prcm = {
392 .omap2 = {
393 .prcm_reg_id = 1,
394 .module_bit = OMAP3430_EN_GPT11_SHIFT,
395 .module_offs = CORE_MOD,
396 .idlest_reg_id = 1,
397 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
398 },
399 },
400 .dev_attr = &capability_pwm_dev_attr,
401 .class = &omap3xxx_timer_hwmod_class,
402 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
403 };
404
405 /* timer12 */
406 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
407 { .irq = 95 + OMAP_INTC_START, },
408 { .irq = -1 },
409 };
410
411 static struct omap_hwmod omap3xxx_timer12_hwmod = {
412 .name = "timer12",
413 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
414 .main_clk = "gpt12_fck",
415 .prcm = {
416 .omap2 = {
417 .prcm_reg_id = 1,
418 .module_bit = OMAP3430_EN_GPT12_SHIFT,
419 .module_offs = WKUP_MOD,
420 .idlest_reg_id = 1,
421 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
422 },
423 },
424 .dev_attr = &capability_secure_dev_attr,
425 .class = &omap3xxx_timer_hwmod_class,
426 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
427 };
428
429 /*
430 * 'wd_timer' class
431 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
432 * overflow condition
433 */
434
435 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
436 .rev_offs = 0x0000,
437 .sysc_offs = 0x0010,
438 .syss_offs = 0x0014,
439 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
440 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
441 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
442 SYSS_HAS_RESET_STATUS),
443 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
444 .sysc_fields = &omap_hwmod_sysc_type1,
445 };
446
447 /* I2C common */
448 static struct omap_hwmod_class_sysconfig i2c_sysc = {
449 .rev_offs = 0x00,
450 .sysc_offs = 0x20,
451 .syss_offs = 0x10,
452 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
453 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
454 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
455 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
456 .clockact = CLOCKACT_TEST_ICLK,
457 .sysc_fields = &omap_hwmod_sysc_type1,
458 };
459
460 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
461 .name = "wd_timer",
462 .sysc = &omap3xxx_wd_timer_sysc,
463 .pre_shutdown = &omap2_wd_timer_disable,
464 .reset = &omap2_wd_timer_reset,
465 };
466
467 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
468 .name = "wd_timer2",
469 .class = &omap3xxx_wd_timer_hwmod_class,
470 .main_clk = "wdt2_fck",
471 .prcm = {
472 .omap2 = {
473 .prcm_reg_id = 1,
474 .module_bit = OMAP3430_EN_WDT2_SHIFT,
475 .module_offs = WKUP_MOD,
476 .idlest_reg_id = 1,
477 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
478 },
479 },
480 /*
481 * XXX: Use software supervised mode, HW supervised smartidle seems to
482 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
483 */
484 .flags = HWMOD_SWSUP_SIDLE,
485 };
486
487 /* UART1 */
488 static struct omap_hwmod omap3xxx_uart1_hwmod = {
489 .name = "uart1",
490 .mpu_irqs = omap2_uart1_mpu_irqs,
491 .sdma_reqs = omap2_uart1_sdma_reqs,
492 .main_clk = "uart1_fck",
493 .prcm = {
494 .omap2 = {
495 .module_offs = CORE_MOD,
496 .prcm_reg_id = 1,
497 .module_bit = OMAP3430_EN_UART1_SHIFT,
498 .idlest_reg_id = 1,
499 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
500 },
501 },
502 .class = &omap2_uart_class,
503 };
504
505 /* UART2 */
506 static struct omap_hwmod omap3xxx_uart2_hwmod = {
507 .name = "uart2",
508 .mpu_irqs = omap2_uart2_mpu_irqs,
509 .sdma_reqs = omap2_uart2_sdma_reqs,
510 .main_clk = "uart2_fck",
511 .prcm = {
512 .omap2 = {
513 .module_offs = CORE_MOD,
514 .prcm_reg_id = 1,
515 .module_bit = OMAP3430_EN_UART2_SHIFT,
516 .idlest_reg_id = 1,
517 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
518 },
519 },
520 .class = &omap2_uart_class,
521 };
522
523 /* UART3 */
524 static struct omap_hwmod omap3xxx_uart3_hwmod = {
525 .name = "uart3",
526 .mpu_irqs = omap2_uart3_mpu_irqs,
527 .sdma_reqs = omap2_uart3_sdma_reqs,
528 .main_clk = "uart3_fck",
529 .prcm = {
530 .omap2 = {
531 .module_offs = OMAP3430_PER_MOD,
532 .prcm_reg_id = 1,
533 .module_bit = OMAP3430_EN_UART3_SHIFT,
534 .idlest_reg_id = 1,
535 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
536 },
537 },
538 .class = &omap2_uart_class,
539 };
540
541 /* UART4 */
542 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
543 { .irq = 80 + OMAP_INTC_START, },
544 { .irq = -1 },
545 };
546
547 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
548 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
549 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
550 { .dma_req = -1 }
551 };
552
553 static struct omap_hwmod omap36xx_uart4_hwmod = {
554 .name = "uart4",
555 .mpu_irqs = uart4_mpu_irqs,
556 .sdma_reqs = uart4_sdma_reqs,
557 .main_clk = "uart4_fck",
558 .prcm = {
559 .omap2 = {
560 .module_offs = OMAP3430_PER_MOD,
561 .prcm_reg_id = 1,
562 .module_bit = OMAP3630_EN_UART4_SHIFT,
563 .idlest_reg_id = 1,
564 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
565 },
566 },
567 .class = &omap2_uart_class,
568 };
569
570 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
571 { .irq = 84 + OMAP_INTC_START, },
572 { .irq = -1 },
573 };
574
575 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
576 { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
577 { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
578 { .dma_req = -1 }
579 };
580
581 /*
582 * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
583 * uart2_fck being enabled. So we add uart1_fck as an optional clock,
584 * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET. This really
585 * should not be needed. The functional clock structure of the AM35xx
586 * UART4 is extremely unclear and opaque; it is unclear what the role
587 * of uart1/2_fck is for the UART4. Any clarification from either
588 * empirical testing or the AM3505/3517 hardware designers would be
589 * most welcome.
590 */
591 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
592 { .role = "softreset_uart1_fck", .clk = "uart1_fck" },
593 };
594
595 static struct omap_hwmod am35xx_uart4_hwmod = {
596 .name = "uart4",
597 .mpu_irqs = am35xx_uart4_mpu_irqs,
598 .sdma_reqs = am35xx_uart4_sdma_reqs,
599 .main_clk = "uart4_fck",
600 .prcm = {
601 .omap2 = {
602 .module_offs = CORE_MOD,
603 .prcm_reg_id = 1,
604 .module_bit = AM35XX_EN_UART4_SHIFT,
605 .idlest_reg_id = 1,
606 .idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
607 },
608 },
609 .opt_clks = am35xx_uart4_opt_clks,
610 .opt_clks_cnt = ARRAY_SIZE(am35xx_uart4_opt_clks),
611 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
612 .class = &omap2_uart_class,
613 };
614
615 static struct omap_hwmod_class i2c_class = {
616 .name = "i2c",
617 .sysc = &i2c_sysc,
618 .rev = OMAP_I2C_IP_VERSION_1,
619 .reset = &omap_i2c_reset,
620 };
621
622 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
623 { .name = "dispc", .dma_req = 5 },
624 { .name = "dsi1", .dma_req = 74 },
625 { .dma_req = -1 }
626 };
627
628 /* dss */
629 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
630 /*
631 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
632 * driver does not use these clocks.
633 */
634 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
635 { .role = "tv_clk", .clk = "dss_tv_fck" },
636 /* required only on OMAP3430 */
637 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
638 };
639
640 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
641 .name = "dss_core",
642 .class = &omap2_dss_hwmod_class,
643 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
644 .sdma_reqs = omap3xxx_dss_sdma_chs,
645 .prcm = {
646 .omap2 = {
647 .prcm_reg_id = 1,
648 .module_bit = OMAP3430_EN_DSS1_SHIFT,
649 .module_offs = OMAP3430_DSS_MOD,
650 .idlest_reg_id = 1,
651 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
652 },
653 },
654 .opt_clks = dss_opt_clks,
655 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
656 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
657 };
658
659 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
660 .name = "dss_core",
661 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
662 .class = &omap2_dss_hwmod_class,
663 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
664 .sdma_reqs = omap3xxx_dss_sdma_chs,
665 .prcm = {
666 .omap2 = {
667 .prcm_reg_id = 1,
668 .module_bit = OMAP3430_EN_DSS1_SHIFT,
669 .module_offs = OMAP3430_DSS_MOD,
670 .idlest_reg_id = 1,
671 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
672 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
673 },
674 },
675 .opt_clks = dss_opt_clks,
676 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
677 };
678
679 /*
680 * 'dispc' class
681 * display controller
682 */
683
684 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
685 .rev_offs = 0x0000,
686 .sysc_offs = 0x0010,
687 .syss_offs = 0x0014,
688 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
689 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
690 SYSC_HAS_ENAWAKEUP),
691 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
692 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
693 .sysc_fields = &omap_hwmod_sysc_type1,
694 };
695
696 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
697 .name = "dispc",
698 .sysc = &omap3_dispc_sysc,
699 };
700
701 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
702 .name = "dss_dispc",
703 .class = &omap3_dispc_hwmod_class,
704 .mpu_irqs = omap2_dispc_irqs,
705 .main_clk = "dss1_alwon_fck",
706 .prcm = {
707 .omap2 = {
708 .prcm_reg_id = 1,
709 .module_bit = OMAP3430_EN_DSS1_SHIFT,
710 .module_offs = OMAP3430_DSS_MOD,
711 },
712 },
713 .flags = HWMOD_NO_IDLEST,
714 .dev_attr = &omap2_3_dss_dispc_dev_attr
715 };
716
717 /*
718 * 'dsi' class
719 * display serial interface controller
720 */
721
722 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
723 .name = "dsi",
724 };
725
726 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
727 { .irq = 25 + OMAP_INTC_START, },
728 { .irq = -1 },
729 };
730
731 /* dss_dsi1 */
732 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
733 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
734 };
735
736 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
737 .name = "dss_dsi1",
738 .class = &omap3xxx_dsi_hwmod_class,
739 .mpu_irqs = omap3xxx_dsi1_irqs,
740 .main_clk = "dss1_alwon_fck",
741 .prcm = {
742 .omap2 = {
743 .prcm_reg_id = 1,
744 .module_bit = OMAP3430_EN_DSS1_SHIFT,
745 .module_offs = OMAP3430_DSS_MOD,
746 },
747 },
748 .opt_clks = dss_dsi1_opt_clks,
749 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
750 .flags = HWMOD_NO_IDLEST,
751 };
752
753 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
754 { .role = "ick", .clk = "dss_ick" },
755 };
756
757 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
758 .name = "dss_rfbi",
759 .class = &omap2_rfbi_hwmod_class,
760 .main_clk = "dss1_alwon_fck",
761 .prcm = {
762 .omap2 = {
763 .prcm_reg_id = 1,
764 .module_bit = OMAP3430_EN_DSS1_SHIFT,
765 .module_offs = OMAP3430_DSS_MOD,
766 },
767 },
768 .opt_clks = dss_rfbi_opt_clks,
769 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
770 .flags = HWMOD_NO_IDLEST,
771 };
772
773 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
774 /* required only on OMAP3430 */
775 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
776 };
777
778 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
779 .name = "dss_venc",
780 .class = &omap2_venc_hwmod_class,
781 .main_clk = "dss_tv_fck",
782 .prcm = {
783 .omap2 = {
784 .prcm_reg_id = 1,
785 .module_bit = OMAP3430_EN_DSS1_SHIFT,
786 .module_offs = OMAP3430_DSS_MOD,
787 },
788 },
789 .opt_clks = dss_venc_opt_clks,
790 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
791 .flags = HWMOD_NO_IDLEST,
792 };
793
794 /* I2C1 */
795 static struct omap_i2c_dev_attr i2c1_dev_attr = {
796 .fifo_depth = 8, /* bytes */
797 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
798 };
799
800 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
801 .name = "i2c1",
802 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
803 .mpu_irqs = omap2_i2c1_mpu_irqs,
804 .sdma_reqs = omap2_i2c1_sdma_reqs,
805 .main_clk = "i2c1_fck",
806 .prcm = {
807 .omap2 = {
808 .module_offs = CORE_MOD,
809 .prcm_reg_id = 1,
810 .module_bit = OMAP3430_EN_I2C1_SHIFT,
811 .idlest_reg_id = 1,
812 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
813 },
814 },
815 .class = &i2c_class,
816 .dev_attr = &i2c1_dev_attr,
817 };
818
819 /* I2C2 */
820 static struct omap_i2c_dev_attr i2c2_dev_attr = {
821 .fifo_depth = 8, /* bytes */
822 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
823 };
824
825 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
826 .name = "i2c2",
827 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
828 .mpu_irqs = omap2_i2c2_mpu_irqs,
829 .sdma_reqs = omap2_i2c2_sdma_reqs,
830 .main_clk = "i2c2_fck",
831 .prcm = {
832 .omap2 = {
833 .module_offs = CORE_MOD,
834 .prcm_reg_id = 1,
835 .module_bit = OMAP3430_EN_I2C2_SHIFT,
836 .idlest_reg_id = 1,
837 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
838 },
839 },
840 .class = &i2c_class,
841 .dev_attr = &i2c2_dev_attr,
842 };
843
844 /* I2C3 */
845 static struct omap_i2c_dev_attr i2c3_dev_attr = {
846 .fifo_depth = 64, /* bytes */
847 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
848 };
849
850 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
851 { .irq = 61 + OMAP_INTC_START, },
852 { .irq = -1 },
853 };
854
855 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
856 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
857 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
858 { .dma_req = -1 }
859 };
860
861 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
862 .name = "i2c3",
863 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
864 .mpu_irqs = i2c3_mpu_irqs,
865 .sdma_reqs = i2c3_sdma_reqs,
866 .main_clk = "i2c3_fck",
867 .prcm = {
868 .omap2 = {
869 .module_offs = CORE_MOD,
870 .prcm_reg_id = 1,
871 .module_bit = OMAP3430_EN_I2C3_SHIFT,
872 .idlest_reg_id = 1,
873 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
874 },
875 },
876 .class = &i2c_class,
877 .dev_attr = &i2c3_dev_attr,
878 };
879
880 /*
881 * 'gpio' class
882 * general purpose io module
883 */
884
885 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
886 .rev_offs = 0x0000,
887 .sysc_offs = 0x0010,
888 .syss_offs = 0x0014,
889 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
890 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
891 SYSS_HAS_RESET_STATUS),
892 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
893 .sysc_fields = &omap_hwmod_sysc_type1,
894 };
895
896 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
897 .name = "gpio",
898 .sysc = &omap3xxx_gpio_sysc,
899 .rev = 1,
900 };
901
902 /* gpio_dev_attr */
903 static struct omap_gpio_dev_attr gpio_dev_attr = {
904 .bank_width = 32,
905 .dbck_flag = true,
906 };
907
908 /* gpio1 */
909 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
910 { .role = "dbclk", .clk = "gpio1_dbck", },
911 };
912
913 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
914 .name = "gpio1",
915 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
916 .mpu_irqs = omap2_gpio1_irqs,
917 .main_clk = "gpio1_ick",
918 .opt_clks = gpio1_opt_clks,
919 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
920 .prcm = {
921 .omap2 = {
922 .prcm_reg_id = 1,
923 .module_bit = OMAP3430_EN_GPIO1_SHIFT,
924 .module_offs = WKUP_MOD,
925 .idlest_reg_id = 1,
926 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
927 },
928 },
929 .class = &omap3xxx_gpio_hwmod_class,
930 .dev_attr = &gpio_dev_attr,
931 };
932
933 /* gpio2 */
934 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
935 { .role = "dbclk", .clk = "gpio2_dbck", },
936 };
937
938 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
939 .name = "gpio2",
940 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
941 .mpu_irqs = omap2_gpio2_irqs,
942 .main_clk = "gpio2_ick",
943 .opt_clks = gpio2_opt_clks,
944 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
945 .prcm = {
946 .omap2 = {
947 .prcm_reg_id = 1,
948 .module_bit = OMAP3430_EN_GPIO2_SHIFT,
949 .module_offs = OMAP3430_PER_MOD,
950 .idlest_reg_id = 1,
951 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
952 },
953 },
954 .class = &omap3xxx_gpio_hwmod_class,
955 .dev_attr = &gpio_dev_attr,
956 };
957
958 /* gpio3 */
959 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
960 { .role = "dbclk", .clk = "gpio3_dbck", },
961 };
962
963 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
964 .name = "gpio3",
965 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
966 .mpu_irqs = omap2_gpio3_irqs,
967 .main_clk = "gpio3_ick",
968 .opt_clks = gpio3_opt_clks,
969 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
970 .prcm = {
971 .omap2 = {
972 .prcm_reg_id = 1,
973 .module_bit = OMAP3430_EN_GPIO3_SHIFT,
974 .module_offs = OMAP3430_PER_MOD,
975 .idlest_reg_id = 1,
976 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
977 },
978 },
979 .class = &omap3xxx_gpio_hwmod_class,
980 .dev_attr = &gpio_dev_attr,
981 };
982
983 /* gpio4 */
984 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
985 { .role = "dbclk", .clk = "gpio4_dbck", },
986 };
987
988 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
989 .name = "gpio4",
990 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
991 .mpu_irqs = omap2_gpio4_irqs,
992 .main_clk = "gpio4_ick",
993 .opt_clks = gpio4_opt_clks,
994 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
995 .prcm = {
996 .omap2 = {
997 .prcm_reg_id = 1,
998 .module_bit = OMAP3430_EN_GPIO4_SHIFT,
999 .module_offs = OMAP3430_PER_MOD,
1000 .idlest_reg_id = 1,
1001 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
1002 },
1003 },
1004 .class = &omap3xxx_gpio_hwmod_class,
1005 .dev_attr = &gpio_dev_attr,
1006 };
1007
1008 /* gpio5 */
1009 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
1010 { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */
1011 { .irq = -1 },
1012 };
1013
1014 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1015 { .role = "dbclk", .clk = "gpio5_dbck", },
1016 };
1017
1018 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
1019 .name = "gpio5",
1020 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1021 .mpu_irqs = omap3xxx_gpio5_irqs,
1022 .main_clk = "gpio5_ick",
1023 .opt_clks = gpio5_opt_clks,
1024 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1025 .prcm = {
1026 .omap2 = {
1027 .prcm_reg_id = 1,
1028 .module_bit = OMAP3430_EN_GPIO5_SHIFT,
1029 .module_offs = OMAP3430_PER_MOD,
1030 .idlest_reg_id = 1,
1031 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
1032 },
1033 },
1034 .class = &omap3xxx_gpio_hwmod_class,
1035 .dev_attr = &gpio_dev_attr,
1036 };
1037
1038 /* gpio6 */
1039 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
1040 { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */
1041 { .irq = -1 },
1042 };
1043
1044 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1045 { .role = "dbclk", .clk = "gpio6_dbck", },
1046 };
1047
1048 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
1049 .name = "gpio6",
1050 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1051 .mpu_irqs = omap3xxx_gpio6_irqs,
1052 .main_clk = "gpio6_ick",
1053 .opt_clks = gpio6_opt_clks,
1054 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1055 .prcm = {
1056 .omap2 = {
1057 .prcm_reg_id = 1,
1058 .module_bit = OMAP3430_EN_GPIO6_SHIFT,
1059 .module_offs = OMAP3430_PER_MOD,
1060 .idlest_reg_id = 1,
1061 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
1062 },
1063 },
1064 .class = &omap3xxx_gpio_hwmod_class,
1065 .dev_attr = &gpio_dev_attr,
1066 };
1067
1068 /* dma attributes */
1069 static struct omap_dma_dev_attr dma_dev_attr = {
1070 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1071 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1072 .lch_count = 32,
1073 };
1074
1075 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1076 .rev_offs = 0x0000,
1077 .sysc_offs = 0x002c,
1078 .syss_offs = 0x0028,
1079 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1080 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1081 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
1082 SYSS_HAS_RESET_STATUS),
1083 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1084 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1085 .sysc_fields = &omap_hwmod_sysc_type1,
1086 };
1087
1088 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1089 .name = "dma",
1090 .sysc = &omap3xxx_dma_sysc,
1091 };
1092
1093 /* dma_system */
1094 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1095 .name = "dma",
1096 .class = &omap3xxx_dma_hwmod_class,
1097 .mpu_irqs = omap2_dma_system_irqs,
1098 .main_clk = "core_l3_ick",
1099 .prcm = {
1100 .omap2 = {
1101 .module_offs = CORE_MOD,
1102 .prcm_reg_id = 1,
1103 .module_bit = OMAP3430_ST_SDMA_SHIFT,
1104 .idlest_reg_id = 1,
1105 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
1106 },
1107 },
1108 .dev_attr = &dma_dev_attr,
1109 .flags = HWMOD_NO_IDLEST,
1110 };
1111
1112 /*
1113 * 'mcbsp' class
1114 * multi channel buffered serial port controller
1115 */
1116
1117 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
1118 .sysc_offs = 0x008c,
1119 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1120 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1121 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1122 .sysc_fields = &omap_hwmod_sysc_type1,
1123 .clockact = 0x2,
1124 };
1125
1126 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1127 .name = "mcbsp",
1128 .sysc = &omap3xxx_mcbsp_sysc,
1129 .rev = MCBSP_CONFIG_TYPE3,
1130 };
1131
1132 /* McBSP functional clock mapping */
1133 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
1134 { .role = "pad_fck", .clk = "mcbsp_clks" },
1135 { .role = "prcm_fck", .clk = "core_96m_fck" },
1136 };
1137
1138 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
1139 { .role = "pad_fck", .clk = "mcbsp_clks" },
1140 { .role = "prcm_fck", .clk = "per_96m_fck" },
1141 };
1142
1143 /* mcbsp1 */
1144 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
1145 { .name = "common", .irq = 16 + OMAP_INTC_START, },
1146 { .name = "tx", .irq = 59 + OMAP_INTC_START, },
1147 { .name = "rx", .irq = 60 + OMAP_INTC_START, },
1148 { .irq = -1 },
1149 };
1150
1151 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1152 .name = "mcbsp1",
1153 .class = &omap3xxx_mcbsp_hwmod_class,
1154 .mpu_irqs = omap3xxx_mcbsp1_irqs,
1155 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
1156 .main_clk = "mcbsp1_fck",
1157 .prcm = {
1158 .omap2 = {
1159 .prcm_reg_id = 1,
1160 .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
1161 .module_offs = CORE_MOD,
1162 .idlest_reg_id = 1,
1163 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
1164 },
1165 },
1166 .opt_clks = mcbsp15_opt_clks,
1167 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
1168 };
1169
1170 /* mcbsp2 */
1171 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
1172 { .name = "common", .irq = 17 + OMAP_INTC_START, },
1173 { .name = "tx", .irq = 62 + OMAP_INTC_START, },
1174 { .name = "rx", .irq = 63 + OMAP_INTC_START, },
1175 { .irq = -1 },
1176 };
1177
1178 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1179 .sidetone = "mcbsp2_sidetone",
1180 };
1181
1182 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1183 .name = "mcbsp2",
1184 .class = &omap3xxx_mcbsp_hwmod_class,
1185 .mpu_irqs = omap3xxx_mcbsp2_irqs,
1186 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
1187 .main_clk = "mcbsp2_fck",
1188 .prcm = {
1189 .omap2 = {
1190 .prcm_reg_id = 1,
1191 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1192 .module_offs = OMAP3430_PER_MOD,
1193 .idlest_reg_id = 1,
1194 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1195 },
1196 },
1197 .opt_clks = mcbsp234_opt_clks,
1198 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1199 .dev_attr = &omap34xx_mcbsp2_dev_attr,
1200 };
1201
1202 /* mcbsp3 */
1203 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
1204 { .name = "common", .irq = 22 + OMAP_INTC_START, },
1205 { .name = "tx", .irq = 89 + OMAP_INTC_START, },
1206 { .name = "rx", .irq = 90 + OMAP_INTC_START, },
1207 { .irq = -1 },
1208 };
1209
1210 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1211 .sidetone = "mcbsp3_sidetone",
1212 };
1213
1214 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1215 .name = "mcbsp3",
1216 .class = &omap3xxx_mcbsp_hwmod_class,
1217 .mpu_irqs = omap3xxx_mcbsp3_irqs,
1218 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
1219 .main_clk = "mcbsp3_fck",
1220 .prcm = {
1221 .omap2 = {
1222 .prcm_reg_id = 1,
1223 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1224 .module_offs = OMAP3430_PER_MOD,
1225 .idlest_reg_id = 1,
1226 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1227 },
1228 },
1229 .opt_clks = mcbsp234_opt_clks,
1230 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1231 .dev_attr = &omap34xx_mcbsp3_dev_attr,
1232 };
1233
1234 /* mcbsp4 */
1235 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
1236 { .name = "common", .irq = 23 + OMAP_INTC_START, },
1237 { .name = "tx", .irq = 54 + OMAP_INTC_START, },
1238 { .name = "rx", .irq = 55 + OMAP_INTC_START, },
1239 { .irq = -1 },
1240 };
1241
1242 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
1243 { .name = "rx", .dma_req = 20 },
1244 { .name = "tx", .dma_req = 19 },
1245 { .dma_req = -1 }
1246 };
1247
1248 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1249 .name = "mcbsp4",
1250 .class = &omap3xxx_mcbsp_hwmod_class,
1251 .mpu_irqs = omap3xxx_mcbsp4_irqs,
1252 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
1253 .main_clk = "mcbsp4_fck",
1254 .prcm = {
1255 .omap2 = {
1256 .prcm_reg_id = 1,
1257 .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
1258 .module_offs = OMAP3430_PER_MOD,
1259 .idlest_reg_id = 1,
1260 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
1261 },
1262 },
1263 .opt_clks = mcbsp234_opt_clks,
1264 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1265 };
1266
1267 /* mcbsp5 */
1268 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
1269 { .name = "common", .irq = 27 + OMAP_INTC_START, },
1270 { .name = "tx", .irq = 81 + OMAP_INTC_START, },
1271 { .name = "rx", .irq = 82 + OMAP_INTC_START, },
1272 { .irq = -1 },
1273 };
1274
1275 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
1276 { .name = "rx", .dma_req = 22 },
1277 { .name = "tx", .dma_req = 21 },
1278 { .dma_req = -1 }
1279 };
1280
1281 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1282 .name = "mcbsp5",
1283 .class = &omap3xxx_mcbsp_hwmod_class,
1284 .mpu_irqs = omap3xxx_mcbsp5_irqs,
1285 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
1286 .main_clk = "mcbsp5_fck",
1287 .prcm = {
1288 .omap2 = {
1289 .prcm_reg_id = 1,
1290 .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
1291 .module_offs = CORE_MOD,
1292 .idlest_reg_id = 1,
1293 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
1294 },
1295 },
1296 .opt_clks = mcbsp15_opt_clks,
1297 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
1298 };
1299
1300 /* 'mcbsp sidetone' class */
1301 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
1302 .sysc_offs = 0x0010,
1303 .sysc_flags = SYSC_HAS_AUTOIDLE,
1304 .sysc_fields = &omap_hwmod_sysc_type1,
1305 };
1306
1307 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
1308 .name = "mcbsp_sidetone",
1309 .sysc = &omap3xxx_mcbsp_sidetone_sysc,
1310 };
1311
1312 /* mcbsp2_sidetone */
1313 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
1314 { .name = "irq", .irq = 4 + OMAP_INTC_START, },
1315 { .irq = -1 },
1316 };
1317
1318 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1319 .name = "mcbsp2_sidetone",
1320 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1321 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
1322 .main_clk = "mcbsp2_fck",
1323 .prcm = {
1324 .omap2 = {
1325 .prcm_reg_id = 1,
1326 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1327 .module_offs = OMAP3430_PER_MOD,
1328 .idlest_reg_id = 1,
1329 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1330 },
1331 },
1332 };
1333
1334 /* mcbsp3_sidetone */
1335 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
1336 { .name = "irq", .irq = 5 + OMAP_INTC_START, },
1337 { .irq = -1 },
1338 };
1339
1340 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1341 .name = "mcbsp3_sidetone",
1342 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1343 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
1344 .main_clk = "mcbsp3_fck",
1345 .prcm = {
1346 .omap2 = {
1347 .prcm_reg_id = 1,
1348 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1349 .module_offs = OMAP3430_PER_MOD,
1350 .idlest_reg_id = 1,
1351 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1352 },
1353 },
1354 };
1355
1356 /* SR common */
1357 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1358 .clkact_shift = 20,
1359 };
1360
1361 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1362 .sysc_offs = 0x24,
1363 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1364 .clockact = CLOCKACT_TEST_ICLK,
1365 .sysc_fields = &omap34xx_sr_sysc_fields,
1366 };
1367
1368 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1369 .name = "smartreflex",
1370 .sysc = &omap34xx_sr_sysc,
1371 .rev = 1,
1372 };
1373
1374 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
1375 .sidle_shift = 24,
1376 .enwkup_shift = 26,
1377 };
1378
1379 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1380 .sysc_offs = 0x38,
1381 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1382 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1383 SYSC_NO_CACHE),
1384 .sysc_fields = &omap36xx_sr_sysc_fields,
1385 };
1386
1387 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1388 .name = "smartreflex",
1389 .sysc = &omap36xx_sr_sysc,
1390 .rev = 2,
1391 };
1392
1393 /* SR1 */
1394 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1395 .sensor_voltdm_name = "mpu_iva",
1396 };
1397
1398 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
1399 { .irq = 18 + OMAP_INTC_START, },
1400 { .irq = -1 },
1401 };
1402
1403 static struct omap_hwmod omap34xx_sr1_hwmod = {
1404 .name = "smartreflex_mpu_iva",
1405 .class = &omap34xx_smartreflex_hwmod_class,
1406 .main_clk = "sr1_fck",
1407 .prcm = {
1408 .omap2 = {
1409 .prcm_reg_id = 1,
1410 .module_bit = OMAP3430_EN_SR1_SHIFT,
1411 .module_offs = WKUP_MOD,
1412 .idlest_reg_id = 1,
1413 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1414 },
1415 },
1416 .dev_attr = &sr1_dev_attr,
1417 .mpu_irqs = omap3_smartreflex_mpu_irqs,
1418 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1419 };
1420
1421 static struct omap_hwmod omap36xx_sr1_hwmod = {
1422 .name = "smartreflex_mpu_iva",
1423 .class = &omap36xx_smartreflex_hwmod_class,
1424 .main_clk = "sr1_fck",
1425 .prcm = {
1426 .omap2 = {
1427 .prcm_reg_id = 1,
1428 .module_bit = OMAP3430_EN_SR1_SHIFT,
1429 .module_offs = WKUP_MOD,
1430 .idlest_reg_id = 1,
1431 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1432 },
1433 },
1434 .dev_attr = &sr1_dev_attr,
1435 .mpu_irqs = omap3_smartreflex_mpu_irqs,
1436 };
1437
1438 /* SR2 */
1439 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1440 .sensor_voltdm_name = "core",
1441 };
1442
1443 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
1444 { .irq = 19 + OMAP_INTC_START, },
1445 { .irq = -1 },
1446 };
1447
1448 static struct omap_hwmod omap34xx_sr2_hwmod = {
1449 .name = "smartreflex_core",
1450 .class = &omap34xx_smartreflex_hwmod_class,
1451 .main_clk = "sr2_fck",
1452 .prcm = {
1453 .omap2 = {
1454 .prcm_reg_id = 1,
1455 .module_bit = OMAP3430_EN_SR2_SHIFT,
1456 .module_offs = WKUP_MOD,
1457 .idlest_reg_id = 1,
1458 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1459 },
1460 },
1461 .dev_attr = &sr2_dev_attr,
1462 .mpu_irqs = omap3_smartreflex_core_irqs,
1463 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1464 };
1465
1466 static struct omap_hwmod omap36xx_sr2_hwmod = {
1467 .name = "smartreflex_core",
1468 .class = &omap36xx_smartreflex_hwmod_class,
1469 .main_clk = "sr2_fck",
1470 .prcm = {
1471 .omap2 = {
1472 .prcm_reg_id = 1,
1473 .module_bit = OMAP3430_EN_SR2_SHIFT,
1474 .module_offs = WKUP_MOD,
1475 .idlest_reg_id = 1,
1476 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1477 },
1478 },
1479 .dev_attr = &sr2_dev_attr,
1480 .mpu_irqs = omap3_smartreflex_core_irqs,
1481 };
1482
1483 /*
1484 * 'mailbox' class
1485 * mailbox module allowing communication between the on-chip processors
1486 * using a queued mailbox-interrupt mechanism.
1487 */
1488
1489 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1490 .rev_offs = 0x000,
1491 .sysc_offs = 0x010,
1492 .syss_offs = 0x014,
1493 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1494 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1495 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1496 .sysc_fields = &omap_hwmod_sysc_type1,
1497 };
1498
1499 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1500 .name = "mailbox",
1501 .sysc = &omap3xxx_mailbox_sysc,
1502 };
1503
1504 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
1505 { .irq = 26 + OMAP_INTC_START, },
1506 { .irq = -1 },
1507 };
1508
1509 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1510 .name = "mailbox",
1511 .class = &omap3xxx_mailbox_hwmod_class,
1512 .mpu_irqs = omap3xxx_mailbox_irqs,
1513 .main_clk = "mailboxes_ick",
1514 .prcm = {
1515 .omap2 = {
1516 .prcm_reg_id = 1,
1517 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1518 .module_offs = CORE_MOD,
1519 .idlest_reg_id = 1,
1520 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1521 },
1522 },
1523 };
1524
1525 /*
1526 * 'mcspi' class
1527 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1528 * bus
1529 */
1530
1531 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1532 .rev_offs = 0x0000,
1533 .sysc_offs = 0x0010,
1534 .syss_offs = 0x0014,
1535 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1536 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1537 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1538 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1539 .sysc_fields = &omap_hwmod_sysc_type1,
1540 };
1541
1542 static struct omap_hwmod_class omap34xx_mcspi_class = {
1543 .name = "mcspi",
1544 .sysc = &omap34xx_mcspi_sysc,
1545 .rev = OMAP3_MCSPI_REV,
1546 };
1547
1548 /* mcspi1 */
1549 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1550 .num_chipselect = 4,
1551 };
1552
1553 static struct omap_hwmod omap34xx_mcspi1 = {
1554 .name = "mcspi1",
1555 .mpu_irqs = omap2_mcspi1_mpu_irqs,
1556 .sdma_reqs = omap2_mcspi1_sdma_reqs,
1557 .main_clk = "mcspi1_fck",
1558 .prcm = {
1559 .omap2 = {
1560 .module_offs = CORE_MOD,
1561 .prcm_reg_id = 1,
1562 .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
1563 .idlest_reg_id = 1,
1564 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1565 },
1566 },
1567 .class = &omap34xx_mcspi_class,
1568 .dev_attr = &omap_mcspi1_dev_attr,
1569 };
1570
1571 /* mcspi2 */
1572 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1573 .num_chipselect = 2,
1574 };
1575
1576 static struct omap_hwmod omap34xx_mcspi2 = {
1577 .name = "mcspi2",
1578 .mpu_irqs = omap2_mcspi2_mpu_irqs,
1579 .sdma_reqs = omap2_mcspi2_sdma_reqs,
1580 .main_clk = "mcspi2_fck",
1581 .prcm = {
1582 .omap2 = {
1583 .module_offs = CORE_MOD,
1584 .prcm_reg_id = 1,
1585 .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
1586 .idlest_reg_id = 1,
1587 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1588 },
1589 },
1590 .class = &omap34xx_mcspi_class,
1591 .dev_attr = &omap_mcspi2_dev_attr,
1592 };
1593
1594 /* mcspi3 */
1595 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
1596 { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */
1597 { .irq = -1 },
1598 };
1599
1600 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
1601 { .name = "tx0", .dma_req = 15 },
1602 { .name = "rx0", .dma_req = 16 },
1603 { .name = "tx1", .dma_req = 23 },
1604 { .name = "rx1", .dma_req = 24 },
1605 { .dma_req = -1 }
1606 };
1607
1608 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1609 .num_chipselect = 2,
1610 };
1611
1612 static struct omap_hwmod omap34xx_mcspi3 = {
1613 .name = "mcspi3",
1614 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
1615 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
1616 .main_clk = "mcspi3_fck",
1617 .prcm = {
1618 .omap2 = {
1619 .module_offs = CORE_MOD,
1620 .prcm_reg_id = 1,
1621 .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
1622 .idlest_reg_id = 1,
1623 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1624 },
1625 },
1626 .class = &omap34xx_mcspi_class,
1627 .dev_attr = &omap_mcspi3_dev_attr,
1628 };
1629
1630 /* mcspi4 */
1631 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
1632 { .name = "irq", .irq = 48 + OMAP_INTC_START, },
1633 { .irq = -1 },
1634 };
1635
1636 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
1637 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
1638 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
1639 { .dma_req = -1 }
1640 };
1641
1642 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1643 .num_chipselect = 1,
1644 };
1645
1646 static struct omap_hwmod omap34xx_mcspi4 = {
1647 .name = "mcspi4",
1648 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
1649 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
1650 .main_clk = "mcspi4_fck",
1651 .prcm = {
1652 .omap2 = {
1653 .module_offs = CORE_MOD,
1654 .prcm_reg_id = 1,
1655 .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
1656 .idlest_reg_id = 1,
1657 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1658 },
1659 },
1660 .class = &omap34xx_mcspi_class,
1661 .dev_attr = &omap_mcspi4_dev_attr,
1662 };
1663
1664 /* usbhsotg */
1665 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1666 .rev_offs = 0x0400,
1667 .sysc_offs = 0x0404,
1668 .syss_offs = 0x0408,
1669 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1670 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1671 SYSC_HAS_AUTOIDLE),
1672 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1673 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1674 .sysc_fields = &omap_hwmod_sysc_type1,
1675 };
1676
1677 static struct omap_hwmod_class usbotg_class = {
1678 .name = "usbotg",
1679 .sysc = &omap3xxx_usbhsotg_sysc,
1680 };
1681
1682 /* usb_otg_hs */
1683 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
1684
1685 { .name = "mc", .irq = 92 + OMAP_INTC_START, },
1686 { .name = "dma", .irq = 93 + OMAP_INTC_START, },
1687 { .irq = -1 },
1688 };
1689
1690 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1691 .name = "usb_otg_hs",
1692 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
1693 .main_clk = "hsotgusb_ick",
1694 .prcm = {
1695 .omap2 = {
1696 .prcm_reg_id = 1,
1697 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1698 .module_offs = CORE_MOD,
1699 .idlest_reg_id = 1,
1700 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1701 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
1702 },
1703 },
1704 .class = &usbotg_class,
1705
1706 /*
1707 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
1708 * broken when autoidle is enabled
1709 * workaround is to disable the autoidle bit at module level.
1710 *
1711 * Enabling the device in any other MIDLEMODE setting but force-idle
1712 * causes core_pwrdm not enter idle states at least on OMAP3630.
1713 * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY
1714 * signal when MIDLEMODE is set to force-idle.
1715 */
1716 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
1717 | HWMOD_FORCE_MSTANDBY,
1718 };
1719
1720 /* usb_otg_hs */
1721 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
1722 { .name = "mc", .irq = 71 + OMAP_INTC_START, },
1723 { .irq = -1 },
1724 };
1725
1726 static struct omap_hwmod_class am35xx_usbotg_class = {
1727 .name = "am35xx_usbotg",
1728 };
1729
1730 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1731 .name = "am35x_otg_hs",
1732 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
1733 .main_clk = "hsotgusb_fck",
1734 .class = &am35xx_usbotg_class,
1735 .flags = HWMOD_NO_IDLEST,
1736 };
1737
1738 /* MMC/SD/SDIO common */
1739 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1740 .rev_offs = 0x1fc,
1741 .sysc_offs = 0x10,
1742 .syss_offs = 0x14,
1743 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1744 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1745 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1746 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1747 .sysc_fields = &omap_hwmod_sysc_type1,
1748 };
1749
1750 static struct omap_hwmod_class omap34xx_mmc_class = {
1751 .name = "mmc",
1752 .sysc = &omap34xx_mmc_sysc,
1753 };
1754
1755 /* MMC/SD/SDIO1 */
1756
1757 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
1758 { .irq = 83 + OMAP_INTC_START, },
1759 { .irq = -1 },
1760 };
1761
1762 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
1763 { .name = "tx", .dma_req = 61, },
1764 { .name = "rx", .dma_req = 62, },
1765 { .dma_req = -1 }
1766 };
1767
1768 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1769 { .role = "dbck", .clk = "omap_32k_fck", },
1770 };
1771
1772 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1773 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1774 };
1775
1776 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1777 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
1778 .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1779 OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1780 };
1781
1782 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1783 .name = "mmc1",
1784 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
1785 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
1786 .opt_clks = omap34xx_mmc1_opt_clks,
1787 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1788 .main_clk = "mmchs1_fck",
1789 .prcm = {
1790 .omap2 = {
1791 .module_offs = CORE_MOD,
1792 .prcm_reg_id = 1,
1793 .module_bit = OMAP3430_EN_MMC1_SHIFT,
1794 .idlest_reg_id = 1,
1795 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1796 },
1797 },
1798 .dev_attr = &mmc1_pre_es3_dev_attr,
1799 .class = &omap34xx_mmc_class,
1800 };
1801
1802 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1803 .name = "mmc1",
1804 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
1805 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
1806 .opt_clks = omap34xx_mmc1_opt_clks,
1807 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1808 .main_clk = "mmchs1_fck",
1809 .prcm = {
1810 .omap2 = {
1811 .module_offs = CORE_MOD,
1812 .prcm_reg_id = 1,
1813 .module_bit = OMAP3430_EN_MMC1_SHIFT,
1814 .idlest_reg_id = 1,
1815 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1816 },
1817 },
1818 .dev_attr = &mmc1_dev_attr,
1819 .class = &omap34xx_mmc_class,
1820 };
1821
1822 /* MMC/SD/SDIO2 */
1823
1824 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
1825 { .irq = 86 + OMAP_INTC_START, },
1826 { .irq = -1 },
1827 };
1828
1829 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
1830 { .name = "tx", .dma_req = 47, },
1831 { .name = "rx", .dma_req = 48, },
1832 { .dma_req = -1 }
1833 };
1834
1835 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1836 { .role = "dbck", .clk = "omap_32k_fck", },
1837 };
1838
1839 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1840 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
1841 .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1842 };
1843
1844 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1845 .name = "mmc2",
1846 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
1847 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
1848 .opt_clks = omap34xx_mmc2_opt_clks,
1849 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1850 .main_clk = "mmchs2_fck",
1851 .prcm = {
1852 .omap2 = {
1853 .module_offs = CORE_MOD,
1854 .prcm_reg_id = 1,
1855 .module_bit = OMAP3430_EN_MMC2_SHIFT,
1856 .idlest_reg_id = 1,
1857 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1858 },
1859 },
1860 .dev_attr = &mmc2_pre_es3_dev_attr,
1861 .class = &omap34xx_mmc_class,
1862 };
1863
1864 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1865 .name = "mmc2",
1866 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
1867 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
1868 .opt_clks = omap34xx_mmc2_opt_clks,
1869 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1870 .main_clk = "mmchs2_fck",
1871 .prcm = {
1872 .omap2 = {
1873 .module_offs = CORE_MOD,
1874 .prcm_reg_id = 1,
1875 .module_bit = OMAP3430_EN_MMC2_SHIFT,
1876 .idlest_reg_id = 1,
1877 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1878 },
1879 },
1880 .class = &omap34xx_mmc_class,
1881 };
1882
1883 /* MMC/SD/SDIO3 */
1884
1885 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
1886 { .irq = 94 + OMAP_INTC_START, },
1887 { .irq = -1 },
1888 };
1889
1890 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
1891 { .name = "tx", .dma_req = 77, },
1892 { .name = "rx", .dma_req = 78, },
1893 { .dma_req = -1 }
1894 };
1895
1896 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1897 { .role = "dbck", .clk = "omap_32k_fck", },
1898 };
1899
1900 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1901 .name = "mmc3",
1902 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
1903 .sdma_reqs = omap34xx_mmc3_sdma_reqs,
1904 .opt_clks = omap34xx_mmc3_opt_clks,
1905 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1906 .main_clk = "mmchs3_fck",
1907 .prcm = {
1908 .omap2 = {
1909 .prcm_reg_id = 1,
1910 .module_bit = OMAP3430_EN_MMC3_SHIFT,
1911 .idlest_reg_id = 1,
1912 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1913 },
1914 },
1915 .class = &omap34xx_mmc_class,
1916 };
1917
1918 /*
1919 * 'usb_host_hs' class
1920 * high-speed multi-port usb host controller
1921 */
1922
1923 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1924 .rev_offs = 0x0000,
1925 .sysc_offs = 0x0010,
1926 .syss_offs = 0x0014,
1927 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1928 SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1929 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1930 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1931 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1932 .sysc_fields = &omap_hwmod_sysc_type1,
1933 };
1934
1935 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1936 .name = "usb_host_hs",
1937 .sysc = &omap3xxx_usb_host_hs_sysc,
1938 };
1939
1940 static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
1941 { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
1942 };
1943
1944 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
1945 { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, },
1946 { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, },
1947 { .irq = -1 },
1948 };
1949
1950 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1951 .name = "usb_host_hs",
1952 .class = &omap3xxx_usb_host_hs_hwmod_class,
1953 .clkdm_name = "l3_init_clkdm",
1954 .mpu_irqs = omap3xxx_usb_host_hs_irqs,
1955 .main_clk = "usbhost_48m_fck",
1956 .prcm = {
1957 .omap2 = {
1958 .module_offs = OMAP3430ES2_USBHOST_MOD,
1959 .prcm_reg_id = 1,
1960 .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
1961 .idlest_reg_id = 1,
1962 .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1963 .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
1964 },
1965 },
1966 .opt_clks = omap3xxx_usb_host_hs_opt_clks,
1967 .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
1968
1969 /*
1970 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1971 * id: i660
1972 *
1973 * Description:
1974 * In the following configuration :
1975 * - USBHOST module is set to smart-idle mode
1976 * - PRCM asserts idle_req to the USBHOST module ( This typically
1977 * happens when the system is going to a low power mode : all ports
1978 * have been suspended, the master part of the USBHOST module has
1979 * entered the standby state, and SW has cut the functional clocks)
1980 * - an USBHOST interrupt occurs before the module is able to answer
1981 * idle_ack, typically a remote wakeup IRQ.
1982 * Then the USB HOST module will enter a deadlock situation where it
1983 * is no more accessible nor functional.
1984 *
1985 * Workaround:
1986 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1987 */
1988
1989 /*
1990 * Errata: USB host EHCI may stall when entering smart-standby mode
1991 * Id: i571
1992 *
1993 * Description:
1994 * When the USBHOST module is set to smart-standby mode, and when it is
1995 * ready to enter the standby state (i.e. all ports are suspended and
1996 * all attached devices are in suspend mode), then it can wrongly assert
1997 * the Mstandby signal too early while there are still some residual OCP
1998 * transactions ongoing. If this condition occurs, the internal state
1999 * machine may go to an undefined state and the USB link may be stuck
2000 * upon the next resume.
2001 *
2002 * Workaround:
2003 * Don't use smart standby; use only force standby,
2004 * hence HWMOD_SWSUP_MSTANDBY
2005 */
2006
2007 /*
2008 * During system boot; If the hwmod framework resets the module
2009 * the module will have smart idle settings; which can lead to deadlock
2010 * (above Errata Id:i660); so, dont reset the module during boot;
2011 * Use HWMOD_INIT_NO_RESET.
2012 */
2013
2014 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
2015 HWMOD_INIT_NO_RESET,
2016 };
2017
2018 /*
2019 * 'usb_tll_hs' class
2020 * usb_tll_hs module is the adapter on the usb_host_hs ports
2021 */
2022 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
2023 .rev_offs = 0x0000,
2024 .sysc_offs = 0x0010,
2025 .syss_offs = 0x0014,
2026 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2027 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2028 SYSC_HAS_AUTOIDLE),
2029 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2030 .sysc_fields = &omap_hwmod_sysc_type1,
2031 };
2032
2033 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
2034 .name = "usb_tll_hs",
2035 .sysc = &omap3xxx_usb_tll_hs_sysc,
2036 };
2037
2038 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
2039 { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, },
2040 { .irq = -1 },
2041 };
2042
2043 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
2044 .name = "usb_tll_hs",
2045 .class = &omap3xxx_usb_tll_hs_hwmod_class,
2046 .clkdm_name = "l3_init_clkdm",
2047 .mpu_irqs = omap3xxx_usb_tll_hs_irqs,
2048 .main_clk = "usbtll_fck",
2049 .prcm = {
2050 .omap2 = {
2051 .module_offs = CORE_MOD,
2052 .prcm_reg_id = 3,
2053 .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
2054 .idlest_reg_id = 3,
2055 .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
2056 },
2057 },
2058 };
2059
2060 static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
2061 .name = "hdq1w",
2062 .mpu_irqs = omap2_hdq1w_mpu_irqs,
2063 .main_clk = "hdq_fck",
2064 .prcm = {
2065 .omap2 = {
2066 .module_offs = CORE_MOD,
2067 .prcm_reg_id = 1,
2068 .module_bit = OMAP3430_EN_HDQ_SHIFT,
2069 .idlest_reg_id = 1,
2070 .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
2071 },
2072 },
2073 .class = &omap2_hdq1w_class,
2074 };
2075
2076 /* SAD2D */
2077 static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = {
2078 { .name = "rst_modem_pwron_sw", .rst_shift = 0 },
2079 { .name = "rst_modem_sw", .rst_shift = 1 },
2080 };
2081
2082 static struct omap_hwmod_class omap3xxx_sad2d_class = {
2083 .name = "sad2d",
2084 };
2085
2086 static struct omap_hwmod omap3xxx_sad2d_hwmod = {
2087 .name = "sad2d",
2088 .rst_lines = omap3xxx_sad2d_resets,
2089 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_sad2d_resets),
2090 .main_clk = "sad2d_ick",
2091 .prcm = {
2092 .omap2 = {
2093 .module_offs = CORE_MOD,
2094 .prcm_reg_id = 1,
2095 .module_bit = OMAP3430_EN_SAD2D_SHIFT,
2096 .idlest_reg_id = 1,
2097 .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT,
2098 },
2099 },
2100 .class = &omap3xxx_sad2d_class,
2101 };
2102
2103 /*
2104 * '32K sync counter' class
2105 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
2106 */
2107 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
2108 .rev_offs = 0x0000,
2109 .sysc_offs = 0x0004,
2110 .sysc_flags = SYSC_HAS_SIDLEMODE,
2111 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
2112 .sysc_fields = &omap_hwmod_sysc_type1,
2113 };
2114
2115 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
2116 .name = "counter",
2117 .sysc = &omap3xxx_counter_sysc,
2118 };
2119
2120 static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
2121 .name = "counter_32k",
2122 .class = &omap3xxx_counter_hwmod_class,
2123 .clkdm_name = "wkup_clkdm",
2124 .flags = HWMOD_SWSUP_SIDLE,
2125 .main_clk = "wkup_32k_fck",
2126 .prcm = {
2127 .omap2 = {
2128 .module_offs = WKUP_MOD,
2129 .prcm_reg_id = 1,
2130 .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
2131 .idlest_reg_id = 1,
2132 .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
2133 },
2134 },
2135 };
2136
2137 /*
2138 * 'gpmc' class
2139 * general purpose memory controller
2140 */
2141
2142 static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
2143 .rev_offs = 0x0000,
2144 .sysc_offs = 0x0010,
2145 .syss_offs = 0x0014,
2146 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2147 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2148 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2149 .sysc_fields = &omap_hwmod_sysc_type1,
2150 };
2151
2152 static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
2153 .name = "gpmc",
2154 .sysc = &omap3xxx_gpmc_sysc,
2155 };
2156
2157 static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = {
2158 { .irq = 20 },
2159 { .irq = -1 }
2160 };
2161
2162 static struct omap_hwmod omap3xxx_gpmc_hwmod = {
2163 .name = "gpmc",
2164 .class = &omap3xxx_gpmc_hwmod_class,
2165 .clkdm_name = "core_l3_clkdm",
2166 .mpu_irqs = omap3xxx_gpmc_irqs,
2167 .main_clk = "gpmc_fck",
2168 /*
2169 * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
2170 * block. It is not being added due to any known bugs with
2171 * resetting the GPMC IP block, but rather because any timings
2172 * set by the bootloader are not being correctly programmed by
2173 * the kernel from the board file or DT data.
2174 * HWMOD_INIT_NO_RESET should be removed ASAP.
2175 */
2176 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
2177 HWMOD_NO_IDLEST),
2178 };
2179
2180 /*
2181 * interfaces
2182 */
2183
2184 /* L3 -> L4_CORE interface */
2185 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
2186 .master = &omap3xxx_l3_main_hwmod,
2187 .slave = &omap3xxx_l4_core_hwmod,
2188 .user = OCP_USER_MPU | OCP_USER_SDMA,
2189 };
2190
2191 /* L3 -> L4_PER interface */
2192 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
2193 .master = &omap3xxx_l3_main_hwmod,
2194 .slave = &omap3xxx_l4_per_hwmod,
2195 .user = OCP_USER_MPU | OCP_USER_SDMA,
2196 };
2197
2198 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
2199 {
2200 .pa_start = 0x68000000,
2201 .pa_end = 0x6800ffff,
2202 .flags = ADDR_TYPE_RT,
2203 },
2204 { }
2205 };
2206
2207 /* MPU -> L3 interface */
2208 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
2209 .master = &omap3xxx_mpu_hwmod,
2210 .slave = &omap3xxx_l3_main_hwmod,
2211 .addr = omap3xxx_l3_main_addrs,
2212 .user = OCP_USER_MPU,
2213 };
2214
2215 static struct omap_hwmod_addr_space omap3xxx_l4_emu_addrs[] = {
2216 {
2217 .pa_start = 0x54000000,
2218 .pa_end = 0x547fffff,
2219 .flags = ADDR_TYPE_RT,
2220 },
2221 { }
2222 };
2223
2224 /* l3 -> debugss */
2225 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = {
2226 .master = &omap3xxx_l3_main_hwmod,
2227 .slave = &omap3xxx_debugss_hwmod,
2228 .addr = omap3xxx_l4_emu_addrs,
2229 .user = OCP_USER_MPU,
2230 };
2231
2232 /* DSS -> l3 */
2233 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
2234 .master = &omap3430es1_dss_core_hwmod,
2235 .slave = &omap3xxx_l3_main_hwmod,
2236 .user = OCP_USER_MPU | OCP_USER_SDMA,
2237 };
2238
2239 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
2240 .master = &omap3xxx_dss_core_hwmod,
2241 .slave = &omap3xxx_l3_main_hwmod,
2242 .fw = {
2243 .omap2 = {
2244 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
2245 .flags = OMAP_FIREWALL_L3,
2246 }
2247 },
2248 .user = OCP_USER_MPU | OCP_USER_SDMA,
2249 };
2250
2251 /* l3_core -> usbhsotg interface */
2252 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
2253 .master = &omap3xxx_usbhsotg_hwmod,
2254 .slave = &omap3xxx_l3_main_hwmod,
2255 .clk = "core_l3_ick",
2256 .user = OCP_USER_MPU,
2257 };
2258
2259 /* l3_core -> am35xx_usbhsotg interface */
2260 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
2261 .master = &am35xx_usbhsotg_hwmod,
2262 .slave = &omap3xxx_l3_main_hwmod,
2263 .clk = "hsotgusb_ick",
2264 .user = OCP_USER_MPU,
2265 };
2266
2267 /* l3_core -> sad2d interface */
2268 static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = {
2269 .master = &omap3xxx_sad2d_hwmod,
2270 .slave = &omap3xxx_l3_main_hwmod,
2271 .clk = "core_l3_ick",
2272 .user = OCP_USER_MPU,
2273 };
2274
2275 /* L4_CORE -> L4_WKUP interface */
2276 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
2277 .master = &omap3xxx_l4_core_hwmod,
2278 .slave = &omap3xxx_l4_wkup_hwmod,
2279 .user = OCP_USER_MPU | OCP_USER_SDMA,
2280 };
2281
2282 /* L4 CORE -> MMC1 interface */
2283 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
2284 .master = &omap3xxx_l4_core_hwmod,
2285 .slave = &omap3xxx_pre_es3_mmc1_hwmod,
2286 .clk = "mmchs1_ick",
2287 .addr = omap2430_mmc1_addr_space,
2288 .user = OCP_USER_MPU | OCP_USER_SDMA,
2289 .flags = OMAP_FIREWALL_L4
2290 };
2291
2292 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
2293 .master = &omap3xxx_l4_core_hwmod,
2294 .slave = &omap3xxx_es3plus_mmc1_hwmod,
2295 .clk = "mmchs1_ick",
2296 .addr = omap2430_mmc1_addr_space,
2297 .user = OCP_USER_MPU | OCP_USER_SDMA,
2298 .flags = OMAP_FIREWALL_L4
2299 };
2300
2301 /* L4 CORE -> MMC2 interface */
2302 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
2303 .master = &omap3xxx_l4_core_hwmod,
2304 .slave = &omap3xxx_pre_es3_mmc2_hwmod,
2305 .clk = "mmchs2_ick",
2306 .addr = omap2430_mmc2_addr_space,
2307 .user = OCP_USER_MPU | OCP_USER_SDMA,
2308 .flags = OMAP_FIREWALL_L4
2309 };
2310
2311 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2312 .master = &omap3xxx_l4_core_hwmod,
2313 .slave = &omap3xxx_es3plus_mmc2_hwmod,
2314 .clk = "mmchs2_ick",
2315 .addr = omap2430_mmc2_addr_space,
2316 .user = OCP_USER_MPU | OCP_USER_SDMA,
2317 .flags = OMAP_FIREWALL_L4
2318 };
2319
2320 /* L4 CORE -> MMC3 interface */
2321 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
2322 {
2323 .pa_start = 0x480ad000,
2324 .pa_end = 0x480ad1ff,
2325 .flags = ADDR_TYPE_RT,
2326 },
2327 { }
2328 };
2329
2330 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2331 .master = &omap3xxx_l4_core_hwmod,
2332 .slave = &omap3xxx_mmc3_hwmod,
2333 .clk = "mmchs3_ick",
2334 .addr = omap3xxx_mmc3_addr_space,
2335 .user = OCP_USER_MPU | OCP_USER_SDMA,
2336 .flags = OMAP_FIREWALL_L4
2337 };
2338
2339 /* L4 CORE -> UART1 interface */
2340 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
2341 {
2342 .pa_start = OMAP3_UART1_BASE,
2343 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
2344 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2345 },
2346 { }
2347 };
2348
2349 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2350 .master = &omap3xxx_l4_core_hwmod,
2351 .slave = &omap3xxx_uart1_hwmod,
2352 .clk = "uart1_ick",
2353 .addr = omap3xxx_uart1_addr_space,
2354 .user = OCP_USER_MPU | OCP_USER_SDMA,
2355 };
2356
2357 /* L4 CORE -> UART2 interface */
2358 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
2359 {
2360 .pa_start = OMAP3_UART2_BASE,
2361 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
2362 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2363 },
2364 { }
2365 };
2366
2367 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2368 .master = &omap3xxx_l4_core_hwmod,
2369 .slave = &omap3xxx_uart2_hwmod,
2370 .clk = "uart2_ick",
2371 .addr = omap3xxx_uart2_addr_space,
2372 .user = OCP_USER_MPU | OCP_USER_SDMA,
2373 };
2374
2375 /* L4 PER -> UART3 interface */
2376 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
2377 {
2378 .pa_start = OMAP3_UART3_BASE,
2379 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
2380 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2381 },
2382 { }
2383 };
2384
2385 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2386 .master = &omap3xxx_l4_per_hwmod,
2387 .slave = &omap3xxx_uart3_hwmod,
2388 .clk = "uart3_ick",
2389 .addr = omap3xxx_uart3_addr_space,
2390 .user = OCP_USER_MPU | OCP_USER_SDMA,
2391 };
2392
2393 /* L4 PER -> UART4 interface */
2394 static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
2395 {
2396 .pa_start = OMAP3_UART4_BASE,
2397 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
2398 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2399 },
2400 { }
2401 };
2402
2403 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2404 .master = &omap3xxx_l4_per_hwmod,
2405 .slave = &omap36xx_uart4_hwmod,
2406 .clk = "uart4_ick",
2407 .addr = omap36xx_uart4_addr_space,
2408 .user = OCP_USER_MPU | OCP_USER_SDMA,
2409 };
2410
2411 /* AM35xx: L4 CORE -> UART4 interface */
2412 static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
2413 {
2414 .pa_start = OMAP3_UART4_AM35XX_BASE,
2415 .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
2416 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2417 },
2418 { }
2419 };
2420
2421 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2422 .master = &omap3xxx_l4_core_hwmod,
2423 .slave = &am35xx_uart4_hwmod,
2424 .clk = "uart4_ick",
2425 .addr = am35xx_uart4_addr_space,
2426 .user = OCP_USER_MPU | OCP_USER_SDMA,
2427 };
2428
2429 /* L4 CORE -> I2C1 interface */
2430 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2431 .master = &omap3xxx_l4_core_hwmod,
2432 .slave = &omap3xxx_i2c1_hwmod,
2433 .clk = "i2c1_ick",
2434 .addr = omap2_i2c1_addr_space,
2435 .fw = {
2436 .omap2 = {
2437 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
2438 .l4_prot_group = 7,
2439 .flags = OMAP_FIREWALL_L4,
2440 }
2441 },
2442 .user = OCP_USER_MPU | OCP_USER_SDMA,
2443 };
2444
2445 /* L4 CORE -> I2C2 interface */
2446 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2447 .master = &omap3xxx_l4_core_hwmod,
2448 .slave = &omap3xxx_i2c2_hwmod,
2449 .clk = "i2c2_ick",
2450 .addr = omap2_i2c2_addr_space,
2451 .fw = {
2452 .omap2 = {
2453 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
2454 .l4_prot_group = 7,
2455 .flags = OMAP_FIREWALL_L4,
2456 }
2457 },
2458 .user = OCP_USER_MPU | OCP_USER_SDMA,
2459 };
2460
2461 /* L4 CORE -> I2C3 interface */
2462 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
2463 {
2464 .pa_start = 0x48060000,
2465 .pa_end = 0x48060000 + SZ_128 - 1,
2466 .flags = ADDR_TYPE_RT,
2467 },
2468 { }
2469 };
2470
2471 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2472 .master = &omap3xxx_l4_core_hwmod,
2473 .slave = &omap3xxx_i2c3_hwmod,
2474 .clk = "i2c3_ick",
2475 .addr = omap3xxx_i2c3_addr_space,
2476 .fw = {
2477 .omap2 = {
2478 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
2479 .l4_prot_group = 7,
2480 .flags = OMAP_FIREWALL_L4,
2481 }
2482 },
2483 .user = OCP_USER_MPU | OCP_USER_SDMA,
2484 };
2485
2486 /* L4 CORE -> SR1 interface */
2487 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
2488 {
2489 .pa_start = OMAP34XX_SR1_BASE,
2490 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
2491 .flags = ADDR_TYPE_RT,
2492 },
2493 { }
2494 };
2495
2496 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2497 .master = &omap3xxx_l4_core_hwmod,
2498 .slave = &omap34xx_sr1_hwmod,
2499 .clk = "sr_l4_ick",
2500 .addr = omap3_sr1_addr_space,
2501 .user = OCP_USER_MPU,
2502 };
2503
2504 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2505 .master = &omap3xxx_l4_core_hwmod,
2506 .slave = &omap36xx_sr1_hwmod,
2507 .clk = "sr_l4_ick",
2508 .addr = omap3_sr1_addr_space,
2509 .user = OCP_USER_MPU,
2510 };
2511
2512 /* L4 CORE -> SR1 interface */
2513 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
2514 {
2515 .pa_start = OMAP34XX_SR2_BASE,
2516 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
2517 .flags = ADDR_TYPE_RT,
2518 },
2519 { }
2520 };
2521
2522 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2523 .master = &omap3xxx_l4_core_hwmod,
2524 .slave = &omap34xx_sr2_hwmod,
2525 .clk = "sr_l4_ick",
2526 .addr = omap3_sr2_addr_space,
2527 .user = OCP_USER_MPU,
2528 };
2529
2530 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2531 .master = &omap3xxx_l4_core_hwmod,
2532 .slave = &omap36xx_sr2_hwmod,
2533 .clk = "sr_l4_ick",
2534 .addr = omap3_sr2_addr_space,
2535 .user = OCP_USER_MPU,
2536 };
2537
2538 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
2539 {
2540 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
2541 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
2542 .flags = ADDR_TYPE_RT
2543 },
2544 { }
2545 };
2546
2547 /* l4_core -> usbhsotg */
2548 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2549 .master = &omap3xxx_l4_core_hwmod,
2550 .slave = &omap3xxx_usbhsotg_hwmod,
2551 .clk = "l4_ick",
2552 .addr = omap3xxx_usbhsotg_addrs,
2553 .user = OCP_USER_MPU,
2554 };
2555
2556 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
2557 {
2558 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
2559 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
2560 .flags = ADDR_TYPE_RT
2561 },
2562 { }
2563 };
2564
2565 /* l4_core -> usbhsotg */
2566 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2567 .master = &omap3xxx_l4_core_hwmod,
2568 .slave = &am35xx_usbhsotg_hwmod,
2569 .clk = "hsotgusb_ick",
2570 .addr = am35xx_usbhsotg_addrs,
2571 .user = OCP_USER_MPU,
2572 };
2573
2574 /* L4_WKUP -> L4_SEC interface */
2575 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2576 .master = &omap3xxx_l4_wkup_hwmod,
2577 .slave = &omap3xxx_l4_sec_hwmod,
2578 .user = OCP_USER_MPU | OCP_USER_SDMA,
2579 };
2580
2581 /* IVA2 <- L3 interface */
2582 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2583 .master = &omap3xxx_l3_main_hwmod,
2584 .slave = &omap3xxx_iva_hwmod,
2585 .clk = "core_l3_ick",
2586 .user = OCP_USER_MPU | OCP_USER_SDMA,
2587 };
2588
2589 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
2590 {
2591 .pa_start = 0x48318000,
2592 .pa_end = 0x48318000 + SZ_1K - 1,
2593 .flags = ADDR_TYPE_RT
2594 },
2595 { }
2596 };
2597
2598 /* l4_wkup -> timer1 */
2599 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2600 .master = &omap3xxx_l4_wkup_hwmod,
2601 .slave = &omap3xxx_timer1_hwmod,
2602 .clk = "gpt1_ick",
2603 .addr = omap3xxx_timer1_addrs,
2604 .user = OCP_USER_MPU | OCP_USER_SDMA,
2605 };
2606
2607 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
2608 {
2609 .pa_start = 0x49032000,
2610 .pa_end = 0x49032000 + SZ_1K - 1,
2611 .flags = ADDR_TYPE_RT
2612 },
2613 { }
2614 };
2615
2616 /* l4_per -> timer2 */
2617 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2618 .master = &omap3xxx_l4_per_hwmod,
2619 .slave = &omap3xxx_timer2_hwmod,
2620 .clk = "gpt2_ick",
2621 .addr = omap3xxx_timer2_addrs,
2622 .user = OCP_USER_MPU | OCP_USER_SDMA,
2623 };
2624
2625 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
2626 {
2627 .pa_start = 0x49034000,
2628 .pa_end = 0x49034000 + SZ_1K - 1,
2629 .flags = ADDR_TYPE_RT
2630 },
2631 { }
2632 };
2633
2634 /* l4_per -> timer3 */
2635 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2636 .master = &omap3xxx_l4_per_hwmod,
2637 .slave = &omap3xxx_timer3_hwmod,
2638 .clk = "gpt3_ick",
2639 .addr = omap3xxx_timer3_addrs,
2640 .user = OCP_USER_MPU | OCP_USER_SDMA,
2641 };
2642
2643 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
2644 {
2645 .pa_start = 0x49036000,
2646 .pa_end = 0x49036000 + SZ_1K - 1,
2647 .flags = ADDR_TYPE_RT
2648 },
2649 { }
2650 };
2651
2652 /* l4_per -> timer4 */
2653 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2654 .master = &omap3xxx_l4_per_hwmod,
2655 .slave = &omap3xxx_timer4_hwmod,
2656 .clk = "gpt4_ick",
2657 .addr = omap3xxx_timer4_addrs,
2658 .user = OCP_USER_MPU | OCP_USER_SDMA,
2659 };
2660
2661 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
2662 {
2663 .pa_start = 0x49038000,
2664 .pa_end = 0x49038000 + SZ_1K - 1,
2665 .flags = ADDR_TYPE_RT
2666 },
2667 { }
2668 };
2669
2670 /* l4_per -> timer5 */
2671 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2672 .master = &omap3xxx_l4_per_hwmod,
2673 .slave = &omap3xxx_timer5_hwmod,
2674 .clk = "gpt5_ick",
2675 .addr = omap3xxx_timer5_addrs,
2676 .user = OCP_USER_MPU | OCP_USER_SDMA,
2677 };
2678
2679 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
2680 {
2681 .pa_start = 0x4903A000,
2682 .pa_end = 0x4903A000 + SZ_1K - 1,
2683 .flags = ADDR_TYPE_RT
2684 },
2685 { }
2686 };
2687
2688 /* l4_per -> timer6 */
2689 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2690 .master = &omap3xxx_l4_per_hwmod,
2691 .slave = &omap3xxx_timer6_hwmod,
2692 .clk = "gpt6_ick",
2693 .addr = omap3xxx_timer6_addrs,
2694 .user = OCP_USER_MPU | OCP_USER_SDMA,
2695 };
2696
2697 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
2698 {
2699 .pa_start = 0x4903C000,
2700 .pa_end = 0x4903C000 + SZ_1K - 1,
2701 .flags = ADDR_TYPE_RT
2702 },
2703 { }
2704 };
2705
2706 /* l4_per -> timer7 */
2707 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2708 .master = &omap3xxx_l4_per_hwmod,
2709 .slave = &omap3xxx_timer7_hwmod,
2710 .clk = "gpt7_ick",
2711 .addr = omap3xxx_timer7_addrs,
2712 .user = OCP_USER_MPU | OCP_USER_SDMA,
2713 };
2714
2715 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
2716 {
2717 .pa_start = 0x4903E000,
2718 .pa_end = 0x4903E000 + SZ_1K - 1,
2719 .flags = ADDR_TYPE_RT
2720 },
2721 { }
2722 };
2723
2724 /* l4_per -> timer8 */
2725 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2726 .master = &omap3xxx_l4_per_hwmod,
2727 .slave = &omap3xxx_timer8_hwmod,
2728 .clk = "gpt8_ick",
2729 .addr = omap3xxx_timer8_addrs,
2730 .user = OCP_USER_MPU | OCP_USER_SDMA,
2731 };
2732
2733 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
2734 {
2735 .pa_start = 0x49040000,
2736 .pa_end = 0x49040000 + SZ_1K - 1,
2737 .flags = ADDR_TYPE_RT
2738 },
2739 { }
2740 };
2741
2742 /* l4_per -> timer9 */
2743 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2744 .master = &omap3xxx_l4_per_hwmod,
2745 .slave = &omap3xxx_timer9_hwmod,
2746 .clk = "gpt9_ick",
2747 .addr = omap3xxx_timer9_addrs,
2748 .user = OCP_USER_MPU | OCP_USER_SDMA,
2749 };
2750
2751 /* l4_core -> timer10 */
2752 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2753 .master = &omap3xxx_l4_core_hwmod,
2754 .slave = &omap3xxx_timer10_hwmod,
2755 .clk = "gpt10_ick",
2756 .addr = omap2_timer10_addrs,
2757 .user = OCP_USER_MPU | OCP_USER_SDMA,
2758 };
2759
2760 /* l4_core -> timer11 */
2761 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2762 .master = &omap3xxx_l4_core_hwmod,
2763 .slave = &omap3xxx_timer11_hwmod,
2764 .clk = "gpt11_ick",
2765 .addr = omap2_timer11_addrs,
2766 .user = OCP_USER_MPU | OCP_USER_SDMA,
2767 };
2768
2769 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
2770 {
2771 .pa_start = 0x48304000,
2772 .pa_end = 0x48304000 + SZ_1K - 1,
2773 .flags = ADDR_TYPE_RT
2774 },
2775 { }
2776 };
2777
2778 /* l4_core -> timer12 */
2779 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2780 .master = &omap3xxx_l4_sec_hwmod,
2781 .slave = &omap3xxx_timer12_hwmod,
2782 .clk = "gpt12_ick",
2783 .addr = omap3xxx_timer12_addrs,
2784 .user = OCP_USER_MPU | OCP_USER_SDMA,
2785 };
2786
2787 /* l4_wkup -> wd_timer2 */
2788 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
2789 {
2790 .pa_start = 0x48314000,
2791 .pa_end = 0x4831407f,
2792 .flags = ADDR_TYPE_RT
2793 },
2794 { }
2795 };
2796
2797 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2798 .master = &omap3xxx_l4_wkup_hwmod,
2799 .slave = &omap3xxx_wd_timer2_hwmod,
2800 .clk = "wdt2_ick",
2801 .addr = omap3xxx_wd_timer2_addrs,
2802 .user = OCP_USER_MPU | OCP_USER_SDMA,
2803 };
2804
2805 /* l4_core -> dss */
2806 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2807 .master = &omap3xxx_l4_core_hwmod,
2808 .slave = &omap3430es1_dss_core_hwmod,
2809 .clk = "dss_ick",
2810 .addr = omap2_dss_addrs,
2811 .fw = {
2812 .omap2 = {
2813 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2814 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2815 .flags = OMAP_FIREWALL_L4,
2816 }
2817 },
2818 .user = OCP_USER_MPU | OCP_USER_SDMA,
2819 };
2820
2821 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2822 .master = &omap3xxx_l4_core_hwmod,
2823 .slave = &omap3xxx_dss_core_hwmod,
2824 .clk = "dss_ick",
2825 .addr = omap2_dss_addrs,
2826 .fw = {
2827 .omap2 = {
2828 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2829 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2830 .flags = OMAP_FIREWALL_L4,
2831 }
2832 },
2833 .user = OCP_USER_MPU | OCP_USER_SDMA,
2834 };
2835
2836 /* l4_core -> dss_dispc */
2837 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2838 .master = &omap3xxx_l4_core_hwmod,
2839 .slave = &omap3xxx_dss_dispc_hwmod,
2840 .clk = "dss_ick",
2841 .addr = omap2_dss_dispc_addrs,
2842 .fw = {
2843 .omap2 = {
2844 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2845 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2846 .flags = OMAP_FIREWALL_L4,
2847 }
2848 },
2849 .user = OCP_USER_MPU | OCP_USER_SDMA,
2850 };
2851
2852 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
2853 {
2854 .pa_start = 0x4804FC00,
2855 .pa_end = 0x4804FFFF,
2856 .flags = ADDR_TYPE_RT
2857 },
2858 { }
2859 };
2860
2861 /* l4_core -> dss_dsi1 */
2862 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2863 .master = &omap3xxx_l4_core_hwmod,
2864 .slave = &omap3xxx_dss_dsi1_hwmod,
2865 .clk = "dss_ick",
2866 .addr = omap3xxx_dss_dsi1_addrs,
2867 .fw = {
2868 .omap2 = {
2869 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2870 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2871 .flags = OMAP_FIREWALL_L4,
2872 }
2873 },
2874 .user = OCP_USER_MPU | OCP_USER_SDMA,
2875 };
2876
2877 /* l4_core -> dss_rfbi */
2878 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2879 .master = &omap3xxx_l4_core_hwmod,
2880 .slave = &omap3xxx_dss_rfbi_hwmod,
2881 .clk = "dss_ick",
2882 .addr = omap2_dss_rfbi_addrs,
2883 .fw = {
2884 .omap2 = {
2885 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2886 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2887 .flags = OMAP_FIREWALL_L4,
2888 }
2889 },
2890 .user = OCP_USER_MPU | OCP_USER_SDMA,
2891 };
2892
2893 /* l4_core -> dss_venc */
2894 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2895 .master = &omap3xxx_l4_core_hwmod,
2896 .slave = &omap3xxx_dss_venc_hwmod,
2897 .clk = "dss_ick",
2898 .addr = omap2_dss_venc_addrs,
2899 .fw = {
2900 .omap2 = {
2901 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2902 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2903 .flags = OMAP_FIREWALL_L4,
2904 }
2905 },
2906 .flags = OCPIF_SWSUP_IDLE,
2907 .user = OCP_USER_MPU | OCP_USER_SDMA,
2908 };
2909
2910 /* l4_wkup -> gpio1 */
2911 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2912 {
2913 .pa_start = 0x48310000,
2914 .pa_end = 0x483101ff,
2915 .flags = ADDR_TYPE_RT
2916 },
2917 { }
2918 };
2919
2920 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2921 .master = &omap3xxx_l4_wkup_hwmod,
2922 .slave = &omap3xxx_gpio1_hwmod,
2923 .addr = omap3xxx_gpio1_addrs,
2924 .user = OCP_USER_MPU | OCP_USER_SDMA,
2925 };
2926
2927 /* l4_per -> gpio2 */
2928 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2929 {
2930 .pa_start = 0x49050000,
2931 .pa_end = 0x490501ff,
2932 .flags = ADDR_TYPE_RT
2933 },
2934 { }
2935 };
2936
2937 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2938 .master = &omap3xxx_l4_per_hwmod,
2939 .slave = &omap3xxx_gpio2_hwmod,
2940 .addr = omap3xxx_gpio2_addrs,
2941 .user = OCP_USER_MPU | OCP_USER_SDMA,
2942 };
2943
2944 /* l4_per -> gpio3 */
2945 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2946 {
2947 .pa_start = 0x49052000,
2948 .pa_end = 0x490521ff,
2949 .flags = ADDR_TYPE_RT
2950 },
2951 { }
2952 };
2953
2954 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2955 .master = &omap3xxx_l4_per_hwmod,
2956 .slave = &omap3xxx_gpio3_hwmod,
2957 .addr = omap3xxx_gpio3_addrs,
2958 .user = OCP_USER_MPU | OCP_USER_SDMA,
2959 };
2960
2961 /*
2962 * 'mmu' class
2963 * The memory management unit performs virtual to physical address translation
2964 * for its requestors.
2965 */
2966
2967 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2968 .rev_offs = 0x000,
2969 .sysc_offs = 0x010,
2970 .syss_offs = 0x014,
2971 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2972 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2973 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2974 .sysc_fields = &omap_hwmod_sysc_type1,
2975 };
2976
2977 static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = {
2978 .name = "mmu",
2979 .sysc = &mmu_sysc,
2980 };
2981
2982 /* mmu isp */
2983
2984 static struct omap_mmu_dev_attr mmu_isp_dev_attr = {
2985 .da_start = 0x0,
2986 .da_end = 0xfffff000,
2987 .nr_tlb_entries = 8,
2988 };
2989
2990 static struct omap_hwmod omap3xxx_mmu_isp_hwmod;
2991 static struct omap_hwmod_irq_info omap3xxx_mmu_isp_irqs[] = {
2992 { .irq = 24 },
2993 { .irq = -1 }
2994 };
2995
2996 static struct omap_hwmod_addr_space omap3xxx_mmu_isp_addrs[] = {
2997 {
2998 .pa_start = 0x480bd400,
2999 .pa_end = 0x480bd47f,
3000 .flags = ADDR_TYPE_RT,
3001 },
3002 { }
3003 };
3004
3005 /* l4_core -> mmu isp */
3006 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = {
3007 .master = &omap3xxx_l4_core_hwmod,
3008 .slave = &omap3xxx_mmu_isp_hwmod,
3009 .addr = omap3xxx_mmu_isp_addrs,
3010 .user = OCP_USER_MPU | OCP_USER_SDMA,
3011 };
3012
3013 static struct omap_hwmod omap3xxx_mmu_isp_hwmod = {
3014 .name = "mmu_isp",
3015 .class = &omap3xxx_mmu_hwmod_class,
3016 .mpu_irqs = omap3xxx_mmu_isp_irqs,
3017 .main_clk = "cam_ick",
3018 .dev_attr = &mmu_isp_dev_attr,
3019 .flags = HWMOD_NO_IDLEST,
3020 };
3021
3022 #ifdef CONFIG_OMAP_IOMMU_IVA2
3023
3024 /* mmu iva */
3025
3026 static struct omap_mmu_dev_attr mmu_iva_dev_attr = {
3027 .da_start = 0x11000000,
3028 .da_end = 0xfffff000,
3029 .nr_tlb_entries = 32,
3030 };
3031
3032 static struct omap_hwmod omap3xxx_mmu_iva_hwmod;
3033 static struct omap_hwmod_irq_info omap3xxx_mmu_iva_irqs[] = {
3034 { .irq = 28 },
3035 { .irq = -1 }
3036 };
3037
3038 static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = {
3039 { .name = "mmu", .rst_shift = 1, .st_shift = 9 },
3040 };
3041
3042 static struct omap_hwmod_addr_space omap3xxx_mmu_iva_addrs[] = {
3043 {
3044 .pa_start = 0x5d000000,
3045 .pa_end = 0x5d00007f,
3046 .flags = ADDR_TYPE_RT,
3047 },
3048 { }
3049 };
3050
3051 /* l3_main -> iva mmu */
3052 static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = {
3053 .master = &omap3xxx_l3_main_hwmod,
3054 .slave = &omap3xxx_mmu_iva_hwmod,
3055 .addr = omap3xxx_mmu_iva_addrs,
3056 .user = OCP_USER_MPU | OCP_USER_SDMA,
3057 };
3058
3059 static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
3060 .name = "mmu_iva",
3061 .class = &omap3xxx_mmu_hwmod_class,
3062 .mpu_irqs = omap3xxx_mmu_iva_irqs,
3063 .rst_lines = omap3xxx_mmu_iva_resets,
3064 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_mmu_iva_resets),
3065 .main_clk = "iva2_ck",
3066 .prcm = {
3067 .omap2 = {
3068 .module_offs = OMAP3430_IVA2_MOD,
3069 },
3070 },
3071 .dev_attr = &mmu_iva_dev_attr,
3072 .flags = HWMOD_NO_IDLEST,
3073 };
3074
3075 #endif
3076
3077 /* l4_per -> gpio4 */
3078 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
3079 {
3080 .pa_start = 0x49054000,
3081 .pa_end = 0x490541ff,
3082 .flags = ADDR_TYPE_RT
3083 },
3084 { }
3085 };
3086
3087 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
3088 .master = &omap3xxx_l4_per_hwmod,
3089 .slave = &omap3xxx_gpio4_hwmod,
3090 .addr = omap3xxx_gpio4_addrs,
3091 .user = OCP_USER_MPU | OCP_USER_SDMA,
3092 };
3093
3094 /* l4_per -> gpio5 */
3095 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
3096 {
3097 .pa_start = 0x49056000,
3098 .pa_end = 0x490561ff,
3099 .flags = ADDR_TYPE_RT
3100 },
3101 { }
3102 };
3103
3104 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
3105 .master = &omap3xxx_l4_per_hwmod,
3106 .slave = &omap3xxx_gpio5_hwmod,
3107 .addr = omap3xxx_gpio5_addrs,
3108 .user = OCP_USER_MPU | OCP_USER_SDMA,
3109 };
3110
3111 /* l4_per -> gpio6 */
3112 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
3113 {
3114 .pa_start = 0x49058000,
3115 .pa_end = 0x490581ff,
3116 .flags = ADDR_TYPE_RT
3117 },
3118 { }
3119 };
3120
3121 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
3122 .master = &omap3xxx_l4_per_hwmod,
3123 .slave = &omap3xxx_gpio6_hwmod,
3124 .addr = omap3xxx_gpio6_addrs,
3125 .user = OCP_USER_MPU | OCP_USER_SDMA,
3126 };
3127
3128 /* dma_system -> L3 */
3129 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
3130 .master = &omap3xxx_dma_system_hwmod,
3131 .slave = &omap3xxx_l3_main_hwmod,
3132 .clk = "core_l3_ick",
3133 .user = OCP_USER_MPU | OCP_USER_SDMA,
3134 };
3135
3136 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
3137 {
3138 .pa_start = 0x48056000,
3139 .pa_end = 0x48056fff,
3140 .flags = ADDR_TYPE_RT
3141 },
3142 { }
3143 };
3144
3145 /* l4_cfg -> dma_system */
3146 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
3147 .master = &omap3xxx_l4_core_hwmod,
3148 .slave = &omap3xxx_dma_system_hwmod,
3149 .clk = "core_l4_ick",
3150 .addr = omap3xxx_dma_system_addrs,
3151 .user = OCP_USER_MPU | OCP_USER_SDMA,
3152 };
3153
3154 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
3155 {
3156 .name = "mpu",
3157 .pa_start = 0x48074000,
3158 .pa_end = 0x480740ff,
3159 .flags = ADDR_TYPE_RT
3160 },
3161 { }
3162 };
3163
3164 /* l4_core -> mcbsp1 */
3165 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
3166 .master = &omap3xxx_l4_core_hwmod,
3167 .slave = &omap3xxx_mcbsp1_hwmod,
3168 .clk = "mcbsp1_ick",
3169 .addr = omap3xxx_mcbsp1_addrs,
3170 .user = OCP_USER_MPU | OCP_USER_SDMA,
3171 };
3172
3173 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
3174 {
3175 .name = "mpu",
3176 .pa_start = 0x49022000,
3177 .pa_end = 0x490220ff,
3178 .flags = ADDR_TYPE_RT
3179 },
3180 { }
3181 };
3182
3183 /* l4_per -> mcbsp2 */
3184 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
3185 .master = &omap3xxx_l4_per_hwmod,
3186 .slave = &omap3xxx_mcbsp2_hwmod,
3187 .clk = "mcbsp2_ick",
3188 .addr = omap3xxx_mcbsp2_addrs,
3189 .user = OCP_USER_MPU | OCP_USER_SDMA,
3190 };
3191
3192 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
3193 {
3194 .name = "mpu",
3195 .pa_start = 0x49024000,
3196 .pa_end = 0x490240ff,
3197 .flags = ADDR_TYPE_RT
3198 },
3199 { }
3200 };
3201
3202 /* l4_per -> mcbsp3 */
3203 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
3204 .master = &omap3xxx_l4_per_hwmod,
3205 .slave = &omap3xxx_mcbsp3_hwmod,
3206 .clk = "mcbsp3_ick",
3207 .addr = omap3xxx_mcbsp3_addrs,
3208 .user = OCP_USER_MPU | OCP_USER_SDMA,
3209 };
3210
3211 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
3212 {
3213 .name = "mpu",
3214 .pa_start = 0x49026000,
3215 .pa_end = 0x490260ff,
3216 .flags = ADDR_TYPE_RT
3217 },
3218 { }
3219 };
3220
3221 /* l4_per -> mcbsp4 */
3222 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
3223 .master = &omap3xxx_l4_per_hwmod,
3224 .slave = &omap3xxx_mcbsp4_hwmod,
3225 .clk = "mcbsp4_ick",
3226 .addr = omap3xxx_mcbsp4_addrs,
3227 .user = OCP_USER_MPU | OCP_USER_SDMA,
3228 };
3229
3230 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
3231 {
3232 .name = "mpu",
3233 .pa_start = 0x48096000,
3234 .pa_end = 0x480960ff,
3235 .flags = ADDR_TYPE_RT
3236 },
3237 { }
3238 };
3239
3240 /* l4_core -> mcbsp5 */
3241 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
3242 .master = &omap3xxx_l4_core_hwmod,
3243 .slave = &omap3xxx_mcbsp5_hwmod,
3244 .clk = "mcbsp5_ick",
3245 .addr = omap3xxx_mcbsp5_addrs,
3246 .user = OCP_USER_MPU | OCP_USER_SDMA,
3247 };
3248
3249 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
3250 {
3251 .name = "sidetone",
3252 .pa_start = 0x49028000,
3253 .pa_end = 0x490280ff,
3254 .flags = ADDR_TYPE_RT
3255 },
3256 { }
3257 };
3258
3259 /* l4_per -> mcbsp2_sidetone */
3260 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
3261 .master = &omap3xxx_l4_per_hwmod,
3262 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
3263 .clk = "mcbsp2_ick",
3264 .addr = omap3xxx_mcbsp2_sidetone_addrs,
3265 .user = OCP_USER_MPU,
3266 };
3267
3268 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
3269 {
3270 .name = "sidetone",
3271 .pa_start = 0x4902A000,
3272 .pa_end = 0x4902A0ff,
3273 .flags = ADDR_TYPE_RT
3274 },
3275 { }
3276 };
3277
3278 /* l4_per -> mcbsp3_sidetone */
3279 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
3280 .master = &omap3xxx_l4_per_hwmod,
3281 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
3282 .clk = "mcbsp3_ick",
3283 .addr = omap3xxx_mcbsp3_sidetone_addrs,
3284 .user = OCP_USER_MPU,
3285 };
3286
3287 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
3288 {
3289 .pa_start = 0x48094000,
3290 .pa_end = 0x480941ff,
3291 .flags = ADDR_TYPE_RT,
3292 },
3293 { }
3294 };
3295
3296 /* l4_core -> mailbox */
3297 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3298 .master = &omap3xxx_l4_core_hwmod,
3299 .slave = &omap3xxx_mailbox_hwmod,
3300 .addr = omap3xxx_mailbox_addrs,
3301 .user = OCP_USER_MPU | OCP_USER_SDMA,
3302 };
3303
3304 /* l4 core -> mcspi1 interface */
3305 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3306 .master = &omap3xxx_l4_core_hwmod,
3307 .slave = &omap34xx_mcspi1,
3308 .clk = "mcspi1_ick",
3309 .addr = omap2_mcspi1_addr_space,
3310 .user = OCP_USER_MPU | OCP_USER_SDMA,
3311 };
3312
3313 /* l4 core -> mcspi2 interface */
3314 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3315 .master = &omap3xxx_l4_core_hwmod,
3316 .slave = &omap34xx_mcspi2,
3317 .clk = "mcspi2_ick",
3318 .addr = omap2_mcspi2_addr_space,
3319 .user = OCP_USER_MPU | OCP_USER_SDMA,
3320 };
3321
3322 /* l4 core -> mcspi3 interface */
3323 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3324 .master = &omap3xxx_l4_core_hwmod,
3325 .slave = &omap34xx_mcspi3,
3326 .clk = "mcspi3_ick",
3327 .addr = omap2430_mcspi3_addr_space,
3328 .user = OCP_USER_MPU | OCP_USER_SDMA,
3329 };
3330
3331 /* l4 core -> mcspi4 interface */
3332 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3333 {
3334 .pa_start = 0x480ba000,
3335 .pa_end = 0x480ba0ff,
3336 .flags = ADDR_TYPE_RT,
3337 },
3338 { }
3339 };
3340
3341 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3342 .master = &omap3xxx_l4_core_hwmod,
3343 .slave = &omap34xx_mcspi4,
3344 .clk = "mcspi4_ick",
3345 .addr = omap34xx_mcspi4_addr_space,
3346 .user = OCP_USER_MPU | OCP_USER_SDMA,
3347 };
3348
3349 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3350 .master = &omap3xxx_usb_host_hs_hwmod,
3351 .slave = &omap3xxx_l3_main_hwmod,
3352 .clk = "core_l3_ick",
3353 .user = OCP_USER_MPU,
3354 };
3355
3356 static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3357 {
3358 .name = "uhh",
3359 .pa_start = 0x48064000,
3360 .pa_end = 0x480643ff,
3361 .flags = ADDR_TYPE_RT
3362 },
3363 {
3364 .name = "ohci",
3365 .pa_start = 0x48064400,
3366 .pa_end = 0x480647ff,
3367 },
3368 {
3369 .name = "ehci",
3370 .pa_start = 0x48064800,
3371 .pa_end = 0x48064cff,
3372 },
3373 {}
3374 };
3375
3376 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3377 .master = &omap3xxx_l4_core_hwmod,
3378 .slave = &omap3xxx_usb_host_hs_hwmod,
3379 .clk = "usbhost_ick",
3380 .addr = omap3xxx_usb_host_hs_addrs,
3381 .user = OCP_USER_MPU | OCP_USER_SDMA,
3382 };
3383
3384 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3385 {
3386 .name = "tll",
3387 .pa_start = 0x48062000,
3388 .pa_end = 0x48062fff,
3389 .flags = ADDR_TYPE_RT
3390 },
3391 {}
3392 };
3393
3394 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3395 .master = &omap3xxx_l4_core_hwmod,
3396 .slave = &omap3xxx_usb_tll_hs_hwmod,
3397 .clk = "usbtll_ick",
3398 .addr = omap3xxx_usb_tll_hs_addrs,
3399 .user = OCP_USER_MPU | OCP_USER_SDMA,
3400 };
3401
3402 /* l4_core -> hdq1w interface */
3403 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
3404 .master = &omap3xxx_l4_core_hwmod,
3405 .slave = &omap3xxx_hdq1w_hwmod,
3406 .clk = "hdq_ick",
3407 .addr = omap2_hdq1w_addr_space,
3408 .user = OCP_USER_MPU | OCP_USER_SDMA,
3409 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
3410 };
3411
3412 /* l4_wkup -> 32ksync_counter */
3413 static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
3414 {
3415 .pa_start = 0x48320000,
3416 .pa_end = 0x4832001f,
3417 .flags = ADDR_TYPE_RT
3418 },
3419 { }
3420 };
3421
3422 static struct omap_hwmod_addr_space omap3xxx_gpmc_addrs[] = {
3423 {
3424 .pa_start = 0x6e000000,
3425 .pa_end = 0x6e000fff,
3426 .flags = ADDR_TYPE_RT
3427 },
3428 { }
3429 };
3430
3431 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
3432 .master = &omap3xxx_l4_wkup_hwmod,
3433 .slave = &omap3xxx_counter_32k_hwmod,
3434 .clk = "omap_32ksync_ick",
3435 .addr = omap3xxx_counter_32k_addrs,
3436 .user = OCP_USER_MPU | OCP_USER_SDMA,
3437 };
3438
3439 /* am35xx has Davinci MDIO & EMAC */
3440 static struct omap_hwmod_class am35xx_mdio_class = {
3441 .name = "davinci_mdio",
3442 };
3443
3444 static struct omap_hwmod am35xx_mdio_hwmod = {
3445 .name = "davinci_mdio",
3446 .class = &am35xx_mdio_class,
3447 .flags = HWMOD_NO_IDLEST,
3448 };
3449
3450 /*
3451 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3452 * but this will probably require some additional hwmod core support,
3453 * so is left as a future to-do item.
3454 */
3455 static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
3456 .master = &am35xx_mdio_hwmod,
3457 .slave = &omap3xxx_l3_main_hwmod,
3458 .clk = "emac_fck",
3459 .user = OCP_USER_MPU,
3460 };
3461
3462 static struct omap_hwmod_addr_space am35xx_mdio_addrs[] = {
3463 {
3464 .pa_start = AM35XX_IPSS_MDIO_BASE,
3465 .pa_end = AM35XX_IPSS_MDIO_BASE + SZ_4K - 1,
3466 .flags = ADDR_TYPE_RT,
3467 },
3468 { }
3469 };
3470
3471 /* l4_core -> davinci mdio */
3472 /*
3473 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3474 * but this will probably require some additional hwmod core support,
3475 * so is left as a future to-do item.
3476 */
3477 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
3478 .master = &omap3xxx_l4_core_hwmod,
3479 .slave = &am35xx_mdio_hwmod,
3480 .clk = "emac_fck",
3481 .addr = am35xx_mdio_addrs,
3482 .user = OCP_USER_MPU,
3483 };
3484
3485 static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = {
3486 { .name = "rxthresh", .irq = 67 + OMAP_INTC_START, },
3487 { .name = "rx_pulse", .irq = 68 + OMAP_INTC_START, },
3488 { .name = "tx_pulse", .irq = 69 + OMAP_INTC_START },
3489 { .name = "misc_pulse", .irq = 70 + OMAP_INTC_START },
3490 { .irq = -1 },
3491 };
3492
3493 static struct omap_hwmod_class am35xx_emac_class = {
3494 .name = "davinci_emac",
3495 };
3496
3497 static struct omap_hwmod am35xx_emac_hwmod = {
3498 .name = "davinci_emac",
3499 .mpu_irqs = am35xx_emac_mpu_irqs,
3500 .class = &am35xx_emac_class,
3501 /*
3502 * According to Mark Greer, the MPU will not return from WFI
3503 * when the EMAC signals an interrupt.
3504 * http://www.spinics.net/lists/arm-kernel/msg174734.html
3505 */
3506 .flags = (HWMOD_NO_IDLEST | HWMOD_BLOCK_WFI),
3507 };
3508
3509 /* l3_core -> davinci emac interface */
3510 /*
3511 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3512 * but this will probably require some additional hwmod core support,
3513 * so is left as a future to-do item.
3514 */
3515 static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
3516 .master = &am35xx_emac_hwmod,
3517 .slave = &omap3xxx_l3_main_hwmod,
3518 .clk = "emac_ick",
3519 .user = OCP_USER_MPU,
3520 };
3521
3522 static struct omap_hwmod_addr_space am35xx_emac_addrs[] = {
3523 {
3524 .pa_start = AM35XX_IPSS_EMAC_BASE,
3525 .pa_end = AM35XX_IPSS_EMAC_BASE + 0x30000 - 1,
3526 .flags = ADDR_TYPE_RT,
3527 },
3528 { }
3529 };
3530
3531 /* l4_core -> davinci emac */
3532 /*
3533 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3534 * but this will probably require some additional hwmod core support,
3535 * so is left as a future to-do item.
3536 */
3537 static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
3538 .master = &omap3xxx_l4_core_hwmod,
3539 .slave = &am35xx_emac_hwmod,
3540 .clk = "emac_ick",
3541 .addr = am35xx_emac_addrs,
3542 .user = OCP_USER_MPU,
3543 };
3544
3545 static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
3546 .master = &omap3xxx_l3_main_hwmod,
3547 .slave = &omap3xxx_gpmc_hwmod,
3548 .clk = "core_l3_ick",
3549 .addr = omap3xxx_gpmc_addrs,
3550 .user = OCP_USER_MPU | OCP_USER_SDMA,
3551 };
3552
3553 /* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */
3554 static struct omap_hwmod_sysc_fields omap3_sham_sysc_fields = {
3555 .sidle_shift = 4,
3556 .srst_shift = 1,
3557 .autoidle_shift = 0,
3558 };
3559
3560 static struct omap_hwmod_class_sysconfig omap3_sham_sysc = {
3561 .rev_offs = 0x5c,
3562 .sysc_offs = 0x60,
3563 .syss_offs = 0x64,
3564 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3565 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3566 .sysc_fields = &omap3_sham_sysc_fields,
3567 };
3568
3569 static struct omap_hwmod_class omap3xxx_sham_class = {
3570 .name = "sham",
3571 .sysc = &omap3_sham_sysc,
3572 };
3573
3574 static struct omap_hwmod_irq_info omap3_sham_mpu_irqs[] = {
3575 { .irq = 49 + OMAP_INTC_START, },
3576 { .irq = -1 }
3577 };
3578
3579 static struct omap_hwmod_dma_info omap3_sham_sdma_reqs[] = {
3580 { .name = "rx", .dma_req = OMAP34XX_DMA_SHA1MD5_RX, },
3581 { .dma_req = -1 }
3582 };
3583
3584 static struct omap_hwmod omap3xxx_sham_hwmod = {
3585 .name = "sham",
3586 .mpu_irqs = omap3_sham_mpu_irqs,
3587 .sdma_reqs = omap3_sham_sdma_reqs,
3588 .main_clk = "sha12_ick",
3589 .prcm = {
3590 .omap2 = {
3591 .module_offs = CORE_MOD,
3592 .prcm_reg_id = 1,
3593 .module_bit = OMAP3430_EN_SHA12_SHIFT,
3594 .idlest_reg_id = 1,
3595 .idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT,
3596 },
3597 },
3598 .class = &omap3xxx_sham_class,
3599 };
3600
3601 static struct omap_hwmod_addr_space omap3xxx_sham_addrs[] = {
3602 {
3603 .pa_start = 0x480c3000,
3604 .pa_end = 0x480c3000 + 0x64 - 1,
3605 .flags = ADDR_TYPE_RT
3606 },
3607 { }
3608 };
3609
3610 static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
3611 .master = &omap3xxx_l4_core_hwmod,
3612 .slave = &omap3xxx_sham_hwmod,
3613 .clk = "sha12_ick",
3614 .addr = omap3xxx_sham_addrs,
3615 .user = OCP_USER_MPU | OCP_USER_SDMA,
3616 };
3617
3618 /* l4_core -> AES */
3619 static struct omap_hwmod_sysc_fields omap3xxx_aes_sysc_fields = {
3620 .sidle_shift = 6,
3621 .srst_shift = 1,
3622 .autoidle_shift = 0,
3623 };
3624
3625 static struct omap_hwmod_class_sysconfig omap3_aes_sysc = {
3626 .rev_offs = 0x44,
3627 .sysc_offs = 0x48,
3628 .syss_offs = 0x4c,
3629 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3630 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3631 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3632 .sysc_fields = &omap3xxx_aes_sysc_fields,
3633 };
3634
3635 static struct omap_hwmod_class omap3xxx_aes_class = {
3636 .name = "aes",
3637 .sysc = &omap3_aes_sysc,
3638 };
3639
3640 static struct omap_hwmod_dma_info omap3_aes_sdma_reqs[] = {
3641 { .name = "tx", .dma_req = OMAP34XX_DMA_AES2_TX, },
3642 { .name = "rx", .dma_req = OMAP34XX_DMA_AES2_RX, },
3643 { .dma_req = -1 }
3644 };
3645
3646 static struct omap_hwmod omap3xxx_aes_hwmod = {
3647 .name = "aes",
3648 .sdma_reqs = omap3_aes_sdma_reqs,
3649 .main_clk = "aes2_ick",
3650 .prcm = {
3651 .omap2 = {
3652 .module_offs = CORE_MOD,
3653 .prcm_reg_id = 1,
3654 .module_bit = OMAP3430_EN_AES2_SHIFT,
3655 .idlest_reg_id = 1,
3656 .idlest_idle_bit = OMAP3430_ST_AES2_SHIFT,
3657 },
3658 },
3659 .class = &omap3xxx_aes_class,
3660 };
3661
3662 static struct omap_hwmod_addr_space omap3xxx_aes_addrs[] = {
3663 {
3664 .pa_start = 0x480c5000,
3665 .pa_end = 0x480c5000 + 0x50 - 1,
3666 .flags = ADDR_TYPE_RT
3667 },
3668 { }
3669 };
3670
3671 static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = {
3672 .master = &omap3xxx_l4_core_hwmod,
3673 .slave = &omap3xxx_aes_hwmod,
3674 .clk = "aes2_ick",
3675 .addr = omap3xxx_aes_addrs,
3676 .user = OCP_USER_MPU | OCP_USER_SDMA,
3677 };
3678
3679 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3680 &omap3xxx_l3_main__l4_core,
3681 &omap3xxx_l3_main__l4_per,
3682 &omap3xxx_mpu__l3_main,
3683 &omap3xxx_l3_main__l4_debugss,
3684 &omap3xxx_l4_core__l4_wkup,
3685 &omap3xxx_l4_core__mmc3,
3686 &omap3_l4_core__uart1,
3687 &omap3_l4_core__uart2,
3688 &omap3_l4_per__uart3,
3689 &omap3_l4_core__i2c1,
3690 &omap3_l4_core__i2c2,
3691 &omap3_l4_core__i2c3,
3692 &omap3xxx_l4_wkup__l4_sec,
3693 &omap3xxx_l4_wkup__timer1,
3694 &omap3xxx_l4_per__timer2,
3695 &omap3xxx_l4_per__timer3,
3696 &omap3xxx_l4_per__timer4,
3697 &omap3xxx_l4_per__timer5,
3698 &omap3xxx_l4_per__timer6,
3699 &omap3xxx_l4_per__timer7,
3700 &omap3xxx_l4_per__timer8,
3701 &omap3xxx_l4_per__timer9,
3702 &omap3xxx_l4_core__timer10,
3703 &omap3xxx_l4_core__timer11,
3704 &omap3xxx_l4_wkup__wd_timer2,
3705 &omap3xxx_l4_wkup__gpio1,
3706 &omap3xxx_l4_per__gpio2,
3707 &omap3xxx_l4_per__gpio3,
3708 &omap3xxx_l4_per__gpio4,
3709 &omap3xxx_l4_per__gpio5,
3710 &omap3xxx_l4_per__gpio6,
3711 &omap3xxx_dma_system__l3,
3712 &omap3xxx_l4_core__dma_system,
3713 &omap3xxx_l4_core__mcbsp1,
3714 &omap3xxx_l4_per__mcbsp2,
3715 &omap3xxx_l4_per__mcbsp3,
3716 &omap3xxx_l4_per__mcbsp4,
3717 &omap3xxx_l4_core__mcbsp5,
3718 &omap3xxx_l4_per__mcbsp2_sidetone,
3719 &omap3xxx_l4_per__mcbsp3_sidetone,
3720 &omap34xx_l4_core__mcspi1,
3721 &omap34xx_l4_core__mcspi2,
3722 &omap34xx_l4_core__mcspi3,
3723 &omap34xx_l4_core__mcspi4,
3724 &omap3xxx_l4_wkup__counter_32k,
3725 &omap3xxx_l3_main__gpmc,
3726 NULL,
3727 };
3728
3729 /* GP-only hwmod links */
3730 static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = {
3731 &omap3xxx_l4_sec__timer12,
3732 &omap3xxx_l4_core__sham,
3733 &omap3xxx_l4_core__aes,
3734 NULL
3735 };
3736
3737 static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = {
3738 &omap3xxx_l4_sec__timer12,
3739 &omap3xxx_l4_core__sham,
3740 &omap3xxx_l4_core__aes,
3741 NULL
3742 };
3743
3744 static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = {
3745 &omap3xxx_l4_sec__timer12,
3746 /*
3747 * Apparently the SHA/MD5 and AES accelerator IP blocks are
3748 * only present on some AM35xx chips, and no one knows which
3749 * ones. See
3750 * http://www.spinics.net/lists/arm-kernel/msg215466.html So
3751 * if you need these IP blocks on an AM35xx, try uncommenting
3752 * the following lines.
3753 */
3754 /* &omap3xxx_l4_core__sham, */
3755 /* &omap3xxx_l4_core__aes, */
3756 NULL
3757 };
3758
3759 /* 3430ES1-only hwmod links */
3760 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
3761 &omap3430es1_dss__l3,
3762 &omap3430es1_l4_core__dss,
3763 NULL
3764 };
3765
3766 /* 3430ES2+-only hwmod links */
3767 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
3768 &omap3xxx_dss__l3,
3769 &omap3xxx_l4_core__dss,
3770 &omap3xxx_usbhsotg__l3,
3771 &omap3xxx_l4_core__usbhsotg,
3772 &omap3xxx_usb_host_hs__l3_main_2,
3773 &omap3xxx_l4_core__usb_host_hs,
3774 &omap3xxx_l4_core__usb_tll_hs,
3775 NULL
3776 };
3777
3778 /* <= 3430ES3-only hwmod links */
3779 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
3780 &omap3xxx_l4_core__pre_es3_mmc1,
3781 &omap3xxx_l4_core__pre_es3_mmc2,
3782 NULL
3783 };
3784
3785 /* 3430ES3+-only hwmod links */
3786 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3787 &omap3xxx_l4_core__es3plus_mmc1,
3788 &omap3xxx_l4_core__es3plus_mmc2,
3789 NULL
3790 };
3791
3792 /* 34xx-only hwmod links (all ES revisions) */
3793 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3794 &omap3xxx_l3__iva,
3795 &omap34xx_l4_core__sr1,
3796 &omap34xx_l4_core__sr2,
3797 &omap3xxx_l4_core__mailbox,
3798 &omap3xxx_l4_core__hdq1w,
3799 &omap3xxx_sad2d__l3,
3800 &omap3xxx_l4_core__mmu_isp,
3801 #ifdef CONFIG_OMAP_IOMMU_IVA2
3802 &omap3xxx_l3_main__mmu_iva,
3803 #endif
3804 NULL
3805 };
3806
3807 /* 36xx-only hwmod links (all ES revisions) */
3808 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3809 &omap3xxx_l3__iva,
3810 &omap36xx_l4_per__uart4,
3811 &omap3xxx_dss__l3,
3812 &omap3xxx_l4_core__dss,
3813 &omap36xx_l4_core__sr1,
3814 &omap36xx_l4_core__sr2,
3815 &omap3xxx_usbhsotg__l3,
3816 &omap3xxx_l4_core__usbhsotg,
3817 &omap3xxx_l4_core__mailbox,
3818 &omap3xxx_usb_host_hs__l3_main_2,
3819 &omap3xxx_l4_core__usb_host_hs,
3820 &omap3xxx_l4_core__usb_tll_hs,
3821 &omap3xxx_l4_core__es3plus_mmc1,
3822 &omap3xxx_l4_core__es3plus_mmc2,
3823 &omap3xxx_l4_core__hdq1w,
3824 &omap3xxx_sad2d__l3,
3825 &omap3xxx_l4_core__mmu_isp,
3826 #ifdef CONFIG_OMAP_IOMMU_IVA2
3827 &omap3xxx_l3_main__mmu_iva,
3828 #endif
3829 NULL
3830 };
3831
3832 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3833 &omap3xxx_dss__l3,
3834 &omap3xxx_l4_core__dss,
3835 &am35xx_usbhsotg__l3,
3836 &am35xx_l4_core__usbhsotg,
3837 &am35xx_l4_core__uart4,
3838 &omap3xxx_usb_host_hs__l3_main_2,
3839 &omap3xxx_l4_core__usb_host_hs,
3840 &omap3xxx_l4_core__usb_tll_hs,
3841 &omap3xxx_l4_core__es3plus_mmc1,
3842 &omap3xxx_l4_core__es3plus_mmc2,
3843 &omap3xxx_l4_core__hdq1w,
3844 &am35xx_mdio__l3,
3845 &am35xx_l4_core__mdio,
3846 &am35xx_emac__l3,
3847 &am35xx_l4_core__emac,
3848 NULL
3849 };
3850
3851 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3852 &omap3xxx_l4_core__dss_dispc,
3853 &omap3xxx_l4_core__dss_dsi1,
3854 &omap3xxx_l4_core__dss_rfbi,
3855 &omap3xxx_l4_core__dss_venc,
3856 NULL
3857 };
3858
3859 int __init omap3xxx_hwmod_init(void)
3860 {
3861 int r;
3862 struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL;
3863 unsigned int rev;
3864
3865 omap_hwmod_init();
3866
3867 /* Register hwmod links common to all OMAP3 */
3868 r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
3869 if (r < 0)
3870 return r;
3871
3872 rev = omap_rev();
3873
3874 /*
3875 * Register hwmod links common to individual OMAP3 families, all
3876 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3877 * All possible revisions should be included in this conditional.
3878 */
3879 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3880 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3881 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3882 h = omap34xx_hwmod_ocp_ifs;
3883 h_gp = omap34xx_gp_hwmod_ocp_ifs;
3884 } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
3885 h = am35xx_hwmod_ocp_ifs;
3886 h_gp = am35xx_gp_hwmod_ocp_ifs;
3887 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3888 rev == OMAP3630_REV_ES1_2) {
3889 h = omap36xx_hwmod_ocp_ifs;
3890 h_gp = omap36xx_gp_hwmod_ocp_ifs;
3891 } else {
3892 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3893 return -EINVAL;
3894 }
3895
3896 r = omap_hwmod_register_links(h);
3897 if (r < 0)
3898 return r;
3899
3900 /* Register GP-only hwmod links. */
3901 if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) {
3902 r = omap_hwmod_register_links(h_gp);
3903 if (r < 0)
3904 return r;
3905 }
3906
3907
3908 /*
3909 * Register hwmod links specific to certain ES levels of a
3910 * particular family of silicon (e.g., 34xx ES1.0)
3911 */
3912 h = NULL;
3913 if (rev == OMAP3430_REV_ES1_0) {
3914 h = omap3430es1_hwmod_ocp_ifs;
3915 } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3916 rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3917 rev == OMAP3430_REV_ES3_1_2) {
3918 h = omap3430es2plus_hwmod_ocp_ifs;
3919 }
3920
3921 if (h) {
3922 r = omap_hwmod_register_links(h);
3923 if (r < 0)
3924 return r;
3925 }
3926
3927 h = NULL;
3928 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3929 rev == OMAP3430_REV_ES2_1) {
3930 h = omap3430_pre_es3_hwmod_ocp_ifs;
3931 } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3932 rev == OMAP3430_REV_ES3_1_2) {
3933 h = omap3430_es3plus_hwmod_ocp_ifs;
3934 }
3935
3936 if (h)
3937 r = omap_hwmod_register_links(h);
3938 if (r < 0)
3939 return r;
3940
3941 /*
3942 * DSS code presumes that dss_core hwmod is handled first,
3943 * _before_ any other DSS related hwmods so register common
3944 * DSS hwmod links last to ensure that dss_core is already
3945 * registered. Otherwise some change things may happen, for
3946 * ex. if dispc is handled before dss_core and DSS is enabled
3947 * in bootloader DISPC will be reset with outputs enabled
3948 * which sometimes leads to unrecoverable L3 error. XXX The
3949 * long-term fix to this is to ensure hwmods are set up in
3950 * dependency order in the hwmod core code.
3951 */
3952 r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
3953
3954 return r;
3955 }
Linux kernel - Deliverables
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