projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
ARM: OMAP3+: SmartReflex: use voltage domain name in device attributes
[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_3xxx_data.c
1 /*
2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
3 *
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * The data in this file should be completely autogeneratable from
12 * the TI hardware database or other technical documentation.
13 *
14 * XXX these should be marked initdata for multi-OMAP kernels
15 */
16 #include <plat/omap_hwmod.h>
17 #include <mach/irqs.h>
18 #include <plat/cpu.h>
19 #include <plat/dma.h>
20 #include <plat/serial.h>
21 #include <plat/l3_3xxx.h>
22 #include <plat/l4_3xxx.h>
23 #include <plat/i2c.h>
24 #include <plat/gpio.h>
25 #include <plat/mmc.h>
26 #include <plat/mcbsp.h>
27 #include <plat/mcspi.h>
28 #include <plat/dmtimer.h>
29
30 #include "omap_hwmod_common_data.h"
31
32 #include "smartreflex.h"
33 #include "prm-regbits-34xx.h"
34 #include "cm-regbits-34xx.h"
35 #include "wd_timer.h"
36 #include <mach/am35xx.h>
37
38 /*
39 * OMAP3xxx hardware module integration data
40 *
41 * ALl of the data in this section should be autogeneratable from the
42 * TI hardware database or other technical documentation. Data that
43 * is driver-specific or driver-kernel integration-specific belongs
44 * elsewhere.
45 */
46
47 static struct omap_hwmod omap3xxx_mpu_hwmod;
48 static struct omap_hwmod omap3xxx_iva_hwmod;
49 static struct omap_hwmod omap3xxx_l3_main_hwmod;
50 static struct omap_hwmod omap3xxx_l4_core_hwmod;
51 static struct omap_hwmod omap3xxx_l4_per_hwmod;
52 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
53 static struct omap_hwmod omap3430es1_dss_core_hwmod;
54 static struct omap_hwmod omap3xxx_dss_core_hwmod;
55 static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
56 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
57 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
58 static struct omap_hwmod omap3xxx_dss_venc_hwmod;
59 static struct omap_hwmod omap3xxx_i2c1_hwmod;
60 static struct omap_hwmod omap3xxx_i2c2_hwmod;
61 static struct omap_hwmod omap3xxx_i2c3_hwmod;
62 static struct omap_hwmod omap3xxx_gpio1_hwmod;
63 static struct omap_hwmod omap3xxx_gpio2_hwmod;
64 static struct omap_hwmod omap3xxx_gpio3_hwmod;
65 static struct omap_hwmod omap3xxx_gpio4_hwmod;
66 static struct omap_hwmod omap3xxx_gpio5_hwmod;
67 static struct omap_hwmod omap3xxx_gpio6_hwmod;
68 static struct omap_hwmod omap34xx_sr1_hwmod;
69 static struct omap_hwmod omap34xx_sr2_hwmod;
70 static struct omap_hwmod omap34xx_mcspi1;
71 static struct omap_hwmod omap34xx_mcspi2;
72 static struct omap_hwmod omap34xx_mcspi3;
73 static struct omap_hwmod omap34xx_mcspi4;
74 static struct omap_hwmod omap3xxx_mmc1_hwmod;
75 static struct omap_hwmod omap3xxx_mmc2_hwmod;
76 static struct omap_hwmod omap3xxx_mmc3_hwmod;
77 static struct omap_hwmod am35xx_usbhsotg_hwmod;
78
79 static struct omap_hwmod omap3xxx_dma_system_hwmod;
80
81 static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
82 static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
83 static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
84 static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
85 static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
86 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
87 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
88 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod;
89 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod;
90
91 /* L3 -> L4_CORE interface */
92 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
93 .master = &omap3xxx_l3_main_hwmod,
94 .slave = &omap3xxx_l4_core_hwmod,
95 .user = OCP_USER_MPU | OCP_USER_SDMA,
96 };
97
98 /* L3 -> L4_PER interface */
99 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
100 .master = &omap3xxx_l3_main_hwmod,
101 .slave = &omap3xxx_l4_per_hwmod,
102 .user = OCP_USER_MPU | OCP_USER_SDMA,
103 };
104
105 /* L3 taret configuration and error log registers */
106 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
107 { .irq = INT_34XX_L3_DBG_IRQ },
108 { .irq = INT_34XX_L3_APP_IRQ },
109 { .irq = -1 }
110 };
111
112 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
113 {
114 .pa_start = 0x68000000,
115 .pa_end = 0x6800ffff,
116 .flags = ADDR_TYPE_RT,
117 },
118 { }
119 };
120
121 /* MPU -> L3 interface */
122 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
123 .master = &omap3xxx_mpu_hwmod,
124 .slave = &omap3xxx_l3_main_hwmod,
125 .addr = omap3xxx_l3_main_addrs,
126 .user = OCP_USER_MPU,
127 };
128
129 /* Slave interfaces on the L3 interconnect */
130 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
131 &omap3xxx_mpu__l3_main,
132 };
133
134 /* DSS -> l3 */
135 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
136 .master = &omap3xxx_dss_core_hwmod,
137 .slave = &omap3xxx_l3_main_hwmod,
138 .fw = {
139 .omap2 = {
140 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
141 .flags = OMAP_FIREWALL_L3,
142 }
143 },
144 .user = OCP_USER_MPU | OCP_USER_SDMA,
145 };
146
147 /* Master interfaces on the L3 interconnect */
148 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
149 &omap3xxx_l3_main__l4_core,
150 &omap3xxx_l3_main__l4_per,
151 };
152
153 /* L3 */
154 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
155 .name = "l3_main",
156 .class = &l3_hwmod_class,
157 .mpu_irqs = omap3xxx_l3_main_irqs,
158 .masters = omap3xxx_l3_main_masters,
159 .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
160 .slaves = omap3xxx_l3_main_slaves,
161 .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves),
162 .flags = HWMOD_NO_IDLEST,
163 };
164
165 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
166 static struct omap_hwmod omap3xxx_uart1_hwmod;
167 static struct omap_hwmod omap3xxx_uart2_hwmod;
168 static struct omap_hwmod omap3xxx_uart3_hwmod;
169 static struct omap_hwmod omap3xxx_uart4_hwmod;
170 static struct omap_hwmod am35xx_uart4_hwmod;
171 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
172
173 /* l3_core -> usbhsotg interface */
174 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
175 .master = &omap3xxx_usbhsotg_hwmod,
176 .slave = &omap3xxx_l3_main_hwmod,
177 .clk = "core_l3_ick",
178 .user = OCP_USER_MPU,
179 };
180
181 /* l3_core -> am35xx_usbhsotg interface */
182 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
183 .master = &am35xx_usbhsotg_hwmod,
184 .slave = &omap3xxx_l3_main_hwmod,
185 .clk = "core_l3_ick",
186 .user = OCP_USER_MPU,
187 };
188 /* L4_CORE -> L4_WKUP interface */
189 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
190 .master = &omap3xxx_l4_core_hwmod,
191 .slave = &omap3xxx_l4_wkup_hwmod,
192 .user = OCP_USER_MPU | OCP_USER_SDMA,
193 };
194
195 /* L4 CORE -> MMC1 interface */
196 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
197 .master = &omap3xxx_l4_core_hwmod,
198 .slave = &omap3xxx_mmc1_hwmod,
199 .clk = "mmchs1_ick",
200 .addr = omap2430_mmc1_addr_space,
201 .user = OCP_USER_MPU | OCP_USER_SDMA,
202 .flags = OMAP_FIREWALL_L4
203 };
204
205 /* L4 CORE -> MMC2 interface */
206 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
207 .master = &omap3xxx_l4_core_hwmod,
208 .slave = &omap3xxx_mmc2_hwmod,
209 .clk = "mmchs2_ick",
210 .addr = omap2430_mmc2_addr_space,
211 .user = OCP_USER_MPU | OCP_USER_SDMA,
212 .flags = OMAP_FIREWALL_L4
213 };
214
215 /* L4 CORE -> MMC3 interface */
216 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
217 {
218 .pa_start = 0x480ad000,
219 .pa_end = 0x480ad1ff,
220 .flags = ADDR_TYPE_RT,
221 },
222 { }
223 };
224
225 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
226 .master = &omap3xxx_l4_core_hwmod,
227 .slave = &omap3xxx_mmc3_hwmod,
228 .clk = "mmchs3_ick",
229 .addr = omap3xxx_mmc3_addr_space,
230 .user = OCP_USER_MPU | OCP_USER_SDMA,
231 .flags = OMAP_FIREWALL_L4
232 };
233
234 /* L4 CORE -> UART1 interface */
235 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
236 {
237 .pa_start = OMAP3_UART1_BASE,
238 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
239 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
240 },
241 { }
242 };
243
244 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
245 .master = &omap3xxx_l4_core_hwmod,
246 .slave = &omap3xxx_uart1_hwmod,
247 .clk = "uart1_ick",
248 .addr = omap3xxx_uart1_addr_space,
249 .user = OCP_USER_MPU | OCP_USER_SDMA,
250 };
251
252 /* L4 CORE -> UART2 interface */
253 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
254 {
255 .pa_start = OMAP3_UART2_BASE,
256 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
257 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
258 },
259 { }
260 };
261
262 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
263 .master = &omap3xxx_l4_core_hwmod,
264 .slave = &omap3xxx_uart2_hwmod,
265 .clk = "uart2_ick",
266 .addr = omap3xxx_uart2_addr_space,
267 .user = OCP_USER_MPU | OCP_USER_SDMA,
268 };
269
270 /* L4 PER -> UART3 interface */
271 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
272 {
273 .pa_start = OMAP3_UART3_BASE,
274 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
275 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
276 },
277 { }
278 };
279
280 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
281 .master = &omap3xxx_l4_per_hwmod,
282 .slave = &omap3xxx_uart3_hwmod,
283 .clk = "uart3_ick",
284 .addr = omap3xxx_uart3_addr_space,
285 .user = OCP_USER_MPU | OCP_USER_SDMA,
286 };
287
288 /* L4 PER -> UART4 interface */
289 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
290 {
291 .pa_start = OMAP3_UART4_BASE,
292 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
293 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
294 },
295 { }
296 };
297
298 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
299 .master = &omap3xxx_l4_per_hwmod,
300 .slave = &omap3xxx_uart4_hwmod,
301 .clk = "uart4_ick",
302 .addr = omap3xxx_uart4_addr_space,
303 .user = OCP_USER_MPU | OCP_USER_SDMA,
304 };
305
306 /* AM35xx: L4 CORE -> UART4 interface */
307 static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
308 {
309 .pa_start = OMAP3_UART4_AM35XX_BASE,
310 .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
311 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
312 },
313 };
314
315 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
316 .master = &omap3xxx_l4_core_hwmod,
317 .slave = &am35xx_uart4_hwmod,
318 .clk = "uart4_ick",
319 .addr = am35xx_uart4_addr_space,
320 .user = OCP_USER_MPU | OCP_USER_SDMA,
321 };
322
323 /* L4 CORE -> I2C1 interface */
324 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
325 .master = &omap3xxx_l4_core_hwmod,
326 .slave = &omap3xxx_i2c1_hwmod,
327 .clk = "i2c1_ick",
328 .addr = omap2_i2c1_addr_space,
329 .fw = {
330 .omap2 = {
331 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
332 .l4_prot_group = 7,
333 .flags = OMAP_FIREWALL_L4,
334 }
335 },
336 .user = OCP_USER_MPU | OCP_USER_SDMA,
337 };
338
339 /* L4 CORE -> I2C2 interface */
340 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
341 .master = &omap3xxx_l4_core_hwmod,
342 .slave = &omap3xxx_i2c2_hwmod,
343 .clk = "i2c2_ick",
344 .addr = omap2_i2c2_addr_space,
345 .fw = {
346 .omap2 = {
347 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
348 .l4_prot_group = 7,
349 .flags = OMAP_FIREWALL_L4,
350 }
351 },
352 .user = OCP_USER_MPU | OCP_USER_SDMA,
353 };
354
355 /* L4 CORE -> I2C3 interface */
356 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
357 {
358 .pa_start = 0x48060000,
359 .pa_end = 0x48060000 + SZ_128 - 1,
360 .flags = ADDR_TYPE_RT,
361 },
362 { }
363 };
364
365 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
366 .master = &omap3xxx_l4_core_hwmod,
367 .slave = &omap3xxx_i2c3_hwmod,
368 .clk = "i2c3_ick",
369 .addr = omap3xxx_i2c3_addr_space,
370 .fw = {
371 .omap2 = {
372 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
373 .l4_prot_group = 7,
374 .flags = OMAP_FIREWALL_L4,
375 }
376 },
377 .user = OCP_USER_MPU | OCP_USER_SDMA,
378 };
379
380 /* L4 CORE -> SR1 interface */
381 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
382 {
383 .pa_start = OMAP34XX_SR1_BASE,
384 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
385 .flags = ADDR_TYPE_RT,
386 },
387 { }
388 };
389
390 static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
391 .master = &omap3xxx_l4_core_hwmod,
392 .slave = &omap34xx_sr1_hwmod,
393 .clk = "sr_l4_ick",
394 .addr = omap3_sr1_addr_space,
395 .user = OCP_USER_MPU,
396 };
397
398 /* L4 CORE -> SR1 interface */
399 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
400 {
401 .pa_start = OMAP34XX_SR2_BASE,
402 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
403 .flags = ADDR_TYPE_RT,
404 },
405 { }
406 };
407
408 static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
409 .master = &omap3xxx_l4_core_hwmod,
410 .slave = &omap34xx_sr2_hwmod,
411 .clk = "sr_l4_ick",
412 .addr = omap3_sr2_addr_space,
413 .user = OCP_USER_MPU,
414 };
415
416 /*
417 * usbhsotg interface data
418 */
419
420 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
421 {
422 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
423 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
424 .flags = ADDR_TYPE_RT
425 },
426 { }
427 };
428
429 /* l4_core -> usbhsotg */
430 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
431 .master = &omap3xxx_l4_core_hwmod,
432 .slave = &omap3xxx_usbhsotg_hwmod,
433 .clk = "l4_ick",
434 .addr = omap3xxx_usbhsotg_addrs,
435 .user = OCP_USER_MPU,
436 };
437
438 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
439 &omap3xxx_usbhsotg__l3,
440 };
441
442 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
443 &omap3xxx_l4_core__usbhsotg,
444 };
445
446 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
447 {
448 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
449 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
450 .flags = ADDR_TYPE_RT
451 },
452 { }
453 };
454
455 /* l4_core -> usbhsotg */
456 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
457 .master = &omap3xxx_l4_core_hwmod,
458 .slave = &am35xx_usbhsotg_hwmod,
459 .clk = "l4_ick",
460 .addr = am35xx_usbhsotg_addrs,
461 .user = OCP_USER_MPU,
462 };
463
464 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
465 &am35xx_usbhsotg__l3,
466 };
467
468 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
469 &am35xx_l4_core__usbhsotg,
470 };
471 /* Slave interfaces on the L4_CORE interconnect */
472 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
473 &omap3xxx_l3_main__l4_core,
474 };
475
476 /* L4 CORE */
477 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
478 .name = "l4_core",
479 .class = &l4_hwmod_class,
480 .slaves = omap3xxx_l4_core_slaves,
481 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves),
482 .flags = HWMOD_NO_IDLEST,
483 };
484
485 /* Slave interfaces on the L4_PER interconnect */
486 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
487 &omap3xxx_l3_main__l4_per,
488 };
489
490 /* L4 PER */
491 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
492 .name = "l4_per",
493 .class = &l4_hwmod_class,
494 .slaves = omap3xxx_l4_per_slaves,
495 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves),
496 .flags = HWMOD_NO_IDLEST,
497 };
498
499 /* Slave interfaces on the L4_WKUP interconnect */
500 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
501 &omap3xxx_l4_core__l4_wkup,
502 };
503
504 /* L4 WKUP */
505 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
506 .name = "l4_wkup",
507 .class = &l4_hwmod_class,
508 .slaves = omap3xxx_l4_wkup_slaves,
509 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
510 .flags = HWMOD_NO_IDLEST,
511 };
512
513 /* Master interfaces on the MPU device */
514 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
515 &omap3xxx_mpu__l3_main,
516 };
517
518 /* MPU */
519 static struct omap_hwmod omap3xxx_mpu_hwmod = {
520 .name = "mpu",
521 .class = &mpu_hwmod_class,
522 .main_clk = "arm_fck",
523 .masters = omap3xxx_mpu_masters,
524 .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters),
525 };
526
527 /*
528 * IVA2_2 interface data
529 */
530
531 /* IVA2 <- L3 interface */
532 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
533 .master = &omap3xxx_l3_main_hwmod,
534 .slave = &omap3xxx_iva_hwmod,
535 .clk = "iva2_ck",
536 .user = OCP_USER_MPU | OCP_USER_SDMA,
537 };
538
539 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
540 &omap3xxx_l3__iva,
541 };
542
543 /*
544 * IVA2 (IVA2)
545 */
546
547 static struct omap_hwmod omap3xxx_iva_hwmod = {
548 .name = "iva",
549 .class = &iva_hwmod_class,
550 .masters = omap3xxx_iva_masters,
551 .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters),
552 };
553
554 /* timer class */
555 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
556 .rev_offs = 0x0000,
557 .sysc_offs = 0x0010,
558 .syss_offs = 0x0014,
559 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
560 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
561 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
562 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
563 .sysc_fields = &omap_hwmod_sysc_type1,
564 };
565
566 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
567 .name = "timer",
568 .sysc = &omap3xxx_timer_1ms_sysc,
569 .rev = OMAP_TIMER_IP_VERSION_1,
570 };
571
572 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
573 .rev_offs = 0x0000,
574 .sysc_offs = 0x0010,
575 .syss_offs = 0x0014,
576 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
577 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
578 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
579 .sysc_fields = &omap_hwmod_sysc_type1,
580 };
581
582 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
583 .name = "timer",
584 .sysc = &omap3xxx_timer_sysc,
585 .rev = OMAP_TIMER_IP_VERSION_1,
586 };
587
588 /* secure timers dev attribute */
589 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
590 .timer_capability = OMAP_TIMER_SECURE,
591 };
592
593 /* always-on timers dev attribute */
594 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
595 .timer_capability = OMAP_TIMER_ALWON,
596 };
597
598 /* pwm timers dev attribute */
599 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
600 .timer_capability = OMAP_TIMER_HAS_PWM,
601 };
602
603 /* timer1 */
604 static struct omap_hwmod omap3xxx_timer1_hwmod;
605
606 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
607 {
608 .pa_start = 0x48318000,
609 .pa_end = 0x48318000 + SZ_1K - 1,
610 .flags = ADDR_TYPE_RT
611 },
612 { }
613 };
614
615 /* l4_wkup -> timer1 */
616 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
617 .master = &omap3xxx_l4_wkup_hwmod,
618 .slave = &omap3xxx_timer1_hwmod,
619 .clk = "gpt1_ick",
620 .addr = omap3xxx_timer1_addrs,
621 .user = OCP_USER_MPU | OCP_USER_SDMA,
622 };
623
624 /* timer1 slave port */
625 static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
626 &omap3xxx_l4_wkup__timer1,
627 };
628
629 /* timer1 hwmod */
630 static struct omap_hwmod omap3xxx_timer1_hwmod = {
631 .name = "timer1",
632 .mpu_irqs = omap2_timer1_mpu_irqs,
633 .main_clk = "gpt1_fck",
634 .prcm = {
635 .omap2 = {
636 .prcm_reg_id = 1,
637 .module_bit = OMAP3430_EN_GPT1_SHIFT,
638 .module_offs = WKUP_MOD,
639 .idlest_reg_id = 1,
640 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
641 },
642 },
643 .dev_attr = &capability_alwon_dev_attr,
644 .slaves = omap3xxx_timer1_slaves,
645 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer1_slaves),
646 .class = &omap3xxx_timer_1ms_hwmod_class,
647 };
648
649 /* timer2 */
650 static struct omap_hwmod omap3xxx_timer2_hwmod;
651
652 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
653 {
654 .pa_start = 0x49032000,
655 .pa_end = 0x49032000 + SZ_1K - 1,
656 .flags = ADDR_TYPE_RT
657 },
658 { }
659 };
660
661 /* l4_per -> timer2 */
662 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
663 .master = &omap3xxx_l4_per_hwmod,
664 .slave = &omap3xxx_timer2_hwmod,
665 .clk = "gpt2_ick",
666 .addr = omap3xxx_timer2_addrs,
667 .user = OCP_USER_MPU | OCP_USER_SDMA,
668 };
669
670 /* timer2 slave port */
671 static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
672 &omap3xxx_l4_per__timer2,
673 };
674
675 /* timer2 hwmod */
676 static struct omap_hwmod omap3xxx_timer2_hwmod = {
677 .name = "timer2",
678 .mpu_irqs = omap2_timer2_mpu_irqs,
679 .main_clk = "gpt2_fck",
680 .prcm = {
681 .omap2 = {
682 .prcm_reg_id = 1,
683 .module_bit = OMAP3430_EN_GPT2_SHIFT,
684 .module_offs = OMAP3430_PER_MOD,
685 .idlest_reg_id = 1,
686 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
687 },
688 },
689 .dev_attr = &capability_alwon_dev_attr,
690 .slaves = omap3xxx_timer2_slaves,
691 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer2_slaves),
692 .class = &omap3xxx_timer_1ms_hwmod_class,
693 };
694
695 /* timer3 */
696 static struct omap_hwmod omap3xxx_timer3_hwmod;
697
698 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
699 {
700 .pa_start = 0x49034000,
701 .pa_end = 0x49034000 + SZ_1K - 1,
702 .flags = ADDR_TYPE_RT
703 },
704 { }
705 };
706
707 /* l4_per -> timer3 */
708 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
709 .master = &omap3xxx_l4_per_hwmod,
710 .slave = &omap3xxx_timer3_hwmod,
711 .clk = "gpt3_ick",
712 .addr = omap3xxx_timer3_addrs,
713 .user = OCP_USER_MPU | OCP_USER_SDMA,
714 };
715
716 /* timer3 slave port */
717 static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
718 &omap3xxx_l4_per__timer3,
719 };
720
721 /* timer3 hwmod */
722 static struct omap_hwmod omap3xxx_timer3_hwmod = {
723 .name = "timer3",
724 .mpu_irqs = omap2_timer3_mpu_irqs,
725 .main_clk = "gpt3_fck",
726 .prcm = {
727 .omap2 = {
728 .prcm_reg_id = 1,
729 .module_bit = OMAP3430_EN_GPT3_SHIFT,
730 .module_offs = OMAP3430_PER_MOD,
731 .idlest_reg_id = 1,
732 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
733 },
734 },
735 .dev_attr = &capability_alwon_dev_attr,
736 .slaves = omap3xxx_timer3_slaves,
737 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer3_slaves),
738 .class = &omap3xxx_timer_hwmod_class,
739 };
740
741 /* timer4 */
742 static struct omap_hwmod omap3xxx_timer4_hwmod;
743
744 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
745 {
746 .pa_start = 0x49036000,
747 .pa_end = 0x49036000 + SZ_1K - 1,
748 .flags = ADDR_TYPE_RT
749 },
750 { }
751 };
752
753 /* l4_per -> timer4 */
754 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
755 .master = &omap3xxx_l4_per_hwmod,
756 .slave = &omap3xxx_timer4_hwmod,
757 .clk = "gpt4_ick",
758 .addr = omap3xxx_timer4_addrs,
759 .user = OCP_USER_MPU | OCP_USER_SDMA,
760 };
761
762 /* timer4 slave port */
763 static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
764 &omap3xxx_l4_per__timer4,
765 };
766
767 /* timer4 hwmod */
768 static struct omap_hwmod omap3xxx_timer4_hwmod = {
769 .name = "timer4",
770 .mpu_irqs = omap2_timer4_mpu_irqs,
771 .main_clk = "gpt4_fck",
772 .prcm = {
773 .omap2 = {
774 .prcm_reg_id = 1,
775 .module_bit = OMAP3430_EN_GPT4_SHIFT,
776 .module_offs = OMAP3430_PER_MOD,
777 .idlest_reg_id = 1,
778 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
779 },
780 },
781 .dev_attr = &capability_alwon_dev_attr,
782 .slaves = omap3xxx_timer4_slaves,
783 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer4_slaves),
784 .class = &omap3xxx_timer_hwmod_class,
785 };
786
787 /* timer5 */
788 static struct omap_hwmod omap3xxx_timer5_hwmod;
789
790 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
791 {
792 .pa_start = 0x49038000,
793 .pa_end = 0x49038000 + SZ_1K - 1,
794 .flags = ADDR_TYPE_RT
795 },
796 { }
797 };
798
799 /* l4_per -> timer5 */
800 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
801 .master = &omap3xxx_l4_per_hwmod,
802 .slave = &omap3xxx_timer5_hwmod,
803 .clk = "gpt5_ick",
804 .addr = omap3xxx_timer5_addrs,
805 .user = OCP_USER_MPU | OCP_USER_SDMA,
806 };
807
808 /* timer5 slave port */
809 static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
810 &omap3xxx_l4_per__timer5,
811 };
812
813 /* timer5 hwmod */
814 static struct omap_hwmod omap3xxx_timer5_hwmod = {
815 .name = "timer5",
816 .mpu_irqs = omap2_timer5_mpu_irqs,
817 .main_clk = "gpt5_fck",
818 .prcm = {
819 .omap2 = {
820 .prcm_reg_id = 1,
821 .module_bit = OMAP3430_EN_GPT5_SHIFT,
822 .module_offs = OMAP3430_PER_MOD,
823 .idlest_reg_id = 1,
824 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
825 },
826 },
827 .dev_attr = &capability_alwon_dev_attr,
828 .slaves = omap3xxx_timer5_slaves,
829 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer5_slaves),
830 .class = &omap3xxx_timer_hwmod_class,
831 };
832
833 /* timer6 */
834 static struct omap_hwmod omap3xxx_timer6_hwmod;
835
836 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
837 {
838 .pa_start = 0x4903A000,
839 .pa_end = 0x4903A000 + SZ_1K - 1,
840 .flags = ADDR_TYPE_RT
841 },
842 { }
843 };
844
845 /* l4_per -> timer6 */
846 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
847 .master = &omap3xxx_l4_per_hwmod,
848 .slave = &omap3xxx_timer6_hwmod,
849 .clk = "gpt6_ick",
850 .addr = omap3xxx_timer6_addrs,
851 .user = OCP_USER_MPU | OCP_USER_SDMA,
852 };
853
854 /* timer6 slave port */
855 static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
856 &omap3xxx_l4_per__timer6,
857 };
858
859 /* timer6 hwmod */
860 static struct omap_hwmod omap3xxx_timer6_hwmod = {
861 .name = "timer6",
862 .mpu_irqs = omap2_timer6_mpu_irqs,
863 .main_clk = "gpt6_fck",
864 .prcm = {
865 .omap2 = {
866 .prcm_reg_id = 1,
867 .module_bit = OMAP3430_EN_GPT6_SHIFT,
868 .module_offs = OMAP3430_PER_MOD,
869 .idlest_reg_id = 1,
870 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
871 },
872 },
873 .dev_attr = &capability_alwon_dev_attr,
874 .slaves = omap3xxx_timer6_slaves,
875 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer6_slaves),
876 .class = &omap3xxx_timer_hwmod_class,
877 };
878
879 /* timer7 */
880 static struct omap_hwmod omap3xxx_timer7_hwmod;
881
882 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
883 {
884 .pa_start = 0x4903C000,
885 .pa_end = 0x4903C000 + SZ_1K - 1,
886 .flags = ADDR_TYPE_RT
887 },
888 { }
889 };
890
891 /* l4_per -> timer7 */
892 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
893 .master = &omap3xxx_l4_per_hwmod,
894 .slave = &omap3xxx_timer7_hwmod,
895 .clk = "gpt7_ick",
896 .addr = omap3xxx_timer7_addrs,
897 .user = OCP_USER_MPU | OCP_USER_SDMA,
898 };
899
900 /* timer7 slave port */
901 static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
902 &omap3xxx_l4_per__timer7,
903 };
904
905 /* timer7 hwmod */
906 static struct omap_hwmod omap3xxx_timer7_hwmod = {
907 .name = "timer7",
908 .mpu_irqs = omap2_timer7_mpu_irqs,
909 .main_clk = "gpt7_fck",
910 .prcm = {
911 .omap2 = {
912 .prcm_reg_id = 1,
913 .module_bit = OMAP3430_EN_GPT7_SHIFT,
914 .module_offs = OMAP3430_PER_MOD,
915 .idlest_reg_id = 1,
916 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
917 },
918 },
919 .dev_attr = &capability_alwon_dev_attr,
920 .slaves = omap3xxx_timer7_slaves,
921 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer7_slaves),
922 .class = &omap3xxx_timer_hwmod_class,
923 };
924
925 /* timer8 */
926 static struct omap_hwmod omap3xxx_timer8_hwmod;
927
928 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
929 {
930 .pa_start = 0x4903E000,
931 .pa_end = 0x4903E000 + SZ_1K - 1,
932 .flags = ADDR_TYPE_RT
933 },
934 { }
935 };
936
937 /* l4_per -> timer8 */
938 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
939 .master = &omap3xxx_l4_per_hwmod,
940 .slave = &omap3xxx_timer8_hwmod,
941 .clk = "gpt8_ick",
942 .addr = omap3xxx_timer8_addrs,
943 .user = OCP_USER_MPU | OCP_USER_SDMA,
944 };
945
946 /* timer8 slave port */
947 static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
948 &omap3xxx_l4_per__timer8,
949 };
950
951 /* timer8 hwmod */
952 static struct omap_hwmod omap3xxx_timer8_hwmod = {
953 .name = "timer8",
954 .mpu_irqs = omap2_timer8_mpu_irqs,
955 .main_clk = "gpt8_fck",
956 .prcm = {
957 .omap2 = {
958 .prcm_reg_id = 1,
959 .module_bit = OMAP3430_EN_GPT8_SHIFT,
960 .module_offs = OMAP3430_PER_MOD,
961 .idlest_reg_id = 1,
962 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
963 },
964 },
965 .dev_attr = &capability_pwm_dev_attr,
966 .slaves = omap3xxx_timer8_slaves,
967 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer8_slaves),
968 .class = &omap3xxx_timer_hwmod_class,
969 };
970
971 /* timer9 */
972 static struct omap_hwmod omap3xxx_timer9_hwmod;
973
974 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
975 {
976 .pa_start = 0x49040000,
977 .pa_end = 0x49040000 + SZ_1K - 1,
978 .flags = ADDR_TYPE_RT
979 },
980 { }
981 };
982
983 /* l4_per -> timer9 */
984 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
985 .master = &omap3xxx_l4_per_hwmod,
986 .slave = &omap3xxx_timer9_hwmod,
987 .clk = "gpt9_ick",
988 .addr = omap3xxx_timer9_addrs,
989 .user = OCP_USER_MPU | OCP_USER_SDMA,
990 };
991
992 /* timer9 slave port */
993 static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
994 &omap3xxx_l4_per__timer9,
995 };
996
997 /* timer9 hwmod */
998 static struct omap_hwmod omap3xxx_timer9_hwmod = {
999 .name = "timer9",
1000 .mpu_irqs = omap2_timer9_mpu_irqs,
1001 .main_clk = "gpt9_fck",
1002 .prcm = {
1003 .omap2 = {
1004 .prcm_reg_id = 1,
1005 .module_bit = OMAP3430_EN_GPT9_SHIFT,
1006 .module_offs = OMAP3430_PER_MOD,
1007 .idlest_reg_id = 1,
1008 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
1009 },
1010 },
1011 .dev_attr = &capability_pwm_dev_attr,
1012 .slaves = omap3xxx_timer9_slaves,
1013 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer9_slaves),
1014 .class = &omap3xxx_timer_hwmod_class,
1015 };
1016
1017 /* timer10 */
1018 static struct omap_hwmod omap3xxx_timer10_hwmod;
1019
1020 /* l4_core -> timer10 */
1021 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1022 .master = &omap3xxx_l4_core_hwmod,
1023 .slave = &omap3xxx_timer10_hwmod,
1024 .clk = "gpt10_ick",
1025 .addr = omap2_timer10_addrs,
1026 .user = OCP_USER_MPU | OCP_USER_SDMA,
1027 };
1028
1029 /* timer10 slave port */
1030 static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1031 &omap3xxx_l4_core__timer10,
1032 };
1033
1034 /* timer10 hwmod */
1035 static struct omap_hwmod omap3xxx_timer10_hwmod = {
1036 .name = "timer10",
1037 .mpu_irqs = omap2_timer10_mpu_irqs,
1038 .main_clk = "gpt10_fck",
1039 .prcm = {
1040 .omap2 = {
1041 .prcm_reg_id = 1,
1042 .module_bit = OMAP3430_EN_GPT10_SHIFT,
1043 .module_offs = CORE_MOD,
1044 .idlest_reg_id = 1,
1045 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
1046 },
1047 },
1048 .dev_attr = &capability_pwm_dev_attr,
1049 .slaves = omap3xxx_timer10_slaves,
1050 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer10_slaves),
1051 .class = &omap3xxx_timer_1ms_hwmod_class,
1052 };
1053
1054 /* timer11 */
1055 static struct omap_hwmod omap3xxx_timer11_hwmod;
1056
1057 /* l4_core -> timer11 */
1058 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1059 .master = &omap3xxx_l4_core_hwmod,
1060 .slave = &omap3xxx_timer11_hwmod,
1061 .clk = "gpt11_ick",
1062 .addr = omap2_timer11_addrs,
1063 .user = OCP_USER_MPU | OCP_USER_SDMA,
1064 };
1065
1066 /* timer11 slave port */
1067 static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1068 &omap3xxx_l4_core__timer11,
1069 };
1070
1071 /* timer11 hwmod */
1072 static struct omap_hwmod omap3xxx_timer11_hwmod = {
1073 .name = "timer11",
1074 .mpu_irqs = omap2_timer11_mpu_irqs,
1075 .main_clk = "gpt11_fck",
1076 .prcm = {
1077 .omap2 = {
1078 .prcm_reg_id = 1,
1079 .module_bit = OMAP3430_EN_GPT11_SHIFT,
1080 .module_offs = CORE_MOD,
1081 .idlest_reg_id = 1,
1082 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
1083 },
1084 },
1085 .dev_attr = &capability_pwm_dev_attr,
1086 .slaves = omap3xxx_timer11_slaves,
1087 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer11_slaves),
1088 .class = &omap3xxx_timer_hwmod_class,
1089 };
1090
1091 /* timer12*/
1092 static struct omap_hwmod omap3xxx_timer12_hwmod;
1093 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1094 { .irq = 95, },
1095 { .irq = -1 }
1096 };
1097
1098 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1099 {
1100 .pa_start = 0x48304000,
1101 .pa_end = 0x48304000 + SZ_1K - 1,
1102 .flags = ADDR_TYPE_RT
1103 },
1104 { }
1105 };
1106
1107 /* l4_core -> timer12 */
1108 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1109 .master = &omap3xxx_l4_core_hwmod,
1110 .slave = &omap3xxx_timer12_hwmod,
1111 .clk = "gpt12_ick",
1112 .addr = omap3xxx_timer12_addrs,
1113 .user = OCP_USER_MPU | OCP_USER_SDMA,
1114 };
1115
1116 /* timer12 slave port */
1117 static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1118 &omap3xxx_l4_core__timer12,
1119 };
1120
1121 /* timer12 hwmod */
1122 static struct omap_hwmod omap3xxx_timer12_hwmod = {
1123 .name = "timer12",
1124 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
1125 .main_clk = "gpt12_fck",
1126 .prcm = {
1127 .omap2 = {
1128 .prcm_reg_id = 1,
1129 .module_bit = OMAP3430_EN_GPT12_SHIFT,
1130 .module_offs = WKUP_MOD,
1131 .idlest_reg_id = 1,
1132 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
1133 },
1134 },
1135 .dev_attr = &capability_secure_dev_attr,
1136 .slaves = omap3xxx_timer12_slaves,
1137 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer12_slaves),
1138 .class = &omap3xxx_timer_hwmod_class,
1139 };
1140
1141 /* l4_wkup -> wd_timer2 */
1142 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1143 {
1144 .pa_start = 0x48314000,
1145 .pa_end = 0x4831407f,
1146 .flags = ADDR_TYPE_RT
1147 },
1148 { }
1149 };
1150
1151 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1152 .master = &omap3xxx_l4_wkup_hwmod,
1153 .slave = &omap3xxx_wd_timer2_hwmod,
1154 .clk = "wdt2_ick",
1155 .addr = omap3xxx_wd_timer2_addrs,
1156 .user = OCP_USER_MPU | OCP_USER_SDMA,
1157 };
1158
1159 /*
1160 * 'wd_timer' class
1161 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1162 * overflow condition
1163 */
1164
1165 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
1166 .rev_offs = 0x0000,
1167 .sysc_offs = 0x0010,
1168 .syss_offs = 0x0014,
1169 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
1170 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1171 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1172 SYSS_HAS_RESET_STATUS),
1173 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1174 .sysc_fields = &omap_hwmod_sysc_type1,
1175 };
1176
1177 /* I2C common */
1178 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1179 .rev_offs = 0x00,
1180 .sysc_offs = 0x20,
1181 .syss_offs = 0x10,
1182 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1183 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1184 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1185 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1186 .clockact = CLOCKACT_TEST_ICLK,
1187 .sysc_fields = &omap_hwmod_sysc_type1,
1188 };
1189
1190 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
1191 .name = "wd_timer",
1192 .sysc = &omap3xxx_wd_timer_sysc,
1193 .pre_shutdown = &omap2_wd_timer_disable
1194 };
1195
1196 /* wd_timer2 */
1197 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
1198 &omap3xxx_l4_wkup__wd_timer2,
1199 };
1200
1201 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1202 .name = "wd_timer2",
1203 .class = &omap3xxx_wd_timer_hwmod_class,
1204 .main_clk = "wdt2_fck",
1205 .prcm = {
1206 .omap2 = {
1207 .prcm_reg_id = 1,
1208 .module_bit = OMAP3430_EN_WDT2_SHIFT,
1209 .module_offs = WKUP_MOD,
1210 .idlest_reg_id = 1,
1211 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
1212 },
1213 },
1214 .slaves = omap3xxx_wd_timer2_slaves,
1215 .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1216 /*
1217 * XXX: Use software supervised mode, HW supervised smartidle seems to
1218 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
1219 */
1220 .flags = HWMOD_SWSUP_SIDLE,
1221 };
1222
1223 /* UART1 */
1224
1225 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1226 &omap3_l4_core__uart1,
1227 };
1228
1229 static struct omap_hwmod omap3xxx_uart1_hwmod = {
1230 .name = "uart1",
1231 .mpu_irqs = omap2_uart1_mpu_irqs,
1232 .sdma_reqs = omap2_uart1_sdma_reqs,
1233 .main_clk = "uart1_fck",
1234 .prcm = {
1235 .omap2 = {
1236 .module_offs = CORE_MOD,
1237 .prcm_reg_id = 1,
1238 .module_bit = OMAP3430_EN_UART1_SHIFT,
1239 .idlest_reg_id = 1,
1240 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
1241 },
1242 },
1243 .slaves = omap3xxx_uart1_slaves,
1244 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
1245 .class = &omap2_uart_class,
1246 };
1247
1248 /* UART2 */
1249
1250 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1251 &omap3_l4_core__uart2,
1252 };
1253
1254 static struct omap_hwmod omap3xxx_uart2_hwmod = {
1255 .name = "uart2",
1256 .mpu_irqs = omap2_uart2_mpu_irqs,
1257 .sdma_reqs = omap2_uart2_sdma_reqs,
1258 .main_clk = "uart2_fck",
1259 .prcm = {
1260 .omap2 = {
1261 .module_offs = CORE_MOD,
1262 .prcm_reg_id = 1,
1263 .module_bit = OMAP3430_EN_UART2_SHIFT,
1264 .idlest_reg_id = 1,
1265 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
1266 },
1267 },
1268 .slaves = omap3xxx_uart2_slaves,
1269 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
1270 .class = &omap2_uart_class,
1271 };
1272
1273 /* UART3 */
1274
1275 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1276 &omap3_l4_per__uart3,
1277 };
1278
1279 static struct omap_hwmod omap3xxx_uart3_hwmod = {
1280 .name = "uart3",
1281 .mpu_irqs = omap2_uart3_mpu_irqs,
1282 .sdma_reqs = omap2_uart3_sdma_reqs,
1283 .main_clk = "uart3_fck",
1284 .prcm = {
1285 .omap2 = {
1286 .module_offs = OMAP3430_PER_MOD,
1287 .prcm_reg_id = 1,
1288 .module_bit = OMAP3430_EN_UART3_SHIFT,
1289 .idlest_reg_id = 1,
1290 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
1291 },
1292 },
1293 .slaves = omap3xxx_uart3_slaves,
1294 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
1295 .class = &omap2_uart_class,
1296 };
1297
1298 /* UART4 */
1299
1300 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1301 { .irq = INT_36XX_UART4_IRQ, },
1302 { .irq = -1 }
1303 };
1304
1305 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1306 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
1307 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
1308 { .dma_req = -1 }
1309 };
1310
1311 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
1312 &omap3_l4_per__uart4,
1313 };
1314
1315 static struct omap_hwmod omap3xxx_uart4_hwmod = {
1316 .name = "uart4",
1317 .mpu_irqs = uart4_mpu_irqs,
1318 .sdma_reqs = uart4_sdma_reqs,
1319 .main_clk = "uart4_fck",
1320 .prcm = {
1321 .omap2 = {
1322 .module_offs = OMAP3430_PER_MOD,
1323 .prcm_reg_id = 1,
1324 .module_bit = OMAP3630_EN_UART4_SHIFT,
1325 .idlest_reg_id = 1,
1326 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
1327 },
1328 },
1329 .slaves = omap3xxx_uart4_slaves,
1330 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
1331 .class = &omap2_uart_class,
1332 };
1333
1334 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
1335 { .irq = INT_35XX_UART4_IRQ, },
1336 };
1337
1338 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
1339 { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
1340 { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
1341 };
1342
1343 static struct omap_hwmod_ocp_if *am35xx_uart4_slaves[] = {
1344 &am35xx_l4_core__uart4,
1345 };
1346
1347 static struct omap_hwmod am35xx_uart4_hwmod = {
1348 .name = "uart4",
1349 .mpu_irqs = am35xx_uart4_mpu_irqs,
1350 .sdma_reqs = am35xx_uart4_sdma_reqs,
1351 .main_clk = "uart4_fck",
1352 .prcm = {
1353 .omap2 = {
1354 .module_offs = CORE_MOD,
1355 .prcm_reg_id = 1,
1356 .module_bit = OMAP3430_EN_UART4_SHIFT,
1357 .idlest_reg_id = 1,
1358 .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT,
1359 },
1360 },
1361 .slaves = am35xx_uart4_slaves,
1362 .slaves_cnt = ARRAY_SIZE(am35xx_uart4_slaves),
1363 .class = &omap2_uart_class,
1364 };
1365
1366
1367 static struct omap_hwmod_class i2c_class = {
1368 .name = "i2c",
1369 .sysc = &i2c_sysc,
1370 .rev = OMAP_I2C_IP_VERSION_1,
1371 .reset = &omap_i2c_reset,
1372 };
1373
1374 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1375 { .name = "dispc", .dma_req = 5 },
1376 { .name = "dsi1", .dma_req = 74 },
1377 { .dma_req = -1 }
1378 };
1379
1380 /* dss */
1381 /* dss master ports */
1382 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1383 &omap3xxx_dss__l3,
1384 };
1385
1386 /* l4_core -> dss */
1387 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1388 .master = &omap3xxx_l4_core_hwmod,
1389 .slave = &omap3430es1_dss_core_hwmod,
1390 .clk = "dss_ick",
1391 .addr = omap2_dss_addrs,
1392 .fw = {
1393 .omap2 = {
1394 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1395 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1396 .flags = OMAP_FIREWALL_L4,
1397 }
1398 },
1399 .user = OCP_USER_MPU | OCP_USER_SDMA,
1400 };
1401
1402 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1403 .master = &omap3xxx_l4_core_hwmod,
1404 .slave = &omap3xxx_dss_core_hwmod,
1405 .clk = "dss_ick",
1406 .addr = omap2_dss_addrs,
1407 .fw = {
1408 .omap2 = {
1409 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1410 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1411 .flags = OMAP_FIREWALL_L4,
1412 }
1413 },
1414 .user = OCP_USER_MPU | OCP_USER_SDMA,
1415 };
1416
1417 /* dss slave ports */
1418 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
1419 &omap3430es1_l4_core__dss,
1420 };
1421
1422 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1423 &omap3xxx_l4_core__dss,
1424 };
1425
1426 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1427 /*
1428 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
1429 * driver does not use these clocks.
1430 */
1431 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1432 { .role = "tv_clk", .clk = "dss_tv_fck" },
1433 /* required only on OMAP3430 */
1434 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
1435 };
1436
1437 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1438 .name = "dss_core",
1439 .class = &omap2_dss_hwmod_class,
1440 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1441 .sdma_reqs = omap3xxx_dss_sdma_chs,
1442 .prcm = {
1443 .omap2 = {
1444 .prcm_reg_id = 1,
1445 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1446 .module_offs = OMAP3430_DSS_MOD,
1447 .idlest_reg_id = 1,
1448 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
1449 },
1450 },
1451 .opt_clks = dss_opt_clks,
1452 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1453 .slaves = omap3430es1_dss_slaves,
1454 .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves),
1455 .masters = omap3xxx_dss_masters,
1456 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1457 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1458 };
1459
1460 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1461 .name = "dss_core",
1462 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1463 .class = &omap2_dss_hwmod_class,
1464 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1465 .sdma_reqs = omap3xxx_dss_sdma_chs,
1466 .prcm = {
1467 .omap2 = {
1468 .prcm_reg_id = 1,
1469 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1470 .module_offs = OMAP3430_DSS_MOD,
1471 .idlest_reg_id = 1,
1472 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
1473 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
1474 },
1475 },
1476 .opt_clks = dss_opt_clks,
1477 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1478 .slaves = omap3xxx_dss_slaves,
1479 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves),
1480 .masters = omap3xxx_dss_masters,
1481 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1482 };
1483
1484 /*
1485 * 'dispc' class
1486 * display controller
1487 */
1488
1489 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
1490 .rev_offs = 0x0000,
1491 .sysc_offs = 0x0010,
1492 .syss_offs = 0x0014,
1493 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
1494 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1495 SYSC_HAS_ENAWAKEUP),
1496 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1497 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1498 .sysc_fields = &omap_hwmod_sysc_type1,
1499 };
1500
1501 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
1502 .name = "dispc",
1503 .sysc = &omap3_dispc_sysc,
1504 };
1505
1506 /* l4_core -> dss_dispc */
1507 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1508 .master = &omap3xxx_l4_core_hwmod,
1509 .slave = &omap3xxx_dss_dispc_hwmod,
1510 .clk = "dss_ick",
1511 .addr = omap2_dss_dispc_addrs,
1512 .fw = {
1513 .omap2 = {
1514 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1515 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1516 .flags = OMAP_FIREWALL_L4,
1517 }
1518 },
1519 .user = OCP_USER_MPU | OCP_USER_SDMA,
1520 };
1521
1522 /* dss_dispc slave ports */
1523 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1524 &omap3xxx_l4_core__dss_dispc,
1525 };
1526
1527 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1528 .name = "dss_dispc",
1529 .class = &omap3_dispc_hwmod_class,
1530 .mpu_irqs = omap2_dispc_irqs,
1531 .main_clk = "dss1_alwon_fck",
1532 .prcm = {
1533 .omap2 = {
1534 .prcm_reg_id = 1,
1535 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1536 .module_offs = OMAP3430_DSS_MOD,
1537 },
1538 },
1539 .slaves = omap3xxx_dss_dispc_slaves,
1540 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1541 .flags = HWMOD_NO_IDLEST,
1542 .dev_attr = &omap2_3_dss_dispc_dev_attr
1543 };
1544
1545 /*
1546 * 'dsi' class
1547 * display serial interface controller
1548 */
1549
1550 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1551 .name = "dsi",
1552 };
1553
1554 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
1555 { .irq = 25 },
1556 { .irq = -1 }
1557 };
1558
1559 /* dss_dsi1 */
1560 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1561 {
1562 .pa_start = 0x4804FC00,
1563 .pa_end = 0x4804FFFF,
1564 .flags = ADDR_TYPE_RT
1565 },
1566 { }
1567 };
1568
1569 /* l4_core -> dss_dsi1 */
1570 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1571 .master = &omap3xxx_l4_core_hwmod,
1572 .slave = &omap3xxx_dss_dsi1_hwmod,
1573 .clk = "dss_ick",
1574 .addr = omap3xxx_dss_dsi1_addrs,
1575 .fw = {
1576 .omap2 = {
1577 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1578 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1579 .flags = OMAP_FIREWALL_L4,
1580 }
1581 },
1582 .user = OCP_USER_MPU | OCP_USER_SDMA,
1583 };
1584
1585 /* dss_dsi1 slave ports */
1586 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1587 &omap3xxx_l4_core__dss_dsi1,
1588 };
1589
1590 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1591 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1592 };
1593
1594 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1595 .name = "dss_dsi1",
1596 .class = &omap3xxx_dsi_hwmod_class,
1597 .mpu_irqs = omap3xxx_dsi1_irqs,
1598 .main_clk = "dss1_alwon_fck",
1599 .prcm = {
1600 .omap2 = {
1601 .prcm_reg_id = 1,
1602 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1603 .module_offs = OMAP3430_DSS_MOD,
1604 },
1605 },
1606 .opt_clks = dss_dsi1_opt_clks,
1607 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
1608 .slaves = omap3xxx_dss_dsi1_slaves,
1609 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1610 .flags = HWMOD_NO_IDLEST,
1611 };
1612
1613 /* l4_core -> dss_rfbi */
1614 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1615 .master = &omap3xxx_l4_core_hwmod,
1616 .slave = &omap3xxx_dss_rfbi_hwmod,
1617 .clk = "dss_ick",
1618 .addr = omap2_dss_rfbi_addrs,
1619 .fw = {
1620 .omap2 = {
1621 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1622 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1623 .flags = OMAP_FIREWALL_L4,
1624 }
1625 },
1626 .user = OCP_USER_MPU | OCP_USER_SDMA,
1627 };
1628
1629 /* dss_rfbi slave ports */
1630 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1631 &omap3xxx_l4_core__dss_rfbi,
1632 };
1633
1634 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1635 { .role = "ick", .clk = "dss_ick" },
1636 };
1637
1638 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1639 .name = "dss_rfbi",
1640 .class = &omap2_rfbi_hwmod_class,
1641 .main_clk = "dss1_alwon_fck",
1642 .prcm = {
1643 .omap2 = {
1644 .prcm_reg_id = 1,
1645 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1646 .module_offs = OMAP3430_DSS_MOD,
1647 },
1648 },
1649 .opt_clks = dss_rfbi_opt_clks,
1650 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
1651 .slaves = omap3xxx_dss_rfbi_slaves,
1652 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1653 .flags = HWMOD_NO_IDLEST,
1654 };
1655
1656 /* l4_core -> dss_venc */
1657 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1658 .master = &omap3xxx_l4_core_hwmod,
1659 .slave = &omap3xxx_dss_venc_hwmod,
1660 .clk = "dss_ick",
1661 .addr = omap2_dss_venc_addrs,
1662 .fw = {
1663 .omap2 = {
1664 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1665 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1666 .flags = OMAP_FIREWALL_L4,
1667 }
1668 },
1669 .flags = OCPIF_SWSUP_IDLE,
1670 .user = OCP_USER_MPU | OCP_USER_SDMA,
1671 };
1672
1673 /* dss_venc slave ports */
1674 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1675 &omap3xxx_l4_core__dss_venc,
1676 };
1677
1678 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
1679 /* required only on OMAP3430 */
1680 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
1681 };
1682
1683 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1684 .name = "dss_venc",
1685 .class = &omap2_venc_hwmod_class,
1686 .main_clk = "dss_tv_fck",
1687 .prcm = {
1688 .omap2 = {
1689 .prcm_reg_id = 1,
1690 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1691 .module_offs = OMAP3430_DSS_MOD,
1692 },
1693 },
1694 .opt_clks = dss_venc_opt_clks,
1695 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
1696 .slaves = omap3xxx_dss_venc_slaves,
1697 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1698 .flags = HWMOD_NO_IDLEST,
1699 };
1700
1701 /* I2C1 */
1702
1703 static struct omap_i2c_dev_attr i2c1_dev_attr = {
1704 .fifo_depth = 8, /* bytes */
1705 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1706 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1707 OMAP_I2C_FLAG_BUS_SHIFT_2,
1708 };
1709
1710 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1711 &omap3_l4_core__i2c1,
1712 };
1713
1714 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1715 .name = "i2c1",
1716 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1717 .mpu_irqs = omap2_i2c1_mpu_irqs,
1718 .sdma_reqs = omap2_i2c1_sdma_reqs,
1719 .main_clk = "i2c1_fck",
1720 .prcm = {
1721 .omap2 = {
1722 .module_offs = CORE_MOD,
1723 .prcm_reg_id = 1,
1724 .module_bit = OMAP3430_EN_I2C1_SHIFT,
1725 .idlest_reg_id = 1,
1726 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1727 },
1728 },
1729 .slaves = omap3xxx_i2c1_slaves,
1730 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1731 .class = &i2c_class,
1732 .dev_attr = &i2c1_dev_attr,
1733 };
1734
1735 /* I2C2 */
1736
1737 static struct omap_i2c_dev_attr i2c2_dev_attr = {
1738 .fifo_depth = 8, /* bytes */
1739 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1740 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1741 OMAP_I2C_FLAG_BUS_SHIFT_2,
1742 };
1743
1744 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1745 &omap3_l4_core__i2c2,
1746 };
1747
1748 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1749 .name = "i2c2",
1750 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1751 .mpu_irqs = omap2_i2c2_mpu_irqs,
1752 .sdma_reqs = omap2_i2c2_sdma_reqs,
1753 .main_clk = "i2c2_fck",
1754 .prcm = {
1755 .omap2 = {
1756 .module_offs = CORE_MOD,
1757 .prcm_reg_id = 1,
1758 .module_bit = OMAP3430_EN_I2C2_SHIFT,
1759 .idlest_reg_id = 1,
1760 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1761 },
1762 },
1763 .slaves = omap3xxx_i2c2_slaves,
1764 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1765 .class = &i2c_class,
1766 .dev_attr = &i2c2_dev_attr,
1767 };
1768
1769 /* I2C3 */
1770
1771 static struct omap_i2c_dev_attr i2c3_dev_attr = {
1772 .fifo_depth = 64, /* bytes */
1773 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1774 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1775 OMAP_I2C_FLAG_BUS_SHIFT_2,
1776 };
1777
1778 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1779 { .irq = INT_34XX_I2C3_IRQ, },
1780 { .irq = -1 }
1781 };
1782
1783 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1784 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1785 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1786 { .dma_req = -1 }
1787 };
1788
1789 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1790 &omap3_l4_core__i2c3,
1791 };
1792
1793 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1794 .name = "i2c3",
1795 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1796 .mpu_irqs = i2c3_mpu_irqs,
1797 .sdma_reqs = i2c3_sdma_reqs,
1798 .main_clk = "i2c3_fck",
1799 .prcm = {
1800 .omap2 = {
1801 .module_offs = CORE_MOD,
1802 .prcm_reg_id = 1,
1803 .module_bit = OMAP3430_EN_I2C3_SHIFT,
1804 .idlest_reg_id = 1,
1805 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1806 },
1807 },
1808 .slaves = omap3xxx_i2c3_slaves,
1809 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1810 .class = &i2c_class,
1811 .dev_attr = &i2c3_dev_attr,
1812 };
1813
1814 /* l4_wkup -> gpio1 */
1815 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
1816 {
1817 .pa_start = 0x48310000,
1818 .pa_end = 0x483101ff,
1819 .flags = ADDR_TYPE_RT
1820 },
1821 { }
1822 };
1823
1824 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
1825 .master = &omap3xxx_l4_wkup_hwmod,
1826 .slave = &omap3xxx_gpio1_hwmod,
1827 .addr = omap3xxx_gpio1_addrs,
1828 .user = OCP_USER_MPU | OCP_USER_SDMA,
1829 };
1830
1831 /* l4_per -> gpio2 */
1832 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
1833 {
1834 .pa_start = 0x49050000,
1835 .pa_end = 0x490501ff,
1836 .flags = ADDR_TYPE_RT
1837 },
1838 { }
1839 };
1840
1841 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
1842 .master = &omap3xxx_l4_per_hwmod,
1843 .slave = &omap3xxx_gpio2_hwmod,
1844 .addr = omap3xxx_gpio2_addrs,
1845 .user = OCP_USER_MPU | OCP_USER_SDMA,
1846 };
1847
1848 /* l4_per -> gpio3 */
1849 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
1850 {
1851 .pa_start = 0x49052000,
1852 .pa_end = 0x490521ff,
1853 .flags = ADDR_TYPE_RT
1854 },
1855 { }
1856 };
1857
1858 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
1859 .master = &omap3xxx_l4_per_hwmod,
1860 .slave = &omap3xxx_gpio3_hwmod,
1861 .addr = omap3xxx_gpio3_addrs,
1862 .user = OCP_USER_MPU | OCP_USER_SDMA,
1863 };
1864
1865 /* l4_per -> gpio4 */
1866 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
1867 {
1868 .pa_start = 0x49054000,
1869 .pa_end = 0x490541ff,
1870 .flags = ADDR_TYPE_RT
1871 },
1872 { }
1873 };
1874
1875 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
1876 .master = &omap3xxx_l4_per_hwmod,
1877 .slave = &omap3xxx_gpio4_hwmod,
1878 .addr = omap3xxx_gpio4_addrs,
1879 .user = OCP_USER_MPU | OCP_USER_SDMA,
1880 };
1881
1882 /* l4_per -> gpio5 */
1883 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
1884 {
1885 .pa_start = 0x49056000,
1886 .pa_end = 0x490561ff,
1887 .flags = ADDR_TYPE_RT
1888 },
1889 { }
1890 };
1891
1892 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
1893 .master = &omap3xxx_l4_per_hwmod,
1894 .slave = &omap3xxx_gpio5_hwmod,
1895 .addr = omap3xxx_gpio5_addrs,
1896 .user = OCP_USER_MPU | OCP_USER_SDMA,
1897 };
1898
1899 /* l4_per -> gpio6 */
1900 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
1901 {
1902 .pa_start = 0x49058000,
1903 .pa_end = 0x490581ff,
1904 .flags = ADDR_TYPE_RT
1905 },
1906 { }
1907 };
1908
1909 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
1910 .master = &omap3xxx_l4_per_hwmod,
1911 .slave = &omap3xxx_gpio6_hwmod,
1912 .addr = omap3xxx_gpio6_addrs,
1913 .user = OCP_USER_MPU | OCP_USER_SDMA,
1914 };
1915
1916 /*
1917 * 'gpio' class
1918 * general purpose io module
1919 */
1920
1921 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
1922 .rev_offs = 0x0000,
1923 .sysc_offs = 0x0010,
1924 .syss_offs = 0x0014,
1925 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1926 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1927 SYSS_HAS_RESET_STATUS),
1928 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1929 .sysc_fields = &omap_hwmod_sysc_type1,
1930 };
1931
1932 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
1933 .name = "gpio",
1934 .sysc = &omap3xxx_gpio_sysc,
1935 .rev = 1,
1936 };
1937
1938 /* gpio_dev_attr*/
1939 static struct omap_gpio_dev_attr gpio_dev_attr = {
1940 .bank_width = 32,
1941 .dbck_flag = true,
1942 };
1943
1944 /* gpio1 */
1945 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1946 { .role = "dbclk", .clk = "gpio1_dbck", },
1947 };
1948
1949 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
1950 &omap3xxx_l4_wkup__gpio1,
1951 };
1952
1953 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
1954 .name = "gpio1",
1955 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1956 .mpu_irqs = omap2_gpio1_irqs,
1957 .main_clk = "gpio1_ick",
1958 .opt_clks = gpio1_opt_clks,
1959 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1960 .prcm = {
1961 .omap2 = {
1962 .prcm_reg_id = 1,
1963 .module_bit = OMAP3430_EN_GPIO1_SHIFT,
1964 .module_offs = WKUP_MOD,
1965 .idlest_reg_id = 1,
1966 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
1967 },
1968 },
1969 .slaves = omap3xxx_gpio1_slaves,
1970 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves),
1971 .class = &omap3xxx_gpio_hwmod_class,
1972 .dev_attr = &gpio_dev_attr,
1973 };
1974
1975 /* gpio2 */
1976 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1977 { .role = "dbclk", .clk = "gpio2_dbck", },
1978 };
1979
1980 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
1981 &omap3xxx_l4_per__gpio2,
1982 };
1983
1984 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
1985 .name = "gpio2",
1986 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1987 .mpu_irqs = omap2_gpio2_irqs,
1988 .main_clk = "gpio2_ick",
1989 .opt_clks = gpio2_opt_clks,
1990 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1991 .prcm = {
1992 .omap2 = {
1993 .prcm_reg_id = 1,
1994 .module_bit = OMAP3430_EN_GPIO2_SHIFT,
1995 .module_offs = OMAP3430_PER_MOD,
1996 .idlest_reg_id = 1,
1997 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
1998 },
1999 },
2000 .slaves = omap3xxx_gpio2_slaves,
2001 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves),
2002 .class = &omap3xxx_gpio_hwmod_class,
2003 .dev_attr = &gpio_dev_attr,
2004 };
2005
2006 /* gpio3 */
2007 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
2008 { .role = "dbclk", .clk = "gpio3_dbck", },
2009 };
2010
2011 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
2012 &omap3xxx_l4_per__gpio3,
2013 };
2014
2015 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
2016 .name = "gpio3",
2017 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2018 .mpu_irqs = omap2_gpio3_irqs,
2019 .main_clk = "gpio3_ick",
2020 .opt_clks = gpio3_opt_clks,
2021 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
2022 .prcm = {
2023 .omap2 = {
2024 .prcm_reg_id = 1,
2025 .module_bit = OMAP3430_EN_GPIO3_SHIFT,
2026 .module_offs = OMAP3430_PER_MOD,
2027 .idlest_reg_id = 1,
2028 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
2029 },
2030 },
2031 .slaves = omap3xxx_gpio3_slaves,
2032 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves),
2033 .class = &omap3xxx_gpio_hwmod_class,
2034 .dev_attr = &gpio_dev_attr,
2035 };
2036
2037 /* gpio4 */
2038 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2039 { .role = "dbclk", .clk = "gpio4_dbck", },
2040 };
2041
2042 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
2043 &omap3xxx_l4_per__gpio4,
2044 };
2045
2046 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
2047 .name = "gpio4",
2048 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2049 .mpu_irqs = omap2_gpio4_irqs,
2050 .main_clk = "gpio4_ick",
2051 .opt_clks = gpio4_opt_clks,
2052 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
2053 .prcm = {
2054 .omap2 = {
2055 .prcm_reg_id = 1,
2056 .module_bit = OMAP3430_EN_GPIO4_SHIFT,
2057 .module_offs = OMAP3430_PER_MOD,
2058 .idlest_reg_id = 1,
2059 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
2060 },
2061 },
2062 .slaves = omap3xxx_gpio4_slaves,
2063 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves),
2064 .class = &omap3xxx_gpio_hwmod_class,
2065 .dev_attr = &gpio_dev_attr,
2066 };
2067
2068 /* gpio5 */
2069 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
2070 { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
2071 { .irq = -1 }
2072 };
2073
2074 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2075 { .role = "dbclk", .clk = "gpio5_dbck", },
2076 };
2077
2078 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
2079 &omap3xxx_l4_per__gpio5,
2080 };
2081
2082 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2083 .name = "gpio5",
2084 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2085 .mpu_irqs = omap3xxx_gpio5_irqs,
2086 .main_clk = "gpio5_ick",
2087 .opt_clks = gpio5_opt_clks,
2088 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
2089 .prcm = {
2090 .omap2 = {
2091 .prcm_reg_id = 1,
2092 .module_bit = OMAP3430_EN_GPIO5_SHIFT,
2093 .module_offs = OMAP3430_PER_MOD,
2094 .idlest_reg_id = 1,
2095 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
2096 },
2097 },
2098 .slaves = omap3xxx_gpio5_slaves,
2099 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves),
2100 .class = &omap3xxx_gpio_hwmod_class,
2101 .dev_attr = &gpio_dev_attr,
2102 };
2103
2104 /* gpio6 */
2105 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
2106 { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
2107 { .irq = -1 }
2108 };
2109
2110 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2111 { .role = "dbclk", .clk = "gpio6_dbck", },
2112 };
2113
2114 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
2115 &omap3xxx_l4_per__gpio6,
2116 };
2117
2118 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2119 .name = "gpio6",
2120 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2121 .mpu_irqs = omap3xxx_gpio6_irqs,
2122 .main_clk = "gpio6_ick",
2123 .opt_clks = gpio6_opt_clks,
2124 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
2125 .prcm = {
2126 .omap2 = {
2127 .prcm_reg_id = 1,
2128 .module_bit = OMAP3430_EN_GPIO6_SHIFT,
2129 .module_offs = OMAP3430_PER_MOD,
2130 .idlest_reg_id = 1,
2131 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
2132 },
2133 },
2134 .slaves = omap3xxx_gpio6_slaves,
2135 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves),
2136 .class = &omap3xxx_gpio_hwmod_class,
2137 .dev_attr = &gpio_dev_attr,
2138 };
2139
2140 /* dma_system -> L3 */
2141 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2142 .master = &omap3xxx_dma_system_hwmod,
2143 .slave = &omap3xxx_l3_main_hwmod,
2144 .clk = "core_l3_ick",
2145 .user = OCP_USER_MPU | OCP_USER_SDMA,
2146 };
2147
2148 /* dma attributes */
2149 static struct omap_dma_dev_attr dma_dev_attr = {
2150 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
2151 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
2152 .lch_count = 32,
2153 };
2154
2155 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
2156 .rev_offs = 0x0000,
2157 .sysc_offs = 0x002c,
2158 .syss_offs = 0x0028,
2159 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2160 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
2161 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
2162 SYSS_HAS_RESET_STATUS),
2163 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2164 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2165 .sysc_fields = &omap_hwmod_sysc_type1,
2166 };
2167
2168 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2169 .name = "dma",
2170 .sysc = &omap3xxx_dma_sysc,
2171 };
2172
2173 /* dma_system */
2174 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2175 {
2176 .pa_start = 0x48056000,
2177 .pa_end = 0x48056fff,
2178 .flags = ADDR_TYPE_RT
2179 },
2180 { }
2181 };
2182
2183 /* dma_system master ports */
2184 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
2185 &omap3xxx_dma_system__l3,
2186 };
2187
2188 /* l4_cfg -> dma_system */
2189 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2190 .master = &omap3xxx_l4_core_hwmod,
2191 .slave = &omap3xxx_dma_system_hwmod,
2192 .clk = "core_l4_ick",
2193 .addr = omap3xxx_dma_system_addrs,
2194 .user = OCP_USER_MPU | OCP_USER_SDMA,
2195 };
2196
2197 /* dma_system slave ports */
2198 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2199 &omap3xxx_l4_core__dma_system,
2200 };
2201
2202 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2203 .name = "dma",
2204 .class = &omap3xxx_dma_hwmod_class,
2205 .mpu_irqs = omap2_dma_system_irqs,
2206 .main_clk = "core_l3_ick",
2207 .prcm = {
2208 .omap2 = {
2209 .module_offs = CORE_MOD,
2210 .prcm_reg_id = 1,
2211 .module_bit = OMAP3430_ST_SDMA_SHIFT,
2212 .idlest_reg_id = 1,
2213 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
2214 },
2215 },
2216 .slaves = omap3xxx_dma_system_slaves,
2217 .slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves),
2218 .masters = omap3xxx_dma_system_masters,
2219 .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters),
2220 .dev_attr = &dma_dev_attr,
2221 .flags = HWMOD_NO_IDLEST,
2222 };
2223
2224 /*
2225 * 'mcbsp' class
2226 * multi channel buffered serial port controller
2227 */
2228
2229 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
2230 .sysc_offs = 0x008c,
2231 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2232 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2233 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2234 .sysc_fields = &omap_hwmod_sysc_type1,
2235 .clockact = 0x2,
2236 };
2237
2238 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
2239 .name = "mcbsp",
2240 .sysc = &omap3xxx_mcbsp_sysc,
2241 .rev = MCBSP_CONFIG_TYPE3,
2242 };
2243
2244 /* mcbsp1 */
2245 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2246 { .name = "irq", .irq = 16 },
2247 { .name = "tx", .irq = 59 },
2248 { .name = "rx", .irq = 60 },
2249 { .irq = -1 }
2250 };
2251
2252 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2253 {
2254 .name = "mpu",
2255 .pa_start = 0x48074000,
2256 .pa_end = 0x480740ff,
2257 .flags = ADDR_TYPE_RT
2258 },
2259 { }
2260 };
2261
2262 /* l4_core -> mcbsp1 */
2263 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2264 .master = &omap3xxx_l4_core_hwmod,
2265 .slave = &omap3xxx_mcbsp1_hwmod,
2266 .clk = "mcbsp1_ick",
2267 .addr = omap3xxx_mcbsp1_addrs,
2268 .user = OCP_USER_MPU | OCP_USER_SDMA,
2269 };
2270
2271 /* mcbsp1 slave ports */
2272 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2273 &omap3xxx_l4_core__mcbsp1,
2274 };
2275
2276 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2277 .name = "mcbsp1",
2278 .class = &omap3xxx_mcbsp_hwmod_class,
2279 .mpu_irqs = omap3xxx_mcbsp1_irqs,
2280 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
2281 .main_clk = "mcbsp1_fck",
2282 .prcm = {
2283 .omap2 = {
2284 .prcm_reg_id = 1,
2285 .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
2286 .module_offs = CORE_MOD,
2287 .idlest_reg_id = 1,
2288 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2289 },
2290 },
2291 .slaves = omap3xxx_mcbsp1_slaves,
2292 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2293 };
2294
2295 /* mcbsp2 */
2296 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2297 { .name = "irq", .irq = 17 },
2298 { .name = "tx", .irq = 62 },
2299 { .name = "rx", .irq = 63 },
2300 { .irq = -1 }
2301 };
2302
2303 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2304 {
2305 .name = "mpu",
2306 .pa_start = 0x49022000,
2307 .pa_end = 0x490220ff,
2308 .flags = ADDR_TYPE_RT
2309 },
2310 { }
2311 };
2312
2313 /* l4_per -> mcbsp2 */
2314 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2315 .master = &omap3xxx_l4_per_hwmod,
2316 .slave = &omap3xxx_mcbsp2_hwmod,
2317 .clk = "mcbsp2_ick",
2318 .addr = omap3xxx_mcbsp2_addrs,
2319 .user = OCP_USER_MPU | OCP_USER_SDMA,
2320 };
2321
2322 /* mcbsp2 slave ports */
2323 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2324 &omap3xxx_l4_per__mcbsp2,
2325 };
2326
2327 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2328 .sidetone = "mcbsp2_sidetone",
2329 };
2330
2331 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2332 .name = "mcbsp2",
2333 .class = &omap3xxx_mcbsp_hwmod_class,
2334 .mpu_irqs = omap3xxx_mcbsp2_irqs,
2335 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
2336 .main_clk = "mcbsp2_fck",
2337 .prcm = {
2338 .omap2 = {
2339 .prcm_reg_id = 1,
2340 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2341 .module_offs = OMAP3430_PER_MOD,
2342 .idlest_reg_id = 1,
2343 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2344 },
2345 },
2346 .slaves = omap3xxx_mcbsp2_slaves,
2347 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2348 .dev_attr = &omap34xx_mcbsp2_dev_attr,
2349 };
2350
2351 /* mcbsp3 */
2352 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2353 { .name = "irq", .irq = 22 },
2354 { .name = "tx", .irq = 89 },
2355 { .name = "rx", .irq = 90 },
2356 { .irq = -1 }
2357 };
2358
2359 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2360 {
2361 .name = "mpu",
2362 .pa_start = 0x49024000,
2363 .pa_end = 0x490240ff,
2364 .flags = ADDR_TYPE_RT
2365 },
2366 { }
2367 };
2368
2369 /* l4_per -> mcbsp3 */
2370 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2371 .master = &omap3xxx_l4_per_hwmod,
2372 .slave = &omap3xxx_mcbsp3_hwmod,
2373 .clk = "mcbsp3_ick",
2374 .addr = omap3xxx_mcbsp3_addrs,
2375 .user = OCP_USER_MPU | OCP_USER_SDMA,
2376 };
2377
2378 /* mcbsp3 slave ports */
2379 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2380 &omap3xxx_l4_per__mcbsp3,
2381 };
2382
2383 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2384 .sidetone = "mcbsp3_sidetone",
2385 };
2386
2387 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2388 .name = "mcbsp3",
2389 .class = &omap3xxx_mcbsp_hwmod_class,
2390 .mpu_irqs = omap3xxx_mcbsp3_irqs,
2391 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
2392 .main_clk = "mcbsp3_fck",
2393 .prcm = {
2394 .omap2 = {
2395 .prcm_reg_id = 1,
2396 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2397 .module_offs = OMAP3430_PER_MOD,
2398 .idlest_reg_id = 1,
2399 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2400 },
2401 },
2402 .slaves = omap3xxx_mcbsp3_slaves,
2403 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2404 .dev_attr = &omap34xx_mcbsp3_dev_attr,
2405 };
2406
2407 /* mcbsp4 */
2408 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2409 { .name = "irq", .irq = 23 },
2410 { .name = "tx", .irq = 54 },
2411 { .name = "rx", .irq = 55 },
2412 { .irq = -1 }
2413 };
2414
2415 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2416 { .name = "rx", .dma_req = 20 },
2417 { .name = "tx", .dma_req = 19 },
2418 { .dma_req = -1 }
2419 };
2420
2421 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2422 {
2423 .name = "mpu",
2424 .pa_start = 0x49026000,
2425 .pa_end = 0x490260ff,
2426 .flags = ADDR_TYPE_RT
2427 },
2428 { }
2429 };
2430
2431 /* l4_per -> mcbsp4 */
2432 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2433 .master = &omap3xxx_l4_per_hwmod,
2434 .slave = &omap3xxx_mcbsp4_hwmod,
2435 .clk = "mcbsp4_ick",
2436 .addr = omap3xxx_mcbsp4_addrs,
2437 .user = OCP_USER_MPU | OCP_USER_SDMA,
2438 };
2439
2440 /* mcbsp4 slave ports */
2441 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2442 &omap3xxx_l4_per__mcbsp4,
2443 };
2444
2445 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2446 .name = "mcbsp4",
2447 .class = &omap3xxx_mcbsp_hwmod_class,
2448 .mpu_irqs = omap3xxx_mcbsp4_irqs,
2449 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
2450 .main_clk = "mcbsp4_fck",
2451 .prcm = {
2452 .omap2 = {
2453 .prcm_reg_id = 1,
2454 .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
2455 .module_offs = OMAP3430_PER_MOD,
2456 .idlest_reg_id = 1,
2457 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2458 },
2459 },
2460 .slaves = omap3xxx_mcbsp4_slaves,
2461 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2462 };
2463
2464 /* mcbsp5 */
2465 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2466 { .name = "irq", .irq = 27 },
2467 { .name = "tx", .irq = 81 },
2468 { .name = "rx", .irq = 82 },
2469 { .irq = -1 }
2470 };
2471
2472 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2473 { .name = "rx", .dma_req = 22 },
2474 { .name = "tx", .dma_req = 21 },
2475 { .dma_req = -1 }
2476 };
2477
2478 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2479 {
2480 .name = "mpu",
2481 .pa_start = 0x48096000,
2482 .pa_end = 0x480960ff,
2483 .flags = ADDR_TYPE_RT
2484 },
2485 { }
2486 };
2487
2488 /* l4_core -> mcbsp5 */
2489 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2490 .master = &omap3xxx_l4_core_hwmod,
2491 .slave = &omap3xxx_mcbsp5_hwmod,
2492 .clk = "mcbsp5_ick",
2493 .addr = omap3xxx_mcbsp5_addrs,
2494 .user = OCP_USER_MPU | OCP_USER_SDMA,
2495 };
2496
2497 /* mcbsp5 slave ports */
2498 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2499 &omap3xxx_l4_core__mcbsp5,
2500 };
2501
2502 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2503 .name = "mcbsp5",
2504 .class = &omap3xxx_mcbsp_hwmod_class,
2505 .mpu_irqs = omap3xxx_mcbsp5_irqs,
2506 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
2507 .main_clk = "mcbsp5_fck",
2508 .prcm = {
2509 .omap2 = {
2510 .prcm_reg_id = 1,
2511 .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
2512 .module_offs = CORE_MOD,
2513 .idlest_reg_id = 1,
2514 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2515 },
2516 },
2517 .slaves = omap3xxx_mcbsp5_slaves,
2518 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2519 };
2520 /* 'mcbsp sidetone' class */
2521
2522 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2523 .sysc_offs = 0x0010,
2524 .sysc_flags = SYSC_HAS_AUTOIDLE,
2525 .sysc_fields = &omap_hwmod_sysc_type1,
2526 };
2527
2528 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2529 .name = "mcbsp_sidetone",
2530 .sysc = &omap3xxx_mcbsp_sidetone_sysc,
2531 };
2532
2533 /* mcbsp2_sidetone */
2534 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2535 { .name = "irq", .irq = 4 },
2536 { .irq = -1 }
2537 };
2538
2539 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2540 {
2541 .name = "sidetone",
2542 .pa_start = 0x49028000,
2543 .pa_end = 0x490280ff,
2544 .flags = ADDR_TYPE_RT
2545 },
2546 { }
2547 };
2548
2549 /* l4_per -> mcbsp2_sidetone */
2550 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2551 .master = &omap3xxx_l4_per_hwmod,
2552 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
2553 .clk = "mcbsp2_ick",
2554 .addr = omap3xxx_mcbsp2_sidetone_addrs,
2555 .user = OCP_USER_MPU,
2556 };
2557
2558 /* mcbsp2_sidetone slave ports */
2559 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2560 &omap3xxx_l4_per__mcbsp2_sidetone,
2561 };
2562
2563 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2564 .name = "mcbsp2_sidetone",
2565 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2566 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
2567 .main_clk = "mcbsp2_fck",
2568 .prcm = {
2569 .omap2 = {
2570 .prcm_reg_id = 1,
2571 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2572 .module_offs = OMAP3430_PER_MOD,
2573 .idlest_reg_id = 1,
2574 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2575 },
2576 },
2577 .slaves = omap3xxx_mcbsp2_sidetone_slaves,
2578 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2579 };
2580
2581 /* mcbsp3_sidetone */
2582 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2583 { .name = "irq", .irq = 5 },
2584 { .irq = -1 }
2585 };
2586
2587 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2588 {
2589 .name = "sidetone",
2590 .pa_start = 0x4902A000,
2591 .pa_end = 0x4902A0ff,
2592 .flags = ADDR_TYPE_RT
2593 },
2594 { }
2595 };
2596
2597 /* l4_per -> mcbsp3_sidetone */
2598 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2599 .master = &omap3xxx_l4_per_hwmod,
2600 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
2601 .clk = "mcbsp3_ick",
2602 .addr = omap3xxx_mcbsp3_sidetone_addrs,
2603 .user = OCP_USER_MPU,
2604 };
2605
2606 /* mcbsp3_sidetone slave ports */
2607 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2608 &omap3xxx_l4_per__mcbsp3_sidetone,
2609 };
2610
2611 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2612 .name = "mcbsp3_sidetone",
2613 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2614 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
2615 .main_clk = "mcbsp3_fck",
2616 .prcm = {
2617 .omap2 = {
2618 .prcm_reg_id = 1,
2619 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2620 .module_offs = OMAP3430_PER_MOD,
2621 .idlest_reg_id = 1,
2622 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2623 },
2624 },
2625 .slaves = omap3xxx_mcbsp3_sidetone_slaves,
2626 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2627 };
2628
2629
2630 /* SR common */
2631 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2632 .clkact_shift = 20,
2633 };
2634
2635 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
2636 .sysc_offs = 0x24,
2637 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
2638 .clockact = CLOCKACT_TEST_ICLK,
2639 .sysc_fields = &omap34xx_sr_sysc_fields,
2640 };
2641
2642 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2643 .name = "smartreflex",
2644 .sysc = &omap34xx_sr_sysc,
2645 .rev = 1,
2646 };
2647
2648 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2649 .sidle_shift = 24,
2650 .enwkup_shift = 26
2651 };
2652
2653 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
2654 .sysc_offs = 0x38,
2655 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2656 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2657 SYSC_NO_CACHE),
2658 .sysc_fields = &omap36xx_sr_sysc_fields,
2659 };
2660
2661 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
2662 .name = "smartreflex",
2663 .sysc = &omap36xx_sr_sysc,
2664 .rev = 2,
2665 };
2666
2667 /* SR1 */
2668 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
2669 .sensor_voltdm_name = "mpu_iva",
2670 };
2671
2672 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
2673 &omap3_l4_core__sr1,
2674 };
2675
2676 static struct omap_hwmod omap34xx_sr1_hwmod = {
2677 .name = "sr1_hwmod",
2678 .class = &omap34xx_smartreflex_hwmod_class,
2679 .main_clk = "sr1_fck",
2680 .prcm = {
2681 .omap2 = {
2682 .prcm_reg_id = 1,
2683 .module_bit = OMAP3430_EN_SR1_SHIFT,
2684 .module_offs = WKUP_MOD,
2685 .idlest_reg_id = 1,
2686 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2687 },
2688 },
2689 .slaves = omap3_sr1_slaves,
2690 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
2691 .dev_attr = &sr1_dev_attr,
2692 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2693 };
2694
2695 static struct omap_hwmod omap36xx_sr1_hwmod = {
2696 .name = "sr1_hwmod",
2697 .class = &omap36xx_smartreflex_hwmod_class,
2698 .main_clk = "sr1_fck",
2699 .prcm = {
2700 .omap2 = {
2701 .prcm_reg_id = 1,
2702 .module_bit = OMAP3430_EN_SR1_SHIFT,
2703 .module_offs = WKUP_MOD,
2704 .idlest_reg_id = 1,
2705 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2706 },
2707 },
2708 .slaves = omap3_sr1_slaves,
2709 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
2710 .dev_attr = &sr1_dev_attr,
2711 };
2712
2713 /* SR2 */
2714 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
2715 .sensor_voltdm_name = "core",
2716 };
2717
2718 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
2719 &omap3_l4_core__sr2,
2720 };
2721
2722 static struct omap_hwmod omap34xx_sr2_hwmod = {
2723 .name = "sr2_hwmod",
2724 .class = &omap34xx_smartreflex_hwmod_class,
2725 .main_clk = "sr2_fck",
2726 .prcm = {
2727 .omap2 = {
2728 .prcm_reg_id = 1,
2729 .module_bit = OMAP3430_EN_SR2_SHIFT,
2730 .module_offs = WKUP_MOD,
2731 .idlest_reg_id = 1,
2732 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2733 },
2734 },
2735 .slaves = omap3_sr2_slaves,
2736 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
2737 .dev_attr = &sr2_dev_attr,
2738 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2739 };
2740
2741 static struct omap_hwmod omap36xx_sr2_hwmod = {
2742 .name = "sr2_hwmod",
2743 .class = &omap36xx_smartreflex_hwmod_class,
2744 .main_clk = "sr2_fck",
2745 .prcm = {
2746 .omap2 = {
2747 .prcm_reg_id = 1,
2748 .module_bit = OMAP3430_EN_SR2_SHIFT,
2749 .module_offs = WKUP_MOD,
2750 .idlest_reg_id = 1,
2751 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2752 },
2753 },
2754 .slaves = omap3_sr2_slaves,
2755 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
2756 .dev_attr = &sr2_dev_attr,
2757 };
2758
2759 /*
2760 * 'mailbox' class
2761 * mailbox module allowing communication between the on-chip processors
2762 * using a queued mailbox-interrupt mechanism.
2763 */
2764
2765 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
2766 .rev_offs = 0x000,
2767 .sysc_offs = 0x010,
2768 .syss_offs = 0x014,
2769 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2770 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2771 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2772 .sysc_fields = &omap_hwmod_sysc_type1,
2773 };
2774
2775 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
2776 .name = "mailbox",
2777 .sysc = &omap3xxx_mailbox_sysc,
2778 };
2779
2780 static struct omap_hwmod omap3xxx_mailbox_hwmod;
2781 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
2782 { .irq = 26 },
2783 { .irq = -1 }
2784 };
2785
2786 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2787 {
2788 .pa_start = 0x48094000,
2789 .pa_end = 0x480941ff,
2790 .flags = ADDR_TYPE_RT,
2791 },
2792 { }
2793 };
2794
2795 /* l4_core -> mailbox */
2796 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2797 .master = &omap3xxx_l4_core_hwmod,
2798 .slave = &omap3xxx_mailbox_hwmod,
2799 .addr = omap3xxx_mailbox_addrs,
2800 .user = OCP_USER_MPU | OCP_USER_SDMA,
2801 };
2802
2803 /* mailbox slave ports */
2804 static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
2805 &omap3xxx_l4_core__mailbox,
2806 };
2807
2808 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
2809 .name = "mailbox",
2810 .class = &omap3xxx_mailbox_hwmod_class,
2811 .mpu_irqs = omap3xxx_mailbox_irqs,
2812 .main_clk = "mailboxes_ick",
2813 .prcm = {
2814 .omap2 = {
2815 .prcm_reg_id = 1,
2816 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2817 .module_offs = CORE_MOD,
2818 .idlest_reg_id = 1,
2819 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
2820 },
2821 },
2822 .slaves = omap3xxx_mailbox_slaves,
2823 .slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves),
2824 };
2825
2826 /* l4 core -> mcspi1 interface */
2827 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2828 .master = &omap3xxx_l4_core_hwmod,
2829 .slave = &omap34xx_mcspi1,
2830 .clk = "mcspi1_ick",
2831 .addr = omap2_mcspi1_addr_space,
2832 .user = OCP_USER_MPU | OCP_USER_SDMA,
2833 };
2834
2835 /* l4 core -> mcspi2 interface */
2836 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2837 .master = &omap3xxx_l4_core_hwmod,
2838 .slave = &omap34xx_mcspi2,
2839 .clk = "mcspi2_ick",
2840 .addr = omap2_mcspi2_addr_space,
2841 .user = OCP_USER_MPU | OCP_USER_SDMA,
2842 };
2843
2844 /* l4 core -> mcspi3 interface */
2845 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2846 .master = &omap3xxx_l4_core_hwmod,
2847 .slave = &omap34xx_mcspi3,
2848 .clk = "mcspi3_ick",
2849 .addr = omap2430_mcspi3_addr_space,
2850 .user = OCP_USER_MPU | OCP_USER_SDMA,
2851 };
2852
2853 /* l4 core -> mcspi4 interface */
2854 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
2855 {
2856 .pa_start = 0x480ba000,
2857 .pa_end = 0x480ba0ff,
2858 .flags = ADDR_TYPE_RT,
2859 },
2860 { }
2861 };
2862
2863 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2864 .master = &omap3xxx_l4_core_hwmod,
2865 .slave = &omap34xx_mcspi4,
2866 .clk = "mcspi4_ick",
2867 .addr = omap34xx_mcspi4_addr_space,
2868 .user = OCP_USER_MPU | OCP_USER_SDMA,
2869 };
2870
2871 /*
2872 * 'mcspi' class
2873 * multichannel serial port interface (mcspi) / master/slave synchronous serial
2874 * bus
2875 */
2876
2877 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
2878 .rev_offs = 0x0000,
2879 .sysc_offs = 0x0010,
2880 .syss_offs = 0x0014,
2881 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2882 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2883 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2884 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2885 .sysc_fields = &omap_hwmod_sysc_type1,
2886 };
2887
2888 static struct omap_hwmod_class omap34xx_mcspi_class = {
2889 .name = "mcspi",
2890 .sysc = &omap34xx_mcspi_sysc,
2891 .rev = OMAP3_MCSPI_REV,
2892 };
2893
2894 /* mcspi1 */
2895 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
2896 &omap34xx_l4_core__mcspi1,
2897 };
2898
2899 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2900 .num_chipselect = 4,
2901 };
2902
2903 static struct omap_hwmod omap34xx_mcspi1 = {
2904 .name = "mcspi1",
2905 .mpu_irqs = omap2_mcspi1_mpu_irqs,
2906 .sdma_reqs = omap2_mcspi1_sdma_reqs,
2907 .main_clk = "mcspi1_fck",
2908 .prcm = {
2909 .omap2 = {
2910 .module_offs = CORE_MOD,
2911 .prcm_reg_id = 1,
2912 .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
2913 .idlest_reg_id = 1,
2914 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
2915 },
2916 },
2917 .slaves = omap34xx_mcspi1_slaves,
2918 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves),
2919 .class = &omap34xx_mcspi_class,
2920 .dev_attr = &omap_mcspi1_dev_attr,
2921 };
2922
2923 /* mcspi2 */
2924 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
2925 &omap34xx_l4_core__mcspi2,
2926 };
2927
2928 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2929 .num_chipselect = 2,
2930 };
2931
2932 static struct omap_hwmod omap34xx_mcspi2 = {
2933 .name = "mcspi2",
2934 .mpu_irqs = omap2_mcspi2_mpu_irqs,
2935 .sdma_reqs = omap2_mcspi2_sdma_reqs,
2936 .main_clk = "mcspi2_fck",
2937 .prcm = {
2938 .omap2 = {
2939 .module_offs = CORE_MOD,
2940 .prcm_reg_id = 1,
2941 .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
2942 .idlest_reg_id = 1,
2943 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
2944 },
2945 },
2946 .slaves = omap34xx_mcspi2_slaves,
2947 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves),
2948 .class = &omap34xx_mcspi_class,
2949 .dev_attr = &omap_mcspi2_dev_attr,
2950 };
2951
2952 /* mcspi3 */
2953 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
2954 { .name = "irq", .irq = 91 }, /* 91 */
2955 { .irq = -1 }
2956 };
2957
2958 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
2959 { .name = "tx0", .dma_req = 15 },
2960 { .name = "rx0", .dma_req = 16 },
2961 { .name = "tx1", .dma_req = 23 },
2962 { .name = "rx1", .dma_req = 24 },
2963 { .dma_req = -1 }
2964 };
2965
2966 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
2967 &omap34xx_l4_core__mcspi3,
2968 };
2969
2970 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
2971 .num_chipselect = 2,
2972 };
2973
2974 static struct omap_hwmod omap34xx_mcspi3 = {
2975 .name = "mcspi3",
2976 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
2977 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
2978 .main_clk = "mcspi3_fck",
2979 .prcm = {
2980 .omap2 = {
2981 .module_offs = CORE_MOD,
2982 .prcm_reg_id = 1,
2983 .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
2984 .idlest_reg_id = 1,
2985 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
2986 },
2987 },
2988 .slaves = omap34xx_mcspi3_slaves,
2989 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves),
2990 .class = &omap34xx_mcspi_class,
2991 .dev_attr = &omap_mcspi3_dev_attr,
2992 };
2993
2994 /* SPI4 */
2995 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
2996 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
2997 { .irq = -1 }
2998 };
2999
3000 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
3001 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
3002 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
3003 { .dma_req = -1 }
3004 };
3005
3006 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
3007 &omap34xx_l4_core__mcspi4,
3008 };
3009
3010 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
3011 .num_chipselect = 1,
3012 };
3013
3014 static struct omap_hwmod omap34xx_mcspi4 = {
3015 .name = "mcspi4",
3016 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
3017 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
3018 .main_clk = "mcspi4_fck",
3019 .prcm = {
3020 .omap2 = {
3021 .module_offs = CORE_MOD,
3022 .prcm_reg_id = 1,
3023 .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
3024 .idlest_reg_id = 1,
3025 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
3026 },
3027 },
3028 .slaves = omap34xx_mcspi4_slaves,
3029 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves),
3030 .class = &omap34xx_mcspi_class,
3031 .dev_attr = &omap_mcspi4_dev_attr,
3032 };
3033
3034 /*
3035 * usbhsotg
3036 */
3037 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
3038 .rev_offs = 0x0400,
3039 .sysc_offs = 0x0404,
3040 .syss_offs = 0x0408,
3041 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
3042 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3043 SYSC_HAS_AUTOIDLE),
3044 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3045 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
3046 .sysc_fields = &omap_hwmod_sysc_type1,
3047 };
3048
3049 static struct omap_hwmod_class usbotg_class = {
3050 .name = "usbotg",
3051 .sysc = &omap3xxx_usbhsotg_sysc,
3052 };
3053 /* usb_otg_hs */
3054 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
3055
3056 { .name = "mc", .irq = 92 },
3057 { .name = "dma", .irq = 93 },
3058 { .irq = -1 }
3059 };
3060
3061 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
3062 .name = "usb_otg_hs",
3063 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
3064 .main_clk = "hsotgusb_ick",
3065 .prcm = {
3066 .omap2 = {
3067 .prcm_reg_id = 1,
3068 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
3069 .module_offs = CORE_MOD,
3070 .idlest_reg_id = 1,
3071 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
3072 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
3073 },
3074 },
3075 .masters = omap3xxx_usbhsotg_masters,
3076 .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
3077 .slaves = omap3xxx_usbhsotg_slaves,
3078 .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
3079 .class = &usbotg_class,
3080
3081 /*
3082 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
3083 * broken when autoidle is enabled
3084 * workaround is to disable the autoidle bit at module level.
3085 */
3086 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
3087 | HWMOD_SWSUP_MSTANDBY,
3088 };
3089
3090 /* usb_otg_hs */
3091 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
3092
3093 { .name = "mc", .irq = 71 },
3094 { .irq = -1 }
3095 };
3096
3097 static struct omap_hwmod_class am35xx_usbotg_class = {
3098 .name = "am35xx_usbotg",
3099 .sysc = NULL,
3100 };
3101
3102 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
3103 .name = "am35x_otg_hs",
3104 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
3105 .main_clk = NULL,
3106 .prcm = {
3107 .omap2 = {
3108 },
3109 },
3110 .masters = am35xx_usbhsotg_masters,
3111 .masters_cnt = ARRAY_SIZE(am35xx_usbhsotg_masters),
3112 .slaves = am35xx_usbhsotg_slaves,
3113 .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves),
3114 .class = &am35xx_usbotg_class,
3115 };
3116
3117 /* MMC/SD/SDIO common */
3118
3119 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
3120 .rev_offs = 0x1fc,
3121 .sysc_offs = 0x10,
3122 .syss_offs = 0x14,
3123 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3124 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3125 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3126 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3127 .sysc_fields = &omap_hwmod_sysc_type1,
3128 };
3129
3130 static struct omap_hwmod_class omap34xx_mmc_class = {
3131 .name = "mmc",
3132 .sysc = &omap34xx_mmc_sysc,
3133 };
3134
3135 /* MMC/SD/SDIO1 */
3136
3137 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
3138 { .irq = 83, },
3139 { .irq = -1 }
3140 };
3141
3142 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
3143 { .name = "tx", .dma_req = 61, },
3144 { .name = "rx", .dma_req = 62, },
3145 { .dma_req = -1 }
3146 };
3147
3148 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
3149 { .role = "dbck", .clk = "omap_32k_fck", },
3150 };
3151
3152 static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
3153 &omap3xxx_l4_core__mmc1,
3154 };
3155
3156 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3157 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3158 };
3159
3160 /* See 35xx errata 2.1.1.128 in SPRZ278F */
3161 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
3162 .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
3163 OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
3164 };
3165
3166 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
3167 .name = "mmc1",
3168 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
3169 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
3170 .opt_clks = omap34xx_mmc1_opt_clks,
3171 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3172 .main_clk = "mmchs1_fck",
3173 .prcm = {
3174 .omap2 = {
3175 .module_offs = CORE_MOD,
3176 .prcm_reg_id = 1,
3177 .module_bit = OMAP3430_EN_MMC1_SHIFT,
3178 .idlest_reg_id = 1,
3179 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3180 },
3181 },
3182 .dev_attr = &mmc1_pre_es3_dev_attr,
3183 .slaves = omap3xxx_mmc1_slaves,
3184 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3185 .class = &omap34xx_mmc_class,
3186 };
3187
3188 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
3189 .name = "mmc1",
3190 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
3191 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
3192 .opt_clks = omap34xx_mmc1_opt_clks,
3193 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3194 .main_clk = "mmchs1_fck",
3195 .prcm = {
3196 .omap2 = {
3197 .module_offs = CORE_MOD,
3198 .prcm_reg_id = 1,
3199 .module_bit = OMAP3430_EN_MMC1_SHIFT,
3200 .idlest_reg_id = 1,
3201 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3202 },
3203 },
3204 .dev_attr = &mmc1_dev_attr,
3205 .slaves = omap3xxx_mmc1_slaves,
3206 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3207 .class = &omap34xx_mmc_class,
3208 };
3209
3210 /* MMC/SD/SDIO2 */
3211
3212 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
3213 { .irq = INT_24XX_MMC2_IRQ, },
3214 { .irq = -1 }
3215 };
3216
3217 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
3218 { .name = "tx", .dma_req = 47, },
3219 { .name = "rx", .dma_req = 48, },
3220 { .dma_req = -1 }
3221 };
3222
3223 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
3224 { .role = "dbck", .clk = "omap_32k_fck", },
3225 };
3226
3227 static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3228 &omap3xxx_l4_core__mmc2,
3229 };
3230
3231 /* See 35xx errata 2.1.1.128 in SPRZ278F */
3232 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
3233 .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
3234 };
3235
3236 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
3237 .name = "mmc2",
3238 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
3239 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
3240 .opt_clks = omap34xx_mmc2_opt_clks,
3241 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3242 .main_clk = "mmchs2_fck",
3243 .prcm = {
3244 .omap2 = {
3245 .module_offs = CORE_MOD,
3246 .prcm_reg_id = 1,
3247 .module_bit = OMAP3430_EN_MMC2_SHIFT,
3248 .idlest_reg_id = 1,
3249 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3250 },
3251 },
3252 .dev_attr = &mmc2_pre_es3_dev_attr,
3253 .slaves = omap3xxx_mmc2_slaves,
3254 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3255 .class = &omap34xx_mmc_class,
3256 };
3257
3258 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
3259 .name = "mmc2",
3260 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
3261 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
3262 .opt_clks = omap34xx_mmc2_opt_clks,
3263 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3264 .main_clk = "mmchs2_fck",
3265 .prcm = {
3266 .omap2 = {
3267 .module_offs = CORE_MOD,
3268 .prcm_reg_id = 1,
3269 .module_bit = OMAP3430_EN_MMC2_SHIFT,
3270 .idlest_reg_id = 1,
3271 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3272 },
3273 },
3274 .slaves = omap3xxx_mmc2_slaves,
3275 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3276 .class = &omap34xx_mmc_class,
3277 };
3278
3279 /* MMC/SD/SDIO3 */
3280
3281 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
3282 { .irq = 94, },
3283 { .irq = -1 }
3284 };
3285
3286 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
3287 { .name = "tx", .dma_req = 77, },
3288 { .name = "rx", .dma_req = 78, },
3289 { .dma_req = -1 }
3290 };
3291
3292 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
3293 { .role = "dbck", .clk = "omap_32k_fck", },
3294 };
3295
3296 static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3297 &omap3xxx_l4_core__mmc3,
3298 };
3299
3300 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3301 .name = "mmc3",
3302 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
3303 .sdma_reqs = omap34xx_mmc3_sdma_reqs,
3304 .opt_clks = omap34xx_mmc3_opt_clks,
3305 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
3306 .main_clk = "mmchs3_fck",
3307 .prcm = {
3308 .omap2 = {
3309 .prcm_reg_id = 1,
3310 .module_bit = OMAP3430_EN_MMC3_SHIFT,
3311 .idlest_reg_id = 1,
3312 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
3313 },
3314 },
3315 .slaves = omap3xxx_mmc3_slaves,
3316 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc3_slaves),
3317 .class = &omap34xx_mmc_class,
3318 };
3319
3320 /*
3321 * 'usb_host_hs' class
3322 * high-speed multi-port usb host controller
3323 */
3324 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3325 .master = &omap3xxx_usb_host_hs_hwmod,
3326 .slave = &omap3xxx_l3_main_hwmod,
3327 .clk = "core_l3_ick",
3328 .user = OCP_USER_MPU,
3329 };
3330
3331 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
3332 .rev_offs = 0x0000,
3333 .sysc_offs = 0x0010,
3334 .syss_offs = 0x0014,
3335 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
3336 SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
3337 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
3338 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3339 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
3340 .sysc_fields = &omap_hwmod_sysc_type1,
3341 };
3342
3343 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
3344 .name = "usb_host_hs",
3345 .sysc = &omap3xxx_usb_host_hs_sysc,
3346 };
3347
3348 static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_masters[] = {
3349 &omap3xxx_usb_host_hs__l3_main_2,
3350 };
3351
3352 static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3353 {
3354 .name = "uhh",
3355 .pa_start = 0x48064000,
3356 .pa_end = 0x480643ff,
3357 .flags = ADDR_TYPE_RT
3358 },
3359 {
3360 .name = "ohci",
3361 .pa_start = 0x48064400,
3362 .pa_end = 0x480647ff,
3363 },
3364 {
3365 .name = "ehci",
3366 .pa_start = 0x48064800,
3367 .pa_end = 0x48064cff,
3368 },
3369 {}
3370 };
3371
3372 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3373 .master = &omap3xxx_l4_core_hwmod,
3374 .slave = &omap3xxx_usb_host_hs_hwmod,
3375 .clk = "usbhost_ick",
3376 .addr = omap3xxx_usb_host_hs_addrs,
3377 .user = OCP_USER_MPU | OCP_USER_SDMA,
3378 };
3379
3380 static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_slaves[] = {
3381 &omap3xxx_l4_core__usb_host_hs,
3382 };
3383
3384 static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
3385 { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
3386 };
3387
3388 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
3389 { .name = "ohci-irq", .irq = 76 },
3390 { .name = "ehci-irq", .irq = 77 },
3391 { .irq = -1 }
3392 };
3393
3394 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
3395 .name = "usb_host_hs",
3396 .class = &omap3xxx_usb_host_hs_hwmod_class,
3397 .clkdm_name = "l3_init_clkdm",
3398 .mpu_irqs = omap3xxx_usb_host_hs_irqs,
3399 .main_clk = "usbhost_48m_fck",
3400 .prcm = {
3401 .omap2 = {
3402 .module_offs = OMAP3430ES2_USBHOST_MOD,
3403 .prcm_reg_id = 1,
3404 .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
3405 .idlest_reg_id = 1,
3406 .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
3407 .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
3408 },
3409 },
3410 .opt_clks = omap3xxx_usb_host_hs_opt_clks,
3411 .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
3412 .slaves = omap3xxx_usb_host_hs_slaves,
3413 .slaves_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_slaves),
3414 .masters = omap3xxx_usb_host_hs_masters,
3415 .masters_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_masters),
3416
3417 /*
3418 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3419 * id: i660
3420 *
3421 * Description:
3422 * In the following configuration :
3423 * - USBHOST module is set to smart-idle mode
3424 * - PRCM asserts idle_req to the USBHOST module ( This typically
3425 * happens when the system is going to a low power mode : all ports
3426 * have been suspended, the master part of the USBHOST module has
3427 * entered the standby state, and SW has cut the functional clocks)
3428 * - an USBHOST interrupt occurs before the module is able to answer
3429 * idle_ack, typically a remote wakeup IRQ.
3430 * Then the USB HOST module will enter a deadlock situation where it
3431 * is no more accessible nor functional.
3432 *
3433 * Workaround:
3434 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3435 */
3436
3437 /*
3438 * Errata: USB host EHCI may stall when entering smart-standby mode
3439 * Id: i571
3440 *
3441 * Description:
3442 * When the USBHOST module is set to smart-standby mode, and when it is
3443 * ready to enter the standby state (i.e. all ports are suspended and
3444 * all attached devices are in suspend mode), then it can wrongly assert
3445 * the Mstandby signal too early while there are still some residual OCP
3446 * transactions ongoing. If this condition occurs, the internal state
3447 * machine may go to an undefined state and the USB link may be stuck
3448 * upon the next resume.
3449 *
3450 * Workaround:
3451 * Don't use smart standby; use only force standby,
3452 * hence HWMOD_SWSUP_MSTANDBY
3453 */
3454
3455 /*
3456 * During system boot; If the hwmod framework resets the module
3457 * the module will have smart idle settings; which can lead to deadlock
3458 * (above Errata Id:i660); so, dont reset the module during boot;
3459 * Use HWMOD_INIT_NO_RESET.
3460 */
3461
3462 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3463 HWMOD_INIT_NO_RESET,
3464 };
3465
3466 /*
3467 * 'usb_tll_hs' class
3468 * usb_tll_hs module is the adapter on the usb_host_hs ports
3469 */
3470 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
3471 .rev_offs = 0x0000,
3472 .sysc_offs = 0x0010,
3473 .syss_offs = 0x0014,
3474 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3475 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3476 SYSC_HAS_AUTOIDLE),
3477 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3478 .sysc_fields = &omap_hwmod_sysc_type1,
3479 };
3480
3481 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
3482 .name = "usb_tll_hs",
3483 .sysc = &omap3xxx_usb_tll_hs_sysc,
3484 };
3485
3486 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
3487 { .name = "tll-irq", .irq = 78 },
3488 { .irq = -1 }
3489 };
3490
3491 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3492 {
3493 .name = "tll",
3494 .pa_start = 0x48062000,
3495 .pa_end = 0x48062fff,
3496 .flags = ADDR_TYPE_RT
3497 },
3498 {}
3499 };
3500
3501 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3502 .master = &omap3xxx_l4_core_hwmod,
3503 .slave = &omap3xxx_usb_tll_hs_hwmod,
3504 .clk = "usbtll_ick",
3505 .addr = omap3xxx_usb_tll_hs_addrs,
3506 .user = OCP_USER_MPU | OCP_USER_SDMA,
3507 };
3508
3509 static struct omap_hwmod_ocp_if *omap3xxx_usb_tll_hs_slaves[] = {
3510 &omap3xxx_l4_core__usb_tll_hs,
3511 };
3512
3513 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
3514 .name = "usb_tll_hs",
3515 .class = &omap3xxx_usb_tll_hs_hwmod_class,
3516 .clkdm_name = "l3_init_clkdm",
3517 .mpu_irqs = omap3xxx_usb_tll_hs_irqs,
3518 .main_clk = "usbtll_fck",
3519 .prcm = {
3520 .omap2 = {
3521 .module_offs = CORE_MOD,
3522 .prcm_reg_id = 3,
3523 .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
3524 .idlest_reg_id = 3,
3525 .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
3526 },
3527 },
3528 .slaves = omap3xxx_usb_tll_hs_slaves,
3529 .slaves_cnt = ARRAY_SIZE(omap3xxx_usb_tll_hs_slaves),
3530 };
3531
3532 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
3533 &omap3xxx_l3_main_hwmod,
3534 &omap3xxx_l4_core_hwmod,
3535 &omap3xxx_l4_per_hwmod,
3536 &omap3xxx_l4_wkup_hwmod,
3537 &omap3xxx_mmc3_hwmod,
3538 &omap3xxx_mpu_hwmod,
3539
3540 &omap3xxx_timer1_hwmod,
3541 &omap3xxx_timer2_hwmod,
3542 &omap3xxx_timer3_hwmod,
3543 &omap3xxx_timer4_hwmod,
3544 &omap3xxx_timer5_hwmod,
3545 &omap3xxx_timer6_hwmod,
3546 &omap3xxx_timer7_hwmod,
3547 &omap3xxx_timer8_hwmod,
3548 &omap3xxx_timer9_hwmod,
3549 &omap3xxx_timer10_hwmod,
3550 &omap3xxx_timer11_hwmod,
3551
3552 &omap3xxx_wd_timer2_hwmod,
3553 &omap3xxx_uart1_hwmod,
3554 &omap3xxx_uart2_hwmod,
3555 &omap3xxx_uart3_hwmod,
3556
3557 /* i2c class */
3558 &omap3xxx_i2c1_hwmod,
3559 &omap3xxx_i2c2_hwmod,
3560 &omap3xxx_i2c3_hwmod,
3561
3562 /* gpio class */
3563 &omap3xxx_gpio1_hwmod,
3564 &omap3xxx_gpio2_hwmod,
3565 &omap3xxx_gpio3_hwmod,
3566 &omap3xxx_gpio4_hwmod,
3567 &omap3xxx_gpio5_hwmod,
3568 &omap3xxx_gpio6_hwmod,
3569
3570 /* dma_system class*/
3571 &omap3xxx_dma_system_hwmod,
3572
3573 /* mcbsp class */
3574 &omap3xxx_mcbsp1_hwmod,
3575 &omap3xxx_mcbsp2_hwmod,
3576 &omap3xxx_mcbsp3_hwmod,
3577 &omap3xxx_mcbsp4_hwmod,
3578 &omap3xxx_mcbsp5_hwmod,
3579 &omap3xxx_mcbsp2_sidetone_hwmod,
3580 &omap3xxx_mcbsp3_sidetone_hwmod,
3581
3582
3583 /* mcspi class */
3584 &omap34xx_mcspi1,
3585 &omap34xx_mcspi2,
3586 &omap34xx_mcspi3,
3587 &omap34xx_mcspi4,
3588
3589 NULL,
3590 };
3591
3592 /* GP-only hwmods */
3593 static __initdata struct omap_hwmod *omap3xxx_gp_hwmods[] = {
3594 &omap3xxx_timer12_hwmod,
3595 NULL
3596 };
3597
3598 /* 3430ES1-only hwmods */
3599 static __initdata struct omap_hwmod *omap3430es1_hwmods[] = {
3600 &omap3430es1_dss_core_hwmod,
3601 NULL
3602 };
3603
3604 /* 3430ES2+-only hwmods */
3605 static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = {
3606 &omap3xxx_dss_core_hwmod,
3607 &omap3xxx_usbhsotg_hwmod,
3608 &omap3xxx_usb_host_hs_hwmod,
3609 &omap3xxx_usb_tll_hs_hwmod,
3610 NULL
3611 };
3612
3613 /* <= 3430ES3-only hwmods */
3614 static struct omap_hwmod *omap3430_pre_es3_hwmods[] __initdata = {
3615 &omap3xxx_pre_es3_mmc1_hwmod,
3616 &omap3xxx_pre_es3_mmc2_hwmod,
3617 NULL
3618 };
3619
3620 /* 3430ES3+-only hwmods */
3621 static struct omap_hwmod *omap3430_es3plus_hwmods[] __initdata = {
3622 &omap3xxx_es3plus_mmc1_hwmod,
3623 &omap3xxx_es3plus_mmc2_hwmod,
3624 NULL
3625 };
3626
3627 /* 34xx-only hwmods (all ES revisions) */
3628 static __initdata struct omap_hwmod *omap34xx_hwmods[] = {
3629 &omap3xxx_iva_hwmod,
3630 &omap34xx_sr1_hwmod,
3631 &omap34xx_sr2_hwmod,
3632 &omap3xxx_mailbox_hwmod,
3633 NULL
3634 };
3635
3636 /* 36xx-only hwmods (all ES revisions) */
3637 static __initdata struct omap_hwmod *omap36xx_hwmods[] = {
3638 &omap3xxx_iva_hwmod,
3639 &omap3xxx_uart4_hwmod,
3640 &omap3xxx_dss_core_hwmod,
3641 &omap36xx_sr1_hwmod,
3642 &omap36xx_sr2_hwmod,
3643 &omap3xxx_usbhsotg_hwmod,
3644 &omap3xxx_mailbox_hwmod,
3645 &omap3xxx_usb_host_hs_hwmod,
3646 &omap3xxx_usb_tll_hs_hwmod,
3647 &omap3xxx_es3plus_mmc1_hwmod,
3648 &omap3xxx_es3plus_mmc2_hwmod,
3649 NULL
3650 };
3651
3652 static __initdata struct omap_hwmod *am35xx_hwmods[] = {
3653 &omap3xxx_dss_core_hwmod, /* XXX ??? */
3654 &am35xx_usbhsotg_hwmod,
3655 &am35xx_uart4_hwmod,
3656 &omap3xxx_usb_host_hs_hwmod,
3657 &omap3xxx_usb_tll_hs_hwmod,
3658 &omap3xxx_es3plus_mmc1_hwmod,
3659 &omap3xxx_es3plus_mmc2_hwmod,
3660 NULL
3661 };
3662
3663 static __initdata struct omap_hwmod *omap3xxx_dss_hwmods[] = {
3664 /* dss class */
3665 &omap3xxx_dss_dispc_hwmod,
3666 &omap3xxx_dss_dsi1_hwmod,
3667 &omap3xxx_dss_rfbi_hwmod,
3668 &omap3xxx_dss_venc_hwmod,
3669 NULL
3670 };
3671
3672 int __init omap3xxx_hwmod_init(void)
3673 {
3674 int r;
3675 struct omap_hwmod **h = NULL;
3676 unsigned int rev;
3677
3678 /* Register hwmods common to all OMAP3 */
3679 r = omap_hwmod_register(omap3xxx_hwmods);
3680 if (r < 0)
3681 return r;
3682
3683 /* Register GP-only hwmods. */
3684 if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
3685 r = omap_hwmod_register(omap3xxx_gp_hwmods);
3686 if (r < 0)
3687 return r;
3688 }
3689
3690 rev = omap_rev();
3691
3692 /*
3693 * Register hwmods common to individual OMAP3 families, all
3694 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3695 * All possible revisions should be included in this conditional.
3696 */
3697 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3698 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3699 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3700 h = omap34xx_hwmods;
3701 } else if (rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1) {
3702 h = am35xx_hwmods;
3703 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3704 rev == OMAP3630_REV_ES1_2) {
3705 h = omap36xx_hwmods;
3706 } else {
3707 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3708 return -EINVAL;
3709 };
3710
3711 r = omap_hwmod_register(h);
3712 if (r < 0)
3713 return r;
3714
3715 /*
3716 * Register hwmods specific to certain ES levels of a
3717 * particular family of silicon (e.g., 34xx ES1.0)
3718 */
3719 h = NULL;
3720 if (rev == OMAP3430_REV_ES1_0) {
3721 h = omap3430es1_hwmods;
3722 } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3723 rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3724 rev == OMAP3430_REV_ES3_1_2) {
3725 h = omap3430es2plus_hwmods;
3726 };
3727
3728 if (h) {
3729 r = omap_hwmod_register(h);
3730 if (r < 0)
3731 return r;
3732 }
3733
3734 h = NULL;
3735 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3736 rev == OMAP3430_REV_ES2_1) {
3737 h = omap3430_pre_es3_hwmods;
3738 } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3739 rev == OMAP3430_REV_ES3_1_2) {
3740 h = omap3430_es3plus_hwmods;
3741 };
3742
3743 if (h)
3744 r = omap_hwmod_register(h);
3745 if (r < 0)
3746 return r;
3747
3748 /*
3749 * DSS code presumes that dss_core hwmod is handled first,
3750 * _before_ any other DSS related hwmods so register common
3751 * DSS hwmods last to ensure that dss_core is already registered.
3752 * Otherwise some change things may happen, for ex. if dispc
3753 * is handled before dss_core and DSS is enabled in bootloader
3754 * DIPSC will be reset with outputs enabled which sometimes leads
3755 * to unrecoverable L3 error.
3756 * XXX The long-term fix to this is to ensure modules are set up
3757 * in dependency order in the hwmod core code.
3758 */
3759 r = omap_hwmod_register(omap3xxx_dss_hwmods);
3760
3761 return r;
3762 }
Linux kernel - Deliverables
This page took 0.213725 seconds and 5 git commands to generate.