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Merge branch 'for-rmk/perf' into for-rmk/virt/kvm/core
[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_3xxx_data.c
1 /*
2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
3 *
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
6 * Paul Walmsley
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * The data in this file should be completely autogeneratable from
13 * the TI hardware database or other technical documentation.
14 *
15 * XXX these should be marked initdata for multi-OMAP kernels
16 */
17
18 #include <linux/i2c-omap.h>
19 #include <linux/power/smartreflex.h>
20 #include <linux/platform_data/gpio-omap.h>
21
22 #include <linux/omap-dma.h>
23 #include "l3_3xxx.h"
24 #include "l4_3xxx.h"
25 #include <linux/platform_data/asoc-ti-mcbsp.h>
26 #include <linux/platform_data/spi-omap2-mcspi.h>
27 #include <linux/platform_data/iommu-omap.h>
28 #include <plat/dmtimer.h>
29
30 #include "am35xx.h"
31
32 #include "soc.h"
33 #include "omap_hwmod.h"
34 #include "omap_hwmod_common_data.h"
35 #include "prm-regbits-34xx.h"
36 #include "cm-regbits-34xx.h"
37
38 #include "dma.h"
39 #include "i2c.h"
40 #include "mmc.h"
41 #include "wd_timer.h"
42 #include "serial.h"
43
44 /*
45 * OMAP3xxx hardware module integration data
46 *
47 * All of the data in this section should be autogeneratable from the
48 * TI hardware database or other technical documentation. Data that
49 * is driver-specific or driver-kernel integration-specific belongs
50 * elsewhere.
51 */
52
53 /*
54 * IP blocks
55 */
56
57 /* L3 */
58 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
59 { .irq = 9 + OMAP_INTC_START, },
60 { .irq = 10 + OMAP_INTC_START, },
61 { .irq = -1 },
62 };
63
64 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
65 .name = "l3_main",
66 .class = &l3_hwmod_class,
67 .mpu_irqs = omap3xxx_l3_main_irqs,
68 .flags = HWMOD_NO_IDLEST,
69 };
70
71 /* L4 CORE */
72 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
73 .name = "l4_core",
74 .class = &l4_hwmod_class,
75 .flags = HWMOD_NO_IDLEST,
76 };
77
78 /* L4 PER */
79 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
80 .name = "l4_per",
81 .class = &l4_hwmod_class,
82 .flags = HWMOD_NO_IDLEST,
83 };
84
85 /* L4 WKUP */
86 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
87 .name = "l4_wkup",
88 .class = &l4_hwmod_class,
89 .flags = HWMOD_NO_IDLEST,
90 };
91
92 /* L4 SEC */
93 static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
94 .name = "l4_sec",
95 .class = &l4_hwmod_class,
96 .flags = HWMOD_NO_IDLEST,
97 };
98
99 /* MPU */
100 static struct omap_hwmod_irq_info omap3xxx_mpu_irqs[] = {
101 { .name = "pmu", .irq = 3 + OMAP_INTC_START },
102 { .irq = -1 }
103 };
104
105 static struct omap_hwmod omap3xxx_mpu_hwmod = {
106 .name = "mpu",
107 .mpu_irqs = omap3xxx_mpu_irqs,
108 .class = &mpu_hwmod_class,
109 .main_clk = "arm_fck",
110 };
111
112 /* IVA2 (IVA2) */
113 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
114 { .name = "logic", .rst_shift = 0, .st_shift = 8 },
115 { .name = "seq0", .rst_shift = 1, .st_shift = 9 },
116 { .name = "seq1", .rst_shift = 2, .st_shift = 10 },
117 };
118
119 static struct omap_hwmod omap3xxx_iva_hwmod = {
120 .name = "iva",
121 .class = &iva_hwmod_class,
122 .clkdm_name = "iva2_clkdm",
123 .rst_lines = omap3xxx_iva_resets,
124 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets),
125 .main_clk = "iva2_ck",
126 .prcm = {
127 .omap2 = {
128 .module_offs = OMAP3430_IVA2_MOD,
129 .prcm_reg_id = 1,
130 .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
131 .idlest_reg_id = 1,
132 .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
133 }
134 },
135 };
136
137 /*
138 * 'debugss' class
139 * debug and emulation sub system
140 */
141
142 static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = {
143 .name = "debugss",
144 };
145
146 /* debugss */
147 static struct omap_hwmod omap3xxx_debugss_hwmod = {
148 .name = "debugss",
149 .class = &omap3xxx_debugss_hwmod_class,
150 .clkdm_name = "emu_clkdm",
151 .main_clk = "emu_src_ck",
152 .flags = HWMOD_NO_IDLEST,
153 };
154
155 /* timer class */
156 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
157 .rev_offs = 0x0000,
158 .sysc_offs = 0x0010,
159 .syss_offs = 0x0014,
160 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
161 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
162 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
163 SYSS_HAS_RESET_STATUS),
164 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
165 .clockact = CLOCKACT_TEST_ICLK,
166 .sysc_fields = &omap_hwmod_sysc_type1,
167 };
168
169 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
170 .name = "timer",
171 .sysc = &omap3xxx_timer_sysc,
172 };
173
174 /* secure timers dev attribute */
175 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
176 .timer_capability = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE,
177 };
178
179 /* always-on timers dev attribute */
180 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
181 .timer_capability = OMAP_TIMER_ALWON,
182 };
183
184 /* pwm timers dev attribute */
185 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
186 .timer_capability = OMAP_TIMER_HAS_PWM,
187 };
188
189 /* timers with DSP interrupt dev attribute */
190 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
191 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
192 };
193
194 /* pwm timers with DSP interrupt dev attribute */
195 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
196 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
197 };
198
199 /* timer1 */
200 static struct omap_hwmod omap3xxx_timer1_hwmod = {
201 .name = "timer1",
202 .mpu_irqs = omap2_timer1_mpu_irqs,
203 .main_clk = "gpt1_fck",
204 .prcm = {
205 .omap2 = {
206 .prcm_reg_id = 1,
207 .module_bit = OMAP3430_EN_GPT1_SHIFT,
208 .module_offs = WKUP_MOD,
209 .idlest_reg_id = 1,
210 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
211 },
212 },
213 .dev_attr = &capability_alwon_dev_attr,
214 .class = &omap3xxx_timer_hwmod_class,
215 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
216 };
217
218 /* timer2 */
219 static struct omap_hwmod omap3xxx_timer2_hwmod = {
220 .name = "timer2",
221 .mpu_irqs = omap2_timer2_mpu_irqs,
222 .main_clk = "gpt2_fck",
223 .prcm = {
224 .omap2 = {
225 .prcm_reg_id = 1,
226 .module_bit = OMAP3430_EN_GPT2_SHIFT,
227 .module_offs = OMAP3430_PER_MOD,
228 .idlest_reg_id = 1,
229 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
230 },
231 },
232 .class = &omap3xxx_timer_hwmod_class,
233 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
234 };
235
236 /* timer3 */
237 static struct omap_hwmod omap3xxx_timer3_hwmod = {
238 .name = "timer3",
239 .mpu_irqs = omap2_timer3_mpu_irqs,
240 .main_clk = "gpt3_fck",
241 .prcm = {
242 .omap2 = {
243 .prcm_reg_id = 1,
244 .module_bit = OMAP3430_EN_GPT3_SHIFT,
245 .module_offs = OMAP3430_PER_MOD,
246 .idlest_reg_id = 1,
247 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
248 },
249 },
250 .class = &omap3xxx_timer_hwmod_class,
251 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
252 };
253
254 /* timer4 */
255 static struct omap_hwmod omap3xxx_timer4_hwmod = {
256 .name = "timer4",
257 .mpu_irqs = omap2_timer4_mpu_irqs,
258 .main_clk = "gpt4_fck",
259 .prcm = {
260 .omap2 = {
261 .prcm_reg_id = 1,
262 .module_bit = OMAP3430_EN_GPT4_SHIFT,
263 .module_offs = OMAP3430_PER_MOD,
264 .idlest_reg_id = 1,
265 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
266 },
267 },
268 .class = &omap3xxx_timer_hwmod_class,
269 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
270 };
271
272 /* timer5 */
273 static struct omap_hwmod omap3xxx_timer5_hwmod = {
274 .name = "timer5",
275 .mpu_irqs = omap2_timer5_mpu_irqs,
276 .main_clk = "gpt5_fck",
277 .prcm = {
278 .omap2 = {
279 .prcm_reg_id = 1,
280 .module_bit = OMAP3430_EN_GPT5_SHIFT,
281 .module_offs = OMAP3430_PER_MOD,
282 .idlest_reg_id = 1,
283 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
284 },
285 },
286 .dev_attr = &capability_dsp_dev_attr,
287 .class = &omap3xxx_timer_hwmod_class,
288 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
289 };
290
291 /* timer6 */
292 static struct omap_hwmod omap3xxx_timer6_hwmod = {
293 .name = "timer6",
294 .mpu_irqs = omap2_timer6_mpu_irqs,
295 .main_clk = "gpt6_fck",
296 .prcm = {
297 .omap2 = {
298 .prcm_reg_id = 1,
299 .module_bit = OMAP3430_EN_GPT6_SHIFT,
300 .module_offs = OMAP3430_PER_MOD,
301 .idlest_reg_id = 1,
302 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
303 },
304 },
305 .dev_attr = &capability_dsp_dev_attr,
306 .class = &omap3xxx_timer_hwmod_class,
307 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
308 };
309
310 /* timer7 */
311 static struct omap_hwmod omap3xxx_timer7_hwmod = {
312 .name = "timer7",
313 .mpu_irqs = omap2_timer7_mpu_irqs,
314 .main_clk = "gpt7_fck",
315 .prcm = {
316 .omap2 = {
317 .prcm_reg_id = 1,
318 .module_bit = OMAP3430_EN_GPT7_SHIFT,
319 .module_offs = OMAP3430_PER_MOD,
320 .idlest_reg_id = 1,
321 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
322 },
323 },
324 .dev_attr = &capability_dsp_dev_attr,
325 .class = &omap3xxx_timer_hwmod_class,
326 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
327 };
328
329 /* timer8 */
330 static struct omap_hwmod omap3xxx_timer8_hwmod = {
331 .name = "timer8",
332 .mpu_irqs = omap2_timer8_mpu_irqs,
333 .main_clk = "gpt8_fck",
334 .prcm = {
335 .omap2 = {
336 .prcm_reg_id = 1,
337 .module_bit = OMAP3430_EN_GPT8_SHIFT,
338 .module_offs = OMAP3430_PER_MOD,
339 .idlest_reg_id = 1,
340 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
341 },
342 },
343 .dev_attr = &capability_dsp_pwm_dev_attr,
344 .class = &omap3xxx_timer_hwmod_class,
345 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
346 };
347
348 /* timer9 */
349 static struct omap_hwmod omap3xxx_timer9_hwmod = {
350 .name = "timer9",
351 .mpu_irqs = omap2_timer9_mpu_irqs,
352 .main_clk = "gpt9_fck",
353 .prcm = {
354 .omap2 = {
355 .prcm_reg_id = 1,
356 .module_bit = OMAP3430_EN_GPT9_SHIFT,
357 .module_offs = OMAP3430_PER_MOD,
358 .idlest_reg_id = 1,
359 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
360 },
361 },
362 .dev_attr = &capability_pwm_dev_attr,
363 .class = &omap3xxx_timer_hwmod_class,
364 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
365 };
366
367 /* timer10 */
368 static struct omap_hwmod omap3xxx_timer10_hwmod = {
369 .name = "timer10",
370 .mpu_irqs = omap2_timer10_mpu_irqs,
371 .main_clk = "gpt10_fck",
372 .prcm = {
373 .omap2 = {
374 .prcm_reg_id = 1,
375 .module_bit = OMAP3430_EN_GPT10_SHIFT,
376 .module_offs = CORE_MOD,
377 .idlest_reg_id = 1,
378 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
379 },
380 },
381 .dev_attr = &capability_pwm_dev_attr,
382 .class = &omap3xxx_timer_hwmod_class,
383 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
384 };
385
386 /* timer11 */
387 static struct omap_hwmod omap3xxx_timer11_hwmod = {
388 .name = "timer11",
389 .mpu_irqs = omap2_timer11_mpu_irqs,
390 .main_clk = "gpt11_fck",
391 .prcm = {
392 .omap2 = {
393 .prcm_reg_id = 1,
394 .module_bit = OMAP3430_EN_GPT11_SHIFT,
395 .module_offs = CORE_MOD,
396 .idlest_reg_id = 1,
397 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
398 },
399 },
400 .dev_attr = &capability_pwm_dev_attr,
401 .class = &omap3xxx_timer_hwmod_class,
402 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
403 };
404
405 /* timer12 */
406 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
407 { .irq = 95 + OMAP_INTC_START, },
408 { .irq = -1 },
409 };
410
411 static struct omap_hwmod omap3xxx_timer12_hwmod = {
412 .name = "timer12",
413 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
414 .main_clk = "gpt12_fck",
415 .prcm = {
416 .omap2 = {
417 .prcm_reg_id = 1,
418 .module_bit = OMAP3430_EN_GPT12_SHIFT,
419 .module_offs = WKUP_MOD,
420 .idlest_reg_id = 1,
421 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
422 },
423 },
424 .dev_attr = &capability_secure_dev_attr,
425 .class = &omap3xxx_timer_hwmod_class,
426 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
427 };
428
429 /*
430 * 'wd_timer' class
431 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
432 * overflow condition
433 */
434
435 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
436 .rev_offs = 0x0000,
437 .sysc_offs = 0x0010,
438 .syss_offs = 0x0014,
439 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
440 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
441 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
442 SYSS_HAS_RESET_STATUS),
443 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
444 .sysc_fields = &omap_hwmod_sysc_type1,
445 };
446
447 /* I2C common */
448 static struct omap_hwmod_class_sysconfig i2c_sysc = {
449 .rev_offs = 0x00,
450 .sysc_offs = 0x20,
451 .syss_offs = 0x10,
452 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
453 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
454 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
455 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
456 .clockact = CLOCKACT_TEST_ICLK,
457 .sysc_fields = &omap_hwmod_sysc_type1,
458 };
459
460 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
461 .name = "wd_timer",
462 .sysc = &omap3xxx_wd_timer_sysc,
463 .pre_shutdown = &omap2_wd_timer_disable,
464 .reset = &omap2_wd_timer_reset,
465 };
466
467 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
468 .name = "wd_timer2",
469 .class = &omap3xxx_wd_timer_hwmod_class,
470 .main_clk = "wdt2_fck",
471 .prcm = {
472 .omap2 = {
473 .prcm_reg_id = 1,
474 .module_bit = OMAP3430_EN_WDT2_SHIFT,
475 .module_offs = WKUP_MOD,
476 .idlest_reg_id = 1,
477 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
478 },
479 },
480 /*
481 * XXX: Use software supervised mode, HW supervised smartidle seems to
482 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
483 */
484 .flags = HWMOD_SWSUP_SIDLE,
485 };
486
487 /* UART1 */
488 static struct omap_hwmod omap3xxx_uart1_hwmod = {
489 .name = "uart1",
490 .mpu_irqs = omap2_uart1_mpu_irqs,
491 .sdma_reqs = omap2_uart1_sdma_reqs,
492 .main_clk = "uart1_fck",
493 .prcm = {
494 .omap2 = {
495 .module_offs = CORE_MOD,
496 .prcm_reg_id = 1,
497 .module_bit = OMAP3430_EN_UART1_SHIFT,
498 .idlest_reg_id = 1,
499 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
500 },
501 },
502 .class = &omap2_uart_class,
503 };
504
505 /* UART2 */
506 static struct omap_hwmod omap3xxx_uart2_hwmod = {
507 .name = "uart2",
508 .mpu_irqs = omap2_uart2_mpu_irqs,
509 .sdma_reqs = omap2_uart2_sdma_reqs,
510 .main_clk = "uart2_fck",
511 .prcm = {
512 .omap2 = {
513 .module_offs = CORE_MOD,
514 .prcm_reg_id = 1,
515 .module_bit = OMAP3430_EN_UART2_SHIFT,
516 .idlest_reg_id = 1,
517 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
518 },
519 },
520 .class = &omap2_uart_class,
521 };
522
523 /* UART3 */
524 static struct omap_hwmod omap3xxx_uart3_hwmod = {
525 .name = "uart3",
526 .mpu_irqs = omap2_uart3_mpu_irqs,
527 .sdma_reqs = omap2_uart3_sdma_reqs,
528 .main_clk = "uart3_fck",
529 .prcm = {
530 .omap2 = {
531 .module_offs = OMAP3430_PER_MOD,
532 .prcm_reg_id = 1,
533 .module_bit = OMAP3430_EN_UART3_SHIFT,
534 .idlest_reg_id = 1,
535 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
536 },
537 },
538 .class = &omap2_uart_class,
539 };
540
541 /* UART4 */
542 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
543 { .irq = 80 + OMAP_INTC_START, },
544 { .irq = -1 },
545 };
546
547 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
548 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
549 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
550 { .dma_req = -1 }
551 };
552
553 static struct omap_hwmod omap36xx_uart4_hwmod = {
554 .name = "uart4",
555 .mpu_irqs = uart4_mpu_irqs,
556 .sdma_reqs = uart4_sdma_reqs,
557 .main_clk = "uart4_fck",
558 .prcm = {
559 .omap2 = {
560 .module_offs = OMAP3430_PER_MOD,
561 .prcm_reg_id = 1,
562 .module_bit = OMAP3630_EN_UART4_SHIFT,
563 .idlest_reg_id = 1,
564 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
565 },
566 },
567 .class = &omap2_uart_class,
568 };
569
570 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
571 { .irq = 84 + OMAP_INTC_START, },
572 { .irq = -1 },
573 };
574
575 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
576 { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
577 { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
578 { .dma_req = -1 }
579 };
580
581 /*
582 * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
583 * uart2_fck being enabled. So we add uart1_fck as an optional clock,
584 * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET. This really
585 * should not be needed. The functional clock structure of the AM35xx
586 * UART4 is extremely unclear and opaque; it is unclear what the role
587 * of uart1/2_fck is for the UART4. Any clarification from either
588 * empirical testing or the AM3505/3517 hardware designers would be
589 * most welcome.
590 */
591 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
592 { .role = "softreset_uart1_fck", .clk = "uart1_fck" },
593 };
594
595 static struct omap_hwmod am35xx_uart4_hwmod = {
596 .name = "uart4",
597 .mpu_irqs = am35xx_uart4_mpu_irqs,
598 .sdma_reqs = am35xx_uart4_sdma_reqs,
599 .main_clk = "uart4_fck",
600 .prcm = {
601 .omap2 = {
602 .module_offs = CORE_MOD,
603 .prcm_reg_id = 1,
604 .module_bit = AM35XX_EN_UART4_SHIFT,
605 .idlest_reg_id = 1,
606 .idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
607 },
608 },
609 .opt_clks = am35xx_uart4_opt_clks,
610 .opt_clks_cnt = ARRAY_SIZE(am35xx_uart4_opt_clks),
611 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
612 .class = &omap2_uart_class,
613 };
614
615 static struct omap_hwmod_class i2c_class = {
616 .name = "i2c",
617 .sysc = &i2c_sysc,
618 .rev = OMAP_I2C_IP_VERSION_1,
619 .reset = &omap_i2c_reset,
620 };
621
622 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
623 { .name = "dispc", .dma_req = 5 },
624 { .name = "dsi1", .dma_req = 74 },
625 { .dma_req = -1 }
626 };
627
628 /* dss */
629 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
630 /*
631 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
632 * driver does not use these clocks.
633 */
634 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
635 { .role = "tv_clk", .clk = "dss_tv_fck" },
636 /* required only on OMAP3430 */
637 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
638 };
639
640 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
641 .name = "dss_core",
642 .class = &omap2_dss_hwmod_class,
643 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
644 .sdma_reqs = omap3xxx_dss_sdma_chs,
645 .prcm = {
646 .omap2 = {
647 .prcm_reg_id = 1,
648 .module_bit = OMAP3430_EN_DSS1_SHIFT,
649 .module_offs = OMAP3430_DSS_MOD,
650 .idlest_reg_id = 1,
651 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
652 },
653 },
654 .opt_clks = dss_opt_clks,
655 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
656 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
657 };
658
659 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
660 .name = "dss_core",
661 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
662 .class = &omap2_dss_hwmod_class,
663 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
664 .sdma_reqs = omap3xxx_dss_sdma_chs,
665 .prcm = {
666 .omap2 = {
667 .prcm_reg_id = 1,
668 .module_bit = OMAP3430_EN_DSS1_SHIFT,
669 .module_offs = OMAP3430_DSS_MOD,
670 .idlest_reg_id = 1,
671 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
672 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
673 },
674 },
675 .opt_clks = dss_opt_clks,
676 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
677 };
678
679 /*
680 * 'dispc' class
681 * display controller
682 */
683
684 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
685 .rev_offs = 0x0000,
686 .sysc_offs = 0x0010,
687 .syss_offs = 0x0014,
688 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
689 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
690 SYSC_HAS_ENAWAKEUP),
691 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
692 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
693 .sysc_fields = &omap_hwmod_sysc_type1,
694 };
695
696 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
697 .name = "dispc",
698 .sysc = &omap3_dispc_sysc,
699 };
700
701 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
702 .name = "dss_dispc",
703 .class = &omap3_dispc_hwmod_class,
704 .mpu_irqs = omap2_dispc_irqs,
705 .main_clk = "dss1_alwon_fck",
706 .prcm = {
707 .omap2 = {
708 .prcm_reg_id = 1,
709 .module_bit = OMAP3430_EN_DSS1_SHIFT,
710 .module_offs = OMAP3430_DSS_MOD,
711 },
712 },
713 .flags = HWMOD_NO_IDLEST,
714 .dev_attr = &omap2_3_dss_dispc_dev_attr
715 };
716
717 /*
718 * 'dsi' class
719 * display serial interface controller
720 */
721
722 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
723 .name = "dsi",
724 };
725
726 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
727 { .irq = 25 + OMAP_INTC_START, },
728 { .irq = -1 },
729 };
730
731 /* dss_dsi1 */
732 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
733 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
734 };
735
736 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
737 .name = "dss_dsi1",
738 .class = &omap3xxx_dsi_hwmod_class,
739 .mpu_irqs = omap3xxx_dsi1_irqs,
740 .main_clk = "dss1_alwon_fck",
741 .prcm = {
742 .omap2 = {
743 .prcm_reg_id = 1,
744 .module_bit = OMAP3430_EN_DSS1_SHIFT,
745 .module_offs = OMAP3430_DSS_MOD,
746 },
747 },
748 .opt_clks = dss_dsi1_opt_clks,
749 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
750 .flags = HWMOD_NO_IDLEST,
751 };
752
753 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
754 { .role = "ick", .clk = "dss_ick" },
755 };
756
757 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
758 .name = "dss_rfbi",
759 .class = &omap2_rfbi_hwmod_class,
760 .main_clk = "dss1_alwon_fck",
761 .prcm = {
762 .omap2 = {
763 .prcm_reg_id = 1,
764 .module_bit = OMAP3430_EN_DSS1_SHIFT,
765 .module_offs = OMAP3430_DSS_MOD,
766 },
767 },
768 .opt_clks = dss_rfbi_opt_clks,
769 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
770 .flags = HWMOD_NO_IDLEST,
771 };
772
773 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
774 /* required only on OMAP3430 */
775 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
776 };
777
778 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
779 .name = "dss_venc",
780 .class = &omap2_venc_hwmod_class,
781 .main_clk = "dss_tv_fck",
782 .prcm = {
783 .omap2 = {
784 .prcm_reg_id = 1,
785 .module_bit = OMAP3430_EN_DSS1_SHIFT,
786 .module_offs = OMAP3430_DSS_MOD,
787 },
788 },
789 .opt_clks = dss_venc_opt_clks,
790 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
791 .flags = HWMOD_NO_IDLEST,
792 };
793
794 /* I2C1 */
795 static struct omap_i2c_dev_attr i2c1_dev_attr = {
796 .fifo_depth = 8, /* bytes */
797 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
798 };
799
800 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
801 .name = "i2c1",
802 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
803 .mpu_irqs = omap2_i2c1_mpu_irqs,
804 .sdma_reqs = omap2_i2c1_sdma_reqs,
805 .main_clk = "i2c1_fck",
806 .prcm = {
807 .omap2 = {
808 .module_offs = CORE_MOD,
809 .prcm_reg_id = 1,
810 .module_bit = OMAP3430_EN_I2C1_SHIFT,
811 .idlest_reg_id = 1,
812 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
813 },
814 },
815 .class = &i2c_class,
816 .dev_attr = &i2c1_dev_attr,
817 };
818
819 /* I2C2 */
820 static struct omap_i2c_dev_attr i2c2_dev_attr = {
821 .fifo_depth = 8, /* bytes */
822 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
823 };
824
825 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
826 .name = "i2c2",
827 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
828 .mpu_irqs = omap2_i2c2_mpu_irqs,
829 .sdma_reqs = omap2_i2c2_sdma_reqs,
830 .main_clk = "i2c2_fck",
831 .prcm = {
832 .omap2 = {
833 .module_offs = CORE_MOD,
834 .prcm_reg_id = 1,
835 .module_bit = OMAP3430_EN_I2C2_SHIFT,
836 .idlest_reg_id = 1,
837 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
838 },
839 },
840 .class = &i2c_class,
841 .dev_attr = &i2c2_dev_attr,
842 };
843
844 /* I2C3 */
845 static struct omap_i2c_dev_attr i2c3_dev_attr = {
846 .fifo_depth = 64, /* bytes */
847 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
848 };
849
850 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
851 { .irq = 61 + OMAP_INTC_START, },
852 { .irq = -1 },
853 };
854
855 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
856 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
857 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
858 { .dma_req = -1 }
859 };
860
861 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
862 .name = "i2c3",
863 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
864 .mpu_irqs = i2c3_mpu_irqs,
865 .sdma_reqs = i2c3_sdma_reqs,
866 .main_clk = "i2c3_fck",
867 .prcm = {
868 .omap2 = {
869 .module_offs = CORE_MOD,
870 .prcm_reg_id = 1,
871 .module_bit = OMAP3430_EN_I2C3_SHIFT,
872 .idlest_reg_id = 1,
873 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
874 },
875 },
876 .class = &i2c_class,
877 .dev_attr = &i2c3_dev_attr,
878 };
879
880 /*
881 * 'gpio' class
882 * general purpose io module
883 */
884
885 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
886 .rev_offs = 0x0000,
887 .sysc_offs = 0x0010,
888 .syss_offs = 0x0014,
889 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
890 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
891 SYSS_HAS_RESET_STATUS),
892 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
893 .sysc_fields = &omap_hwmod_sysc_type1,
894 };
895
896 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
897 .name = "gpio",
898 .sysc = &omap3xxx_gpio_sysc,
899 .rev = 1,
900 };
901
902 /* gpio_dev_attr */
903 static struct omap_gpio_dev_attr gpio_dev_attr = {
904 .bank_width = 32,
905 .dbck_flag = true,
906 };
907
908 /* gpio1 */
909 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
910 { .role = "dbclk", .clk = "gpio1_dbck", },
911 };
912
913 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
914 .name = "gpio1",
915 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
916 .mpu_irqs = omap2_gpio1_irqs,
917 .main_clk = "gpio1_ick",
918 .opt_clks = gpio1_opt_clks,
919 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
920 .prcm = {
921 .omap2 = {
922 .prcm_reg_id = 1,
923 .module_bit = OMAP3430_EN_GPIO1_SHIFT,
924 .module_offs = WKUP_MOD,
925 .idlest_reg_id = 1,
926 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
927 },
928 },
929 .class = &omap3xxx_gpio_hwmod_class,
930 .dev_attr = &gpio_dev_attr,
931 };
932
933 /* gpio2 */
934 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
935 { .role = "dbclk", .clk = "gpio2_dbck", },
936 };
937
938 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
939 .name = "gpio2",
940 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
941 .mpu_irqs = omap2_gpio2_irqs,
942 .main_clk = "gpio2_ick",
943 .opt_clks = gpio2_opt_clks,
944 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
945 .prcm = {
946 .omap2 = {
947 .prcm_reg_id = 1,
948 .module_bit = OMAP3430_EN_GPIO2_SHIFT,
949 .module_offs = OMAP3430_PER_MOD,
950 .idlest_reg_id = 1,
951 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
952 },
953 },
954 .class = &omap3xxx_gpio_hwmod_class,
955 .dev_attr = &gpio_dev_attr,
956 };
957
958 /* gpio3 */
959 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
960 { .role = "dbclk", .clk = "gpio3_dbck", },
961 };
962
963 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
964 .name = "gpio3",
965 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
966 .mpu_irqs = omap2_gpio3_irqs,
967 .main_clk = "gpio3_ick",
968 .opt_clks = gpio3_opt_clks,
969 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
970 .prcm = {
971 .omap2 = {
972 .prcm_reg_id = 1,
973 .module_bit = OMAP3430_EN_GPIO3_SHIFT,
974 .module_offs = OMAP3430_PER_MOD,
975 .idlest_reg_id = 1,
976 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
977 },
978 },
979 .class = &omap3xxx_gpio_hwmod_class,
980 .dev_attr = &gpio_dev_attr,
981 };
982
983 /* gpio4 */
984 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
985 { .role = "dbclk", .clk = "gpio4_dbck", },
986 };
987
988 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
989 .name = "gpio4",
990 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
991 .mpu_irqs = omap2_gpio4_irqs,
992 .main_clk = "gpio4_ick",
993 .opt_clks = gpio4_opt_clks,
994 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
995 .prcm = {
996 .omap2 = {
997 .prcm_reg_id = 1,
998 .module_bit = OMAP3430_EN_GPIO4_SHIFT,
999 .module_offs = OMAP3430_PER_MOD,
1000 .idlest_reg_id = 1,
1001 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
1002 },
1003 },
1004 .class = &omap3xxx_gpio_hwmod_class,
1005 .dev_attr = &gpio_dev_attr,
1006 };
1007
1008 /* gpio5 */
1009 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
1010 { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */
1011 { .irq = -1 },
1012 };
1013
1014 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1015 { .role = "dbclk", .clk = "gpio5_dbck", },
1016 };
1017
1018 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
1019 .name = "gpio5",
1020 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1021 .mpu_irqs = omap3xxx_gpio5_irqs,
1022 .main_clk = "gpio5_ick",
1023 .opt_clks = gpio5_opt_clks,
1024 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1025 .prcm = {
1026 .omap2 = {
1027 .prcm_reg_id = 1,
1028 .module_bit = OMAP3430_EN_GPIO5_SHIFT,
1029 .module_offs = OMAP3430_PER_MOD,
1030 .idlest_reg_id = 1,
1031 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
1032 },
1033 },
1034 .class = &omap3xxx_gpio_hwmod_class,
1035 .dev_attr = &gpio_dev_attr,
1036 };
1037
1038 /* gpio6 */
1039 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
1040 { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */
1041 { .irq = -1 },
1042 };
1043
1044 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1045 { .role = "dbclk", .clk = "gpio6_dbck", },
1046 };
1047
1048 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
1049 .name = "gpio6",
1050 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1051 .mpu_irqs = omap3xxx_gpio6_irqs,
1052 .main_clk = "gpio6_ick",
1053 .opt_clks = gpio6_opt_clks,
1054 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1055 .prcm = {
1056 .omap2 = {
1057 .prcm_reg_id = 1,
1058 .module_bit = OMAP3430_EN_GPIO6_SHIFT,
1059 .module_offs = OMAP3430_PER_MOD,
1060 .idlest_reg_id = 1,
1061 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
1062 },
1063 },
1064 .class = &omap3xxx_gpio_hwmod_class,
1065 .dev_attr = &gpio_dev_attr,
1066 };
1067
1068 /* dma attributes */
1069 static struct omap_dma_dev_attr dma_dev_attr = {
1070 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1071 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1072 .lch_count = 32,
1073 };
1074
1075 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1076 .rev_offs = 0x0000,
1077 .sysc_offs = 0x002c,
1078 .syss_offs = 0x0028,
1079 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1080 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1081 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
1082 SYSS_HAS_RESET_STATUS),
1083 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1084 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1085 .sysc_fields = &omap_hwmod_sysc_type1,
1086 };
1087
1088 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1089 .name = "dma",
1090 .sysc = &omap3xxx_dma_sysc,
1091 };
1092
1093 /* dma_system */
1094 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1095 .name = "dma",
1096 .class = &omap3xxx_dma_hwmod_class,
1097 .mpu_irqs = omap2_dma_system_irqs,
1098 .main_clk = "core_l3_ick",
1099 .prcm = {
1100 .omap2 = {
1101 .module_offs = CORE_MOD,
1102 .prcm_reg_id = 1,
1103 .module_bit = OMAP3430_ST_SDMA_SHIFT,
1104 .idlest_reg_id = 1,
1105 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
1106 },
1107 },
1108 .dev_attr = &dma_dev_attr,
1109 .flags = HWMOD_NO_IDLEST,
1110 };
1111
1112 /*
1113 * 'mcbsp' class
1114 * multi channel buffered serial port controller
1115 */
1116
1117 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
1118 .sysc_offs = 0x008c,
1119 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1120 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1121 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1122 .sysc_fields = &omap_hwmod_sysc_type1,
1123 .clockact = 0x2,
1124 };
1125
1126 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1127 .name = "mcbsp",
1128 .sysc = &omap3xxx_mcbsp_sysc,
1129 .rev = MCBSP_CONFIG_TYPE3,
1130 };
1131
1132 /* McBSP functional clock mapping */
1133 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
1134 { .role = "pad_fck", .clk = "mcbsp_clks" },
1135 { .role = "prcm_fck", .clk = "core_96m_fck" },
1136 };
1137
1138 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
1139 { .role = "pad_fck", .clk = "mcbsp_clks" },
1140 { .role = "prcm_fck", .clk = "per_96m_fck" },
1141 };
1142
1143 /* mcbsp1 */
1144 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
1145 { .name = "common", .irq = 16 + OMAP_INTC_START, },
1146 { .name = "tx", .irq = 59 + OMAP_INTC_START, },
1147 { .name = "rx", .irq = 60 + OMAP_INTC_START, },
1148 { .irq = -1 },
1149 };
1150
1151 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1152 .name = "mcbsp1",
1153 .class = &omap3xxx_mcbsp_hwmod_class,
1154 .mpu_irqs = omap3xxx_mcbsp1_irqs,
1155 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
1156 .main_clk = "mcbsp1_fck",
1157 .prcm = {
1158 .omap2 = {
1159 .prcm_reg_id = 1,
1160 .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
1161 .module_offs = CORE_MOD,
1162 .idlest_reg_id = 1,
1163 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
1164 },
1165 },
1166 .opt_clks = mcbsp15_opt_clks,
1167 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
1168 };
1169
1170 /* mcbsp2 */
1171 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
1172 { .name = "common", .irq = 17 + OMAP_INTC_START, },
1173 { .name = "tx", .irq = 62 + OMAP_INTC_START, },
1174 { .name = "rx", .irq = 63 + OMAP_INTC_START, },
1175 { .irq = -1 },
1176 };
1177
1178 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1179 .sidetone = "mcbsp2_sidetone",
1180 };
1181
1182 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1183 .name = "mcbsp2",
1184 .class = &omap3xxx_mcbsp_hwmod_class,
1185 .mpu_irqs = omap3xxx_mcbsp2_irqs,
1186 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
1187 .main_clk = "mcbsp2_fck",
1188 .prcm = {
1189 .omap2 = {
1190 .prcm_reg_id = 1,
1191 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1192 .module_offs = OMAP3430_PER_MOD,
1193 .idlest_reg_id = 1,
1194 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1195 },
1196 },
1197 .opt_clks = mcbsp234_opt_clks,
1198 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1199 .dev_attr = &omap34xx_mcbsp2_dev_attr,
1200 };
1201
1202 /* mcbsp3 */
1203 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
1204 { .name = "common", .irq = 22 + OMAP_INTC_START, },
1205 { .name = "tx", .irq = 89 + OMAP_INTC_START, },
1206 { .name = "rx", .irq = 90 + OMAP_INTC_START, },
1207 { .irq = -1 },
1208 };
1209
1210 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1211 .sidetone = "mcbsp3_sidetone",
1212 };
1213
1214 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1215 .name = "mcbsp3",
1216 .class = &omap3xxx_mcbsp_hwmod_class,
1217 .mpu_irqs = omap3xxx_mcbsp3_irqs,
1218 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
1219 .main_clk = "mcbsp3_fck",
1220 .prcm = {
1221 .omap2 = {
1222 .prcm_reg_id = 1,
1223 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1224 .module_offs = OMAP3430_PER_MOD,
1225 .idlest_reg_id = 1,
1226 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1227 },
1228 },
1229 .opt_clks = mcbsp234_opt_clks,
1230 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1231 .dev_attr = &omap34xx_mcbsp3_dev_attr,
1232 };
1233
1234 /* mcbsp4 */
1235 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
1236 { .name = "common", .irq = 23 + OMAP_INTC_START, },
1237 { .name = "tx", .irq = 54 + OMAP_INTC_START, },
1238 { .name = "rx", .irq = 55 + OMAP_INTC_START, },
1239 { .irq = -1 },
1240 };
1241
1242 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
1243 { .name = "rx", .dma_req = 20 },
1244 { .name = "tx", .dma_req = 19 },
1245 { .dma_req = -1 }
1246 };
1247
1248 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1249 .name = "mcbsp4",
1250 .class = &omap3xxx_mcbsp_hwmod_class,
1251 .mpu_irqs = omap3xxx_mcbsp4_irqs,
1252 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
1253 .main_clk = "mcbsp4_fck",
1254 .prcm = {
1255 .omap2 = {
1256 .prcm_reg_id = 1,
1257 .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
1258 .module_offs = OMAP3430_PER_MOD,
1259 .idlest_reg_id = 1,
1260 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
1261 },
1262 },
1263 .opt_clks = mcbsp234_opt_clks,
1264 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1265 };
1266
1267 /* mcbsp5 */
1268 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
1269 { .name = "common", .irq = 27 + OMAP_INTC_START, },
1270 { .name = "tx", .irq = 81 + OMAP_INTC_START, },
1271 { .name = "rx", .irq = 82 + OMAP_INTC_START, },
1272 { .irq = -1 },
1273 };
1274
1275 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
1276 { .name = "rx", .dma_req = 22 },
1277 { .name = "tx", .dma_req = 21 },
1278 { .dma_req = -1 }
1279 };
1280
1281 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1282 .name = "mcbsp5",
1283 .class = &omap3xxx_mcbsp_hwmod_class,
1284 .mpu_irqs = omap3xxx_mcbsp5_irqs,
1285 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
1286 .main_clk = "mcbsp5_fck",
1287 .prcm = {
1288 .omap2 = {
1289 .prcm_reg_id = 1,
1290 .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
1291 .module_offs = CORE_MOD,
1292 .idlest_reg_id = 1,
1293 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
1294 },
1295 },
1296 .opt_clks = mcbsp15_opt_clks,
1297 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
1298 };
1299
1300 /* 'mcbsp sidetone' class */
1301 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
1302 .sysc_offs = 0x0010,
1303 .sysc_flags = SYSC_HAS_AUTOIDLE,
1304 .sysc_fields = &omap_hwmod_sysc_type1,
1305 };
1306
1307 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
1308 .name = "mcbsp_sidetone",
1309 .sysc = &omap3xxx_mcbsp_sidetone_sysc,
1310 };
1311
1312 /* mcbsp2_sidetone */
1313 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
1314 { .name = "irq", .irq = 4 + OMAP_INTC_START, },
1315 { .irq = -1 },
1316 };
1317
1318 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1319 .name = "mcbsp2_sidetone",
1320 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1321 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
1322 .main_clk = "mcbsp2_fck",
1323 .prcm = {
1324 .omap2 = {
1325 .prcm_reg_id = 1,
1326 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1327 .module_offs = OMAP3430_PER_MOD,
1328 .idlest_reg_id = 1,
1329 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1330 },
1331 },
1332 };
1333
1334 /* mcbsp3_sidetone */
1335 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
1336 { .name = "irq", .irq = 5 + OMAP_INTC_START, },
1337 { .irq = -1 },
1338 };
1339
1340 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1341 .name = "mcbsp3_sidetone",
1342 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1343 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
1344 .main_clk = "mcbsp3_fck",
1345 .prcm = {
1346 .omap2 = {
1347 .prcm_reg_id = 1,
1348 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1349 .module_offs = OMAP3430_PER_MOD,
1350 .idlest_reg_id = 1,
1351 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1352 },
1353 },
1354 };
1355
1356 /* SR common */
1357 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1358 .clkact_shift = 20,
1359 };
1360
1361 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1362 .sysc_offs = 0x24,
1363 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1364 .clockact = CLOCKACT_TEST_ICLK,
1365 .sysc_fields = &omap34xx_sr_sysc_fields,
1366 };
1367
1368 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1369 .name = "smartreflex",
1370 .sysc = &omap34xx_sr_sysc,
1371 .rev = 1,
1372 };
1373
1374 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
1375 .sidle_shift = 24,
1376 .enwkup_shift = 26,
1377 };
1378
1379 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1380 .sysc_offs = 0x38,
1381 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1382 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1383 SYSC_NO_CACHE),
1384 .sysc_fields = &omap36xx_sr_sysc_fields,
1385 };
1386
1387 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1388 .name = "smartreflex",
1389 .sysc = &omap36xx_sr_sysc,
1390 .rev = 2,
1391 };
1392
1393 /* SR1 */
1394 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1395 .sensor_voltdm_name = "mpu_iva",
1396 };
1397
1398 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
1399 { .irq = 18 + OMAP_INTC_START, },
1400 { .irq = -1 },
1401 };
1402
1403 static struct omap_hwmod omap34xx_sr1_hwmod = {
1404 .name = "smartreflex_mpu_iva",
1405 .class = &omap34xx_smartreflex_hwmod_class,
1406 .main_clk = "sr1_fck",
1407 .prcm = {
1408 .omap2 = {
1409 .prcm_reg_id = 1,
1410 .module_bit = OMAP3430_EN_SR1_SHIFT,
1411 .module_offs = WKUP_MOD,
1412 .idlest_reg_id = 1,
1413 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1414 },
1415 },
1416 .dev_attr = &sr1_dev_attr,
1417 .mpu_irqs = omap3_smartreflex_mpu_irqs,
1418 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1419 };
1420
1421 static struct omap_hwmod omap36xx_sr1_hwmod = {
1422 .name = "smartreflex_mpu_iva",
1423 .class = &omap36xx_smartreflex_hwmod_class,
1424 .main_clk = "sr1_fck",
1425 .prcm = {
1426 .omap2 = {
1427 .prcm_reg_id = 1,
1428 .module_bit = OMAP3430_EN_SR1_SHIFT,
1429 .module_offs = WKUP_MOD,
1430 .idlest_reg_id = 1,
1431 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1432 },
1433 },
1434 .dev_attr = &sr1_dev_attr,
1435 .mpu_irqs = omap3_smartreflex_mpu_irqs,
1436 };
1437
1438 /* SR2 */
1439 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1440 .sensor_voltdm_name = "core",
1441 };
1442
1443 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
1444 { .irq = 19 + OMAP_INTC_START, },
1445 { .irq = -1 },
1446 };
1447
1448 static struct omap_hwmod omap34xx_sr2_hwmod = {
1449 .name = "smartreflex_core",
1450 .class = &omap34xx_smartreflex_hwmod_class,
1451 .main_clk = "sr2_fck",
1452 .prcm = {
1453 .omap2 = {
1454 .prcm_reg_id = 1,
1455 .module_bit = OMAP3430_EN_SR2_SHIFT,
1456 .module_offs = WKUP_MOD,
1457 .idlest_reg_id = 1,
1458 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1459 },
1460 },
1461 .dev_attr = &sr2_dev_attr,
1462 .mpu_irqs = omap3_smartreflex_core_irqs,
1463 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1464 };
1465
1466 static struct omap_hwmod omap36xx_sr2_hwmod = {
1467 .name = "smartreflex_core",
1468 .class = &omap36xx_smartreflex_hwmod_class,
1469 .main_clk = "sr2_fck",
1470 .prcm = {
1471 .omap2 = {
1472 .prcm_reg_id = 1,
1473 .module_bit = OMAP3430_EN_SR2_SHIFT,
1474 .module_offs = WKUP_MOD,
1475 .idlest_reg_id = 1,
1476 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1477 },
1478 },
1479 .dev_attr = &sr2_dev_attr,
1480 .mpu_irqs = omap3_smartreflex_core_irqs,
1481 };
1482
1483 /*
1484 * 'mailbox' class
1485 * mailbox module allowing communication between the on-chip processors
1486 * using a queued mailbox-interrupt mechanism.
1487 */
1488
1489 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1490 .rev_offs = 0x000,
1491 .sysc_offs = 0x010,
1492 .syss_offs = 0x014,
1493 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1494 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1495 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1496 .sysc_fields = &omap_hwmod_sysc_type1,
1497 };
1498
1499 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1500 .name = "mailbox",
1501 .sysc = &omap3xxx_mailbox_sysc,
1502 };
1503
1504 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
1505 { .irq = 26 + OMAP_INTC_START, },
1506 { .irq = -1 },
1507 };
1508
1509 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1510 .name = "mailbox",
1511 .class = &omap3xxx_mailbox_hwmod_class,
1512 .mpu_irqs = omap3xxx_mailbox_irqs,
1513 .main_clk = "mailboxes_ick",
1514 .prcm = {
1515 .omap2 = {
1516 .prcm_reg_id = 1,
1517 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1518 .module_offs = CORE_MOD,
1519 .idlest_reg_id = 1,
1520 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1521 },
1522 },
1523 };
1524
1525 /*
1526 * 'mcspi' class
1527 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1528 * bus
1529 */
1530
1531 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1532 .rev_offs = 0x0000,
1533 .sysc_offs = 0x0010,
1534 .syss_offs = 0x0014,
1535 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1536 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1537 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1538 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1539 .sysc_fields = &omap_hwmod_sysc_type1,
1540 };
1541
1542 static struct omap_hwmod_class omap34xx_mcspi_class = {
1543 .name = "mcspi",
1544 .sysc = &omap34xx_mcspi_sysc,
1545 .rev = OMAP3_MCSPI_REV,
1546 };
1547
1548 /* mcspi1 */
1549 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1550 .num_chipselect = 4,
1551 };
1552
1553 static struct omap_hwmod omap34xx_mcspi1 = {
1554 .name = "mcspi1",
1555 .mpu_irqs = omap2_mcspi1_mpu_irqs,
1556 .sdma_reqs = omap2_mcspi1_sdma_reqs,
1557 .main_clk = "mcspi1_fck",
1558 .prcm = {
1559 .omap2 = {
1560 .module_offs = CORE_MOD,
1561 .prcm_reg_id = 1,
1562 .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
1563 .idlest_reg_id = 1,
1564 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1565 },
1566 },
1567 .class = &omap34xx_mcspi_class,
1568 .dev_attr = &omap_mcspi1_dev_attr,
1569 };
1570
1571 /* mcspi2 */
1572 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1573 .num_chipselect = 2,
1574 };
1575
1576 static struct omap_hwmod omap34xx_mcspi2 = {
1577 .name = "mcspi2",
1578 .mpu_irqs = omap2_mcspi2_mpu_irqs,
1579 .sdma_reqs = omap2_mcspi2_sdma_reqs,
1580 .main_clk = "mcspi2_fck",
1581 .prcm = {
1582 .omap2 = {
1583 .module_offs = CORE_MOD,
1584 .prcm_reg_id = 1,
1585 .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
1586 .idlest_reg_id = 1,
1587 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1588 },
1589 },
1590 .class = &omap34xx_mcspi_class,
1591 .dev_attr = &omap_mcspi2_dev_attr,
1592 };
1593
1594 /* mcspi3 */
1595 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
1596 { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */
1597 { .irq = -1 },
1598 };
1599
1600 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
1601 { .name = "tx0", .dma_req = 15 },
1602 { .name = "rx0", .dma_req = 16 },
1603 { .name = "tx1", .dma_req = 23 },
1604 { .name = "rx1", .dma_req = 24 },
1605 { .dma_req = -1 }
1606 };
1607
1608 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1609 .num_chipselect = 2,
1610 };
1611
1612 static struct omap_hwmod omap34xx_mcspi3 = {
1613 .name = "mcspi3",
1614 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
1615 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
1616 .main_clk = "mcspi3_fck",
1617 .prcm = {
1618 .omap2 = {
1619 .module_offs = CORE_MOD,
1620 .prcm_reg_id = 1,
1621 .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
1622 .idlest_reg_id = 1,
1623 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1624 },
1625 },
1626 .class = &omap34xx_mcspi_class,
1627 .dev_attr = &omap_mcspi3_dev_attr,
1628 };
1629
1630 /* mcspi4 */
1631 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
1632 { .name = "irq", .irq = 48 + OMAP_INTC_START, },
1633 { .irq = -1 },
1634 };
1635
1636 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
1637 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
1638 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
1639 { .dma_req = -1 }
1640 };
1641
1642 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1643 .num_chipselect = 1,
1644 };
1645
1646 static struct omap_hwmod omap34xx_mcspi4 = {
1647 .name = "mcspi4",
1648 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
1649 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
1650 .main_clk = "mcspi4_fck",
1651 .prcm = {
1652 .omap2 = {
1653 .module_offs = CORE_MOD,
1654 .prcm_reg_id = 1,
1655 .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
1656 .idlest_reg_id = 1,
1657 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1658 },
1659 },
1660 .class = &omap34xx_mcspi_class,
1661 .dev_attr = &omap_mcspi4_dev_attr,
1662 };
1663
1664 /* usbhsotg */
1665 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1666 .rev_offs = 0x0400,
1667 .sysc_offs = 0x0404,
1668 .syss_offs = 0x0408,
1669 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1670 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1671 SYSC_HAS_AUTOIDLE),
1672 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1673 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1674 .sysc_fields = &omap_hwmod_sysc_type1,
1675 };
1676
1677 static struct omap_hwmod_class usbotg_class = {
1678 .name = "usbotg",
1679 .sysc = &omap3xxx_usbhsotg_sysc,
1680 };
1681
1682 /* usb_otg_hs */
1683 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
1684
1685 { .name = "mc", .irq = 92 + OMAP_INTC_START, },
1686 { .name = "dma", .irq = 93 + OMAP_INTC_START, },
1687 { .irq = -1 },
1688 };
1689
1690 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1691 .name = "usb_otg_hs",
1692 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
1693 .main_clk = "hsotgusb_ick",
1694 .prcm = {
1695 .omap2 = {
1696 .prcm_reg_id = 1,
1697 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1698 .module_offs = CORE_MOD,
1699 .idlest_reg_id = 1,
1700 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1701 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
1702 },
1703 },
1704 .class = &usbotg_class,
1705
1706 /*
1707 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
1708 * broken when autoidle is enabled
1709 * workaround is to disable the autoidle bit at module level.
1710 */
1711 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
1712 | HWMOD_SWSUP_MSTANDBY,
1713 };
1714
1715 /* usb_otg_hs */
1716 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
1717 { .name = "mc", .irq = 71 + OMAP_INTC_START, },
1718 { .irq = -1 },
1719 };
1720
1721 static struct omap_hwmod_class am35xx_usbotg_class = {
1722 .name = "am35xx_usbotg",
1723 };
1724
1725 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1726 .name = "am35x_otg_hs",
1727 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
1728 .main_clk = "hsotgusb_fck",
1729 .class = &am35xx_usbotg_class,
1730 .flags = HWMOD_NO_IDLEST,
1731 };
1732
1733 /* MMC/SD/SDIO common */
1734 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1735 .rev_offs = 0x1fc,
1736 .sysc_offs = 0x10,
1737 .syss_offs = 0x14,
1738 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1739 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1740 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1741 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1742 .sysc_fields = &omap_hwmod_sysc_type1,
1743 };
1744
1745 static struct omap_hwmod_class omap34xx_mmc_class = {
1746 .name = "mmc",
1747 .sysc = &omap34xx_mmc_sysc,
1748 };
1749
1750 /* MMC/SD/SDIO1 */
1751
1752 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
1753 { .irq = 83 + OMAP_INTC_START, },
1754 { .irq = -1 },
1755 };
1756
1757 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
1758 { .name = "tx", .dma_req = 61, },
1759 { .name = "rx", .dma_req = 62, },
1760 { .dma_req = -1 }
1761 };
1762
1763 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1764 { .role = "dbck", .clk = "omap_32k_fck", },
1765 };
1766
1767 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1768 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1769 };
1770
1771 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1772 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
1773 .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1774 OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1775 };
1776
1777 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1778 .name = "mmc1",
1779 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
1780 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
1781 .opt_clks = omap34xx_mmc1_opt_clks,
1782 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1783 .main_clk = "mmchs1_fck",
1784 .prcm = {
1785 .omap2 = {
1786 .module_offs = CORE_MOD,
1787 .prcm_reg_id = 1,
1788 .module_bit = OMAP3430_EN_MMC1_SHIFT,
1789 .idlest_reg_id = 1,
1790 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1791 },
1792 },
1793 .dev_attr = &mmc1_pre_es3_dev_attr,
1794 .class = &omap34xx_mmc_class,
1795 };
1796
1797 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1798 .name = "mmc1",
1799 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
1800 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
1801 .opt_clks = omap34xx_mmc1_opt_clks,
1802 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1803 .main_clk = "mmchs1_fck",
1804 .prcm = {
1805 .omap2 = {
1806 .module_offs = CORE_MOD,
1807 .prcm_reg_id = 1,
1808 .module_bit = OMAP3430_EN_MMC1_SHIFT,
1809 .idlest_reg_id = 1,
1810 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1811 },
1812 },
1813 .dev_attr = &mmc1_dev_attr,
1814 .class = &omap34xx_mmc_class,
1815 };
1816
1817 /* MMC/SD/SDIO2 */
1818
1819 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
1820 { .irq = 86 + OMAP_INTC_START, },
1821 { .irq = -1 },
1822 };
1823
1824 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
1825 { .name = "tx", .dma_req = 47, },
1826 { .name = "rx", .dma_req = 48, },
1827 { .dma_req = -1 }
1828 };
1829
1830 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1831 { .role = "dbck", .clk = "omap_32k_fck", },
1832 };
1833
1834 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1835 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
1836 .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1837 };
1838
1839 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1840 .name = "mmc2",
1841 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
1842 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
1843 .opt_clks = omap34xx_mmc2_opt_clks,
1844 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1845 .main_clk = "mmchs2_fck",
1846 .prcm = {
1847 .omap2 = {
1848 .module_offs = CORE_MOD,
1849 .prcm_reg_id = 1,
1850 .module_bit = OMAP3430_EN_MMC2_SHIFT,
1851 .idlest_reg_id = 1,
1852 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1853 },
1854 },
1855 .dev_attr = &mmc2_pre_es3_dev_attr,
1856 .class = &omap34xx_mmc_class,
1857 };
1858
1859 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1860 .name = "mmc2",
1861 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
1862 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
1863 .opt_clks = omap34xx_mmc2_opt_clks,
1864 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1865 .main_clk = "mmchs2_fck",
1866 .prcm = {
1867 .omap2 = {
1868 .module_offs = CORE_MOD,
1869 .prcm_reg_id = 1,
1870 .module_bit = OMAP3430_EN_MMC2_SHIFT,
1871 .idlest_reg_id = 1,
1872 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1873 },
1874 },
1875 .class = &omap34xx_mmc_class,
1876 };
1877
1878 /* MMC/SD/SDIO3 */
1879
1880 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
1881 { .irq = 94 + OMAP_INTC_START, },
1882 { .irq = -1 },
1883 };
1884
1885 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
1886 { .name = "tx", .dma_req = 77, },
1887 { .name = "rx", .dma_req = 78, },
1888 { .dma_req = -1 }
1889 };
1890
1891 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1892 { .role = "dbck", .clk = "omap_32k_fck", },
1893 };
1894
1895 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1896 .name = "mmc3",
1897 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
1898 .sdma_reqs = omap34xx_mmc3_sdma_reqs,
1899 .opt_clks = omap34xx_mmc3_opt_clks,
1900 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1901 .main_clk = "mmchs3_fck",
1902 .prcm = {
1903 .omap2 = {
1904 .prcm_reg_id = 1,
1905 .module_bit = OMAP3430_EN_MMC3_SHIFT,
1906 .idlest_reg_id = 1,
1907 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1908 },
1909 },
1910 .class = &omap34xx_mmc_class,
1911 };
1912
1913 /*
1914 * 'usb_host_hs' class
1915 * high-speed multi-port usb host controller
1916 */
1917
1918 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1919 .rev_offs = 0x0000,
1920 .sysc_offs = 0x0010,
1921 .syss_offs = 0x0014,
1922 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1923 SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1924 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1925 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1926 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1927 .sysc_fields = &omap_hwmod_sysc_type1,
1928 };
1929
1930 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1931 .name = "usb_host_hs",
1932 .sysc = &omap3xxx_usb_host_hs_sysc,
1933 };
1934
1935 static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
1936 { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
1937 };
1938
1939 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
1940 { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, },
1941 { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, },
1942 { .irq = -1 },
1943 };
1944
1945 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1946 .name = "usb_host_hs",
1947 .class = &omap3xxx_usb_host_hs_hwmod_class,
1948 .clkdm_name = "l3_init_clkdm",
1949 .mpu_irqs = omap3xxx_usb_host_hs_irqs,
1950 .main_clk = "usbhost_48m_fck",
1951 .prcm = {
1952 .omap2 = {
1953 .module_offs = OMAP3430ES2_USBHOST_MOD,
1954 .prcm_reg_id = 1,
1955 .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
1956 .idlest_reg_id = 1,
1957 .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1958 .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
1959 },
1960 },
1961 .opt_clks = omap3xxx_usb_host_hs_opt_clks,
1962 .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
1963
1964 /*
1965 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1966 * id: i660
1967 *
1968 * Description:
1969 * In the following configuration :
1970 * - USBHOST module is set to smart-idle mode
1971 * - PRCM asserts idle_req to the USBHOST module ( This typically
1972 * happens when the system is going to a low power mode : all ports
1973 * have been suspended, the master part of the USBHOST module has
1974 * entered the standby state, and SW has cut the functional clocks)
1975 * - an USBHOST interrupt occurs before the module is able to answer
1976 * idle_ack, typically a remote wakeup IRQ.
1977 * Then the USB HOST module will enter a deadlock situation where it
1978 * is no more accessible nor functional.
1979 *
1980 * Workaround:
1981 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1982 */
1983
1984 /*
1985 * Errata: USB host EHCI may stall when entering smart-standby mode
1986 * Id: i571
1987 *
1988 * Description:
1989 * When the USBHOST module is set to smart-standby mode, and when it is
1990 * ready to enter the standby state (i.e. all ports are suspended and
1991 * all attached devices are in suspend mode), then it can wrongly assert
1992 * the Mstandby signal too early while there are still some residual OCP
1993 * transactions ongoing. If this condition occurs, the internal state
1994 * machine may go to an undefined state and the USB link may be stuck
1995 * upon the next resume.
1996 *
1997 * Workaround:
1998 * Don't use smart standby; use only force standby,
1999 * hence HWMOD_SWSUP_MSTANDBY
2000 */
2001
2002 /*
2003 * During system boot; If the hwmod framework resets the module
2004 * the module will have smart idle settings; which can lead to deadlock
2005 * (above Errata Id:i660); so, dont reset the module during boot;
2006 * Use HWMOD_INIT_NO_RESET.
2007 */
2008
2009 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
2010 HWMOD_INIT_NO_RESET,
2011 };
2012
2013 /*
2014 * 'usb_tll_hs' class
2015 * usb_tll_hs module is the adapter on the usb_host_hs ports
2016 */
2017 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
2018 .rev_offs = 0x0000,
2019 .sysc_offs = 0x0010,
2020 .syss_offs = 0x0014,
2021 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2022 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2023 SYSC_HAS_AUTOIDLE),
2024 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2025 .sysc_fields = &omap_hwmod_sysc_type1,
2026 };
2027
2028 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
2029 .name = "usb_tll_hs",
2030 .sysc = &omap3xxx_usb_tll_hs_sysc,
2031 };
2032
2033 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
2034 { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, },
2035 { .irq = -1 },
2036 };
2037
2038 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
2039 .name = "usb_tll_hs",
2040 .class = &omap3xxx_usb_tll_hs_hwmod_class,
2041 .clkdm_name = "l3_init_clkdm",
2042 .mpu_irqs = omap3xxx_usb_tll_hs_irqs,
2043 .main_clk = "usbtll_fck",
2044 .prcm = {
2045 .omap2 = {
2046 .module_offs = CORE_MOD,
2047 .prcm_reg_id = 3,
2048 .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
2049 .idlest_reg_id = 3,
2050 .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
2051 },
2052 },
2053 };
2054
2055 static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
2056 .name = "hdq1w",
2057 .mpu_irqs = omap2_hdq1w_mpu_irqs,
2058 .main_clk = "hdq_fck",
2059 .prcm = {
2060 .omap2 = {
2061 .module_offs = CORE_MOD,
2062 .prcm_reg_id = 1,
2063 .module_bit = OMAP3430_EN_HDQ_SHIFT,
2064 .idlest_reg_id = 1,
2065 .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
2066 },
2067 },
2068 .class = &omap2_hdq1w_class,
2069 };
2070
2071 /* SAD2D */
2072 static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = {
2073 { .name = "rst_modem_pwron_sw", .rst_shift = 0 },
2074 { .name = "rst_modem_sw", .rst_shift = 1 },
2075 };
2076
2077 static struct omap_hwmod_class omap3xxx_sad2d_class = {
2078 .name = "sad2d",
2079 };
2080
2081 static struct omap_hwmod omap3xxx_sad2d_hwmod = {
2082 .name = "sad2d",
2083 .rst_lines = omap3xxx_sad2d_resets,
2084 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_sad2d_resets),
2085 .main_clk = "sad2d_ick",
2086 .prcm = {
2087 .omap2 = {
2088 .module_offs = CORE_MOD,
2089 .prcm_reg_id = 1,
2090 .module_bit = OMAP3430_EN_SAD2D_SHIFT,
2091 .idlest_reg_id = 1,
2092 .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT,
2093 },
2094 },
2095 .class = &omap3xxx_sad2d_class,
2096 };
2097
2098 /*
2099 * '32K sync counter' class
2100 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
2101 */
2102 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
2103 .rev_offs = 0x0000,
2104 .sysc_offs = 0x0004,
2105 .sysc_flags = SYSC_HAS_SIDLEMODE,
2106 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
2107 .sysc_fields = &omap_hwmod_sysc_type1,
2108 };
2109
2110 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
2111 .name = "counter",
2112 .sysc = &omap3xxx_counter_sysc,
2113 };
2114
2115 static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
2116 .name = "counter_32k",
2117 .class = &omap3xxx_counter_hwmod_class,
2118 .clkdm_name = "wkup_clkdm",
2119 .flags = HWMOD_SWSUP_SIDLE,
2120 .main_clk = "wkup_32k_fck",
2121 .prcm = {
2122 .omap2 = {
2123 .module_offs = WKUP_MOD,
2124 .prcm_reg_id = 1,
2125 .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
2126 .idlest_reg_id = 1,
2127 .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
2128 },
2129 },
2130 };
2131
2132 /*
2133 * 'gpmc' class
2134 * general purpose memory controller
2135 */
2136
2137 static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
2138 .rev_offs = 0x0000,
2139 .sysc_offs = 0x0010,
2140 .syss_offs = 0x0014,
2141 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2142 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2143 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2144 .sysc_fields = &omap_hwmod_sysc_type1,
2145 };
2146
2147 static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
2148 .name = "gpmc",
2149 .sysc = &omap3xxx_gpmc_sysc,
2150 };
2151
2152 static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = {
2153 { .irq = 20 },
2154 { .irq = -1 }
2155 };
2156
2157 static struct omap_hwmod omap3xxx_gpmc_hwmod = {
2158 .name = "gpmc",
2159 .class = &omap3xxx_gpmc_hwmod_class,
2160 .clkdm_name = "core_l3_clkdm",
2161 .mpu_irqs = omap3xxx_gpmc_irqs,
2162 .main_clk = "gpmc_fck",
2163 /*
2164 * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
2165 * block. It is not being added due to any known bugs with
2166 * resetting the GPMC IP block, but rather because any timings
2167 * set by the bootloader are not being correctly programmed by
2168 * the kernel from the board file or DT data.
2169 * HWMOD_INIT_NO_RESET should be removed ASAP.
2170 */
2171 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
2172 HWMOD_NO_IDLEST),
2173 };
2174
2175 /*
2176 * interfaces
2177 */
2178
2179 /* L3 -> L4_CORE interface */
2180 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
2181 .master = &omap3xxx_l3_main_hwmod,
2182 .slave = &omap3xxx_l4_core_hwmod,
2183 .user = OCP_USER_MPU | OCP_USER_SDMA,
2184 };
2185
2186 /* L3 -> L4_PER interface */
2187 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
2188 .master = &omap3xxx_l3_main_hwmod,
2189 .slave = &omap3xxx_l4_per_hwmod,
2190 .user = OCP_USER_MPU | OCP_USER_SDMA,
2191 };
2192
2193 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
2194 {
2195 .pa_start = 0x68000000,
2196 .pa_end = 0x6800ffff,
2197 .flags = ADDR_TYPE_RT,
2198 },
2199 { }
2200 };
2201
2202 /* MPU -> L3 interface */
2203 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
2204 .master = &omap3xxx_mpu_hwmod,
2205 .slave = &omap3xxx_l3_main_hwmod,
2206 .addr = omap3xxx_l3_main_addrs,
2207 .user = OCP_USER_MPU,
2208 };
2209
2210 static struct omap_hwmod_addr_space omap3xxx_l4_emu_addrs[] = {
2211 {
2212 .pa_start = 0x54000000,
2213 .pa_end = 0x547fffff,
2214 .flags = ADDR_TYPE_RT,
2215 },
2216 { }
2217 };
2218
2219 /* l3 -> debugss */
2220 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = {
2221 .master = &omap3xxx_l3_main_hwmod,
2222 .slave = &omap3xxx_debugss_hwmod,
2223 .addr = omap3xxx_l4_emu_addrs,
2224 .user = OCP_USER_MPU,
2225 };
2226
2227 /* DSS -> l3 */
2228 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
2229 .master = &omap3430es1_dss_core_hwmod,
2230 .slave = &omap3xxx_l3_main_hwmod,
2231 .user = OCP_USER_MPU | OCP_USER_SDMA,
2232 };
2233
2234 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
2235 .master = &omap3xxx_dss_core_hwmod,
2236 .slave = &omap3xxx_l3_main_hwmod,
2237 .fw = {
2238 .omap2 = {
2239 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
2240 .flags = OMAP_FIREWALL_L3,
2241 }
2242 },
2243 .user = OCP_USER_MPU | OCP_USER_SDMA,
2244 };
2245
2246 /* l3_core -> usbhsotg interface */
2247 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
2248 .master = &omap3xxx_usbhsotg_hwmod,
2249 .slave = &omap3xxx_l3_main_hwmod,
2250 .clk = "core_l3_ick",
2251 .user = OCP_USER_MPU,
2252 };
2253
2254 /* l3_core -> am35xx_usbhsotg interface */
2255 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
2256 .master = &am35xx_usbhsotg_hwmod,
2257 .slave = &omap3xxx_l3_main_hwmod,
2258 .clk = "hsotgusb_ick",
2259 .user = OCP_USER_MPU,
2260 };
2261
2262 /* l3_core -> sad2d interface */
2263 static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = {
2264 .master = &omap3xxx_sad2d_hwmod,
2265 .slave = &omap3xxx_l3_main_hwmod,
2266 .clk = "core_l3_ick",
2267 .user = OCP_USER_MPU,
2268 };
2269
2270 /* L4_CORE -> L4_WKUP interface */
2271 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
2272 .master = &omap3xxx_l4_core_hwmod,
2273 .slave = &omap3xxx_l4_wkup_hwmod,
2274 .user = OCP_USER_MPU | OCP_USER_SDMA,
2275 };
2276
2277 /* L4 CORE -> MMC1 interface */
2278 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
2279 .master = &omap3xxx_l4_core_hwmod,
2280 .slave = &omap3xxx_pre_es3_mmc1_hwmod,
2281 .clk = "mmchs1_ick",
2282 .addr = omap2430_mmc1_addr_space,
2283 .user = OCP_USER_MPU | OCP_USER_SDMA,
2284 .flags = OMAP_FIREWALL_L4
2285 };
2286
2287 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
2288 .master = &omap3xxx_l4_core_hwmod,
2289 .slave = &omap3xxx_es3plus_mmc1_hwmod,
2290 .clk = "mmchs1_ick",
2291 .addr = omap2430_mmc1_addr_space,
2292 .user = OCP_USER_MPU | OCP_USER_SDMA,
2293 .flags = OMAP_FIREWALL_L4
2294 };
2295
2296 /* L4 CORE -> MMC2 interface */
2297 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
2298 .master = &omap3xxx_l4_core_hwmod,
2299 .slave = &omap3xxx_pre_es3_mmc2_hwmod,
2300 .clk = "mmchs2_ick",
2301 .addr = omap2430_mmc2_addr_space,
2302 .user = OCP_USER_MPU | OCP_USER_SDMA,
2303 .flags = OMAP_FIREWALL_L4
2304 };
2305
2306 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2307 .master = &omap3xxx_l4_core_hwmod,
2308 .slave = &omap3xxx_es3plus_mmc2_hwmod,
2309 .clk = "mmchs2_ick",
2310 .addr = omap2430_mmc2_addr_space,
2311 .user = OCP_USER_MPU | OCP_USER_SDMA,
2312 .flags = OMAP_FIREWALL_L4
2313 };
2314
2315 /* L4 CORE -> MMC3 interface */
2316 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
2317 {
2318 .pa_start = 0x480ad000,
2319 .pa_end = 0x480ad1ff,
2320 .flags = ADDR_TYPE_RT,
2321 },
2322 { }
2323 };
2324
2325 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2326 .master = &omap3xxx_l4_core_hwmod,
2327 .slave = &omap3xxx_mmc3_hwmod,
2328 .clk = "mmchs3_ick",
2329 .addr = omap3xxx_mmc3_addr_space,
2330 .user = OCP_USER_MPU | OCP_USER_SDMA,
2331 .flags = OMAP_FIREWALL_L4
2332 };
2333
2334 /* L4 CORE -> UART1 interface */
2335 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
2336 {
2337 .pa_start = OMAP3_UART1_BASE,
2338 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
2339 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2340 },
2341 { }
2342 };
2343
2344 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2345 .master = &omap3xxx_l4_core_hwmod,
2346 .slave = &omap3xxx_uart1_hwmod,
2347 .clk = "uart1_ick",
2348 .addr = omap3xxx_uart1_addr_space,
2349 .user = OCP_USER_MPU | OCP_USER_SDMA,
2350 };
2351
2352 /* L4 CORE -> UART2 interface */
2353 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
2354 {
2355 .pa_start = OMAP3_UART2_BASE,
2356 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
2357 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2358 },
2359 { }
2360 };
2361
2362 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2363 .master = &omap3xxx_l4_core_hwmod,
2364 .slave = &omap3xxx_uart2_hwmod,
2365 .clk = "uart2_ick",
2366 .addr = omap3xxx_uart2_addr_space,
2367 .user = OCP_USER_MPU | OCP_USER_SDMA,
2368 };
2369
2370 /* L4 PER -> UART3 interface */
2371 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
2372 {
2373 .pa_start = OMAP3_UART3_BASE,
2374 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
2375 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2376 },
2377 { }
2378 };
2379
2380 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2381 .master = &omap3xxx_l4_per_hwmod,
2382 .slave = &omap3xxx_uart3_hwmod,
2383 .clk = "uart3_ick",
2384 .addr = omap3xxx_uart3_addr_space,
2385 .user = OCP_USER_MPU | OCP_USER_SDMA,
2386 };
2387
2388 /* L4 PER -> UART4 interface */
2389 static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
2390 {
2391 .pa_start = OMAP3_UART4_BASE,
2392 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
2393 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2394 },
2395 { }
2396 };
2397
2398 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2399 .master = &omap3xxx_l4_per_hwmod,
2400 .slave = &omap36xx_uart4_hwmod,
2401 .clk = "uart4_ick",
2402 .addr = omap36xx_uart4_addr_space,
2403 .user = OCP_USER_MPU | OCP_USER_SDMA,
2404 };
2405
2406 /* AM35xx: L4 CORE -> UART4 interface */
2407 static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
2408 {
2409 .pa_start = OMAP3_UART4_AM35XX_BASE,
2410 .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
2411 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2412 },
2413 { }
2414 };
2415
2416 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2417 .master = &omap3xxx_l4_core_hwmod,
2418 .slave = &am35xx_uart4_hwmod,
2419 .clk = "uart4_ick",
2420 .addr = am35xx_uart4_addr_space,
2421 .user = OCP_USER_MPU | OCP_USER_SDMA,
2422 };
2423
2424 /* L4 CORE -> I2C1 interface */
2425 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2426 .master = &omap3xxx_l4_core_hwmod,
2427 .slave = &omap3xxx_i2c1_hwmod,
2428 .clk = "i2c1_ick",
2429 .addr = omap2_i2c1_addr_space,
2430 .fw = {
2431 .omap2 = {
2432 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
2433 .l4_prot_group = 7,
2434 .flags = OMAP_FIREWALL_L4,
2435 }
2436 },
2437 .user = OCP_USER_MPU | OCP_USER_SDMA,
2438 };
2439
2440 /* L4 CORE -> I2C2 interface */
2441 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2442 .master = &omap3xxx_l4_core_hwmod,
2443 .slave = &omap3xxx_i2c2_hwmod,
2444 .clk = "i2c2_ick",
2445 .addr = omap2_i2c2_addr_space,
2446 .fw = {
2447 .omap2 = {
2448 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
2449 .l4_prot_group = 7,
2450 .flags = OMAP_FIREWALL_L4,
2451 }
2452 },
2453 .user = OCP_USER_MPU | OCP_USER_SDMA,
2454 };
2455
2456 /* L4 CORE -> I2C3 interface */
2457 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
2458 {
2459 .pa_start = 0x48060000,
2460 .pa_end = 0x48060000 + SZ_128 - 1,
2461 .flags = ADDR_TYPE_RT,
2462 },
2463 { }
2464 };
2465
2466 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2467 .master = &omap3xxx_l4_core_hwmod,
2468 .slave = &omap3xxx_i2c3_hwmod,
2469 .clk = "i2c3_ick",
2470 .addr = omap3xxx_i2c3_addr_space,
2471 .fw = {
2472 .omap2 = {
2473 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
2474 .l4_prot_group = 7,
2475 .flags = OMAP_FIREWALL_L4,
2476 }
2477 },
2478 .user = OCP_USER_MPU | OCP_USER_SDMA,
2479 };
2480
2481 /* L4 CORE -> SR1 interface */
2482 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
2483 {
2484 .pa_start = OMAP34XX_SR1_BASE,
2485 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
2486 .flags = ADDR_TYPE_RT,
2487 },
2488 { }
2489 };
2490
2491 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2492 .master = &omap3xxx_l4_core_hwmod,
2493 .slave = &omap34xx_sr1_hwmod,
2494 .clk = "sr_l4_ick",
2495 .addr = omap3_sr1_addr_space,
2496 .user = OCP_USER_MPU,
2497 };
2498
2499 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2500 .master = &omap3xxx_l4_core_hwmod,
2501 .slave = &omap36xx_sr1_hwmod,
2502 .clk = "sr_l4_ick",
2503 .addr = omap3_sr1_addr_space,
2504 .user = OCP_USER_MPU,
2505 };
2506
2507 /* L4 CORE -> SR1 interface */
2508 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
2509 {
2510 .pa_start = OMAP34XX_SR2_BASE,
2511 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
2512 .flags = ADDR_TYPE_RT,
2513 },
2514 { }
2515 };
2516
2517 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2518 .master = &omap3xxx_l4_core_hwmod,
2519 .slave = &omap34xx_sr2_hwmod,
2520 .clk = "sr_l4_ick",
2521 .addr = omap3_sr2_addr_space,
2522 .user = OCP_USER_MPU,
2523 };
2524
2525 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2526 .master = &omap3xxx_l4_core_hwmod,
2527 .slave = &omap36xx_sr2_hwmod,
2528 .clk = "sr_l4_ick",
2529 .addr = omap3_sr2_addr_space,
2530 .user = OCP_USER_MPU,
2531 };
2532
2533 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
2534 {
2535 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
2536 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
2537 .flags = ADDR_TYPE_RT
2538 },
2539 { }
2540 };
2541
2542 /* l4_core -> usbhsotg */
2543 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2544 .master = &omap3xxx_l4_core_hwmod,
2545 .slave = &omap3xxx_usbhsotg_hwmod,
2546 .clk = "l4_ick",
2547 .addr = omap3xxx_usbhsotg_addrs,
2548 .user = OCP_USER_MPU,
2549 };
2550
2551 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
2552 {
2553 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
2554 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
2555 .flags = ADDR_TYPE_RT
2556 },
2557 { }
2558 };
2559
2560 /* l4_core -> usbhsotg */
2561 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2562 .master = &omap3xxx_l4_core_hwmod,
2563 .slave = &am35xx_usbhsotg_hwmod,
2564 .clk = "hsotgusb_ick",
2565 .addr = am35xx_usbhsotg_addrs,
2566 .user = OCP_USER_MPU,
2567 };
2568
2569 /* L4_WKUP -> L4_SEC interface */
2570 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2571 .master = &omap3xxx_l4_wkup_hwmod,
2572 .slave = &omap3xxx_l4_sec_hwmod,
2573 .user = OCP_USER_MPU | OCP_USER_SDMA,
2574 };
2575
2576 /* IVA2 <- L3 interface */
2577 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2578 .master = &omap3xxx_l3_main_hwmod,
2579 .slave = &omap3xxx_iva_hwmod,
2580 .clk = "core_l3_ick",
2581 .user = OCP_USER_MPU | OCP_USER_SDMA,
2582 };
2583
2584 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
2585 {
2586 .pa_start = 0x48318000,
2587 .pa_end = 0x48318000 + SZ_1K - 1,
2588 .flags = ADDR_TYPE_RT
2589 },
2590 { }
2591 };
2592
2593 /* l4_wkup -> timer1 */
2594 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2595 .master = &omap3xxx_l4_wkup_hwmod,
2596 .slave = &omap3xxx_timer1_hwmod,
2597 .clk = "gpt1_ick",
2598 .addr = omap3xxx_timer1_addrs,
2599 .user = OCP_USER_MPU | OCP_USER_SDMA,
2600 };
2601
2602 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
2603 {
2604 .pa_start = 0x49032000,
2605 .pa_end = 0x49032000 + SZ_1K - 1,
2606 .flags = ADDR_TYPE_RT
2607 },
2608 { }
2609 };
2610
2611 /* l4_per -> timer2 */
2612 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2613 .master = &omap3xxx_l4_per_hwmod,
2614 .slave = &omap3xxx_timer2_hwmod,
2615 .clk = "gpt2_ick",
2616 .addr = omap3xxx_timer2_addrs,
2617 .user = OCP_USER_MPU | OCP_USER_SDMA,
2618 };
2619
2620 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
2621 {
2622 .pa_start = 0x49034000,
2623 .pa_end = 0x49034000 + SZ_1K - 1,
2624 .flags = ADDR_TYPE_RT
2625 },
2626 { }
2627 };
2628
2629 /* l4_per -> timer3 */
2630 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2631 .master = &omap3xxx_l4_per_hwmod,
2632 .slave = &omap3xxx_timer3_hwmod,
2633 .clk = "gpt3_ick",
2634 .addr = omap3xxx_timer3_addrs,
2635 .user = OCP_USER_MPU | OCP_USER_SDMA,
2636 };
2637
2638 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
2639 {
2640 .pa_start = 0x49036000,
2641 .pa_end = 0x49036000 + SZ_1K - 1,
2642 .flags = ADDR_TYPE_RT
2643 },
2644 { }
2645 };
2646
2647 /* l4_per -> timer4 */
2648 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2649 .master = &omap3xxx_l4_per_hwmod,
2650 .slave = &omap3xxx_timer4_hwmod,
2651 .clk = "gpt4_ick",
2652 .addr = omap3xxx_timer4_addrs,
2653 .user = OCP_USER_MPU | OCP_USER_SDMA,
2654 };
2655
2656 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
2657 {
2658 .pa_start = 0x49038000,
2659 .pa_end = 0x49038000 + SZ_1K - 1,
2660 .flags = ADDR_TYPE_RT
2661 },
2662 { }
2663 };
2664
2665 /* l4_per -> timer5 */
2666 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2667 .master = &omap3xxx_l4_per_hwmod,
2668 .slave = &omap3xxx_timer5_hwmod,
2669 .clk = "gpt5_ick",
2670 .addr = omap3xxx_timer5_addrs,
2671 .user = OCP_USER_MPU | OCP_USER_SDMA,
2672 };
2673
2674 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
2675 {
2676 .pa_start = 0x4903A000,
2677 .pa_end = 0x4903A000 + SZ_1K - 1,
2678 .flags = ADDR_TYPE_RT
2679 },
2680 { }
2681 };
2682
2683 /* l4_per -> timer6 */
2684 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2685 .master = &omap3xxx_l4_per_hwmod,
2686 .slave = &omap3xxx_timer6_hwmod,
2687 .clk = "gpt6_ick",
2688 .addr = omap3xxx_timer6_addrs,
2689 .user = OCP_USER_MPU | OCP_USER_SDMA,
2690 };
2691
2692 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
2693 {
2694 .pa_start = 0x4903C000,
2695 .pa_end = 0x4903C000 + SZ_1K - 1,
2696 .flags = ADDR_TYPE_RT
2697 },
2698 { }
2699 };
2700
2701 /* l4_per -> timer7 */
2702 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2703 .master = &omap3xxx_l4_per_hwmod,
2704 .slave = &omap3xxx_timer7_hwmod,
2705 .clk = "gpt7_ick",
2706 .addr = omap3xxx_timer7_addrs,
2707 .user = OCP_USER_MPU | OCP_USER_SDMA,
2708 };
2709
2710 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
2711 {
2712 .pa_start = 0x4903E000,
2713 .pa_end = 0x4903E000 + SZ_1K - 1,
2714 .flags = ADDR_TYPE_RT
2715 },
2716 { }
2717 };
2718
2719 /* l4_per -> timer8 */
2720 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2721 .master = &omap3xxx_l4_per_hwmod,
2722 .slave = &omap3xxx_timer8_hwmod,
2723 .clk = "gpt8_ick",
2724 .addr = omap3xxx_timer8_addrs,
2725 .user = OCP_USER_MPU | OCP_USER_SDMA,
2726 };
2727
2728 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
2729 {
2730 .pa_start = 0x49040000,
2731 .pa_end = 0x49040000 + SZ_1K - 1,
2732 .flags = ADDR_TYPE_RT
2733 },
2734 { }
2735 };
2736
2737 /* l4_per -> timer9 */
2738 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2739 .master = &omap3xxx_l4_per_hwmod,
2740 .slave = &omap3xxx_timer9_hwmod,
2741 .clk = "gpt9_ick",
2742 .addr = omap3xxx_timer9_addrs,
2743 .user = OCP_USER_MPU | OCP_USER_SDMA,
2744 };
2745
2746 /* l4_core -> timer10 */
2747 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2748 .master = &omap3xxx_l4_core_hwmod,
2749 .slave = &omap3xxx_timer10_hwmod,
2750 .clk = "gpt10_ick",
2751 .addr = omap2_timer10_addrs,
2752 .user = OCP_USER_MPU | OCP_USER_SDMA,
2753 };
2754
2755 /* l4_core -> timer11 */
2756 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2757 .master = &omap3xxx_l4_core_hwmod,
2758 .slave = &omap3xxx_timer11_hwmod,
2759 .clk = "gpt11_ick",
2760 .addr = omap2_timer11_addrs,
2761 .user = OCP_USER_MPU | OCP_USER_SDMA,
2762 };
2763
2764 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
2765 {
2766 .pa_start = 0x48304000,
2767 .pa_end = 0x48304000 + SZ_1K - 1,
2768 .flags = ADDR_TYPE_RT
2769 },
2770 { }
2771 };
2772
2773 /* l4_core -> timer12 */
2774 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2775 .master = &omap3xxx_l4_sec_hwmod,
2776 .slave = &omap3xxx_timer12_hwmod,
2777 .clk = "gpt12_ick",
2778 .addr = omap3xxx_timer12_addrs,
2779 .user = OCP_USER_MPU | OCP_USER_SDMA,
2780 };
2781
2782 /* l4_wkup -> wd_timer2 */
2783 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
2784 {
2785 .pa_start = 0x48314000,
2786 .pa_end = 0x4831407f,
2787 .flags = ADDR_TYPE_RT
2788 },
2789 { }
2790 };
2791
2792 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2793 .master = &omap3xxx_l4_wkup_hwmod,
2794 .slave = &omap3xxx_wd_timer2_hwmod,
2795 .clk = "wdt2_ick",
2796 .addr = omap3xxx_wd_timer2_addrs,
2797 .user = OCP_USER_MPU | OCP_USER_SDMA,
2798 };
2799
2800 /* l4_core -> dss */
2801 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2802 .master = &omap3xxx_l4_core_hwmod,
2803 .slave = &omap3430es1_dss_core_hwmod,
2804 .clk = "dss_ick",
2805 .addr = omap2_dss_addrs,
2806 .fw = {
2807 .omap2 = {
2808 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2809 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2810 .flags = OMAP_FIREWALL_L4,
2811 }
2812 },
2813 .user = OCP_USER_MPU | OCP_USER_SDMA,
2814 };
2815
2816 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2817 .master = &omap3xxx_l4_core_hwmod,
2818 .slave = &omap3xxx_dss_core_hwmod,
2819 .clk = "dss_ick",
2820 .addr = omap2_dss_addrs,
2821 .fw = {
2822 .omap2 = {
2823 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2824 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2825 .flags = OMAP_FIREWALL_L4,
2826 }
2827 },
2828 .user = OCP_USER_MPU | OCP_USER_SDMA,
2829 };
2830
2831 /* l4_core -> dss_dispc */
2832 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2833 .master = &omap3xxx_l4_core_hwmod,
2834 .slave = &omap3xxx_dss_dispc_hwmod,
2835 .clk = "dss_ick",
2836 .addr = omap2_dss_dispc_addrs,
2837 .fw = {
2838 .omap2 = {
2839 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2840 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2841 .flags = OMAP_FIREWALL_L4,
2842 }
2843 },
2844 .user = OCP_USER_MPU | OCP_USER_SDMA,
2845 };
2846
2847 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
2848 {
2849 .pa_start = 0x4804FC00,
2850 .pa_end = 0x4804FFFF,
2851 .flags = ADDR_TYPE_RT
2852 },
2853 { }
2854 };
2855
2856 /* l4_core -> dss_dsi1 */
2857 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2858 .master = &omap3xxx_l4_core_hwmod,
2859 .slave = &omap3xxx_dss_dsi1_hwmod,
2860 .clk = "dss_ick",
2861 .addr = omap3xxx_dss_dsi1_addrs,
2862 .fw = {
2863 .omap2 = {
2864 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2865 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2866 .flags = OMAP_FIREWALL_L4,
2867 }
2868 },
2869 .user = OCP_USER_MPU | OCP_USER_SDMA,
2870 };
2871
2872 /* l4_core -> dss_rfbi */
2873 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2874 .master = &omap3xxx_l4_core_hwmod,
2875 .slave = &omap3xxx_dss_rfbi_hwmod,
2876 .clk = "dss_ick",
2877 .addr = omap2_dss_rfbi_addrs,
2878 .fw = {
2879 .omap2 = {
2880 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2881 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2882 .flags = OMAP_FIREWALL_L4,
2883 }
2884 },
2885 .user = OCP_USER_MPU | OCP_USER_SDMA,
2886 };
2887
2888 /* l4_core -> dss_venc */
2889 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2890 .master = &omap3xxx_l4_core_hwmod,
2891 .slave = &omap3xxx_dss_venc_hwmod,
2892 .clk = "dss_ick",
2893 .addr = omap2_dss_venc_addrs,
2894 .fw = {
2895 .omap2 = {
2896 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2897 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2898 .flags = OMAP_FIREWALL_L4,
2899 }
2900 },
2901 .flags = OCPIF_SWSUP_IDLE,
2902 .user = OCP_USER_MPU | OCP_USER_SDMA,
2903 };
2904
2905 /* l4_wkup -> gpio1 */
2906 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2907 {
2908 .pa_start = 0x48310000,
2909 .pa_end = 0x483101ff,
2910 .flags = ADDR_TYPE_RT
2911 },
2912 { }
2913 };
2914
2915 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2916 .master = &omap3xxx_l4_wkup_hwmod,
2917 .slave = &omap3xxx_gpio1_hwmod,
2918 .addr = omap3xxx_gpio1_addrs,
2919 .user = OCP_USER_MPU | OCP_USER_SDMA,
2920 };
2921
2922 /* l4_per -> gpio2 */
2923 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2924 {
2925 .pa_start = 0x49050000,
2926 .pa_end = 0x490501ff,
2927 .flags = ADDR_TYPE_RT
2928 },
2929 { }
2930 };
2931
2932 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2933 .master = &omap3xxx_l4_per_hwmod,
2934 .slave = &omap3xxx_gpio2_hwmod,
2935 .addr = omap3xxx_gpio2_addrs,
2936 .user = OCP_USER_MPU | OCP_USER_SDMA,
2937 };
2938
2939 /* l4_per -> gpio3 */
2940 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2941 {
2942 .pa_start = 0x49052000,
2943 .pa_end = 0x490521ff,
2944 .flags = ADDR_TYPE_RT
2945 },
2946 { }
2947 };
2948
2949 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2950 .master = &omap3xxx_l4_per_hwmod,
2951 .slave = &omap3xxx_gpio3_hwmod,
2952 .addr = omap3xxx_gpio3_addrs,
2953 .user = OCP_USER_MPU | OCP_USER_SDMA,
2954 };
2955
2956 /*
2957 * 'mmu' class
2958 * The memory management unit performs virtual to physical address translation
2959 * for its requestors.
2960 */
2961
2962 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2963 .rev_offs = 0x000,
2964 .sysc_offs = 0x010,
2965 .syss_offs = 0x014,
2966 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2967 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2968 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2969 .sysc_fields = &omap_hwmod_sysc_type1,
2970 };
2971
2972 static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = {
2973 .name = "mmu",
2974 .sysc = &mmu_sysc,
2975 };
2976
2977 /* mmu isp */
2978
2979 static struct omap_mmu_dev_attr mmu_isp_dev_attr = {
2980 .da_start = 0x0,
2981 .da_end = 0xfffff000,
2982 .nr_tlb_entries = 8,
2983 };
2984
2985 static struct omap_hwmod omap3xxx_mmu_isp_hwmod;
2986 static struct omap_hwmod_irq_info omap3xxx_mmu_isp_irqs[] = {
2987 { .irq = 24 },
2988 { .irq = -1 }
2989 };
2990
2991 static struct omap_hwmod_addr_space omap3xxx_mmu_isp_addrs[] = {
2992 {
2993 .pa_start = 0x480bd400,
2994 .pa_end = 0x480bd47f,
2995 .flags = ADDR_TYPE_RT,
2996 },
2997 { }
2998 };
2999
3000 /* l4_core -> mmu isp */
3001 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = {
3002 .master = &omap3xxx_l4_core_hwmod,
3003 .slave = &omap3xxx_mmu_isp_hwmod,
3004 .addr = omap3xxx_mmu_isp_addrs,
3005 .user = OCP_USER_MPU | OCP_USER_SDMA,
3006 };
3007
3008 static struct omap_hwmod omap3xxx_mmu_isp_hwmod = {
3009 .name = "mmu_isp",
3010 .class = &omap3xxx_mmu_hwmod_class,
3011 .mpu_irqs = omap3xxx_mmu_isp_irqs,
3012 .main_clk = "cam_ick",
3013 .dev_attr = &mmu_isp_dev_attr,
3014 .flags = HWMOD_NO_IDLEST,
3015 };
3016
3017 #ifdef CONFIG_OMAP_IOMMU_IVA2
3018
3019 /* mmu iva */
3020
3021 static struct omap_mmu_dev_attr mmu_iva_dev_attr = {
3022 .da_start = 0x11000000,
3023 .da_end = 0xfffff000,
3024 .nr_tlb_entries = 32,
3025 };
3026
3027 static struct omap_hwmod omap3xxx_mmu_iva_hwmod;
3028 static struct omap_hwmod_irq_info omap3xxx_mmu_iva_irqs[] = {
3029 { .irq = 28 },
3030 { .irq = -1 }
3031 };
3032
3033 static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = {
3034 { .name = "mmu", .rst_shift = 1, .st_shift = 9 },
3035 };
3036
3037 static struct omap_hwmod_addr_space omap3xxx_mmu_iva_addrs[] = {
3038 {
3039 .pa_start = 0x5d000000,
3040 .pa_end = 0x5d00007f,
3041 .flags = ADDR_TYPE_RT,
3042 },
3043 { }
3044 };
3045
3046 /* l3_main -> iva mmu */
3047 static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = {
3048 .master = &omap3xxx_l3_main_hwmod,
3049 .slave = &omap3xxx_mmu_iva_hwmod,
3050 .addr = omap3xxx_mmu_iva_addrs,
3051 .user = OCP_USER_MPU | OCP_USER_SDMA,
3052 };
3053
3054 static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
3055 .name = "mmu_iva",
3056 .class = &omap3xxx_mmu_hwmod_class,
3057 .mpu_irqs = omap3xxx_mmu_iva_irqs,
3058 .rst_lines = omap3xxx_mmu_iva_resets,
3059 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_mmu_iva_resets),
3060 .main_clk = "iva2_ck",
3061 .prcm = {
3062 .omap2 = {
3063 .module_offs = OMAP3430_IVA2_MOD,
3064 },
3065 },
3066 .dev_attr = &mmu_iva_dev_attr,
3067 .flags = HWMOD_NO_IDLEST,
3068 };
3069
3070 #endif
3071
3072 /* l4_per -> gpio4 */
3073 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
3074 {
3075 .pa_start = 0x49054000,
3076 .pa_end = 0x490541ff,
3077 .flags = ADDR_TYPE_RT
3078 },
3079 { }
3080 };
3081
3082 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
3083 .master = &omap3xxx_l4_per_hwmod,
3084 .slave = &omap3xxx_gpio4_hwmod,
3085 .addr = omap3xxx_gpio4_addrs,
3086 .user = OCP_USER_MPU | OCP_USER_SDMA,
3087 };
3088
3089 /* l4_per -> gpio5 */
3090 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
3091 {
3092 .pa_start = 0x49056000,
3093 .pa_end = 0x490561ff,
3094 .flags = ADDR_TYPE_RT
3095 },
3096 { }
3097 };
3098
3099 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
3100 .master = &omap3xxx_l4_per_hwmod,
3101 .slave = &omap3xxx_gpio5_hwmod,
3102 .addr = omap3xxx_gpio5_addrs,
3103 .user = OCP_USER_MPU | OCP_USER_SDMA,
3104 };
3105
3106 /* l4_per -> gpio6 */
3107 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
3108 {
3109 .pa_start = 0x49058000,
3110 .pa_end = 0x490581ff,
3111 .flags = ADDR_TYPE_RT
3112 },
3113 { }
3114 };
3115
3116 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
3117 .master = &omap3xxx_l4_per_hwmod,
3118 .slave = &omap3xxx_gpio6_hwmod,
3119 .addr = omap3xxx_gpio6_addrs,
3120 .user = OCP_USER_MPU | OCP_USER_SDMA,
3121 };
3122
3123 /* dma_system -> L3 */
3124 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
3125 .master = &omap3xxx_dma_system_hwmod,
3126 .slave = &omap3xxx_l3_main_hwmod,
3127 .clk = "core_l3_ick",
3128 .user = OCP_USER_MPU | OCP_USER_SDMA,
3129 };
3130
3131 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
3132 {
3133 .pa_start = 0x48056000,
3134 .pa_end = 0x48056fff,
3135 .flags = ADDR_TYPE_RT
3136 },
3137 { }
3138 };
3139
3140 /* l4_cfg -> dma_system */
3141 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
3142 .master = &omap3xxx_l4_core_hwmod,
3143 .slave = &omap3xxx_dma_system_hwmod,
3144 .clk = "core_l4_ick",
3145 .addr = omap3xxx_dma_system_addrs,
3146 .user = OCP_USER_MPU | OCP_USER_SDMA,
3147 };
3148
3149 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
3150 {
3151 .name = "mpu",
3152 .pa_start = 0x48074000,
3153 .pa_end = 0x480740ff,
3154 .flags = ADDR_TYPE_RT
3155 },
3156 { }
3157 };
3158
3159 /* l4_core -> mcbsp1 */
3160 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
3161 .master = &omap3xxx_l4_core_hwmod,
3162 .slave = &omap3xxx_mcbsp1_hwmod,
3163 .clk = "mcbsp1_ick",
3164 .addr = omap3xxx_mcbsp1_addrs,
3165 .user = OCP_USER_MPU | OCP_USER_SDMA,
3166 };
3167
3168 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
3169 {
3170 .name = "mpu",
3171 .pa_start = 0x49022000,
3172 .pa_end = 0x490220ff,
3173 .flags = ADDR_TYPE_RT
3174 },
3175 { }
3176 };
3177
3178 /* l4_per -> mcbsp2 */
3179 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
3180 .master = &omap3xxx_l4_per_hwmod,
3181 .slave = &omap3xxx_mcbsp2_hwmod,
3182 .clk = "mcbsp2_ick",
3183 .addr = omap3xxx_mcbsp2_addrs,
3184 .user = OCP_USER_MPU | OCP_USER_SDMA,
3185 };
3186
3187 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
3188 {
3189 .name = "mpu",
3190 .pa_start = 0x49024000,
3191 .pa_end = 0x490240ff,
3192 .flags = ADDR_TYPE_RT
3193 },
3194 { }
3195 };
3196
3197 /* l4_per -> mcbsp3 */
3198 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
3199 .master = &omap3xxx_l4_per_hwmod,
3200 .slave = &omap3xxx_mcbsp3_hwmod,
3201 .clk = "mcbsp3_ick",
3202 .addr = omap3xxx_mcbsp3_addrs,
3203 .user = OCP_USER_MPU | OCP_USER_SDMA,
3204 };
3205
3206 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
3207 {
3208 .name = "mpu",
3209 .pa_start = 0x49026000,
3210 .pa_end = 0x490260ff,
3211 .flags = ADDR_TYPE_RT
3212 },
3213 { }
3214 };
3215
3216 /* l4_per -> mcbsp4 */
3217 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
3218 .master = &omap3xxx_l4_per_hwmod,
3219 .slave = &omap3xxx_mcbsp4_hwmod,
3220 .clk = "mcbsp4_ick",
3221 .addr = omap3xxx_mcbsp4_addrs,
3222 .user = OCP_USER_MPU | OCP_USER_SDMA,
3223 };
3224
3225 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
3226 {
3227 .name = "mpu",
3228 .pa_start = 0x48096000,
3229 .pa_end = 0x480960ff,
3230 .flags = ADDR_TYPE_RT
3231 },
3232 { }
3233 };
3234
3235 /* l4_core -> mcbsp5 */
3236 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
3237 .master = &omap3xxx_l4_core_hwmod,
3238 .slave = &omap3xxx_mcbsp5_hwmod,
3239 .clk = "mcbsp5_ick",
3240 .addr = omap3xxx_mcbsp5_addrs,
3241 .user = OCP_USER_MPU | OCP_USER_SDMA,
3242 };
3243
3244 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
3245 {
3246 .name = "sidetone",
3247 .pa_start = 0x49028000,
3248 .pa_end = 0x490280ff,
3249 .flags = ADDR_TYPE_RT
3250 },
3251 { }
3252 };
3253
3254 /* l4_per -> mcbsp2_sidetone */
3255 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
3256 .master = &omap3xxx_l4_per_hwmod,
3257 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
3258 .clk = "mcbsp2_ick",
3259 .addr = omap3xxx_mcbsp2_sidetone_addrs,
3260 .user = OCP_USER_MPU,
3261 };
3262
3263 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
3264 {
3265 .name = "sidetone",
3266 .pa_start = 0x4902A000,
3267 .pa_end = 0x4902A0ff,
3268 .flags = ADDR_TYPE_RT
3269 },
3270 { }
3271 };
3272
3273 /* l4_per -> mcbsp3_sidetone */
3274 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
3275 .master = &omap3xxx_l4_per_hwmod,
3276 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
3277 .clk = "mcbsp3_ick",
3278 .addr = omap3xxx_mcbsp3_sidetone_addrs,
3279 .user = OCP_USER_MPU,
3280 };
3281
3282 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
3283 {
3284 .pa_start = 0x48094000,
3285 .pa_end = 0x480941ff,
3286 .flags = ADDR_TYPE_RT,
3287 },
3288 { }
3289 };
3290
3291 /* l4_core -> mailbox */
3292 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3293 .master = &omap3xxx_l4_core_hwmod,
3294 .slave = &omap3xxx_mailbox_hwmod,
3295 .addr = omap3xxx_mailbox_addrs,
3296 .user = OCP_USER_MPU | OCP_USER_SDMA,
3297 };
3298
3299 /* l4 core -> mcspi1 interface */
3300 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3301 .master = &omap3xxx_l4_core_hwmod,
3302 .slave = &omap34xx_mcspi1,
3303 .clk = "mcspi1_ick",
3304 .addr = omap2_mcspi1_addr_space,
3305 .user = OCP_USER_MPU | OCP_USER_SDMA,
3306 };
3307
3308 /* l4 core -> mcspi2 interface */
3309 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3310 .master = &omap3xxx_l4_core_hwmod,
3311 .slave = &omap34xx_mcspi2,
3312 .clk = "mcspi2_ick",
3313 .addr = omap2_mcspi2_addr_space,
3314 .user = OCP_USER_MPU | OCP_USER_SDMA,
3315 };
3316
3317 /* l4 core -> mcspi3 interface */
3318 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3319 .master = &omap3xxx_l4_core_hwmod,
3320 .slave = &omap34xx_mcspi3,
3321 .clk = "mcspi3_ick",
3322 .addr = omap2430_mcspi3_addr_space,
3323 .user = OCP_USER_MPU | OCP_USER_SDMA,
3324 };
3325
3326 /* l4 core -> mcspi4 interface */
3327 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3328 {
3329 .pa_start = 0x480ba000,
3330 .pa_end = 0x480ba0ff,
3331 .flags = ADDR_TYPE_RT,
3332 },
3333 { }
3334 };
3335
3336 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3337 .master = &omap3xxx_l4_core_hwmod,
3338 .slave = &omap34xx_mcspi4,
3339 .clk = "mcspi4_ick",
3340 .addr = omap34xx_mcspi4_addr_space,
3341 .user = OCP_USER_MPU | OCP_USER_SDMA,
3342 };
3343
3344 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3345 .master = &omap3xxx_usb_host_hs_hwmod,
3346 .slave = &omap3xxx_l3_main_hwmod,
3347 .clk = "core_l3_ick",
3348 .user = OCP_USER_MPU,
3349 };
3350
3351 static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3352 {
3353 .name = "uhh",
3354 .pa_start = 0x48064000,
3355 .pa_end = 0x480643ff,
3356 .flags = ADDR_TYPE_RT
3357 },
3358 {
3359 .name = "ohci",
3360 .pa_start = 0x48064400,
3361 .pa_end = 0x480647ff,
3362 },
3363 {
3364 .name = "ehci",
3365 .pa_start = 0x48064800,
3366 .pa_end = 0x48064cff,
3367 },
3368 {}
3369 };
3370
3371 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3372 .master = &omap3xxx_l4_core_hwmod,
3373 .slave = &omap3xxx_usb_host_hs_hwmod,
3374 .clk = "usbhost_ick",
3375 .addr = omap3xxx_usb_host_hs_addrs,
3376 .user = OCP_USER_MPU | OCP_USER_SDMA,
3377 };
3378
3379 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3380 {
3381 .name = "tll",
3382 .pa_start = 0x48062000,
3383 .pa_end = 0x48062fff,
3384 .flags = ADDR_TYPE_RT
3385 },
3386 {}
3387 };
3388
3389 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3390 .master = &omap3xxx_l4_core_hwmod,
3391 .slave = &omap3xxx_usb_tll_hs_hwmod,
3392 .clk = "usbtll_ick",
3393 .addr = omap3xxx_usb_tll_hs_addrs,
3394 .user = OCP_USER_MPU | OCP_USER_SDMA,
3395 };
3396
3397 /* l4_core -> hdq1w interface */
3398 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
3399 .master = &omap3xxx_l4_core_hwmod,
3400 .slave = &omap3xxx_hdq1w_hwmod,
3401 .clk = "hdq_ick",
3402 .addr = omap2_hdq1w_addr_space,
3403 .user = OCP_USER_MPU | OCP_USER_SDMA,
3404 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
3405 };
3406
3407 /* l4_wkup -> 32ksync_counter */
3408 static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
3409 {
3410 .pa_start = 0x48320000,
3411 .pa_end = 0x4832001f,
3412 .flags = ADDR_TYPE_RT
3413 },
3414 { }
3415 };
3416
3417 static struct omap_hwmod_addr_space omap3xxx_gpmc_addrs[] = {
3418 {
3419 .pa_start = 0x6e000000,
3420 .pa_end = 0x6e000fff,
3421 .flags = ADDR_TYPE_RT
3422 },
3423 { }
3424 };
3425
3426 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
3427 .master = &omap3xxx_l4_wkup_hwmod,
3428 .slave = &omap3xxx_counter_32k_hwmod,
3429 .clk = "omap_32ksync_ick",
3430 .addr = omap3xxx_counter_32k_addrs,
3431 .user = OCP_USER_MPU | OCP_USER_SDMA,
3432 };
3433
3434 /* am35xx has Davinci MDIO & EMAC */
3435 static struct omap_hwmod_class am35xx_mdio_class = {
3436 .name = "davinci_mdio",
3437 };
3438
3439 static struct omap_hwmod am35xx_mdio_hwmod = {
3440 .name = "davinci_mdio",
3441 .class = &am35xx_mdio_class,
3442 .flags = HWMOD_NO_IDLEST,
3443 };
3444
3445 /*
3446 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3447 * but this will probably require some additional hwmod core support,
3448 * so is left as a future to-do item.
3449 */
3450 static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
3451 .master = &am35xx_mdio_hwmod,
3452 .slave = &omap3xxx_l3_main_hwmod,
3453 .clk = "emac_fck",
3454 .user = OCP_USER_MPU,
3455 };
3456
3457 static struct omap_hwmod_addr_space am35xx_mdio_addrs[] = {
3458 {
3459 .pa_start = AM35XX_IPSS_MDIO_BASE,
3460 .pa_end = AM35XX_IPSS_MDIO_BASE + SZ_4K - 1,
3461 .flags = ADDR_TYPE_RT,
3462 },
3463 { }
3464 };
3465
3466 /* l4_core -> davinci mdio */
3467 /*
3468 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3469 * but this will probably require some additional hwmod core support,
3470 * so is left as a future to-do item.
3471 */
3472 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
3473 .master = &omap3xxx_l4_core_hwmod,
3474 .slave = &am35xx_mdio_hwmod,
3475 .clk = "emac_fck",
3476 .addr = am35xx_mdio_addrs,
3477 .user = OCP_USER_MPU,
3478 };
3479
3480 static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = {
3481 { .name = "rxthresh", .irq = 67 + OMAP_INTC_START, },
3482 { .name = "rx_pulse", .irq = 68 + OMAP_INTC_START, },
3483 { .name = "tx_pulse", .irq = 69 + OMAP_INTC_START },
3484 { .name = "misc_pulse", .irq = 70 + OMAP_INTC_START },
3485 { .irq = -1 },
3486 };
3487
3488 static struct omap_hwmod_class am35xx_emac_class = {
3489 .name = "davinci_emac",
3490 };
3491
3492 static struct omap_hwmod am35xx_emac_hwmod = {
3493 .name = "davinci_emac",
3494 .mpu_irqs = am35xx_emac_mpu_irqs,
3495 .class = &am35xx_emac_class,
3496 .flags = HWMOD_NO_IDLEST,
3497 };
3498
3499 /* l3_core -> davinci emac interface */
3500 /*
3501 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3502 * but this will probably require some additional hwmod core support,
3503 * so is left as a future to-do item.
3504 */
3505 static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
3506 .master = &am35xx_emac_hwmod,
3507 .slave = &omap3xxx_l3_main_hwmod,
3508 .clk = "emac_ick",
3509 .user = OCP_USER_MPU,
3510 };
3511
3512 static struct omap_hwmod_addr_space am35xx_emac_addrs[] = {
3513 {
3514 .pa_start = AM35XX_IPSS_EMAC_BASE,
3515 .pa_end = AM35XX_IPSS_EMAC_BASE + 0x30000 - 1,
3516 .flags = ADDR_TYPE_RT,
3517 },
3518 { }
3519 };
3520
3521 /* l4_core -> davinci emac */
3522 /*
3523 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3524 * but this will probably require some additional hwmod core support,
3525 * so is left as a future to-do item.
3526 */
3527 static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
3528 .master = &omap3xxx_l4_core_hwmod,
3529 .slave = &am35xx_emac_hwmod,
3530 .clk = "emac_ick",
3531 .addr = am35xx_emac_addrs,
3532 .user = OCP_USER_MPU,
3533 };
3534
3535 static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
3536 .master = &omap3xxx_l3_main_hwmod,
3537 .slave = &omap3xxx_gpmc_hwmod,
3538 .clk = "core_l3_ick",
3539 .addr = omap3xxx_gpmc_addrs,
3540 .user = OCP_USER_MPU | OCP_USER_SDMA,
3541 };
3542
3543 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3544 &omap3xxx_l3_main__l4_core,
3545 &omap3xxx_l3_main__l4_per,
3546 &omap3xxx_mpu__l3_main,
3547 &omap3xxx_l3_main__l4_debugss,
3548 &omap3xxx_l4_core__l4_wkup,
3549 &omap3xxx_l4_core__mmc3,
3550 &omap3_l4_core__uart1,
3551 &omap3_l4_core__uart2,
3552 &omap3_l4_per__uart3,
3553 &omap3_l4_core__i2c1,
3554 &omap3_l4_core__i2c2,
3555 &omap3_l4_core__i2c3,
3556 &omap3xxx_l4_wkup__l4_sec,
3557 &omap3xxx_l4_wkup__timer1,
3558 &omap3xxx_l4_per__timer2,
3559 &omap3xxx_l4_per__timer3,
3560 &omap3xxx_l4_per__timer4,
3561 &omap3xxx_l4_per__timer5,
3562 &omap3xxx_l4_per__timer6,
3563 &omap3xxx_l4_per__timer7,
3564 &omap3xxx_l4_per__timer8,
3565 &omap3xxx_l4_per__timer9,
3566 &omap3xxx_l4_core__timer10,
3567 &omap3xxx_l4_core__timer11,
3568 &omap3xxx_l4_wkup__wd_timer2,
3569 &omap3xxx_l4_wkup__gpio1,
3570 &omap3xxx_l4_per__gpio2,
3571 &omap3xxx_l4_per__gpio3,
3572 &omap3xxx_l4_per__gpio4,
3573 &omap3xxx_l4_per__gpio5,
3574 &omap3xxx_l4_per__gpio6,
3575 &omap3xxx_dma_system__l3,
3576 &omap3xxx_l4_core__dma_system,
3577 &omap3xxx_l4_core__mcbsp1,
3578 &omap3xxx_l4_per__mcbsp2,
3579 &omap3xxx_l4_per__mcbsp3,
3580 &omap3xxx_l4_per__mcbsp4,
3581 &omap3xxx_l4_core__mcbsp5,
3582 &omap3xxx_l4_per__mcbsp2_sidetone,
3583 &omap3xxx_l4_per__mcbsp3_sidetone,
3584 &omap34xx_l4_core__mcspi1,
3585 &omap34xx_l4_core__mcspi2,
3586 &omap34xx_l4_core__mcspi3,
3587 &omap34xx_l4_core__mcspi4,
3588 &omap3xxx_l4_wkup__counter_32k,
3589 &omap3xxx_l3_main__gpmc,
3590 NULL,
3591 };
3592
3593 /* GP-only hwmod links */
3594 static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = {
3595 &omap3xxx_l4_sec__timer12,
3596 NULL
3597 };
3598
3599 /* 3430ES1-only hwmod links */
3600 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
3601 &omap3430es1_dss__l3,
3602 &omap3430es1_l4_core__dss,
3603 NULL
3604 };
3605
3606 /* 3430ES2+-only hwmod links */
3607 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
3608 &omap3xxx_dss__l3,
3609 &omap3xxx_l4_core__dss,
3610 &omap3xxx_usbhsotg__l3,
3611 &omap3xxx_l4_core__usbhsotg,
3612 &omap3xxx_usb_host_hs__l3_main_2,
3613 &omap3xxx_l4_core__usb_host_hs,
3614 &omap3xxx_l4_core__usb_tll_hs,
3615 NULL
3616 };
3617
3618 /* <= 3430ES3-only hwmod links */
3619 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
3620 &omap3xxx_l4_core__pre_es3_mmc1,
3621 &omap3xxx_l4_core__pre_es3_mmc2,
3622 NULL
3623 };
3624
3625 /* 3430ES3+-only hwmod links */
3626 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3627 &omap3xxx_l4_core__es3plus_mmc1,
3628 &omap3xxx_l4_core__es3plus_mmc2,
3629 NULL
3630 };
3631
3632 /* 34xx-only hwmod links (all ES revisions) */
3633 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3634 &omap3xxx_l3__iva,
3635 &omap34xx_l4_core__sr1,
3636 &omap34xx_l4_core__sr2,
3637 &omap3xxx_l4_core__mailbox,
3638 &omap3xxx_l4_core__hdq1w,
3639 &omap3xxx_sad2d__l3,
3640 &omap3xxx_l4_core__mmu_isp,
3641 #ifdef CONFIG_OMAP_IOMMU_IVA2
3642 &omap3xxx_l3_main__mmu_iva,
3643 #endif
3644 NULL
3645 };
3646
3647 /* 36xx-only hwmod links (all ES revisions) */
3648 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3649 &omap3xxx_l3__iva,
3650 &omap36xx_l4_per__uart4,
3651 &omap3xxx_dss__l3,
3652 &omap3xxx_l4_core__dss,
3653 &omap36xx_l4_core__sr1,
3654 &omap36xx_l4_core__sr2,
3655 &omap3xxx_usbhsotg__l3,
3656 &omap3xxx_l4_core__usbhsotg,
3657 &omap3xxx_l4_core__mailbox,
3658 &omap3xxx_usb_host_hs__l3_main_2,
3659 &omap3xxx_l4_core__usb_host_hs,
3660 &omap3xxx_l4_core__usb_tll_hs,
3661 &omap3xxx_l4_core__es3plus_mmc1,
3662 &omap3xxx_l4_core__es3plus_mmc2,
3663 &omap3xxx_l4_core__hdq1w,
3664 &omap3xxx_sad2d__l3,
3665 &omap3xxx_l4_core__mmu_isp,
3666 #ifdef CONFIG_OMAP_IOMMU_IVA2
3667 &omap3xxx_l3_main__mmu_iva,
3668 #endif
3669 NULL
3670 };
3671
3672 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3673 &omap3xxx_dss__l3,
3674 &omap3xxx_l4_core__dss,
3675 &am35xx_usbhsotg__l3,
3676 &am35xx_l4_core__usbhsotg,
3677 &am35xx_l4_core__uart4,
3678 &omap3xxx_usb_host_hs__l3_main_2,
3679 &omap3xxx_l4_core__usb_host_hs,
3680 &omap3xxx_l4_core__usb_tll_hs,
3681 &omap3xxx_l4_core__es3plus_mmc1,
3682 &omap3xxx_l4_core__es3plus_mmc2,
3683 &omap3xxx_l4_core__hdq1w,
3684 &am35xx_mdio__l3,
3685 &am35xx_l4_core__mdio,
3686 &am35xx_emac__l3,
3687 &am35xx_l4_core__emac,
3688 NULL
3689 };
3690
3691 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3692 &omap3xxx_l4_core__dss_dispc,
3693 &omap3xxx_l4_core__dss_dsi1,
3694 &omap3xxx_l4_core__dss_rfbi,
3695 &omap3xxx_l4_core__dss_venc,
3696 NULL
3697 };
3698
3699 int __init omap3xxx_hwmod_init(void)
3700 {
3701 int r;
3702 struct omap_hwmod_ocp_if **h = NULL;
3703 unsigned int rev;
3704
3705 omap_hwmod_init();
3706
3707 /* Register hwmod links common to all OMAP3 */
3708 r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
3709 if (r < 0)
3710 return r;
3711
3712 /* Register GP-only hwmod links. */
3713 if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
3714 r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs);
3715 if (r < 0)
3716 return r;
3717 }
3718
3719 rev = omap_rev();
3720
3721 /*
3722 * Register hwmod links common to individual OMAP3 families, all
3723 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3724 * All possible revisions should be included in this conditional.
3725 */
3726 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3727 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3728 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3729 h = omap34xx_hwmod_ocp_ifs;
3730 } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
3731 h = am35xx_hwmod_ocp_ifs;
3732 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3733 rev == OMAP3630_REV_ES1_2) {
3734 h = omap36xx_hwmod_ocp_ifs;
3735 } else {
3736 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3737 return -EINVAL;
3738 }
3739
3740 r = omap_hwmod_register_links(h);
3741 if (r < 0)
3742 return r;
3743
3744 /*
3745 * Register hwmod links specific to certain ES levels of a
3746 * particular family of silicon (e.g., 34xx ES1.0)
3747 */
3748 h = NULL;
3749 if (rev == OMAP3430_REV_ES1_0) {
3750 h = omap3430es1_hwmod_ocp_ifs;
3751 } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3752 rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3753 rev == OMAP3430_REV_ES3_1_2) {
3754 h = omap3430es2plus_hwmod_ocp_ifs;
3755 }
3756
3757 if (h) {
3758 r = omap_hwmod_register_links(h);
3759 if (r < 0)
3760 return r;
3761 }
3762
3763 h = NULL;
3764 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3765 rev == OMAP3430_REV_ES2_1) {
3766 h = omap3430_pre_es3_hwmod_ocp_ifs;
3767 } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3768 rev == OMAP3430_REV_ES3_1_2) {
3769 h = omap3430_es3plus_hwmod_ocp_ifs;
3770 }
3771
3772 if (h)
3773 r = omap_hwmod_register_links(h);
3774 if (r < 0)
3775 return r;
3776
3777 /*
3778 * DSS code presumes that dss_core hwmod is handled first,
3779 * _before_ any other DSS related hwmods so register common
3780 * DSS hwmod links last to ensure that dss_core is already
3781 * registered. Otherwise some change things may happen, for
3782 * ex. if dispc is handled before dss_core and DSS is enabled
3783 * in bootloader DISPC will be reset with outputs enabled
3784 * which sometimes leads to unrecoverable L3 error. XXX The
3785 * long-term fix to this is to ensure hwmods are set up in
3786 * dependency order in the hwmod core code.
3787 */
3788 r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
3789
3790 return r;
3791 }
Linux kernel - Deliverables
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