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ARM: OMAP: Remove unused old gpio-switch.h
[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_3xxx_data.c
1 /*
2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
3 *
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
6 * Paul Walmsley
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * The data in this file should be completely autogeneratable from
13 * the TI hardware database or other technical documentation.
14 *
15 * XXX these should be marked initdata for multi-OMAP kernels
16 */
17 #include <linux/power/smartreflex.h>
18 #include <linux/platform_data/gpio-omap.h>
19
20 #include <plat/omap_hwmod.h>
21 #include <plat/cpu.h>
22 #include <plat/dma.h>
23 #include <plat/serial.h>
24 #include <plat/l3_3xxx.h>
25 #include <plat/l4_3xxx.h>
26 #include <plat/i2c.h>
27 #include <plat/mmc.h>
28 #include <plat/mcbsp.h>
29 #include <plat/mcspi.h>
30 #include <plat/dmtimer.h>
31
32 #include <mach/hardware.h>
33 #include <mach/am35xx.h>
34
35 #include "omap_hwmod_common_data.h"
36 #include "prm-regbits-34xx.h"
37 #include "cm-regbits-34xx.h"
38 #include "wd_timer.h"
39
40 /*
41 * OMAP3xxx hardware module integration data
42 *
43 * All of the data in this section should be autogeneratable from the
44 * TI hardware database or other technical documentation. Data that
45 * is driver-specific or driver-kernel integration-specific belongs
46 * elsewhere.
47 */
48
49 /*
50 * IP blocks
51 */
52
53 /* L3 */
54 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
55 { .irq = 9 + OMAP_INTC_START, },
56 { .irq = 10 + OMAP_INTC_START, },
57 { .irq = -1 },
58 };
59
60 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
61 .name = "l3_main",
62 .class = &l3_hwmod_class,
63 .mpu_irqs = omap3xxx_l3_main_irqs,
64 .flags = HWMOD_NO_IDLEST,
65 };
66
67 /* L4 CORE */
68 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
69 .name = "l4_core",
70 .class = &l4_hwmod_class,
71 .flags = HWMOD_NO_IDLEST,
72 };
73
74 /* L4 PER */
75 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
76 .name = "l4_per",
77 .class = &l4_hwmod_class,
78 .flags = HWMOD_NO_IDLEST,
79 };
80
81 /* L4 WKUP */
82 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
83 .name = "l4_wkup",
84 .class = &l4_hwmod_class,
85 .flags = HWMOD_NO_IDLEST,
86 };
87
88 /* L4 SEC */
89 static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
90 .name = "l4_sec",
91 .class = &l4_hwmod_class,
92 .flags = HWMOD_NO_IDLEST,
93 };
94
95 /* MPU */
96 static struct omap_hwmod omap3xxx_mpu_hwmod = {
97 .name = "mpu",
98 .class = &mpu_hwmod_class,
99 .main_clk = "arm_fck",
100 };
101
102 /* IVA2 (IVA2) */
103 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
104 { .name = "logic", .rst_shift = 0 },
105 { .name = "seq0", .rst_shift = 1 },
106 { .name = "seq1", .rst_shift = 2 },
107 };
108
109 static struct omap_hwmod omap3xxx_iva_hwmod = {
110 .name = "iva",
111 .class = &iva_hwmod_class,
112 .clkdm_name = "iva2_clkdm",
113 .rst_lines = omap3xxx_iva_resets,
114 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets),
115 .main_clk = "iva2_ck",
116 };
117
118 /* timer class */
119 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
120 .rev_offs = 0x0000,
121 .sysc_offs = 0x0010,
122 .syss_offs = 0x0014,
123 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
124 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
125 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
126 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
127 .sysc_fields = &omap_hwmod_sysc_type1,
128 };
129
130 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
131 .name = "timer",
132 .sysc = &omap3xxx_timer_1ms_sysc,
133 };
134
135 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
136 .rev_offs = 0x0000,
137 .sysc_offs = 0x0010,
138 .syss_offs = 0x0014,
139 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
140 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
141 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
142 .sysc_fields = &omap_hwmod_sysc_type1,
143 };
144
145 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
146 .name = "timer",
147 .sysc = &omap3xxx_timer_sysc,
148 };
149
150 /* secure timers dev attribute */
151 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
152 .timer_capability = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE,
153 };
154
155 /* always-on timers dev attribute */
156 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
157 .timer_capability = OMAP_TIMER_ALWON,
158 };
159
160 /* pwm timers dev attribute */
161 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
162 .timer_capability = OMAP_TIMER_HAS_PWM,
163 };
164
165 /* timer1 */
166 static struct omap_hwmod omap3xxx_timer1_hwmod = {
167 .name = "timer1",
168 .mpu_irqs = omap2_timer1_mpu_irqs,
169 .main_clk = "gpt1_fck",
170 .prcm = {
171 .omap2 = {
172 .prcm_reg_id = 1,
173 .module_bit = OMAP3430_EN_GPT1_SHIFT,
174 .module_offs = WKUP_MOD,
175 .idlest_reg_id = 1,
176 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
177 },
178 },
179 .dev_attr = &capability_alwon_dev_attr,
180 .class = &omap3xxx_timer_1ms_hwmod_class,
181 };
182
183 /* timer2 */
184 static struct omap_hwmod omap3xxx_timer2_hwmod = {
185 .name = "timer2",
186 .mpu_irqs = omap2_timer2_mpu_irqs,
187 .main_clk = "gpt2_fck",
188 .prcm = {
189 .omap2 = {
190 .prcm_reg_id = 1,
191 .module_bit = OMAP3430_EN_GPT2_SHIFT,
192 .module_offs = OMAP3430_PER_MOD,
193 .idlest_reg_id = 1,
194 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
195 },
196 },
197 .class = &omap3xxx_timer_1ms_hwmod_class,
198 };
199
200 /* timer3 */
201 static struct omap_hwmod omap3xxx_timer3_hwmod = {
202 .name = "timer3",
203 .mpu_irqs = omap2_timer3_mpu_irqs,
204 .main_clk = "gpt3_fck",
205 .prcm = {
206 .omap2 = {
207 .prcm_reg_id = 1,
208 .module_bit = OMAP3430_EN_GPT3_SHIFT,
209 .module_offs = OMAP3430_PER_MOD,
210 .idlest_reg_id = 1,
211 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
212 },
213 },
214 .class = &omap3xxx_timer_hwmod_class,
215 };
216
217 /* timer4 */
218 static struct omap_hwmod omap3xxx_timer4_hwmod = {
219 .name = "timer4",
220 .mpu_irqs = omap2_timer4_mpu_irqs,
221 .main_clk = "gpt4_fck",
222 .prcm = {
223 .omap2 = {
224 .prcm_reg_id = 1,
225 .module_bit = OMAP3430_EN_GPT4_SHIFT,
226 .module_offs = OMAP3430_PER_MOD,
227 .idlest_reg_id = 1,
228 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
229 },
230 },
231 .class = &omap3xxx_timer_hwmod_class,
232 };
233
234 /* timer5 */
235 static struct omap_hwmod omap3xxx_timer5_hwmod = {
236 .name = "timer5",
237 .mpu_irqs = omap2_timer5_mpu_irqs,
238 .main_clk = "gpt5_fck",
239 .prcm = {
240 .omap2 = {
241 .prcm_reg_id = 1,
242 .module_bit = OMAP3430_EN_GPT5_SHIFT,
243 .module_offs = OMAP3430_PER_MOD,
244 .idlest_reg_id = 1,
245 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
246 },
247 },
248 .class = &omap3xxx_timer_hwmod_class,
249 };
250
251 /* timer6 */
252 static struct omap_hwmod omap3xxx_timer6_hwmod = {
253 .name = "timer6",
254 .mpu_irqs = omap2_timer6_mpu_irqs,
255 .main_clk = "gpt6_fck",
256 .prcm = {
257 .omap2 = {
258 .prcm_reg_id = 1,
259 .module_bit = OMAP3430_EN_GPT6_SHIFT,
260 .module_offs = OMAP3430_PER_MOD,
261 .idlest_reg_id = 1,
262 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
263 },
264 },
265 .class = &omap3xxx_timer_hwmod_class,
266 };
267
268 /* timer7 */
269 static struct omap_hwmod omap3xxx_timer7_hwmod = {
270 .name = "timer7",
271 .mpu_irqs = omap2_timer7_mpu_irqs,
272 .main_clk = "gpt7_fck",
273 .prcm = {
274 .omap2 = {
275 .prcm_reg_id = 1,
276 .module_bit = OMAP3430_EN_GPT7_SHIFT,
277 .module_offs = OMAP3430_PER_MOD,
278 .idlest_reg_id = 1,
279 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
280 },
281 },
282 .class = &omap3xxx_timer_hwmod_class,
283 };
284
285 /* timer8 */
286 static struct omap_hwmod omap3xxx_timer8_hwmod = {
287 .name = "timer8",
288 .mpu_irqs = omap2_timer8_mpu_irqs,
289 .main_clk = "gpt8_fck",
290 .prcm = {
291 .omap2 = {
292 .prcm_reg_id = 1,
293 .module_bit = OMAP3430_EN_GPT8_SHIFT,
294 .module_offs = OMAP3430_PER_MOD,
295 .idlest_reg_id = 1,
296 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
297 },
298 },
299 .dev_attr = &capability_pwm_dev_attr,
300 .class = &omap3xxx_timer_hwmod_class,
301 };
302
303 /* timer9 */
304 static struct omap_hwmod omap3xxx_timer9_hwmod = {
305 .name = "timer9",
306 .mpu_irqs = omap2_timer9_mpu_irqs,
307 .main_clk = "gpt9_fck",
308 .prcm = {
309 .omap2 = {
310 .prcm_reg_id = 1,
311 .module_bit = OMAP3430_EN_GPT9_SHIFT,
312 .module_offs = OMAP3430_PER_MOD,
313 .idlest_reg_id = 1,
314 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
315 },
316 },
317 .dev_attr = &capability_pwm_dev_attr,
318 .class = &omap3xxx_timer_hwmod_class,
319 };
320
321 /* timer10 */
322 static struct omap_hwmod omap3xxx_timer10_hwmod = {
323 .name = "timer10",
324 .mpu_irqs = omap2_timer10_mpu_irqs,
325 .main_clk = "gpt10_fck",
326 .prcm = {
327 .omap2 = {
328 .prcm_reg_id = 1,
329 .module_bit = OMAP3430_EN_GPT10_SHIFT,
330 .module_offs = CORE_MOD,
331 .idlest_reg_id = 1,
332 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
333 },
334 },
335 .dev_attr = &capability_pwm_dev_attr,
336 .class = &omap3xxx_timer_1ms_hwmod_class,
337 };
338
339 /* timer11 */
340 static struct omap_hwmod omap3xxx_timer11_hwmod = {
341 .name = "timer11",
342 .mpu_irqs = omap2_timer11_mpu_irqs,
343 .main_clk = "gpt11_fck",
344 .prcm = {
345 .omap2 = {
346 .prcm_reg_id = 1,
347 .module_bit = OMAP3430_EN_GPT11_SHIFT,
348 .module_offs = CORE_MOD,
349 .idlest_reg_id = 1,
350 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
351 },
352 },
353 .dev_attr = &capability_pwm_dev_attr,
354 .class = &omap3xxx_timer_hwmod_class,
355 };
356
357 /* timer12 */
358 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
359 { .irq = 95 + OMAP_INTC_START, },
360 { .irq = -1 },
361 };
362
363 static struct omap_hwmod omap3xxx_timer12_hwmod = {
364 .name = "timer12",
365 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
366 .main_clk = "gpt12_fck",
367 .prcm = {
368 .omap2 = {
369 .prcm_reg_id = 1,
370 .module_bit = OMAP3430_EN_GPT12_SHIFT,
371 .module_offs = WKUP_MOD,
372 .idlest_reg_id = 1,
373 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
374 },
375 },
376 .dev_attr = &capability_secure_dev_attr,
377 .class = &omap3xxx_timer_hwmod_class,
378 };
379
380 /*
381 * 'wd_timer' class
382 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
383 * overflow condition
384 */
385
386 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
387 .rev_offs = 0x0000,
388 .sysc_offs = 0x0010,
389 .syss_offs = 0x0014,
390 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
391 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
392 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
393 SYSS_HAS_RESET_STATUS),
394 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
395 .sysc_fields = &omap_hwmod_sysc_type1,
396 };
397
398 /* I2C common */
399 static struct omap_hwmod_class_sysconfig i2c_sysc = {
400 .rev_offs = 0x00,
401 .sysc_offs = 0x20,
402 .syss_offs = 0x10,
403 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
404 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
405 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
406 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
407 .clockact = CLOCKACT_TEST_ICLK,
408 .sysc_fields = &omap_hwmod_sysc_type1,
409 };
410
411 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
412 .name = "wd_timer",
413 .sysc = &omap3xxx_wd_timer_sysc,
414 .pre_shutdown = &omap2_wd_timer_disable,
415 .reset = &omap2_wd_timer_reset,
416 };
417
418 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
419 .name = "wd_timer2",
420 .class = &omap3xxx_wd_timer_hwmod_class,
421 .main_clk = "wdt2_fck",
422 .prcm = {
423 .omap2 = {
424 .prcm_reg_id = 1,
425 .module_bit = OMAP3430_EN_WDT2_SHIFT,
426 .module_offs = WKUP_MOD,
427 .idlest_reg_id = 1,
428 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
429 },
430 },
431 /*
432 * XXX: Use software supervised mode, HW supervised smartidle seems to
433 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
434 */
435 .flags = HWMOD_SWSUP_SIDLE,
436 };
437
438 /* UART1 */
439 static struct omap_hwmod omap3xxx_uart1_hwmod = {
440 .name = "uart1",
441 .mpu_irqs = omap2_uart1_mpu_irqs,
442 .sdma_reqs = omap2_uart1_sdma_reqs,
443 .main_clk = "uart1_fck",
444 .prcm = {
445 .omap2 = {
446 .module_offs = CORE_MOD,
447 .prcm_reg_id = 1,
448 .module_bit = OMAP3430_EN_UART1_SHIFT,
449 .idlest_reg_id = 1,
450 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
451 },
452 },
453 .class = &omap2_uart_class,
454 };
455
456 /* UART2 */
457 static struct omap_hwmod omap3xxx_uart2_hwmod = {
458 .name = "uart2",
459 .mpu_irqs = omap2_uart2_mpu_irqs,
460 .sdma_reqs = omap2_uart2_sdma_reqs,
461 .main_clk = "uart2_fck",
462 .prcm = {
463 .omap2 = {
464 .module_offs = CORE_MOD,
465 .prcm_reg_id = 1,
466 .module_bit = OMAP3430_EN_UART2_SHIFT,
467 .idlest_reg_id = 1,
468 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
469 },
470 },
471 .class = &omap2_uart_class,
472 };
473
474 /* UART3 */
475 static struct omap_hwmod omap3xxx_uart3_hwmod = {
476 .name = "uart3",
477 .mpu_irqs = omap2_uart3_mpu_irqs,
478 .sdma_reqs = omap2_uart3_sdma_reqs,
479 .main_clk = "uart3_fck",
480 .prcm = {
481 .omap2 = {
482 .module_offs = OMAP3430_PER_MOD,
483 .prcm_reg_id = 1,
484 .module_bit = OMAP3430_EN_UART3_SHIFT,
485 .idlest_reg_id = 1,
486 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
487 },
488 },
489 .class = &omap2_uart_class,
490 };
491
492 /* UART4 */
493 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
494 { .irq = 80 + OMAP_INTC_START, },
495 { .irq = -1 },
496 };
497
498 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
499 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
500 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
501 { .dma_req = -1 }
502 };
503
504 static struct omap_hwmod omap36xx_uart4_hwmod = {
505 .name = "uart4",
506 .mpu_irqs = uart4_mpu_irqs,
507 .sdma_reqs = uart4_sdma_reqs,
508 .main_clk = "uart4_fck",
509 .prcm = {
510 .omap2 = {
511 .module_offs = OMAP3430_PER_MOD,
512 .prcm_reg_id = 1,
513 .module_bit = OMAP3630_EN_UART4_SHIFT,
514 .idlest_reg_id = 1,
515 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
516 },
517 },
518 .class = &omap2_uart_class,
519 };
520
521 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
522 { .irq = 84 + OMAP_INTC_START, },
523 { .irq = -1 },
524 };
525
526 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
527 { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
528 { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
529 { .dma_req = -1 }
530 };
531
532 /*
533 * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
534 * uart2_fck being enabled. So we add uart1_fck as an optional clock,
535 * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET. This really
536 * should not be needed. The functional clock structure of the AM35xx
537 * UART4 is extremely unclear and opaque; it is unclear what the role
538 * of uart1/2_fck is for the UART4. Any clarification from either
539 * empirical testing or the AM3505/3517 hardware designers would be
540 * most welcome.
541 */
542 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
543 { .role = "softreset_uart1_fck", .clk = "uart1_fck" },
544 };
545
546 static struct omap_hwmod am35xx_uart4_hwmod = {
547 .name = "uart4",
548 .mpu_irqs = am35xx_uart4_mpu_irqs,
549 .sdma_reqs = am35xx_uart4_sdma_reqs,
550 .main_clk = "uart4_fck",
551 .prcm = {
552 .omap2 = {
553 .module_offs = CORE_MOD,
554 .prcm_reg_id = 1,
555 .module_bit = AM35XX_EN_UART4_SHIFT,
556 .idlest_reg_id = 1,
557 .idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
558 },
559 },
560 .opt_clks = am35xx_uart4_opt_clks,
561 .opt_clks_cnt = ARRAY_SIZE(am35xx_uart4_opt_clks),
562 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
563 .class = &omap2_uart_class,
564 };
565
566 static struct omap_hwmod_class i2c_class = {
567 .name = "i2c",
568 .sysc = &i2c_sysc,
569 .rev = OMAP_I2C_IP_VERSION_1,
570 .reset = &omap_i2c_reset,
571 };
572
573 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
574 { .name = "dispc", .dma_req = 5 },
575 { .name = "dsi1", .dma_req = 74 },
576 { .dma_req = -1 }
577 };
578
579 /* dss */
580 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
581 /*
582 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
583 * driver does not use these clocks.
584 */
585 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
586 { .role = "tv_clk", .clk = "dss_tv_fck" },
587 /* required only on OMAP3430 */
588 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
589 };
590
591 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
592 .name = "dss_core",
593 .class = &omap2_dss_hwmod_class,
594 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
595 .sdma_reqs = omap3xxx_dss_sdma_chs,
596 .prcm = {
597 .omap2 = {
598 .prcm_reg_id = 1,
599 .module_bit = OMAP3430_EN_DSS1_SHIFT,
600 .module_offs = OMAP3430_DSS_MOD,
601 .idlest_reg_id = 1,
602 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
603 },
604 },
605 .opt_clks = dss_opt_clks,
606 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
607 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
608 };
609
610 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
611 .name = "dss_core",
612 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
613 .class = &omap2_dss_hwmod_class,
614 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
615 .sdma_reqs = omap3xxx_dss_sdma_chs,
616 .prcm = {
617 .omap2 = {
618 .prcm_reg_id = 1,
619 .module_bit = OMAP3430_EN_DSS1_SHIFT,
620 .module_offs = OMAP3430_DSS_MOD,
621 .idlest_reg_id = 1,
622 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
623 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
624 },
625 },
626 .opt_clks = dss_opt_clks,
627 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
628 };
629
630 /*
631 * 'dispc' class
632 * display controller
633 */
634
635 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
636 .rev_offs = 0x0000,
637 .sysc_offs = 0x0010,
638 .syss_offs = 0x0014,
639 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
640 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
641 SYSC_HAS_ENAWAKEUP),
642 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
643 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
644 .sysc_fields = &omap_hwmod_sysc_type1,
645 };
646
647 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
648 .name = "dispc",
649 .sysc = &omap3_dispc_sysc,
650 };
651
652 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
653 .name = "dss_dispc",
654 .class = &omap3_dispc_hwmod_class,
655 .mpu_irqs = omap2_dispc_irqs,
656 .main_clk = "dss1_alwon_fck",
657 .prcm = {
658 .omap2 = {
659 .prcm_reg_id = 1,
660 .module_bit = OMAP3430_EN_DSS1_SHIFT,
661 .module_offs = OMAP3430_DSS_MOD,
662 },
663 },
664 .flags = HWMOD_NO_IDLEST,
665 .dev_attr = &omap2_3_dss_dispc_dev_attr
666 };
667
668 /*
669 * 'dsi' class
670 * display serial interface controller
671 */
672
673 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
674 .name = "dsi",
675 };
676
677 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
678 { .irq = 25 + OMAP_INTC_START, },
679 { .irq = -1 },
680 };
681
682 /* dss_dsi1 */
683 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
684 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
685 };
686
687 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
688 .name = "dss_dsi1",
689 .class = &omap3xxx_dsi_hwmod_class,
690 .mpu_irqs = omap3xxx_dsi1_irqs,
691 .main_clk = "dss1_alwon_fck",
692 .prcm = {
693 .omap2 = {
694 .prcm_reg_id = 1,
695 .module_bit = OMAP3430_EN_DSS1_SHIFT,
696 .module_offs = OMAP3430_DSS_MOD,
697 },
698 },
699 .opt_clks = dss_dsi1_opt_clks,
700 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
701 .flags = HWMOD_NO_IDLEST,
702 };
703
704 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
705 { .role = "ick", .clk = "dss_ick" },
706 };
707
708 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
709 .name = "dss_rfbi",
710 .class = &omap2_rfbi_hwmod_class,
711 .main_clk = "dss1_alwon_fck",
712 .prcm = {
713 .omap2 = {
714 .prcm_reg_id = 1,
715 .module_bit = OMAP3430_EN_DSS1_SHIFT,
716 .module_offs = OMAP3430_DSS_MOD,
717 },
718 },
719 .opt_clks = dss_rfbi_opt_clks,
720 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
721 .flags = HWMOD_NO_IDLEST,
722 };
723
724 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
725 /* required only on OMAP3430 */
726 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
727 };
728
729 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
730 .name = "dss_venc",
731 .class = &omap2_venc_hwmod_class,
732 .main_clk = "dss_tv_fck",
733 .prcm = {
734 .omap2 = {
735 .prcm_reg_id = 1,
736 .module_bit = OMAP3430_EN_DSS1_SHIFT,
737 .module_offs = OMAP3430_DSS_MOD,
738 },
739 },
740 .opt_clks = dss_venc_opt_clks,
741 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
742 .flags = HWMOD_NO_IDLEST,
743 };
744
745 /* I2C1 */
746 static struct omap_i2c_dev_attr i2c1_dev_attr = {
747 .fifo_depth = 8, /* bytes */
748 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
749 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
750 OMAP_I2C_FLAG_BUS_SHIFT_2,
751 };
752
753 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
754 .name = "i2c1",
755 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
756 .mpu_irqs = omap2_i2c1_mpu_irqs,
757 .sdma_reqs = omap2_i2c1_sdma_reqs,
758 .main_clk = "i2c1_fck",
759 .prcm = {
760 .omap2 = {
761 .module_offs = CORE_MOD,
762 .prcm_reg_id = 1,
763 .module_bit = OMAP3430_EN_I2C1_SHIFT,
764 .idlest_reg_id = 1,
765 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
766 },
767 },
768 .class = &i2c_class,
769 .dev_attr = &i2c1_dev_attr,
770 };
771
772 /* I2C2 */
773 static struct omap_i2c_dev_attr i2c2_dev_attr = {
774 .fifo_depth = 8, /* bytes */
775 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
776 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
777 OMAP_I2C_FLAG_BUS_SHIFT_2,
778 };
779
780 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
781 .name = "i2c2",
782 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
783 .mpu_irqs = omap2_i2c2_mpu_irqs,
784 .sdma_reqs = omap2_i2c2_sdma_reqs,
785 .main_clk = "i2c2_fck",
786 .prcm = {
787 .omap2 = {
788 .module_offs = CORE_MOD,
789 .prcm_reg_id = 1,
790 .module_bit = OMAP3430_EN_I2C2_SHIFT,
791 .idlest_reg_id = 1,
792 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
793 },
794 },
795 .class = &i2c_class,
796 .dev_attr = &i2c2_dev_attr,
797 };
798
799 /* I2C3 */
800 static struct omap_i2c_dev_attr i2c3_dev_attr = {
801 .fifo_depth = 64, /* bytes */
802 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
803 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
804 OMAP_I2C_FLAG_BUS_SHIFT_2,
805 };
806
807 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
808 { .irq = 61 + OMAP_INTC_START, },
809 { .irq = -1 },
810 };
811
812 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
813 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
814 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
815 { .dma_req = -1 }
816 };
817
818 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
819 .name = "i2c3",
820 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
821 .mpu_irqs = i2c3_mpu_irqs,
822 .sdma_reqs = i2c3_sdma_reqs,
823 .main_clk = "i2c3_fck",
824 .prcm = {
825 .omap2 = {
826 .module_offs = CORE_MOD,
827 .prcm_reg_id = 1,
828 .module_bit = OMAP3430_EN_I2C3_SHIFT,
829 .idlest_reg_id = 1,
830 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
831 },
832 },
833 .class = &i2c_class,
834 .dev_attr = &i2c3_dev_attr,
835 };
836
837 /*
838 * 'gpio' class
839 * general purpose io module
840 */
841
842 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
843 .rev_offs = 0x0000,
844 .sysc_offs = 0x0010,
845 .syss_offs = 0x0014,
846 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
847 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
848 SYSS_HAS_RESET_STATUS),
849 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
850 .sysc_fields = &omap_hwmod_sysc_type1,
851 };
852
853 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
854 .name = "gpio",
855 .sysc = &omap3xxx_gpio_sysc,
856 .rev = 1,
857 };
858
859 /* gpio_dev_attr */
860 static struct omap_gpio_dev_attr gpio_dev_attr = {
861 .bank_width = 32,
862 .dbck_flag = true,
863 };
864
865 /* gpio1 */
866 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
867 { .role = "dbclk", .clk = "gpio1_dbck", },
868 };
869
870 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
871 .name = "gpio1",
872 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
873 .mpu_irqs = omap2_gpio1_irqs,
874 .main_clk = "gpio1_ick",
875 .opt_clks = gpio1_opt_clks,
876 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
877 .prcm = {
878 .omap2 = {
879 .prcm_reg_id = 1,
880 .module_bit = OMAP3430_EN_GPIO1_SHIFT,
881 .module_offs = WKUP_MOD,
882 .idlest_reg_id = 1,
883 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
884 },
885 },
886 .class = &omap3xxx_gpio_hwmod_class,
887 .dev_attr = &gpio_dev_attr,
888 };
889
890 /* gpio2 */
891 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
892 { .role = "dbclk", .clk = "gpio2_dbck", },
893 };
894
895 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
896 .name = "gpio2",
897 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
898 .mpu_irqs = omap2_gpio2_irqs,
899 .main_clk = "gpio2_ick",
900 .opt_clks = gpio2_opt_clks,
901 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
902 .prcm = {
903 .omap2 = {
904 .prcm_reg_id = 1,
905 .module_bit = OMAP3430_EN_GPIO2_SHIFT,
906 .module_offs = OMAP3430_PER_MOD,
907 .idlest_reg_id = 1,
908 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
909 },
910 },
911 .class = &omap3xxx_gpio_hwmod_class,
912 .dev_attr = &gpio_dev_attr,
913 };
914
915 /* gpio3 */
916 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
917 { .role = "dbclk", .clk = "gpio3_dbck", },
918 };
919
920 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
921 .name = "gpio3",
922 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
923 .mpu_irqs = omap2_gpio3_irqs,
924 .main_clk = "gpio3_ick",
925 .opt_clks = gpio3_opt_clks,
926 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
927 .prcm = {
928 .omap2 = {
929 .prcm_reg_id = 1,
930 .module_bit = OMAP3430_EN_GPIO3_SHIFT,
931 .module_offs = OMAP3430_PER_MOD,
932 .idlest_reg_id = 1,
933 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
934 },
935 },
936 .class = &omap3xxx_gpio_hwmod_class,
937 .dev_attr = &gpio_dev_attr,
938 };
939
940 /* gpio4 */
941 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
942 { .role = "dbclk", .clk = "gpio4_dbck", },
943 };
944
945 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
946 .name = "gpio4",
947 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
948 .mpu_irqs = omap2_gpio4_irqs,
949 .main_clk = "gpio4_ick",
950 .opt_clks = gpio4_opt_clks,
951 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
952 .prcm = {
953 .omap2 = {
954 .prcm_reg_id = 1,
955 .module_bit = OMAP3430_EN_GPIO4_SHIFT,
956 .module_offs = OMAP3430_PER_MOD,
957 .idlest_reg_id = 1,
958 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
959 },
960 },
961 .class = &omap3xxx_gpio_hwmod_class,
962 .dev_attr = &gpio_dev_attr,
963 };
964
965 /* gpio5 */
966 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
967 { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */
968 { .irq = -1 },
969 };
970
971 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
972 { .role = "dbclk", .clk = "gpio5_dbck", },
973 };
974
975 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
976 .name = "gpio5",
977 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
978 .mpu_irqs = omap3xxx_gpio5_irqs,
979 .main_clk = "gpio5_ick",
980 .opt_clks = gpio5_opt_clks,
981 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
982 .prcm = {
983 .omap2 = {
984 .prcm_reg_id = 1,
985 .module_bit = OMAP3430_EN_GPIO5_SHIFT,
986 .module_offs = OMAP3430_PER_MOD,
987 .idlest_reg_id = 1,
988 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
989 },
990 },
991 .class = &omap3xxx_gpio_hwmod_class,
992 .dev_attr = &gpio_dev_attr,
993 };
994
995 /* gpio6 */
996 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
997 { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */
998 { .irq = -1 },
999 };
1000
1001 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1002 { .role = "dbclk", .clk = "gpio6_dbck", },
1003 };
1004
1005 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
1006 .name = "gpio6",
1007 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1008 .mpu_irqs = omap3xxx_gpio6_irqs,
1009 .main_clk = "gpio6_ick",
1010 .opt_clks = gpio6_opt_clks,
1011 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1012 .prcm = {
1013 .omap2 = {
1014 .prcm_reg_id = 1,
1015 .module_bit = OMAP3430_EN_GPIO6_SHIFT,
1016 .module_offs = OMAP3430_PER_MOD,
1017 .idlest_reg_id = 1,
1018 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
1019 },
1020 },
1021 .class = &omap3xxx_gpio_hwmod_class,
1022 .dev_attr = &gpio_dev_attr,
1023 };
1024
1025 /* dma attributes */
1026 static struct omap_dma_dev_attr dma_dev_attr = {
1027 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1028 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1029 .lch_count = 32,
1030 };
1031
1032 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1033 .rev_offs = 0x0000,
1034 .sysc_offs = 0x002c,
1035 .syss_offs = 0x0028,
1036 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1037 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1038 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
1039 SYSS_HAS_RESET_STATUS),
1040 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1041 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1042 .sysc_fields = &omap_hwmod_sysc_type1,
1043 };
1044
1045 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1046 .name = "dma",
1047 .sysc = &omap3xxx_dma_sysc,
1048 };
1049
1050 /* dma_system */
1051 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1052 .name = "dma",
1053 .class = &omap3xxx_dma_hwmod_class,
1054 .mpu_irqs = omap2_dma_system_irqs,
1055 .main_clk = "core_l3_ick",
1056 .prcm = {
1057 .omap2 = {
1058 .module_offs = CORE_MOD,
1059 .prcm_reg_id = 1,
1060 .module_bit = OMAP3430_ST_SDMA_SHIFT,
1061 .idlest_reg_id = 1,
1062 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
1063 },
1064 },
1065 .dev_attr = &dma_dev_attr,
1066 .flags = HWMOD_NO_IDLEST,
1067 };
1068
1069 /*
1070 * 'mcbsp' class
1071 * multi channel buffered serial port controller
1072 */
1073
1074 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
1075 .sysc_offs = 0x008c,
1076 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1077 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1078 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1079 .sysc_fields = &omap_hwmod_sysc_type1,
1080 .clockact = 0x2,
1081 };
1082
1083 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1084 .name = "mcbsp",
1085 .sysc = &omap3xxx_mcbsp_sysc,
1086 .rev = MCBSP_CONFIG_TYPE3,
1087 };
1088
1089 /* McBSP functional clock mapping */
1090 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
1091 { .role = "pad_fck", .clk = "mcbsp_clks" },
1092 { .role = "prcm_fck", .clk = "core_96m_fck" },
1093 };
1094
1095 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
1096 { .role = "pad_fck", .clk = "mcbsp_clks" },
1097 { .role = "prcm_fck", .clk = "per_96m_fck" },
1098 };
1099
1100 /* mcbsp1 */
1101 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
1102 { .name = "common", .irq = 16 + OMAP_INTC_START, },
1103 { .name = "tx", .irq = 59 + OMAP_INTC_START, },
1104 { .name = "rx", .irq = 60 + OMAP_INTC_START, },
1105 { .irq = -1 },
1106 };
1107
1108 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1109 .name = "mcbsp1",
1110 .class = &omap3xxx_mcbsp_hwmod_class,
1111 .mpu_irqs = omap3xxx_mcbsp1_irqs,
1112 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
1113 .main_clk = "mcbsp1_fck",
1114 .prcm = {
1115 .omap2 = {
1116 .prcm_reg_id = 1,
1117 .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
1118 .module_offs = CORE_MOD,
1119 .idlest_reg_id = 1,
1120 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
1121 },
1122 },
1123 .opt_clks = mcbsp15_opt_clks,
1124 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
1125 };
1126
1127 /* mcbsp2 */
1128 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
1129 { .name = "common", .irq = 17 + OMAP_INTC_START, },
1130 { .name = "tx", .irq = 62 + OMAP_INTC_START, },
1131 { .name = "rx", .irq = 63 + OMAP_INTC_START, },
1132 { .irq = -1 },
1133 };
1134
1135 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1136 .sidetone = "mcbsp2_sidetone",
1137 };
1138
1139 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1140 .name = "mcbsp2",
1141 .class = &omap3xxx_mcbsp_hwmod_class,
1142 .mpu_irqs = omap3xxx_mcbsp2_irqs,
1143 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
1144 .main_clk = "mcbsp2_fck",
1145 .prcm = {
1146 .omap2 = {
1147 .prcm_reg_id = 1,
1148 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1149 .module_offs = OMAP3430_PER_MOD,
1150 .idlest_reg_id = 1,
1151 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1152 },
1153 },
1154 .opt_clks = mcbsp234_opt_clks,
1155 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1156 .dev_attr = &omap34xx_mcbsp2_dev_attr,
1157 };
1158
1159 /* mcbsp3 */
1160 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
1161 { .name = "common", .irq = 22 + OMAP_INTC_START, },
1162 { .name = "tx", .irq = 89 + OMAP_INTC_START, },
1163 { .name = "rx", .irq = 90 + OMAP_INTC_START, },
1164 { .irq = -1 },
1165 };
1166
1167 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1168 .sidetone = "mcbsp3_sidetone",
1169 };
1170
1171 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1172 .name = "mcbsp3",
1173 .class = &omap3xxx_mcbsp_hwmod_class,
1174 .mpu_irqs = omap3xxx_mcbsp3_irqs,
1175 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
1176 .main_clk = "mcbsp3_fck",
1177 .prcm = {
1178 .omap2 = {
1179 .prcm_reg_id = 1,
1180 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1181 .module_offs = OMAP3430_PER_MOD,
1182 .idlest_reg_id = 1,
1183 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1184 },
1185 },
1186 .opt_clks = mcbsp234_opt_clks,
1187 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1188 .dev_attr = &omap34xx_mcbsp3_dev_attr,
1189 };
1190
1191 /* mcbsp4 */
1192 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
1193 { .name = "common", .irq = 23 + OMAP_INTC_START, },
1194 { .name = "tx", .irq = 54 + OMAP_INTC_START, },
1195 { .name = "rx", .irq = 55 + OMAP_INTC_START, },
1196 { .irq = -1 },
1197 };
1198
1199 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
1200 { .name = "rx", .dma_req = 20 },
1201 { .name = "tx", .dma_req = 19 },
1202 { .dma_req = -1 }
1203 };
1204
1205 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1206 .name = "mcbsp4",
1207 .class = &omap3xxx_mcbsp_hwmod_class,
1208 .mpu_irqs = omap3xxx_mcbsp4_irqs,
1209 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
1210 .main_clk = "mcbsp4_fck",
1211 .prcm = {
1212 .omap2 = {
1213 .prcm_reg_id = 1,
1214 .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
1215 .module_offs = OMAP3430_PER_MOD,
1216 .idlest_reg_id = 1,
1217 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
1218 },
1219 },
1220 .opt_clks = mcbsp234_opt_clks,
1221 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1222 };
1223
1224 /* mcbsp5 */
1225 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
1226 { .name = "common", .irq = 27 + OMAP_INTC_START, },
1227 { .name = "tx", .irq = 81 + OMAP_INTC_START, },
1228 { .name = "rx", .irq = 82 + OMAP_INTC_START, },
1229 { .irq = -1 },
1230 };
1231
1232 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
1233 { .name = "rx", .dma_req = 22 },
1234 { .name = "tx", .dma_req = 21 },
1235 { .dma_req = -1 }
1236 };
1237
1238 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1239 .name = "mcbsp5",
1240 .class = &omap3xxx_mcbsp_hwmod_class,
1241 .mpu_irqs = omap3xxx_mcbsp5_irqs,
1242 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
1243 .main_clk = "mcbsp5_fck",
1244 .prcm = {
1245 .omap2 = {
1246 .prcm_reg_id = 1,
1247 .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
1248 .module_offs = CORE_MOD,
1249 .idlest_reg_id = 1,
1250 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
1251 },
1252 },
1253 .opt_clks = mcbsp15_opt_clks,
1254 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
1255 };
1256
1257 /* 'mcbsp sidetone' class */
1258 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
1259 .sysc_offs = 0x0010,
1260 .sysc_flags = SYSC_HAS_AUTOIDLE,
1261 .sysc_fields = &omap_hwmod_sysc_type1,
1262 };
1263
1264 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
1265 .name = "mcbsp_sidetone",
1266 .sysc = &omap3xxx_mcbsp_sidetone_sysc,
1267 };
1268
1269 /* mcbsp2_sidetone */
1270 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
1271 { .name = "irq", .irq = 4 + OMAP_INTC_START, },
1272 { .irq = -1 },
1273 };
1274
1275 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1276 .name = "mcbsp2_sidetone",
1277 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1278 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
1279 .main_clk = "mcbsp2_fck",
1280 .prcm = {
1281 .omap2 = {
1282 .prcm_reg_id = 1,
1283 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1284 .module_offs = OMAP3430_PER_MOD,
1285 .idlest_reg_id = 1,
1286 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1287 },
1288 },
1289 };
1290
1291 /* mcbsp3_sidetone */
1292 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
1293 { .name = "irq", .irq = 5 + OMAP_INTC_START, },
1294 { .irq = -1 },
1295 };
1296
1297 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1298 .name = "mcbsp3_sidetone",
1299 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1300 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
1301 .main_clk = "mcbsp3_fck",
1302 .prcm = {
1303 .omap2 = {
1304 .prcm_reg_id = 1,
1305 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1306 .module_offs = OMAP3430_PER_MOD,
1307 .idlest_reg_id = 1,
1308 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1309 },
1310 },
1311 };
1312
1313 /* SR common */
1314 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1315 .clkact_shift = 20,
1316 };
1317
1318 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1319 .sysc_offs = 0x24,
1320 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1321 .clockact = CLOCKACT_TEST_ICLK,
1322 .sysc_fields = &omap34xx_sr_sysc_fields,
1323 };
1324
1325 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1326 .name = "smartreflex",
1327 .sysc = &omap34xx_sr_sysc,
1328 .rev = 1,
1329 };
1330
1331 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
1332 .sidle_shift = 24,
1333 .enwkup_shift = 26,
1334 };
1335
1336 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1337 .sysc_offs = 0x38,
1338 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1339 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1340 SYSC_NO_CACHE),
1341 .sysc_fields = &omap36xx_sr_sysc_fields,
1342 };
1343
1344 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1345 .name = "smartreflex",
1346 .sysc = &omap36xx_sr_sysc,
1347 .rev = 2,
1348 };
1349
1350 /* SR1 */
1351 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1352 .sensor_voltdm_name = "mpu_iva",
1353 };
1354
1355 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
1356 { .irq = 18 + OMAP_INTC_START, },
1357 { .irq = -1 },
1358 };
1359
1360 static struct omap_hwmod omap34xx_sr1_hwmod = {
1361 .name = "smartreflex_mpu_iva",
1362 .class = &omap34xx_smartreflex_hwmod_class,
1363 .main_clk = "sr1_fck",
1364 .prcm = {
1365 .omap2 = {
1366 .prcm_reg_id = 1,
1367 .module_bit = OMAP3430_EN_SR1_SHIFT,
1368 .module_offs = WKUP_MOD,
1369 .idlest_reg_id = 1,
1370 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1371 },
1372 },
1373 .dev_attr = &sr1_dev_attr,
1374 .mpu_irqs = omap3_smartreflex_mpu_irqs,
1375 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1376 };
1377
1378 static struct omap_hwmod omap36xx_sr1_hwmod = {
1379 .name = "smartreflex_mpu_iva",
1380 .class = &omap36xx_smartreflex_hwmod_class,
1381 .main_clk = "sr1_fck",
1382 .prcm = {
1383 .omap2 = {
1384 .prcm_reg_id = 1,
1385 .module_bit = OMAP3430_EN_SR1_SHIFT,
1386 .module_offs = WKUP_MOD,
1387 .idlest_reg_id = 1,
1388 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1389 },
1390 },
1391 .dev_attr = &sr1_dev_attr,
1392 .mpu_irqs = omap3_smartreflex_mpu_irqs,
1393 };
1394
1395 /* SR2 */
1396 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1397 .sensor_voltdm_name = "core",
1398 };
1399
1400 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
1401 { .irq = 19 + OMAP_INTC_START, },
1402 { .irq = -1 },
1403 };
1404
1405 static struct omap_hwmod omap34xx_sr2_hwmod = {
1406 .name = "smartreflex_core",
1407 .class = &omap34xx_smartreflex_hwmod_class,
1408 .main_clk = "sr2_fck",
1409 .prcm = {
1410 .omap2 = {
1411 .prcm_reg_id = 1,
1412 .module_bit = OMAP3430_EN_SR2_SHIFT,
1413 .module_offs = WKUP_MOD,
1414 .idlest_reg_id = 1,
1415 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1416 },
1417 },
1418 .dev_attr = &sr2_dev_attr,
1419 .mpu_irqs = omap3_smartreflex_core_irqs,
1420 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1421 };
1422
1423 static struct omap_hwmod omap36xx_sr2_hwmod = {
1424 .name = "smartreflex_core",
1425 .class = &omap36xx_smartreflex_hwmod_class,
1426 .main_clk = "sr2_fck",
1427 .prcm = {
1428 .omap2 = {
1429 .prcm_reg_id = 1,
1430 .module_bit = OMAP3430_EN_SR2_SHIFT,
1431 .module_offs = WKUP_MOD,
1432 .idlest_reg_id = 1,
1433 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1434 },
1435 },
1436 .dev_attr = &sr2_dev_attr,
1437 .mpu_irqs = omap3_smartreflex_core_irqs,
1438 };
1439
1440 /*
1441 * 'mailbox' class
1442 * mailbox module allowing communication between the on-chip processors
1443 * using a queued mailbox-interrupt mechanism.
1444 */
1445
1446 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1447 .rev_offs = 0x000,
1448 .sysc_offs = 0x010,
1449 .syss_offs = 0x014,
1450 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1451 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1452 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1453 .sysc_fields = &omap_hwmod_sysc_type1,
1454 };
1455
1456 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1457 .name = "mailbox",
1458 .sysc = &omap3xxx_mailbox_sysc,
1459 };
1460
1461 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
1462 { .irq = 26 + OMAP_INTC_START, },
1463 { .irq = -1 },
1464 };
1465
1466 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1467 .name = "mailbox",
1468 .class = &omap3xxx_mailbox_hwmod_class,
1469 .mpu_irqs = omap3xxx_mailbox_irqs,
1470 .main_clk = "mailboxes_ick",
1471 .prcm = {
1472 .omap2 = {
1473 .prcm_reg_id = 1,
1474 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1475 .module_offs = CORE_MOD,
1476 .idlest_reg_id = 1,
1477 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1478 },
1479 },
1480 };
1481
1482 /*
1483 * 'mcspi' class
1484 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1485 * bus
1486 */
1487
1488 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1489 .rev_offs = 0x0000,
1490 .sysc_offs = 0x0010,
1491 .syss_offs = 0x0014,
1492 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1493 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1494 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1495 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1496 .sysc_fields = &omap_hwmod_sysc_type1,
1497 };
1498
1499 static struct omap_hwmod_class omap34xx_mcspi_class = {
1500 .name = "mcspi",
1501 .sysc = &omap34xx_mcspi_sysc,
1502 .rev = OMAP3_MCSPI_REV,
1503 };
1504
1505 /* mcspi1 */
1506 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1507 .num_chipselect = 4,
1508 };
1509
1510 static struct omap_hwmod omap34xx_mcspi1 = {
1511 .name = "mcspi1",
1512 .mpu_irqs = omap2_mcspi1_mpu_irqs,
1513 .sdma_reqs = omap2_mcspi1_sdma_reqs,
1514 .main_clk = "mcspi1_fck",
1515 .prcm = {
1516 .omap2 = {
1517 .module_offs = CORE_MOD,
1518 .prcm_reg_id = 1,
1519 .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
1520 .idlest_reg_id = 1,
1521 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1522 },
1523 },
1524 .class = &omap34xx_mcspi_class,
1525 .dev_attr = &omap_mcspi1_dev_attr,
1526 };
1527
1528 /* mcspi2 */
1529 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1530 .num_chipselect = 2,
1531 };
1532
1533 static struct omap_hwmod omap34xx_mcspi2 = {
1534 .name = "mcspi2",
1535 .mpu_irqs = omap2_mcspi2_mpu_irqs,
1536 .sdma_reqs = omap2_mcspi2_sdma_reqs,
1537 .main_clk = "mcspi2_fck",
1538 .prcm = {
1539 .omap2 = {
1540 .module_offs = CORE_MOD,
1541 .prcm_reg_id = 1,
1542 .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
1543 .idlest_reg_id = 1,
1544 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1545 },
1546 },
1547 .class = &omap34xx_mcspi_class,
1548 .dev_attr = &omap_mcspi2_dev_attr,
1549 };
1550
1551 /* mcspi3 */
1552 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
1553 { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */
1554 { .irq = -1 },
1555 };
1556
1557 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
1558 { .name = "tx0", .dma_req = 15 },
1559 { .name = "rx0", .dma_req = 16 },
1560 { .name = "tx1", .dma_req = 23 },
1561 { .name = "rx1", .dma_req = 24 },
1562 { .dma_req = -1 }
1563 };
1564
1565 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1566 .num_chipselect = 2,
1567 };
1568
1569 static struct omap_hwmod omap34xx_mcspi3 = {
1570 .name = "mcspi3",
1571 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
1572 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
1573 .main_clk = "mcspi3_fck",
1574 .prcm = {
1575 .omap2 = {
1576 .module_offs = CORE_MOD,
1577 .prcm_reg_id = 1,
1578 .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
1579 .idlest_reg_id = 1,
1580 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1581 },
1582 },
1583 .class = &omap34xx_mcspi_class,
1584 .dev_attr = &omap_mcspi3_dev_attr,
1585 };
1586
1587 /* mcspi4 */
1588 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
1589 { .name = "irq", .irq = 48 + OMAP_INTC_START, },
1590 { .irq = -1 },
1591 };
1592
1593 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
1594 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
1595 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
1596 { .dma_req = -1 }
1597 };
1598
1599 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1600 .num_chipselect = 1,
1601 };
1602
1603 static struct omap_hwmod omap34xx_mcspi4 = {
1604 .name = "mcspi4",
1605 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
1606 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
1607 .main_clk = "mcspi4_fck",
1608 .prcm = {
1609 .omap2 = {
1610 .module_offs = CORE_MOD,
1611 .prcm_reg_id = 1,
1612 .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
1613 .idlest_reg_id = 1,
1614 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1615 },
1616 },
1617 .class = &omap34xx_mcspi_class,
1618 .dev_attr = &omap_mcspi4_dev_attr,
1619 };
1620
1621 /* usbhsotg */
1622 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1623 .rev_offs = 0x0400,
1624 .sysc_offs = 0x0404,
1625 .syss_offs = 0x0408,
1626 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1627 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1628 SYSC_HAS_AUTOIDLE),
1629 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1630 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1631 .sysc_fields = &omap_hwmod_sysc_type1,
1632 };
1633
1634 static struct omap_hwmod_class usbotg_class = {
1635 .name = "usbotg",
1636 .sysc = &omap3xxx_usbhsotg_sysc,
1637 };
1638
1639 /* usb_otg_hs */
1640 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
1641
1642 { .name = "mc", .irq = 92 + OMAP_INTC_START, },
1643 { .name = "dma", .irq = 93 + OMAP_INTC_START, },
1644 { .irq = -1 },
1645 };
1646
1647 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1648 .name = "usb_otg_hs",
1649 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
1650 .main_clk = "hsotgusb_ick",
1651 .prcm = {
1652 .omap2 = {
1653 .prcm_reg_id = 1,
1654 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1655 .module_offs = CORE_MOD,
1656 .idlest_reg_id = 1,
1657 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1658 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
1659 },
1660 },
1661 .class = &usbotg_class,
1662
1663 /*
1664 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
1665 * broken when autoidle is enabled
1666 * workaround is to disable the autoidle bit at module level.
1667 */
1668 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
1669 | HWMOD_SWSUP_MSTANDBY,
1670 };
1671
1672 /* usb_otg_hs */
1673 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
1674 { .name = "mc", .irq = 71 + OMAP_INTC_START, },
1675 { .irq = -1 },
1676 };
1677
1678 static struct omap_hwmod_class am35xx_usbotg_class = {
1679 .name = "am35xx_usbotg",
1680 };
1681
1682 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1683 .name = "am35x_otg_hs",
1684 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
1685 .main_clk = "hsotgusb_fck",
1686 .class = &am35xx_usbotg_class,
1687 .flags = HWMOD_NO_IDLEST,
1688 };
1689
1690 /* MMC/SD/SDIO common */
1691 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1692 .rev_offs = 0x1fc,
1693 .sysc_offs = 0x10,
1694 .syss_offs = 0x14,
1695 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1696 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1697 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1698 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1699 .sysc_fields = &omap_hwmod_sysc_type1,
1700 };
1701
1702 static struct omap_hwmod_class omap34xx_mmc_class = {
1703 .name = "mmc",
1704 .sysc = &omap34xx_mmc_sysc,
1705 };
1706
1707 /* MMC/SD/SDIO1 */
1708
1709 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
1710 { .irq = 83 + OMAP_INTC_START, },
1711 { .irq = -1 },
1712 };
1713
1714 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
1715 { .name = "tx", .dma_req = 61, },
1716 { .name = "rx", .dma_req = 62, },
1717 { .dma_req = -1 }
1718 };
1719
1720 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1721 { .role = "dbck", .clk = "omap_32k_fck", },
1722 };
1723
1724 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1725 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1726 };
1727
1728 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1729 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
1730 .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1731 OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1732 };
1733
1734 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1735 .name = "mmc1",
1736 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
1737 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
1738 .opt_clks = omap34xx_mmc1_opt_clks,
1739 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1740 .main_clk = "mmchs1_fck",
1741 .prcm = {
1742 .omap2 = {
1743 .module_offs = CORE_MOD,
1744 .prcm_reg_id = 1,
1745 .module_bit = OMAP3430_EN_MMC1_SHIFT,
1746 .idlest_reg_id = 1,
1747 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1748 },
1749 },
1750 .dev_attr = &mmc1_pre_es3_dev_attr,
1751 .class = &omap34xx_mmc_class,
1752 };
1753
1754 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1755 .name = "mmc1",
1756 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
1757 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
1758 .opt_clks = omap34xx_mmc1_opt_clks,
1759 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1760 .main_clk = "mmchs1_fck",
1761 .prcm = {
1762 .omap2 = {
1763 .module_offs = CORE_MOD,
1764 .prcm_reg_id = 1,
1765 .module_bit = OMAP3430_EN_MMC1_SHIFT,
1766 .idlest_reg_id = 1,
1767 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1768 },
1769 },
1770 .dev_attr = &mmc1_dev_attr,
1771 .class = &omap34xx_mmc_class,
1772 };
1773
1774 /* MMC/SD/SDIO2 */
1775
1776 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
1777 { .irq = 86 + OMAP_INTC_START, },
1778 { .irq = -1 },
1779 };
1780
1781 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
1782 { .name = "tx", .dma_req = 47, },
1783 { .name = "rx", .dma_req = 48, },
1784 { .dma_req = -1 }
1785 };
1786
1787 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1788 { .role = "dbck", .clk = "omap_32k_fck", },
1789 };
1790
1791 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1792 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
1793 .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1794 };
1795
1796 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1797 .name = "mmc2",
1798 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
1799 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
1800 .opt_clks = omap34xx_mmc2_opt_clks,
1801 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1802 .main_clk = "mmchs2_fck",
1803 .prcm = {
1804 .omap2 = {
1805 .module_offs = CORE_MOD,
1806 .prcm_reg_id = 1,
1807 .module_bit = OMAP3430_EN_MMC2_SHIFT,
1808 .idlest_reg_id = 1,
1809 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1810 },
1811 },
1812 .dev_attr = &mmc2_pre_es3_dev_attr,
1813 .class = &omap34xx_mmc_class,
1814 };
1815
1816 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1817 .name = "mmc2",
1818 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
1819 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
1820 .opt_clks = omap34xx_mmc2_opt_clks,
1821 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1822 .main_clk = "mmchs2_fck",
1823 .prcm = {
1824 .omap2 = {
1825 .module_offs = CORE_MOD,
1826 .prcm_reg_id = 1,
1827 .module_bit = OMAP3430_EN_MMC2_SHIFT,
1828 .idlest_reg_id = 1,
1829 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1830 },
1831 },
1832 .class = &omap34xx_mmc_class,
1833 };
1834
1835 /* MMC/SD/SDIO3 */
1836
1837 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
1838 { .irq = 94 + OMAP_INTC_START, },
1839 { .irq = -1 },
1840 };
1841
1842 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
1843 { .name = "tx", .dma_req = 77, },
1844 { .name = "rx", .dma_req = 78, },
1845 { .dma_req = -1 }
1846 };
1847
1848 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1849 { .role = "dbck", .clk = "omap_32k_fck", },
1850 };
1851
1852 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1853 .name = "mmc3",
1854 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
1855 .sdma_reqs = omap34xx_mmc3_sdma_reqs,
1856 .opt_clks = omap34xx_mmc3_opt_clks,
1857 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1858 .main_clk = "mmchs3_fck",
1859 .prcm = {
1860 .omap2 = {
1861 .prcm_reg_id = 1,
1862 .module_bit = OMAP3430_EN_MMC3_SHIFT,
1863 .idlest_reg_id = 1,
1864 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1865 },
1866 },
1867 .class = &omap34xx_mmc_class,
1868 };
1869
1870 /*
1871 * 'usb_host_hs' class
1872 * high-speed multi-port usb host controller
1873 */
1874
1875 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1876 .rev_offs = 0x0000,
1877 .sysc_offs = 0x0010,
1878 .syss_offs = 0x0014,
1879 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1880 SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1881 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1882 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1883 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1884 .sysc_fields = &omap_hwmod_sysc_type1,
1885 };
1886
1887 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1888 .name = "usb_host_hs",
1889 .sysc = &omap3xxx_usb_host_hs_sysc,
1890 };
1891
1892 static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
1893 { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
1894 };
1895
1896 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
1897 { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, },
1898 { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, },
1899 { .irq = -1 },
1900 };
1901
1902 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1903 .name = "usb_host_hs",
1904 .class = &omap3xxx_usb_host_hs_hwmod_class,
1905 .clkdm_name = "l3_init_clkdm",
1906 .mpu_irqs = omap3xxx_usb_host_hs_irqs,
1907 .main_clk = "usbhost_48m_fck",
1908 .prcm = {
1909 .omap2 = {
1910 .module_offs = OMAP3430ES2_USBHOST_MOD,
1911 .prcm_reg_id = 1,
1912 .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
1913 .idlest_reg_id = 1,
1914 .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1915 .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
1916 },
1917 },
1918 .opt_clks = omap3xxx_usb_host_hs_opt_clks,
1919 .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
1920
1921 /*
1922 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1923 * id: i660
1924 *
1925 * Description:
1926 * In the following configuration :
1927 * - USBHOST module is set to smart-idle mode
1928 * - PRCM asserts idle_req to the USBHOST module ( This typically
1929 * happens when the system is going to a low power mode : all ports
1930 * have been suspended, the master part of the USBHOST module has
1931 * entered the standby state, and SW has cut the functional clocks)
1932 * - an USBHOST interrupt occurs before the module is able to answer
1933 * idle_ack, typically a remote wakeup IRQ.
1934 * Then the USB HOST module will enter a deadlock situation where it
1935 * is no more accessible nor functional.
1936 *
1937 * Workaround:
1938 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1939 */
1940
1941 /*
1942 * Errata: USB host EHCI may stall when entering smart-standby mode
1943 * Id: i571
1944 *
1945 * Description:
1946 * When the USBHOST module is set to smart-standby mode, and when it is
1947 * ready to enter the standby state (i.e. all ports are suspended and
1948 * all attached devices are in suspend mode), then it can wrongly assert
1949 * the Mstandby signal too early while there are still some residual OCP
1950 * transactions ongoing. If this condition occurs, the internal state
1951 * machine may go to an undefined state and the USB link may be stuck
1952 * upon the next resume.
1953 *
1954 * Workaround:
1955 * Don't use smart standby; use only force standby,
1956 * hence HWMOD_SWSUP_MSTANDBY
1957 */
1958
1959 /*
1960 * During system boot; If the hwmod framework resets the module
1961 * the module will have smart idle settings; which can lead to deadlock
1962 * (above Errata Id:i660); so, dont reset the module during boot;
1963 * Use HWMOD_INIT_NO_RESET.
1964 */
1965
1966 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
1967 HWMOD_INIT_NO_RESET,
1968 };
1969
1970 /*
1971 * 'usb_tll_hs' class
1972 * usb_tll_hs module is the adapter on the usb_host_hs ports
1973 */
1974 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
1975 .rev_offs = 0x0000,
1976 .sysc_offs = 0x0010,
1977 .syss_offs = 0x0014,
1978 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1979 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1980 SYSC_HAS_AUTOIDLE),
1981 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1982 .sysc_fields = &omap_hwmod_sysc_type1,
1983 };
1984
1985 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
1986 .name = "usb_tll_hs",
1987 .sysc = &omap3xxx_usb_tll_hs_sysc,
1988 };
1989
1990 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
1991 { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, },
1992 { .irq = -1 },
1993 };
1994
1995 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
1996 .name = "usb_tll_hs",
1997 .class = &omap3xxx_usb_tll_hs_hwmod_class,
1998 .clkdm_name = "l3_init_clkdm",
1999 .mpu_irqs = omap3xxx_usb_tll_hs_irqs,
2000 .main_clk = "usbtll_fck",
2001 .prcm = {
2002 .omap2 = {
2003 .module_offs = CORE_MOD,
2004 .prcm_reg_id = 3,
2005 .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
2006 .idlest_reg_id = 3,
2007 .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
2008 },
2009 },
2010 };
2011
2012 static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
2013 .name = "hdq1w",
2014 .mpu_irqs = omap2_hdq1w_mpu_irqs,
2015 .main_clk = "hdq_fck",
2016 .prcm = {
2017 .omap2 = {
2018 .module_offs = CORE_MOD,
2019 .prcm_reg_id = 1,
2020 .module_bit = OMAP3430_EN_HDQ_SHIFT,
2021 .idlest_reg_id = 1,
2022 .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
2023 },
2024 },
2025 .class = &omap2_hdq1w_class,
2026 };
2027
2028 /*
2029 * '32K sync counter' class
2030 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
2031 */
2032 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
2033 .rev_offs = 0x0000,
2034 .sysc_offs = 0x0004,
2035 .sysc_flags = SYSC_HAS_SIDLEMODE,
2036 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
2037 .sysc_fields = &omap_hwmod_sysc_type1,
2038 };
2039
2040 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
2041 .name = "counter",
2042 .sysc = &omap3xxx_counter_sysc,
2043 };
2044
2045 static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
2046 .name = "counter_32k",
2047 .class = &omap3xxx_counter_hwmod_class,
2048 .clkdm_name = "wkup_clkdm",
2049 .flags = HWMOD_SWSUP_SIDLE,
2050 .main_clk = "wkup_32k_fck",
2051 .prcm = {
2052 .omap2 = {
2053 .module_offs = WKUP_MOD,
2054 .prcm_reg_id = 1,
2055 .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
2056 .idlest_reg_id = 1,
2057 .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
2058 },
2059 },
2060 };
2061
2062 /*
2063 * interfaces
2064 */
2065
2066 /* L3 -> L4_CORE interface */
2067 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
2068 .master = &omap3xxx_l3_main_hwmod,
2069 .slave = &omap3xxx_l4_core_hwmod,
2070 .user = OCP_USER_MPU | OCP_USER_SDMA,
2071 };
2072
2073 /* L3 -> L4_PER interface */
2074 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
2075 .master = &omap3xxx_l3_main_hwmod,
2076 .slave = &omap3xxx_l4_per_hwmod,
2077 .user = OCP_USER_MPU | OCP_USER_SDMA,
2078 };
2079
2080 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
2081 {
2082 .pa_start = 0x68000000,
2083 .pa_end = 0x6800ffff,
2084 .flags = ADDR_TYPE_RT,
2085 },
2086 { }
2087 };
2088
2089 /* MPU -> L3 interface */
2090 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
2091 .master = &omap3xxx_mpu_hwmod,
2092 .slave = &omap3xxx_l3_main_hwmod,
2093 .addr = omap3xxx_l3_main_addrs,
2094 .user = OCP_USER_MPU,
2095 };
2096
2097 /* DSS -> l3 */
2098 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
2099 .master = &omap3430es1_dss_core_hwmod,
2100 .slave = &omap3xxx_l3_main_hwmod,
2101 .user = OCP_USER_MPU | OCP_USER_SDMA,
2102 };
2103
2104 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
2105 .master = &omap3xxx_dss_core_hwmod,
2106 .slave = &omap3xxx_l3_main_hwmod,
2107 .fw = {
2108 .omap2 = {
2109 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
2110 .flags = OMAP_FIREWALL_L3,
2111 }
2112 },
2113 .user = OCP_USER_MPU | OCP_USER_SDMA,
2114 };
2115
2116 /* l3_core -> usbhsotg interface */
2117 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
2118 .master = &omap3xxx_usbhsotg_hwmod,
2119 .slave = &omap3xxx_l3_main_hwmod,
2120 .clk = "core_l3_ick",
2121 .user = OCP_USER_MPU,
2122 };
2123
2124 /* l3_core -> am35xx_usbhsotg interface */
2125 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
2126 .master = &am35xx_usbhsotg_hwmod,
2127 .slave = &omap3xxx_l3_main_hwmod,
2128 .clk = "hsotgusb_ick",
2129 .user = OCP_USER_MPU,
2130 };
2131
2132 /* L4_CORE -> L4_WKUP interface */
2133 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
2134 .master = &omap3xxx_l4_core_hwmod,
2135 .slave = &omap3xxx_l4_wkup_hwmod,
2136 .user = OCP_USER_MPU | OCP_USER_SDMA,
2137 };
2138
2139 /* L4 CORE -> MMC1 interface */
2140 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
2141 .master = &omap3xxx_l4_core_hwmod,
2142 .slave = &omap3xxx_pre_es3_mmc1_hwmod,
2143 .clk = "mmchs1_ick",
2144 .addr = omap2430_mmc1_addr_space,
2145 .user = OCP_USER_MPU | OCP_USER_SDMA,
2146 .flags = OMAP_FIREWALL_L4
2147 };
2148
2149 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
2150 .master = &omap3xxx_l4_core_hwmod,
2151 .slave = &omap3xxx_es3plus_mmc1_hwmod,
2152 .clk = "mmchs1_ick",
2153 .addr = omap2430_mmc1_addr_space,
2154 .user = OCP_USER_MPU | OCP_USER_SDMA,
2155 .flags = OMAP_FIREWALL_L4
2156 };
2157
2158 /* L4 CORE -> MMC2 interface */
2159 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
2160 .master = &omap3xxx_l4_core_hwmod,
2161 .slave = &omap3xxx_pre_es3_mmc2_hwmod,
2162 .clk = "mmchs2_ick",
2163 .addr = omap2430_mmc2_addr_space,
2164 .user = OCP_USER_MPU | OCP_USER_SDMA,
2165 .flags = OMAP_FIREWALL_L4
2166 };
2167
2168 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2169 .master = &omap3xxx_l4_core_hwmod,
2170 .slave = &omap3xxx_es3plus_mmc2_hwmod,
2171 .clk = "mmchs2_ick",
2172 .addr = omap2430_mmc2_addr_space,
2173 .user = OCP_USER_MPU | OCP_USER_SDMA,
2174 .flags = OMAP_FIREWALL_L4
2175 };
2176
2177 /* L4 CORE -> MMC3 interface */
2178 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
2179 {
2180 .pa_start = 0x480ad000,
2181 .pa_end = 0x480ad1ff,
2182 .flags = ADDR_TYPE_RT,
2183 },
2184 { }
2185 };
2186
2187 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2188 .master = &omap3xxx_l4_core_hwmod,
2189 .slave = &omap3xxx_mmc3_hwmod,
2190 .clk = "mmchs3_ick",
2191 .addr = omap3xxx_mmc3_addr_space,
2192 .user = OCP_USER_MPU | OCP_USER_SDMA,
2193 .flags = OMAP_FIREWALL_L4
2194 };
2195
2196 /* L4 CORE -> UART1 interface */
2197 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
2198 {
2199 .pa_start = OMAP3_UART1_BASE,
2200 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
2201 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2202 },
2203 { }
2204 };
2205
2206 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2207 .master = &omap3xxx_l4_core_hwmod,
2208 .slave = &omap3xxx_uart1_hwmod,
2209 .clk = "uart1_ick",
2210 .addr = omap3xxx_uart1_addr_space,
2211 .user = OCP_USER_MPU | OCP_USER_SDMA,
2212 };
2213
2214 /* L4 CORE -> UART2 interface */
2215 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
2216 {
2217 .pa_start = OMAP3_UART2_BASE,
2218 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
2219 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2220 },
2221 { }
2222 };
2223
2224 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2225 .master = &omap3xxx_l4_core_hwmod,
2226 .slave = &omap3xxx_uart2_hwmod,
2227 .clk = "uart2_ick",
2228 .addr = omap3xxx_uart2_addr_space,
2229 .user = OCP_USER_MPU | OCP_USER_SDMA,
2230 };
2231
2232 /* L4 PER -> UART3 interface */
2233 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
2234 {
2235 .pa_start = OMAP3_UART3_BASE,
2236 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
2237 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2238 },
2239 { }
2240 };
2241
2242 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2243 .master = &omap3xxx_l4_per_hwmod,
2244 .slave = &omap3xxx_uart3_hwmod,
2245 .clk = "uart3_ick",
2246 .addr = omap3xxx_uart3_addr_space,
2247 .user = OCP_USER_MPU | OCP_USER_SDMA,
2248 };
2249
2250 /* L4 PER -> UART4 interface */
2251 static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
2252 {
2253 .pa_start = OMAP3_UART4_BASE,
2254 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
2255 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2256 },
2257 { }
2258 };
2259
2260 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2261 .master = &omap3xxx_l4_per_hwmod,
2262 .slave = &omap36xx_uart4_hwmod,
2263 .clk = "uart4_ick",
2264 .addr = omap36xx_uart4_addr_space,
2265 .user = OCP_USER_MPU | OCP_USER_SDMA,
2266 };
2267
2268 /* AM35xx: L4 CORE -> UART4 interface */
2269 static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
2270 {
2271 .pa_start = OMAP3_UART4_AM35XX_BASE,
2272 .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
2273 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2274 },
2275 { }
2276 };
2277
2278 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2279 .master = &omap3xxx_l4_core_hwmod,
2280 .slave = &am35xx_uart4_hwmod,
2281 .clk = "uart4_ick",
2282 .addr = am35xx_uart4_addr_space,
2283 .user = OCP_USER_MPU | OCP_USER_SDMA,
2284 };
2285
2286 /* L4 CORE -> I2C1 interface */
2287 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2288 .master = &omap3xxx_l4_core_hwmod,
2289 .slave = &omap3xxx_i2c1_hwmod,
2290 .clk = "i2c1_ick",
2291 .addr = omap2_i2c1_addr_space,
2292 .fw = {
2293 .omap2 = {
2294 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
2295 .l4_prot_group = 7,
2296 .flags = OMAP_FIREWALL_L4,
2297 }
2298 },
2299 .user = OCP_USER_MPU | OCP_USER_SDMA,
2300 };
2301
2302 /* L4 CORE -> I2C2 interface */
2303 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2304 .master = &omap3xxx_l4_core_hwmod,
2305 .slave = &omap3xxx_i2c2_hwmod,
2306 .clk = "i2c2_ick",
2307 .addr = omap2_i2c2_addr_space,
2308 .fw = {
2309 .omap2 = {
2310 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
2311 .l4_prot_group = 7,
2312 .flags = OMAP_FIREWALL_L4,
2313 }
2314 },
2315 .user = OCP_USER_MPU | OCP_USER_SDMA,
2316 };
2317
2318 /* L4 CORE -> I2C3 interface */
2319 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
2320 {
2321 .pa_start = 0x48060000,
2322 .pa_end = 0x48060000 + SZ_128 - 1,
2323 .flags = ADDR_TYPE_RT,
2324 },
2325 { }
2326 };
2327
2328 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2329 .master = &omap3xxx_l4_core_hwmod,
2330 .slave = &omap3xxx_i2c3_hwmod,
2331 .clk = "i2c3_ick",
2332 .addr = omap3xxx_i2c3_addr_space,
2333 .fw = {
2334 .omap2 = {
2335 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
2336 .l4_prot_group = 7,
2337 .flags = OMAP_FIREWALL_L4,
2338 }
2339 },
2340 .user = OCP_USER_MPU | OCP_USER_SDMA,
2341 };
2342
2343 /* L4 CORE -> SR1 interface */
2344 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
2345 {
2346 .pa_start = OMAP34XX_SR1_BASE,
2347 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
2348 .flags = ADDR_TYPE_RT,
2349 },
2350 { }
2351 };
2352
2353 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2354 .master = &omap3xxx_l4_core_hwmod,
2355 .slave = &omap34xx_sr1_hwmod,
2356 .clk = "sr_l4_ick",
2357 .addr = omap3_sr1_addr_space,
2358 .user = OCP_USER_MPU,
2359 };
2360
2361 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2362 .master = &omap3xxx_l4_core_hwmod,
2363 .slave = &omap36xx_sr1_hwmod,
2364 .clk = "sr_l4_ick",
2365 .addr = omap3_sr1_addr_space,
2366 .user = OCP_USER_MPU,
2367 };
2368
2369 /* L4 CORE -> SR1 interface */
2370 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
2371 {
2372 .pa_start = OMAP34XX_SR2_BASE,
2373 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
2374 .flags = ADDR_TYPE_RT,
2375 },
2376 { }
2377 };
2378
2379 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2380 .master = &omap3xxx_l4_core_hwmod,
2381 .slave = &omap34xx_sr2_hwmod,
2382 .clk = "sr_l4_ick",
2383 .addr = omap3_sr2_addr_space,
2384 .user = OCP_USER_MPU,
2385 };
2386
2387 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2388 .master = &omap3xxx_l4_core_hwmod,
2389 .slave = &omap36xx_sr2_hwmod,
2390 .clk = "sr_l4_ick",
2391 .addr = omap3_sr2_addr_space,
2392 .user = OCP_USER_MPU,
2393 };
2394
2395 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
2396 {
2397 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
2398 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
2399 .flags = ADDR_TYPE_RT
2400 },
2401 { }
2402 };
2403
2404 /* l4_core -> usbhsotg */
2405 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2406 .master = &omap3xxx_l4_core_hwmod,
2407 .slave = &omap3xxx_usbhsotg_hwmod,
2408 .clk = "l4_ick",
2409 .addr = omap3xxx_usbhsotg_addrs,
2410 .user = OCP_USER_MPU,
2411 };
2412
2413 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
2414 {
2415 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
2416 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
2417 .flags = ADDR_TYPE_RT
2418 },
2419 { }
2420 };
2421
2422 /* l4_core -> usbhsotg */
2423 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2424 .master = &omap3xxx_l4_core_hwmod,
2425 .slave = &am35xx_usbhsotg_hwmod,
2426 .clk = "hsotgusb_ick",
2427 .addr = am35xx_usbhsotg_addrs,
2428 .user = OCP_USER_MPU,
2429 };
2430
2431 /* L4_WKUP -> L4_SEC interface */
2432 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2433 .master = &omap3xxx_l4_wkup_hwmod,
2434 .slave = &omap3xxx_l4_sec_hwmod,
2435 .user = OCP_USER_MPU | OCP_USER_SDMA,
2436 };
2437
2438 /* IVA2 <- L3 interface */
2439 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2440 .master = &omap3xxx_l3_main_hwmod,
2441 .slave = &omap3xxx_iva_hwmod,
2442 .clk = "core_l3_ick",
2443 .user = OCP_USER_MPU | OCP_USER_SDMA,
2444 };
2445
2446 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
2447 {
2448 .pa_start = 0x48318000,
2449 .pa_end = 0x48318000 + SZ_1K - 1,
2450 .flags = ADDR_TYPE_RT
2451 },
2452 { }
2453 };
2454
2455 /* l4_wkup -> timer1 */
2456 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2457 .master = &omap3xxx_l4_wkup_hwmod,
2458 .slave = &omap3xxx_timer1_hwmod,
2459 .clk = "gpt1_ick",
2460 .addr = omap3xxx_timer1_addrs,
2461 .user = OCP_USER_MPU | OCP_USER_SDMA,
2462 };
2463
2464 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
2465 {
2466 .pa_start = 0x49032000,
2467 .pa_end = 0x49032000 + SZ_1K - 1,
2468 .flags = ADDR_TYPE_RT
2469 },
2470 { }
2471 };
2472
2473 /* l4_per -> timer2 */
2474 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2475 .master = &omap3xxx_l4_per_hwmod,
2476 .slave = &omap3xxx_timer2_hwmod,
2477 .clk = "gpt2_ick",
2478 .addr = omap3xxx_timer2_addrs,
2479 .user = OCP_USER_MPU | OCP_USER_SDMA,
2480 };
2481
2482 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
2483 {
2484 .pa_start = 0x49034000,
2485 .pa_end = 0x49034000 + SZ_1K - 1,
2486 .flags = ADDR_TYPE_RT
2487 },
2488 { }
2489 };
2490
2491 /* l4_per -> timer3 */
2492 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2493 .master = &omap3xxx_l4_per_hwmod,
2494 .slave = &omap3xxx_timer3_hwmod,
2495 .clk = "gpt3_ick",
2496 .addr = omap3xxx_timer3_addrs,
2497 .user = OCP_USER_MPU | OCP_USER_SDMA,
2498 };
2499
2500 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
2501 {
2502 .pa_start = 0x49036000,
2503 .pa_end = 0x49036000 + SZ_1K - 1,
2504 .flags = ADDR_TYPE_RT
2505 },
2506 { }
2507 };
2508
2509 /* l4_per -> timer4 */
2510 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2511 .master = &omap3xxx_l4_per_hwmod,
2512 .slave = &omap3xxx_timer4_hwmod,
2513 .clk = "gpt4_ick",
2514 .addr = omap3xxx_timer4_addrs,
2515 .user = OCP_USER_MPU | OCP_USER_SDMA,
2516 };
2517
2518 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
2519 {
2520 .pa_start = 0x49038000,
2521 .pa_end = 0x49038000 + SZ_1K - 1,
2522 .flags = ADDR_TYPE_RT
2523 },
2524 { }
2525 };
2526
2527 /* l4_per -> timer5 */
2528 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2529 .master = &omap3xxx_l4_per_hwmod,
2530 .slave = &omap3xxx_timer5_hwmod,
2531 .clk = "gpt5_ick",
2532 .addr = omap3xxx_timer5_addrs,
2533 .user = OCP_USER_MPU | OCP_USER_SDMA,
2534 };
2535
2536 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
2537 {
2538 .pa_start = 0x4903A000,
2539 .pa_end = 0x4903A000 + SZ_1K - 1,
2540 .flags = ADDR_TYPE_RT
2541 },
2542 { }
2543 };
2544
2545 /* l4_per -> timer6 */
2546 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2547 .master = &omap3xxx_l4_per_hwmod,
2548 .slave = &omap3xxx_timer6_hwmod,
2549 .clk = "gpt6_ick",
2550 .addr = omap3xxx_timer6_addrs,
2551 .user = OCP_USER_MPU | OCP_USER_SDMA,
2552 };
2553
2554 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
2555 {
2556 .pa_start = 0x4903C000,
2557 .pa_end = 0x4903C000 + SZ_1K - 1,
2558 .flags = ADDR_TYPE_RT
2559 },
2560 { }
2561 };
2562
2563 /* l4_per -> timer7 */
2564 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2565 .master = &omap3xxx_l4_per_hwmod,
2566 .slave = &omap3xxx_timer7_hwmod,
2567 .clk = "gpt7_ick",
2568 .addr = omap3xxx_timer7_addrs,
2569 .user = OCP_USER_MPU | OCP_USER_SDMA,
2570 };
2571
2572 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
2573 {
2574 .pa_start = 0x4903E000,
2575 .pa_end = 0x4903E000 + SZ_1K - 1,
2576 .flags = ADDR_TYPE_RT
2577 },
2578 { }
2579 };
2580
2581 /* l4_per -> timer8 */
2582 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2583 .master = &omap3xxx_l4_per_hwmod,
2584 .slave = &omap3xxx_timer8_hwmod,
2585 .clk = "gpt8_ick",
2586 .addr = omap3xxx_timer8_addrs,
2587 .user = OCP_USER_MPU | OCP_USER_SDMA,
2588 };
2589
2590 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
2591 {
2592 .pa_start = 0x49040000,
2593 .pa_end = 0x49040000 + SZ_1K - 1,
2594 .flags = ADDR_TYPE_RT
2595 },
2596 { }
2597 };
2598
2599 /* l4_per -> timer9 */
2600 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2601 .master = &omap3xxx_l4_per_hwmod,
2602 .slave = &omap3xxx_timer9_hwmod,
2603 .clk = "gpt9_ick",
2604 .addr = omap3xxx_timer9_addrs,
2605 .user = OCP_USER_MPU | OCP_USER_SDMA,
2606 };
2607
2608 /* l4_core -> timer10 */
2609 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2610 .master = &omap3xxx_l4_core_hwmod,
2611 .slave = &omap3xxx_timer10_hwmod,
2612 .clk = "gpt10_ick",
2613 .addr = omap2_timer10_addrs,
2614 .user = OCP_USER_MPU | OCP_USER_SDMA,
2615 };
2616
2617 /* l4_core -> timer11 */
2618 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2619 .master = &omap3xxx_l4_core_hwmod,
2620 .slave = &omap3xxx_timer11_hwmod,
2621 .clk = "gpt11_ick",
2622 .addr = omap2_timer11_addrs,
2623 .user = OCP_USER_MPU | OCP_USER_SDMA,
2624 };
2625
2626 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
2627 {
2628 .pa_start = 0x48304000,
2629 .pa_end = 0x48304000 + SZ_1K - 1,
2630 .flags = ADDR_TYPE_RT
2631 },
2632 { }
2633 };
2634
2635 /* l4_core -> timer12 */
2636 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2637 .master = &omap3xxx_l4_sec_hwmod,
2638 .slave = &omap3xxx_timer12_hwmod,
2639 .clk = "gpt12_ick",
2640 .addr = omap3xxx_timer12_addrs,
2641 .user = OCP_USER_MPU | OCP_USER_SDMA,
2642 };
2643
2644 /* l4_wkup -> wd_timer2 */
2645 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
2646 {
2647 .pa_start = 0x48314000,
2648 .pa_end = 0x4831407f,
2649 .flags = ADDR_TYPE_RT
2650 },
2651 { }
2652 };
2653
2654 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2655 .master = &omap3xxx_l4_wkup_hwmod,
2656 .slave = &omap3xxx_wd_timer2_hwmod,
2657 .clk = "wdt2_ick",
2658 .addr = omap3xxx_wd_timer2_addrs,
2659 .user = OCP_USER_MPU | OCP_USER_SDMA,
2660 };
2661
2662 /* l4_core -> dss */
2663 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2664 .master = &omap3xxx_l4_core_hwmod,
2665 .slave = &omap3430es1_dss_core_hwmod,
2666 .clk = "dss_ick",
2667 .addr = omap2_dss_addrs,
2668 .fw = {
2669 .omap2 = {
2670 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2671 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2672 .flags = OMAP_FIREWALL_L4,
2673 }
2674 },
2675 .user = OCP_USER_MPU | OCP_USER_SDMA,
2676 };
2677
2678 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2679 .master = &omap3xxx_l4_core_hwmod,
2680 .slave = &omap3xxx_dss_core_hwmod,
2681 .clk = "dss_ick",
2682 .addr = omap2_dss_addrs,
2683 .fw = {
2684 .omap2 = {
2685 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2686 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2687 .flags = OMAP_FIREWALL_L4,
2688 }
2689 },
2690 .user = OCP_USER_MPU | OCP_USER_SDMA,
2691 };
2692
2693 /* l4_core -> dss_dispc */
2694 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2695 .master = &omap3xxx_l4_core_hwmod,
2696 .slave = &omap3xxx_dss_dispc_hwmod,
2697 .clk = "dss_ick",
2698 .addr = omap2_dss_dispc_addrs,
2699 .fw = {
2700 .omap2 = {
2701 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2702 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2703 .flags = OMAP_FIREWALL_L4,
2704 }
2705 },
2706 .user = OCP_USER_MPU | OCP_USER_SDMA,
2707 };
2708
2709 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
2710 {
2711 .pa_start = 0x4804FC00,
2712 .pa_end = 0x4804FFFF,
2713 .flags = ADDR_TYPE_RT
2714 },
2715 { }
2716 };
2717
2718 /* l4_core -> dss_dsi1 */
2719 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2720 .master = &omap3xxx_l4_core_hwmod,
2721 .slave = &omap3xxx_dss_dsi1_hwmod,
2722 .clk = "dss_ick",
2723 .addr = omap3xxx_dss_dsi1_addrs,
2724 .fw = {
2725 .omap2 = {
2726 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2727 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2728 .flags = OMAP_FIREWALL_L4,
2729 }
2730 },
2731 .user = OCP_USER_MPU | OCP_USER_SDMA,
2732 };
2733
2734 /* l4_core -> dss_rfbi */
2735 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2736 .master = &omap3xxx_l4_core_hwmod,
2737 .slave = &omap3xxx_dss_rfbi_hwmod,
2738 .clk = "dss_ick",
2739 .addr = omap2_dss_rfbi_addrs,
2740 .fw = {
2741 .omap2 = {
2742 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2743 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2744 .flags = OMAP_FIREWALL_L4,
2745 }
2746 },
2747 .user = OCP_USER_MPU | OCP_USER_SDMA,
2748 };
2749
2750 /* l4_core -> dss_venc */
2751 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2752 .master = &omap3xxx_l4_core_hwmod,
2753 .slave = &omap3xxx_dss_venc_hwmod,
2754 .clk = "dss_ick",
2755 .addr = omap2_dss_venc_addrs,
2756 .fw = {
2757 .omap2 = {
2758 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2759 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2760 .flags = OMAP_FIREWALL_L4,
2761 }
2762 },
2763 .flags = OCPIF_SWSUP_IDLE,
2764 .user = OCP_USER_MPU | OCP_USER_SDMA,
2765 };
2766
2767 /* l4_wkup -> gpio1 */
2768 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2769 {
2770 .pa_start = 0x48310000,
2771 .pa_end = 0x483101ff,
2772 .flags = ADDR_TYPE_RT
2773 },
2774 { }
2775 };
2776
2777 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2778 .master = &omap3xxx_l4_wkup_hwmod,
2779 .slave = &omap3xxx_gpio1_hwmod,
2780 .addr = omap3xxx_gpio1_addrs,
2781 .user = OCP_USER_MPU | OCP_USER_SDMA,
2782 };
2783
2784 /* l4_per -> gpio2 */
2785 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2786 {
2787 .pa_start = 0x49050000,
2788 .pa_end = 0x490501ff,
2789 .flags = ADDR_TYPE_RT
2790 },
2791 { }
2792 };
2793
2794 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2795 .master = &omap3xxx_l4_per_hwmod,
2796 .slave = &omap3xxx_gpio2_hwmod,
2797 .addr = omap3xxx_gpio2_addrs,
2798 .user = OCP_USER_MPU | OCP_USER_SDMA,
2799 };
2800
2801 /* l4_per -> gpio3 */
2802 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2803 {
2804 .pa_start = 0x49052000,
2805 .pa_end = 0x490521ff,
2806 .flags = ADDR_TYPE_RT
2807 },
2808 { }
2809 };
2810
2811 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2812 .master = &omap3xxx_l4_per_hwmod,
2813 .slave = &omap3xxx_gpio3_hwmod,
2814 .addr = omap3xxx_gpio3_addrs,
2815 .user = OCP_USER_MPU | OCP_USER_SDMA,
2816 };
2817
2818 /* l4_per -> gpio4 */
2819 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
2820 {
2821 .pa_start = 0x49054000,
2822 .pa_end = 0x490541ff,
2823 .flags = ADDR_TYPE_RT
2824 },
2825 { }
2826 };
2827
2828 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
2829 .master = &omap3xxx_l4_per_hwmod,
2830 .slave = &omap3xxx_gpio4_hwmod,
2831 .addr = omap3xxx_gpio4_addrs,
2832 .user = OCP_USER_MPU | OCP_USER_SDMA,
2833 };
2834
2835 /* l4_per -> gpio5 */
2836 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
2837 {
2838 .pa_start = 0x49056000,
2839 .pa_end = 0x490561ff,
2840 .flags = ADDR_TYPE_RT
2841 },
2842 { }
2843 };
2844
2845 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
2846 .master = &omap3xxx_l4_per_hwmod,
2847 .slave = &omap3xxx_gpio5_hwmod,
2848 .addr = omap3xxx_gpio5_addrs,
2849 .user = OCP_USER_MPU | OCP_USER_SDMA,
2850 };
2851
2852 /* l4_per -> gpio6 */
2853 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
2854 {
2855 .pa_start = 0x49058000,
2856 .pa_end = 0x490581ff,
2857 .flags = ADDR_TYPE_RT
2858 },
2859 { }
2860 };
2861
2862 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
2863 .master = &omap3xxx_l4_per_hwmod,
2864 .slave = &omap3xxx_gpio6_hwmod,
2865 .addr = omap3xxx_gpio6_addrs,
2866 .user = OCP_USER_MPU | OCP_USER_SDMA,
2867 };
2868
2869 /* dma_system -> L3 */
2870 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2871 .master = &omap3xxx_dma_system_hwmod,
2872 .slave = &omap3xxx_l3_main_hwmod,
2873 .clk = "core_l3_ick",
2874 .user = OCP_USER_MPU | OCP_USER_SDMA,
2875 };
2876
2877 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2878 {
2879 .pa_start = 0x48056000,
2880 .pa_end = 0x48056fff,
2881 .flags = ADDR_TYPE_RT
2882 },
2883 { }
2884 };
2885
2886 /* l4_cfg -> dma_system */
2887 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2888 .master = &omap3xxx_l4_core_hwmod,
2889 .slave = &omap3xxx_dma_system_hwmod,
2890 .clk = "core_l4_ick",
2891 .addr = omap3xxx_dma_system_addrs,
2892 .user = OCP_USER_MPU | OCP_USER_SDMA,
2893 };
2894
2895 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2896 {
2897 .name = "mpu",
2898 .pa_start = 0x48074000,
2899 .pa_end = 0x480740ff,
2900 .flags = ADDR_TYPE_RT
2901 },
2902 { }
2903 };
2904
2905 /* l4_core -> mcbsp1 */
2906 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2907 .master = &omap3xxx_l4_core_hwmod,
2908 .slave = &omap3xxx_mcbsp1_hwmod,
2909 .clk = "mcbsp1_ick",
2910 .addr = omap3xxx_mcbsp1_addrs,
2911 .user = OCP_USER_MPU | OCP_USER_SDMA,
2912 };
2913
2914 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2915 {
2916 .name = "mpu",
2917 .pa_start = 0x49022000,
2918 .pa_end = 0x490220ff,
2919 .flags = ADDR_TYPE_RT
2920 },
2921 { }
2922 };
2923
2924 /* l4_per -> mcbsp2 */
2925 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2926 .master = &omap3xxx_l4_per_hwmod,
2927 .slave = &omap3xxx_mcbsp2_hwmod,
2928 .clk = "mcbsp2_ick",
2929 .addr = omap3xxx_mcbsp2_addrs,
2930 .user = OCP_USER_MPU | OCP_USER_SDMA,
2931 };
2932
2933 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2934 {
2935 .name = "mpu",
2936 .pa_start = 0x49024000,
2937 .pa_end = 0x490240ff,
2938 .flags = ADDR_TYPE_RT
2939 },
2940 { }
2941 };
2942
2943 /* l4_per -> mcbsp3 */
2944 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2945 .master = &omap3xxx_l4_per_hwmod,
2946 .slave = &omap3xxx_mcbsp3_hwmod,
2947 .clk = "mcbsp3_ick",
2948 .addr = omap3xxx_mcbsp3_addrs,
2949 .user = OCP_USER_MPU | OCP_USER_SDMA,
2950 };
2951
2952 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2953 {
2954 .name = "mpu",
2955 .pa_start = 0x49026000,
2956 .pa_end = 0x490260ff,
2957 .flags = ADDR_TYPE_RT
2958 },
2959 { }
2960 };
2961
2962 /* l4_per -> mcbsp4 */
2963 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2964 .master = &omap3xxx_l4_per_hwmod,
2965 .slave = &omap3xxx_mcbsp4_hwmod,
2966 .clk = "mcbsp4_ick",
2967 .addr = omap3xxx_mcbsp4_addrs,
2968 .user = OCP_USER_MPU | OCP_USER_SDMA,
2969 };
2970
2971 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2972 {
2973 .name = "mpu",
2974 .pa_start = 0x48096000,
2975 .pa_end = 0x480960ff,
2976 .flags = ADDR_TYPE_RT
2977 },
2978 { }
2979 };
2980
2981 /* l4_core -> mcbsp5 */
2982 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2983 .master = &omap3xxx_l4_core_hwmod,
2984 .slave = &omap3xxx_mcbsp5_hwmod,
2985 .clk = "mcbsp5_ick",
2986 .addr = omap3xxx_mcbsp5_addrs,
2987 .user = OCP_USER_MPU | OCP_USER_SDMA,
2988 };
2989
2990 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2991 {
2992 .name = "sidetone",
2993 .pa_start = 0x49028000,
2994 .pa_end = 0x490280ff,
2995 .flags = ADDR_TYPE_RT
2996 },
2997 { }
2998 };
2999
3000 /* l4_per -> mcbsp2_sidetone */
3001 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
3002 .master = &omap3xxx_l4_per_hwmod,
3003 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
3004 .clk = "mcbsp2_ick",
3005 .addr = omap3xxx_mcbsp2_sidetone_addrs,
3006 .user = OCP_USER_MPU,
3007 };
3008
3009 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
3010 {
3011 .name = "sidetone",
3012 .pa_start = 0x4902A000,
3013 .pa_end = 0x4902A0ff,
3014 .flags = ADDR_TYPE_RT
3015 },
3016 { }
3017 };
3018
3019 /* l4_per -> mcbsp3_sidetone */
3020 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
3021 .master = &omap3xxx_l4_per_hwmod,
3022 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
3023 .clk = "mcbsp3_ick",
3024 .addr = omap3xxx_mcbsp3_sidetone_addrs,
3025 .user = OCP_USER_MPU,
3026 };
3027
3028 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
3029 {
3030 .pa_start = 0x48094000,
3031 .pa_end = 0x480941ff,
3032 .flags = ADDR_TYPE_RT,
3033 },
3034 { }
3035 };
3036
3037 /* l4_core -> mailbox */
3038 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3039 .master = &omap3xxx_l4_core_hwmod,
3040 .slave = &omap3xxx_mailbox_hwmod,
3041 .addr = omap3xxx_mailbox_addrs,
3042 .user = OCP_USER_MPU | OCP_USER_SDMA,
3043 };
3044
3045 /* l4 core -> mcspi1 interface */
3046 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3047 .master = &omap3xxx_l4_core_hwmod,
3048 .slave = &omap34xx_mcspi1,
3049 .clk = "mcspi1_ick",
3050 .addr = omap2_mcspi1_addr_space,
3051 .user = OCP_USER_MPU | OCP_USER_SDMA,
3052 };
3053
3054 /* l4 core -> mcspi2 interface */
3055 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3056 .master = &omap3xxx_l4_core_hwmod,
3057 .slave = &omap34xx_mcspi2,
3058 .clk = "mcspi2_ick",
3059 .addr = omap2_mcspi2_addr_space,
3060 .user = OCP_USER_MPU | OCP_USER_SDMA,
3061 };
3062
3063 /* l4 core -> mcspi3 interface */
3064 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3065 .master = &omap3xxx_l4_core_hwmod,
3066 .slave = &omap34xx_mcspi3,
3067 .clk = "mcspi3_ick",
3068 .addr = omap2430_mcspi3_addr_space,
3069 .user = OCP_USER_MPU | OCP_USER_SDMA,
3070 };
3071
3072 /* l4 core -> mcspi4 interface */
3073 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3074 {
3075 .pa_start = 0x480ba000,
3076 .pa_end = 0x480ba0ff,
3077 .flags = ADDR_TYPE_RT,
3078 },
3079 { }
3080 };
3081
3082 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3083 .master = &omap3xxx_l4_core_hwmod,
3084 .slave = &omap34xx_mcspi4,
3085 .clk = "mcspi4_ick",
3086 .addr = omap34xx_mcspi4_addr_space,
3087 .user = OCP_USER_MPU | OCP_USER_SDMA,
3088 };
3089
3090 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3091 .master = &omap3xxx_usb_host_hs_hwmod,
3092 .slave = &omap3xxx_l3_main_hwmod,
3093 .clk = "core_l3_ick",
3094 .user = OCP_USER_MPU,
3095 };
3096
3097 static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3098 {
3099 .name = "uhh",
3100 .pa_start = 0x48064000,
3101 .pa_end = 0x480643ff,
3102 .flags = ADDR_TYPE_RT
3103 },
3104 {
3105 .name = "ohci",
3106 .pa_start = 0x48064400,
3107 .pa_end = 0x480647ff,
3108 },
3109 {
3110 .name = "ehci",
3111 .pa_start = 0x48064800,
3112 .pa_end = 0x48064cff,
3113 },
3114 {}
3115 };
3116
3117 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3118 .master = &omap3xxx_l4_core_hwmod,
3119 .slave = &omap3xxx_usb_host_hs_hwmod,
3120 .clk = "usbhost_ick",
3121 .addr = omap3xxx_usb_host_hs_addrs,
3122 .user = OCP_USER_MPU | OCP_USER_SDMA,
3123 };
3124
3125 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3126 {
3127 .name = "tll",
3128 .pa_start = 0x48062000,
3129 .pa_end = 0x48062fff,
3130 .flags = ADDR_TYPE_RT
3131 },
3132 {}
3133 };
3134
3135 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3136 .master = &omap3xxx_l4_core_hwmod,
3137 .slave = &omap3xxx_usb_tll_hs_hwmod,
3138 .clk = "usbtll_ick",
3139 .addr = omap3xxx_usb_tll_hs_addrs,
3140 .user = OCP_USER_MPU | OCP_USER_SDMA,
3141 };
3142
3143 /* l4_core -> hdq1w interface */
3144 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
3145 .master = &omap3xxx_l4_core_hwmod,
3146 .slave = &omap3xxx_hdq1w_hwmod,
3147 .clk = "hdq_ick",
3148 .addr = omap2_hdq1w_addr_space,
3149 .user = OCP_USER_MPU | OCP_USER_SDMA,
3150 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
3151 };
3152
3153 /* l4_wkup -> 32ksync_counter */
3154 static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
3155 {
3156 .pa_start = 0x48320000,
3157 .pa_end = 0x4832001f,
3158 .flags = ADDR_TYPE_RT
3159 },
3160 { }
3161 };
3162
3163 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
3164 .master = &omap3xxx_l4_wkup_hwmod,
3165 .slave = &omap3xxx_counter_32k_hwmod,
3166 .clk = "omap_32ksync_ick",
3167 .addr = omap3xxx_counter_32k_addrs,
3168 .user = OCP_USER_MPU | OCP_USER_SDMA,
3169 };
3170
3171 /* am35xx has Davinci MDIO & EMAC */
3172 static struct omap_hwmod_class am35xx_mdio_class = {
3173 .name = "davinci_mdio",
3174 };
3175
3176 static struct omap_hwmod am35xx_mdio_hwmod = {
3177 .name = "davinci_mdio",
3178 .class = &am35xx_mdio_class,
3179 .flags = HWMOD_NO_IDLEST,
3180 };
3181
3182 /*
3183 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3184 * but this will probably require some additional hwmod core support,
3185 * so is left as a future to-do item.
3186 */
3187 static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
3188 .master = &am35xx_mdio_hwmod,
3189 .slave = &omap3xxx_l3_main_hwmod,
3190 .clk = "emac_fck",
3191 .user = OCP_USER_MPU,
3192 };
3193
3194 static struct omap_hwmod_addr_space am35xx_mdio_addrs[] = {
3195 {
3196 .pa_start = AM35XX_IPSS_MDIO_BASE,
3197 .pa_end = AM35XX_IPSS_MDIO_BASE + SZ_4K - 1,
3198 .flags = ADDR_TYPE_RT,
3199 },
3200 { }
3201 };
3202
3203 /* l4_core -> davinci mdio */
3204 /*
3205 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3206 * but this will probably require some additional hwmod core support,
3207 * so is left as a future to-do item.
3208 */
3209 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
3210 .master = &omap3xxx_l4_core_hwmod,
3211 .slave = &am35xx_mdio_hwmod,
3212 .clk = "emac_fck",
3213 .addr = am35xx_mdio_addrs,
3214 .user = OCP_USER_MPU,
3215 };
3216
3217 static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = {
3218 { .name = "rxthresh", .irq = 67 + OMAP_INTC_START, },
3219 { .name = "rx_pulse", .irq = 68 + OMAP_INTC_START, },
3220 { .name = "tx_pulse", .irq = 69 + OMAP_INTC_START },
3221 { .name = "misc_pulse", .irq = 70 + OMAP_INTC_START },
3222 { .irq = -1 },
3223 };
3224
3225 static struct omap_hwmod_class am35xx_emac_class = {
3226 .name = "davinci_emac",
3227 };
3228
3229 static struct omap_hwmod am35xx_emac_hwmod = {
3230 .name = "davinci_emac",
3231 .mpu_irqs = am35xx_emac_mpu_irqs,
3232 .class = &am35xx_emac_class,
3233 .flags = HWMOD_NO_IDLEST,
3234 };
3235
3236 /* l3_core -> davinci emac interface */
3237 /*
3238 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3239 * but this will probably require some additional hwmod core support,
3240 * so is left as a future to-do item.
3241 */
3242 static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
3243 .master = &am35xx_emac_hwmod,
3244 .slave = &omap3xxx_l3_main_hwmod,
3245 .clk = "emac_ick",
3246 .user = OCP_USER_MPU,
3247 };
3248
3249 static struct omap_hwmod_addr_space am35xx_emac_addrs[] = {
3250 {
3251 .pa_start = AM35XX_IPSS_EMAC_BASE,
3252 .pa_end = AM35XX_IPSS_EMAC_BASE + 0x30000 - 1,
3253 .flags = ADDR_TYPE_RT,
3254 },
3255 { }
3256 };
3257
3258 /* l4_core -> davinci emac */
3259 /*
3260 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3261 * but this will probably require some additional hwmod core support,
3262 * so is left as a future to-do item.
3263 */
3264 static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
3265 .master = &omap3xxx_l4_core_hwmod,
3266 .slave = &am35xx_emac_hwmod,
3267 .clk = "emac_ick",
3268 .addr = am35xx_emac_addrs,
3269 .user = OCP_USER_MPU,
3270 };
3271
3272 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3273 &omap3xxx_l3_main__l4_core,
3274 &omap3xxx_l3_main__l4_per,
3275 &omap3xxx_mpu__l3_main,
3276 &omap3xxx_l4_core__l4_wkup,
3277 &omap3xxx_l4_core__mmc3,
3278 &omap3_l4_core__uart1,
3279 &omap3_l4_core__uart2,
3280 &omap3_l4_per__uart3,
3281 &omap3_l4_core__i2c1,
3282 &omap3_l4_core__i2c2,
3283 &omap3_l4_core__i2c3,
3284 &omap3xxx_l4_wkup__l4_sec,
3285 &omap3xxx_l4_wkup__timer1,
3286 &omap3xxx_l4_per__timer2,
3287 &omap3xxx_l4_per__timer3,
3288 &omap3xxx_l4_per__timer4,
3289 &omap3xxx_l4_per__timer5,
3290 &omap3xxx_l4_per__timer6,
3291 &omap3xxx_l4_per__timer7,
3292 &omap3xxx_l4_per__timer8,
3293 &omap3xxx_l4_per__timer9,
3294 &omap3xxx_l4_core__timer10,
3295 &omap3xxx_l4_core__timer11,
3296 &omap3xxx_l4_wkup__wd_timer2,
3297 &omap3xxx_l4_wkup__gpio1,
3298 &omap3xxx_l4_per__gpio2,
3299 &omap3xxx_l4_per__gpio3,
3300 &omap3xxx_l4_per__gpio4,
3301 &omap3xxx_l4_per__gpio5,
3302 &omap3xxx_l4_per__gpio6,
3303 &omap3xxx_dma_system__l3,
3304 &omap3xxx_l4_core__dma_system,
3305 &omap3xxx_l4_core__mcbsp1,
3306 &omap3xxx_l4_per__mcbsp2,
3307 &omap3xxx_l4_per__mcbsp3,
3308 &omap3xxx_l4_per__mcbsp4,
3309 &omap3xxx_l4_core__mcbsp5,
3310 &omap3xxx_l4_per__mcbsp2_sidetone,
3311 &omap3xxx_l4_per__mcbsp3_sidetone,
3312 &omap34xx_l4_core__mcspi1,
3313 &omap34xx_l4_core__mcspi2,
3314 &omap34xx_l4_core__mcspi3,
3315 &omap34xx_l4_core__mcspi4,
3316 &omap3xxx_l4_wkup__counter_32k,
3317 NULL,
3318 };
3319
3320 /* GP-only hwmod links */
3321 static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = {
3322 &omap3xxx_l4_sec__timer12,
3323 NULL
3324 };
3325
3326 /* 3430ES1-only hwmod links */
3327 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
3328 &omap3430es1_dss__l3,
3329 &omap3430es1_l4_core__dss,
3330 NULL
3331 };
3332
3333 /* 3430ES2+-only hwmod links */
3334 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
3335 &omap3xxx_dss__l3,
3336 &omap3xxx_l4_core__dss,
3337 &omap3xxx_usbhsotg__l3,
3338 &omap3xxx_l4_core__usbhsotg,
3339 &omap3xxx_usb_host_hs__l3_main_2,
3340 &omap3xxx_l4_core__usb_host_hs,
3341 &omap3xxx_l4_core__usb_tll_hs,
3342 NULL
3343 };
3344
3345 /* <= 3430ES3-only hwmod links */
3346 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
3347 &omap3xxx_l4_core__pre_es3_mmc1,
3348 &omap3xxx_l4_core__pre_es3_mmc2,
3349 NULL
3350 };
3351
3352 /* 3430ES3+-only hwmod links */
3353 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3354 &omap3xxx_l4_core__es3plus_mmc1,
3355 &omap3xxx_l4_core__es3plus_mmc2,
3356 NULL
3357 };
3358
3359 /* 34xx-only hwmod links (all ES revisions) */
3360 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3361 &omap3xxx_l3__iva,
3362 &omap34xx_l4_core__sr1,
3363 &omap34xx_l4_core__sr2,
3364 &omap3xxx_l4_core__mailbox,
3365 &omap3xxx_l4_core__hdq1w,
3366 NULL
3367 };
3368
3369 /* 36xx-only hwmod links (all ES revisions) */
3370 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3371 &omap3xxx_l3__iva,
3372 &omap36xx_l4_per__uart4,
3373 &omap3xxx_dss__l3,
3374 &omap3xxx_l4_core__dss,
3375 &omap36xx_l4_core__sr1,
3376 &omap36xx_l4_core__sr2,
3377 &omap3xxx_usbhsotg__l3,
3378 &omap3xxx_l4_core__usbhsotg,
3379 &omap3xxx_l4_core__mailbox,
3380 &omap3xxx_usb_host_hs__l3_main_2,
3381 &omap3xxx_l4_core__usb_host_hs,
3382 &omap3xxx_l4_core__usb_tll_hs,
3383 &omap3xxx_l4_core__es3plus_mmc1,
3384 &omap3xxx_l4_core__es3plus_mmc2,
3385 &omap3xxx_l4_core__hdq1w,
3386 NULL
3387 };
3388
3389 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3390 &omap3xxx_dss__l3,
3391 &omap3xxx_l4_core__dss,
3392 &am35xx_usbhsotg__l3,
3393 &am35xx_l4_core__usbhsotg,
3394 &am35xx_l4_core__uart4,
3395 &omap3xxx_usb_host_hs__l3_main_2,
3396 &omap3xxx_l4_core__usb_host_hs,
3397 &omap3xxx_l4_core__usb_tll_hs,
3398 &omap3xxx_l4_core__es3plus_mmc1,
3399 &omap3xxx_l4_core__es3plus_mmc2,
3400 &am35xx_mdio__l3,
3401 &am35xx_l4_core__mdio,
3402 &am35xx_emac__l3,
3403 &am35xx_l4_core__emac,
3404 NULL
3405 };
3406
3407 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3408 &omap3xxx_l4_core__dss_dispc,
3409 &omap3xxx_l4_core__dss_dsi1,
3410 &omap3xxx_l4_core__dss_rfbi,
3411 &omap3xxx_l4_core__dss_venc,
3412 NULL
3413 };
3414
3415 int __init omap3xxx_hwmod_init(void)
3416 {
3417 int r;
3418 struct omap_hwmod_ocp_if **h = NULL;
3419 unsigned int rev;
3420
3421 omap_hwmod_init();
3422
3423 /* Register hwmod links common to all OMAP3 */
3424 r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
3425 if (r < 0)
3426 return r;
3427
3428 /* Register GP-only hwmod links. */
3429 if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
3430 r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs);
3431 if (r < 0)
3432 return r;
3433 }
3434
3435 rev = omap_rev();
3436
3437 /*
3438 * Register hwmod links common to individual OMAP3 families, all
3439 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3440 * All possible revisions should be included in this conditional.
3441 */
3442 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3443 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3444 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3445 h = omap34xx_hwmod_ocp_ifs;
3446 } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
3447 h = am35xx_hwmod_ocp_ifs;
3448 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3449 rev == OMAP3630_REV_ES1_2) {
3450 h = omap36xx_hwmod_ocp_ifs;
3451 } else {
3452 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3453 return -EINVAL;
3454 };
3455
3456 r = omap_hwmod_register_links(h);
3457 if (r < 0)
3458 return r;
3459
3460 /*
3461 * Register hwmod links specific to certain ES levels of a
3462 * particular family of silicon (e.g., 34xx ES1.0)
3463 */
3464 h = NULL;
3465 if (rev == OMAP3430_REV_ES1_0) {
3466 h = omap3430es1_hwmod_ocp_ifs;
3467 } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3468 rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3469 rev == OMAP3430_REV_ES3_1_2) {
3470 h = omap3430es2plus_hwmod_ocp_ifs;
3471 };
3472
3473 if (h) {
3474 r = omap_hwmod_register_links(h);
3475 if (r < 0)
3476 return r;
3477 }
3478
3479 h = NULL;
3480 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3481 rev == OMAP3430_REV_ES2_1) {
3482 h = omap3430_pre_es3_hwmod_ocp_ifs;
3483 } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3484 rev == OMAP3430_REV_ES3_1_2) {
3485 h = omap3430_es3plus_hwmod_ocp_ifs;
3486 };
3487
3488 if (h)
3489 r = omap_hwmod_register_links(h);
3490 if (r < 0)
3491 return r;
3492
3493 /*
3494 * DSS code presumes that dss_core hwmod is handled first,
3495 * _before_ any other DSS related hwmods so register common
3496 * DSS hwmod links last to ensure that dss_core is already
3497 * registered. Otherwise some change things may happen, for
3498 * ex. if dispc is handled before dss_core and DSS is enabled
3499 * in bootloader DISPC will be reset with outputs enabled
3500 * which sometimes leads to unrecoverable L3 error. XXX The
3501 * long-term fix to this is to ensure hwmods are set up in
3502 * dependency order in the hwmod core code.
3503 */
3504 r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
3505
3506 return r;
3507 }
Linux kernel - Deliverables
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