2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
4 * Copyright (C) 2009-2010 Nokia Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * The data in this file should be completely autogeneratable from
12 * the TI hardware database or other technical documentation.
14 * XXX these should be marked initdata for multi-OMAP kernels
16 #include <plat/omap_hwmod.h>
17 #include <mach/irqs.h>
20 #include <plat/serial.h>
21 #include <plat/l3_3xxx.h>
22 #include <plat/l4_3xxx.h>
24 #include <plat/gpio.h>
26 #include <plat/smartreflex.h>
27 #include <plat/mcbsp.h>
28 #include <plat/mcspi.h>
29 #include <plat/dmtimer.h>
31 #include "omap_hwmod_common_data.h"
33 #include "prm-regbits-34xx.h"
34 #include "cm-regbits-34xx.h"
36 #include <mach/am35xx.h>
39 * OMAP3xxx hardware module integration data
41 * ALl of the data in this section should be autogeneratable from the
42 * TI hardware database or other technical documentation. Data that
43 * is driver-specific or driver-kernel integration-specific belongs
47 static struct omap_hwmod omap3xxx_mpu_hwmod
;
48 static struct omap_hwmod omap3xxx_iva_hwmod
;
49 static struct omap_hwmod omap3xxx_l3_main_hwmod
;
50 static struct omap_hwmod omap3xxx_l4_core_hwmod
;
51 static struct omap_hwmod omap3xxx_l4_per_hwmod
;
52 static struct omap_hwmod omap3xxx_wd_timer2_hwmod
;
53 static struct omap_hwmod omap3430es1_dss_core_hwmod
;
54 static struct omap_hwmod omap3xxx_dss_core_hwmod
;
55 static struct omap_hwmod omap3xxx_dss_dispc_hwmod
;
56 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod
;
57 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod
;
58 static struct omap_hwmod omap3xxx_dss_venc_hwmod
;
59 static struct omap_hwmod omap3xxx_i2c1_hwmod
;
60 static struct omap_hwmod omap3xxx_i2c2_hwmod
;
61 static struct omap_hwmod omap3xxx_i2c3_hwmod
;
62 static struct omap_hwmod omap3xxx_gpio1_hwmod
;
63 static struct omap_hwmod omap3xxx_gpio2_hwmod
;
64 static struct omap_hwmod omap3xxx_gpio3_hwmod
;
65 static struct omap_hwmod omap3xxx_gpio4_hwmod
;
66 static struct omap_hwmod omap3xxx_gpio5_hwmod
;
67 static struct omap_hwmod omap3xxx_gpio6_hwmod
;
68 static struct omap_hwmod omap34xx_sr1_hwmod
;
69 static struct omap_hwmod omap34xx_sr2_hwmod
;
70 static struct omap_hwmod omap34xx_mcspi1
;
71 static struct omap_hwmod omap34xx_mcspi2
;
72 static struct omap_hwmod omap34xx_mcspi3
;
73 static struct omap_hwmod omap34xx_mcspi4
;
74 static struct omap_hwmod omap3xxx_mmc1_hwmod
;
75 static struct omap_hwmod omap3xxx_mmc2_hwmod
;
76 static struct omap_hwmod omap3xxx_mmc3_hwmod
;
77 static struct omap_hwmod am35xx_usbhsotg_hwmod
;
79 static struct omap_hwmod omap3xxx_dma_system_hwmod
;
81 static struct omap_hwmod omap3xxx_mcbsp1_hwmod
;
82 static struct omap_hwmod omap3xxx_mcbsp2_hwmod
;
83 static struct omap_hwmod omap3xxx_mcbsp3_hwmod
;
84 static struct omap_hwmod omap3xxx_mcbsp4_hwmod
;
85 static struct omap_hwmod omap3xxx_mcbsp5_hwmod
;
86 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod
;
87 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod
;
89 /* L3 -> L4_CORE interface */
90 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core
= {
91 .master
= &omap3xxx_l3_main_hwmod
,
92 .slave
= &omap3xxx_l4_core_hwmod
,
93 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
96 /* L3 -> L4_PER interface */
97 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per
= {
98 .master
= &omap3xxx_l3_main_hwmod
,
99 .slave
= &omap3xxx_l4_per_hwmod
,
100 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
103 /* MPU -> L3 interface */
104 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main
= {
105 .master
= &omap3xxx_mpu_hwmod
,
106 .slave
= &omap3xxx_l3_main_hwmod
,
107 .user
= OCP_USER_MPU
,
110 /* Slave interfaces on the L3 interconnect */
111 static struct omap_hwmod_ocp_if
*omap3xxx_l3_main_slaves
[] = {
112 &omap3xxx_mpu__l3_main
,
116 static struct omap_hwmod_ocp_if omap3xxx_dss__l3
= {
117 .master
= &omap3xxx_dss_core_hwmod
,
118 .slave
= &omap3xxx_l3_main_hwmod
,
121 .l3_perm_bit
= OMAP3_L3_CORE_FW_INIT_ID_DSS
,
122 .flags
= OMAP_FIREWALL_L3
,
125 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
128 /* Master interfaces on the L3 interconnect */
129 static struct omap_hwmod_ocp_if
*omap3xxx_l3_main_masters
[] = {
130 &omap3xxx_l3_main__l4_core
,
131 &omap3xxx_l3_main__l4_per
,
135 static struct omap_hwmod omap3xxx_l3_main_hwmod
= {
137 .class = &l3_hwmod_class
,
138 .masters
= omap3xxx_l3_main_masters
,
139 .masters_cnt
= ARRAY_SIZE(omap3xxx_l3_main_masters
),
140 .slaves
= omap3xxx_l3_main_slaves
,
141 .slaves_cnt
= ARRAY_SIZE(omap3xxx_l3_main_slaves
),
142 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
143 .flags
= HWMOD_NO_IDLEST
,
146 static struct omap_hwmod omap3xxx_l4_wkup_hwmod
;
147 static struct omap_hwmod omap3xxx_uart1_hwmod
;
148 static struct omap_hwmod omap3xxx_uart2_hwmod
;
149 static struct omap_hwmod omap3xxx_uart3_hwmod
;
150 static struct omap_hwmod omap3xxx_uart4_hwmod
;
151 static struct omap_hwmod omap3xxx_usbhsotg_hwmod
;
153 /* l3_core -> usbhsotg interface */
154 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3
= {
155 .master
= &omap3xxx_usbhsotg_hwmod
,
156 .slave
= &omap3xxx_l3_main_hwmod
,
157 .clk
= "core_l3_ick",
158 .user
= OCP_USER_MPU
,
161 /* l3_core -> am35xx_usbhsotg interface */
162 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3
= {
163 .master
= &am35xx_usbhsotg_hwmod
,
164 .slave
= &omap3xxx_l3_main_hwmod
,
165 .clk
= "core_l3_ick",
166 .user
= OCP_USER_MPU
,
168 /* L4_CORE -> L4_WKUP interface */
169 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup
= {
170 .master
= &omap3xxx_l4_core_hwmod
,
171 .slave
= &omap3xxx_l4_wkup_hwmod
,
172 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
175 /* L4 CORE -> MMC1 interface */
176 static struct omap_hwmod_addr_space omap3xxx_mmc1_addr_space
[] = {
178 .pa_start
= 0x4809c000,
179 .pa_end
= 0x4809c1ff,
180 .flags
= ADDR_TYPE_RT
,
184 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1
= {
185 .master
= &omap3xxx_l4_core_hwmod
,
186 .slave
= &omap3xxx_mmc1_hwmod
,
188 .addr
= omap3xxx_mmc1_addr_space
,
189 .addr_cnt
= ARRAY_SIZE(omap3xxx_mmc1_addr_space
),
190 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
191 .flags
= OMAP_FIREWALL_L4
194 /* L4 CORE -> MMC2 interface */
195 static struct omap_hwmod_addr_space omap3xxx_mmc2_addr_space
[] = {
197 .pa_start
= 0x480b4000,
198 .pa_end
= 0x480b41ff,
199 .flags
= ADDR_TYPE_RT
,
203 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2
= {
204 .master
= &omap3xxx_l4_core_hwmod
,
205 .slave
= &omap3xxx_mmc2_hwmod
,
207 .addr
= omap3xxx_mmc2_addr_space
,
208 .addr_cnt
= ARRAY_SIZE(omap3xxx_mmc2_addr_space
),
209 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
210 .flags
= OMAP_FIREWALL_L4
213 /* L4 CORE -> MMC3 interface */
214 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space
[] = {
216 .pa_start
= 0x480ad000,
217 .pa_end
= 0x480ad1ff,
218 .flags
= ADDR_TYPE_RT
,
222 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3
= {
223 .master
= &omap3xxx_l4_core_hwmod
,
224 .slave
= &omap3xxx_mmc3_hwmod
,
226 .addr
= omap3xxx_mmc3_addr_space
,
227 .addr_cnt
= ARRAY_SIZE(omap3xxx_mmc3_addr_space
),
228 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
229 .flags
= OMAP_FIREWALL_L4
232 /* L4 CORE -> UART1 interface */
233 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space
[] = {
235 .pa_start
= OMAP3_UART1_BASE
,
236 .pa_end
= OMAP3_UART1_BASE
+ SZ_8K
- 1,
237 .flags
= ADDR_MAP_ON_INIT
| ADDR_TYPE_RT
,
241 static struct omap_hwmod_ocp_if omap3_l4_core__uart1
= {
242 .master
= &omap3xxx_l4_core_hwmod
,
243 .slave
= &omap3xxx_uart1_hwmod
,
245 .addr
= omap3xxx_uart1_addr_space
,
246 .addr_cnt
= ARRAY_SIZE(omap3xxx_uart1_addr_space
),
247 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
250 /* L4 CORE -> UART2 interface */
251 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space
[] = {
253 .pa_start
= OMAP3_UART2_BASE
,
254 .pa_end
= OMAP3_UART2_BASE
+ SZ_1K
- 1,
255 .flags
= ADDR_MAP_ON_INIT
| ADDR_TYPE_RT
,
259 static struct omap_hwmod_ocp_if omap3_l4_core__uart2
= {
260 .master
= &omap3xxx_l4_core_hwmod
,
261 .slave
= &omap3xxx_uart2_hwmod
,
263 .addr
= omap3xxx_uart2_addr_space
,
264 .addr_cnt
= ARRAY_SIZE(omap3xxx_uart2_addr_space
),
265 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
268 /* L4 PER -> UART3 interface */
269 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space
[] = {
271 .pa_start
= OMAP3_UART3_BASE
,
272 .pa_end
= OMAP3_UART3_BASE
+ SZ_1K
- 1,
273 .flags
= ADDR_MAP_ON_INIT
| ADDR_TYPE_RT
,
277 static struct omap_hwmod_ocp_if omap3_l4_per__uart3
= {
278 .master
= &omap3xxx_l4_per_hwmod
,
279 .slave
= &omap3xxx_uart3_hwmod
,
281 .addr
= omap3xxx_uart3_addr_space
,
282 .addr_cnt
= ARRAY_SIZE(omap3xxx_uart3_addr_space
),
283 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
286 /* L4 PER -> UART4 interface */
287 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space
[] = {
289 .pa_start
= OMAP3_UART4_BASE
,
290 .pa_end
= OMAP3_UART4_BASE
+ SZ_1K
- 1,
291 .flags
= ADDR_MAP_ON_INIT
| ADDR_TYPE_RT
,
295 static struct omap_hwmod_ocp_if omap3_l4_per__uart4
= {
296 .master
= &omap3xxx_l4_per_hwmod
,
297 .slave
= &omap3xxx_uart4_hwmod
,
299 .addr
= omap3xxx_uart4_addr_space
,
300 .addr_cnt
= ARRAY_SIZE(omap3xxx_uart4_addr_space
),
301 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
304 /* I2C IP block address space length (in bytes) */
305 #define OMAP2_I2C_AS_LEN 128
307 /* L4 CORE -> I2C1 interface */
308 static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space
[] = {
310 .pa_start
= 0x48070000,
311 .pa_end
= 0x48070000 + OMAP2_I2C_AS_LEN
- 1,
312 .flags
= ADDR_TYPE_RT
,
316 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1
= {
317 .master
= &omap3xxx_l4_core_hwmod
,
318 .slave
= &omap3xxx_i2c1_hwmod
,
320 .addr
= omap3xxx_i2c1_addr_space
,
321 .addr_cnt
= ARRAY_SIZE(omap3xxx_i2c1_addr_space
),
324 .l4_fw_region
= OMAP3_L4_CORE_FW_I2C1_REGION
,
326 .flags
= OMAP_FIREWALL_L4
,
329 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
332 /* L4 CORE -> I2C2 interface */
333 static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space
[] = {
335 .pa_start
= 0x48072000,
336 .pa_end
= 0x48072000 + OMAP2_I2C_AS_LEN
- 1,
337 .flags
= ADDR_TYPE_RT
,
341 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2
= {
342 .master
= &omap3xxx_l4_core_hwmod
,
343 .slave
= &omap3xxx_i2c2_hwmod
,
345 .addr
= omap3xxx_i2c2_addr_space
,
346 .addr_cnt
= ARRAY_SIZE(omap3xxx_i2c2_addr_space
),
349 .l4_fw_region
= OMAP3_L4_CORE_FW_I2C2_REGION
,
351 .flags
= OMAP_FIREWALL_L4
,
354 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
357 /* L4 CORE -> I2C3 interface */
358 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space
[] = {
360 .pa_start
= 0x48060000,
361 .pa_end
= 0x48060000 + OMAP2_I2C_AS_LEN
- 1,
362 .flags
= ADDR_TYPE_RT
,
366 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3
= {
367 .master
= &omap3xxx_l4_core_hwmod
,
368 .slave
= &omap3xxx_i2c3_hwmod
,
370 .addr
= omap3xxx_i2c3_addr_space
,
371 .addr_cnt
= ARRAY_SIZE(omap3xxx_i2c3_addr_space
),
374 .l4_fw_region
= OMAP3_L4_CORE_FW_I2C3_REGION
,
376 .flags
= OMAP_FIREWALL_L4
,
379 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
382 /* L4 CORE -> SR1 interface */
383 static struct omap_hwmod_addr_space omap3_sr1_addr_space
[] = {
385 .pa_start
= OMAP34XX_SR1_BASE
,
386 .pa_end
= OMAP34XX_SR1_BASE
+ SZ_1K
- 1,
387 .flags
= ADDR_TYPE_RT
,
391 static struct omap_hwmod_ocp_if omap3_l4_core__sr1
= {
392 .master
= &omap3xxx_l4_core_hwmod
,
393 .slave
= &omap34xx_sr1_hwmod
,
395 .addr
= omap3_sr1_addr_space
,
396 .addr_cnt
= ARRAY_SIZE(omap3_sr1_addr_space
),
397 .user
= OCP_USER_MPU
,
400 /* L4 CORE -> SR1 interface */
401 static struct omap_hwmod_addr_space omap3_sr2_addr_space
[] = {
403 .pa_start
= OMAP34XX_SR2_BASE
,
404 .pa_end
= OMAP34XX_SR2_BASE
+ SZ_1K
- 1,
405 .flags
= ADDR_TYPE_RT
,
409 static struct omap_hwmod_ocp_if omap3_l4_core__sr2
= {
410 .master
= &omap3xxx_l4_core_hwmod
,
411 .slave
= &omap34xx_sr2_hwmod
,
413 .addr
= omap3_sr2_addr_space
,
414 .addr_cnt
= ARRAY_SIZE(omap3_sr2_addr_space
),
415 .user
= OCP_USER_MPU
,
419 * usbhsotg interface data
422 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs
[] = {
424 .pa_start
= OMAP34XX_HSUSB_OTG_BASE
,
425 .pa_end
= OMAP34XX_HSUSB_OTG_BASE
+ SZ_4K
- 1,
426 .flags
= ADDR_TYPE_RT
430 /* l4_core -> usbhsotg */
431 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg
= {
432 .master
= &omap3xxx_l4_core_hwmod
,
433 .slave
= &omap3xxx_usbhsotg_hwmod
,
435 .addr
= omap3xxx_usbhsotg_addrs
,
436 .addr_cnt
= ARRAY_SIZE(omap3xxx_usbhsotg_addrs
),
437 .user
= OCP_USER_MPU
,
440 static struct omap_hwmod_ocp_if
*omap3xxx_usbhsotg_masters
[] = {
441 &omap3xxx_usbhsotg__l3
,
444 static struct omap_hwmod_ocp_if
*omap3xxx_usbhsotg_slaves
[] = {
445 &omap3xxx_l4_core__usbhsotg
,
448 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs
[] = {
450 .pa_start
= AM35XX_IPSS_USBOTGSS_BASE
,
451 .pa_end
= AM35XX_IPSS_USBOTGSS_BASE
+ SZ_4K
- 1,
452 .flags
= ADDR_TYPE_RT
456 /* l4_core -> usbhsotg */
457 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg
= {
458 .master
= &omap3xxx_l4_core_hwmod
,
459 .slave
= &am35xx_usbhsotg_hwmod
,
461 .addr
= am35xx_usbhsotg_addrs
,
462 .addr_cnt
= ARRAY_SIZE(am35xx_usbhsotg_addrs
),
463 .user
= OCP_USER_MPU
,
466 static struct omap_hwmod_ocp_if
*am35xx_usbhsotg_masters
[] = {
467 &am35xx_usbhsotg__l3
,
470 static struct omap_hwmod_ocp_if
*am35xx_usbhsotg_slaves
[] = {
471 &am35xx_l4_core__usbhsotg
,
473 /* Slave interfaces on the L4_CORE interconnect */
474 static struct omap_hwmod_ocp_if
*omap3xxx_l4_core_slaves
[] = {
475 &omap3xxx_l3_main__l4_core
,
480 /* Master interfaces on the L4_CORE interconnect */
481 static struct omap_hwmod_ocp_if
*omap3xxx_l4_core_masters
[] = {
482 &omap3xxx_l4_core__l4_wkup
,
483 &omap3_l4_core__uart1
,
484 &omap3_l4_core__uart2
,
485 &omap3_l4_core__i2c1
,
486 &omap3_l4_core__i2c2
,
487 &omap3_l4_core__i2c3
,
491 static struct omap_hwmod omap3xxx_l4_core_hwmod
= {
493 .class = &l4_hwmod_class
,
494 .masters
= omap3xxx_l4_core_masters
,
495 .masters_cnt
= ARRAY_SIZE(omap3xxx_l4_core_masters
),
496 .slaves
= omap3xxx_l4_core_slaves
,
497 .slaves_cnt
= ARRAY_SIZE(omap3xxx_l4_core_slaves
),
498 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
499 .flags
= HWMOD_NO_IDLEST
,
502 /* Slave interfaces on the L4_PER interconnect */
503 static struct omap_hwmod_ocp_if
*omap3xxx_l4_per_slaves
[] = {
504 &omap3xxx_l3_main__l4_per
,
507 /* Master interfaces on the L4_PER interconnect */
508 static struct omap_hwmod_ocp_if
*omap3xxx_l4_per_masters
[] = {
509 &omap3_l4_per__uart3
,
510 &omap3_l4_per__uart4
,
514 static struct omap_hwmod omap3xxx_l4_per_hwmod
= {
516 .class = &l4_hwmod_class
,
517 .masters
= omap3xxx_l4_per_masters
,
518 .masters_cnt
= ARRAY_SIZE(omap3xxx_l4_per_masters
),
519 .slaves
= omap3xxx_l4_per_slaves
,
520 .slaves_cnt
= ARRAY_SIZE(omap3xxx_l4_per_slaves
),
521 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
522 .flags
= HWMOD_NO_IDLEST
,
525 /* Slave interfaces on the L4_WKUP interconnect */
526 static struct omap_hwmod_ocp_if
*omap3xxx_l4_wkup_slaves
[] = {
527 &omap3xxx_l4_core__l4_wkup
,
530 /* Master interfaces on the L4_WKUP interconnect */
531 static struct omap_hwmod_ocp_if
*omap3xxx_l4_wkup_masters
[] = {
535 static struct omap_hwmod omap3xxx_l4_wkup_hwmod
= {
537 .class = &l4_hwmod_class
,
538 .masters
= omap3xxx_l4_wkup_masters
,
539 .masters_cnt
= ARRAY_SIZE(omap3xxx_l4_wkup_masters
),
540 .slaves
= omap3xxx_l4_wkup_slaves
,
541 .slaves_cnt
= ARRAY_SIZE(omap3xxx_l4_wkup_slaves
),
542 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
543 .flags
= HWMOD_NO_IDLEST
,
546 /* Master interfaces on the MPU device */
547 static struct omap_hwmod_ocp_if
*omap3xxx_mpu_masters
[] = {
548 &omap3xxx_mpu__l3_main
,
552 static struct omap_hwmod omap3xxx_mpu_hwmod
= {
554 .class = &mpu_hwmod_class
,
555 .main_clk
= "arm_fck",
556 .masters
= omap3xxx_mpu_masters
,
557 .masters_cnt
= ARRAY_SIZE(omap3xxx_mpu_masters
),
558 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
562 * IVA2_2 interface data
565 /* IVA2 <- L3 interface */
566 static struct omap_hwmod_ocp_if omap3xxx_l3__iva
= {
567 .master
= &omap3xxx_l3_main_hwmod
,
568 .slave
= &omap3xxx_iva_hwmod
,
570 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
573 static struct omap_hwmod_ocp_if
*omap3xxx_iva_masters
[] = {
581 static struct omap_hwmod omap3xxx_iva_hwmod
= {
583 .class = &iva_hwmod_class
,
584 .masters
= omap3xxx_iva_masters
,
585 .masters_cnt
= ARRAY_SIZE(omap3xxx_iva_masters
),
586 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
)
590 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc
= {
594 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_CLOCKACTIVITY
|
595 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
596 SYSC_HAS_EMUFREE
| SYSC_HAS_AUTOIDLE
),
597 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
598 .sysc_fields
= &omap_hwmod_sysc_type1
,
601 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class
= {
603 .sysc
= &omap3xxx_timer_1ms_sysc
,
604 .rev
= OMAP_TIMER_IP_VERSION_1
,
607 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc
= {
611 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_ENAWAKEUP
|
612 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
),
613 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
614 .sysc_fields
= &omap_hwmod_sysc_type1
,
617 static struct omap_hwmod_class omap3xxx_timer_hwmod_class
= {
619 .sysc
= &omap3xxx_timer_sysc
,
620 .rev
= OMAP_TIMER_IP_VERSION_1
,
624 static struct omap_hwmod omap3xxx_timer1_hwmod
;
625 static struct omap_hwmod_irq_info omap3xxx_timer1_mpu_irqs
[] = {
629 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs
[] = {
631 .pa_start
= 0x48318000,
632 .pa_end
= 0x48318000 + SZ_1K
- 1,
633 .flags
= ADDR_TYPE_RT
637 /* l4_wkup -> timer1 */
638 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1
= {
639 .master
= &omap3xxx_l4_wkup_hwmod
,
640 .slave
= &omap3xxx_timer1_hwmod
,
642 .addr
= omap3xxx_timer1_addrs
,
643 .addr_cnt
= ARRAY_SIZE(omap3xxx_timer1_addrs
),
644 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
647 /* timer1 slave port */
648 static struct omap_hwmod_ocp_if
*omap3xxx_timer1_slaves
[] = {
649 &omap3xxx_l4_wkup__timer1
,
653 static struct omap_hwmod omap3xxx_timer1_hwmod
= {
655 .mpu_irqs
= omap3xxx_timer1_mpu_irqs
,
656 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_timer1_mpu_irqs
),
657 .main_clk
= "gpt1_fck",
661 .module_bit
= OMAP3430_EN_GPT1_SHIFT
,
662 .module_offs
= WKUP_MOD
,
664 .idlest_idle_bit
= OMAP3430_ST_GPT1_SHIFT
,
667 .slaves
= omap3xxx_timer1_slaves
,
668 .slaves_cnt
= ARRAY_SIZE(omap3xxx_timer1_slaves
),
669 .class = &omap3xxx_timer_1ms_hwmod_class
,
670 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
)
674 static struct omap_hwmod omap3xxx_timer2_hwmod
;
675 static struct omap_hwmod_irq_info omap3xxx_timer2_mpu_irqs
[] = {
679 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs
[] = {
681 .pa_start
= 0x49032000,
682 .pa_end
= 0x49032000 + SZ_1K
- 1,
683 .flags
= ADDR_TYPE_RT
687 /* l4_per -> timer2 */
688 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2
= {
689 .master
= &omap3xxx_l4_per_hwmod
,
690 .slave
= &omap3xxx_timer2_hwmod
,
692 .addr
= omap3xxx_timer2_addrs
,
693 .addr_cnt
= ARRAY_SIZE(omap3xxx_timer2_addrs
),
694 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
697 /* timer2 slave port */
698 static struct omap_hwmod_ocp_if
*omap3xxx_timer2_slaves
[] = {
699 &omap3xxx_l4_per__timer2
,
703 static struct omap_hwmod omap3xxx_timer2_hwmod
= {
705 .mpu_irqs
= omap3xxx_timer2_mpu_irqs
,
706 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_timer2_mpu_irqs
),
707 .main_clk
= "gpt2_fck",
711 .module_bit
= OMAP3430_EN_GPT2_SHIFT
,
712 .module_offs
= OMAP3430_PER_MOD
,
714 .idlest_idle_bit
= OMAP3430_ST_GPT2_SHIFT
,
717 .slaves
= omap3xxx_timer2_slaves
,
718 .slaves_cnt
= ARRAY_SIZE(omap3xxx_timer2_slaves
),
719 .class = &omap3xxx_timer_1ms_hwmod_class
,
720 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
)
724 static struct omap_hwmod omap3xxx_timer3_hwmod
;
725 static struct omap_hwmod_irq_info omap3xxx_timer3_mpu_irqs
[] = {
729 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs
[] = {
731 .pa_start
= 0x49034000,
732 .pa_end
= 0x49034000 + SZ_1K
- 1,
733 .flags
= ADDR_TYPE_RT
737 /* l4_per -> timer3 */
738 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3
= {
739 .master
= &omap3xxx_l4_per_hwmod
,
740 .slave
= &omap3xxx_timer3_hwmod
,
742 .addr
= omap3xxx_timer3_addrs
,
743 .addr_cnt
= ARRAY_SIZE(omap3xxx_timer3_addrs
),
744 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
747 /* timer3 slave port */
748 static struct omap_hwmod_ocp_if
*omap3xxx_timer3_slaves
[] = {
749 &omap3xxx_l4_per__timer3
,
753 static struct omap_hwmod omap3xxx_timer3_hwmod
= {
755 .mpu_irqs
= omap3xxx_timer3_mpu_irqs
,
756 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_timer3_mpu_irqs
),
757 .main_clk
= "gpt3_fck",
761 .module_bit
= OMAP3430_EN_GPT3_SHIFT
,
762 .module_offs
= OMAP3430_PER_MOD
,
764 .idlest_idle_bit
= OMAP3430_ST_GPT3_SHIFT
,
767 .slaves
= omap3xxx_timer3_slaves
,
768 .slaves_cnt
= ARRAY_SIZE(omap3xxx_timer3_slaves
),
769 .class = &omap3xxx_timer_hwmod_class
,
770 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
)
774 static struct omap_hwmod omap3xxx_timer4_hwmod
;
775 static struct omap_hwmod_irq_info omap3xxx_timer4_mpu_irqs
[] = {
779 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs
[] = {
781 .pa_start
= 0x49036000,
782 .pa_end
= 0x49036000 + SZ_1K
- 1,
783 .flags
= ADDR_TYPE_RT
787 /* l4_per -> timer4 */
788 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4
= {
789 .master
= &omap3xxx_l4_per_hwmod
,
790 .slave
= &omap3xxx_timer4_hwmod
,
792 .addr
= omap3xxx_timer4_addrs
,
793 .addr_cnt
= ARRAY_SIZE(omap3xxx_timer4_addrs
),
794 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
797 /* timer4 slave port */
798 static struct omap_hwmod_ocp_if
*omap3xxx_timer4_slaves
[] = {
799 &omap3xxx_l4_per__timer4
,
803 static struct omap_hwmod omap3xxx_timer4_hwmod
= {
805 .mpu_irqs
= omap3xxx_timer4_mpu_irqs
,
806 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_timer4_mpu_irqs
),
807 .main_clk
= "gpt4_fck",
811 .module_bit
= OMAP3430_EN_GPT4_SHIFT
,
812 .module_offs
= OMAP3430_PER_MOD
,
814 .idlest_idle_bit
= OMAP3430_ST_GPT4_SHIFT
,
817 .slaves
= omap3xxx_timer4_slaves
,
818 .slaves_cnt
= ARRAY_SIZE(omap3xxx_timer4_slaves
),
819 .class = &omap3xxx_timer_hwmod_class
,
820 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
)
824 static struct omap_hwmod omap3xxx_timer5_hwmod
;
825 static struct omap_hwmod_irq_info omap3xxx_timer5_mpu_irqs
[] = {
829 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs
[] = {
831 .pa_start
= 0x49038000,
832 .pa_end
= 0x49038000 + SZ_1K
- 1,
833 .flags
= ADDR_TYPE_RT
837 /* l4_per -> timer5 */
838 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5
= {
839 .master
= &omap3xxx_l4_per_hwmod
,
840 .slave
= &omap3xxx_timer5_hwmod
,
842 .addr
= omap3xxx_timer5_addrs
,
843 .addr_cnt
= ARRAY_SIZE(omap3xxx_timer5_addrs
),
844 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
847 /* timer5 slave port */
848 static struct omap_hwmod_ocp_if
*omap3xxx_timer5_slaves
[] = {
849 &omap3xxx_l4_per__timer5
,
853 static struct omap_hwmod omap3xxx_timer5_hwmod
= {
855 .mpu_irqs
= omap3xxx_timer5_mpu_irqs
,
856 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_timer5_mpu_irqs
),
857 .main_clk
= "gpt5_fck",
861 .module_bit
= OMAP3430_EN_GPT5_SHIFT
,
862 .module_offs
= OMAP3430_PER_MOD
,
864 .idlest_idle_bit
= OMAP3430_ST_GPT5_SHIFT
,
867 .slaves
= omap3xxx_timer5_slaves
,
868 .slaves_cnt
= ARRAY_SIZE(omap3xxx_timer5_slaves
),
869 .class = &omap3xxx_timer_hwmod_class
,
870 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
)
874 static struct omap_hwmod omap3xxx_timer6_hwmod
;
875 static struct omap_hwmod_irq_info omap3xxx_timer6_mpu_irqs
[] = {
879 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs
[] = {
881 .pa_start
= 0x4903A000,
882 .pa_end
= 0x4903A000 + SZ_1K
- 1,
883 .flags
= ADDR_TYPE_RT
887 /* l4_per -> timer6 */
888 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6
= {
889 .master
= &omap3xxx_l4_per_hwmod
,
890 .slave
= &omap3xxx_timer6_hwmod
,
892 .addr
= omap3xxx_timer6_addrs
,
893 .addr_cnt
= ARRAY_SIZE(omap3xxx_timer6_addrs
),
894 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
897 /* timer6 slave port */
898 static struct omap_hwmod_ocp_if
*omap3xxx_timer6_slaves
[] = {
899 &omap3xxx_l4_per__timer6
,
903 static struct omap_hwmod omap3xxx_timer6_hwmod
= {
905 .mpu_irqs
= omap3xxx_timer6_mpu_irqs
,
906 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_timer6_mpu_irqs
),
907 .main_clk
= "gpt6_fck",
911 .module_bit
= OMAP3430_EN_GPT6_SHIFT
,
912 .module_offs
= OMAP3430_PER_MOD
,
914 .idlest_idle_bit
= OMAP3430_ST_GPT6_SHIFT
,
917 .slaves
= omap3xxx_timer6_slaves
,
918 .slaves_cnt
= ARRAY_SIZE(omap3xxx_timer6_slaves
),
919 .class = &omap3xxx_timer_hwmod_class
,
920 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
)
924 static struct omap_hwmod omap3xxx_timer7_hwmod
;
925 static struct omap_hwmod_irq_info omap3xxx_timer7_mpu_irqs
[] = {
929 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs
[] = {
931 .pa_start
= 0x4903C000,
932 .pa_end
= 0x4903C000 + SZ_1K
- 1,
933 .flags
= ADDR_TYPE_RT
937 /* l4_per -> timer7 */
938 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7
= {
939 .master
= &omap3xxx_l4_per_hwmod
,
940 .slave
= &omap3xxx_timer7_hwmod
,
942 .addr
= omap3xxx_timer7_addrs
,
943 .addr_cnt
= ARRAY_SIZE(omap3xxx_timer7_addrs
),
944 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
947 /* timer7 slave port */
948 static struct omap_hwmod_ocp_if
*omap3xxx_timer7_slaves
[] = {
949 &omap3xxx_l4_per__timer7
,
953 static struct omap_hwmod omap3xxx_timer7_hwmod
= {
955 .mpu_irqs
= omap3xxx_timer7_mpu_irqs
,
956 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_timer7_mpu_irqs
),
957 .main_clk
= "gpt7_fck",
961 .module_bit
= OMAP3430_EN_GPT7_SHIFT
,
962 .module_offs
= OMAP3430_PER_MOD
,
964 .idlest_idle_bit
= OMAP3430_ST_GPT7_SHIFT
,
967 .slaves
= omap3xxx_timer7_slaves
,
968 .slaves_cnt
= ARRAY_SIZE(omap3xxx_timer7_slaves
),
969 .class = &omap3xxx_timer_hwmod_class
,
970 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
)
974 static struct omap_hwmod omap3xxx_timer8_hwmod
;
975 static struct omap_hwmod_irq_info omap3xxx_timer8_mpu_irqs
[] = {
979 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs
[] = {
981 .pa_start
= 0x4903E000,
982 .pa_end
= 0x4903E000 + SZ_1K
- 1,
983 .flags
= ADDR_TYPE_RT
987 /* l4_per -> timer8 */
988 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8
= {
989 .master
= &omap3xxx_l4_per_hwmod
,
990 .slave
= &omap3xxx_timer8_hwmod
,
992 .addr
= omap3xxx_timer8_addrs
,
993 .addr_cnt
= ARRAY_SIZE(omap3xxx_timer8_addrs
),
994 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
997 /* timer8 slave port */
998 static struct omap_hwmod_ocp_if
*omap3xxx_timer8_slaves
[] = {
999 &omap3xxx_l4_per__timer8
,
1003 static struct omap_hwmod omap3xxx_timer8_hwmod
= {
1005 .mpu_irqs
= omap3xxx_timer8_mpu_irqs
,
1006 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_timer8_mpu_irqs
),
1007 .main_clk
= "gpt8_fck",
1011 .module_bit
= OMAP3430_EN_GPT8_SHIFT
,
1012 .module_offs
= OMAP3430_PER_MOD
,
1014 .idlest_idle_bit
= OMAP3430_ST_GPT8_SHIFT
,
1017 .slaves
= omap3xxx_timer8_slaves
,
1018 .slaves_cnt
= ARRAY_SIZE(omap3xxx_timer8_slaves
),
1019 .class = &omap3xxx_timer_hwmod_class
,
1020 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
)
1024 static struct omap_hwmod omap3xxx_timer9_hwmod
;
1025 static struct omap_hwmod_irq_info omap3xxx_timer9_mpu_irqs
[] = {
1029 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs
[] = {
1031 .pa_start
= 0x49040000,
1032 .pa_end
= 0x49040000 + SZ_1K
- 1,
1033 .flags
= ADDR_TYPE_RT
1037 /* l4_per -> timer9 */
1038 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9
= {
1039 .master
= &omap3xxx_l4_per_hwmod
,
1040 .slave
= &omap3xxx_timer9_hwmod
,
1042 .addr
= omap3xxx_timer9_addrs
,
1043 .addr_cnt
= ARRAY_SIZE(omap3xxx_timer9_addrs
),
1044 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1047 /* timer9 slave port */
1048 static struct omap_hwmod_ocp_if
*omap3xxx_timer9_slaves
[] = {
1049 &omap3xxx_l4_per__timer9
,
1053 static struct omap_hwmod omap3xxx_timer9_hwmod
= {
1055 .mpu_irqs
= omap3xxx_timer9_mpu_irqs
,
1056 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_timer9_mpu_irqs
),
1057 .main_clk
= "gpt9_fck",
1061 .module_bit
= OMAP3430_EN_GPT9_SHIFT
,
1062 .module_offs
= OMAP3430_PER_MOD
,
1064 .idlest_idle_bit
= OMAP3430_ST_GPT9_SHIFT
,
1067 .slaves
= omap3xxx_timer9_slaves
,
1068 .slaves_cnt
= ARRAY_SIZE(omap3xxx_timer9_slaves
),
1069 .class = &omap3xxx_timer_hwmod_class
,
1070 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
)
1074 static struct omap_hwmod omap3xxx_timer10_hwmod
;
1075 static struct omap_hwmod_irq_info omap3xxx_timer10_mpu_irqs
[] = {
1079 static struct omap_hwmod_addr_space omap3xxx_timer10_addrs
[] = {
1081 .pa_start
= 0x48086000,
1082 .pa_end
= 0x48086000 + SZ_1K
- 1,
1083 .flags
= ADDR_TYPE_RT
1087 /* l4_core -> timer10 */
1088 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10
= {
1089 .master
= &omap3xxx_l4_core_hwmod
,
1090 .slave
= &omap3xxx_timer10_hwmod
,
1092 .addr
= omap3xxx_timer10_addrs
,
1093 .addr_cnt
= ARRAY_SIZE(omap3xxx_timer10_addrs
),
1094 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1097 /* timer10 slave port */
1098 static struct omap_hwmod_ocp_if
*omap3xxx_timer10_slaves
[] = {
1099 &omap3xxx_l4_core__timer10
,
1103 static struct omap_hwmod omap3xxx_timer10_hwmod
= {
1105 .mpu_irqs
= omap3xxx_timer10_mpu_irqs
,
1106 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_timer10_mpu_irqs
),
1107 .main_clk
= "gpt10_fck",
1111 .module_bit
= OMAP3430_EN_GPT10_SHIFT
,
1112 .module_offs
= CORE_MOD
,
1114 .idlest_idle_bit
= OMAP3430_ST_GPT10_SHIFT
,
1117 .slaves
= omap3xxx_timer10_slaves
,
1118 .slaves_cnt
= ARRAY_SIZE(omap3xxx_timer10_slaves
),
1119 .class = &omap3xxx_timer_1ms_hwmod_class
,
1120 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
)
1124 static struct omap_hwmod omap3xxx_timer11_hwmod
;
1125 static struct omap_hwmod_irq_info omap3xxx_timer11_mpu_irqs
[] = {
1129 static struct omap_hwmod_addr_space omap3xxx_timer11_addrs
[] = {
1131 .pa_start
= 0x48088000,
1132 .pa_end
= 0x48088000 + SZ_1K
- 1,
1133 .flags
= ADDR_TYPE_RT
1137 /* l4_core -> timer11 */
1138 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11
= {
1139 .master
= &omap3xxx_l4_core_hwmod
,
1140 .slave
= &omap3xxx_timer11_hwmod
,
1142 .addr
= omap3xxx_timer11_addrs
,
1143 .addr_cnt
= ARRAY_SIZE(omap3xxx_timer11_addrs
),
1144 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1147 /* timer11 slave port */
1148 static struct omap_hwmod_ocp_if
*omap3xxx_timer11_slaves
[] = {
1149 &omap3xxx_l4_core__timer11
,
1153 static struct omap_hwmod omap3xxx_timer11_hwmod
= {
1155 .mpu_irqs
= omap3xxx_timer11_mpu_irqs
,
1156 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_timer11_mpu_irqs
),
1157 .main_clk
= "gpt11_fck",
1161 .module_bit
= OMAP3430_EN_GPT11_SHIFT
,
1162 .module_offs
= CORE_MOD
,
1164 .idlest_idle_bit
= OMAP3430_ST_GPT11_SHIFT
,
1167 .slaves
= omap3xxx_timer11_slaves
,
1168 .slaves_cnt
= ARRAY_SIZE(omap3xxx_timer11_slaves
),
1169 .class = &omap3xxx_timer_hwmod_class
,
1170 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
)
1174 static struct omap_hwmod omap3xxx_timer12_hwmod
;
1175 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs
[] = {
1179 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs
[] = {
1181 .pa_start
= 0x48304000,
1182 .pa_end
= 0x48304000 + SZ_1K
- 1,
1183 .flags
= ADDR_TYPE_RT
1187 /* l4_core -> timer12 */
1188 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12
= {
1189 .master
= &omap3xxx_l4_core_hwmod
,
1190 .slave
= &omap3xxx_timer12_hwmod
,
1192 .addr
= omap3xxx_timer12_addrs
,
1193 .addr_cnt
= ARRAY_SIZE(omap3xxx_timer12_addrs
),
1194 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1197 /* timer12 slave port */
1198 static struct omap_hwmod_ocp_if
*omap3xxx_timer12_slaves
[] = {
1199 &omap3xxx_l4_core__timer12
,
1203 static struct omap_hwmod omap3xxx_timer12_hwmod
= {
1205 .mpu_irqs
= omap3xxx_timer12_mpu_irqs
,
1206 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_timer12_mpu_irqs
),
1207 .main_clk
= "gpt12_fck",
1211 .module_bit
= OMAP3430_EN_GPT12_SHIFT
,
1212 .module_offs
= WKUP_MOD
,
1214 .idlest_idle_bit
= OMAP3430_ST_GPT12_SHIFT
,
1217 .slaves
= omap3xxx_timer12_slaves
,
1218 .slaves_cnt
= ARRAY_SIZE(omap3xxx_timer12_slaves
),
1219 .class = &omap3xxx_timer_hwmod_class
,
1220 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
)
1223 /* l4_wkup -> wd_timer2 */
1224 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs
[] = {
1226 .pa_start
= 0x48314000,
1227 .pa_end
= 0x4831407f,
1228 .flags
= ADDR_TYPE_RT
1232 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2
= {
1233 .master
= &omap3xxx_l4_wkup_hwmod
,
1234 .slave
= &omap3xxx_wd_timer2_hwmod
,
1236 .addr
= omap3xxx_wd_timer2_addrs
,
1237 .addr_cnt
= ARRAY_SIZE(omap3xxx_wd_timer2_addrs
),
1238 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1243 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1244 * overflow condition
1247 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc
= {
1249 .sysc_offs
= 0x0010,
1250 .syss_offs
= 0x0014,
1251 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_EMUFREE
|
1252 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
1253 SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
),
1254 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1255 .sysc_fields
= &omap_hwmod_sysc_type1
,
1259 static struct omap_hwmod_class_sysconfig i2c_sysc
= {
1263 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
1264 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
1266 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1267 .sysc_fields
= &omap_hwmod_sysc_type1
,
1270 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class
= {
1272 .sysc
= &omap3xxx_wd_timer_sysc
,
1273 .pre_shutdown
= &omap2_wd_timer_disable
1277 static struct omap_hwmod_ocp_if
*omap3xxx_wd_timer2_slaves
[] = {
1278 &omap3xxx_l4_wkup__wd_timer2
,
1281 static struct omap_hwmod omap3xxx_wd_timer2_hwmod
= {
1282 .name
= "wd_timer2",
1283 .class = &omap3xxx_wd_timer_hwmod_class
,
1284 .main_clk
= "wdt2_fck",
1288 .module_bit
= OMAP3430_EN_WDT2_SHIFT
,
1289 .module_offs
= WKUP_MOD
,
1291 .idlest_idle_bit
= OMAP3430_ST_WDT2_SHIFT
,
1294 .slaves
= omap3xxx_wd_timer2_slaves
,
1295 .slaves_cnt
= ARRAY_SIZE(omap3xxx_wd_timer2_slaves
),
1296 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
1301 static struct omap_hwmod_class_sysconfig uart_sysc
= {
1305 .sysc_flags
= (SYSC_HAS_SIDLEMODE
|
1306 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
1308 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1309 .sysc_fields
= &omap_hwmod_sysc_type1
,
1312 static struct omap_hwmod_class uart_class
= {
1319 static struct omap_hwmod_irq_info uart1_mpu_irqs
[] = {
1320 { .irq
= INT_24XX_UART1_IRQ
, },
1323 static struct omap_hwmod_dma_info uart1_sdma_reqs
[] = {
1324 { .name
= "tx", .dma_req
= OMAP24XX_DMA_UART1_TX
, },
1325 { .name
= "rx", .dma_req
= OMAP24XX_DMA_UART1_RX
, },
1328 static struct omap_hwmod_ocp_if
*omap3xxx_uart1_slaves
[] = {
1329 &omap3_l4_core__uart1
,
1332 static struct omap_hwmod omap3xxx_uart1_hwmod
= {
1334 .mpu_irqs
= uart1_mpu_irqs
,
1335 .mpu_irqs_cnt
= ARRAY_SIZE(uart1_mpu_irqs
),
1336 .sdma_reqs
= uart1_sdma_reqs
,
1337 .sdma_reqs_cnt
= ARRAY_SIZE(uart1_sdma_reqs
),
1338 .main_clk
= "uart1_fck",
1341 .module_offs
= CORE_MOD
,
1343 .module_bit
= OMAP3430_EN_UART1_SHIFT
,
1345 .idlest_idle_bit
= OMAP3430_EN_UART1_SHIFT
,
1348 .slaves
= omap3xxx_uart1_slaves
,
1349 .slaves_cnt
= ARRAY_SIZE(omap3xxx_uart1_slaves
),
1350 .class = &uart_class
,
1351 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
1356 static struct omap_hwmod_irq_info uart2_mpu_irqs
[] = {
1357 { .irq
= INT_24XX_UART2_IRQ
, },
1360 static struct omap_hwmod_dma_info uart2_sdma_reqs
[] = {
1361 { .name
= "tx", .dma_req
= OMAP24XX_DMA_UART2_TX
, },
1362 { .name
= "rx", .dma_req
= OMAP24XX_DMA_UART2_RX
, },
1365 static struct omap_hwmod_ocp_if
*omap3xxx_uart2_slaves
[] = {
1366 &omap3_l4_core__uart2
,
1369 static struct omap_hwmod omap3xxx_uart2_hwmod
= {
1371 .mpu_irqs
= uart2_mpu_irqs
,
1372 .mpu_irqs_cnt
= ARRAY_SIZE(uart2_mpu_irqs
),
1373 .sdma_reqs
= uart2_sdma_reqs
,
1374 .sdma_reqs_cnt
= ARRAY_SIZE(uart2_sdma_reqs
),
1375 .main_clk
= "uart2_fck",
1378 .module_offs
= CORE_MOD
,
1380 .module_bit
= OMAP3430_EN_UART2_SHIFT
,
1382 .idlest_idle_bit
= OMAP3430_EN_UART2_SHIFT
,
1385 .slaves
= omap3xxx_uart2_slaves
,
1386 .slaves_cnt
= ARRAY_SIZE(omap3xxx_uart2_slaves
),
1387 .class = &uart_class
,
1388 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
1393 static struct omap_hwmod_irq_info uart3_mpu_irqs
[] = {
1394 { .irq
= INT_24XX_UART3_IRQ
, },
1397 static struct omap_hwmod_dma_info uart3_sdma_reqs
[] = {
1398 { .name
= "tx", .dma_req
= OMAP24XX_DMA_UART3_TX
, },
1399 { .name
= "rx", .dma_req
= OMAP24XX_DMA_UART3_RX
, },
1402 static struct omap_hwmod_ocp_if
*omap3xxx_uart3_slaves
[] = {
1403 &omap3_l4_per__uart3
,
1406 static struct omap_hwmod omap3xxx_uart3_hwmod
= {
1408 .mpu_irqs
= uart3_mpu_irqs
,
1409 .mpu_irqs_cnt
= ARRAY_SIZE(uart3_mpu_irqs
),
1410 .sdma_reqs
= uart3_sdma_reqs
,
1411 .sdma_reqs_cnt
= ARRAY_SIZE(uart3_sdma_reqs
),
1412 .main_clk
= "uart3_fck",
1415 .module_offs
= OMAP3430_PER_MOD
,
1417 .module_bit
= OMAP3430_EN_UART3_SHIFT
,
1419 .idlest_idle_bit
= OMAP3430_EN_UART3_SHIFT
,
1422 .slaves
= omap3xxx_uart3_slaves
,
1423 .slaves_cnt
= ARRAY_SIZE(omap3xxx_uart3_slaves
),
1424 .class = &uart_class
,
1425 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
1430 static struct omap_hwmod_irq_info uart4_mpu_irqs
[] = {
1431 { .irq
= INT_36XX_UART4_IRQ
, },
1434 static struct omap_hwmod_dma_info uart4_sdma_reqs
[] = {
1435 { .name
= "rx", .dma_req
= OMAP36XX_DMA_UART4_RX
, },
1436 { .name
= "tx", .dma_req
= OMAP36XX_DMA_UART4_TX
, },
1439 static struct omap_hwmod_ocp_if
*omap3xxx_uart4_slaves
[] = {
1440 &omap3_l4_per__uart4
,
1443 static struct omap_hwmod omap3xxx_uart4_hwmod
= {
1445 .mpu_irqs
= uart4_mpu_irqs
,
1446 .mpu_irqs_cnt
= ARRAY_SIZE(uart4_mpu_irqs
),
1447 .sdma_reqs
= uart4_sdma_reqs
,
1448 .sdma_reqs_cnt
= ARRAY_SIZE(uart4_sdma_reqs
),
1449 .main_clk
= "uart4_fck",
1452 .module_offs
= OMAP3430_PER_MOD
,
1454 .module_bit
= OMAP3630_EN_UART4_SHIFT
,
1456 .idlest_idle_bit
= OMAP3630_EN_UART4_SHIFT
,
1459 .slaves
= omap3xxx_uart4_slaves
,
1460 .slaves_cnt
= ARRAY_SIZE(omap3xxx_uart4_slaves
),
1461 .class = &uart_class
,
1462 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1
),
1465 static struct omap_hwmod_class i2c_class
= {
1472 * display sub-system
1475 static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc
= {
1477 .sysc_offs
= 0x0010,
1478 .syss_offs
= 0x0014,
1479 .sysc_flags
= (SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
),
1480 .sysc_fields
= &omap_hwmod_sysc_type1
,
1483 static struct omap_hwmod_class omap3xxx_dss_hwmod_class
= {
1485 .sysc
= &omap3xxx_dss_sysc
,
1489 static struct omap_hwmod_irq_info omap3xxx_dss_irqs
[] = {
1493 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs
[] = {
1494 { .name
= "dispc", .dma_req
= 5 },
1495 { .name
= "dsi1", .dma_req
= 74 },
1499 /* dss master ports */
1500 static struct omap_hwmod_ocp_if
*omap3xxx_dss_masters
[] = {
1504 static struct omap_hwmod_addr_space omap3xxx_dss_addrs
[] = {
1506 .pa_start
= 0x48050000,
1507 .pa_end
= 0x480503FF,
1508 .flags
= ADDR_TYPE_RT
1512 /* l4_core -> dss */
1513 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss
= {
1514 .master
= &omap3xxx_l4_core_hwmod
,
1515 .slave
= &omap3430es1_dss_core_hwmod
,
1517 .addr
= omap3xxx_dss_addrs
,
1518 .addr_cnt
= ARRAY_SIZE(omap3xxx_dss_addrs
),
1521 .l4_fw_region
= OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION
,
1522 .l4_prot_group
= OMAP3_L4_CORE_FW_DSS_PROT_GROUP
,
1523 .flags
= OMAP_FIREWALL_L4
,
1526 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1529 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss
= {
1530 .master
= &omap3xxx_l4_core_hwmod
,
1531 .slave
= &omap3xxx_dss_core_hwmod
,
1533 .addr
= omap3xxx_dss_addrs
,
1534 .addr_cnt
= ARRAY_SIZE(omap3xxx_dss_addrs
),
1537 .l4_fw_region
= OMAP3_L4_CORE_FW_DSS_CORE_REGION
,
1538 .l4_prot_group
= OMAP3_L4_CORE_FW_DSS_PROT_GROUP
,
1539 .flags
= OMAP_FIREWALL_L4
,
1542 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1545 /* dss slave ports */
1546 static struct omap_hwmod_ocp_if
*omap3430es1_dss_slaves
[] = {
1547 &omap3430es1_l4_core__dss
,
1550 static struct omap_hwmod_ocp_if
*omap3xxx_dss_slaves
[] = {
1551 &omap3xxx_l4_core__dss
,
1554 static struct omap_hwmod_opt_clk dss_opt_clks
[] = {
1555 { .role
= "tv_clk", .clk
= "dss_tv_fck" },
1556 { .role
= "dssclk", .clk
= "dss_96m_fck" },
1557 { .role
= "sys_clk", .clk
= "dss2_alwon_fck" },
1560 static struct omap_hwmod omap3430es1_dss_core_hwmod
= {
1562 .class = &omap3xxx_dss_hwmod_class
,
1563 .main_clk
= "dss1_alwon_fck", /* instead of dss_fck */
1564 .mpu_irqs
= omap3xxx_dss_irqs
,
1565 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_dss_irqs
),
1566 .sdma_reqs
= omap3xxx_dss_sdma_chs
,
1567 .sdma_reqs_cnt
= ARRAY_SIZE(omap3xxx_dss_sdma_chs
),
1572 .module_bit
= OMAP3430_EN_DSS1_SHIFT
,
1573 .module_offs
= OMAP3430_DSS_MOD
,
1575 .idlest_stdby_bit
= OMAP3430ES1_ST_DSS_SHIFT
,
1578 .opt_clks
= dss_opt_clks
,
1579 .opt_clks_cnt
= ARRAY_SIZE(dss_opt_clks
),
1580 .slaves
= omap3430es1_dss_slaves
,
1581 .slaves_cnt
= ARRAY_SIZE(omap3430es1_dss_slaves
),
1582 .masters
= omap3xxx_dss_masters
,
1583 .masters_cnt
= ARRAY_SIZE(omap3xxx_dss_masters
),
1584 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1
),
1585 .flags
= HWMOD_NO_IDLEST
,
1588 static struct omap_hwmod omap3xxx_dss_core_hwmod
= {
1590 .class = &omap3xxx_dss_hwmod_class
,
1591 .main_clk
= "dss1_alwon_fck", /* instead of dss_fck */
1592 .mpu_irqs
= omap3xxx_dss_irqs
,
1593 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_dss_irqs
),
1594 .sdma_reqs
= omap3xxx_dss_sdma_chs
,
1595 .sdma_reqs_cnt
= ARRAY_SIZE(omap3xxx_dss_sdma_chs
),
1600 .module_bit
= OMAP3430_EN_DSS1_SHIFT
,
1601 .module_offs
= OMAP3430_DSS_MOD
,
1603 .idlest_idle_bit
= OMAP3430ES2_ST_DSS_IDLE_SHIFT
,
1604 .idlest_stdby_bit
= OMAP3430ES2_ST_DSS_STDBY_SHIFT
,
1607 .opt_clks
= dss_opt_clks
,
1608 .opt_clks_cnt
= ARRAY_SIZE(dss_opt_clks
),
1609 .slaves
= omap3xxx_dss_slaves
,
1610 .slaves_cnt
= ARRAY_SIZE(omap3xxx_dss_slaves
),
1611 .masters
= omap3xxx_dss_masters
,
1612 .masters_cnt
= ARRAY_SIZE(omap3xxx_dss_masters
),
1613 .omap_chip
= OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2
|
1614 CHIP_IS_OMAP3630ES1
| CHIP_GE_OMAP3630ES1_1
),
1619 * display controller
1622 static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc
= {
1624 .sysc_offs
= 0x0010,
1625 .syss_offs
= 0x0014,
1626 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_CLOCKACTIVITY
|
1627 SYSC_HAS_MIDLEMODE
| SYSC_HAS_ENAWAKEUP
|
1628 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
),
1629 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1630 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
1631 .sysc_fields
= &omap_hwmod_sysc_type1
,
1634 static struct omap_hwmod_class omap3xxx_dispc_hwmod_class
= {
1636 .sysc
= &omap3xxx_dispc_sysc
,
1639 static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs
[] = {
1641 .pa_start
= 0x48050400,
1642 .pa_end
= 0x480507FF,
1643 .flags
= ADDR_TYPE_RT
1647 /* l4_core -> dss_dispc */
1648 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc
= {
1649 .master
= &omap3xxx_l4_core_hwmod
,
1650 .slave
= &omap3xxx_dss_dispc_hwmod
,
1652 .addr
= omap3xxx_dss_dispc_addrs
,
1653 .addr_cnt
= ARRAY_SIZE(omap3xxx_dss_dispc_addrs
),
1656 .l4_fw_region
= OMAP3_L4_CORE_FW_DSS_DISPC_REGION
,
1657 .l4_prot_group
= OMAP3_L4_CORE_FW_DSS_PROT_GROUP
,
1658 .flags
= OMAP_FIREWALL_L4
,
1661 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1664 /* dss_dispc slave ports */
1665 static struct omap_hwmod_ocp_if
*omap3xxx_dss_dispc_slaves
[] = {
1666 &omap3xxx_l4_core__dss_dispc
,
1669 static struct omap_hwmod omap3xxx_dss_dispc_hwmod
= {
1670 .name
= "dss_dispc",
1671 .class = &omap3xxx_dispc_hwmod_class
,
1672 .main_clk
= "dss1_alwon_fck",
1676 .module_bit
= OMAP3430_EN_DSS1_SHIFT
,
1677 .module_offs
= OMAP3430_DSS_MOD
,
1680 .slaves
= omap3xxx_dss_dispc_slaves
,
1681 .slaves_cnt
= ARRAY_SIZE(omap3xxx_dss_dispc_slaves
),
1682 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1
|
1683 CHIP_GE_OMAP3430ES2
| CHIP_IS_OMAP3630ES1
|
1684 CHIP_GE_OMAP3630ES1_1
),
1685 .flags
= HWMOD_NO_IDLEST
,
1690 * display serial interface controller
1693 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class
= {
1698 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs
[] = {
1700 .pa_start
= 0x4804FC00,
1701 .pa_end
= 0x4804FFFF,
1702 .flags
= ADDR_TYPE_RT
1706 /* l4_core -> dss_dsi1 */
1707 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1
= {
1708 .master
= &omap3xxx_l4_core_hwmod
,
1709 .slave
= &omap3xxx_dss_dsi1_hwmod
,
1710 .addr
= omap3xxx_dss_dsi1_addrs
,
1711 .addr_cnt
= ARRAY_SIZE(omap3xxx_dss_dsi1_addrs
),
1714 .l4_fw_region
= OMAP3_L4_CORE_FW_DSS_DSI_REGION
,
1715 .l4_prot_group
= OMAP3_L4_CORE_FW_DSS_PROT_GROUP
,
1716 .flags
= OMAP_FIREWALL_L4
,
1719 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1722 /* dss_dsi1 slave ports */
1723 static struct omap_hwmod_ocp_if
*omap3xxx_dss_dsi1_slaves
[] = {
1724 &omap3xxx_l4_core__dss_dsi1
,
1727 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod
= {
1729 .class = &omap3xxx_dsi_hwmod_class
,
1730 .main_clk
= "dss1_alwon_fck",
1734 .module_bit
= OMAP3430_EN_DSS1_SHIFT
,
1735 .module_offs
= OMAP3430_DSS_MOD
,
1738 .slaves
= omap3xxx_dss_dsi1_slaves
,
1739 .slaves_cnt
= ARRAY_SIZE(omap3xxx_dss_dsi1_slaves
),
1740 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1
|
1741 CHIP_GE_OMAP3430ES2
| CHIP_IS_OMAP3630ES1
|
1742 CHIP_GE_OMAP3630ES1_1
),
1743 .flags
= HWMOD_NO_IDLEST
,
1748 * remote frame buffer interface
1751 static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc
= {
1753 .sysc_offs
= 0x0010,
1754 .syss_offs
= 0x0014,
1755 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
1757 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1758 .sysc_fields
= &omap_hwmod_sysc_type1
,
1761 static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class
= {
1763 .sysc
= &omap3xxx_rfbi_sysc
,
1766 static struct omap_hwmod_addr_space omap3xxx_dss_rfbi_addrs
[] = {
1768 .pa_start
= 0x48050800,
1769 .pa_end
= 0x48050BFF,
1770 .flags
= ADDR_TYPE_RT
1774 /* l4_core -> dss_rfbi */
1775 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi
= {
1776 .master
= &omap3xxx_l4_core_hwmod
,
1777 .slave
= &omap3xxx_dss_rfbi_hwmod
,
1779 .addr
= omap3xxx_dss_rfbi_addrs
,
1780 .addr_cnt
= ARRAY_SIZE(omap3xxx_dss_rfbi_addrs
),
1783 .l4_fw_region
= OMAP3_L4_CORE_FW_DSS_RFBI_REGION
,
1784 .l4_prot_group
= OMAP3_L4_CORE_FW_DSS_PROT_GROUP
,
1785 .flags
= OMAP_FIREWALL_L4
,
1788 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1791 /* dss_rfbi slave ports */
1792 static struct omap_hwmod_ocp_if
*omap3xxx_dss_rfbi_slaves
[] = {
1793 &omap3xxx_l4_core__dss_rfbi
,
1796 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod
= {
1798 .class = &omap3xxx_rfbi_hwmod_class
,
1799 .main_clk
= "dss1_alwon_fck",
1803 .module_bit
= OMAP3430_EN_DSS1_SHIFT
,
1804 .module_offs
= OMAP3430_DSS_MOD
,
1807 .slaves
= omap3xxx_dss_rfbi_slaves
,
1808 .slaves_cnt
= ARRAY_SIZE(omap3xxx_dss_rfbi_slaves
),
1809 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1
|
1810 CHIP_GE_OMAP3430ES2
| CHIP_IS_OMAP3630ES1
|
1811 CHIP_GE_OMAP3630ES1_1
),
1812 .flags
= HWMOD_NO_IDLEST
,
1820 static struct omap_hwmod_class omap3xxx_venc_hwmod_class
= {
1825 static struct omap_hwmod_addr_space omap3xxx_dss_venc_addrs
[] = {
1827 .pa_start
= 0x48050C00,
1828 .pa_end
= 0x48050FFF,
1829 .flags
= ADDR_TYPE_RT
1833 /* l4_core -> dss_venc */
1834 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc
= {
1835 .master
= &omap3xxx_l4_core_hwmod
,
1836 .slave
= &omap3xxx_dss_venc_hwmod
,
1837 .clk
= "dss_tv_fck",
1838 .addr
= omap3xxx_dss_venc_addrs
,
1839 .addr_cnt
= ARRAY_SIZE(omap3xxx_dss_venc_addrs
),
1842 .l4_fw_region
= OMAP3_L4_CORE_FW_DSS_VENC_REGION
,
1843 .l4_prot_group
= OMAP3_L4_CORE_FW_DSS_PROT_GROUP
,
1844 .flags
= OMAP_FIREWALL_L4
,
1847 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1850 /* dss_venc slave ports */
1851 static struct omap_hwmod_ocp_if
*omap3xxx_dss_venc_slaves
[] = {
1852 &omap3xxx_l4_core__dss_venc
,
1855 static struct omap_hwmod omap3xxx_dss_venc_hwmod
= {
1857 .class = &omap3xxx_venc_hwmod_class
,
1858 .main_clk
= "dss1_alwon_fck",
1862 .module_bit
= OMAP3430_EN_DSS1_SHIFT
,
1863 .module_offs
= OMAP3430_DSS_MOD
,
1866 .slaves
= omap3xxx_dss_venc_slaves
,
1867 .slaves_cnt
= ARRAY_SIZE(omap3xxx_dss_venc_slaves
),
1868 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1
|
1869 CHIP_GE_OMAP3430ES2
| CHIP_IS_OMAP3630ES1
|
1870 CHIP_GE_OMAP3630ES1_1
),
1871 .flags
= HWMOD_NO_IDLEST
,
1876 static struct omap_i2c_dev_attr i2c1_dev_attr
= {
1877 .fifo_depth
= 8, /* bytes */
1880 static struct omap_hwmod_irq_info i2c1_mpu_irqs
[] = {
1881 { .irq
= INT_24XX_I2C1_IRQ
, },
1884 static struct omap_hwmod_dma_info i2c1_sdma_reqs
[] = {
1885 { .name
= "tx", .dma_req
= OMAP24XX_DMA_I2C1_TX
},
1886 { .name
= "rx", .dma_req
= OMAP24XX_DMA_I2C1_RX
},
1889 static struct omap_hwmod_ocp_if
*omap3xxx_i2c1_slaves
[] = {
1890 &omap3_l4_core__i2c1
,
1893 static struct omap_hwmod omap3xxx_i2c1_hwmod
= {
1895 .mpu_irqs
= i2c1_mpu_irqs
,
1896 .mpu_irqs_cnt
= ARRAY_SIZE(i2c1_mpu_irqs
),
1897 .sdma_reqs
= i2c1_sdma_reqs
,
1898 .sdma_reqs_cnt
= ARRAY_SIZE(i2c1_sdma_reqs
),
1899 .main_clk
= "i2c1_fck",
1902 .module_offs
= CORE_MOD
,
1904 .module_bit
= OMAP3430_EN_I2C1_SHIFT
,
1906 .idlest_idle_bit
= OMAP3430_ST_I2C1_SHIFT
,
1909 .slaves
= omap3xxx_i2c1_slaves
,
1910 .slaves_cnt
= ARRAY_SIZE(omap3xxx_i2c1_slaves
),
1911 .class = &i2c_class
,
1912 .dev_attr
= &i2c1_dev_attr
,
1913 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
1918 static struct omap_i2c_dev_attr i2c2_dev_attr
= {
1919 .fifo_depth
= 8, /* bytes */
1922 static struct omap_hwmod_irq_info i2c2_mpu_irqs
[] = {
1923 { .irq
= INT_24XX_I2C2_IRQ
, },
1926 static struct omap_hwmod_dma_info i2c2_sdma_reqs
[] = {
1927 { .name
= "tx", .dma_req
= OMAP24XX_DMA_I2C2_TX
},
1928 { .name
= "rx", .dma_req
= OMAP24XX_DMA_I2C2_RX
},
1931 static struct omap_hwmod_ocp_if
*omap3xxx_i2c2_slaves
[] = {
1932 &omap3_l4_core__i2c2
,
1935 static struct omap_hwmod omap3xxx_i2c2_hwmod
= {
1937 .mpu_irqs
= i2c2_mpu_irqs
,
1938 .mpu_irqs_cnt
= ARRAY_SIZE(i2c2_mpu_irqs
),
1939 .sdma_reqs
= i2c2_sdma_reqs
,
1940 .sdma_reqs_cnt
= ARRAY_SIZE(i2c2_sdma_reqs
),
1941 .main_clk
= "i2c2_fck",
1944 .module_offs
= CORE_MOD
,
1946 .module_bit
= OMAP3430_EN_I2C2_SHIFT
,
1948 .idlest_idle_bit
= OMAP3430_ST_I2C2_SHIFT
,
1951 .slaves
= omap3xxx_i2c2_slaves
,
1952 .slaves_cnt
= ARRAY_SIZE(omap3xxx_i2c2_slaves
),
1953 .class = &i2c_class
,
1954 .dev_attr
= &i2c2_dev_attr
,
1955 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
1960 static struct omap_i2c_dev_attr i2c3_dev_attr
= {
1961 .fifo_depth
= 64, /* bytes */
1964 static struct omap_hwmod_irq_info i2c3_mpu_irqs
[] = {
1965 { .irq
= INT_34XX_I2C3_IRQ
, },
1968 static struct omap_hwmod_dma_info i2c3_sdma_reqs
[] = {
1969 { .name
= "tx", .dma_req
= OMAP34XX_DMA_I2C3_TX
},
1970 { .name
= "rx", .dma_req
= OMAP34XX_DMA_I2C3_RX
},
1973 static struct omap_hwmod_ocp_if
*omap3xxx_i2c3_slaves
[] = {
1974 &omap3_l4_core__i2c3
,
1977 static struct omap_hwmod omap3xxx_i2c3_hwmod
= {
1979 .mpu_irqs
= i2c3_mpu_irqs
,
1980 .mpu_irqs_cnt
= ARRAY_SIZE(i2c3_mpu_irqs
),
1981 .sdma_reqs
= i2c3_sdma_reqs
,
1982 .sdma_reqs_cnt
= ARRAY_SIZE(i2c3_sdma_reqs
),
1983 .main_clk
= "i2c3_fck",
1986 .module_offs
= CORE_MOD
,
1988 .module_bit
= OMAP3430_EN_I2C3_SHIFT
,
1990 .idlest_idle_bit
= OMAP3430_ST_I2C3_SHIFT
,
1993 .slaves
= omap3xxx_i2c3_slaves
,
1994 .slaves_cnt
= ARRAY_SIZE(omap3xxx_i2c3_slaves
),
1995 .class = &i2c_class
,
1996 .dev_attr
= &i2c3_dev_attr
,
1997 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
2000 /* l4_wkup -> gpio1 */
2001 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs
[] = {
2003 .pa_start
= 0x48310000,
2004 .pa_end
= 0x483101ff,
2005 .flags
= ADDR_TYPE_RT
2009 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1
= {
2010 .master
= &omap3xxx_l4_wkup_hwmod
,
2011 .slave
= &omap3xxx_gpio1_hwmod
,
2012 .addr
= omap3xxx_gpio1_addrs
,
2013 .addr_cnt
= ARRAY_SIZE(omap3xxx_gpio1_addrs
),
2014 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2017 /* l4_per -> gpio2 */
2018 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs
[] = {
2020 .pa_start
= 0x49050000,
2021 .pa_end
= 0x490501ff,
2022 .flags
= ADDR_TYPE_RT
2026 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2
= {
2027 .master
= &omap3xxx_l4_per_hwmod
,
2028 .slave
= &omap3xxx_gpio2_hwmod
,
2029 .addr
= omap3xxx_gpio2_addrs
,
2030 .addr_cnt
= ARRAY_SIZE(omap3xxx_gpio2_addrs
),
2031 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2034 /* l4_per -> gpio3 */
2035 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs
[] = {
2037 .pa_start
= 0x49052000,
2038 .pa_end
= 0x490521ff,
2039 .flags
= ADDR_TYPE_RT
2043 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3
= {
2044 .master
= &omap3xxx_l4_per_hwmod
,
2045 .slave
= &omap3xxx_gpio3_hwmod
,
2046 .addr
= omap3xxx_gpio3_addrs
,
2047 .addr_cnt
= ARRAY_SIZE(omap3xxx_gpio3_addrs
),
2048 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2051 /* l4_per -> gpio4 */
2052 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs
[] = {
2054 .pa_start
= 0x49054000,
2055 .pa_end
= 0x490541ff,
2056 .flags
= ADDR_TYPE_RT
2060 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4
= {
2061 .master
= &omap3xxx_l4_per_hwmod
,
2062 .slave
= &omap3xxx_gpio4_hwmod
,
2063 .addr
= omap3xxx_gpio4_addrs
,
2064 .addr_cnt
= ARRAY_SIZE(omap3xxx_gpio4_addrs
),
2065 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2068 /* l4_per -> gpio5 */
2069 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs
[] = {
2071 .pa_start
= 0x49056000,
2072 .pa_end
= 0x490561ff,
2073 .flags
= ADDR_TYPE_RT
2077 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5
= {
2078 .master
= &omap3xxx_l4_per_hwmod
,
2079 .slave
= &omap3xxx_gpio5_hwmod
,
2080 .addr
= omap3xxx_gpio5_addrs
,
2081 .addr_cnt
= ARRAY_SIZE(omap3xxx_gpio5_addrs
),
2082 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2085 /* l4_per -> gpio6 */
2086 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs
[] = {
2088 .pa_start
= 0x49058000,
2089 .pa_end
= 0x490581ff,
2090 .flags
= ADDR_TYPE_RT
2094 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6
= {
2095 .master
= &omap3xxx_l4_per_hwmod
,
2096 .slave
= &omap3xxx_gpio6_hwmod
,
2097 .addr
= omap3xxx_gpio6_addrs
,
2098 .addr_cnt
= ARRAY_SIZE(omap3xxx_gpio6_addrs
),
2099 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2104 * general purpose io module
2107 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc
= {
2109 .sysc_offs
= 0x0010,
2110 .syss_offs
= 0x0014,
2111 .sysc_flags
= (SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
2112 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
),
2113 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
2114 .sysc_fields
= &omap_hwmod_sysc_type1
,
2117 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class
= {
2119 .sysc
= &omap3xxx_gpio_sysc
,
2124 static struct omap_gpio_dev_attr gpio_dev_attr
= {
2130 static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs
[] = {
2131 { .irq
= 29 }, /* INT_34XX_GPIO_BANK1 */
2134 static struct omap_hwmod_opt_clk gpio1_opt_clks
[] = {
2135 { .role
= "dbclk", .clk
= "gpio1_dbck", },
2138 static struct omap_hwmod_ocp_if
*omap3xxx_gpio1_slaves
[] = {
2139 &omap3xxx_l4_wkup__gpio1
,
2142 static struct omap_hwmod omap3xxx_gpio1_hwmod
= {
2144 .mpu_irqs
= omap3xxx_gpio1_irqs
,
2145 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_gpio1_irqs
),
2146 .main_clk
= "gpio1_ick",
2147 .opt_clks
= gpio1_opt_clks
,
2148 .opt_clks_cnt
= ARRAY_SIZE(gpio1_opt_clks
),
2152 .module_bit
= OMAP3430_EN_GPIO1_SHIFT
,
2153 .module_offs
= WKUP_MOD
,
2155 .idlest_idle_bit
= OMAP3430_ST_GPIO1_SHIFT
,
2158 .slaves
= omap3xxx_gpio1_slaves
,
2159 .slaves_cnt
= ARRAY_SIZE(omap3xxx_gpio1_slaves
),
2160 .class = &omap3xxx_gpio_hwmod_class
,
2161 .dev_attr
= &gpio_dev_attr
,
2162 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
2166 static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs
[] = {
2167 { .irq
= 30 }, /* INT_34XX_GPIO_BANK2 */
2170 static struct omap_hwmod_opt_clk gpio2_opt_clks
[] = {
2171 { .role
= "dbclk", .clk
= "gpio2_dbck", },
2174 static struct omap_hwmod_ocp_if
*omap3xxx_gpio2_slaves
[] = {
2175 &omap3xxx_l4_per__gpio2
,
2178 static struct omap_hwmod omap3xxx_gpio2_hwmod
= {
2180 .mpu_irqs
= omap3xxx_gpio2_irqs
,
2181 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_gpio2_irqs
),
2182 .main_clk
= "gpio2_ick",
2183 .opt_clks
= gpio2_opt_clks
,
2184 .opt_clks_cnt
= ARRAY_SIZE(gpio2_opt_clks
),
2188 .module_bit
= OMAP3430_EN_GPIO2_SHIFT
,
2189 .module_offs
= OMAP3430_PER_MOD
,
2191 .idlest_idle_bit
= OMAP3430_ST_GPIO2_SHIFT
,
2194 .slaves
= omap3xxx_gpio2_slaves
,
2195 .slaves_cnt
= ARRAY_SIZE(omap3xxx_gpio2_slaves
),
2196 .class = &omap3xxx_gpio_hwmod_class
,
2197 .dev_attr
= &gpio_dev_attr
,
2198 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
2202 static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs
[] = {
2203 { .irq
= 31 }, /* INT_34XX_GPIO_BANK3 */
2206 static struct omap_hwmod_opt_clk gpio3_opt_clks
[] = {
2207 { .role
= "dbclk", .clk
= "gpio3_dbck", },
2210 static struct omap_hwmod_ocp_if
*omap3xxx_gpio3_slaves
[] = {
2211 &omap3xxx_l4_per__gpio3
,
2214 static struct omap_hwmod omap3xxx_gpio3_hwmod
= {
2216 .mpu_irqs
= omap3xxx_gpio3_irqs
,
2217 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_gpio3_irqs
),
2218 .main_clk
= "gpio3_ick",
2219 .opt_clks
= gpio3_opt_clks
,
2220 .opt_clks_cnt
= ARRAY_SIZE(gpio3_opt_clks
),
2224 .module_bit
= OMAP3430_EN_GPIO3_SHIFT
,
2225 .module_offs
= OMAP3430_PER_MOD
,
2227 .idlest_idle_bit
= OMAP3430_ST_GPIO3_SHIFT
,
2230 .slaves
= omap3xxx_gpio3_slaves
,
2231 .slaves_cnt
= ARRAY_SIZE(omap3xxx_gpio3_slaves
),
2232 .class = &omap3xxx_gpio_hwmod_class
,
2233 .dev_attr
= &gpio_dev_attr
,
2234 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
2238 static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs
[] = {
2239 { .irq
= 32 }, /* INT_34XX_GPIO_BANK4 */
2242 static struct omap_hwmod_opt_clk gpio4_opt_clks
[] = {
2243 { .role
= "dbclk", .clk
= "gpio4_dbck", },
2246 static struct omap_hwmod_ocp_if
*omap3xxx_gpio4_slaves
[] = {
2247 &omap3xxx_l4_per__gpio4
,
2250 static struct omap_hwmod omap3xxx_gpio4_hwmod
= {
2252 .mpu_irqs
= omap3xxx_gpio4_irqs
,
2253 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_gpio4_irqs
),
2254 .main_clk
= "gpio4_ick",
2255 .opt_clks
= gpio4_opt_clks
,
2256 .opt_clks_cnt
= ARRAY_SIZE(gpio4_opt_clks
),
2260 .module_bit
= OMAP3430_EN_GPIO4_SHIFT
,
2261 .module_offs
= OMAP3430_PER_MOD
,
2263 .idlest_idle_bit
= OMAP3430_ST_GPIO4_SHIFT
,
2266 .slaves
= omap3xxx_gpio4_slaves
,
2267 .slaves_cnt
= ARRAY_SIZE(omap3xxx_gpio4_slaves
),
2268 .class = &omap3xxx_gpio_hwmod_class
,
2269 .dev_attr
= &gpio_dev_attr
,
2270 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
2274 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs
[] = {
2275 { .irq
= 33 }, /* INT_34XX_GPIO_BANK5 */
2278 static struct omap_hwmod_opt_clk gpio5_opt_clks
[] = {
2279 { .role
= "dbclk", .clk
= "gpio5_dbck", },
2282 static struct omap_hwmod_ocp_if
*omap3xxx_gpio5_slaves
[] = {
2283 &omap3xxx_l4_per__gpio5
,
2286 static struct omap_hwmod omap3xxx_gpio5_hwmod
= {
2288 .mpu_irqs
= omap3xxx_gpio5_irqs
,
2289 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_gpio5_irqs
),
2290 .main_clk
= "gpio5_ick",
2291 .opt_clks
= gpio5_opt_clks
,
2292 .opt_clks_cnt
= ARRAY_SIZE(gpio5_opt_clks
),
2296 .module_bit
= OMAP3430_EN_GPIO5_SHIFT
,
2297 .module_offs
= OMAP3430_PER_MOD
,
2299 .idlest_idle_bit
= OMAP3430_ST_GPIO5_SHIFT
,
2302 .slaves
= omap3xxx_gpio5_slaves
,
2303 .slaves_cnt
= ARRAY_SIZE(omap3xxx_gpio5_slaves
),
2304 .class = &omap3xxx_gpio_hwmod_class
,
2305 .dev_attr
= &gpio_dev_attr
,
2306 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
2310 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs
[] = {
2311 { .irq
= 34 }, /* INT_34XX_GPIO_BANK6 */
2314 static struct omap_hwmod_opt_clk gpio6_opt_clks
[] = {
2315 { .role
= "dbclk", .clk
= "gpio6_dbck", },
2318 static struct omap_hwmod_ocp_if
*omap3xxx_gpio6_slaves
[] = {
2319 &omap3xxx_l4_per__gpio6
,
2322 static struct omap_hwmod omap3xxx_gpio6_hwmod
= {
2324 .mpu_irqs
= omap3xxx_gpio6_irqs
,
2325 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_gpio6_irqs
),
2326 .main_clk
= "gpio6_ick",
2327 .opt_clks
= gpio6_opt_clks
,
2328 .opt_clks_cnt
= ARRAY_SIZE(gpio6_opt_clks
),
2332 .module_bit
= OMAP3430_EN_GPIO6_SHIFT
,
2333 .module_offs
= OMAP3430_PER_MOD
,
2335 .idlest_idle_bit
= OMAP3430_ST_GPIO6_SHIFT
,
2338 .slaves
= omap3xxx_gpio6_slaves
,
2339 .slaves_cnt
= ARRAY_SIZE(omap3xxx_gpio6_slaves
),
2340 .class = &omap3xxx_gpio_hwmod_class
,
2341 .dev_attr
= &gpio_dev_attr
,
2342 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
2345 /* dma_system -> L3 */
2346 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3
= {
2347 .master
= &omap3xxx_dma_system_hwmod
,
2348 .slave
= &omap3xxx_l3_main_hwmod
,
2349 .clk
= "core_l3_ick",
2350 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2353 /* dma attributes */
2354 static struct omap_dma_dev_attr dma_dev_attr
= {
2355 .dev_caps
= RESERVE_CHANNEL
| DMA_LINKED_LCH
| GLOBAL_PRIORITY
|
2356 IS_CSSA_32
| IS_CDSA_32
| IS_RW_PRIORITY
,
2360 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc
= {
2362 .sysc_offs
= 0x002c,
2363 .syss_offs
= 0x0028,
2364 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
2365 SYSC_HAS_MIDLEMODE
| SYSC_HAS_CLOCKACTIVITY
|
2366 SYSC_HAS_EMUFREE
| SYSC_HAS_AUTOIDLE
),
2367 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2368 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
2369 .sysc_fields
= &omap_hwmod_sysc_type1
,
2372 static struct omap_hwmod_class omap3xxx_dma_hwmod_class
= {
2374 .sysc
= &omap3xxx_dma_sysc
,
2378 static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs
[] = {
2379 { .name
= "0", .irq
= 12 }, /* INT_24XX_SDMA_IRQ0 */
2380 { .name
= "1", .irq
= 13 }, /* INT_24XX_SDMA_IRQ1 */
2381 { .name
= "2", .irq
= 14 }, /* INT_24XX_SDMA_IRQ2 */
2382 { .name
= "3", .irq
= 15 }, /* INT_24XX_SDMA_IRQ3 */
2385 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs
[] = {
2387 .pa_start
= 0x48056000,
2388 .pa_end
= 0x4a0560ff,
2389 .flags
= ADDR_TYPE_RT
2393 /* dma_system master ports */
2394 static struct omap_hwmod_ocp_if
*omap3xxx_dma_system_masters
[] = {
2395 &omap3xxx_dma_system__l3
,
2398 /* l4_cfg -> dma_system */
2399 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system
= {
2400 .master
= &omap3xxx_l4_core_hwmod
,
2401 .slave
= &omap3xxx_dma_system_hwmod
,
2402 .clk
= "core_l4_ick",
2403 .addr
= omap3xxx_dma_system_addrs
,
2404 .addr_cnt
= ARRAY_SIZE(omap3xxx_dma_system_addrs
),
2405 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2408 /* dma_system slave ports */
2409 static struct omap_hwmod_ocp_if
*omap3xxx_dma_system_slaves
[] = {
2410 &omap3xxx_l4_core__dma_system
,
2413 static struct omap_hwmod omap3xxx_dma_system_hwmod
= {
2415 .class = &omap3xxx_dma_hwmod_class
,
2416 .mpu_irqs
= omap3xxx_dma_system_irqs
,
2417 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_dma_system_irqs
),
2418 .main_clk
= "core_l3_ick",
2421 .module_offs
= CORE_MOD
,
2423 .module_bit
= OMAP3430_ST_SDMA_SHIFT
,
2425 .idlest_idle_bit
= OMAP3430_ST_SDMA_SHIFT
,
2428 .slaves
= omap3xxx_dma_system_slaves
,
2429 .slaves_cnt
= ARRAY_SIZE(omap3xxx_dma_system_slaves
),
2430 .masters
= omap3xxx_dma_system_masters
,
2431 .masters_cnt
= ARRAY_SIZE(omap3xxx_dma_system_masters
),
2432 .dev_attr
= &dma_dev_attr
,
2433 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
2434 .flags
= HWMOD_NO_IDLEST
,
2439 * multi channel buffered serial port controller
2442 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc
= {
2443 .sysc_offs
= 0x008c,
2444 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_ENAWAKEUP
|
2445 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
2446 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
2447 .sysc_fields
= &omap_hwmod_sysc_type1
,
2451 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class
= {
2453 .sysc
= &omap3xxx_mcbsp_sysc
,
2454 .rev
= MCBSP_CONFIG_TYPE3
,
2458 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs
[] = {
2459 { .name
= "irq", .irq
= 16 },
2460 { .name
= "tx", .irq
= 59 },
2461 { .name
= "rx", .irq
= 60 },
2464 static struct omap_hwmod_dma_info omap3xxx_mcbsp1_sdma_chs
[] = {
2465 { .name
= "rx", .dma_req
= 32 },
2466 { .name
= "tx", .dma_req
= 31 },
2469 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs
[] = {
2472 .pa_start
= 0x48074000,
2473 .pa_end
= 0x480740ff,
2474 .flags
= ADDR_TYPE_RT
2478 /* l4_core -> mcbsp1 */
2479 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1
= {
2480 .master
= &omap3xxx_l4_core_hwmod
,
2481 .slave
= &omap3xxx_mcbsp1_hwmod
,
2482 .clk
= "mcbsp1_ick",
2483 .addr
= omap3xxx_mcbsp1_addrs
,
2484 .addr_cnt
= ARRAY_SIZE(omap3xxx_mcbsp1_addrs
),
2485 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2488 /* mcbsp1 slave ports */
2489 static struct omap_hwmod_ocp_if
*omap3xxx_mcbsp1_slaves
[] = {
2490 &omap3xxx_l4_core__mcbsp1
,
2493 static struct omap_hwmod omap3xxx_mcbsp1_hwmod
= {
2495 .class = &omap3xxx_mcbsp_hwmod_class
,
2496 .mpu_irqs
= omap3xxx_mcbsp1_irqs
,
2497 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_mcbsp1_irqs
),
2498 .sdma_reqs
= omap3xxx_mcbsp1_sdma_chs
,
2499 .sdma_reqs_cnt
= ARRAY_SIZE(omap3xxx_mcbsp1_sdma_chs
),
2500 .main_clk
= "mcbsp1_fck",
2504 .module_bit
= OMAP3430_EN_MCBSP1_SHIFT
,
2505 .module_offs
= CORE_MOD
,
2507 .idlest_idle_bit
= OMAP3430_ST_MCBSP1_SHIFT
,
2510 .slaves
= omap3xxx_mcbsp1_slaves
,
2511 .slaves_cnt
= ARRAY_SIZE(omap3xxx_mcbsp1_slaves
),
2512 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
2516 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs
[] = {
2517 { .name
= "irq", .irq
= 17 },
2518 { .name
= "tx", .irq
= 62 },
2519 { .name
= "rx", .irq
= 63 },
2522 static struct omap_hwmod_dma_info omap3xxx_mcbsp2_sdma_chs
[] = {
2523 { .name
= "rx", .dma_req
= 34 },
2524 { .name
= "tx", .dma_req
= 33 },
2527 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs
[] = {
2530 .pa_start
= 0x49022000,
2531 .pa_end
= 0x490220ff,
2532 .flags
= ADDR_TYPE_RT
2536 /* l4_per -> mcbsp2 */
2537 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2
= {
2538 .master
= &omap3xxx_l4_per_hwmod
,
2539 .slave
= &omap3xxx_mcbsp2_hwmod
,
2540 .clk
= "mcbsp2_ick",
2541 .addr
= omap3xxx_mcbsp2_addrs
,
2542 .addr_cnt
= ARRAY_SIZE(omap3xxx_mcbsp2_addrs
),
2543 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2546 /* mcbsp2 slave ports */
2547 static struct omap_hwmod_ocp_if
*omap3xxx_mcbsp2_slaves
[] = {
2548 &omap3xxx_l4_per__mcbsp2
,
2551 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr
= {
2552 .sidetone
= "mcbsp2_sidetone",
2555 static struct omap_hwmod omap3xxx_mcbsp2_hwmod
= {
2557 .class = &omap3xxx_mcbsp_hwmod_class
,
2558 .mpu_irqs
= omap3xxx_mcbsp2_irqs
,
2559 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_mcbsp2_irqs
),
2560 .sdma_reqs
= omap3xxx_mcbsp2_sdma_chs
,
2561 .sdma_reqs_cnt
= ARRAY_SIZE(omap3xxx_mcbsp2_sdma_chs
),
2562 .main_clk
= "mcbsp2_fck",
2566 .module_bit
= OMAP3430_EN_MCBSP2_SHIFT
,
2567 .module_offs
= OMAP3430_PER_MOD
,
2569 .idlest_idle_bit
= OMAP3430_ST_MCBSP2_SHIFT
,
2572 .slaves
= omap3xxx_mcbsp2_slaves
,
2573 .slaves_cnt
= ARRAY_SIZE(omap3xxx_mcbsp2_slaves
),
2574 .dev_attr
= &omap34xx_mcbsp2_dev_attr
,
2575 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
2579 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs
[] = {
2580 { .name
= "irq", .irq
= 22 },
2581 { .name
= "tx", .irq
= 89 },
2582 { .name
= "rx", .irq
= 90 },
2585 static struct omap_hwmod_dma_info omap3xxx_mcbsp3_sdma_chs
[] = {
2586 { .name
= "rx", .dma_req
= 18 },
2587 { .name
= "tx", .dma_req
= 17 },
2590 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs
[] = {
2593 .pa_start
= 0x49024000,
2594 .pa_end
= 0x490240ff,
2595 .flags
= ADDR_TYPE_RT
2599 /* l4_per -> mcbsp3 */
2600 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3
= {
2601 .master
= &omap3xxx_l4_per_hwmod
,
2602 .slave
= &omap3xxx_mcbsp3_hwmod
,
2603 .clk
= "mcbsp3_ick",
2604 .addr
= omap3xxx_mcbsp3_addrs
,
2605 .addr_cnt
= ARRAY_SIZE(omap3xxx_mcbsp3_addrs
),
2606 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2609 /* mcbsp3 slave ports */
2610 static struct omap_hwmod_ocp_if
*omap3xxx_mcbsp3_slaves
[] = {
2611 &omap3xxx_l4_per__mcbsp3
,
2614 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr
= {
2615 .sidetone
= "mcbsp3_sidetone",
2618 static struct omap_hwmod omap3xxx_mcbsp3_hwmod
= {
2620 .class = &omap3xxx_mcbsp_hwmod_class
,
2621 .mpu_irqs
= omap3xxx_mcbsp3_irqs
,
2622 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_mcbsp3_irqs
),
2623 .sdma_reqs
= omap3xxx_mcbsp3_sdma_chs
,
2624 .sdma_reqs_cnt
= ARRAY_SIZE(omap3xxx_mcbsp3_sdma_chs
),
2625 .main_clk
= "mcbsp3_fck",
2629 .module_bit
= OMAP3430_EN_MCBSP3_SHIFT
,
2630 .module_offs
= OMAP3430_PER_MOD
,
2632 .idlest_idle_bit
= OMAP3430_ST_MCBSP3_SHIFT
,
2635 .slaves
= omap3xxx_mcbsp3_slaves
,
2636 .slaves_cnt
= ARRAY_SIZE(omap3xxx_mcbsp3_slaves
),
2637 .dev_attr
= &omap34xx_mcbsp3_dev_attr
,
2638 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
2642 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs
[] = {
2643 { .name
= "irq", .irq
= 23 },
2644 { .name
= "tx", .irq
= 54 },
2645 { .name
= "rx", .irq
= 55 },
2648 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs
[] = {
2649 { .name
= "rx", .dma_req
= 20 },
2650 { .name
= "tx", .dma_req
= 19 },
2653 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs
[] = {
2656 .pa_start
= 0x49026000,
2657 .pa_end
= 0x490260ff,
2658 .flags
= ADDR_TYPE_RT
2662 /* l4_per -> mcbsp4 */
2663 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4
= {
2664 .master
= &omap3xxx_l4_per_hwmod
,
2665 .slave
= &omap3xxx_mcbsp4_hwmod
,
2666 .clk
= "mcbsp4_ick",
2667 .addr
= omap3xxx_mcbsp4_addrs
,
2668 .addr_cnt
= ARRAY_SIZE(omap3xxx_mcbsp4_addrs
),
2669 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2672 /* mcbsp4 slave ports */
2673 static struct omap_hwmod_ocp_if
*omap3xxx_mcbsp4_slaves
[] = {
2674 &omap3xxx_l4_per__mcbsp4
,
2677 static struct omap_hwmod omap3xxx_mcbsp4_hwmod
= {
2679 .class = &omap3xxx_mcbsp_hwmod_class
,
2680 .mpu_irqs
= omap3xxx_mcbsp4_irqs
,
2681 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_mcbsp4_irqs
),
2682 .sdma_reqs
= omap3xxx_mcbsp4_sdma_chs
,
2683 .sdma_reqs_cnt
= ARRAY_SIZE(omap3xxx_mcbsp4_sdma_chs
),
2684 .main_clk
= "mcbsp4_fck",
2688 .module_bit
= OMAP3430_EN_MCBSP4_SHIFT
,
2689 .module_offs
= OMAP3430_PER_MOD
,
2691 .idlest_idle_bit
= OMAP3430_ST_MCBSP4_SHIFT
,
2694 .slaves
= omap3xxx_mcbsp4_slaves
,
2695 .slaves_cnt
= ARRAY_SIZE(omap3xxx_mcbsp4_slaves
),
2696 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
2700 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs
[] = {
2701 { .name
= "irq", .irq
= 27 },
2702 { .name
= "tx", .irq
= 81 },
2703 { .name
= "rx", .irq
= 82 },
2706 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs
[] = {
2707 { .name
= "rx", .dma_req
= 22 },
2708 { .name
= "tx", .dma_req
= 21 },
2711 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs
[] = {
2714 .pa_start
= 0x48096000,
2715 .pa_end
= 0x480960ff,
2716 .flags
= ADDR_TYPE_RT
2720 /* l4_core -> mcbsp5 */
2721 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5
= {
2722 .master
= &omap3xxx_l4_core_hwmod
,
2723 .slave
= &omap3xxx_mcbsp5_hwmod
,
2724 .clk
= "mcbsp5_ick",
2725 .addr
= omap3xxx_mcbsp5_addrs
,
2726 .addr_cnt
= ARRAY_SIZE(omap3xxx_mcbsp5_addrs
),
2727 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2730 /* mcbsp5 slave ports */
2731 static struct omap_hwmod_ocp_if
*omap3xxx_mcbsp5_slaves
[] = {
2732 &omap3xxx_l4_core__mcbsp5
,
2735 static struct omap_hwmod omap3xxx_mcbsp5_hwmod
= {
2737 .class = &omap3xxx_mcbsp_hwmod_class
,
2738 .mpu_irqs
= omap3xxx_mcbsp5_irqs
,
2739 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_mcbsp5_irqs
),
2740 .sdma_reqs
= omap3xxx_mcbsp5_sdma_chs
,
2741 .sdma_reqs_cnt
= ARRAY_SIZE(omap3xxx_mcbsp5_sdma_chs
),
2742 .main_clk
= "mcbsp5_fck",
2746 .module_bit
= OMAP3430_EN_MCBSP5_SHIFT
,
2747 .module_offs
= CORE_MOD
,
2749 .idlest_idle_bit
= OMAP3430_ST_MCBSP5_SHIFT
,
2752 .slaves
= omap3xxx_mcbsp5_slaves
,
2753 .slaves_cnt
= ARRAY_SIZE(omap3xxx_mcbsp5_slaves
),
2754 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
2756 /* 'mcbsp sidetone' class */
2758 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc
= {
2759 .sysc_offs
= 0x0010,
2760 .sysc_flags
= SYSC_HAS_AUTOIDLE
,
2761 .sysc_fields
= &omap_hwmod_sysc_type1
,
2764 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class
= {
2765 .name
= "mcbsp_sidetone",
2766 .sysc
= &omap3xxx_mcbsp_sidetone_sysc
,
2769 /* mcbsp2_sidetone */
2770 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs
[] = {
2771 { .name
= "irq", .irq
= 4 },
2774 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs
[] = {
2777 .pa_start
= 0x49028000,
2778 .pa_end
= 0x490280ff,
2779 .flags
= ADDR_TYPE_RT
2783 /* l4_per -> mcbsp2_sidetone */
2784 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone
= {
2785 .master
= &omap3xxx_l4_per_hwmod
,
2786 .slave
= &omap3xxx_mcbsp2_sidetone_hwmod
,
2787 .clk
= "mcbsp2_ick",
2788 .addr
= omap3xxx_mcbsp2_sidetone_addrs
,
2789 .addr_cnt
= ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_addrs
),
2790 .user
= OCP_USER_MPU
,
2793 /* mcbsp2_sidetone slave ports */
2794 static struct omap_hwmod_ocp_if
*omap3xxx_mcbsp2_sidetone_slaves
[] = {
2795 &omap3xxx_l4_per__mcbsp2_sidetone
,
2798 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod
= {
2799 .name
= "mcbsp2_sidetone",
2800 .class = &omap3xxx_mcbsp_sidetone_hwmod_class
,
2801 .mpu_irqs
= omap3xxx_mcbsp2_sidetone_irqs
,
2802 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_irqs
),
2803 .main_clk
= "mcbsp2_fck",
2807 .module_bit
= OMAP3430_EN_MCBSP2_SHIFT
,
2808 .module_offs
= OMAP3430_PER_MOD
,
2810 .idlest_idle_bit
= OMAP3430_ST_MCBSP2_SHIFT
,
2813 .slaves
= omap3xxx_mcbsp2_sidetone_slaves
,
2814 .slaves_cnt
= ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves
),
2815 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
2818 /* mcbsp3_sidetone */
2819 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs
[] = {
2820 { .name
= "irq", .irq
= 5 },
2823 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs
[] = {
2826 .pa_start
= 0x4902A000,
2827 .pa_end
= 0x4902A0ff,
2828 .flags
= ADDR_TYPE_RT
2832 /* l4_per -> mcbsp3_sidetone */
2833 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone
= {
2834 .master
= &omap3xxx_l4_per_hwmod
,
2835 .slave
= &omap3xxx_mcbsp3_sidetone_hwmod
,
2836 .clk
= "mcbsp3_ick",
2837 .addr
= omap3xxx_mcbsp3_sidetone_addrs
,
2838 .addr_cnt
= ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_addrs
),
2839 .user
= OCP_USER_MPU
,
2842 /* mcbsp3_sidetone slave ports */
2843 static struct omap_hwmod_ocp_if
*omap3xxx_mcbsp3_sidetone_slaves
[] = {
2844 &omap3xxx_l4_per__mcbsp3_sidetone
,
2847 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod
= {
2848 .name
= "mcbsp3_sidetone",
2849 .class = &omap3xxx_mcbsp_sidetone_hwmod_class
,
2850 .mpu_irqs
= omap3xxx_mcbsp3_sidetone_irqs
,
2851 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_irqs
),
2852 .main_clk
= "mcbsp3_fck",
2856 .module_bit
= OMAP3430_EN_MCBSP3_SHIFT
,
2857 .module_offs
= OMAP3430_PER_MOD
,
2859 .idlest_idle_bit
= OMAP3430_ST_MCBSP3_SHIFT
,
2862 .slaves
= omap3xxx_mcbsp3_sidetone_slaves
,
2863 .slaves_cnt
= ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves
),
2864 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
2869 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields
= {
2873 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc
= {
2875 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_NO_CACHE
),
2876 .clockact
= CLOCKACT_TEST_ICLK
,
2877 .sysc_fields
= &omap34xx_sr_sysc_fields
,
2880 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class
= {
2881 .name
= "smartreflex",
2882 .sysc
= &omap34xx_sr_sysc
,
2886 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields
= {
2891 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc
= {
2893 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
2894 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_ENAWAKEUP
|
2896 .sysc_fields
= &omap36xx_sr_sysc_fields
,
2899 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class
= {
2900 .name
= "smartreflex",
2901 .sysc
= &omap36xx_sr_sysc
,
2906 static struct omap_hwmod_ocp_if
*omap3_sr1_slaves
[] = {
2907 &omap3_l4_core__sr1
,
2910 static struct omap_hwmod omap34xx_sr1_hwmod
= {
2911 .name
= "sr1_hwmod",
2912 .class = &omap34xx_smartreflex_hwmod_class
,
2913 .main_clk
= "sr1_fck",
2918 .module_bit
= OMAP3430_EN_SR1_SHIFT
,
2919 .module_offs
= WKUP_MOD
,
2921 .idlest_idle_bit
= OMAP3430_EN_SR1_SHIFT
,
2924 .slaves
= omap3_sr1_slaves
,
2925 .slaves_cnt
= ARRAY_SIZE(omap3_sr1_slaves
),
2926 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2
|
2927 CHIP_IS_OMAP3430ES3_0
|
2928 CHIP_IS_OMAP3430ES3_1
),
2929 .flags
= HWMOD_SET_DEFAULT_CLOCKACT
,
2932 static struct omap_hwmod omap36xx_sr1_hwmod
= {
2933 .name
= "sr1_hwmod",
2934 .class = &omap36xx_smartreflex_hwmod_class
,
2935 .main_clk
= "sr1_fck",
2940 .module_bit
= OMAP3430_EN_SR1_SHIFT
,
2941 .module_offs
= WKUP_MOD
,
2943 .idlest_idle_bit
= OMAP3430_EN_SR1_SHIFT
,
2946 .slaves
= omap3_sr1_slaves
,
2947 .slaves_cnt
= ARRAY_SIZE(omap3_sr1_slaves
),
2948 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1
),
2952 static struct omap_hwmod_ocp_if
*omap3_sr2_slaves
[] = {
2953 &omap3_l4_core__sr2
,
2956 static struct omap_hwmod omap34xx_sr2_hwmod
= {
2957 .name
= "sr2_hwmod",
2958 .class = &omap34xx_smartreflex_hwmod_class
,
2959 .main_clk
= "sr2_fck",
2964 .module_bit
= OMAP3430_EN_SR2_SHIFT
,
2965 .module_offs
= WKUP_MOD
,
2967 .idlest_idle_bit
= OMAP3430_EN_SR2_SHIFT
,
2970 .slaves
= omap3_sr2_slaves
,
2971 .slaves_cnt
= ARRAY_SIZE(omap3_sr2_slaves
),
2972 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2
|
2973 CHIP_IS_OMAP3430ES3_0
|
2974 CHIP_IS_OMAP3430ES3_1
),
2975 .flags
= HWMOD_SET_DEFAULT_CLOCKACT
,
2978 static struct omap_hwmod omap36xx_sr2_hwmod
= {
2979 .name
= "sr2_hwmod",
2980 .class = &omap36xx_smartreflex_hwmod_class
,
2981 .main_clk
= "sr2_fck",
2986 .module_bit
= OMAP3430_EN_SR2_SHIFT
,
2987 .module_offs
= WKUP_MOD
,
2989 .idlest_idle_bit
= OMAP3430_EN_SR2_SHIFT
,
2992 .slaves
= omap3_sr2_slaves
,
2993 .slaves_cnt
= ARRAY_SIZE(omap3_sr2_slaves
),
2994 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1
),
2999 * mailbox module allowing communication between the on-chip processors
3000 * using a queued mailbox-interrupt mechanism.
3003 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc
= {
3007 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
3008 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
),
3009 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
3010 .sysc_fields
= &omap_hwmod_sysc_type1
,
3013 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class
= {
3015 .sysc
= &omap3xxx_mailbox_sysc
,
3018 static struct omap_hwmod omap3xxx_mailbox_hwmod
;
3019 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs
[] = {
3023 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs
[] = {
3025 .pa_start
= 0x48094000,
3026 .pa_end
= 0x480941ff,
3027 .flags
= ADDR_TYPE_RT
,
3031 /* l4_core -> mailbox */
3032 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox
= {
3033 .master
= &omap3xxx_l4_core_hwmod
,
3034 .slave
= &omap3xxx_mailbox_hwmod
,
3035 .addr
= omap3xxx_mailbox_addrs
,
3036 .addr_cnt
= ARRAY_SIZE(omap3xxx_mailbox_addrs
),
3037 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3040 /* mailbox slave ports */
3041 static struct omap_hwmod_ocp_if
*omap3xxx_mailbox_slaves
[] = {
3042 &omap3xxx_l4_core__mailbox
,
3045 static struct omap_hwmod omap3xxx_mailbox_hwmod
= {
3047 .class = &omap3xxx_mailbox_hwmod_class
,
3048 .mpu_irqs
= omap3xxx_mailbox_irqs
,
3049 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_mailbox_irqs
),
3050 .main_clk
= "mailboxes_ick",
3054 .module_bit
= OMAP3430_EN_MAILBOXES_SHIFT
,
3055 .module_offs
= CORE_MOD
,
3057 .idlest_idle_bit
= OMAP3430_ST_MAILBOXES_SHIFT
,
3060 .slaves
= omap3xxx_mailbox_slaves
,
3061 .slaves_cnt
= ARRAY_SIZE(omap3xxx_mailbox_slaves
),
3062 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
3065 /* l4 core -> mcspi1 interface */
3066 static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space
[] = {
3068 .pa_start
= 0x48098000,
3069 .pa_end
= 0x480980ff,
3070 .flags
= ADDR_TYPE_RT
,
3074 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1
= {
3075 .master
= &omap3xxx_l4_core_hwmod
,
3076 .slave
= &omap34xx_mcspi1
,
3077 .clk
= "mcspi1_ick",
3078 .addr
= omap34xx_mcspi1_addr_space
,
3079 .addr_cnt
= ARRAY_SIZE(omap34xx_mcspi1_addr_space
),
3080 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3083 /* l4 core -> mcspi2 interface */
3084 static struct omap_hwmod_addr_space omap34xx_mcspi2_addr_space
[] = {
3086 .pa_start
= 0x4809a000,
3087 .pa_end
= 0x4809a0ff,
3088 .flags
= ADDR_TYPE_RT
,
3092 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2
= {
3093 .master
= &omap3xxx_l4_core_hwmod
,
3094 .slave
= &omap34xx_mcspi2
,
3095 .clk
= "mcspi2_ick",
3096 .addr
= omap34xx_mcspi2_addr_space
,
3097 .addr_cnt
= ARRAY_SIZE(omap34xx_mcspi2_addr_space
),
3098 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3101 /* l4 core -> mcspi3 interface */
3102 static struct omap_hwmod_addr_space omap34xx_mcspi3_addr_space
[] = {
3104 .pa_start
= 0x480b8000,
3105 .pa_end
= 0x480b80ff,
3106 .flags
= ADDR_TYPE_RT
,
3110 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3
= {
3111 .master
= &omap3xxx_l4_core_hwmod
,
3112 .slave
= &omap34xx_mcspi3
,
3113 .clk
= "mcspi3_ick",
3114 .addr
= omap34xx_mcspi3_addr_space
,
3115 .addr_cnt
= ARRAY_SIZE(omap34xx_mcspi3_addr_space
),
3116 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3119 /* l4 core -> mcspi4 interface */
3120 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space
[] = {
3122 .pa_start
= 0x480ba000,
3123 .pa_end
= 0x480ba0ff,
3124 .flags
= ADDR_TYPE_RT
,
3128 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4
= {
3129 .master
= &omap3xxx_l4_core_hwmod
,
3130 .slave
= &omap34xx_mcspi4
,
3131 .clk
= "mcspi4_ick",
3132 .addr
= omap34xx_mcspi4_addr_space
,
3133 .addr_cnt
= ARRAY_SIZE(omap34xx_mcspi4_addr_space
),
3134 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3139 * multichannel serial port interface (mcspi) / master/slave synchronous serial
3143 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc
= {
3145 .sysc_offs
= 0x0010,
3146 .syss_offs
= 0x0014,
3147 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
3148 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
3149 SYSC_HAS_AUTOIDLE
| SYSS_HAS_RESET_STATUS
),
3150 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
3151 .sysc_fields
= &omap_hwmod_sysc_type1
,
3154 static struct omap_hwmod_class omap34xx_mcspi_class
= {
3156 .sysc
= &omap34xx_mcspi_sysc
,
3157 .rev
= OMAP3_MCSPI_REV
,
3161 static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs
[] = {
3162 { .name
= "irq", .irq
= 65 },
3165 static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs
[] = {
3166 { .name
= "tx0", .dma_req
= 35 },
3167 { .name
= "rx0", .dma_req
= 36 },
3168 { .name
= "tx1", .dma_req
= 37 },
3169 { .name
= "rx1", .dma_req
= 38 },
3170 { .name
= "tx2", .dma_req
= 39 },
3171 { .name
= "rx2", .dma_req
= 40 },
3172 { .name
= "tx3", .dma_req
= 41 },
3173 { .name
= "rx3", .dma_req
= 42 },
3176 static struct omap_hwmod_ocp_if
*omap34xx_mcspi1_slaves
[] = {
3177 &omap34xx_l4_core__mcspi1
,
3180 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr
= {
3181 .num_chipselect
= 4,
3184 static struct omap_hwmod omap34xx_mcspi1
= {
3186 .mpu_irqs
= omap34xx_mcspi1_mpu_irqs
,
3187 .mpu_irqs_cnt
= ARRAY_SIZE(omap34xx_mcspi1_mpu_irqs
),
3188 .sdma_reqs
= omap34xx_mcspi1_sdma_reqs
,
3189 .sdma_reqs_cnt
= ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs
),
3190 .main_clk
= "mcspi1_fck",
3193 .module_offs
= CORE_MOD
,
3195 .module_bit
= OMAP3430_EN_MCSPI1_SHIFT
,
3197 .idlest_idle_bit
= OMAP3430_ST_MCSPI1_SHIFT
,
3200 .slaves
= omap34xx_mcspi1_slaves
,
3201 .slaves_cnt
= ARRAY_SIZE(omap34xx_mcspi1_slaves
),
3202 .class = &omap34xx_mcspi_class
,
3203 .dev_attr
= &omap_mcspi1_dev_attr
,
3204 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
3208 static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs
[] = {
3209 { .name
= "irq", .irq
= 66 },
3212 static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs
[] = {
3213 { .name
= "tx0", .dma_req
= 43 },
3214 { .name
= "rx0", .dma_req
= 44 },
3215 { .name
= "tx1", .dma_req
= 45 },
3216 { .name
= "rx1", .dma_req
= 46 },
3219 static struct omap_hwmod_ocp_if
*omap34xx_mcspi2_slaves
[] = {
3220 &omap34xx_l4_core__mcspi2
,
3223 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr
= {
3224 .num_chipselect
= 2,
3227 static struct omap_hwmod omap34xx_mcspi2
= {
3229 .mpu_irqs
= omap34xx_mcspi2_mpu_irqs
,
3230 .mpu_irqs_cnt
= ARRAY_SIZE(omap34xx_mcspi2_mpu_irqs
),
3231 .sdma_reqs
= omap34xx_mcspi2_sdma_reqs
,
3232 .sdma_reqs_cnt
= ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs
),
3233 .main_clk
= "mcspi2_fck",
3236 .module_offs
= CORE_MOD
,
3238 .module_bit
= OMAP3430_EN_MCSPI2_SHIFT
,
3240 .idlest_idle_bit
= OMAP3430_ST_MCSPI2_SHIFT
,
3243 .slaves
= omap34xx_mcspi2_slaves
,
3244 .slaves_cnt
= ARRAY_SIZE(omap34xx_mcspi2_slaves
),
3245 .class = &omap34xx_mcspi_class
,
3246 .dev_attr
= &omap_mcspi2_dev_attr
,
3247 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
3251 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs
[] = {
3252 { .name
= "irq", .irq
= 91 }, /* 91 */
3255 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs
[] = {
3256 { .name
= "tx0", .dma_req
= 15 },
3257 { .name
= "rx0", .dma_req
= 16 },
3258 { .name
= "tx1", .dma_req
= 23 },
3259 { .name
= "rx1", .dma_req
= 24 },
3262 static struct omap_hwmod_ocp_if
*omap34xx_mcspi3_slaves
[] = {
3263 &omap34xx_l4_core__mcspi3
,
3266 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr
= {
3267 .num_chipselect
= 2,
3270 static struct omap_hwmod omap34xx_mcspi3
= {
3272 .mpu_irqs
= omap34xx_mcspi3_mpu_irqs
,
3273 .mpu_irqs_cnt
= ARRAY_SIZE(omap34xx_mcspi3_mpu_irqs
),
3274 .sdma_reqs
= omap34xx_mcspi3_sdma_reqs
,
3275 .sdma_reqs_cnt
= ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs
),
3276 .main_clk
= "mcspi3_fck",
3279 .module_offs
= CORE_MOD
,
3281 .module_bit
= OMAP3430_EN_MCSPI3_SHIFT
,
3283 .idlest_idle_bit
= OMAP3430_ST_MCSPI3_SHIFT
,
3286 .slaves
= omap34xx_mcspi3_slaves
,
3287 .slaves_cnt
= ARRAY_SIZE(omap34xx_mcspi3_slaves
),
3288 .class = &omap34xx_mcspi_class
,
3289 .dev_attr
= &omap_mcspi3_dev_attr
,
3290 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
3294 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs
[] = {
3295 { .name
= "irq", .irq
= INT_34XX_SPI4_IRQ
}, /* 48 */
3298 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs
[] = {
3299 { .name
= "tx0", .dma_req
= 70 }, /* DMA_SPI4_TX0 */
3300 { .name
= "rx0", .dma_req
= 71 }, /* DMA_SPI4_RX0 */
3303 static struct omap_hwmod_ocp_if
*omap34xx_mcspi4_slaves
[] = {
3304 &omap34xx_l4_core__mcspi4
,
3307 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr
= {
3308 .num_chipselect
= 1,
3311 static struct omap_hwmod omap34xx_mcspi4
= {
3313 .mpu_irqs
= omap34xx_mcspi4_mpu_irqs
,
3314 .mpu_irqs_cnt
= ARRAY_SIZE(omap34xx_mcspi4_mpu_irqs
),
3315 .sdma_reqs
= omap34xx_mcspi4_sdma_reqs
,
3316 .sdma_reqs_cnt
= ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs
),
3317 .main_clk
= "mcspi4_fck",
3320 .module_offs
= CORE_MOD
,
3322 .module_bit
= OMAP3430_EN_MCSPI4_SHIFT
,
3324 .idlest_idle_bit
= OMAP3430_ST_MCSPI4_SHIFT
,
3327 .slaves
= omap34xx_mcspi4_slaves
,
3328 .slaves_cnt
= ARRAY_SIZE(omap34xx_mcspi4_slaves
),
3329 .class = &omap34xx_mcspi_class
,
3330 .dev_attr
= &omap_mcspi4_dev_attr
,
3331 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
3337 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc
= {
3339 .sysc_offs
= 0x0404,
3340 .syss_offs
= 0x0408,
3341 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_MIDLEMODE
|
3342 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
3344 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3345 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
3346 .sysc_fields
= &omap_hwmod_sysc_type1
,
3349 static struct omap_hwmod_class usbotg_class
= {
3351 .sysc
= &omap3xxx_usbhsotg_sysc
,
3354 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs
[] = {
3356 { .name
= "mc", .irq
= 92 },
3357 { .name
= "dma", .irq
= 93 },
3360 static struct omap_hwmod omap3xxx_usbhsotg_hwmod
= {
3361 .name
= "usb_otg_hs",
3362 .mpu_irqs
= omap3xxx_usbhsotg_mpu_irqs
,
3363 .mpu_irqs_cnt
= ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs
),
3364 .main_clk
= "hsotgusb_ick",
3368 .module_bit
= OMAP3430_EN_HSOTGUSB_SHIFT
,
3369 .module_offs
= CORE_MOD
,
3371 .idlest_idle_bit
= OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT
,
3372 .idlest_stdby_bit
= OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
3375 .masters
= omap3xxx_usbhsotg_masters
,
3376 .masters_cnt
= ARRAY_SIZE(omap3xxx_usbhsotg_masters
),
3377 .slaves
= omap3xxx_usbhsotg_slaves
,
3378 .slaves_cnt
= ARRAY_SIZE(omap3xxx_usbhsotg_slaves
),
3379 .class = &usbotg_class
,
3382 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
3383 * broken when autoidle is enabled
3384 * workaround is to disable the autoidle bit at module level.
3386 .flags
= HWMOD_NO_OCP_AUTOIDLE
| HWMOD_SWSUP_SIDLE
3387 | HWMOD_SWSUP_MSTANDBY
,
3388 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
)
3392 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs
[] = {
3394 { .name
= "mc", .irq
= 71 },
3397 static struct omap_hwmod_class am35xx_usbotg_class
= {
3398 .name
= "am35xx_usbotg",
3402 static struct omap_hwmod am35xx_usbhsotg_hwmod
= {
3403 .name
= "am35x_otg_hs",
3404 .mpu_irqs
= am35xx_usbhsotg_mpu_irqs
,
3405 .mpu_irqs_cnt
= ARRAY_SIZE(am35xx_usbhsotg_mpu_irqs
),
3411 .masters
= am35xx_usbhsotg_masters
,
3412 .masters_cnt
= ARRAY_SIZE(am35xx_usbhsotg_masters
),
3413 .slaves
= am35xx_usbhsotg_slaves
,
3414 .slaves_cnt
= ARRAY_SIZE(am35xx_usbhsotg_slaves
),
3415 .class = &am35xx_usbotg_class
,
3416 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1
)
3419 /* MMC/SD/SDIO common */
3421 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc
= {
3425 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
3426 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
3427 SYSC_HAS_AUTOIDLE
| SYSS_HAS_RESET_STATUS
),
3428 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
3429 .sysc_fields
= &omap_hwmod_sysc_type1
,
3432 static struct omap_hwmod_class omap34xx_mmc_class
= {
3434 .sysc
= &omap34xx_mmc_sysc
,
3439 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs
[] = {
3443 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs
[] = {
3444 { .name
= "tx", .dma_req
= 61, },
3445 { .name
= "rx", .dma_req
= 62, },
3448 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks
[] = {
3449 { .role
= "dbck", .clk
= "omap_32k_fck", },
3452 static struct omap_hwmod_ocp_if
*omap3xxx_mmc1_slaves
[] = {
3453 &omap3xxx_l4_core__mmc1
,
3456 static struct omap_mmc_dev_attr mmc1_dev_attr
= {
3457 .flags
= OMAP_HSMMC_SUPPORTS_DUAL_VOLT
,
3460 static struct omap_hwmod omap3xxx_mmc1_hwmod
= {
3462 .mpu_irqs
= omap34xx_mmc1_mpu_irqs
,
3463 .mpu_irqs_cnt
= ARRAY_SIZE(omap34xx_mmc1_mpu_irqs
),
3464 .sdma_reqs
= omap34xx_mmc1_sdma_reqs
,
3465 .sdma_reqs_cnt
= ARRAY_SIZE(omap34xx_mmc1_sdma_reqs
),
3466 .opt_clks
= omap34xx_mmc1_opt_clks
,
3467 .opt_clks_cnt
= ARRAY_SIZE(omap34xx_mmc1_opt_clks
),
3468 .main_clk
= "mmchs1_fck",
3471 .module_offs
= CORE_MOD
,
3473 .module_bit
= OMAP3430_EN_MMC1_SHIFT
,
3475 .idlest_idle_bit
= OMAP3430_ST_MMC1_SHIFT
,
3478 .dev_attr
= &mmc1_dev_attr
,
3479 .slaves
= omap3xxx_mmc1_slaves
,
3480 .slaves_cnt
= ARRAY_SIZE(omap3xxx_mmc1_slaves
),
3481 .class = &omap34xx_mmc_class
,
3482 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
3487 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs
[] = {
3488 { .irq
= INT_24XX_MMC2_IRQ
, },
3491 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs
[] = {
3492 { .name
= "tx", .dma_req
= 47, },
3493 { .name
= "rx", .dma_req
= 48, },
3496 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks
[] = {
3497 { .role
= "dbck", .clk
= "omap_32k_fck", },
3500 static struct omap_hwmod_ocp_if
*omap3xxx_mmc2_slaves
[] = {
3501 &omap3xxx_l4_core__mmc2
,
3504 static struct omap_hwmod omap3xxx_mmc2_hwmod
= {
3506 .mpu_irqs
= omap34xx_mmc2_mpu_irqs
,
3507 .mpu_irqs_cnt
= ARRAY_SIZE(omap34xx_mmc2_mpu_irqs
),
3508 .sdma_reqs
= omap34xx_mmc2_sdma_reqs
,
3509 .sdma_reqs_cnt
= ARRAY_SIZE(omap34xx_mmc2_sdma_reqs
),
3510 .opt_clks
= omap34xx_mmc2_opt_clks
,
3511 .opt_clks_cnt
= ARRAY_SIZE(omap34xx_mmc2_opt_clks
),
3512 .main_clk
= "mmchs2_fck",
3515 .module_offs
= CORE_MOD
,
3517 .module_bit
= OMAP3430_EN_MMC2_SHIFT
,
3519 .idlest_idle_bit
= OMAP3430_ST_MMC2_SHIFT
,
3522 .slaves
= omap3xxx_mmc2_slaves
,
3523 .slaves_cnt
= ARRAY_SIZE(omap3xxx_mmc2_slaves
),
3524 .class = &omap34xx_mmc_class
,
3525 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
3530 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs
[] = {
3534 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs
[] = {
3535 { .name
= "tx", .dma_req
= 77, },
3536 { .name
= "rx", .dma_req
= 78, },
3539 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks
[] = {
3540 { .role
= "dbck", .clk
= "omap_32k_fck", },
3543 static struct omap_hwmod_ocp_if
*omap3xxx_mmc3_slaves
[] = {
3544 &omap3xxx_l4_core__mmc3
,
3547 static struct omap_hwmod omap3xxx_mmc3_hwmod
= {
3549 .mpu_irqs
= omap34xx_mmc3_mpu_irqs
,
3550 .mpu_irqs_cnt
= ARRAY_SIZE(omap34xx_mmc3_mpu_irqs
),
3551 .sdma_reqs
= omap34xx_mmc3_sdma_reqs
,
3552 .sdma_reqs_cnt
= ARRAY_SIZE(omap34xx_mmc3_sdma_reqs
),
3553 .opt_clks
= omap34xx_mmc3_opt_clks
,
3554 .opt_clks_cnt
= ARRAY_SIZE(omap34xx_mmc3_opt_clks
),
3555 .main_clk
= "mmchs3_fck",
3559 .module_bit
= OMAP3430_EN_MMC3_SHIFT
,
3561 .idlest_idle_bit
= OMAP3430_ST_MMC3_SHIFT
,
3564 .slaves
= omap3xxx_mmc3_slaves
,
3565 .slaves_cnt
= ARRAY_SIZE(omap3xxx_mmc3_slaves
),
3566 .class = &omap34xx_mmc_class
,
3567 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP3430
),
3570 static __initdata
struct omap_hwmod
*omap3xxx_hwmods
[] = {
3571 &omap3xxx_l3_main_hwmod
,
3572 &omap3xxx_l4_core_hwmod
,
3573 &omap3xxx_l4_per_hwmod
,
3574 &omap3xxx_l4_wkup_hwmod
,
3575 &omap3xxx_mmc1_hwmod
,
3576 &omap3xxx_mmc2_hwmod
,
3577 &omap3xxx_mmc3_hwmod
,
3578 &omap3xxx_mpu_hwmod
,
3579 &omap3xxx_iva_hwmod
,
3581 &omap3xxx_timer1_hwmod
,
3582 &omap3xxx_timer2_hwmod
,
3583 &omap3xxx_timer3_hwmod
,
3584 &omap3xxx_timer4_hwmod
,
3585 &omap3xxx_timer5_hwmod
,
3586 &omap3xxx_timer6_hwmod
,
3587 &omap3xxx_timer7_hwmod
,
3588 &omap3xxx_timer8_hwmod
,
3589 &omap3xxx_timer9_hwmod
,
3590 &omap3xxx_timer10_hwmod
,
3591 &omap3xxx_timer11_hwmod
,
3592 &omap3xxx_timer12_hwmod
,
3594 &omap3xxx_wd_timer2_hwmod
,
3595 &omap3xxx_uart1_hwmod
,
3596 &omap3xxx_uart2_hwmod
,
3597 &omap3xxx_uart3_hwmod
,
3598 &omap3xxx_uart4_hwmod
,
3600 &omap3430es1_dss_core_hwmod
,
3601 &omap3xxx_dss_core_hwmod
,
3602 &omap3xxx_dss_dispc_hwmod
,
3603 &omap3xxx_dss_dsi1_hwmod
,
3604 &omap3xxx_dss_rfbi_hwmod
,
3605 &omap3xxx_dss_venc_hwmod
,
3608 &omap3xxx_i2c1_hwmod
,
3609 &omap3xxx_i2c2_hwmod
,
3610 &omap3xxx_i2c3_hwmod
,
3611 &omap34xx_sr1_hwmod
,
3612 &omap34xx_sr2_hwmod
,
3613 &omap36xx_sr1_hwmod
,
3614 &omap36xx_sr2_hwmod
,
3618 &omap3xxx_gpio1_hwmod
,
3619 &omap3xxx_gpio2_hwmod
,
3620 &omap3xxx_gpio3_hwmod
,
3621 &omap3xxx_gpio4_hwmod
,
3622 &omap3xxx_gpio5_hwmod
,
3623 &omap3xxx_gpio6_hwmod
,
3625 /* dma_system class*/
3626 &omap3xxx_dma_system_hwmod
,
3629 &omap3xxx_mcbsp1_hwmod
,
3630 &omap3xxx_mcbsp2_hwmod
,
3631 &omap3xxx_mcbsp3_hwmod
,
3632 &omap3xxx_mcbsp4_hwmod
,
3633 &omap3xxx_mcbsp5_hwmod
,
3634 &omap3xxx_mcbsp2_sidetone_hwmod
,
3635 &omap3xxx_mcbsp3_sidetone_hwmod
,
3638 &omap3xxx_mailbox_hwmod
,
3647 &omap3xxx_usbhsotg_hwmod
,
3649 /* usbotg for am35x */
3650 &am35xx_usbhsotg_hwmod
,
3655 int __init
omap3xxx_hwmod_init(void)
3657 return omap_hwmod_register(omap3xxx_hwmods
);