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OMAP2/3: VENC hwmod: add OCPIF_SWSUP_IDLE flag to interface
[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_3xxx_data.c
1 /*
2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
3 *
4 * Copyright (C) 2009-2010 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * The data in this file should be completely autogeneratable from
12 * the TI hardware database or other technical documentation.
13 *
14 * XXX these should be marked initdata for multi-OMAP kernels
15 */
16 #include <plat/omap_hwmod.h>
17 #include <mach/irqs.h>
18 #include <plat/cpu.h>
19 #include <plat/dma.h>
20 #include <plat/serial.h>
21 #include <plat/l3_3xxx.h>
22 #include <plat/l4_3xxx.h>
23 #include <plat/i2c.h>
24 #include <plat/gpio.h>
25 #include <plat/mmc.h>
26 #include <plat/smartreflex.h>
27 #include <plat/mcbsp.h>
28 #include <plat/mcspi.h>
29 #include <plat/dmtimer.h>
30
31 #include "omap_hwmod_common_data.h"
32
33 #include "prm-regbits-34xx.h"
34 #include "cm-regbits-34xx.h"
35 #include "wd_timer.h"
36 #include <mach/am35xx.h>
37
38 /*
39 * OMAP3xxx hardware module integration data
40 *
41 * ALl of the data in this section should be autogeneratable from the
42 * TI hardware database or other technical documentation. Data that
43 * is driver-specific or driver-kernel integration-specific belongs
44 * elsewhere.
45 */
46
47 static struct omap_hwmod omap3xxx_mpu_hwmod;
48 static struct omap_hwmod omap3xxx_iva_hwmod;
49 static struct omap_hwmod omap3xxx_l3_main_hwmod;
50 static struct omap_hwmod omap3xxx_l4_core_hwmod;
51 static struct omap_hwmod omap3xxx_l4_per_hwmod;
52 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
53 static struct omap_hwmod omap3430es1_dss_core_hwmod;
54 static struct omap_hwmod omap3xxx_dss_core_hwmod;
55 static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
56 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
57 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
58 static struct omap_hwmod omap3xxx_dss_venc_hwmod;
59 static struct omap_hwmod omap3xxx_i2c1_hwmod;
60 static struct omap_hwmod omap3xxx_i2c2_hwmod;
61 static struct omap_hwmod omap3xxx_i2c3_hwmod;
62 static struct omap_hwmod omap3xxx_gpio1_hwmod;
63 static struct omap_hwmod omap3xxx_gpio2_hwmod;
64 static struct omap_hwmod omap3xxx_gpio3_hwmod;
65 static struct omap_hwmod omap3xxx_gpio4_hwmod;
66 static struct omap_hwmod omap3xxx_gpio5_hwmod;
67 static struct omap_hwmod omap3xxx_gpio6_hwmod;
68 static struct omap_hwmod omap34xx_sr1_hwmod;
69 static struct omap_hwmod omap34xx_sr2_hwmod;
70 static struct omap_hwmod omap34xx_mcspi1;
71 static struct omap_hwmod omap34xx_mcspi2;
72 static struct omap_hwmod omap34xx_mcspi3;
73 static struct omap_hwmod omap34xx_mcspi4;
74 static struct omap_hwmod omap3xxx_mmc1_hwmod;
75 static struct omap_hwmod omap3xxx_mmc2_hwmod;
76 static struct omap_hwmod omap3xxx_mmc3_hwmod;
77 static struct omap_hwmod am35xx_usbhsotg_hwmod;
78
79 static struct omap_hwmod omap3xxx_dma_system_hwmod;
80
81 static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
82 static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
83 static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
84 static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
85 static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
86 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
87 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
88
89 /* L3 -> L4_CORE interface */
90 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
91 .master = &omap3xxx_l3_main_hwmod,
92 .slave = &omap3xxx_l4_core_hwmod,
93 .user = OCP_USER_MPU | OCP_USER_SDMA,
94 };
95
96 /* L3 -> L4_PER interface */
97 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
98 .master = &omap3xxx_l3_main_hwmod,
99 .slave = &omap3xxx_l4_per_hwmod,
100 .user = OCP_USER_MPU | OCP_USER_SDMA,
101 };
102
103 /* MPU -> L3 interface */
104 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
105 .master = &omap3xxx_mpu_hwmod,
106 .slave = &omap3xxx_l3_main_hwmod,
107 .user = OCP_USER_MPU,
108 };
109
110 /* Slave interfaces on the L3 interconnect */
111 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
112 &omap3xxx_mpu__l3_main,
113 };
114
115 /* DSS -> l3 */
116 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
117 .master = &omap3xxx_dss_core_hwmod,
118 .slave = &omap3xxx_l3_main_hwmod,
119 .fw = {
120 .omap2 = {
121 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
122 .flags = OMAP_FIREWALL_L3,
123 }
124 },
125 .user = OCP_USER_MPU | OCP_USER_SDMA,
126 };
127
128 /* Master interfaces on the L3 interconnect */
129 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
130 &omap3xxx_l3_main__l4_core,
131 &omap3xxx_l3_main__l4_per,
132 };
133
134 /* L3 */
135 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
136 .name = "l3_main",
137 .class = &l3_hwmod_class,
138 .masters = omap3xxx_l3_main_masters,
139 .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
140 .slaves = omap3xxx_l3_main_slaves,
141 .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves),
142 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
143 .flags = HWMOD_NO_IDLEST,
144 };
145
146 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
147 static struct omap_hwmod omap3xxx_uart1_hwmod;
148 static struct omap_hwmod omap3xxx_uart2_hwmod;
149 static struct omap_hwmod omap3xxx_uart3_hwmod;
150 static struct omap_hwmod omap3xxx_uart4_hwmod;
151 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
152
153 /* l3_core -> usbhsotg interface */
154 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
155 .master = &omap3xxx_usbhsotg_hwmod,
156 .slave = &omap3xxx_l3_main_hwmod,
157 .clk = "core_l3_ick",
158 .user = OCP_USER_MPU,
159 };
160
161 /* l3_core -> am35xx_usbhsotg interface */
162 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
163 .master = &am35xx_usbhsotg_hwmod,
164 .slave = &omap3xxx_l3_main_hwmod,
165 .clk = "core_l3_ick",
166 .user = OCP_USER_MPU,
167 };
168 /* L4_CORE -> L4_WKUP interface */
169 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
170 .master = &omap3xxx_l4_core_hwmod,
171 .slave = &omap3xxx_l4_wkup_hwmod,
172 .user = OCP_USER_MPU | OCP_USER_SDMA,
173 };
174
175 /* L4 CORE -> MMC1 interface */
176 static struct omap_hwmod_addr_space omap3xxx_mmc1_addr_space[] = {
177 {
178 .pa_start = 0x4809c000,
179 .pa_end = 0x4809c1ff,
180 .flags = ADDR_TYPE_RT,
181 },
182 };
183
184 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
185 .master = &omap3xxx_l4_core_hwmod,
186 .slave = &omap3xxx_mmc1_hwmod,
187 .clk = "mmchs1_ick",
188 .addr = omap3xxx_mmc1_addr_space,
189 .addr_cnt = ARRAY_SIZE(omap3xxx_mmc1_addr_space),
190 .user = OCP_USER_MPU | OCP_USER_SDMA,
191 .flags = OMAP_FIREWALL_L4
192 };
193
194 /* L4 CORE -> MMC2 interface */
195 static struct omap_hwmod_addr_space omap3xxx_mmc2_addr_space[] = {
196 {
197 .pa_start = 0x480b4000,
198 .pa_end = 0x480b41ff,
199 .flags = ADDR_TYPE_RT,
200 },
201 };
202
203 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
204 .master = &omap3xxx_l4_core_hwmod,
205 .slave = &omap3xxx_mmc2_hwmod,
206 .clk = "mmchs2_ick",
207 .addr = omap3xxx_mmc2_addr_space,
208 .addr_cnt = ARRAY_SIZE(omap3xxx_mmc2_addr_space),
209 .user = OCP_USER_MPU | OCP_USER_SDMA,
210 .flags = OMAP_FIREWALL_L4
211 };
212
213 /* L4 CORE -> MMC3 interface */
214 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
215 {
216 .pa_start = 0x480ad000,
217 .pa_end = 0x480ad1ff,
218 .flags = ADDR_TYPE_RT,
219 },
220 };
221
222 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
223 .master = &omap3xxx_l4_core_hwmod,
224 .slave = &omap3xxx_mmc3_hwmod,
225 .clk = "mmchs3_ick",
226 .addr = omap3xxx_mmc3_addr_space,
227 .addr_cnt = ARRAY_SIZE(omap3xxx_mmc3_addr_space),
228 .user = OCP_USER_MPU | OCP_USER_SDMA,
229 .flags = OMAP_FIREWALL_L4
230 };
231
232 /* L4 CORE -> UART1 interface */
233 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
234 {
235 .pa_start = OMAP3_UART1_BASE,
236 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
237 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
238 },
239 };
240
241 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
242 .master = &omap3xxx_l4_core_hwmod,
243 .slave = &omap3xxx_uart1_hwmod,
244 .clk = "uart1_ick",
245 .addr = omap3xxx_uart1_addr_space,
246 .addr_cnt = ARRAY_SIZE(omap3xxx_uart1_addr_space),
247 .user = OCP_USER_MPU | OCP_USER_SDMA,
248 };
249
250 /* L4 CORE -> UART2 interface */
251 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
252 {
253 .pa_start = OMAP3_UART2_BASE,
254 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
255 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
256 },
257 };
258
259 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
260 .master = &omap3xxx_l4_core_hwmod,
261 .slave = &omap3xxx_uart2_hwmod,
262 .clk = "uart2_ick",
263 .addr = omap3xxx_uart2_addr_space,
264 .addr_cnt = ARRAY_SIZE(omap3xxx_uart2_addr_space),
265 .user = OCP_USER_MPU | OCP_USER_SDMA,
266 };
267
268 /* L4 PER -> UART3 interface */
269 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
270 {
271 .pa_start = OMAP3_UART3_BASE,
272 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
273 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
274 },
275 };
276
277 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
278 .master = &omap3xxx_l4_per_hwmod,
279 .slave = &omap3xxx_uart3_hwmod,
280 .clk = "uart3_ick",
281 .addr = omap3xxx_uart3_addr_space,
282 .addr_cnt = ARRAY_SIZE(omap3xxx_uart3_addr_space),
283 .user = OCP_USER_MPU | OCP_USER_SDMA,
284 };
285
286 /* L4 PER -> UART4 interface */
287 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
288 {
289 .pa_start = OMAP3_UART4_BASE,
290 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
291 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
292 },
293 };
294
295 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
296 .master = &omap3xxx_l4_per_hwmod,
297 .slave = &omap3xxx_uart4_hwmod,
298 .clk = "uart4_ick",
299 .addr = omap3xxx_uart4_addr_space,
300 .addr_cnt = ARRAY_SIZE(omap3xxx_uart4_addr_space),
301 .user = OCP_USER_MPU | OCP_USER_SDMA,
302 };
303
304 /* I2C IP block address space length (in bytes) */
305 #define OMAP2_I2C_AS_LEN 128
306
307 /* L4 CORE -> I2C1 interface */
308 static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = {
309 {
310 .pa_start = 0x48070000,
311 .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
312 .flags = ADDR_TYPE_RT,
313 },
314 };
315
316 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
317 .master = &omap3xxx_l4_core_hwmod,
318 .slave = &omap3xxx_i2c1_hwmod,
319 .clk = "i2c1_ick",
320 .addr = omap3xxx_i2c1_addr_space,
321 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c1_addr_space),
322 .fw = {
323 .omap2 = {
324 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
325 .l4_prot_group = 7,
326 .flags = OMAP_FIREWALL_L4,
327 }
328 },
329 .user = OCP_USER_MPU | OCP_USER_SDMA,
330 };
331
332 /* L4 CORE -> I2C2 interface */
333 static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = {
334 {
335 .pa_start = 0x48072000,
336 .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
337 .flags = ADDR_TYPE_RT,
338 },
339 };
340
341 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
342 .master = &omap3xxx_l4_core_hwmod,
343 .slave = &omap3xxx_i2c2_hwmod,
344 .clk = "i2c2_ick",
345 .addr = omap3xxx_i2c2_addr_space,
346 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c2_addr_space),
347 .fw = {
348 .omap2 = {
349 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
350 .l4_prot_group = 7,
351 .flags = OMAP_FIREWALL_L4,
352 }
353 },
354 .user = OCP_USER_MPU | OCP_USER_SDMA,
355 };
356
357 /* L4 CORE -> I2C3 interface */
358 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
359 {
360 .pa_start = 0x48060000,
361 .pa_end = 0x48060000 + OMAP2_I2C_AS_LEN - 1,
362 .flags = ADDR_TYPE_RT,
363 },
364 };
365
366 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
367 .master = &omap3xxx_l4_core_hwmod,
368 .slave = &omap3xxx_i2c3_hwmod,
369 .clk = "i2c3_ick",
370 .addr = omap3xxx_i2c3_addr_space,
371 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c3_addr_space),
372 .fw = {
373 .omap2 = {
374 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
375 .l4_prot_group = 7,
376 .flags = OMAP_FIREWALL_L4,
377 }
378 },
379 .user = OCP_USER_MPU | OCP_USER_SDMA,
380 };
381
382 /* L4 CORE -> SR1 interface */
383 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
384 {
385 .pa_start = OMAP34XX_SR1_BASE,
386 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
387 .flags = ADDR_TYPE_RT,
388 },
389 };
390
391 static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
392 .master = &omap3xxx_l4_core_hwmod,
393 .slave = &omap34xx_sr1_hwmod,
394 .clk = "sr_l4_ick",
395 .addr = omap3_sr1_addr_space,
396 .addr_cnt = ARRAY_SIZE(omap3_sr1_addr_space),
397 .user = OCP_USER_MPU,
398 };
399
400 /* L4 CORE -> SR1 interface */
401 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
402 {
403 .pa_start = OMAP34XX_SR2_BASE,
404 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
405 .flags = ADDR_TYPE_RT,
406 },
407 };
408
409 static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
410 .master = &omap3xxx_l4_core_hwmod,
411 .slave = &omap34xx_sr2_hwmod,
412 .clk = "sr_l4_ick",
413 .addr = omap3_sr2_addr_space,
414 .addr_cnt = ARRAY_SIZE(omap3_sr2_addr_space),
415 .user = OCP_USER_MPU,
416 };
417
418 /*
419 * usbhsotg interface data
420 */
421
422 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
423 {
424 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
425 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
426 .flags = ADDR_TYPE_RT
427 },
428 };
429
430 /* l4_core -> usbhsotg */
431 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
432 .master = &omap3xxx_l4_core_hwmod,
433 .slave = &omap3xxx_usbhsotg_hwmod,
434 .clk = "l4_ick",
435 .addr = omap3xxx_usbhsotg_addrs,
436 .addr_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_addrs),
437 .user = OCP_USER_MPU,
438 };
439
440 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
441 &omap3xxx_usbhsotg__l3,
442 };
443
444 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
445 &omap3xxx_l4_core__usbhsotg,
446 };
447
448 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
449 {
450 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
451 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
452 .flags = ADDR_TYPE_RT
453 },
454 };
455
456 /* l4_core -> usbhsotg */
457 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
458 .master = &omap3xxx_l4_core_hwmod,
459 .slave = &am35xx_usbhsotg_hwmod,
460 .clk = "l4_ick",
461 .addr = am35xx_usbhsotg_addrs,
462 .addr_cnt = ARRAY_SIZE(am35xx_usbhsotg_addrs),
463 .user = OCP_USER_MPU,
464 };
465
466 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
467 &am35xx_usbhsotg__l3,
468 };
469
470 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
471 &am35xx_l4_core__usbhsotg,
472 };
473 /* Slave interfaces on the L4_CORE interconnect */
474 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
475 &omap3xxx_l3_main__l4_core,
476 &omap3_l4_core__sr1,
477 &omap3_l4_core__sr2,
478 };
479
480 /* Master interfaces on the L4_CORE interconnect */
481 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = {
482 &omap3xxx_l4_core__l4_wkup,
483 &omap3_l4_core__uart1,
484 &omap3_l4_core__uart2,
485 &omap3_l4_core__i2c1,
486 &omap3_l4_core__i2c2,
487 &omap3_l4_core__i2c3,
488 };
489
490 /* L4 CORE */
491 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
492 .name = "l4_core",
493 .class = &l4_hwmod_class,
494 .masters = omap3xxx_l4_core_masters,
495 .masters_cnt = ARRAY_SIZE(omap3xxx_l4_core_masters),
496 .slaves = omap3xxx_l4_core_slaves,
497 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves),
498 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
499 .flags = HWMOD_NO_IDLEST,
500 };
501
502 /* Slave interfaces on the L4_PER interconnect */
503 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
504 &omap3xxx_l3_main__l4_per,
505 };
506
507 /* Master interfaces on the L4_PER interconnect */
508 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = {
509 &omap3_l4_per__uart3,
510 &omap3_l4_per__uart4,
511 };
512
513 /* L4 PER */
514 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
515 .name = "l4_per",
516 .class = &l4_hwmod_class,
517 .masters = omap3xxx_l4_per_masters,
518 .masters_cnt = ARRAY_SIZE(omap3xxx_l4_per_masters),
519 .slaves = omap3xxx_l4_per_slaves,
520 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves),
521 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
522 .flags = HWMOD_NO_IDLEST,
523 };
524
525 /* Slave interfaces on the L4_WKUP interconnect */
526 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
527 &omap3xxx_l4_core__l4_wkup,
528 };
529
530 /* Master interfaces on the L4_WKUP interconnect */
531 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_masters[] = {
532 };
533
534 /* L4 WKUP */
535 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
536 .name = "l4_wkup",
537 .class = &l4_hwmod_class,
538 .masters = omap3xxx_l4_wkup_masters,
539 .masters_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_masters),
540 .slaves = omap3xxx_l4_wkup_slaves,
541 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
542 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
543 .flags = HWMOD_NO_IDLEST,
544 };
545
546 /* Master interfaces on the MPU device */
547 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
548 &omap3xxx_mpu__l3_main,
549 };
550
551 /* MPU */
552 static struct omap_hwmod omap3xxx_mpu_hwmod = {
553 .name = "mpu",
554 .class = &mpu_hwmod_class,
555 .main_clk = "arm_fck",
556 .masters = omap3xxx_mpu_masters,
557 .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters),
558 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
559 };
560
561 /*
562 * IVA2_2 interface data
563 */
564
565 /* IVA2 <- L3 interface */
566 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
567 .master = &omap3xxx_l3_main_hwmod,
568 .slave = &omap3xxx_iva_hwmod,
569 .clk = "iva2_ck",
570 .user = OCP_USER_MPU | OCP_USER_SDMA,
571 };
572
573 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
574 &omap3xxx_l3__iva,
575 };
576
577 /*
578 * IVA2 (IVA2)
579 */
580
581 static struct omap_hwmod omap3xxx_iva_hwmod = {
582 .name = "iva",
583 .class = &iva_hwmod_class,
584 .masters = omap3xxx_iva_masters,
585 .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters),
586 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
587 };
588
589 /* timer class */
590 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
591 .rev_offs = 0x0000,
592 .sysc_offs = 0x0010,
593 .syss_offs = 0x0014,
594 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
595 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
596 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
597 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
598 .sysc_fields = &omap_hwmod_sysc_type1,
599 };
600
601 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
602 .name = "timer",
603 .sysc = &omap3xxx_timer_1ms_sysc,
604 .rev = OMAP_TIMER_IP_VERSION_1,
605 };
606
607 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
608 .rev_offs = 0x0000,
609 .sysc_offs = 0x0010,
610 .syss_offs = 0x0014,
611 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
612 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
613 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
614 .sysc_fields = &omap_hwmod_sysc_type1,
615 };
616
617 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
618 .name = "timer",
619 .sysc = &omap3xxx_timer_sysc,
620 .rev = OMAP_TIMER_IP_VERSION_1,
621 };
622
623 /* timer1 */
624 static struct omap_hwmod omap3xxx_timer1_hwmod;
625 static struct omap_hwmod_irq_info omap3xxx_timer1_mpu_irqs[] = {
626 { .irq = 37, },
627 };
628
629 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
630 {
631 .pa_start = 0x48318000,
632 .pa_end = 0x48318000 + SZ_1K - 1,
633 .flags = ADDR_TYPE_RT
634 },
635 };
636
637 /* l4_wkup -> timer1 */
638 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
639 .master = &omap3xxx_l4_wkup_hwmod,
640 .slave = &omap3xxx_timer1_hwmod,
641 .clk = "gpt1_ick",
642 .addr = omap3xxx_timer1_addrs,
643 .addr_cnt = ARRAY_SIZE(omap3xxx_timer1_addrs),
644 .user = OCP_USER_MPU | OCP_USER_SDMA,
645 };
646
647 /* timer1 slave port */
648 static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
649 &omap3xxx_l4_wkup__timer1,
650 };
651
652 /* timer1 hwmod */
653 static struct omap_hwmod omap3xxx_timer1_hwmod = {
654 .name = "timer1",
655 .mpu_irqs = omap3xxx_timer1_mpu_irqs,
656 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer1_mpu_irqs),
657 .main_clk = "gpt1_fck",
658 .prcm = {
659 .omap2 = {
660 .prcm_reg_id = 1,
661 .module_bit = OMAP3430_EN_GPT1_SHIFT,
662 .module_offs = WKUP_MOD,
663 .idlest_reg_id = 1,
664 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
665 },
666 },
667 .slaves = omap3xxx_timer1_slaves,
668 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer1_slaves),
669 .class = &omap3xxx_timer_1ms_hwmod_class,
670 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
671 };
672
673 /* timer2 */
674 static struct omap_hwmod omap3xxx_timer2_hwmod;
675 static struct omap_hwmod_irq_info omap3xxx_timer2_mpu_irqs[] = {
676 { .irq = 38, },
677 };
678
679 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
680 {
681 .pa_start = 0x49032000,
682 .pa_end = 0x49032000 + SZ_1K - 1,
683 .flags = ADDR_TYPE_RT
684 },
685 };
686
687 /* l4_per -> timer2 */
688 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
689 .master = &omap3xxx_l4_per_hwmod,
690 .slave = &omap3xxx_timer2_hwmod,
691 .clk = "gpt2_ick",
692 .addr = omap3xxx_timer2_addrs,
693 .addr_cnt = ARRAY_SIZE(omap3xxx_timer2_addrs),
694 .user = OCP_USER_MPU | OCP_USER_SDMA,
695 };
696
697 /* timer2 slave port */
698 static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
699 &omap3xxx_l4_per__timer2,
700 };
701
702 /* timer2 hwmod */
703 static struct omap_hwmod omap3xxx_timer2_hwmod = {
704 .name = "timer2",
705 .mpu_irqs = omap3xxx_timer2_mpu_irqs,
706 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer2_mpu_irqs),
707 .main_clk = "gpt2_fck",
708 .prcm = {
709 .omap2 = {
710 .prcm_reg_id = 1,
711 .module_bit = OMAP3430_EN_GPT2_SHIFT,
712 .module_offs = OMAP3430_PER_MOD,
713 .idlest_reg_id = 1,
714 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
715 },
716 },
717 .slaves = omap3xxx_timer2_slaves,
718 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer2_slaves),
719 .class = &omap3xxx_timer_1ms_hwmod_class,
720 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
721 };
722
723 /* timer3 */
724 static struct omap_hwmod omap3xxx_timer3_hwmod;
725 static struct omap_hwmod_irq_info omap3xxx_timer3_mpu_irqs[] = {
726 { .irq = 39, },
727 };
728
729 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
730 {
731 .pa_start = 0x49034000,
732 .pa_end = 0x49034000 + SZ_1K - 1,
733 .flags = ADDR_TYPE_RT
734 },
735 };
736
737 /* l4_per -> timer3 */
738 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
739 .master = &omap3xxx_l4_per_hwmod,
740 .slave = &omap3xxx_timer3_hwmod,
741 .clk = "gpt3_ick",
742 .addr = omap3xxx_timer3_addrs,
743 .addr_cnt = ARRAY_SIZE(omap3xxx_timer3_addrs),
744 .user = OCP_USER_MPU | OCP_USER_SDMA,
745 };
746
747 /* timer3 slave port */
748 static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
749 &omap3xxx_l4_per__timer3,
750 };
751
752 /* timer3 hwmod */
753 static struct omap_hwmod omap3xxx_timer3_hwmod = {
754 .name = "timer3",
755 .mpu_irqs = omap3xxx_timer3_mpu_irqs,
756 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer3_mpu_irqs),
757 .main_clk = "gpt3_fck",
758 .prcm = {
759 .omap2 = {
760 .prcm_reg_id = 1,
761 .module_bit = OMAP3430_EN_GPT3_SHIFT,
762 .module_offs = OMAP3430_PER_MOD,
763 .idlest_reg_id = 1,
764 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
765 },
766 },
767 .slaves = omap3xxx_timer3_slaves,
768 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer3_slaves),
769 .class = &omap3xxx_timer_hwmod_class,
770 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
771 };
772
773 /* timer4 */
774 static struct omap_hwmod omap3xxx_timer4_hwmod;
775 static struct omap_hwmod_irq_info omap3xxx_timer4_mpu_irqs[] = {
776 { .irq = 40, },
777 };
778
779 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
780 {
781 .pa_start = 0x49036000,
782 .pa_end = 0x49036000 + SZ_1K - 1,
783 .flags = ADDR_TYPE_RT
784 },
785 };
786
787 /* l4_per -> timer4 */
788 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
789 .master = &omap3xxx_l4_per_hwmod,
790 .slave = &omap3xxx_timer4_hwmod,
791 .clk = "gpt4_ick",
792 .addr = omap3xxx_timer4_addrs,
793 .addr_cnt = ARRAY_SIZE(omap3xxx_timer4_addrs),
794 .user = OCP_USER_MPU | OCP_USER_SDMA,
795 };
796
797 /* timer4 slave port */
798 static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
799 &omap3xxx_l4_per__timer4,
800 };
801
802 /* timer4 hwmod */
803 static struct omap_hwmod omap3xxx_timer4_hwmod = {
804 .name = "timer4",
805 .mpu_irqs = omap3xxx_timer4_mpu_irqs,
806 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer4_mpu_irqs),
807 .main_clk = "gpt4_fck",
808 .prcm = {
809 .omap2 = {
810 .prcm_reg_id = 1,
811 .module_bit = OMAP3430_EN_GPT4_SHIFT,
812 .module_offs = OMAP3430_PER_MOD,
813 .idlest_reg_id = 1,
814 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
815 },
816 },
817 .slaves = omap3xxx_timer4_slaves,
818 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer4_slaves),
819 .class = &omap3xxx_timer_hwmod_class,
820 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
821 };
822
823 /* timer5 */
824 static struct omap_hwmod omap3xxx_timer5_hwmod;
825 static struct omap_hwmod_irq_info omap3xxx_timer5_mpu_irqs[] = {
826 { .irq = 41, },
827 };
828
829 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
830 {
831 .pa_start = 0x49038000,
832 .pa_end = 0x49038000 + SZ_1K - 1,
833 .flags = ADDR_TYPE_RT
834 },
835 };
836
837 /* l4_per -> timer5 */
838 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
839 .master = &omap3xxx_l4_per_hwmod,
840 .slave = &omap3xxx_timer5_hwmod,
841 .clk = "gpt5_ick",
842 .addr = omap3xxx_timer5_addrs,
843 .addr_cnt = ARRAY_SIZE(omap3xxx_timer5_addrs),
844 .user = OCP_USER_MPU | OCP_USER_SDMA,
845 };
846
847 /* timer5 slave port */
848 static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
849 &omap3xxx_l4_per__timer5,
850 };
851
852 /* timer5 hwmod */
853 static struct omap_hwmod omap3xxx_timer5_hwmod = {
854 .name = "timer5",
855 .mpu_irqs = omap3xxx_timer5_mpu_irqs,
856 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer5_mpu_irqs),
857 .main_clk = "gpt5_fck",
858 .prcm = {
859 .omap2 = {
860 .prcm_reg_id = 1,
861 .module_bit = OMAP3430_EN_GPT5_SHIFT,
862 .module_offs = OMAP3430_PER_MOD,
863 .idlest_reg_id = 1,
864 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
865 },
866 },
867 .slaves = omap3xxx_timer5_slaves,
868 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer5_slaves),
869 .class = &omap3xxx_timer_hwmod_class,
870 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
871 };
872
873 /* timer6 */
874 static struct omap_hwmod omap3xxx_timer6_hwmod;
875 static struct omap_hwmod_irq_info omap3xxx_timer6_mpu_irqs[] = {
876 { .irq = 42, },
877 };
878
879 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
880 {
881 .pa_start = 0x4903A000,
882 .pa_end = 0x4903A000 + SZ_1K - 1,
883 .flags = ADDR_TYPE_RT
884 },
885 };
886
887 /* l4_per -> timer6 */
888 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
889 .master = &omap3xxx_l4_per_hwmod,
890 .slave = &omap3xxx_timer6_hwmod,
891 .clk = "gpt6_ick",
892 .addr = omap3xxx_timer6_addrs,
893 .addr_cnt = ARRAY_SIZE(omap3xxx_timer6_addrs),
894 .user = OCP_USER_MPU | OCP_USER_SDMA,
895 };
896
897 /* timer6 slave port */
898 static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
899 &omap3xxx_l4_per__timer6,
900 };
901
902 /* timer6 hwmod */
903 static struct omap_hwmod omap3xxx_timer6_hwmod = {
904 .name = "timer6",
905 .mpu_irqs = omap3xxx_timer6_mpu_irqs,
906 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer6_mpu_irqs),
907 .main_clk = "gpt6_fck",
908 .prcm = {
909 .omap2 = {
910 .prcm_reg_id = 1,
911 .module_bit = OMAP3430_EN_GPT6_SHIFT,
912 .module_offs = OMAP3430_PER_MOD,
913 .idlest_reg_id = 1,
914 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
915 },
916 },
917 .slaves = omap3xxx_timer6_slaves,
918 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer6_slaves),
919 .class = &omap3xxx_timer_hwmod_class,
920 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
921 };
922
923 /* timer7 */
924 static struct omap_hwmod omap3xxx_timer7_hwmod;
925 static struct omap_hwmod_irq_info omap3xxx_timer7_mpu_irqs[] = {
926 { .irq = 43, },
927 };
928
929 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
930 {
931 .pa_start = 0x4903C000,
932 .pa_end = 0x4903C000 + SZ_1K - 1,
933 .flags = ADDR_TYPE_RT
934 },
935 };
936
937 /* l4_per -> timer7 */
938 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
939 .master = &omap3xxx_l4_per_hwmod,
940 .slave = &omap3xxx_timer7_hwmod,
941 .clk = "gpt7_ick",
942 .addr = omap3xxx_timer7_addrs,
943 .addr_cnt = ARRAY_SIZE(omap3xxx_timer7_addrs),
944 .user = OCP_USER_MPU | OCP_USER_SDMA,
945 };
946
947 /* timer7 slave port */
948 static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
949 &omap3xxx_l4_per__timer7,
950 };
951
952 /* timer7 hwmod */
953 static struct omap_hwmod omap3xxx_timer7_hwmod = {
954 .name = "timer7",
955 .mpu_irqs = omap3xxx_timer7_mpu_irqs,
956 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer7_mpu_irqs),
957 .main_clk = "gpt7_fck",
958 .prcm = {
959 .omap2 = {
960 .prcm_reg_id = 1,
961 .module_bit = OMAP3430_EN_GPT7_SHIFT,
962 .module_offs = OMAP3430_PER_MOD,
963 .idlest_reg_id = 1,
964 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
965 },
966 },
967 .slaves = omap3xxx_timer7_slaves,
968 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer7_slaves),
969 .class = &omap3xxx_timer_hwmod_class,
970 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
971 };
972
973 /* timer8 */
974 static struct omap_hwmod omap3xxx_timer8_hwmod;
975 static struct omap_hwmod_irq_info omap3xxx_timer8_mpu_irqs[] = {
976 { .irq = 44, },
977 };
978
979 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
980 {
981 .pa_start = 0x4903E000,
982 .pa_end = 0x4903E000 + SZ_1K - 1,
983 .flags = ADDR_TYPE_RT
984 },
985 };
986
987 /* l4_per -> timer8 */
988 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
989 .master = &omap3xxx_l4_per_hwmod,
990 .slave = &omap3xxx_timer8_hwmod,
991 .clk = "gpt8_ick",
992 .addr = omap3xxx_timer8_addrs,
993 .addr_cnt = ARRAY_SIZE(omap3xxx_timer8_addrs),
994 .user = OCP_USER_MPU | OCP_USER_SDMA,
995 };
996
997 /* timer8 slave port */
998 static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
999 &omap3xxx_l4_per__timer8,
1000 };
1001
1002 /* timer8 hwmod */
1003 static struct omap_hwmod omap3xxx_timer8_hwmod = {
1004 .name = "timer8",
1005 .mpu_irqs = omap3xxx_timer8_mpu_irqs,
1006 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer8_mpu_irqs),
1007 .main_clk = "gpt8_fck",
1008 .prcm = {
1009 .omap2 = {
1010 .prcm_reg_id = 1,
1011 .module_bit = OMAP3430_EN_GPT8_SHIFT,
1012 .module_offs = OMAP3430_PER_MOD,
1013 .idlest_reg_id = 1,
1014 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
1015 },
1016 },
1017 .slaves = omap3xxx_timer8_slaves,
1018 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer8_slaves),
1019 .class = &omap3xxx_timer_hwmod_class,
1020 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1021 };
1022
1023 /* timer9 */
1024 static struct omap_hwmod omap3xxx_timer9_hwmod;
1025 static struct omap_hwmod_irq_info omap3xxx_timer9_mpu_irqs[] = {
1026 { .irq = 45, },
1027 };
1028
1029 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
1030 {
1031 .pa_start = 0x49040000,
1032 .pa_end = 0x49040000 + SZ_1K - 1,
1033 .flags = ADDR_TYPE_RT
1034 },
1035 };
1036
1037 /* l4_per -> timer9 */
1038 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
1039 .master = &omap3xxx_l4_per_hwmod,
1040 .slave = &omap3xxx_timer9_hwmod,
1041 .clk = "gpt9_ick",
1042 .addr = omap3xxx_timer9_addrs,
1043 .addr_cnt = ARRAY_SIZE(omap3xxx_timer9_addrs),
1044 .user = OCP_USER_MPU | OCP_USER_SDMA,
1045 };
1046
1047 /* timer9 slave port */
1048 static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
1049 &omap3xxx_l4_per__timer9,
1050 };
1051
1052 /* timer9 hwmod */
1053 static struct omap_hwmod omap3xxx_timer9_hwmod = {
1054 .name = "timer9",
1055 .mpu_irqs = omap3xxx_timer9_mpu_irqs,
1056 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer9_mpu_irqs),
1057 .main_clk = "gpt9_fck",
1058 .prcm = {
1059 .omap2 = {
1060 .prcm_reg_id = 1,
1061 .module_bit = OMAP3430_EN_GPT9_SHIFT,
1062 .module_offs = OMAP3430_PER_MOD,
1063 .idlest_reg_id = 1,
1064 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
1065 },
1066 },
1067 .slaves = omap3xxx_timer9_slaves,
1068 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer9_slaves),
1069 .class = &omap3xxx_timer_hwmod_class,
1070 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1071 };
1072
1073 /* timer10 */
1074 static struct omap_hwmod omap3xxx_timer10_hwmod;
1075 static struct omap_hwmod_irq_info omap3xxx_timer10_mpu_irqs[] = {
1076 { .irq = 46, },
1077 };
1078
1079 static struct omap_hwmod_addr_space omap3xxx_timer10_addrs[] = {
1080 {
1081 .pa_start = 0x48086000,
1082 .pa_end = 0x48086000 + SZ_1K - 1,
1083 .flags = ADDR_TYPE_RT
1084 },
1085 };
1086
1087 /* l4_core -> timer10 */
1088 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1089 .master = &omap3xxx_l4_core_hwmod,
1090 .slave = &omap3xxx_timer10_hwmod,
1091 .clk = "gpt10_ick",
1092 .addr = omap3xxx_timer10_addrs,
1093 .addr_cnt = ARRAY_SIZE(omap3xxx_timer10_addrs),
1094 .user = OCP_USER_MPU | OCP_USER_SDMA,
1095 };
1096
1097 /* timer10 slave port */
1098 static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1099 &omap3xxx_l4_core__timer10,
1100 };
1101
1102 /* timer10 hwmod */
1103 static struct omap_hwmod omap3xxx_timer10_hwmod = {
1104 .name = "timer10",
1105 .mpu_irqs = omap3xxx_timer10_mpu_irqs,
1106 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer10_mpu_irqs),
1107 .main_clk = "gpt10_fck",
1108 .prcm = {
1109 .omap2 = {
1110 .prcm_reg_id = 1,
1111 .module_bit = OMAP3430_EN_GPT10_SHIFT,
1112 .module_offs = CORE_MOD,
1113 .idlest_reg_id = 1,
1114 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
1115 },
1116 },
1117 .slaves = omap3xxx_timer10_slaves,
1118 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer10_slaves),
1119 .class = &omap3xxx_timer_1ms_hwmod_class,
1120 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1121 };
1122
1123 /* timer11 */
1124 static struct omap_hwmod omap3xxx_timer11_hwmod;
1125 static struct omap_hwmod_irq_info omap3xxx_timer11_mpu_irqs[] = {
1126 { .irq = 47, },
1127 };
1128
1129 static struct omap_hwmod_addr_space omap3xxx_timer11_addrs[] = {
1130 {
1131 .pa_start = 0x48088000,
1132 .pa_end = 0x48088000 + SZ_1K - 1,
1133 .flags = ADDR_TYPE_RT
1134 },
1135 };
1136
1137 /* l4_core -> timer11 */
1138 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1139 .master = &omap3xxx_l4_core_hwmod,
1140 .slave = &omap3xxx_timer11_hwmod,
1141 .clk = "gpt11_ick",
1142 .addr = omap3xxx_timer11_addrs,
1143 .addr_cnt = ARRAY_SIZE(omap3xxx_timer11_addrs),
1144 .user = OCP_USER_MPU | OCP_USER_SDMA,
1145 };
1146
1147 /* timer11 slave port */
1148 static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1149 &omap3xxx_l4_core__timer11,
1150 };
1151
1152 /* timer11 hwmod */
1153 static struct omap_hwmod omap3xxx_timer11_hwmod = {
1154 .name = "timer11",
1155 .mpu_irqs = omap3xxx_timer11_mpu_irqs,
1156 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer11_mpu_irqs),
1157 .main_clk = "gpt11_fck",
1158 .prcm = {
1159 .omap2 = {
1160 .prcm_reg_id = 1,
1161 .module_bit = OMAP3430_EN_GPT11_SHIFT,
1162 .module_offs = CORE_MOD,
1163 .idlest_reg_id = 1,
1164 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
1165 },
1166 },
1167 .slaves = omap3xxx_timer11_slaves,
1168 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer11_slaves),
1169 .class = &omap3xxx_timer_hwmod_class,
1170 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1171 };
1172
1173 /* timer12*/
1174 static struct omap_hwmod omap3xxx_timer12_hwmod;
1175 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1176 { .irq = 95, },
1177 };
1178
1179 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1180 {
1181 .pa_start = 0x48304000,
1182 .pa_end = 0x48304000 + SZ_1K - 1,
1183 .flags = ADDR_TYPE_RT
1184 },
1185 };
1186
1187 /* l4_core -> timer12 */
1188 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1189 .master = &omap3xxx_l4_core_hwmod,
1190 .slave = &omap3xxx_timer12_hwmod,
1191 .clk = "gpt12_ick",
1192 .addr = omap3xxx_timer12_addrs,
1193 .addr_cnt = ARRAY_SIZE(omap3xxx_timer12_addrs),
1194 .user = OCP_USER_MPU | OCP_USER_SDMA,
1195 };
1196
1197 /* timer12 slave port */
1198 static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1199 &omap3xxx_l4_core__timer12,
1200 };
1201
1202 /* timer12 hwmod */
1203 static struct omap_hwmod omap3xxx_timer12_hwmod = {
1204 .name = "timer12",
1205 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
1206 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer12_mpu_irqs),
1207 .main_clk = "gpt12_fck",
1208 .prcm = {
1209 .omap2 = {
1210 .prcm_reg_id = 1,
1211 .module_bit = OMAP3430_EN_GPT12_SHIFT,
1212 .module_offs = WKUP_MOD,
1213 .idlest_reg_id = 1,
1214 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
1215 },
1216 },
1217 .slaves = omap3xxx_timer12_slaves,
1218 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer12_slaves),
1219 .class = &omap3xxx_timer_hwmod_class,
1220 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1221 };
1222
1223 /* l4_wkup -> wd_timer2 */
1224 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1225 {
1226 .pa_start = 0x48314000,
1227 .pa_end = 0x4831407f,
1228 .flags = ADDR_TYPE_RT
1229 },
1230 };
1231
1232 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1233 .master = &omap3xxx_l4_wkup_hwmod,
1234 .slave = &omap3xxx_wd_timer2_hwmod,
1235 .clk = "wdt2_ick",
1236 .addr = omap3xxx_wd_timer2_addrs,
1237 .addr_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_addrs),
1238 .user = OCP_USER_MPU | OCP_USER_SDMA,
1239 };
1240
1241 /*
1242 * 'wd_timer' class
1243 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1244 * overflow condition
1245 */
1246
1247 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
1248 .rev_offs = 0x0000,
1249 .sysc_offs = 0x0010,
1250 .syss_offs = 0x0014,
1251 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
1252 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1253 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY),
1254 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1255 .sysc_fields = &omap_hwmod_sysc_type1,
1256 };
1257
1258 /* I2C common */
1259 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1260 .rev_offs = 0x00,
1261 .sysc_offs = 0x20,
1262 .syss_offs = 0x10,
1263 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1264 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1265 SYSC_HAS_AUTOIDLE),
1266 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1267 .sysc_fields = &omap_hwmod_sysc_type1,
1268 };
1269
1270 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
1271 .name = "wd_timer",
1272 .sysc = &omap3xxx_wd_timer_sysc,
1273 .pre_shutdown = &omap2_wd_timer_disable
1274 };
1275
1276 /* wd_timer2 */
1277 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
1278 &omap3xxx_l4_wkup__wd_timer2,
1279 };
1280
1281 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1282 .name = "wd_timer2",
1283 .class = &omap3xxx_wd_timer_hwmod_class,
1284 .main_clk = "wdt2_fck",
1285 .prcm = {
1286 .omap2 = {
1287 .prcm_reg_id = 1,
1288 .module_bit = OMAP3430_EN_WDT2_SHIFT,
1289 .module_offs = WKUP_MOD,
1290 .idlest_reg_id = 1,
1291 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
1292 },
1293 },
1294 .slaves = omap3xxx_wd_timer2_slaves,
1295 .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1296 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1297 };
1298
1299 /* UART common */
1300
1301 static struct omap_hwmod_class_sysconfig uart_sysc = {
1302 .rev_offs = 0x50,
1303 .sysc_offs = 0x54,
1304 .syss_offs = 0x58,
1305 .sysc_flags = (SYSC_HAS_SIDLEMODE |
1306 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1307 SYSC_HAS_AUTOIDLE),
1308 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1309 .sysc_fields = &omap_hwmod_sysc_type1,
1310 };
1311
1312 static struct omap_hwmod_class uart_class = {
1313 .name = "uart",
1314 .sysc = &uart_sysc,
1315 };
1316
1317 /* UART1 */
1318
1319 static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
1320 { .irq = INT_24XX_UART1_IRQ, },
1321 };
1322
1323 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
1324 { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
1325 { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
1326 };
1327
1328 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1329 &omap3_l4_core__uart1,
1330 };
1331
1332 static struct omap_hwmod omap3xxx_uart1_hwmod = {
1333 .name = "uart1",
1334 .mpu_irqs = uart1_mpu_irqs,
1335 .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs),
1336 .sdma_reqs = uart1_sdma_reqs,
1337 .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
1338 .main_clk = "uart1_fck",
1339 .prcm = {
1340 .omap2 = {
1341 .module_offs = CORE_MOD,
1342 .prcm_reg_id = 1,
1343 .module_bit = OMAP3430_EN_UART1_SHIFT,
1344 .idlest_reg_id = 1,
1345 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
1346 },
1347 },
1348 .slaves = omap3xxx_uart1_slaves,
1349 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
1350 .class = &uart_class,
1351 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1352 };
1353
1354 /* UART2 */
1355
1356 static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
1357 { .irq = INT_24XX_UART2_IRQ, },
1358 };
1359
1360 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
1361 { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
1362 { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
1363 };
1364
1365 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1366 &omap3_l4_core__uart2,
1367 };
1368
1369 static struct omap_hwmod omap3xxx_uart2_hwmod = {
1370 .name = "uart2",
1371 .mpu_irqs = uart2_mpu_irqs,
1372 .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs),
1373 .sdma_reqs = uart2_sdma_reqs,
1374 .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
1375 .main_clk = "uart2_fck",
1376 .prcm = {
1377 .omap2 = {
1378 .module_offs = CORE_MOD,
1379 .prcm_reg_id = 1,
1380 .module_bit = OMAP3430_EN_UART2_SHIFT,
1381 .idlest_reg_id = 1,
1382 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
1383 },
1384 },
1385 .slaves = omap3xxx_uart2_slaves,
1386 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
1387 .class = &uart_class,
1388 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1389 };
1390
1391 /* UART3 */
1392
1393 static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
1394 { .irq = INT_24XX_UART3_IRQ, },
1395 };
1396
1397 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
1398 { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
1399 { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
1400 };
1401
1402 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1403 &omap3_l4_per__uart3,
1404 };
1405
1406 static struct omap_hwmod omap3xxx_uart3_hwmod = {
1407 .name = "uart3",
1408 .mpu_irqs = uart3_mpu_irqs,
1409 .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs),
1410 .sdma_reqs = uart3_sdma_reqs,
1411 .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
1412 .main_clk = "uart3_fck",
1413 .prcm = {
1414 .omap2 = {
1415 .module_offs = OMAP3430_PER_MOD,
1416 .prcm_reg_id = 1,
1417 .module_bit = OMAP3430_EN_UART3_SHIFT,
1418 .idlest_reg_id = 1,
1419 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
1420 },
1421 },
1422 .slaves = omap3xxx_uart3_slaves,
1423 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
1424 .class = &uart_class,
1425 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1426 };
1427
1428 /* UART4 */
1429
1430 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1431 { .irq = INT_36XX_UART4_IRQ, },
1432 };
1433
1434 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1435 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
1436 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
1437 };
1438
1439 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
1440 &omap3_l4_per__uart4,
1441 };
1442
1443 static struct omap_hwmod omap3xxx_uart4_hwmod = {
1444 .name = "uart4",
1445 .mpu_irqs = uart4_mpu_irqs,
1446 .mpu_irqs_cnt = ARRAY_SIZE(uart4_mpu_irqs),
1447 .sdma_reqs = uart4_sdma_reqs,
1448 .sdma_reqs_cnt = ARRAY_SIZE(uart4_sdma_reqs),
1449 .main_clk = "uart4_fck",
1450 .prcm = {
1451 .omap2 = {
1452 .module_offs = OMAP3430_PER_MOD,
1453 .prcm_reg_id = 1,
1454 .module_bit = OMAP3630_EN_UART4_SHIFT,
1455 .idlest_reg_id = 1,
1456 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
1457 },
1458 },
1459 .slaves = omap3xxx_uart4_slaves,
1460 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
1461 .class = &uart_class,
1462 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
1463 };
1464
1465 static struct omap_hwmod_class i2c_class = {
1466 .name = "i2c",
1467 .sysc = &i2c_sysc,
1468 };
1469
1470 /*
1471 * 'dss' class
1472 * display sub-system
1473 */
1474
1475 static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = {
1476 .rev_offs = 0x0000,
1477 .sysc_offs = 0x0010,
1478 .syss_offs = 0x0014,
1479 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1480 .sysc_fields = &omap_hwmod_sysc_type1,
1481 };
1482
1483 static struct omap_hwmod_class omap3xxx_dss_hwmod_class = {
1484 .name = "dss",
1485 .sysc = &omap3xxx_dss_sysc,
1486 };
1487
1488 /* dss */
1489 static struct omap_hwmod_irq_info omap3xxx_dss_irqs[] = {
1490 { .irq = 25 },
1491 };
1492
1493 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1494 { .name = "dispc", .dma_req = 5 },
1495 { .name = "dsi1", .dma_req = 74 },
1496 };
1497
1498 /* dss */
1499 /* dss master ports */
1500 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1501 &omap3xxx_dss__l3,
1502 };
1503
1504 static struct omap_hwmod_addr_space omap3xxx_dss_addrs[] = {
1505 {
1506 .pa_start = 0x48050000,
1507 .pa_end = 0x480503FF,
1508 .flags = ADDR_TYPE_RT
1509 },
1510 };
1511
1512 /* l4_core -> dss */
1513 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1514 .master = &omap3xxx_l4_core_hwmod,
1515 .slave = &omap3430es1_dss_core_hwmod,
1516 .clk = "dss_ick",
1517 .addr = omap3xxx_dss_addrs,
1518 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs),
1519 .fw = {
1520 .omap2 = {
1521 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1522 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1523 .flags = OMAP_FIREWALL_L4,
1524 }
1525 },
1526 .user = OCP_USER_MPU | OCP_USER_SDMA,
1527 };
1528
1529 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1530 .master = &omap3xxx_l4_core_hwmod,
1531 .slave = &omap3xxx_dss_core_hwmod,
1532 .clk = "dss_ick",
1533 .addr = omap3xxx_dss_addrs,
1534 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs),
1535 .fw = {
1536 .omap2 = {
1537 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1538 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1539 .flags = OMAP_FIREWALL_L4,
1540 }
1541 },
1542 .user = OCP_USER_MPU | OCP_USER_SDMA,
1543 };
1544
1545 /* dss slave ports */
1546 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
1547 &omap3430es1_l4_core__dss,
1548 };
1549
1550 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1551 &omap3xxx_l4_core__dss,
1552 };
1553
1554 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1555 { .role = "tv_clk", .clk = "dss_tv_fck" },
1556 { .role = "dssclk", .clk = "dss_96m_fck" },
1557 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1558 };
1559
1560 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1561 .name = "dss_core",
1562 .class = &omap3xxx_dss_hwmod_class,
1563 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1564 .mpu_irqs = omap3xxx_dss_irqs,
1565 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dss_irqs),
1566 .sdma_reqs = omap3xxx_dss_sdma_chs,
1567 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
1568
1569 .prcm = {
1570 .omap2 = {
1571 .prcm_reg_id = 1,
1572 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1573 .module_offs = OMAP3430_DSS_MOD,
1574 .idlest_reg_id = 1,
1575 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
1576 },
1577 },
1578 .opt_clks = dss_opt_clks,
1579 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1580 .slaves = omap3430es1_dss_slaves,
1581 .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves),
1582 .masters = omap3xxx_dss_masters,
1583 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1584 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
1585 .flags = HWMOD_NO_IDLEST,
1586 };
1587
1588 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1589 .name = "dss_core",
1590 .class = &omap3xxx_dss_hwmod_class,
1591 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1592 .mpu_irqs = omap3xxx_dss_irqs,
1593 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dss_irqs),
1594 .sdma_reqs = omap3xxx_dss_sdma_chs,
1595 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
1596
1597 .prcm = {
1598 .omap2 = {
1599 .prcm_reg_id = 1,
1600 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1601 .module_offs = OMAP3430_DSS_MOD,
1602 .idlest_reg_id = 1,
1603 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
1604 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
1605 },
1606 },
1607 .opt_clks = dss_opt_clks,
1608 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1609 .slaves = omap3xxx_dss_slaves,
1610 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves),
1611 .masters = omap3xxx_dss_masters,
1612 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1613 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 |
1614 CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
1615 };
1616
1617 /*
1618 * 'dispc' class
1619 * display controller
1620 */
1621
1622 static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = {
1623 .rev_offs = 0x0000,
1624 .sysc_offs = 0x0010,
1625 .syss_offs = 0x0014,
1626 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1627 SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP |
1628 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1629 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1630 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1631 .sysc_fields = &omap_hwmod_sysc_type1,
1632 };
1633
1634 static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = {
1635 .name = "dispc",
1636 .sysc = &omap3xxx_dispc_sysc,
1637 };
1638
1639 static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs[] = {
1640 {
1641 .pa_start = 0x48050400,
1642 .pa_end = 0x480507FF,
1643 .flags = ADDR_TYPE_RT
1644 },
1645 };
1646
1647 /* l4_core -> dss_dispc */
1648 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1649 .master = &omap3xxx_l4_core_hwmod,
1650 .slave = &omap3xxx_dss_dispc_hwmod,
1651 .clk = "dss_ick",
1652 .addr = omap3xxx_dss_dispc_addrs,
1653 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_addrs),
1654 .fw = {
1655 .omap2 = {
1656 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1657 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1658 .flags = OMAP_FIREWALL_L4,
1659 }
1660 },
1661 .user = OCP_USER_MPU | OCP_USER_SDMA,
1662 };
1663
1664 /* dss_dispc slave ports */
1665 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1666 &omap3xxx_l4_core__dss_dispc,
1667 };
1668
1669 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1670 .name = "dss_dispc",
1671 .class = &omap3xxx_dispc_hwmod_class,
1672 .main_clk = "dss1_alwon_fck",
1673 .prcm = {
1674 .omap2 = {
1675 .prcm_reg_id = 1,
1676 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1677 .module_offs = OMAP3430_DSS_MOD,
1678 },
1679 },
1680 .slaves = omap3xxx_dss_dispc_slaves,
1681 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1682 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1683 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1684 CHIP_GE_OMAP3630ES1_1),
1685 .flags = HWMOD_NO_IDLEST,
1686 };
1687
1688 /*
1689 * 'dsi' class
1690 * display serial interface controller
1691 */
1692
1693 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1694 .name = "dsi",
1695 };
1696
1697 /* dss_dsi1 */
1698 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1699 {
1700 .pa_start = 0x4804FC00,
1701 .pa_end = 0x4804FFFF,
1702 .flags = ADDR_TYPE_RT
1703 },
1704 };
1705
1706 /* l4_core -> dss_dsi1 */
1707 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1708 .master = &omap3xxx_l4_core_hwmod,
1709 .slave = &omap3xxx_dss_dsi1_hwmod,
1710 .addr = omap3xxx_dss_dsi1_addrs,
1711 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_addrs),
1712 .fw = {
1713 .omap2 = {
1714 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1715 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1716 .flags = OMAP_FIREWALL_L4,
1717 }
1718 },
1719 .user = OCP_USER_MPU | OCP_USER_SDMA,
1720 };
1721
1722 /* dss_dsi1 slave ports */
1723 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1724 &omap3xxx_l4_core__dss_dsi1,
1725 };
1726
1727 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1728 .name = "dss_dsi1",
1729 .class = &omap3xxx_dsi_hwmod_class,
1730 .main_clk = "dss1_alwon_fck",
1731 .prcm = {
1732 .omap2 = {
1733 .prcm_reg_id = 1,
1734 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1735 .module_offs = OMAP3430_DSS_MOD,
1736 },
1737 },
1738 .slaves = omap3xxx_dss_dsi1_slaves,
1739 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1740 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1741 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1742 CHIP_GE_OMAP3630ES1_1),
1743 .flags = HWMOD_NO_IDLEST,
1744 };
1745
1746 /*
1747 * 'rfbi' class
1748 * remote frame buffer interface
1749 */
1750
1751 static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = {
1752 .rev_offs = 0x0000,
1753 .sysc_offs = 0x0010,
1754 .syss_offs = 0x0014,
1755 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1756 SYSC_HAS_AUTOIDLE),
1757 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1758 .sysc_fields = &omap_hwmod_sysc_type1,
1759 };
1760
1761 static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = {
1762 .name = "rfbi",
1763 .sysc = &omap3xxx_rfbi_sysc,
1764 };
1765
1766 static struct omap_hwmod_addr_space omap3xxx_dss_rfbi_addrs[] = {
1767 {
1768 .pa_start = 0x48050800,
1769 .pa_end = 0x48050BFF,
1770 .flags = ADDR_TYPE_RT
1771 },
1772 };
1773
1774 /* l4_core -> dss_rfbi */
1775 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1776 .master = &omap3xxx_l4_core_hwmod,
1777 .slave = &omap3xxx_dss_rfbi_hwmod,
1778 .clk = "dss_ick",
1779 .addr = omap3xxx_dss_rfbi_addrs,
1780 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_addrs),
1781 .fw = {
1782 .omap2 = {
1783 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1784 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1785 .flags = OMAP_FIREWALL_L4,
1786 }
1787 },
1788 .user = OCP_USER_MPU | OCP_USER_SDMA,
1789 };
1790
1791 /* dss_rfbi slave ports */
1792 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1793 &omap3xxx_l4_core__dss_rfbi,
1794 };
1795
1796 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1797 .name = "dss_rfbi",
1798 .class = &omap3xxx_rfbi_hwmod_class,
1799 .main_clk = "dss1_alwon_fck",
1800 .prcm = {
1801 .omap2 = {
1802 .prcm_reg_id = 1,
1803 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1804 .module_offs = OMAP3430_DSS_MOD,
1805 },
1806 },
1807 .slaves = omap3xxx_dss_rfbi_slaves,
1808 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1809 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1810 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1811 CHIP_GE_OMAP3630ES1_1),
1812 .flags = HWMOD_NO_IDLEST,
1813 };
1814
1815 /*
1816 * 'venc' class
1817 * video encoder
1818 */
1819
1820 static struct omap_hwmod_class omap3xxx_venc_hwmod_class = {
1821 .name = "venc",
1822 };
1823
1824 /* dss_venc */
1825 static struct omap_hwmod_addr_space omap3xxx_dss_venc_addrs[] = {
1826 {
1827 .pa_start = 0x48050C00,
1828 .pa_end = 0x48050FFF,
1829 .flags = ADDR_TYPE_RT
1830 },
1831 };
1832
1833 /* l4_core -> dss_venc */
1834 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1835 .master = &omap3xxx_l4_core_hwmod,
1836 .slave = &omap3xxx_dss_venc_hwmod,
1837 .clk = "dss_tv_fck",
1838 .addr = omap3xxx_dss_venc_addrs,
1839 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_venc_addrs),
1840 .fw = {
1841 .omap2 = {
1842 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1843 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1844 .flags = OMAP_FIREWALL_L4,
1845 }
1846 },
1847 .flags = OCPIF_SWSUP_IDLE,
1848 .user = OCP_USER_MPU | OCP_USER_SDMA,
1849 };
1850
1851 /* dss_venc slave ports */
1852 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1853 &omap3xxx_l4_core__dss_venc,
1854 };
1855
1856 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1857 .name = "dss_venc",
1858 .class = &omap3xxx_venc_hwmod_class,
1859 .main_clk = "dss1_alwon_fck",
1860 .prcm = {
1861 .omap2 = {
1862 .prcm_reg_id = 1,
1863 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1864 .module_offs = OMAP3430_DSS_MOD,
1865 },
1866 },
1867 .slaves = omap3xxx_dss_venc_slaves,
1868 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1869 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1870 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1871 CHIP_GE_OMAP3630ES1_1),
1872 .flags = HWMOD_NO_IDLEST,
1873 };
1874
1875 /* I2C1 */
1876
1877 static struct omap_i2c_dev_attr i2c1_dev_attr = {
1878 .fifo_depth = 8, /* bytes */
1879 };
1880
1881 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1882 { .irq = INT_24XX_I2C1_IRQ, },
1883 };
1884
1885 static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
1886 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
1887 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
1888 };
1889
1890 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1891 &omap3_l4_core__i2c1,
1892 };
1893
1894 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1895 .name = "i2c1",
1896 .mpu_irqs = i2c1_mpu_irqs,
1897 .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs),
1898 .sdma_reqs = i2c1_sdma_reqs,
1899 .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
1900 .main_clk = "i2c1_fck",
1901 .prcm = {
1902 .omap2 = {
1903 .module_offs = CORE_MOD,
1904 .prcm_reg_id = 1,
1905 .module_bit = OMAP3430_EN_I2C1_SHIFT,
1906 .idlest_reg_id = 1,
1907 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1908 },
1909 },
1910 .slaves = omap3xxx_i2c1_slaves,
1911 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1912 .class = &i2c_class,
1913 .dev_attr = &i2c1_dev_attr,
1914 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1915 };
1916
1917 /* I2C2 */
1918
1919 static struct omap_i2c_dev_attr i2c2_dev_attr = {
1920 .fifo_depth = 8, /* bytes */
1921 };
1922
1923 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1924 { .irq = INT_24XX_I2C2_IRQ, },
1925 };
1926
1927 static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
1928 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
1929 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
1930 };
1931
1932 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1933 &omap3_l4_core__i2c2,
1934 };
1935
1936 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1937 .name = "i2c2",
1938 .mpu_irqs = i2c2_mpu_irqs,
1939 .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs),
1940 .sdma_reqs = i2c2_sdma_reqs,
1941 .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
1942 .main_clk = "i2c2_fck",
1943 .prcm = {
1944 .omap2 = {
1945 .module_offs = CORE_MOD,
1946 .prcm_reg_id = 1,
1947 .module_bit = OMAP3430_EN_I2C2_SHIFT,
1948 .idlest_reg_id = 1,
1949 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1950 },
1951 },
1952 .slaves = omap3xxx_i2c2_slaves,
1953 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1954 .class = &i2c_class,
1955 .dev_attr = &i2c2_dev_attr,
1956 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1957 };
1958
1959 /* I2C3 */
1960
1961 static struct omap_i2c_dev_attr i2c3_dev_attr = {
1962 .fifo_depth = 64, /* bytes */
1963 };
1964
1965 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1966 { .irq = INT_34XX_I2C3_IRQ, },
1967 };
1968
1969 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1970 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1971 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1972 };
1973
1974 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1975 &omap3_l4_core__i2c3,
1976 };
1977
1978 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1979 .name = "i2c3",
1980 .mpu_irqs = i2c3_mpu_irqs,
1981 .mpu_irqs_cnt = ARRAY_SIZE(i2c3_mpu_irqs),
1982 .sdma_reqs = i2c3_sdma_reqs,
1983 .sdma_reqs_cnt = ARRAY_SIZE(i2c3_sdma_reqs),
1984 .main_clk = "i2c3_fck",
1985 .prcm = {
1986 .omap2 = {
1987 .module_offs = CORE_MOD,
1988 .prcm_reg_id = 1,
1989 .module_bit = OMAP3430_EN_I2C3_SHIFT,
1990 .idlest_reg_id = 1,
1991 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1992 },
1993 },
1994 .slaves = omap3xxx_i2c3_slaves,
1995 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1996 .class = &i2c_class,
1997 .dev_attr = &i2c3_dev_attr,
1998 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1999 };
2000
2001 /* l4_wkup -> gpio1 */
2002 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2003 {
2004 .pa_start = 0x48310000,
2005 .pa_end = 0x483101ff,
2006 .flags = ADDR_TYPE_RT
2007 },
2008 };
2009
2010 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2011 .master = &omap3xxx_l4_wkup_hwmod,
2012 .slave = &omap3xxx_gpio1_hwmod,
2013 .addr = omap3xxx_gpio1_addrs,
2014 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio1_addrs),
2015 .user = OCP_USER_MPU | OCP_USER_SDMA,
2016 };
2017
2018 /* l4_per -> gpio2 */
2019 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2020 {
2021 .pa_start = 0x49050000,
2022 .pa_end = 0x490501ff,
2023 .flags = ADDR_TYPE_RT
2024 },
2025 };
2026
2027 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2028 .master = &omap3xxx_l4_per_hwmod,
2029 .slave = &omap3xxx_gpio2_hwmod,
2030 .addr = omap3xxx_gpio2_addrs,
2031 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio2_addrs),
2032 .user = OCP_USER_MPU | OCP_USER_SDMA,
2033 };
2034
2035 /* l4_per -> gpio3 */
2036 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2037 {
2038 .pa_start = 0x49052000,
2039 .pa_end = 0x490521ff,
2040 .flags = ADDR_TYPE_RT
2041 },
2042 };
2043
2044 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2045 .master = &omap3xxx_l4_per_hwmod,
2046 .slave = &omap3xxx_gpio3_hwmod,
2047 .addr = omap3xxx_gpio3_addrs,
2048 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio3_addrs),
2049 .user = OCP_USER_MPU | OCP_USER_SDMA,
2050 };
2051
2052 /* l4_per -> gpio4 */
2053 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
2054 {
2055 .pa_start = 0x49054000,
2056 .pa_end = 0x490541ff,
2057 .flags = ADDR_TYPE_RT
2058 },
2059 };
2060
2061 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
2062 .master = &omap3xxx_l4_per_hwmod,
2063 .slave = &omap3xxx_gpio4_hwmod,
2064 .addr = omap3xxx_gpio4_addrs,
2065 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio4_addrs),
2066 .user = OCP_USER_MPU | OCP_USER_SDMA,
2067 };
2068
2069 /* l4_per -> gpio5 */
2070 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
2071 {
2072 .pa_start = 0x49056000,
2073 .pa_end = 0x490561ff,
2074 .flags = ADDR_TYPE_RT
2075 },
2076 };
2077
2078 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
2079 .master = &omap3xxx_l4_per_hwmod,
2080 .slave = &omap3xxx_gpio5_hwmod,
2081 .addr = omap3xxx_gpio5_addrs,
2082 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio5_addrs),
2083 .user = OCP_USER_MPU | OCP_USER_SDMA,
2084 };
2085
2086 /* l4_per -> gpio6 */
2087 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
2088 {
2089 .pa_start = 0x49058000,
2090 .pa_end = 0x490581ff,
2091 .flags = ADDR_TYPE_RT
2092 },
2093 };
2094
2095 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
2096 .master = &omap3xxx_l4_per_hwmod,
2097 .slave = &omap3xxx_gpio6_hwmod,
2098 .addr = omap3xxx_gpio6_addrs,
2099 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio6_addrs),
2100 .user = OCP_USER_MPU | OCP_USER_SDMA,
2101 };
2102
2103 /*
2104 * 'gpio' class
2105 * general purpose io module
2106 */
2107
2108 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
2109 .rev_offs = 0x0000,
2110 .sysc_offs = 0x0010,
2111 .syss_offs = 0x0014,
2112 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2113 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2114 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2115 .sysc_fields = &omap_hwmod_sysc_type1,
2116 };
2117
2118 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
2119 .name = "gpio",
2120 .sysc = &omap3xxx_gpio_sysc,
2121 .rev = 1,
2122 };
2123
2124 /* gpio_dev_attr*/
2125 static struct omap_gpio_dev_attr gpio_dev_attr = {
2126 .bank_width = 32,
2127 .dbck_flag = true,
2128 };
2129
2130 /* gpio1 */
2131 static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = {
2132 { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */
2133 };
2134
2135 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
2136 { .role = "dbclk", .clk = "gpio1_dbck", },
2137 };
2138
2139 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
2140 &omap3xxx_l4_wkup__gpio1,
2141 };
2142
2143 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
2144 .name = "gpio1",
2145 .mpu_irqs = omap3xxx_gpio1_irqs,
2146 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio1_irqs),
2147 .main_clk = "gpio1_ick",
2148 .opt_clks = gpio1_opt_clks,
2149 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
2150 .prcm = {
2151 .omap2 = {
2152 .prcm_reg_id = 1,
2153 .module_bit = OMAP3430_EN_GPIO1_SHIFT,
2154 .module_offs = WKUP_MOD,
2155 .idlest_reg_id = 1,
2156 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
2157 },
2158 },
2159 .slaves = omap3xxx_gpio1_slaves,
2160 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves),
2161 .class = &omap3xxx_gpio_hwmod_class,
2162 .dev_attr = &gpio_dev_attr,
2163 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2164 };
2165
2166 /* gpio2 */
2167 static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = {
2168 { .irq = 30 }, /* INT_34XX_GPIO_BANK2 */
2169 };
2170
2171 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
2172 { .role = "dbclk", .clk = "gpio2_dbck", },
2173 };
2174
2175 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
2176 &omap3xxx_l4_per__gpio2,
2177 };
2178
2179 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
2180 .name = "gpio2",
2181 .mpu_irqs = omap3xxx_gpio2_irqs,
2182 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio2_irqs),
2183 .main_clk = "gpio2_ick",
2184 .opt_clks = gpio2_opt_clks,
2185 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
2186 .prcm = {
2187 .omap2 = {
2188 .prcm_reg_id = 1,
2189 .module_bit = OMAP3430_EN_GPIO2_SHIFT,
2190 .module_offs = OMAP3430_PER_MOD,
2191 .idlest_reg_id = 1,
2192 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
2193 },
2194 },
2195 .slaves = omap3xxx_gpio2_slaves,
2196 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves),
2197 .class = &omap3xxx_gpio_hwmod_class,
2198 .dev_attr = &gpio_dev_attr,
2199 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2200 };
2201
2202 /* gpio3 */
2203 static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = {
2204 { .irq = 31 }, /* INT_34XX_GPIO_BANK3 */
2205 };
2206
2207 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
2208 { .role = "dbclk", .clk = "gpio3_dbck", },
2209 };
2210
2211 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
2212 &omap3xxx_l4_per__gpio3,
2213 };
2214
2215 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
2216 .name = "gpio3",
2217 .mpu_irqs = omap3xxx_gpio3_irqs,
2218 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio3_irqs),
2219 .main_clk = "gpio3_ick",
2220 .opt_clks = gpio3_opt_clks,
2221 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
2222 .prcm = {
2223 .omap2 = {
2224 .prcm_reg_id = 1,
2225 .module_bit = OMAP3430_EN_GPIO3_SHIFT,
2226 .module_offs = OMAP3430_PER_MOD,
2227 .idlest_reg_id = 1,
2228 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
2229 },
2230 },
2231 .slaves = omap3xxx_gpio3_slaves,
2232 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves),
2233 .class = &omap3xxx_gpio_hwmod_class,
2234 .dev_attr = &gpio_dev_attr,
2235 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2236 };
2237
2238 /* gpio4 */
2239 static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = {
2240 { .irq = 32 }, /* INT_34XX_GPIO_BANK4 */
2241 };
2242
2243 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2244 { .role = "dbclk", .clk = "gpio4_dbck", },
2245 };
2246
2247 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
2248 &omap3xxx_l4_per__gpio4,
2249 };
2250
2251 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
2252 .name = "gpio4",
2253 .mpu_irqs = omap3xxx_gpio4_irqs,
2254 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio4_irqs),
2255 .main_clk = "gpio4_ick",
2256 .opt_clks = gpio4_opt_clks,
2257 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
2258 .prcm = {
2259 .omap2 = {
2260 .prcm_reg_id = 1,
2261 .module_bit = OMAP3430_EN_GPIO4_SHIFT,
2262 .module_offs = OMAP3430_PER_MOD,
2263 .idlest_reg_id = 1,
2264 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
2265 },
2266 },
2267 .slaves = omap3xxx_gpio4_slaves,
2268 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves),
2269 .class = &omap3xxx_gpio_hwmod_class,
2270 .dev_attr = &gpio_dev_attr,
2271 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2272 };
2273
2274 /* gpio5 */
2275 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
2276 { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
2277 };
2278
2279 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2280 { .role = "dbclk", .clk = "gpio5_dbck", },
2281 };
2282
2283 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
2284 &omap3xxx_l4_per__gpio5,
2285 };
2286
2287 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2288 .name = "gpio5",
2289 .mpu_irqs = omap3xxx_gpio5_irqs,
2290 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio5_irqs),
2291 .main_clk = "gpio5_ick",
2292 .opt_clks = gpio5_opt_clks,
2293 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
2294 .prcm = {
2295 .omap2 = {
2296 .prcm_reg_id = 1,
2297 .module_bit = OMAP3430_EN_GPIO5_SHIFT,
2298 .module_offs = OMAP3430_PER_MOD,
2299 .idlest_reg_id = 1,
2300 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
2301 },
2302 },
2303 .slaves = omap3xxx_gpio5_slaves,
2304 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves),
2305 .class = &omap3xxx_gpio_hwmod_class,
2306 .dev_attr = &gpio_dev_attr,
2307 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2308 };
2309
2310 /* gpio6 */
2311 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
2312 { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
2313 };
2314
2315 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2316 { .role = "dbclk", .clk = "gpio6_dbck", },
2317 };
2318
2319 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
2320 &omap3xxx_l4_per__gpio6,
2321 };
2322
2323 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2324 .name = "gpio6",
2325 .mpu_irqs = omap3xxx_gpio6_irqs,
2326 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio6_irqs),
2327 .main_clk = "gpio6_ick",
2328 .opt_clks = gpio6_opt_clks,
2329 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
2330 .prcm = {
2331 .omap2 = {
2332 .prcm_reg_id = 1,
2333 .module_bit = OMAP3430_EN_GPIO6_SHIFT,
2334 .module_offs = OMAP3430_PER_MOD,
2335 .idlest_reg_id = 1,
2336 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
2337 },
2338 },
2339 .slaves = omap3xxx_gpio6_slaves,
2340 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves),
2341 .class = &omap3xxx_gpio_hwmod_class,
2342 .dev_attr = &gpio_dev_attr,
2343 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2344 };
2345
2346 /* dma_system -> L3 */
2347 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2348 .master = &omap3xxx_dma_system_hwmod,
2349 .slave = &omap3xxx_l3_main_hwmod,
2350 .clk = "core_l3_ick",
2351 .user = OCP_USER_MPU | OCP_USER_SDMA,
2352 };
2353
2354 /* dma attributes */
2355 static struct omap_dma_dev_attr dma_dev_attr = {
2356 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
2357 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
2358 .lch_count = 32,
2359 };
2360
2361 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
2362 .rev_offs = 0x0000,
2363 .sysc_offs = 0x002c,
2364 .syss_offs = 0x0028,
2365 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2366 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
2367 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
2368 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2369 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2370 .sysc_fields = &omap_hwmod_sysc_type1,
2371 };
2372
2373 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2374 .name = "dma",
2375 .sysc = &omap3xxx_dma_sysc,
2376 };
2377
2378 /* dma_system */
2379 static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
2380 { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
2381 { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
2382 { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
2383 { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
2384 };
2385
2386 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2387 {
2388 .pa_start = 0x48056000,
2389 .pa_end = 0x4a0560ff,
2390 .flags = ADDR_TYPE_RT
2391 },
2392 };
2393
2394 /* dma_system master ports */
2395 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
2396 &omap3xxx_dma_system__l3,
2397 };
2398
2399 /* l4_cfg -> dma_system */
2400 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2401 .master = &omap3xxx_l4_core_hwmod,
2402 .slave = &omap3xxx_dma_system_hwmod,
2403 .clk = "core_l4_ick",
2404 .addr = omap3xxx_dma_system_addrs,
2405 .addr_cnt = ARRAY_SIZE(omap3xxx_dma_system_addrs),
2406 .user = OCP_USER_MPU | OCP_USER_SDMA,
2407 };
2408
2409 /* dma_system slave ports */
2410 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2411 &omap3xxx_l4_core__dma_system,
2412 };
2413
2414 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2415 .name = "dma",
2416 .class = &omap3xxx_dma_hwmod_class,
2417 .mpu_irqs = omap3xxx_dma_system_irqs,
2418 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dma_system_irqs),
2419 .main_clk = "core_l3_ick",
2420 .prcm = {
2421 .omap2 = {
2422 .module_offs = CORE_MOD,
2423 .prcm_reg_id = 1,
2424 .module_bit = OMAP3430_ST_SDMA_SHIFT,
2425 .idlest_reg_id = 1,
2426 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
2427 },
2428 },
2429 .slaves = omap3xxx_dma_system_slaves,
2430 .slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves),
2431 .masters = omap3xxx_dma_system_masters,
2432 .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters),
2433 .dev_attr = &dma_dev_attr,
2434 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2435 .flags = HWMOD_NO_IDLEST,
2436 };
2437
2438 /*
2439 * 'mcbsp' class
2440 * multi channel buffered serial port controller
2441 */
2442
2443 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
2444 .sysc_offs = 0x008c,
2445 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2446 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2447 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2448 .sysc_fields = &omap_hwmod_sysc_type1,
2449 .clockact = 0x2,
2450 };
2451
2452 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
2453 .name = "mcbsp",
2454 .sysc = &omap3xxx_mcbsp_sysc,
2455 .rev = MCBSP_CONFIG_TYPE3,
2456 };
2457
2458 /* mcbsp1 */
2459 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2460 { .name = "irq", .irq = 16 },
2461 { .name = "tx", .irq = 59 },
2462 { .name = "rx", .irq = 60 },
2463 };
2464
2465 static struct omap_hwmod_dma_info omap3xxx_mcbsp1_sdma_chs[] = {
2466 { .name = "rx", .dma_req = 32 },
2467 { .name = "tx", .dma_req = 31 },
2468 };
2469
2470 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2471 {
2472 .name = "mpu",
2473 .pa_start = 0x48074000,
2474 .pa_end = 0x480740ff,
2475 .flags = ADDR_TYPE_RT
2476 },
2477 };
2478
2479 /* l4_core -> mcbsp1 */
2480 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2481 .master = &omap3xxx_l4_core_hwmod,
2482 .slave = &omap3xxx_mcbsp1_hwmod,
2483 .clk = "mcbsp1_ick",
2484 .addr = omap3xxx_mcbsp1_addrs,
2485 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_addrs),
2486 .user = OCP_USER_MPU | OCP_USER_SDMA,
2487 };
2488
2489 /* mcbsp1 slave ports */
2490 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2491 &omap3xxx_l4_core__mcbsp1,
2492 };
2493
2494 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2495 .name = "mcbsp1",
2496 .class = &omap3xxx_mcbsp_hwmod_class,
2497 .mpu_irqs = omap3xxx_mcbsp1_irqs,
2498 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_irqs),
2499 .sdma_reqs = omap3xxx_mcbsp1_sdma_chs,
2500 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_sdma_chs),
2501 .main_clk = "mcbsp1_fck",
2502 .prcm = {
2503 .omap2 = {
2504 .prcm_reg_id = 1,
2505 .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
2506 .module_offs = CORE_MOD,
2507 .idlest_reg_id = 1,
2508 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2509 },
2510 },
2511 .slaves = omap3xxx_mcbsp1_slaves,
2512 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2513 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2514 };
2515
2516 /* mcbsp2 */
2517 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2518 { .name = "irq", .irq = 17 },
2519 { .name = "tx", .irq = 62 },
2520 { .name = "rx", .irq = 63 },
2521 };
2522
2523 static struct omap_hwmod_dma_info omap3xxx_mcbsp2_sdma_chs[] = {
2524 { .name = "rx", .dma_req = 34 },
2525 { .name = "tx", .dma_req = 33 },
2526 };
2527
2528 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2529 {
2530 .name = "mpu",
2531 .pa_start = 0x49022000,
2532 .pa_end = 0x490220ff,
2533 .flags = ADDR_TYPE_RT
2534 },
2535 };
2536
2537 /* l4_per -> mcbsp2 */
2538 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2539 .master = &omap3xxx_l4_per_hwmod,
2540 .slave = &omap3xxx_mcbsp2_hwmod,
2541 .clk = "mcbsp2_ick",
2542 .addr = omap3xxx_mcbsp2_addrs,
2543 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_addrs),
2544 .user = OCP_USER_MPU | OCP_USER_SDMA,
2545 };
2546
2547 /* mcbsp2 slave ports */
2548 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2549 &omap3xxx_l4_per__mcbsp2,
2550 };
2551
2552 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2553 .sidetone = "mcbsp2_sidetone",
2554 };
2555
2556 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2557 .name = "mcbsp2",
2558 .class = &omap3xxx_mcbsp_hwmod_class,
2559 .mpu_irqs = omap3xxx_mcbsp2_irqs,
2560 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_irqs),
2561 .sdma_reqs = omap3xxx_mcbsp2_sdma_chs,
2562 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sdma_chs),
2563 .main_clk = "mcbsp2_fck",
2564 .prcm = {
2565 .omap2 = {
2566 .prcm_reg_id = 1,
2567 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2568 .module_offs = OMAP3430_PER_MOD,
2569 .idlest_reg_id = 1,
2570 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2571 },
2572 },
2573 .slaves = omap3xxx_mcbsp2_slaves,
2574 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2575 .dev_attr = &omap34xx_mcbsp2_dev_attr,
2576 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2577 };
2578
2579 /* mcbsp3 */
2580 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2581 { .name = "irq", .irq = 22 },
2582 { .name = "tx", .irq = 89 },
2583 { .name = "rx", .irq = 90 },
2584 };
2585
2586 static struct omap_hwmod_dma_info omap3xxx_mcbsp3_sdma_chs[] = {
2587 { .name = "rx", .dma_req = 18 },
2588 { .name = "tx", .dma_req = 17 },
2589 };
2590
2591 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2592 {
2593 .name = "mpu",
2594 .pa_start = 0x49024000,
2595 .pa_end = 0x490240ff,
2596 .flags = ADDR_TYPE_RT
2597 },
2598 };
2599
2600 /* l4_per -> mcbsp3 */
2601 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2602 .master = &omap3xxx_l4_per_hwmod,
2603 .slave = &omap3xxx_mcbsp3_hwmod,
2604 .clk = "mcbsp3_ick",
2605 .addr = omap3xxx_mcbsp3_addrs,
2606 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_addrs),
2607 .user = OCP_USER_MPU | OCP_USER_SDMA,
2608 };
2609
2610 /* mcbsp3 slave ports */
2611 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2612 &omap3xxx_l4_per__mcbsp3,
2613 };
2614
2615 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2616 .sidetone = "mcbsp3_sidetone",
2617 };
2618
2619 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2620 .name = "mcbsp3",
2621 .class = &omap3xxx_mcbsp_hwmod_class,
2622 .mpu_irqs = omap3xxx_mcbsp3_irqs,
2623 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_irqs),
2624 .sdma_reqs = omap3xxx_mcbsp3_sdma_chs,
2625 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sdma_chs),
2626 .main_clk = "mcbsp3_fck",
2627 .prcm = {
2628 .omap2 = {
2629 .prcm_reg_id = 1,
2630 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2631 .module_offs = OMAP3430_PER_MOD,
2632 .idlest_reg_id = 1,
2633 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2634 },
2635 },
2636 .slaves = omap3xxx_mcbsp3_slaves,
2637 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2638 .dev_attr = &omap34xx_mcbsp3_dev_attr,
2639 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2640 };
2641
2642 /* mcbsp4 */
2643 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2644 { .name = "irq", .irq = 23 },
2645 { .name = "tx", .irq = 54 },
2646 { .name = "rx", .irq = 55 },
2647 };
2648
2649 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2650 { .name = "rx", .dma_req = 20 },
2651 { .name = "tx", .dma_req = 19 },
2652 };
2653
2654 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2655 {
2656 .name = "mpu",
2657 .pa_start = 0x49026000,
2658 .pa_end = 0x490260ff,
2659 .flags = ADDR_TYPE_RT
2660 },
2661 };
2662
2663 /* l4_per -> mcbsp4 */
2664 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2665 .master = &omap3xxx_l4_per_hwmod,
2666 .slave = &omap3xxx_mcbsp4_hwmod,
2667 .clk = "mcbsp4_ick",
2668 .addr = omap3xxx_mcbsp4_addrs,
2669 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_addrs),
2670 .user = OCP_USER_MPU | OCP_USER_SDMA,
2671 };
2672
2673 /* mcbsp4 slave ports */
2674 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2675 &omap3xxx_l4_per__mcbsp4,
2676 };
2677
2678 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2679 .name = "mcbsp4",
2680 .class = &omap3xxx_mcbsp_hwmod_class,
2681 .mpu_irqs = omap3xxx_mcbsp4_irqs,
2682 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_irqs),
2683 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
2684 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_sdma_chs),
2685 .main_clk = "mcbsp4_fck",
2686 .prcm = {
2687 .omap2 = {
2688 .prcm_reg_id = 1,
2689 .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
2690 .module_offs = OMAP3430_PER_MOD,
2691 .idlest_reg_id = 1,
2692 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2693 },
2694 },
2695 .slaves = omap3xxx_mcbsp4_slaves,
2696 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2697 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2698 };
2699
2700 /* mcbsp5 */
2701 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2702 { .name = "irq", .irq = 27 },
2703 { .name = "tx", .irq = 81 },
2704 { .name = "rx", .irq = 82 },
2705 };
2706
2707 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2708 { .name = "rx", .dma_req = 22 },
2709 { .name = "tx", .dma_req = 21 },
2710 };
2711
2712 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2713 {
2714 .name = "mpu",
2715 .pa_start = 0x48096000,
2716 .pa_end = 0x480960ff,
2717 .flags = ADDR_TYPE_RT
2718 },
2719 };
2720
2721 /* l4_core -> mcbsp5 */
2722 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2723 .master = &omap3xxx_l4_core_hwmod,
2724 .slave = &omap3xxx_mcbsp5_hwmod,
2725 .clk = "mcbsp5_ick",
2726 .addr = omap3xxx_mcbsp5_addrs,
2727 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_addrs),
2728 .user = OCP_USER_MPU | OCP_USER_SDMA,
2729 };
2730
2731 /* mcbsp5 slave ports */
2732 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2733 &omap3xxx_l4_core__mcbsp5,
2734 };
2735
2736 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2737 .name = "mcbsp5",
2738 .class = &omap3xxx_mcbsp_hwmod_class,
2739 .mpu_irqs = omap3xxx_mcbsp5_irqs,
2740 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_irqs),
2741 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
2742 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_sdma_chs),
2743 .main_clk = "mcbsp5_fck",
2744 .prcm = {
2745 .omap2 = {
2746 .prcm_reg_id = 1,
2747 .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
2748 .module_offs = CORE_MOD,
2749 .idlest_reg_id = 1,
2750 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2751 },
2752 },
2753 .slaves = omap3xxx_mcbsp5_slaves,
2754 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2755 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2756 };
2757 /* 'mcbsp sidetone' class */
2758
2759 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2760 .sysc_offs = 0x0010,
2761 .sysc_flags = SYSC_HAS_AUTOIDLE,
2762 .sysc_fields = &omap_hwmod_sysc_type1,
2763 };
2764
2765 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2766 .name = "mcbsp_sidetone",
2767 .sysc = &omap3xxx_mcbsp_sidetone_sysc,
2768 };
2769
2770 /* mcbsp2_sidetone */
2771 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2772 { .name = "irq", .irq = 4 },
2773 };
2774
2775 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2776 {
2777 .name = "sidetone",
2778 .pa_start = 0x49028000,
2779 .pa_end = 0x490280ff,
2780 .flags = ADDR_TYPE_RT
2781 },
2782 };
2783
2784 /* l4_per -> mcbsp2_sidetone */
2785 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2786 .master = &omap3xxx_l4_per_hwmod,
2787 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
2788 .clk = "mcbsp2_ick",
2789 .addr = omap3xxx_mcbsp2_sidetone_addrs,
2790 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_addrs),
2791 .user = OCP_USER_MPU,
2792 };
2793
2794 /* mcbsp2_sidetone slave ports */
2795 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2796 &omap3xxx_l4_per__mcbsp2_sidetone,
2797 };
2798
2799 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2800 .name = "mcbsp2_sidetone",
2801 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2802 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
2803 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_irqs),
2804 .main_clk = "mcbsp2_fck",
2805 .prcm = {
2806 .omap2 = {
2807 .prcm_reg_id = 1,
2808 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2809 .module_offs = OMAP3430_PER_MOD,
2810 .idlest_reg_id = 1,
2811 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2812 },
2813 },
2814 .slaves = omap3xxx_mcbsp2_sidetone_slaves,
2815 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2816 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2817 };
2818
2819 /* mcbsp3_sidetone */
2820 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2821 { .name = "irq", .irq = 5 },
2822 };
2823
2824 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2825 {
2826 .name = "sidetone",
2827 .pa_start = 0x4902A000,
2828 .pa_end = 0x4902A0ff,
2829 .flags = ADDR_TYPE_RT
2830 },
2831 };
2832
2833 /* l4_per -> mcbsp3_sidetone */
2834 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2835 .master = &omap3xxx_l4_per_hwmod,
2836 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
2837 .clk = "mcbsp3_ick",
2838 .addr = omap3xxx_mcbsp3_sidetone_addrs,
2839 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_addrs),
2840 .user = OCP_USER_MPU,
2841 };
2842
2843 /* mcbsp3_sidetone slave ports */
2844 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2845 &omap3xxx_l4_per__mcbsp3_sidetone,
2846 };
2847
2848 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2849 .name = "mcbsp3_sidetone",
2850 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2851 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
2852 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_irqs),
2853 .main_clk = "mcbsp3_fck",
2854 .prcm = {
2855 .omap2 = {
2856 .prcm_reg_id = 1,
2857 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2858 .module_offs = OMAP3430_PER_MOD,
2859 .idlest_reg_id = 1,
2860 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2861 },
2862 },
2863 .slaves = omap3xxx_mcbsp3_sidetone_slaves,
2864 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2865 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2866 };
2867
2868
2869 /* SR common */
2870 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2871 .clkact_shift = 20,
2872 };
2873
2874 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
2875 .sysc_offs = 0x24,
2876 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
2877 .clockact = CLOCKACT_TEST_ICLK,
2878 .sysc_fields = &omap34xx_sr_sysc_fields,
2879 };
2880
2881 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2882 .name = "smartreflex",
2883 .sysc = &omap34xx_sr_sysc,
2884 .rev = 1,
2885 };
2886
2887 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2888 .sidle_shift = 24,
2889 .enwkup_shift = 26
2890 };
2891
2892 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
2893 .sysc_offs = 0x38,
2894 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2895 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2896 SYSC_NO_CACHE),
2897 .sysc_fields = &omap36xx_sr_sysc_fields,
2898 };
2899
2900 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
2901 .name = "smartreflex",
2902 .sysc = &omap36xx_sr_sysc,
2903 .rev = 2,
2904 };
2905
2906 /* SR1 */
2907 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
2908 &omap3_l4_core__sr1,
2909 };
2910
2911 static struct omap_hwmod omap34xx_sr1_hwmod = {
2912 .name = "sr1_hwmod",
2913 .class = &omap34xx_smartreflex_hwmod_class,
2914 .main_clk = "sr1_fck",
2915 .vdd_name = "mpu",
2916 .prcm = {
2917 .omap2 = {
2918 .prcm_reg_id = 1,
2919 .module_bit = OMAP3430_EN_SR1_SHIFT,
2920 .module_offs = WKUP_MOD,
2921 .idlest_reg_id = 1,
2922 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2923 },
2924 },
2925 .slaves = omap3_sr1_slaves,
2926 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
2927 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2928 CHIP_IS_OMAP3430ES3_0 |
2929 CHIP_IS_OMAP3430ES3_1),
2930 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2931 };
2932
2933 static struct omap_hwmod omap36xx_sr1_hwmod = {
2934 .name = "sr1_hwmod",
2935 .class = &omap36xx_smartreflex_hwmod_class,
2936 .main_clk = "sr1_fck",
2937 .vdd_name = "mpu",
2938 .prcm = {
2939 .omap2 = {
2940 .prcm_reg_id = 1,
2941 .module_bit = OMAP3430_EN_SR1_SHIFT,
2942 .module_offs = WKUP_MOD,
2943 .idlest_reg_id = 1,
2944 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2945 },
2946 },
2947 .slaves = omap3_sr1_slaves,
2948 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
2949 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2950 };
2951
2952 /* SR2 */
2953 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
2954 &omap3_l4_core__sr2,
2955 };
2956
2957 static struct omap_hwmod omap34xx_sr2_hwmod = {
2958 .name = "sr2_hwmod",
2959 .class = &omap34xx_smartreflex_hwmod_class,
2960 .main_clk = "sr2_fck",
2961 .vdd_name = "core",
2962 .prcm = {
2963 .omap2 = {
2964 .prcm_reg_id = 1,
2965 .module_bit = OMAP3430_EN_SR2_SHIFT,
2966 .module_offs = WKUP_MOD,
2967 .idlest_reg_id = 1,
2968 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2969 },
2970 },
2971 .slaves = omap3_sr2_slaves,
2972 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
2973 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2974 CHIP_IS_OMAP3430ES3_0 |
2975 CHIP_IS_OMAP3430ES3_1),
2976 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2977 };
2978
2979 static struct omap_hwmod omap36xx_sr2_hwmod = {
2980 .name = "sr2_hwmod",
2981 .class = &omap36xx_smartreflex_hwmod_class,
2982 .main_clk = "sr2_fck",
2983 .vdd_name = "core",
2984 .prcm = {
2985 .omap2 = {
2986 .prcm_reg_id = 1,
2987 .module_bit = OMAP3430_EN_SR2_SHIFT,
2988 .module_offs = WKUP_MOD,
2989 .idlest_reg_id = 1,
2990 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2991 },
2992 },
2993 .slaves = omap3_sr2_slaves,
2994 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
2995 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2996 };
2997
2998 /*
2999 * 'mailbox' class
3000 * mailbox module allowing communication between the on-chip processors
3001 * using a queued mailbox-interrupt mechanism.
3002 */
3003
3004 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
3005 .rev_offs = 0x000,
3006 .sysc_offs = 0x010,
3007 .syss_offs = 0x014,
3008 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3009 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
3010 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3011 .sysc_fields = &omap_hwmod_sysc_type1,
3012 };
3013
3014 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
3015 .name = "mailbox",
3016 .sysc = &omap3xxx_mailbox_sysc,
3017 };
3018
3019 static struct omap_hwmod omap3xxx_mailbox_hwmod;
3020 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
3021 { .irq = 26 },
3022 };
3023
3024 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
3025 {
3026 .pa_start = 0x48094000,
3027 .pa_end = 0x480941ff,
3028 .flags = ADDR_TYPE_RT,
3029 },
3030 };
3031
3032 /* l4_core -> mailbox */
3033 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3034 .master = &omap3xxx_l4_core_hwmod,
3035 .slave = &omap3xxx_mailbox_hwmod,
3036 .addr = omap3xxx_mailbox_addrs,
3037 .addr_cnt = ARRAY_SIZE(omap3xxx_mailbox_addrs),
3038 .user = OCP_USER_MPU | OCP_USER_SDMA,
3039 };
3040
3041 /* mailbox slave ports */
3042 static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
3043 &omap3xxx_l4_core__mailbox,
3044 };
3045
3046 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
3047 .name = "mailbox",
3048 .class = &omap3xxx_mailbox_hwmod_class,
3049 .mpu_irqs = omap3xxx_mailbox_irqs,
3050 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mailbox_irqs),
3051 .main_clk = "mailboxes_ick",
3052 .prcm = {
3053 .omap2 = {
3054 .prcm_reg_id = 1,
3055 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
3056 .module_offs = CORE_MOD,
3057 .idlest_reg_id = 1,
3058 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
3059 },
3060 },
3061 .slaves = omap3xxx_mailbox_slaves,
3062 .slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves),
3063 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3064 };
3065
3066 /* l4 core -> mcspi1 interface */
3067 static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = {
3068 {
3069 .pa_start = 0x48098000,
3070 .pa_end = 0x480980ff,
3071 .flags = ADDR_TYPE_RT,
3072 },
3073 };
3074
3075 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3076 .master = &omap3xxx_l4_core_hwmod,
3077 .slave = &omap34xx_mcspi1,
3078 .clk = "mcspi1_ick",
3079 .addr = omap34xx_mcspi1_addr_space,
3080 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi1_addr_space),
3081 .user = OCP_USER_MPU | OCP_USER_SDMA,
3082 };
3083
3084 /* l4 core -> mcspi2 interface */
3085 static struct omap_hwmod_addr_space omap34xx_mcspi2_addr_space[] = {
3086 {
3087 .pa_start = 0x4809a000,
3088 .pa_end = 0x4809a0ff,
3089 .flags = ADDR_TYPE_RT,
3090 },
3091 };
3092
3093 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3094 .master = &omap3xxx_l4_core_hwmod,
3095 .slave = &omap34xx_mcspi2,
3096 .clk = "mcspi2_ick",
3097 .addr = omap34xx_mcspi2_addr_space,
3098 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi2_addr_space),
3099 .user = OCP_USER_MPU | OCP_USER_SDMA,
3100 };
3101
3102 /* l4 core -> mcspi3 interface */
3103 static struct omap_hwmod_addr_space omap34xx_mcspi3_addr_space[] = {
3104 {
3105 .pa_start = 0x480b8000,
3106 .pa_end = 0x480b80ff,
3107 .flags = ADDR_TYPE_RT,
3108 },
3109 };
3110
3111 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3112 .master = &omap3xxx_l4_core_hwmod,
3113 .slave = &omap34xx_mcspi3,
3114 .clk = "mcspi3_ick",
3115 .addr = omap34xx_mcspi3_addr_space,
3116 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi3_addr_space),
3117 .user = OCP_USER_MPU | OCP_USER_SDMA,
3118 };
3119
3120 /* l4 core -> mcspi4 interface */
3121 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3122 {
3123 .pa_start = 0x480ba000,
3124 .pa_end = 0x480ba0ff,
3125 .flags = ADDR_TYPE_RT,
3126 },
3127 };
3128
3129 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3130 .master = &omap3xxx_l4_core_hwmod,
3131 .slave = &omap34xx_mcspi4,
3132 .clk = "mcspi4_ick",
3133 .addr = omap34xx_mcspi4_addr_space,
3134 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi4_addr_space),
3135 .user = OCP_USER_MPU | OCP_USER_SDMA,
3136 };
3137
3138 /*
3139 * 'mcspi' class
3140 * multichannel serial port interface (mcspi) / master/slave synchronous serial
3141 * bus
3142 */
3143
3144 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
3145 .rev_offs = 0x0000,
3146 .sysc_offs = 0x0010,
3147 .syss_offs = 0x0014,
3148 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3149 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3150 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3151 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3152 .sysc_fields = &omap_hwmod_sysc_type1,
3153 };
3154
3155 static struct omap_hwmod_class omap34xx_mcspi_class = {
3156 .name = "mcspi",
3157 .sysc = &omap34xx_mcspi_sysc,
3158 .rev = OMAP3_MCSPI_REV,
3159 };
3160
3161 /* mcspi1 */
3162 static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs[] = {
3163 { .name = "irq", .irq = 65 },
3164 };
3165
3166 static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = {
3167 { .name = "tx0", .dma_req = 35 },
3168 { .name = "rx0", .dma_req = 36 },
3169 { .name = "tx1", .dma_req = 37 },
3170 { .name = "rx1", .dma_req = 38 },
3171 { .name = "tx2", .dma_req = 39 },
3172 { .name = "rx2", .dma_req = 40 },
3173 { .name = "tx3", .dma_req = 41 },
3174 { .name = "rx3", .dma_req = 42 },
3175 };
3176
3177 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
3178 &omap34xx_l4_core__mcspi1,
3179 };
3180
3181 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
3182 .num_chipselect = 4,
3183 };
3184
3185 static struct omap_hwmod omap34xx_mcspi1 = {
3186 .name = "mcspi1",
3187 .mpu_irqs = omap34xx_mcspi1_mpu_irqs,
3188 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_mpu_irqs),
3189 .sdma_reqs = omap34xx_mcspi1_sdma_reqs,
3190 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs),
3191 .main_clk = "mcspi1_fck",
3192 .prcm = {
3193 .omap2 = {
3194 .module_offs = CORE_MOD,
3195 .prcm_reg_id = 1,
3196 .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
3197 .idlest_reg_id = 1,
3198 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
3199 },
3200 },
3201 .slaves = omap34xx_mcspi1_slaves,
3202 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves),
3203 .class = &omap34xx_mcspi_class,
3204 .dev_attr = &omap_mcspi1_dev_attr,
3205 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3206 };
3207
3208 /* mcspi2 */
3209 static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs[] = {
3210 { .name = "irq", .irq = 66 },
3211 };
3212
3213 static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = {
3214 { .name = "tx0", .dma_req = 43 },
3215 { .name = "rx0", .dma_req = 44 },
3216 { .name = "tx1", .dma_req = 45 },
3217 { .name = "rx1", .dma_req = 46 },
3218 };
3219
3220 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
3221 &omap34xx_l4_core__mcspi2,
3222 };
3223
3224 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
3225 .num_chipselect = 2,
3226 };
3227
3228 static struct omap_hwmod omap34xx_mcspi2 = {
3229 .name = "mcspi2",
3230 .mpu_irqs = omap34xx_mcspi2_mpu_irqs,
3231 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_mpu_irqs),
3232 .sdma_reqs = omap34xx_mcspi2_sdma_reqs,
3233 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs),
3234 .main_clk = "mcspi2_fck",
3235 .prcm = {
3236 .omap2 = {
3237 .module_offs = CORE_MOD,
3238 .prcm_reg_id = 1,
3239 .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
3240 .idlest_reg_id = 1,
3241 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
3242 },
3243 },
3244 .slaves = omap34xx_mcspi2_slaves,
3245 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves),
3246 .class = &omap34xx_mcspi_class,
3247 .dev_attr = &omap_mcspi2_dev_attr,
3248 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3249 };
3250
3251 /* mcspi3 */
3252 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
3253 { .name = "irq", .irq = 91 }, /* 91 */
3254 };
3255
3256 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
3257 { .name = "tx0", .dma_req = 15 },
3258 { .name = "rx0", .dma_req = 16 },
3259 { .name = "tx1", .dma_req = 23 },
3260 { .name = "rx1", .dma_req = 24 },
3261 };
3262
3263 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
3264 &omap34xx_l4_core__mcspi3,
3265 };
3266
3267 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
3268 .num_chipselect = 2,
3269 };
3270
3271 static struct omap_hwmod omap34xx_mcspi3 = {
3272 .name = "mcspi3",
3273 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
3274 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_mpu_irqs),
3275 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
3276 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs),
3277 .main_clk = "mcspi3_fck",
3278 .prcm = {
3279 .omap2 = {
3280 .module_offs = CORE_MOD,
3281 .prcm_reg_id = 1,
3282 .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
3283 .idlest_reg_id = 1,
3284 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
3285 },
3286 },
3287 .slaves = omap34xx_mcspi3_slaves,
3288 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves),
3289 .class = &omap34xx_mcspi_class,
3290 .dev_attr = &omap_mcspi3_dev_attr,
3291 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3292 };
3293
3294 /* SPI4 */
3295 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
3296 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
3297 };
3298
3299 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
3300 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
3301 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
3302 };
3303
3304 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
3305 &omap34xx_l4_core__mcspi4,
3306 };
3307
3308 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
3309 .num_chipselect = 1,
3310 };
3311
3312 static struct omap_hwmod omap34xx_mcspi4 = {
3313 .name = "mcspi4",
3314 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
3315 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_mpu_irqs),
3316 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
3317 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs),
3318 .main_clk = "mcspi4_fck",
3319 .prcm = {
3320 .omap2 = {
3321 .module_offs = CORE_MOD,
3322 .prcm_reg_id = 1,
3323 .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
3324 .idlest_reg_id = 1,
3325 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
3326 },
3327 },
3328 .slaves = omap34xx_mcspi4_slaves,
3329 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves),
3330 .class = &omap34xx_mcspi_class,
3331 .dev_attr = &omap_mcspi4_dev_attr,
3332 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3333 };
3334
3335 /*
3336 * usbhsotg
3337 */
3338 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
3339 .rev_offs = 0x0400,
3340 .sysc_offs = 0x0404,
3341 .syss_offs = 0x0408,
3342 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
3343 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3344 SYSC_HAS_AUTOIDLE),
3345 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3346 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
3347 .sysc_fields = &omap_hwmod_sysc_type1,
3348 };
3349
3350 static struct omap_hwmod_class usbotg_class = {
3351 .name = "usbotg",
3352 .sysc = &omap3xxx_usbhsotg_sysc,
3353 };
3354 /* usb_otg_hs */
3355 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
3356
3357 { .name = "mc", .irq = 92 },
3358 { .name = "dma", .irq = 93 },
3359 };
3360
3361 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
3362 .name = "usb_otg_hs",
3363 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
3364 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs),
3365 .main_clk = "hsotgusb_ick",
3366 .prcm = {
3367 .omap2 = {
3368 .prcm_reg_id = 1,
3369 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
3370 .module_offs = CORE_MOD,
3371 .idlest_reg_id = 1,
3372 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
3373 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
3374 },
3375 },
3376 .masters = omap3xxx_usbhsotg_masters,
3377 .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
3378 .slaves = omap3xxx_usbhsotg_slaves,
3379 .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
3380 .class = &usbotg_class,
3381
3382 /*
3383 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
3384 * broken when autoidle is enabled
3385 * workaround is to disable the autoidle bit at module level.
3386 */
3387 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
3388 | HWMOD_SWSUP_MSTANDBY,
3389 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
3390 };
3391
3392 /* usb_otg_hs */
3393 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
3394
3395 { .name = "mc", .irq = 71 },
3396 };
3397
3398 static struct omap_hwmod_class am35xx_usbotg_class = {
3399 .name = "am35xx_usbotg",
3400 .sysc = NULL,
3401 };
3402
3403 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
3404 .name = "am35x_otg_hs",
3405 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
3406 .mpu_irqs_cnt = ARRAY_SIZE(am35xx_usbhsotg_mpu_irqs),
3407 .main_clk = NULL,
3408 .prcm = {
3409 .omap2 = {
3410 },
3411 },
3412 .masters = am35xx_usbhsotg_masters,
3413 .masters_cnt = ARRAY_SIZE(am35xx_usbhsotg_masters),
3414 .slaves = am35xx_usbhsotg_slaves,
3415 .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves),
3416 .class = &am35xx_usbotg_class,
3417 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
3418 };
3419
3420 /* MMC/SD/SDIO common */
3421
3422 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
3423 .rev_offs = 0x1fc,
3424 .sysc_offs = 0x10,
3425 .syss_offs = 0x14,
3426 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3427 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3428 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3429 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3430 .sysc_fields = &omap_hwmod_sysc_type1,
3431 };
3432
3433 static struct omap_hwmod_class omap34xx_mmc_class = {
3434 .name = "mmc",
3435 .sysc = &omap34xx_mmc_sysc,
3436 };
3437
3438 /* MMC/SD/SDIO1 */
3439
3440 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
3441 { .irq = 83, },
3442 };
3443
3444 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
3445 { .name = "tx", .dma_req = 61, },
3446 { .name = "rx", .dma_req = 62, },
3447 };
3448
3449 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
3450 { .role = "dbck", .clk = "omap_32k_fck", },
3451 };
3452
3453 static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
3454 &omap3xxx_l4_core__mmc1,
3455 };
3456
3457 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3458 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3459 };
3460
3461 static struct omap_hwmod omap3xxx_mmc1_hwmod = {
3462 .name = "mmc1",
3463 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
3464 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc1_mpu_irqs),
3465 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
3466 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc1_sdma_reqs),
3467 .opt_clks = omap34xx_mmc1_opt_clks,
3468 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3469 .main_clk = "mmchs1_fck",
3470 .prcm = {
3471 .omap2 = {
3472 .module_offs = CORE_MOD,
3473 .prcm_reg_id = 1,
3474 .module_bit = OMAP3430_EN_MMC1_SHIFT,
3475 .idlest_reg_id = 1,
3476 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3477 },
3478 },
3479 .dev_attr = &mmc1_dev_attr,
3480 .slaves = omap3xxx_mmc1_slaves,
3481 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3482 .class = &omap34xx_mmc_class,
3483 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3484 };
3485
3486 /* MMC/SD/SDIO2 */
3487
3488 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
3489 { .irq = INT_24XX_MMC2_IRQ, },
3490 };
3491
3492 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
3493 { .name = "tx", .dma_req = 47, },
3494 { .name = "rx", .dma_req = 48, },
3495 };
3496
3497 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
3498 { .role = "dbck", .clk = "omap_32k_fck", },
3499 };
3500
3501 static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3502 &omap3xxx_l4_core__mmc2,
3503 };
3504
3505 static struct omap_hwmod omap3xxx_mmc2_hwmod = {
3506 .name = "mmc2",
3507 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
3508 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc2_mpu_irqs),
3509 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
3510 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc2_sdma_reqs),
3511 .opt_clks = omap34xx_mmc2_opt_clks,
3512 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3513 .main_clk = "mmchs2_fck",
3514 .prcm = {
3515 .omap2 = {
3516 .module_offs = CORE_MOD,
3517 .prcm_reg_id = 1,
3518 .module_bit = OMAP3430_EN_MMC2_SHIFT,
3519 .idlest_reg_id = 1,
3520 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3521 },
3522 },
3523 .slaves = omap3xxx_mmc2_slaves,
3524 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3525 .class = &omap34xx_mmc_class,
3526 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3527 };
3528
3529 /* MMC/SD/SDIO3 */
3530
3531 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
3532 { .irq = 94, },
3533 };
3534
3535 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
3536 { .name = "tx", .dma_req = 77, },
3537 { .name = "rx", .dma_req = 78, },
3538 };
3539
3540 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
3541 { .role = "dbck", .clk = "omap_32k_fck", },
3542 };
3543
3544 static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3545 &omap3xxx_l4_core__mmc3,
3546 };
3547
3548 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3549 .name = "mmc3",
3550 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
3551 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc3_mpu_irqs),
3552 .sdma_reqs = omap34xx_mmc3_sdma_reqs,
3553 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc3_sdma_reqs),
3554 .opt_clks = omap34xx_mmc3_opt_clks,
3555 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
3556 .main_clk = "mmchs3_fck",
3557 .prcm = {
3558 .omap2 = {
3559 .prcm_reg_id = 1,
3560 .module_bit = OMAP3430_EN_MMC3_SHIFT,
3561 .idlest_reg_id = 1,
3562 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
3563 },
3564 },
3565 .slaves = omap3xxx_mmc3_slaves,
3566 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc3_slaves),
3567 .class = &omap34xx_mmc_class,
3568 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3569 };
3570
3571 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
3572 &omap3xxx_l3_main_hwmod,
3573 &omap3xxx_l4_core_hwmod,
3574 &omap3xxx_l4_per_hwmod,
3575 &omap3xxx_l4_wkup_hwmod,
3576 &omap3xxx_mmc1_hwmod,
3577 &omap3xxx_mmc2_hwmod,
3578 &omap3xxx_mmc3_hwmod,
3579 &omap3xxx_mpu_hwmod,
3580 &omap3xxx_iva_hwmod,
3581
3582 &omap3xxx_timer1_hwmod,
3583 &omap3xxx_timer2_hwmod,
3584 &omap3xxx_timer3_hwmod,
3585 &omap3xxx_timer4_hwmod,
3586 &omap3xxx_timer5_hwmod,
3587 &omap3xxx_timer6_hwmod,
3588 &omap3xxx_timer7_hwmod,
3589 &omap3xxx_timer8_hwmod,
3590 &omap3xxx_timer9_hwmod,
3591 &omap3xxx_timer10_hwmod,
3592 &omap3xxx_timer11_hwmod,
3593 &omap3xxx_timer12_hwmod,
3594
3595 &omap3xxx_wd_timer2_hwmod,
3596 &omap3xxx_uart1_hwmod,
3597 &omap3xxx_uart2_hwmod,
3598 &omap3xxx_uart3_hwmod,
3599 &omap3xxx_uart4_hwmod,
3600 /* dss class */
3601 &omap3430es1_dss_core_hwmod,
3602 &omap3xxx_dss_core_hwmod,
3603 &omap3xxx_dss_dispc_hwmod,
3604 &omap3xxx_dss_dsi1_hwmod,
3605 &omap3xxx_dss_rfbi_hwmod,
3606 &omap3xxx_dss_venc_hwmod,
3607
3608 /* i2c class */
3609 &omap3xxx_i2c1_hwmod,
3610 &omap3xxx_i2c2_hwmod,
3611 &omap3xxx_i2c3_hwmod,
3612 &omap34xx_sr1_hwmod,
3613 &omap34xx_sr2_hwmod,
3614 &omap36xx_sr1_hwmod,
3615 &omap36xx_sr2_hwmod,
3616
3617
3618 /* gpio class */
3619 &omap3xxx_gpio1_hwmod,
3620 &omap3xxx_gpio2_hwmod,
3621 &omap3xxx_gpio3_hwmod,
3622 &omap3xxx_gpio4_hwmod,
3623 &omap3xxx_gpio5_hwmod,
3624 &omap3xxx_gpio6_hwmod,
3625
3626 /* dma_system class*/
3627 &omap3xxx_dma_system_hwmod,
3628
3629 /* mcbsp class */
3630 &omap3xxx_mcbsp1_hwmod,
3631 &omap3xxx_mcbsp2_hwmod,
3632 &omap3xxx_mcbsp3_hwmod,
3633 &omap3xxx_mcbsp4_hwmod,
3634 &omap3xxx_mcbsp5_hwmod,
3635 &omap3xxx_mcbsp2_sidetone_hwmod,
3636 &omap3xxx_mcbsp3_sidetone_hwmod,
3637
3638 /* mailbox class */
3639 &omap3xxx_mailbox_hwmod,
3640
3641 /* mcspi class */
3642 &omap34xx_mcspi1,
3643 &omap34xx_mcspi2,
3644 &omap34xx_mcspi3,
3645 &omap34xx_mcspi4,
3646
3647 /* usbotg class */
3648 &omap3xxx_usbhsotg_hwmod,
3649
3650 /* usbotg for am35x */
3651 &am35xx_usbhsotg_hwmod,
3652
3653 NULL,
3654 };
3655
3656 int __init omap3xxx_hwmod_init(void)
3657 {
3658 return omap_hwmod_register(omap3xxx_hwmods);
3659 }
Linux kernel - Deliverables
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