2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * The data in this file should be completely autogeneratable from
13 * the TI hardware database or other technical documentation.
15 * XXX these should be marked initdata for multi-OMAP kernels
17 #include <linux/power/smartreflex.h>
19 #include <plat/omap_hwmod.h>
20 #include <mach/irqs.h>
23 #include <plat/serial.h>
24 #include <plat/l3_3xxx.h>
25 #include <plat/l4_3xxx.h>
27 #include <plat/gpio.h>
29 #include <plat/mcbsp.h>
30 #include <plat/mcspi.h>
31 #include <plat/dmtimer.h>
33 #include "omap_hwmod_common_data.h"
34 #include "prm-regbits-34xx.h"
35 #include "cm-regbits-34xx.h"
37 #include <mach/am35xx.h>
40 * OMAP3xxx hardware module integration data
42 * All of the data in this section should be autogeneratable from the
43 * TI hardware database or other technical documentation. Data that
44 * is driver-specific or driver-kernel integration-specific belongs
53 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs
[] = {
54 { .irq
= INT_34XX_L3_DBG_IRQ
},
55 { .irq
= INT_34XX_L3_APP_IRQ
},
59 static struct omap_hwmod omap3xxx_l3_main_hwmod
= {
61 .class = &l3_hwmod_class
,
62 .mpu_irqs
= omap3xxx_l3_main_irqs
,
63 .flags
= HWMOD_NO_IDLEST
,
67 static struct omap_hwmod omap3xxx_l4_core_hwmod
= {
69 .class = &l4_hwmod_class
,
70 .flags
= HWMOD_NO_IDLEST
,
74 static struct omap_hwmod omap3xxx_l4_per_hwmod
= {
76 .class = &l4_hwmod_class
,
77 .flags
= HWMOD_NO_IDLEST
,
81 static struct omap_hwmod omap3xxx_l4_wkup_hwmod
= {
83 .class = &l4_hwmod_class
,
84 .flags
= HWMOD_NO_IDLEST
,
88 static struct omap_hwmod omap3xxx_l4_sec_hwmod
= {
90 .class = &l4_hwmod_class
,
91 .flags
= HWMOD_NO_IDLEST
,
95 static struct omap_hwmod omap3xxx_mpu_hwmod
= {
97 .class = &mpu_hwmod_class
,
98 .main_clk
= "arm_fck",
102 static struct omap_hwmod_rst_info omap3xxx_iva_resets
[] = {
103 { .name
= "logic", .rst_shift
= 0, .st_shift
= 8 },
104 { .name
= "seq0", .rst_shift
= 1, .st_shift
= 9 },
105 { .name
= "seq1", .rst_shift
= 2, .st_shift
= 10 },
108 static struct omap_hwmod omap3xxx_iva_hwmod
= {
110 .class = &iva_hwmod_class
,
111 .clkdm_name
= "iva2_clkdm",
112 .rst_lines
= omap3xxx_iva_resets
,
113 .rst_lines_cnt
= ARRAY_SIZE(omap3xxx_iva_resets
),
114 .main_clk
= "iva2_ck",
117 .module_offs
= OMAP3430_IVA2_MOD
,
119 .module_bit
= OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT
,
121 .idlest_idle_bit
= OMAP3430_ST_IVA2_SHIFT
,
127 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc
= {
131 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_CLOCKACTIVITY
|
132 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
133 SYSC_HAS_EMUFREE
| SYSC_HAS_AUTOIDLE
),
134 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
135 .sysc_fields
= &omap_hwmod_sysc_type1
,
138 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class
= {
140 .sysc
= &omap3xxx_timer_1ms_sysc
,
143 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc
= {
147 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_ENAWAKEUP
|
148 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
),
149 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
150 .sysc_fields
= &omap_hwmod_sysc_type1
,
153 static struct omap_hwmod_class omap3xxx_timer_hwmod_class
= {
155 .sysc
= &omap3xxx_timer_sysc
,
158 /* secure timers dev attribute */
159 static struct omap_timer_capability_dev_attr capability_secure_dev_attr
= {
160 .timer_capability
= OMAP_TIMER_ALWON
| OMAP_TIMER_SECURE
,
163 /* always-on timers dev attribute */
164 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr
= {
165 .timer_capability
= OMAP_TIMER_ALWON
,
168 /* pwm timers dev attribute */
169 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr
= {
170 .timer_capability
= OMAP_TIMER_HAS_PWM
,
174 static struct omap_hwmod omap3xxx_timer1_hwmod
= {
176 .mpu_irqs
= omap2_timer1_mpu_irqs
,
177 .main_clk
= "gpt1_fck",
181 .module_bit
= OMAP3430_EN_GPT1_SHIFT
,
182 .module_offs
= WKUP_MOD
,
184 .idlest_idle_bit
= OMAP3430_ST_GPT1_SHIFT
,
187 .dev_attr
= &capability_alwon_dev_attr
,
188 .class = &omap3xxx_timer_1ms_hwmod_class
,
192 static struct omap_hwmod omap3xxx_timer2_hwmod
= {
194 .mpu_irqs
= omap2_timer2_mpu_irqs
,
195 .main_clk
= "gpt2_fck",
199 .module_bit
= OMAP3430_EN_GPT2_SHIFT
,
200 .module_offs
= OMAP3430_PER_MOD
,
202 .idlest_idle_bit
= OMAP3430_ST_GPT2_SHIFT
,
205 .class = &omap3xxx_timer_1ms_hwmod_class
,
209 static struct omap_hwmod omap3xxx_timer3_hwmod
= {
211 .mpu_irqs
= omap2_timer3_mpu_irqs
,
212 .main_clk
= "gpt3_fck",
216 .module_bit
= OMAP3430_EN_GPT3_SHIFT
,
217 .module_offs
= OMAP3430_PER_MOD
,
219 .idlest_idle_bit
= OMAP3430_ST_GPT3_SHIFT
,
222 .class = &omap3xxx_timer_hwmod_class
,
226 static struct omap_hwmod omap3xxx_timer4_hwmod
= {
228 .mpu_irqs
= omap2_timer4_mpu_irqs
,
229 .main_clk
= "gpt4_fck",
233 .module_bit
= OMAP3430_EN_GPT4_SHIFT
,
234 .module_offs
= OMAP3430_PER_MOD
,
236 .idlest_idle_bit
= OMAP3430_ST_GPT4_SHIFT
,
239 .class = &omap3xxx_timer_hwmod_class
,
243 static struct omap_hwmod omap3xxx_timer5_hwmod
= {
245 .mpu_irqs
= omap2_timer5_mpu_irqs
,
246 .main_clk
= "gpt5_fck",
250 .module_bit
= OMAP3430_EN_GPT5_SHIFT
,
251 .module_offs
= OMAP3430_PER_MOD
,
253 .idlest_idle_bit
= OMAP3430_ST_GPT5_SHIFT
,
256 .class = &omap3xxx_timer_hwmod_class
,
260 static struct omap_hwmod omap3xxx_timer6_hwmod
= {
262 .mpu_irqs
= omap2_timer6_mpu_irqs
,
263 .main_clk
= "gpt6_fck",
267 .module_bit
= OMAP3430_EN_GPT6_SHIFT
,
268 .module_offs
= OMAP3430_PER_MOD
,
270 .idlest_idle_bit
= OMAP3430_ST_GPT6_SHIFT
,
273 .class = &omap3xxx_timer_hwmod_class
,
277 static struct omap_hwmod omap3xxx_timer7_hwmod
= {
279 .mpu_irqs
= omap2_timer7_mpu_irqs
,
280 .main_clk
= "gpt7_fck",
284 .module_bit
= OMAP3430_EN_GPT7_SHIFT
,
285 .module_offs
= OMAP3430_PER_MOD
,
287 .idlest_idle_bit
= OMAP3430_ST_GPT7_SHIFT
,
290 .class = &omap3xxx_timer_hwmod_class
,
294 static struct omap_hwmod omap3xxx_timer8_hwmod
= {
296 .mpu_irqs
= omap2_timer8_mpu_irqs
,
297 .main_clk
= "gpt8_fck",
301 .module_bit
= OMAP3430_EN_GPT8_SHIFT
,
302 .module_offs
= OMAP3430_PER_MOD
,
304 .idlest_idle_bit
= OMAP3430_ST_GPT8_SHIFT
,
307 .dev_attr
= &capability_pwm_dev_attr
,
308 .class = &omap3xxx_timer_hwmod_class
,
312 static struct omap_hwmod omap3xxx_timer9_hwmod
= {
314 .mpu_irqs
= omap2_timer9_mpu_irqs
,
315 .main_clk
= "gpt9_fck",
319 .module_bit
= OMAP3430_EN_GPT9_SHIFT
,
320 .module_offs
= OMAP3430_PER_MOD
,
322 .idlest_idle_bit
= OMAP3430_ST_GPT9_SHIFT
,
325 .dev_attr
= &capability_pwm_dev_attr
,
326 .class = &omap3xxx_timer_hwmod_class
,
330 static struct omap_hwmod omap3xxx_timer10_hwmod
= {
332 .mpu_irqs
= omap2_timer10_mpu_irqs
,
333 .main_clk
= "gpt10_fck",
337 .module_bit
= OMAP3430_EN_GPT10_SHIFT
,
338 .module_offs
= CORE_MOD
,
340 .idlest_idle_bit
= OMAP3430_ST_GPT10_SHIFT
,
343 .dev_attr
= &capability_pwm_dev_attr
,
344 .class = &omap3xxx_timer_1ms_hwmod_class
,
348 static struct omap_hwmod omap3xxx_timer11_hwmod
= {
350 .mpu_irqs
= omap2_timer11_mpu_irqs
,
351 .main_clk
= "gpt11_fck",
355 .module_bit
= OMAP3430_EN_GPT11_SHIFT
,
356 .module_offs
= CORE_MOD
,
358 .idlest_idle_bit
= OMAP3430_ST_GPT11_SHIFT
,
361 .dev_attr
= &capability_pwm_dev_attr
,
362 .class = &omap3xxx_timer_hwmod_class
,
366 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs
[] = {
371 static struct omap_hwmod omap3xxx_timer12_hwmod
= {
373 .mpu_irqs
= omap3xxx_timer12_mpu_irqs
,
374 .main_clk
= "gpt12_fck",
378 .module_bit
= OMAP3430_EN_GPT12_SHIFT
,
379 .module_offs
= WKUP_MOD
,
381 .idlest_idle_bit
= OMAP3430_ST_GPT12_SHIFT
,
384 .dev_attr
= &capability_secure_dev_attr
,
385 .class = &omap3xxx_timer_hwmod_class
,
390 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
394 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc
= {
398 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_EMUFREE
|
399 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
400 SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
401 SYSS_HAS_RESET_STATUS
),
402 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
403 .sysc_fields
= &omap_hwmod_sysc_type1
,
407 static struct omap_hwmod_class_sysconfig i2c_sysc
= {
411 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
412 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
413 SYSC_HAS_AUTOIDLE
| SYSS_HAS_RESET_STATUS
),
414 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
415 .clockact
= CLOCKACT_TEST_ICLK
,
416 .sysc_fields
= &omap_hwmod_sysc_type1
,
419 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class
= {
421 .sysc
= &omap3xxx_wd_timer_sysc
,
422 .pre_shutdown
= &omap2_wd_timer_disable
,
423 .reset
= &omap2_wd_timer_reset
,
426 static struct omap_hwmod omap3xxx_wd_timer2_hwmod
= {
428 .class = &omap3xxx_wd_timer_hwmod_class
,
429 .main_clk
= "wdt2_fck",
433 .module_bit
= OMAP3430_EN_WDT2_SHIFT
,
434 .module_offs
= WKUP_MOD
,
436 .idlest_idle_bit
= OMAP3430_ST_WDT2_SHIFT
,
440 * XXX: Use software supervised mode, HW supervised smartidle seems to
441 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
443 .flags
= HWMOD_SWSUP_SIDLE
,
447 static struct omap_hwmod omap3xxx_uart1_hwmod
= {
449 .mpu_irqs
= omap2_uart1_mpu_irqs
,
450 .sdma_reqs
= omap2_uart1_sdma_reqs
,
451 .main_clk
= "uart1_fck",
454 .module_offs
= CORE_MOD
,
456 .module_bit
= OMAP3430_EN_UART1_SHIFT
,
458 .idlest_idle_bit
= OMAP3430_EN_UART1_SHIFT
,
461 .class = &omap2_uart_class
,
465 static struct omap_hwmod omap3xxx_uart2_hwmod
= {
467 .mpu_irqs
= omap2_uart2_mpu_irqs
,
468 .sdma_reqs
= omap2_uart2_sdma_reqs
,
469 .main_clk
= "uart2_fck",
472 .module_offs
= CORE_MOD
,
474 .module_bit
= OMAP3430_EN_UART2_SHIFT
,
476 .idlest_idle_bit
= OMAP3430_EN_UART2_SHIFT
,
479 .class = &omap2_uart_class
,
483 static struct omap_hwmod omap3xxx_uart3_hwmod
= {
485 .mpu_irqs
= omap2_uart3_mpu_irqs
,
486 .sdma_reqs
= omap2_uart3_sdma_reqs
,
487 .main_clk
= "uart3_fck",
490 .module_offs
= OMAP3430_PER_MOD
,
492 .module_bit
= OMAP3430_EN_UART3_SHIFT
,
494 .idlest_idle_bit
= OMAP3430_EN_UART3_SHIFT
,
497 .class = &omap2_uart_class
,
501 static struct omap_hwmod_irq_info uart4_mpu_irqs
[] = {
502 { .irq
= INT_36XX_UART4_IRQ
, },
506 static struct omap_hwmod_dma_info uart4_sdma_reqs
[] = {
507 { .name
= "rx", .dma_req
= OMAP36XX_DMA_UART4_RX
, },
508 { .name
= "tx", .dma_req
= OMAP36XX_DMA_UART4_TX
, },
512 static struct omap_hwmod omap36xx_uart4_hwmod
= {
514 .mpu_irqs
= uart4_mpu_irqs
,
515 .sdma_reqs
= uart4_sdma_reqs
,
516 .main_clk
= "uart4_fck",
519 .module_offs
= OMAP3430_PER_MOD
,
521 .module_bit
= OMAP3630_EN_UART4_SHIFT
,
523 .idlest_idle_bit
= OMAP3630_EN_UART4_SHIFT
,
526 .class = &omap2_uart_class
,
529 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs
[] = {
530 { .irq
= INT_35XX_UART4_IRQ
, },
534 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs
[] = {
535 { .name
= "rx", .dma_req
= AM35XX_DMA_UART4_RX
, },
536 { .name
= "tx", .dma_req
= AM35XX_DMA_UART4_TX
, },
541 * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
542 * uart2_fck being enabled. So we add uart1_fck as an optional clock,
543 * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET. This really
544 * should not be needed. The functional clock structure of the AM35xx
545 * UART4 is extremely unclear and opaque; it is unclear what the role
546 * of uart1/2_fck is for the UART4. Any clarification from either
547 * empirical testing or the AM3505/3517 hardware designers would be
550 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks
[] = {
551 { .role
= "softreset_uart1_fck", .clk
= "uart1_fck" },
554 static struct omap_hwmod am35xx_uart4_hwmod
= {
556 .mpu_irqs
= am35xx_uart4_mpu_irqs
,
557 .sdma_reqs
= am35xx_uart4_sdma_reqs
,
558 .main_clk
= "uart4_fck",
561 .module_offs
= CORE_MOD
,
563 .module_bit
= AM35XX_EN_UART4_SHIFT
,
565 .idlest_idle_bit
= AM35XX_ST_UART4_SHIFT
,
568 .opt_clks
= am35xx_uart4_opt_clks
,
569 .opt_clks_cnt
= ARRAY_SIZE(am35xx_uart4_opt_clks
),
570 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
571 .class = &omap2_uart_class
,
574 static struct omap_hwmod_class i2c_class
= {
577 .rev
= OMAP_I2C_IP_VERSION_1
,
578 .reset
= &omap_i2c_reset
,
581 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs
[] = {
582 { .name
= "dispc", .dma_req
= 5 },
583 { .name
= "dsi1", .dma_req
= 74 },
588 static struct omap_hwmod_opt_clk dss_opt_clks
[] = {
590 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
591 * driver does not use these clocks.
593 { .role
= "sys_clk", .clk
= "dss2_alwon_fck" },
594 { .role
= "tv_clk", .clk
= "dss_tv_fck" },
595 /* required only on OMAP3430 */
596 { .role
= "tv_dac_clk", .clk
= "dss_96m_fck" },
599 static struct omap_hwmod omap3430es1_dss_core_hwmod
= {
601 .class = &omap2_dss_hwmod_class
,
602 .main_clk
= "dss1_alwon_fck", /* instead of dss_fck */
603 .sdma_reqs
= omap3xxx_dss_sdma_chs
,
607 .module_bit
= OMAP3430_EN_DSS1_SHIFT
,
608 .module_offs
= OMAP3430_DSS_MOD
,
610 .idlest_stdby_bit
= OMAP3430ES1_ST_DSS_SHIFT
,
613 .opt_clks
= dss_opt_clks
,
614 .opt_clks_cnt
= ARRAY_SIZE(dss_opt_clks
),
615 .flags
= HWMOD_NO_IDLEST
| HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
618 static struct omap_hwmod omap3xxx_dss_core_hwmod
= {
620 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
621 .class = &omap2_dss_hwmod_class
,
622 .main_clk
= "dss1_alwon_fck", /* instead of dss_fck */
623 .sdma_reqs
= omap3xxx_dss_sdma_chs
,
627 .module_bit
= OMAP3430_EN_DSS1_SHIFT
,
628 .module_offs
= OMAP3430_DSS_MOD
,
630 .idlest_idle_bit
= OMAP3430ES2_ST_DSS_IDLE_SHIFT
,
631 .idlest_stdby_bit
= OMAP3430ES2_ST_DSS_STDBY_SHIFT
,
634 .opt_clks
= dss_opt_clks
,
635 .opt_clks_cnt
= ARRAY_SIZE(dss_opt_clks
),
643 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc
= {
647 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_MIDLEMODE
|
648 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
|
650 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
651 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
652 .sysc_fields
= &omap_hwmod_sysc_type1
,
655 static struct omap_hwmod_class omap3_dispc_hwmod_class
= {
657 .sysc
= &omap3_dispc_sysc
,
660 static struct omap_hwmod omap3xxx_dss_dispc_hwmod
= {
662 .class = &omap3_dispc_hwmod_class
,
663 .mpu_irqs
= omap2_dispc_irqs
,
664 .main_clk
= "dss1_alwon_fck",
668 .module_bit
= OMAP3430_EN_DSS1_SHIFT
,
669 .module_offs
= OMAP3430_DSS_MOD
,
672 .flags
= HWMOD_NO_IDLEST
,
673 .dev_attr
= &omap2_3_dss_dispc_dev_attr
678 * display serial interface controller
681 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class
= {
685 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs
[] = {
691 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks
[] = {
692 { .role
= "sys_clk", .clk
= "dss2_alwon_fck" },
695 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod
= {
697 .class = &omap3xxx_dsi_hwmod_class
,
698 .mpu_irqs
= omap3xxx_dsi1_irqs
,
699 .main_clk
= "dss1_alwon_fck",
703 .module_bit
= OMAP3430_EN_DSS1_SHIFT
,
704 .module_offs
= OMAP3430_DSS_MOD
,
707 .opt_clks
= dss_dsi1_opt_clks
,
708 .opt_clks_cnt
= ARRAY_SIZE(dss_dsi1_opt_clks
),
709 .flags
= HWMOD_NO_IDLEST
,
712 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks
[] = {
713 { .role
= "ick", .clk
= "dss_ick" },
716 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod
= {
718 .class = &omap2_rfbi_hwmod_class
,
719 .main_clk
= "dss1_alwon_fck",
723 .module_bit
= OMAP3430_EN_DSS1_SHIFT
,
724 .module_offs
= OMAP3430_DSS_MOD
,
727 .opt_clks
= dss_rfbi_opt_clks
,
728 .opt_clks_cnt
= ARRAY_SIZE(dss_rfbi_opt_clks
),
729 .flags
= HWMOD_NO_IDLEST
,
732 static struct omap_hwmod_opt_clk dss_venc_opt_clks
[] = {
733 /* required only on OMAP3430 */
734 { .role
= "tv_dac_clk", .clk
= "dss_96m_fck" },
737 static struct omap_hwmod omap3xxx_dss_venc_hwmod
= {
739 .class = &omap2_venc_hwmod_class
,
740 .main_clk
= "dss_tv_fck",
744 .module_bit
= OMAP3430_EN_DSS1_SHIFT
,
745 .module_offs
= OMAP3430_DSS_MOD
,
748 .opt_clks
= dss_venc_opt_clks
,
749 .opt_clks_cnt
= ARRAY_SIZE(dss_venc_opt_clks
),
750 .flags
= HWMOD_NO_IDLEST
,
754 static struct omap_i2c_dev_attr i2c1_dev_attr
= {
755 .fifo_depth
= 8, /* bytes */
756 .flags
= OMAP_I2C_FLAG_APPLY_ERRATA_I207
|
757 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE
|
758 OMAP_I2C_FLAG_BUS_SHIFT_2
,
761 static struct omap_hwmod omap3xxx_i2c1_hwmod
= {
763 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
764 .mpu_irqs
= omap2_i2c1_mpu_irqs
,
765 .sdma_reqs
= omap2_i2c1_sdma_reqs
,
766 .main_clk
= "i2c1_fck",
769 .module_offs
= CORE_MOD
,
771 .module_bit
= OMAP3430_EN_I2C1_SHIFT
,
773 .idlest_idle_bit
= OMAP3430_ST_I2C1_SHIFT
,
777 .dev_attr
= &i2c1_dev_attr
,
781 static struct omap_i2c_dev_attr i2c2_dev_attr
= {
782 .fifo_depth
= 8, /* bytes */
783 .flags
= OMAP_I2C_FLAG_APPLY_ERRATA_I207
|
784 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE
|
785 OMAP_I2C_FLAG_BUS_SHIFT_2
,
788 static struct omap_hwmod omap3xxx_i2c2_hwmod
= {
790 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
791 .mpu_irqs
= omap2_i2c2_mpu_irqs
,
792 .sdma_reqs
= omap2_i2c2_sdma_reqs
,
793 .main_clk
= "i2c2_fck",
796 .module_offs
= CORE_MOD
,
798 .module_bit
= OMAP3430_EN_I2C2_SHIFT
,
800 .idlest_idle_bit
= OMAP3430_ST_I2C2_SHIFT
,
804 .dev_attr
= &i2c2_dev_attr
,
808 static struct omap_i2c_dev_attr i2c3_dev_attr
= {
809 .fifo_depth
= 64, /* bytes */
810 .flags
= OMAP_I2C_FLAG_APPLY_ERRATA_I207
|
811 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE
|
812 OMAP_I2C_FLAG_BUS_SHIFT_2
,
815 static struct omap_hwmod_irq_info i2c3_mpu_irqs
[] = {
816 { .irq
= INT_34XX_I2C3_IRQ
, },
820 static struct omap_hwmod_dma_info i2c3_sdma_reqs
[] = {
821 { .name
= "tx", .dma_req
= OMAP34XX_DMA_I2C3_TX
},
822 { .name
= "rx", .dma_req
= OMAP34XX_DMA_I2C3_RX
},
826 static struct omap_hwmod omap3xxx_i2c3_hwmod
= {
828 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
829 .mpu_irqs
= i2c3_mpu_irqs
,
830 .sdma_reqs
= i2c3_sdma_reqs
,
831 .main_clk
= "i2c3_fck",
834 .module_offs
= CORE_MOD
,
836 .module_bit
= OMAP3430_EN_I2C3_SHIFT
,
838 .idlest_idle_bit
= OMAP3430_ST_I2C3_SHIFT
,
842 .dev_attr
= &i2c3_dev_attr
,
847 * general purpose io module
850 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc
= {
854 .sysc_flags
= (SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
855 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
|
856 SYSS_HAS_RESET_STATUS
),
857 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
858 .sysc_fields
= &omap_hwmod_sysc_type1
,
861 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class
= {
863 .sysc
= &omap3xxx_gpio_sysc
,
868 static struct omap_gpio_dev_attr gpio_dev_attr
= {
874 static struct omap_hwmod_opt_clk gpio1_opt_clks
[] = {
875 { .role
= "dbclk", .clk
= "gpio1_dbck", },
878 static struct omap_hwmod omap3xxx_gpio1_hwmod
= {
880 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
881 .mpu_irqs
= omap2_gpio1_irqs
,
882 .main_clk
= "gpio1_ick",
883 .opt_clks
= gpio1_opt_clks
,
884 .opt_clks_cnt
= ARRAY_SIZE(gpio1_opt_clks
),
888 .module_bit
= OMAP3430_EN_GPIO1_SHIFT
,
889 .module_offs
= WKUP_MOD
,
891 .idlest_idle_bit
= OMAP3430_ST_GPIO1_SHIFT
,
894 .class = &omap3xxx_gpio_hwmod_class
,
895 .dev_attr
= &gpio_dev_attr
,
899 static struct omap_hwmod_opt_clk gpio2_opt_clks
[] = {
900 { .role
= "dbclk", .clk
= "gpio2_dbck", },
903 static struct omap_hwmod omap3xxx_gpio2_hwmod
= {
905 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
906 .mpu_irqs
= omap2_gpio2_irqs
,
907 .main_clk
= "gpio2_ick",
908 .opt_clks
= gpio2_opt_clks
,
909 .opt_clks_cnt
= ARRAY_SIZE(gpio2_opt_clks
),
913 .module_bit
= OMAP3430_EN_GPIO2_SHIFT
,
914 .module_offs
= OMAP3430_PER_MOD
,
916 .idlest_idle_bit
= OMAP3430_ST_GPIO2_SHIFT
,
919 .class = &omap3xxx_gpio_hwmod_class
,
920 .dev_attr
= &gpio_dev_attr
,
924 static struct omap_hwmod_opt_clk gpio3_opt_clks
[] = {
925 { .role
= "dbclk", .clk
= "gpio3_dbck", },
928 static struct omap_hwmod omap3xxx_gpio3_hwmod
= {
930 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
931 .mpu_irqs
= omap2_gpio3_irqs
,
932 .main_clk
= "gpio3_ick",
933 .opt_clks
= gpio3_opt_clks
,
934 .opt_clks_cnt
= ARRAY_SIZE(gpio3_opt_clks
),
938 .module_bit
= OMAP3430_EN_GPIO3_SHIFT
,
939 .module_offs
= OMAP3430_PER_MOD
,
941 .idlest_idle_bit
= OMAP3430_ST_GPIO3_SHIFT
,
944 .class = &omap3xxx_gpio_hwmod_class
,
945 .dev_attr
= &gpio_dev_attr
,
949 static struct omap_hwmod_opt_clk gpio4_opt_clks
[] = {
950 { .role
= "dbclk", .clk
= "gpio4_dbck", },
953 static struct omap_hwmod omap3xxx_gpio4_hwmod
= {
955 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
956 .mpu_irqs
= omap2_gpio4_irqs
,
957 .main_clk
= "gpio4_ick",
958 .opt_clks
= gpio4_opt_clks
,
959 .opt_clks_cnt
= ARRAY_SIZE(gpio4_opt_clks
),
963 .module_bit
= OMAP3430_EN_GPIO4_SHIFT
,
964 .module_offs
= OMAP3430_PER_MOD
,
966 .idlest_idle_bit
= OMAP3430_ST_GPIO4_SHIFT
,
969 .class = &omap3xxx_gpio_hwmod_class
,
970 .dev_attr
= &gpio_dev_attr
,
974 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs
[] = {
975 { .irq
= 33 }, /* INT_34XX_GPIO_BANK5 */
979 static struct omap_hwmod_opt_clk gpio5_opt_clks
[] = {
980 { .role
= "dbclk", .clk
= "gpio5_dbck", },
983 static struct omap_hwmod omap3xxx_gpio5_hwmod
= {
985 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
986 .mpu_irqs
= omap3xxx_gpio5_irqs
,
987 .main_clk
= "gpio5_ick",
988 .opt_clks
= gpio5_opt_clks
,
989 .opt_clks_cnt
= ARRAY_SIZE(gpio5_opt_clks
),
993 .module_bit
= OMAP3430_EN_GPIO5_SHIFT
,
994 .module_offs
= OMAP3430_PER_MOD
,
996 .idlest_idle_bit
= OMAP3430_ST_GPIO5_SHIFT
,
999 .class = &omap3xxx_gpio_hwmod_class
,
1000 .dev_attr
= &gpio_dev_attr
,
1004 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs
[] = {
1005 { .irq
= 34 }, /* INT_34XX_GPIO_BANK6 */
1009 static struct omap_hwmod_opt_clk gpio6_opt_clks
[] = {
1010 { .role
= "dbclk", .clk
= "gpio6_dbck", },
1013 static struct omap_hwmod omap3xxx_gpio6_hwmod
= {
1015 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1016 .mpu_irqs
= omap3xxx_gpio6_irqs
,
1017 .main_clk
= "gpio6_ick",
1018 .opt_clks
= gpio6_opt_clks
,
1019 .opt_clks_cnt
= ARRAY_SIZE(gpio6_opt_clks
),
1023 .module_bit
= OMAP3430_EN_GPIO6_SHIFT
,
1024 .module_offs
= OMAP3430_PER_MOD
,
1026 .idlest_idle_bit
= OMAP3430_ST_GPIO6_SHIFT
,
1029 .class = &omap3xxx_gpio_hwmod_class
,
1030 .dev_attr
= &gpio_dev_attr
,
1033 /* dma attributes */
1034 static struct omap_dma_dev_attr dma_dev_attr
= {
1035 .dev_caps
= RESERVE_CHANNEL
| DMA_LINKED_LCH
| GLOBAL_PRIORITY
|
1036 IS_CSSA_32
| IS_CDSA_32
| IS_RW_PRIORITY
,
1040 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc
= {
1042 .sysc_offs
= 0x002c,
1043 .syss_offs
= 0x0028,
1044 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
1045 SYSC_HAS_MIDLEMODE
| SYSC_HAS_CLOCKACTIVITY
|
1046 SYSC_HAS_EMUFREE
| SYSC_HAS_AUTOIDLE
|
1047 SYSS_HAS_RESET_STATUS
),
1048 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1049 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
1050 .sysc_fields
= &omap_hwmod_sysc_type1
,
1053 static struct omap_hwmod_class omap3xxx_dma_hwmod_class
= {
1055 .sysc
= &omap3xxx_dma_sysc
,
1059 static struct omap_hwmod omap3xxx_dma_system_hwmod
= {
1061 .class = &omap3xxx_dma_hwmod_class
,
1062 .mpu_irqs
= omap2_dma_system_irqs
,
1063 .main_clk
= "core_l3_ick",
1066 .module_offs
= CORE_MOD
,
1068 .module_bit
= OMAP3430_ST_SDMA_SHIFT
,
1070 .idlest_idle_bit
= OMAP3430_ST_SDMA_SHIFT
,
1073 .dev_attr
= &dma_dev_attr
,
1074 .flags
= HWMOD_NO_IDLEST
,
1079 * multi channel buffered serial port controller
1082 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc
= {
1083 .sysc_offs
= 0x008c,
1084 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_ENAWAKEUP
|
1085 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1086 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1087 .sysc_fields
= &omap_hwmod_sysc_type1
,
1091 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class
= {
1093 .sysc
= &omap3xxx_mcbsp_sysc
,
1094 .rev
= MCBSP_CONFIG_TYPE3
,
1097 /* McBSP functional clock mapping */
1098 static struct omap_hwmod_opt_clk mcbsp15_opt_clks
[] = {
1099 { .role
= "pad_fck", .clk
= "mcbsp_clks" },
1100 { .role
= "prcm_fck", .clk
= "core_96m_fck" },
1103 static struct omap_hwmod_opt_clk mcbsp234_opt_clks
[] = {
1104 { .role
= "pad_fck", .clk
= "mcbsp_clks" },
1105 { .role
= "prcm_fck", .clk
= "per_96m_fck" },
1109 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs
[] = {
1110 { .name
= "common", .irq
= 16 },
1111 { .name
= "tx", .irq
= 59 },
1112 { .name
= "rx", .irq
= 60 },
1116 static struct omap_hwmod omap3xxx_mcbsp1_hwmod
= {
1118 .class = &omap3xxx_mcbsp_hwmod_class
,
1119 .mpu_irqs
= omap3xxx_mcbsp1_irqs
,
1120 .sdma_reqs
= omap2_mcbsp1_sdma_reqs
,
1121 .main_clk
= "mcbsp1_fck",
1125 .module_bit
= OMAP3430_EN_MCBSP1_SHIFT
,
1126 .module_offs
= CORE_MOD
,
1128 .idlest_idle_bit
= OMAP3430_ST_MCBSP1_SHIFT
,
1131 .opt_clks
= mcbsp15_opt_clks
,
1132 .opt_clks_cnt
= ARRAY_SIZE(mcbsp15_opt_clks
),
1136 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs
[] = {
1137 { .name
= "common", .irq
= 17 },
1138 { .name
= "tx", .irq
= 62 },
1139 { .name
= "rx", .irq
= 63 },
1143 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr
= {
1144 .sidetone
= "mcbsp2_sidetone",
1147 static struct omap_hwmod omap3xxx_mcbsp2_hwmod
= {
1149 .class = &omap3xxx_mcbsp_hwmod_class
,
1150 .mpu_irqs
= omap3xxx_mcbsp2_irqs
,
1151 .sdma_reqs
= omap2_mcbsp2_sdma_reqs
,
1152 .main_clk
= "mcbsp2_fck",
1156 .module_bit
= OMAP3430_EN_MCBSP2_SHIFT
,
1157 .module_offs
= OMAP3430_PER_MOD
,
1159 .idlest_idle_bit
= OMAP3430_ST_MCBSP2_SHIFT
,
1162 .opt_clks
= mcbsp234_opt_clks
,
1163 .opt_clks_cnt
= ARRAY_SIZE(mcbsp234_opt_clks
),
1164 .dev_attr
= &omap34xx_mcbsp2_dev_attr
,
1168 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs
[] = {
1169 { .name
= "common", .irq
= 22 },
1170 { .name
= "tx", .irq
= 89 },
1171 { .name
= "rx", .irq
= 90 },
1175 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr
= {
1176 .sidetone
= "mcbsp3_sidetone",
1179 static struct omap_hwmod omap3xxx_mcbsp3_hwmod
= {
1181 .class = &omap3xxx_mcbsp_hwmod_class
,
1182 .mpu_irqs
= omap3xxx_mcbsp3_irqs
,
1183 .sdma_reqs
= omap2_mcbsp3_sdma_reqs
,
1184 .main_clk
= "mcbsp3_fck",
1188 .module_bit
= OMAP3430_EN_MCBSP3_SHIFT
,
1189 .module_offs
= OMAP3430_PER_MOD
,
1191 .idlest_idle_bit
= OMAP3430_ST_MCBSP3_SHIFT
,
1194 .opt_clks
= mcbsp234_opt_clks
,
1195 .opt_clks_cnt
= ARRAY_SIZE(mcbsp234_opt_clks
),
1196 .dev_attr
= &omap34xx_mcbsp3_dev_attr
,
1200 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs
[] = {
1201 { .name
= "common", .irq
= 23 },
1202 { .name
= "tx", .irq
= 54 },
1203 { .name
= "rx", .irq
= 55 },
1207 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs
[] = {
1208 { .name
= "rx", .dma_req
= 20 },
1209 { .name
= "tx", .dma_req
= 19 },
1213 static struct omap_hwmod omap3xxx_mcbsp4_hwmod
= {
1215 .class = &omap3xxx_mcbsp_hwmod_class
,
1216 .mpu_irqs
= omap3xxx_mcbsp4_irqs
,
1217 .sdma_reqs
= omap3xxx_mcbsp4_sdma_chs
,
1218 .main_clk
= "mcbsp4_fck",
1222 .module_bit
= OMAP3430_EN_MCBSP4_SHIFT
,
1223 .module_offs
= OMAP3430_PER_MOD
,
1225 .idlest_idle_bit
= OMAP3430_ST_MCBSP4_SHIFT
,
1228 .opt_clks
= mcbsp234_opt_clks
,
1229 .opt_clks_cnt
= ARRAY_SIZE(mcbsp234_opt_clks
),
1233 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs
[] = {
1234 { .name
= "common", .irq
= 27 },
1235 { .name
= "tx", .irq
= 81 },
1236 { .name
= "rx", .irq
= 82 },
1240 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs
[] = {
1241 { .name
= "rx", .dma_req
= 22 },
1242 { .name
= "tx", .dma_req
= 21 },
1246 static struct omap_hwmod omap3xxx_mcbsp5_hwmod
= {
1248 .class = &omap3xxx_mcbsp_hwmod_class
,
1249 .mpu_irqs
= omap3xxx_mcbsp5_irqs
,
1250 .sdma_reqs
= omap3xxx_mcbsp5_sdma_chs
,
1251 .main_clk
= "mcbsp5_fck",
1255 .module_bit
= OMAP3430_EN_MCBSP5_SHIFT
,
1256 .module_offs
= CORE_MOD
,
1258 .idlest_idle_bit
= OMAP3430_ST_MCBSP5_SHIFT
,
1261 .opt_clks
= mcbsp15_opt_clks
,
1262 .opt_clks_cnt
= ARRAY_SIZE(mcbsp15_opt_clks
),
1265 /* 'mcbsp sidetone' class */
1266 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc
= {
1267 .sysc_offs
= 0x0010,
1268 .sysc_flags
= SYSC_HAS_AUTOIDLE
,
1269 .sysc_fields
= &omap_hwmod_sysc_type1
,
1272 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class
= {
1273 .name
= "mcbsp_sidetone",
1274 .sysc
= &omap3xxx_mcbsp_sidetone_sysc
,
1277 /* mcbsp2_sidetone */
1278 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs
[] = {
1279 { .name
= "irq", .irq
= 4 },
1283 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod
= {
1284 .name
= "mcbsp2_sidetone",
1285 .class = &omap3xxx_mcbsp_sidetone_hwmod_class
,
1286 .mpu_irqs
= omap3xxx_mcbsp2_sidetone_irqs
,
1287 .main_clk
= "mcbsp2_fck",
1291 .module_bit
= OMAP3430_EN_MCBSP2_SHIFT
,
1292 .module_offs
= OMAP3430_PER_MOD
,
1294 .idlest_idle_bit
= OMAP3430_ST_MCBSP2_SHIFT
,
1299 /* mcbsp3_sidetone */
1300 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs
[] = {
1301 { .name
= "irq", .irq
= 5 },
1305 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod
= {
1306 .name
= "mcbsp3_sidetone",
1307 .class = &omap3xxx_mcbsp_sidetone_hwmod_class
,
1308 .mpu_irqs
= omap3xxx_mcbsp3_sidetone_irqs
,
1309 .main_clk
= "mcbsp3_fck",
1313 .module_bit
= OMAP3430_EN_MCBSP3_SHIFT
,
1314 .module_offs
= OMAP3430_PER_MOD
,
1316 .idlest_idle_bit
= OMAP3430_ST_MCBSP3_SHIFT
,
1322 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields
= {
1326 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc
= {
1328 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_NO_CACHE
),
1329 .clockact
= CLOCKACT_TEST_ICLK
,
1330 .sysc_fields
= &omap34xx_sr_sysc_fields
,
1333 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class
= {
1334 .name
= "smartreflex",
1335 .sysc
= &omap34xx_sr_sysc
,
1339 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields
= {
1344 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc
= {
1346 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1347 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_ENAWAKEUP
|
1349 .sysc_fields
= &omap36xx_sr_sysc_fields
,
1352 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class
= {
1353 .name
= "smartreflex",
1354 .sysc
= &omap36xx_sr_sysc
,
1359 static struct omap_smartreflex_dev_attr sr1_dev_attr
= {
1360 .sensor_voltdm_name
= "mpu_iva",
1363 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs
[] = {
1368 static struct omap_hwmod omap34xx_sr1_hwmod
= {
1369 .name
= "smartreflex_mpu_iva",
1370 .class = &omap34xx_smartreflex_hwmod_class
,
1371 .main_clk
= "sr1_fck",
1375 .module_bit
= OMAP3430_EN_SR1_SHIFT
,
1376 .module_offs
= WKUP_MOD
,
1378 .idlest_idle_bit
= OMAP3430_EN_SR1_SHIFT
,
1381 .dev_attr
= &sr1_dev_attr
,
1382 .mpu_irqs
= omap3_smartreflex_mpu_irqs
,
1383 .flags
= HWMOD_SET_DEFAULT_CLOCKACT
,
1386 static struct omap_hwmod omap36xx_sr1_hwmod
= {
1387 .name
= "smartreflex_mpu_iva",
1388 .class = &omap36xx_smartreflex_hwmod_class
,
1389 .main_clk
= "sr1_fck",
1393 .module_bit
= OMAP3430_EN_SR1_SHIFT
,
1394 .module_offs
= WKUP_MOD
,
1396 .idlest_idle_bit
= OMAP3430_EN_SR1_SHIFT
,
1399 .dev_attr
= &sr1_dev_attr
,
1400 .mpu_irqs
= omap3_smartreflex_mpu_irqs
,
1404 static struct omap_smartreflex_dev_attr sr2_dev_attr
= {
1405 .sensor_voltdm_name
= "core",
1408 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs
[] = {
1413 static struct omap_hwmod omap34xx_sr2_hwmod
= {
1414 .name
= "smartreflex_core",
1415 .class = &omap34xx_smartreflex_hwmod_class
,
1416 .main_clk
= "sr2_fck",
1420 .module_bit
= OMAP3430_EN_SR2_SHIFT
,
1421 .module_offs
= WKUP_MOD
,
1423 .idlest_idle_bit
= OMAP3430_EN_SR2_SHIFT
,
1426 .dev_attr
= &sr2_dev_attr
,
1427 .mpu_irqs
= omap3_smartreflex_core_irqs
,
1428 .flags
= HWMOD_SET_DEFAULT_CLOCKACT
,
1431 static struct omap_hwmod omap36xx_sr2_hwmod
= {
1432 .name
= "smartreflex_core",
1433 .class = &omap36xx_smartreflex_hwmod_class
,
1434 .main_clk
= "sr2_fck",
1438 .module_bit
= OMAP3430_EN_SR2_SHIFT
,
1439 .module_offs
= WKUP_MOD
,
1441 .idlest_idle_bit
= OMAP3430_EN_SR2_SHIFT
,
1444 .dev_attr
= &sr2_dev_attr
,
1445 .mpu_irqs
= omap3_smartreflex_core_irqs
,
1450 * mailbox module allowing communication between the on-chip processors
1451 * using a queued mailbox-interrupt mechanism.
1454 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc
= {
1458 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
1459 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
),
1460 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1461 .sysc_fields
= &omap_hwmod_sysc_type1
,
1464 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class
= {
1466 .sysc
= &omap3xxx_mailbox_sysc
,
1469 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs
[] = {
1474 static struct omap_hwmod omap3xxx_mailbox_hwmod
= {
1476 .class = &omap3xxx_mailbox_hwmod_class
,
1477 .mpu_irqs
= omap3xxx_mailbox_irqs
,
1478 .main_clk
= "mailboxes_ick",
1482 .module_bit
= OMAP3430_EN_MAILBOXES_SHIFT
,
1483 .module_offs
= CORE_MOD
,
1485 .idlest_idle_bit
= OMAP3430_ST_MAILBOXES_SHIFT
,
1492 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1496 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc
= {
1498 .sysc_offs
= 0x0010,
1499 .syss_offs
= 0x0014,
1500 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
1501 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
1502 SYSC_HAS_AUTOIDLE
| SYSS_HAS_RESET_STATUS
),
1503 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1504 .sysc_fields
= &omap_hwmod_sysc_type1
,
1507 static struct omap_hwmod_class omap34xx_mcspi_class
= {
1509 .sysc
= &omap34xx_mcspi_sysc
,
1510 .rev
= OMAP3_MCSPI_REV
,
1514 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr
= {
1515 .num_chipselect
= 4,
1518 static struct omap_hwmod omap34xx_mcspi1
= {
1520 .mpu_irqs
= omap2_mcspi1_mpu_irqs
,
1521 .sdma_reqs
= omap2_mcspi1_sdma_reqs
,
1522 .main_clk
= "mcspi1_fck",
1525 .module_offs
= CORE_MOD
,
1527 .module_bit
= OMAP3430_EN_MCSPI1_SHIFT
,
1529 .idlest_idle_bit
= OMAP3430_ST_MCSPI1_SHIFT
,
1532 .class = &omap34xx_mcspi_class
,
1533 .dev_attr
= &omap_mcspi1_dev_attr
,
1537 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr
= {
1538 .num_chipselect
= 2,
1541 static struct omap_hwmod omap34xx_mcspi2
= {
1543 .mpu_irqs
= omap2_mcspi2_mpu_irqs
,
1544 .sdma_reqs
= omap2_mcspi2_sdma_reqs
,
1545 .main_clk
= "mcspi2_fck",
1548 .module_offs
= CORE_MOD
,
1550 .module_bit
= OMAP3430_EN_MCSPI2_SHIFT
,
1552 .idlest_idle_bit
= OMAP3430_ST_MCSPI2_SHIFT
,
1555 .class = &omap34xx_mcspi_class
,
1556 .dev_attr
= &omap_mcspi2_dev_attr
,
1560 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs
[] = {
1561 { .name
= "irq", .irq
= 91 }, /* 91 */
1565 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs
[] = {
1566 { .name
= "tx0", .dma_req
= 15 },
1567 { .name
= "rx0", .dma_req
= 16 },
1568 { .name
= "tx1", .dma_req
= 23 },
1569 { .name
= "rx1", .dma_req
= 24 },
1573 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr
= {
1574 .num_chipselect
= 2,
1577 static struct omap_hwmod omap34xx_mcspi3
= {
1579 .mpu_irqs
= omap34xx_mcspi3_mpu_irqs
,
1580 .sdma_reqs
= omap34xx_mcspi3_sdma_reqs
,
1581 .main_clk
= "mcspi3_fck",
1584 .module_offs
= CORE_MOD
,
1586 .module_bit
= OMAP3430_EN_MCSPI3_SHIFT
,
1588 .idlest_idle_bit
= OMAP3430_ST_MCSPI3_SHIFT
,
1591 .class = &omap34xx_mcspi_class
,
1592 .dev_attr
= &omap_mcspi3_dev_attr
,
1596 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs
[] = {
1597 { .name
= "irq", .irq
= INT_34XX_SPI4_IRQ
}, /* 48 */
1601 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs
[] = {
1602 { .name
= "tx0", .dma_req
= 70 }, /* DMA_SPI4_TX0 */
1603 { .name
= "rx0", .dma_req
= 71 }, /* DMA_SPI4_RX0 */
1607 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr
= {
1608 .num_chipselect
= 1,
1611 static struct omap_hwmod omap34xx_mcspi4
= {
1613 .mpu_irqs
= omap34xx_mcspi4_mpu_irqs
,
1614 .sdma_reqs
= omap34xx_mcspi4_sdma_reqs
,
1615 .main_clk
= "mcspi4_fck",
1618 .module_offs
= CORE_MOD
,
1620 .module_bit
= OMAP3430_EN_MCSPI4_SHIFT
,
1622 .idlest_idle_bit
= OMAP3430_ST_MCSPI4_SHIFT
,
1625 .class = &omap34xx_mcspi_class
,
1626 .dev_attr
= &omap_mcspi4_dev_attr
,
1630 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc
= {
1632 .sysc_offs
= 0x0404,
1633 .syss_offs
= 0x0408,
1634 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_MIDLEMODE
|
1635 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
1637 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1638 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
1639 .sysc_fields
= &omap_hwmod_sysc_type1
,
1642 static struct omap_hwmod_class usbotg_class
= {
1644 .sysc
= &omap3xxx_usbhsotg_sysc
,
1648 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs
[] = {
1650 { .name
= "mc", .irq
= 92 },
1651 { .name
= "dma", .irq
= 93 },
1655 static struct omap_hwmod omap3xxx_usbhsotg_hwmod
= {
1656 .name
= "usb_otg_hs",
1657 .mpu_irqs
= omap3xxx_usbhsotg_mpu_irqs
,
1658 .main_clk
= "hsotgusb_ick",
1662 .module_bit
= OMAP3430_EN_HSOTGUSB_SHIFT
,
1663 .module_offs
= CORE_MOD
,
1665 .idlest_idle_bit
= OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT
,
1666 .idlest_stdby_bit
= OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
1669 .class = &usbotg_class
,
1672 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
1673 * broken when autoidle is enabled
1674 * workaround is to disable the autoidle bit at module level.
1676 .flags
= HWMOD_NO_OCP_AUTOIDLE
| HWMOD_SWSUP_SIDLE
1677 | HWMOD_SWSUP_MSTANDBY
,
1681 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs
[] = {
1682 { .name
= "mc", .irq
= 71 },
1686 static struct omap_hwmod_class am35xx_usbotg_class
= {
1687 .name
= "am35xx_usbotg",
1690 static struct omap_hwmod am35xx_usbhsotg_hwmod
= {
1691 .name
= "am35x_otg_hs",
1692 .mpu_irqs
= am35xx_usbhsotg_mpu_irqs
,
1693 .main_clk
= "hsotgusb_fck",
1694 .class = &am35xx_usbotg_class
,
1695 .flags
= HWMOD_NO_IDLEST
,
1698 /* MMC/SD/SDIO common */
1699 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc
= {
1703 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
1704 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
1705 SYSC_HAS_AUTOIDLE
| SYSS_HAS_RESET_STATUS
),
1706 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1707 .sysc_fields
= &omap_hwmod_sysc_type1
,
1710 static struct omap_hwmod_class omap34xx_mmc_class
= {
1712 .sysc
= &omap34xx_mmc_sysc
,
1717 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs
[] = {
1722 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs
[] = {
1723 { .name
= "tx", .dma_req
= 61, },
1724 { .name
= "rx", .dma_req
= 62, },
1728 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks
[] = {
1729 { .role
= "dbck", .clk
= "omap_32k_fck", },
1732 static struct omap_mmc_dev_attr mmc1_dev_attr
= {
1733 .flags
= OMAP_HSMMC_SUPPORTS_DUAL_VOLT
,
1736 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1737 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr
= {
1738 .flags
= (OMAP_HSMMC_SUPPORTS_DUAL_VOLT
|
1739 OMAP_HSMMC_BROKEN_MULTIBLOCK_READ
),
1742 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod
= {
1744 .mpu_irqs
= omap34xx_mmc1_mpu_irqs
,
1745 .sdma_reqs
= omap34xx_mmc1_sdma_reqs
,
1746 .opt_clks
= omap34xx_mmc1_opt_clks
,
1747 .opt_clks_cnt
= ARRAY_SIZE(omap34xx_mmc1_opt_clks
),
1748 .main_clk
= "mmchs1_fck",
1751 .module_offs
= CORE_MOD
,
1753 .module_bit
= OMAP3430_EN_MMC1_SHIFT
,
1755 .idlest_idle_bit
= OMAP3430_ST_MMC1_SHIFT
,
1758 .dev_attr
= &mmc1_pre_es3_dev_attr
,
1759 .class = &omap34xx_mmc_class
,
1762 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod
= {
1764 .mpu_irqs
= omap34xx_mmc1_mpu_irqs
,
1765 .sdma_reqs
= omap34xx_mmc1_sdma_reqs
,
1766 .opt_clks
= omap34xx_mmc1_opt_clks
,
1767 .opt_clks_cnt
= ARRAY_SIZE(omap34xx_mmc1_opt_clks
),
1768 .main_clk
= "mmchs1_fck",
1771 .module_offs
= CORE_MOD
,
1773 .module_bit
= OMAP3430_EN_MMC1_SHIFT
,
1775 .idlest_idle_bit
= OMAP3430_ST_MMC1_SHIFT
,
1778 .dev_attr
= &mmc1_dev_attr
,
1779 .class = &omap34xx_mmc_class
,
1784 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs
[] = {
1785 { .irq
= INT_24XX_MMC2_IRQ
, },
1789 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs
[] = {
1790 { .name
= "tx", .dma_req
= 47, },
1791 { .name
= "rx", .dma_req
= 48, },
1795 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks
[] = {
1796 { .role
= "dbck", .clk
= "omap_32k_fck", },
1799 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1800 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr
= {
1801 .flags
= OMAP_HSMMC_BROKEN_MULTIBLOCK_READ
,
1804 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod
= {
1806 .mpu_irqs
= omap34xx_mmc2_mpu_irqs
,
1807 .sdma_reqs
= omap34xx_mmc2_sdma_reqs
,
1808 .opt_clks
= omap34xx_mmc2_opt_clks
,
1809 .opt_clks_cnt
= ARRAY_SIZE(omap34xx_mmc2_opt_clks
),
1810 .main_clk
= "mmchs2_fck",
1813 .module_offs
= CORE_MOD
,
1815 .module_bit
= OMAP3430_EN_MMC2_SHIFT
,
1817 .idlest_idle_bit
= OMAP3430_ST_MMC2_SHIFT
,
1820 .dev_attr
= &mmc2_pre_es3_dev_attr
,
1821 .class = &omap34xx_mmc_class
,
1824 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod
= {
1826 .mpu_irqs
= omap34xx_mmc2_mpu_irqs
,
1827 .sdma_reqs
= omap34xx_mmc2_sdma_reqs
,
1828 .opt_clks
= omap34xx_mmc2_opt_clks
,
1829 .opt_clks_cnt
= ARRAY_SIZE(omap34xx_mmc2_opt_clks
),
1830 .main_clk
= "mmchs2_fck",
1833 .module_offs
= CORE_MOD
,
1835 .module_bit
= OMAP3430_EN_MMC2_SHIFT
,
1837 .idlest_idle_bit
= OMAP3430_ST_MMC2_SHIFT
,
1840 .class = &omap34xx_mmc_class
,
1845 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs
[] = {
1850 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs
[] = {
1851 { .name
= "tx", .dma_req
= 77, },
1852 { .name
= "rx", .dma_req
= 78, },
1856 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks
[] = {
1857 { .role
= "dbck", .clk
= "omap_32k_fck", },
1860 static struct omap_hwmod omap3xxx_mmc3_hwmod
= {
1862 .mpu_irqs
= omap34xx_mmc3_mpu_irqs
,
1863 .sdma_reqs
= omap34xx_mmc3_sdma_reqs
,
1864 .opt_clks
= omap34xx_mmc3_opt_clks
,
1865 .opt_clks_cnt
= ARRAY_SIZE(omap34xx_mmc3_opt_clks
),
1866 .main_clk
= "mmchs3_fck",
1870 .module_bit
= OMAP3430_EN_MMC3_SHIFT
,
1872 .idlest_idle_bit
= OMAP3430_ST_MMC3_SHIFT
,
1875 .class = &omap34xx_mmc_class
,
1879 * 'usb_host_hs' class
1880 * high-speed multi-port usb host controller
1883 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc
= {
1885 .sysc_offs
= 0x0010,
1886 .syss_offs
= 0x0014,
1887 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_CLOCKACTIVITY
|
1888 SYSC_HAS_SIDLEMODE
| SYSC_HAS_ENAWAKEUP
|
1889 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
),
1890 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1891 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
1892 .sysc_fields
= &omap_hwmod_sysc_type1
,
1895 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class
= {
1896 .name
= "usb_host_hs",
1897 .sysc
= &omap3xxx_usb_host_hs_sysc
,
1900 static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks
[] = {
1901 { .role
= "ehci_logic_fck", .clk
= "usbhost_120m_fck", },
1904 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs
[] = {
1905 { .name
= "ohci-irq", .irq
= 76 },
1906 { .name
= "ehci-irq", .irq
= 77 },
1910 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod
= {
1911 .name
= "usb_host_hs",
1912 .class = &omap3xxx_usb_host_hs_hwmod_class
,
1913 .clkdm_name
= "l3_init_clkdm",
1914 .mpu_irqs
= omap3xxx_usb_host_hs_irqs
,
1915 .main_clk
= "usbhost_48m_fck",
1918 .module_offs
= OMAP3430ES2_USBHOST_MOD
,
1920 .module_bit
= OMAP3430ES2_EN_USBHOST1_SHIFT
,
1922 .idlest_idle_bit
= OMAP3430ES2_ST_USBHOST_IDLE_SHIFT
,
1923 .idlest_stdby_bit
= OMAP3430ES2_ST_USBHOST_STDBY_SHIFT
,
1926 .opt_clks
= omap3xxx_usb_host_hs_opt_clks
,
1927 .opt_clks_cnt
= ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks
),
1930 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1934 * In the following configuration :
1935 * - USBHOST module is set to smart-idle mode
1936 * - PRCM asserts idle_req to the USBHOST module ( This typically
1937 * happens when the system is going to a low power mode : all ports
1938 * have been suspended, the master part of the USBHOST module has
1939 * entered the standby state, and SW has cut the functional clocks)
1940 * - an USBHOST interrupt occurs before the module is able to answer
1941 * idle_ack, typically a remote wakeup IRQ.
1942 * Then the USB HOST module will enter a deadlock situation where it
1943 * is no more accessible nor functional.
1946 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1950 * Errata: USB host EHCI may stall when entering smart-standby mode
1954 * When the USBHOST module is set to smart-standby mode, and when it is
1955 * ready to enter the standby state (i.e. all ports are suspended and
1956 * all attached devices are in suspend mode), then it can wrongly assert
1957 * the Mstandby signal too early while there are still some residual OCP
1958 * transactions ongoing. If this condition occurs, the internal state
1959 * machine may go to an undefined state and the USB link may be stuck
1960 * upon the next resume.
1963 * Don't use smart standby; use only force standby,
1964 * hence HWMOD_SWSUP_MSTANDBY
1968 * During system boot; If the hwmod framework resets the module
1969 * the module will have smart idle settings; which can lead to deadlock
1970 * (above Errata Id:i660); so, dont reset the module during boot;
1971 * Use HWMOD_INIT_NO_RESET.
1974 .flags
= HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
|
1975 HWMOD_INIT_NO_RESET
,
1979 * 'usb_tll_hs' class
1980 * usb_tll_hs module is the adapter on the usb_host_hs ports
1982 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc
= {
1984 .sysc_offs
= 0x0010,
1985 .syss_offs
= 0x0014,
1986 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
1987 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
1989 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1990 .sysc_fields
= &omap_hwmod_sysc_type1
,
1993 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class
= {
1994 .name
= "usb_tll_hs",
1995 .sysc
= &omap3xxx_usb_tll_hs_sysc
,
1998 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs
[] = {
1999 { .name
= "tll-irq", .irq
= 78 },
2003 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod
= {
2004 .name
= "usb_tll_hs",
2005 .class = &omap3xxx_usb_tll_hs_hwmod_class
,
2006 .clkdm_name
= "l3_init_clkdm",
2007 .mpu_irqs
= omap3xxx_usb_tll_hs_irqs
,
2008 .main_clk
= "usbtll_fck",
2011 .module_offs
= CORE_MOD
,
2013 .module_bit
= OMAP3430ES2_EN_USBTLL_SHIFT
,
2015 .idlest_idle_bit
= OMAP3430ES2_ST_USBTLL_SHIFT
,
2020 static struct omap_hwmod omap3xxx_hdq1w_hwmod
= {
2022 .mpu_irqs
= omap2_hdq1w_mpu_irqs
,
2023 .main_clk
= "hdq_fck",
2026 .module_offs
= CORE_MOD
,
2028 .module_bit
= OMAP3430_EN_HDQ_SHIFT
,
2030 .idlest_idle_bit
= OMAP3430_ST_HDQ_SHIFT
,
2033 .class = &omap2_hdq1w_class
,
2037 * '32K sync counter' class
2038 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
2040 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc
= {
2042 .sysc_offs
= 0x0004,
2043 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
2044 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
),
2045 .sysc_fields
= &omap_hwmod_sysc_type1
,
2048 static struct omap_hwmod_class omap3xxx_counter_hwmod_class
= {
2050 .sysc
= &omap3xxx_counter_sysc
,
2053 static struct omap_hwmod omap3xxx_counter_32k_hwmod
= {
2054 .name
= "counter_32k",
2055 .class = &omap3xxx_counter_hwmod_class
,
2056 .clkdm_name
= "wkup_clkdm",
2057 .flags
= HWMOD_SWSUP_SIDLE
,
2058 .main_clk
= "wkup_32k_fck",
2061 .module_offs
= WKUP_MOD
,
2063 .module_bit
= OMAP3430_ST_32KSYNC_SHIFT
,
2065 .idlest_idle_bit
= OMAP3430_ST_32KSYNC_SHIFT
,
2074 /* L3 -> L4_CORE interface */
2075 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core
= {
2076 .master
= &omap3xxx_l3_main_hwmod
,
2077 .slave
= &omap3xxx_l4_core_hwmod
,
2078 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2081 /* L3 -> L4_PER interface */
2082 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per
= {
2083 .master
= &omap3xxx_l3_main_hwmod
,
2084 .slave
= &omap3xxx_l4_per_hwmod
,
2085 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2088 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs
[] = {
2090 .pa_start
= 0x68000000,
2091 .pa_end
= 0x6800ffff,
2092 .flags
= ADDR_TYPE_RT
,
2097 /* MPU -> L3 interface */
2098 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main
= {
2099 .master
= &omap3xxx_mpu_hwmod
,
2100 .slave
= &omap3xxx_l3_main_hwmod
,
2101 .addr
= omap3xxx_l3_main_addrs
,
2102 .user
= OCP_USER_MPU
,
2106 static struct omap_hwmod_ocp_if omap3430es1_dss__l3
= {
2107 .master
= &omap3430es1_dss_core_hwmod
,
2108 .slave
= &omap3xxx_l3_main_hwmod
,
2109 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2112 static struct omap_hwmod_ocp_if omap3xxx_dss__l3
= {
2113 .master
= &omap3xxx_dss_core_hwmod
,
2114 .slave
= &omap3xxx_l3_main_hwmod
,
2117 .l3_perm_bit
= OMAP3_L3_CORE_FW_INIT_ID_DSS
,
2118 .flags
= OMAP_FIREWALL_L3
,
2121 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2124 /* l3_core -> usbhsotg interface */
2125 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3
= {
2126 .master
= &omap3xxx_usbhsotg_hwmod
,
2127 .slave
= &omap3xxx_l3_main_hwmod
,
2128 .clk
= "core_l3_ick",
2129 .user
= OCP_USER_MPU
,
2132 /* l3_core -> am35xx_usbhsotg interface */
2133 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3
= {
2134 .master
= &am35xx_usbhsotg_hwmod
,
2135 .slave
= &omap3xxx_l3_main_hwmod
,
2136 .clk
= "hsotgusb_ick",
2137 .user
= OCP_USER_MPU
,
2140 /* L4_CORE -> L4_WKUP interface */
2141 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup
= {
2142 .master
= &omap3xxx_l4_core_hwmod
,
2143 .slave
= &omap3xxx_l4_wkup_hwmod
,
2144 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2147 /* L4 CORE -> MMC1 interface */
2148 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1
= {
2149 .master
= &omap3xxx_l4_core_hwmod
,
2150 .slave
= &omap3xxx_pre_es3_mmc1_hwmod
,
2151 .clk
= "mmchs1_ick",
2152 .addr
= omap2430_mmc1_addr_space
,
2153 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2154 .flags
= OMAP_FIREWALL_L4
2157 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1
= {
2158 .master
= &omap3xxx_l4_core_hwmod
,
2159 .slave
= &omap3xxx_es3plus_mmc1_hwmod
,
2160 .clk
= "mmchs1_ick",
2161 .addr
= omap2430_mmc1_addr_space
,
2162 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2163 .flags
= OMAP_FIREWALL_L4
2166 /* L4 CORE -> MMC2 interface */
2167 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2
= {
2168 .master
= &omap3xxx_l4_core_hwmod
,
2169 .slave
= &omap3xxx_pre_es3_mmc2_hwmod
,
2170 .clk
= "mmchs2_ick",
2171 .addr
= omap2430_mmc2_addr_space
,
2172 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2173 .flags
= OMAP_FIREWALL_L4
2176 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2
= {
2177 .master
= &omap3xxx_l4_core_hwmod
,
2178 .slave
= &omap3xxx_es3plus_mmc2_hwmod
,
2179 .clk
= "mmchs2_ick",
2180 .addr
= omap2430_mmc2_addr_space
,
2181 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2182 .flags
= OMAP_FIREWALL_L4
2185 /* L4 CORE -> MMC3 interface */
2186 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space
[] = {
2188 .pa_start
= 0x480ad000,
2189 .pa_end
= 0x480ad1ff,
2190 .flags
= ADDR_TYPE_RT
,
2195 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3
= {
2196 .master
= &omap3xxx_l4_core_hwmod
,
2197 .slave
= &omap3xxx_mmc3_hwmod
,
2198 .clk
= "mmchs3_ick",
2199 .addr
= omap3xxx_mmc3_addr_space
,
2200 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2201 .flags
= OMAP_FIREWALL_L4
2204 /* L4 CORE -> UART1 interface */
2205 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space
[] = {
2207 .pa_start
= OMAP3_UART1_BASE
,
2208 .pa_end
= OMAP3_UART1_BASE
+ SZ_8K
- 1,
2209 .flags
= ADDR_MAP_ON_INIT
| ADDR_TYPE_RT
,
2214 static struct omap_hwmod_ocp_if omap3_l4_core__uart1
= {
2215 .master
= &omap3xxx_l4_core_hwmod
,
2216 .slave
= &omap3xxx_uart1_hwmod
,
2218 .addr
= omap3xxx_uart1_addr_space
,
2219 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2222 /* L4 CORE -> UART2 interface */
2223 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space
[] = {
2225 .pa_start
= OMAP3_UART2_BASE
,
2226 .pa_end
= OMAP3_UART2_BASE
+ SZ_1K
- 1,
2227 .flags
= ADDR_MAP_ON_INIT
| ADDR_TYPE_RT
,
2232 static struct omap_hwmod_ocp_if omap3_l4_core__uart2
= {
2233 .master
= &omap3xxx_l4_core_hwmod
,
2234 .slave
= &omap3xxx_uart2_hwmod
,
2236 .addr
= omap3xxx_uart2_addr_space
,
2237 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2240 /* L4 PER -> UART3 interface */
2241 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space
[] = {
2243 .pa_start
= OMAP3_UART3_BASE
,
2244 .pa_end
= OMAP3_UART3_BASE
+ SZ_1K
- 1,
2245 .flags
= ADDR_MAP_ON_INIT
| ADDR_TYPE_RT
,
2250 static struct omap_hwmod_ocp_if omap3_l4_per__uart3
= {
2251 .master
= &omap3xxx_l4_per_hwmod
,
2252 .slave
= &omap3xxx_uart3_hwmod
,
2254 .addr
= omap3xxx_uart3_addr_space
,
2255 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2258 /* L4 PER -> UART4 interface */
2259 static struct omap_hwmod_addr_space omap36xx_uart4_addr_space
[] = {
2261 .pa_start
= OMAP3_UART4_BASE
,
2262 .pa_end
= OMAP3_UART4_BASE
+ SZ_1K
- 1,
2263 .flags
= ADDR_MAP_ON_INIT
| ADDR_TYPE_RT
,
2268 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4
= {
2269 .master
= &omap3xxx_l4_per_hwmod
,
2270 .slave
= &omap36xx_uart4_hwmod
,
2272 .addr
= omap36xx_uart4_addr_space
,
2273 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2276 /* AM35xx: L4 CORE -> UART4 interface */
2277 static struct omap_hwmod_addr_space am35xx_uart4_addr_space
[] = {
2279 .pa_start
= OMAP3_UART4_AM35XX_BASE
,
2280 .pa_end
= OMAP3_UART4_AM35XX_BASE
+ SZ_1K
- 1,
2281 .flags
= ADDR_MAP_ON_INIT
| ADDR_TYPE_RT
,
2286 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4
= {
2287 .master
= &omap3xxx_l4_core_hwmod
,
2288 .slave
= &am35xx_uart4_hwmod
,
2290 .addr
= am35xx_uart4_addr_space
,
2291 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2294 /* L4 CORE -> I2C1 interface */
2295 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1
= {
2296 .master
= &omap3xxx_l4_core_hwmod
,
2297 .slave
= &omap3xxx_i2c1_hwmod
,
2299 .addr
= omap2_i2c1_addr_space
,
2302 .l4_fw_region
= OMAP3_L4_CORE_FW_I2C1_REGION
,
2304 .flags
= OMAP_FIREWALL_L4
,
2307 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2310 /* L4 CORE -> I2C2 interface */
2311 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2
= {
2312 .master
= &omap3xxx_l4_core_hwmod
,
2313 .slave
= &omap3xxx_i2c2_hwmod
,
2315 .addr
= omap2_i2c2_addr_space
,
2318 .l4_fw_region
= OMAP3_L4_CORE_FW_I2C2_REGION
,
2320 .flags
= OMAP_FIREWALL_L4
,
2323 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2326 /* L4 CORE -> I2C3 interface */
2327 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space
[] = {
2329 .pa_start
= 0x48060000,
2330 .pa_end
= 0x48060000 + SZ_128
- 1,
2331 .flags
= ADDR_TYPE_RT
,
2336 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3
= {
2337 .master
= &omap3xxx_l4_core_hwmod
,
2338 .slave
= &omap3xxx_i2c3_hwmod
,
2340 .addr
= omap3xxx_i2c3_addr_space
,
2343 .l4_fw_region
= OMAP3_L4_CORE_FW_I2C3_REGION
,
2345 .flags
= OMAP_FIREWALL_L4
,
2348 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2351 /* L4 CORE -> SR1 interface */
2352 static struct omap_hwmod_addr_space omap3_sr1_addr_space
[] = {
2354 .pa_start
= OMAP34XX_SR1_BASE
,
2355 .pa_end
= OMAP34XX_SR1_BASE
+ SZ_1K
- 1,
2356 .flags
= ADDR_TYPE_RT
,
2361 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1
= {
2362 .master
= &omap3xxx_l4_core_hwmod
,
2363 .slave
= &omap34xx_sr1_hwmod
,
2365 .addr
= omap3_sr1_addr_space
,
2366 .user
= OCP_USER_MPU
,
2369 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1
= {
2370 .master
= &omap3xxx_l4_core_hwmod
,
2371 .slave
= &omap36xx_sr1_hwmod
,
2373 .addr
= omap3_sr1_addr_space
,
2374 .user
= OCP_USER_MPU
,
2377 /* L4 CORE -> SR1 interface */
2378 static struct omap_hwmod_addr_space omap3_sr2_addr_space
[] = {
2380 .pa_start
= OMAP34XX_SR2_BASE
,
2381 .pa_end
= OMAP34XX_SR2_BASE
+ SZ_1K
- 1,
2382 .flags
= ADDR_TYPE_RT
,
2387 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2
= {
2388 .master
= &omap3xxx_l4_core_hwmod
,
2389 .slave
= &omap34xx_sr2_hwmod
,
2391 .addr
= omap3_sr2_addr_space
,
2392 .user
= OCP_USER_MPU
,
2395 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2
= {
2396 .master
= &omap3xxx_l4_core_hwmod
,
2397 .slave
= &omap36xx_sr2_hwmod
,
2399 .addr
= omap3_sr2_addr_space
,
2400 .user
= OCP_USER_MPU
,
2403 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs
[] = {
2405 .pa_start
= OMAP34XX_HSUSB_OTG_BASE
,
2406 .pa_end
= OMAP34XX_HSUSB_OTG_BASE
+ SZ_4K
- 1,
2407 .flags
= ADDR_TYPE_RT
2412 /* l4_core -> usbhsotg */
2413 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg
= {
2414 .master
= &omap3xxx_l4_core_hwmod
,
2415 .slave
= &omap3xxx_usbhsotg_hwmod
,
2417 .addr
= omap3xxx_usbhsotg_addrs
,
2418 .user
= OCP_USER_MPU
,
2421 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs
[] = {
2423 .pa_start
= AM35XX_IPSS_USBOTGSS_BASE
,
2424 .pa_end
= AM35XX_IPSS_USBOTGSS_BASE
+ SZ_4K
- 1,
2425 .flags
= ADDR_TYPE_RT
2430 /* l4_core -> usbhsotg */
2431 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg
= {
2432 .master
= &omap3xxx_l4_core_hwmod
,
2433 .slave
= &am35xx_usbhsotg_hwmod
,
2434 .clk
= "hsotgusb_ick",
2435 .addr
= am35xx_usbhsotg_addrs
,
2436 .user
= OCP_USER_MPU
,
2439 /* L4_WKUP -> L4_SEC interface */
2440 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec
= {
2441 .master
= &omap3xxx_l4_wkup_hwmod
,
2442 .slave
= &omap3xxx_l4_sec_hwmod
,
2443 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2446 /* IVA2 <- L3 interface */
2447 static struct omap_hwmod_ocp_if omap3xxx_l3__iva
= {
2448 .master
= &omap3xxx_l3_main_hwmod
,
2449 .slave
= &omap3xxx_iva_hwmod
,
2450 .clk
= "core_l3_ick",
2451 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2454 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs
[] = {
2456 .pa_start
= 0x48318000,
2457 .pa_end
= 0x48318000 + SZ_1K
- 1,
2458 .flags
= ADDR_TYPE_RT
2463 /* l4_wkup -> timer1 */
2464 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1
= {
2465 .master
= &omap3xxx_l4_wkup_hwmod
,
2466 .slave
= &omap3xxx_timer1_hwmod
,
2468 .addr
= omap3xxx_timer1_addrs
,
2469 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2472 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs
[] = {
2474 .pa_start
= 0x49032000,
2475 .pa_end
= 0x49032000 + SZ_1K
- 1,
2476 .flags
= ADDR_TYPE_RT
2481 /* l4_per -> timer2 */
2482 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2
= {
2483 .master
= &omap3xxx_l4_per_hwmod
,
2484 .slave
= &omap3xxx_timer2_hwmod
,
2486 .addr
= omap3xxx_timer2_addrs
,
2487 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2490 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs
[] = {
2492 .pa_start
= 0x49034000,
2493 .pa_end
= 0x49034000 + SZ_1K
- 1,
2494 .flags
= ADDR_TYPE_RT
2499 /* l4_per -> timer3 */
2500 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3
= {
2501 .master
= &omap3xxx_l4_per_hwmod
,
2502 .slave
= &omap3xxx_timer3_hwmod
,
2504 .addr
= omap3xxx_timer3_addrs
,
2505 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2508 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs
[] = {
2510 .pa_start
= 0x49036000,
2511 .pa_end
= 0x49036000 + SZ_1K
- 1,
2512 .flags
= ADDR_TYPE_RT
2517 /* l4_per -> timer4 */
2518 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4
= {
2519 .master
= &omap3xxx_l4_per_hwmod
,
2520 .slave
= &omap3xxx_timer4_hwmod
,
2522 .addr
= omap3xxx_timer4_addrs
,
2523 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2526 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs
[] = {
2528 .pa_start
= 0x49038000,
2529 .pa_end
= 0x49038000 + SZ_1K
- 1,
2530 .flags
= ADDR_TYPE_RT
2535 /* l4_per -> timer5 */
2536 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5
= {
2537 .master
= &omap3xxx_l4_per_hwmod
,
2538 .slave
= &omap3xxx_timer5_hwmod
,
2540 .addr
= omap3xxx_timer5_addrs
,
2541 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2544 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs
[] = {
2546 .pa_start
= 0x4903A000,
2547 .pa_end
= 0x4903A000 + SZ_1K
- 1,
2548 .flags
= ADDR_TYPE_RT
2553 /* l4_per -> timer6 */
2554 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6
= {
2555 .master
= &omap3xxx_l4_per_hwmod
,
2556 .slave
= &omap3xxx_timer6_hwmod
,
2558 .addr
= omap3xxx_timer6_addrs
,
2559 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2562 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs
[] = {
2564 .pa_start
= 0x4903C000,
2565 .pa_end
= 0x4903C000 + SZ_1K
- 1,
2566 .flags
= ADDR_TYPE_RT
2571 /* l4_per -> timer7 */
2572 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7
= {
2573 .master
= &omap3xxx_l4_per_hwmod
,
2574 .slave
= &omap3xxx_timer7_hwmod
,
2576 .addr
= omap3xxx_timer7_addrs
,
2577 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2580 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs
[] = {
2582 .pa_start
= 0x4903E000,
2583 .pa_end
= 0x4903E000 + SZ_1K
- 1,
2584 .flags
= ADDR_TYPE_RT
2589 /* l4_per -> timer8 */
2590 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8
= {
2591 .master
= &omap3xxx_l4_per_hwmod
,
2592 .slave
= &omap3xxx_timer8_hwmod
,
2594 .addr
= omap3xxx_timer8_addrs
,
2595 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2598 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs
[] = {
2600 .pa_start
= 0x49040000,
2601 .pa_end
= 0x49040000 + SZ_1K
- 1,
2602 .flags
= ADDR_TYPE_RT
2607 /* l4_per -> timer9 */
2608 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9
= {
2609 .master
= &omap3xxx_l4_per_hwmod
,
2610 .slave
= &omap3xxx_timer9_hwmod
,
2612 .addr
= omap3xxx_timer9_addrs
,
2613 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2616 /* l4_core -> timer10 */
2617 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10
= {
2618 .master
= &omap3xxx_l4_core_hwmod
,
2619 .slave
= &omap3xxx_timer10_hwmod
,
2621 .addr
= omap2_timer10_addrs
,
2622 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2625 /* l4_core -> timer11 */
2626 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11
= {
2627 .master
= &omap3xxx_l4_core_hwmod
,
2628 .slave
= &omap3xxx_timer11_hwmod
,
2630 .addr
= omap2_timer11_addrs
,
2631 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2634 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs
[] = {
2636 .pa_start
= 0x48304000,
2637 .pa_end
= 0x48304000 + SZ_1K
- 1,
2638 .flags
= ADDR_TYPE_RT
2643 /* l4_core -> timer12 */
2644 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12
= {
2645 .master
= &omap3xxx_l4_sec_hwmod
,
2646 .slave
= &omap3xxx_timer12_hwmod
,
2648 .addr
= omap3xxx_timer12_addrs
,
2649 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2652 /* l4_wkup -> wd_timer2 */
2653 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs
[] = {
2655 .pa_start
= 0x48314000,
2656 .pa_end
= 0x4831407f,
2657 .flags
= ADDR_TYPE_RT
2662 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2
= {
2663 .master
= &omap3xxx_l4_wkup_hwmod
,
2664 .slave
= &omap3xxx_wd_timer2_hwmod
,
2666 .addr
= omap3xxx_wd_timer2_addrs
,
2667 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2670 /* l4_core -> dss */
2671 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss
= {
2672 .master
= &omap3xxx_l4_core_hwmod
,
2673 .slave
= &omap3430es1_dss_core_hwmod
,
2675 .addr
= omap2_dss_addrs
,
2678 .l4_fw_region
= OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION
,
2679 .l4_prot_group
= OMAP3_L4_CORE_FW_DSS_PROT_GROUP
,
2680 .flags
= OMAP_FIREWALL_L4
,
2683 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2686 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss
= {
2687 .master
= &omap3xxx_l4_core_hwmod
,
2688 .slave
= &omap3xxx_dss_core_hwmod
,
2690 .addr
= omap2_dss_addrs
,
2693 .l4_fw_region
= OMAP3_L4_CORE_FW_DSS_CORE_REGION
,
2694 .l4_prot_group
= OMAP3_L4_CORE_FW_DSS_PROT_GROUP
,
2695 .flags
= OMAP_FIREWALL_L4
,
2698 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2701 /* l4_core -> dss_dispc */
2702 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc
= {
2703 .master
= &omap3xxx_l4_core_hwmod
,
2704 .slave
= &omap3xxx_dss_dispc_hwmod
,
2706 .addr
= omap2_dss_dispc_addrs
,
2709 .l4_fw_region
= OMAP3_L4_CORE_FW_DSS_DISPC_REGION
,
2710 .l4_prot_group
= OMAP3_L4_CORE_FW_DSS_PROT_GROUP
,
2711 .flags
= OMAP_FIREWALL_L4
,
2714 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2717 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs
[] = {
2719 .pa_start
= 0x4804FC00,
2720 .pa_end
= 0x4804FFFF,
2721 .flags
= ADDR_TYPE_RT
2726 /* l4_core -> dss_dsi1 */
2727 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1
= {
2728 .master
= &omap3xxx_l4_core_hwmod
,
2729 .slave
= &omap3xxx_dss_dsi1_hwmod
,
2731 .addr
= omap3xxx_dss_dsi1_addrs
,
2734 .l4_fw_region
= OMAP3_L4_CORE_FW_DSS_DSI_REGION
,
2735 .l4_prot_group
= OMAP3_L4_CORE_FW_DSS_PROT_GROUP
,
2736 .flags
= OMAP_FIREWALL_L4
,
2739 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2742 /* l4_core -> dss_rfbi */
2743 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi
= {
2744 .master
= &omap3xxx_l4_core_hwmod
,
2745 .slave
= &omap3xxx_dss_rfbi_hwmod
,
2747 .addr
= omap2_dss_rfbi_addrs
,
2750 .l4_fw_region
= OMAP3_L4_CORE_FW_DSS_RFBI_REGION
,
2751 .l4_prot_group
= OMAP3_L4_CORE_FW_DSS_PROT_GROUP
,
2752 .flags
= OMAP_FIREWALL_L4
,
2755 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2758 /* l4_core -> dss_venc */
2759 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc
= {
2760 .master
= &omap3xxx_l4_core_hwmod
,
2761 .slave
= &omap3xxx_dss_venc_hwmod
,
2763 .addr
= omap2_dss_venc_addrs
,
2766 .l4_fw_region
= OMAP3_L4_CORE_FW_DSS_VENC_REGION
,
2767 .l4_prot_group
= OMAP3_L4_CORE_FW_DSS_PROT_GROUP
,
2768 .flags
= OMAP_FIREWALL_L4
,
2771 .flags
= OCPIF_SWSUP_IDLE
,
2772 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2775 /* l4_wkup -> gpio1 */
2776 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs
[] = {
2778 .pa_start
= 0x48310000,
2779 .pa_end
= 0x483101ff,
2780 .flags
= ADDR_TYPE_RT
2785 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1
= {
2786 .master
= &omap3xxx_l4_wkup_hwmod
,
2787 .slave
= &omap3xxx_gpio1_hwmod
,
2788 .addr
= omap3xxx_gpio1_addrs
,
2789 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2792 /* l4_per -> gpio2 */
2793 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs
[] = {
2795 .pa_start
= 0x49050000,
2796 .pa_end
= 0x490501ff,
2797 .flags
= ADDR_TYPE_RT
2802 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2
= {
2803 .master
= &omap3xxx_l4_per_hwmod
,
2804 .slave
= &omap3xxx_gpio2_hwmod
,
2805 .addr
= omap3xxx_gpio2_addrs
,
2806 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2809 /* l4_per -> gpio3 */
2810 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs
[] = {
2812 .pa_start
= 0x49052000,
2813 .pa_end
= 0x490521ff,
2814 .flags
= ADDR_TYPE_RT
2819 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3
= {
2820 .master
= &omap3xxx_l4_per_hwmod
,
2821 .slave
= &omap3xxx_gpio3_hwmod
,
2822 .addr
= omap3xxx_gpio3_addrs
,
2823 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2826 /* l4_per -> gpio4 */
2827 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs
[] = {
2829 .pa_start
= 0x49054000,
2830 .pa_end
= 0x490541ff,
2831 .flags
= ADDR_TYPE_RT
2836 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4
= {
2837 .master
= &omap3xxx_l4_per_hwmod
,
2838 .slave
= &omap3xxx_gpio4_hwmod
,
2839 .addr
= omap3xxx_gpio4_addrs
,
2840 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2843 /* l4_per -> gpio5 */
2844 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs
[] = {
2846 .pa_start
= 0x49056000,
2847 .pa_end
= 0x490561ff,
2848 .flags
= ADDR_TYPE_RT
2853 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5
= {
2854 .master
= &omap3xxx_l4_per_hwmod
,
2855 .slave
= &omap3xxx_gpio5_hwmod
,
2856 .addr
= omap3xxx_gpio5_addrs
,
2857 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2860 /* l4_per -> gpio6 */
2861 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs
[] = {
2863 .pa_start
= 0x49058000,
2864 .pa_end
= 0x490581ff,
2865 .flags
= ADDR_TYPE_RT
2870 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6
= {
2871 .master
= &omap3xxx_l4_per_hwmod
,
2872 .slave
= &omap3xxx_gpio6_hwmod
,
2873 .addr
= omap3xxx_gpio6_addrs
,
2874 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2877 /* dma_system -> L3 */
2878 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3
= {
2879 .master
= &omap3xxx_dma_system_hwmod
,
2880 .slave
= &omap3xxx_l3_main_hwmod
,
2881 .clk
= "core_l3_ick",
2882 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2885 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs
[] = {
2887 .pa_start
= 0x48056000,
2888 .pa_end
= 0x48056fff,
2889 .flags
= ADDR_TYPE_RT
2894 /* l4_cfg -> dma_system */
2895 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system
= {
2896 .master
= &omap3xxx_l4_core_hwmod
,
2897 .slave
= &omap3xxx_dma_system_hwmod
,
2898 .clk
= "core_l4_ick",
2899 .addr
= omap3xxx_dma_system_addrs
,
2900 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2903 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs
[] = {
2906 .pa_start
= 0x48074000,
2907 .pa_end
= 0x480740ff,
2908 .flags
= ADDR_TYPE_RT
2913 /* l4_core -> mcbsp1 */
2914 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1
= {
2915 .master
= &omap3xxx_l4_core_hwmod
,
2916 .slave
= &omap3xxx_mcbsp1_hwmod
,
2917 .clk
= "mcbsp1_ick",
2918 .addr
= omap3xxx_mcbsp1_addrs
,
2919 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2922 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs
[] = {
2925 .pa_start
= 0x49022000,
2926 .pa_end
= 0x490220ff,
2927 .flags
= ADDR_TYPE_RT
2932 /* l4_per -> mcbsp2 */
2933 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2
= {
2934 .master
= &omap3xxx_l4_per_hwmod
,
2935 .slave
= &omap3xxx_mcbsp2_hwmod
,
2936 .clk
= "mcbsp2_ick",
2937 .addr
= omap3xxx_mcbsp2_addrs
,
2938 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2941 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs
[] = {
2944 .pa_start
= 0x49024000,
2945 .pa_end
= 0x490240ff,
2946 .flags
= ADDR_TYPE_RT
2951 /* l4_per -> mcbsp3 */
2952 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3
= {
2953 .master
= &omap3xxx_l4_per_hwmod
,
2954 .slave
= &omap3xxx_mcbsp3_hwmod
,
2955 .clk
= "mcbsp3_ick",
2956 .addr
= omap3xxx_mcbsp3_addrs
,
2957 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2960 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs
[] = {
2963 .pa_start
= 0x49026000,
2964 .pa_end
= 0x490260ff,
2965 .flags
= ADDR_TYPE_RT
2970 /* l4_per -> mcbsp4 */
2971 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4
= {
2972 .master
= &omap3xxx_l4_per_hwmod
,
2973 .slave
= &omap3xxx_mcbsp4_hwmod
,
2974 .clk
= "mcbsp4_ick",
2975 .addr
= omap3xxx_mcbsp4_addrs
,
2976 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2979 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs
[] = {
2982 .pa_start
= 0x48096000,
2983 .pa_end
= 0x480960ff,
2984 .flags
= ADDR_TYPE_RT
2989 /* l4_core -> mcbsp5 */
2990 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5
= {
2991 .master
= &omap3xxx_l4_core_hwmod
,
2992 .slave
= &omap3xxx_mcbsp5_hwmod
,
2993 .clk
= "mcbsp5_ick",
2994 .addr
= omap3xxx_mcbsp5_addrs
,
2995 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2998 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs
[] = {
3001 .pa_start
= 0x49028000,
3002 .pa_end
= 0x490280ff,
3003 .flags
= ADDR_TYPE_RT
3008 /* l4_per -> mcbsp2_sidetone */
3009 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone
= {
3010 .master
= &omap3xxx_l4_per_hwmod
,
3011 .slave
= &omap3xxx_mcbsp2_sidetone_hwmod
,
3012 .clk
= "mcbsp2_ick",
3013 .addr
= omap3xxx_mcbsp2_sidetone_addrs
,
3014 .user
= OCP_USER_MPU
,
3017 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs
[] = {
3020 .pa_start
= 0x4902A000,
3021 .pa_end
= 0x4902A0ff,
3022 .flags
= ADDR_TYPE_RT
3027 /* l4_per -> mcbsp3_sidetone */
3028 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone
= {
3029 .master
= &omap3xxx_l4_per_hwmod
,
3030 .slave
= &omap3xxx_mcbsp3_sidetone_hwmod
,
3031 .clk
= "mcbsp3_ick",
3032 .addr
= omap3xxx_mcbsp3_sidetone_addrs
,
3033 .user
= OCP_USER_MPU
,
3036 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs
[] = {
3038 .pa_start
= 0x48094000,
3039 .pa_end
= 0x480941ff,
3040 .flags
= ADDR_TYPE_RT
,
3045 /* l4_core -> mailbox */
3046 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox
= {
3047 .master
= &omap3xxx_l4_core_hwmod
,
3048 .slave
= &omap3xxx_mailbox_hwmod
,
3049 .addr
= omap3xxx_mailbox_addrs
,
3050 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3053 /* l4 core -> mcspi1 interface */
3054 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1
= {
3055 .master
= &omap3xxx_l4_core_hwmod
,
3056 .slave
= &omap34xx_mcspi1
,
3057 .clk
= "mcspi1_ick",
3058 .addr
= omap2_mcspi1_addr_space
,
3059 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3062 /* l4 core -> mcspi2 interface */
3063 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2
= {
3064 .master
= &omap3xxx_l4_core_hwmod
,
3065 .slave
= &omap34xx_mcspi2
,
3066 .clk
= "mcspi2_ick",
3067 .addr
= omap2_mcspi2_addr_space
,
3068 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3071 /* l4 core -> mcspi3 interface */
3072 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3
= {
3073 .master
= &omap3xxx_l4_core_hwmod
,
3074 .slave
= &omap34xx_mcspi3
,
3075 .clk
= "mcspi3_ick",
3076 .addr
= omap2430_mcspi3_addr_space
,
3077 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3080 /* l4 core -> mcspi4 interface */
3081 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space
[] = {
3083 .pa_start
= 0x480ba000,
3084 .pa_end
= 0x480ba0ff,
3085 .flags
= ADDR_TYPE_RT
,
3090 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4
= {
3091 .master
= &omap3xxx_l4_core_hwmod
,
3092 .slave
= &omap34xx_mcspi4
,
3093 .clk
= "mcspi4_ick",
3094 .addr
= omap34xx_mcspi4_addr_space
,
3095 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3098 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2
= {
3099 .master
= &omap3xxx_usb_host_hs_hwmod
,
3100 .slave
= &omap3xxx_l3_main_hwmod
,
3101 .clk
= "core_l3_ick",
3102 .user
= OCP_USER_MPU
,
3105 static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs
[] = {
3108 .pa_start
= 0x48064000,
3109 .pa_end
= 0x480643ff,
3110 .flags
= ADDR_TYPE_RT
3114 .pa_start
= 0x48064400,
3115 .pa_end
= 0x480647ff,
3119 .pa_start
= 0x48064800,
3120 .pa_end
= 0x48064cff,
3125 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs
= {
3126 .master
= &omap3xxx_l4_core_hwmod
,
3127 .slave
= &omap3xxx_usb_host_hs_hwmod
,
3128 .clk
= "usbhost_ick",
3129 .addr
= omap3xxx_usb_host_hs_addrs
,
3130 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3133 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs
[] = {
3136 .pa_start
= 0x48062000,
3137 .pa_end
= 0x48062fff,
3138 .flags
= ADDR_TYPE_RT
3143 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs
= {
3144 .master
= &omap3xxx_l4_core_hwmod
,
3145 .slave
= &omap3xxx_usb_tll_hs_hwmod
,
3146 .clk
= "usbtll_ick",
3147 .addr
= omap3xxx_usb_tll_hs_addrs
,
3148 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3151 /* l4_core -> hdq1w interface */
3152 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w
= {
3153 .master
= &omap3xxx_l4_core_hwmod
,
3154 .slave
= &omap3xxx_hdq1w_hwmod
,
3156 .addr
= omap2_hdq1w_addr_space
,
3157 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3158 .flags
= OMAP_FIREWALL_L4
| OCPIF_SWSUP_IDLE
,
3161 /* l4_wkup -> 32ksync_counter */
3162 static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs
[] = {
3164 .pa_start
= 0x48320000,
3165 .pa_end
= 0x4832001f,
3166 .flags
= ADDR_TYPE_RT
3171 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k
= {
3172 .master
= &omap3xxx_l4_wkup_hwmod
,
3173 .slave
= &omap3xxx_counter_32k_hwmod
,
3174 .clk
= "omap_32ksync_ick",
3175 .addr
= omap3xxx_counter_32k_addrs
,
3176 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3179 /* am35xx has Davinci MDIO & EMAC */
3180 static struct omap_hwmod_class am35xx_mdio_class
= {
3181 .name
= "davinci_mdio",
3184 static struct omap_hwmod am35xx_mdio_hwmod
= {
3185 .name
= "davinci_mdio",
3186 .class = &am35xx_mdio_class
,
3187 .flags
= HWMOD_NO_IDLEST
,
3191 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3192 * but this will probably require some additional hwmod core support,
3193 * so is left as a future to-do item.
3195 static struct omap_hwmod_ocp_if am35xx_mdio__l3
= {
3196 .master
= &am35xx_mdio_hwmod
,
3197 .slave
= &omap3xxx_l3_main_hwmod
,
3199 .user
= OCP_USER_MPU
,
3202 static struct omap_hwmod_addr_space am35xx_mdio_addrs
[] = {
3204 .pa_start
= AM35XX_IPSS_MDIO_BASE
,
3205 .pa_end
= AM35XX_IPSS_MDIO_BASE
+ SZ_4K
- 1,
3206 .flags
= ADDR_TYPE_RT
,
3211 /* l4_core -> davinci mdio */
3213 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3214 * but this will probably require some additional hwmod core support,
3215 * so is left as a future to-do item.
3217 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio
= {
3218 .master
= &omap3xxx_l4_core_hwmod
,
3219 .slave
= &am35xx_mdio_hwmod
,
3221 .addr
= am35xx_mdio_addrs
,
3222 .user
= OCP_USER_MPU
,
3225 static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs
[] = {
3226 { .name
= "rxthresh", .irq
= INT_35XX_EMAC_C0_RXTHRESH_IRQ
},
3227 { .name
= "rx_pulse", .irq
= INT_35XX_EMAC_C0_RX_PULSE_IRQ
},
3228 { .name
= "tx_pulse", .irq
= INT_35XX_EMAC_C0_TX_PULSE_IRQ
},
3229 { .name
= "misc_pulse", .irq
= INT_35XX_EMAC_C0_MISC_PULSE_IRQ
},
3233 static struct omap_hwmod_class am35xx_emac_class
= {
3234 .name
= "davinci_emac",
3237 static struct omap_hwmod am35xx_emac_hwmod
= {
3238 .name
= "davinci_emac",
3239 .mpu_irqs
= am35xx_emac_mpu_irqs
,
3240 .class = &am35xx_emac_class
,
3241 .flags
= HWMOD_NO_IDLEST
,
3244 /* l3_core -> davinci emac interface */
3246 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3247 * but this will probably require some additional hwmod core support,
3248 * so is left as a future to-do item.
3250 static struct omap_hwmod_ocp_if am35xx_emac__l3
= {
3251 .master
= &am35xx_emac_hwmod
,
3252 .slave
= &omap3xxx_l3_main_hwmod
,
3254 .user
= OCP_USER_MPU
,
3257 static struct omap_hwmod_addr_space am35xx_emac_addrs
[] = {
3259 .pa_start
= AM35XX_IPSS_EMAC_BASE
,
3260 .pa_end
= AM35XX_IPSS_EMAC_BASE
+ 0x30000 - 1,
3261 .flags
= ADDR_TYPE_RT
,
3266 /* l4_core -> davinci emac */
3268 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3269 * but this will probably require some additional hwmod core support,
3270 * so is left as a future to-do item.
3272 static struct omap_hwmod_ocp_if am35xx_l4_core__emac
= {
3273 .master
= &omap3xxx_l4_core_hwmod
,
3274 .slave
= &am35xx_emac_hwmod
,
3276 .addr
= am35xx_emac_addrs
,
3277 .user
= OCP_USER_MPU
,
3280 static struct omap_hwmod_ocp_if
*omap3xxx_hwmod_ocp_ifs
[] __initdata
= {
3281 &omap3xxx_l3_main__l4_core
,
3282 &omap3xxx_l3_main__l4_per
,
3283 &omap3xxx_mpu__l3_main
,
3284 &omap3xxx_l4_core__l4_wkup
,
3285 &omap3xxx_l4_core__mmc3
,
3286 &omap3_l4_core__uart1
,
3287 &omap3_l4_core__uart2
,
3288 &omap3_l4_per__uart3
,
3289 &omap3_l4_core__i2c1
,
3290 &omap3_l4_core__i2c2
,
3291 &omap3_l4_core__i2c3
,
3292 &omap3xxx_l4_wkup__l4_sec
,
3293 &omap3xxx_l4_wkup__timer1
,
3294 &omap3xxx_l4_per__timer2
,
3295 &omap3xxx_l4_per__timer3
,
3296 &omap3xxx_l4_per__timer4
,
3297 &omap3xxx_l4_per__timer5
,
3298 &omap3xxx_l4_per__timer6
,
3299 &omap3xxx_l4_per__timer7
,
3300 &omap3xxx_l4_per__timer8
,
3301 &omap3xxx_l4_per__timer9
,
3302 &omap3xxx_l4_core__timer10
,
3303 &omap3xxx_l4_core__timer11
,
3304 &omap3xxx_l4_wkup__wd_timer2
,
3305 &omap3xxx_l4_wkup__gpio1
,
3306 &omap3xxx_l4_per__gpio2
,
3307 &omap3xxx_l4_per__gpio3
,
3308 &omap3xxx_l4_per__gpio4
,
3309 &omap3xxx_l4_per__gpio5
,
3310 &omap3xxx_l4_per__gpio6
,
3311 &omap3xxx_dma_system__l3
,
3312 &omap3xxx_l4_core__dma_system
,
3313 &omap3xxx_l4_core__mcbsp1
,
3314 &omap3xxx_l4_per__mcbsp2
,
3315 &omap3xxx_l4_per__mcbsp3
,
3316 &omap3xxx_l4_per__mcbsp4
,
3317 &omap3xxx_l4_core__mcbsp5
,
3318 &omap3xxx_l4_per__mcbsp2_sidetone
,
3319 &omap3xxx_l4_per__mcbsp3_sidetone
,
3320 &omap34xx_l4_core__mcspi1
,
3321 &omap34xx_l4_core__mcspi2
,
3322 &omap34xx_l4_core__mcspi3
,
3323 &omap34xx_l4_core__mcspi4
,
3324 &omap3xxx_l4_wkup__counter_32k
,
3328 /* GP-only hwmod links */
3329 static struct omap_hwmod_ocp_if
*omap3xxx_gp_hwmod_ocp_ifs
[] __initdata
= {
3330 &omap3xxx_l4_sec__timer12
,
3334 /* 3430ES1-only hwmod links */
3335 static struct omap_hwmod_ocp_if
*omap3430es1_hwmod_ocp_ifs
[] __initdata
= {
3336 &omap3430es1_dss__l3
,
3337 &omap3430es1_l4_core__dss
,
3341 /* 3430ES2+-only hwmod links */
3342 static struct omap_hwmod_ocp_if
*omap3430es2plus_hwmod_ocp_ifs
[] __initdata
= {
3344 &omap3xxx_l4_core__dss
,
3345 &omap3xxx_usbhsotg__l3
,
3346 &omap3xxx_l4_core__usbhsotg
,
3347 &omap3xxx_usb_host_hs__l3_main_2
,
3348 &omap3xxx_l4_core__usb_host_hs
,
3349 &omap3xxx_l4_core__usb_tll_hs
,
3353 /* <= 3430ES3-only hwmod links */
3354 static struct omap_hwmod_ocp_if
*omap3430_pre_es3_hwmod_ocp_ifs
[] __initdata
= {
3355 &omap3xxx_l4_core__pre_es3_mmc1
,
3356 &omap3xxx_l4_core__pre_es3_mmc2
,
3360 /* 3430ES3+-only hwmod links */
3361 static struct omap_hwmod_ocp_if
*omap3430_es3plus_hwmod_ocp_ifs
[] __initdata
= {
3362 &omap3xxx_l4_core__es3plus_mmc1
,
3363 &omap3xxx_l4_core__es3plus_mmc2
,
3367 /* 34xx-only hwmod links (all ES revisions) */
3368 static struct omap_hwmod_ocp_if
*omap34xx_hwmod_ocp_ifs
[] __initdata
= {
3370 &omap34xx_l4_core__sr1
,
3371 &omap34xx_l4_core__sr2
,
3372 &omap3xxx_l4_core__mailbox
,
3373 &omap3xxx_l4_core__hdq1w
,
3377 /* 36xx-only hwmod links (all ES revisions) */
3378 static struct omap_hwmod_ocp_if
*omap36xx_hwmod_ocp_ifs
[] __initdata
= {
3380 &omap36xx_l4_per__uart4
,
3382 &omap3xxx_l4_core__dss
,
3383 &omap36xx_l4_core__sr1
,
3384 &omap36xx_l4_core__sr2
,
3385 &omap3xxx_usbhsotg__l3
,
3386 &omap3xxx_l4_core__usbhsotg
,
3387 &omap3xxx_l4_core__mailbox
,
3388 &omap3xxx_usb_host_hs__l3_main_2
,
3389 &omap3xxx_l4_core__usb_host_hs
,
3390 &omap3xxx_l4_core__usb_tll_hs
,
3391 &omap3xxx_l4_core__es3plus_mmc1
,
3392 &omap3xxx_l4_core__es3plus_mmc2
,
3393 &omap3xxx_l4_core__hdq1w
,
3397 static struct omap_hwmod_ocp_if
*am35xx_hwmod_ocp_ifs
[] __initdata
= {
3399 &omap3xxx_l4_core__dss
,
3400 &am35xx_usbhsotg__l3
,
3401 &am35xx_l4_core__usbhsotg
,
3402 &am35xx_l4_core__uart4
,
3403 &omap3xxx_usb_host_hs__l3_main_2
,
3404 &omap3xxx_l4_core__usb_host_hs
,
3405 &omap3xxx_l4_core__usb_tll_hs
,
3406 &omap3xxx_l4_core__es3plus_mmc1
,
3407 &omap3xxx_l4_core__es3plus_mmc2
,
3409 &am35xx_l4_core__mdio
,
3411 &am35xx_l4_core__emac
,
3415 static struct omap_hwmod_ocp_if
*omap3xxx_dss_hwmod_ocp_ifs
[] __initdata
= {
3416 &omap3xxx_l4_core__dss_dispc
,
3417 &omap3xxx_l4_core__dss_dsi1
,
3418 &omap3xxx_l4_core__dss_rfbi
,
3419 &omap3xxx_l4_core__dss_venc
,
3423 int __init
omap3xxx_hwmod_init(void)
3426 struct omap_hwmod_ocp_if
**h
= NULL
;
3431 /* Register hwmod links common to all OMAP3 */
3432 r
= omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs
);
3436 /* Register GP-only hwmod links. */
3437 if (omap_type() == OMAP2_DEVICE_TYPE_GP
) {
3438 r
= omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs
);
3446 * Register hwmod links common to individual OMAP3 families, all
3447 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3448 * All possible revisions should be included in this conditional.
3450 if (rev
== OMAP3430_REV_ES1_0
|| rev
== OMAP3430_REV_ES2_0
||
3451 rev
== OMAP3430_REV_ES2_1
|| rev
== OMAP3430_REV_ES3_0
||
3452 rev
== OMAP3430_REV_ES3_1
|| rev
== OMAP3430_REV_ES3_1_2
) {
3453 h
= omap34xx_hwmod_ocp_ifs
;
3454 } else if (rev
== AM35XX_REV_ES1_0
|| rev
== AM35XX_REV_ES1_1
) {
3455 h
= am35xx_hwmod_ocp_ifs
;
3456 } else if (rev
== OMAP3630_REV_ES1_0
|| rev
== OMAP3630_REV_ES1_1
||
3457 rev
== OMAP3630_REV_ES1_2
) {
3458 h
= omap36xx_hwmod_ocp_ifs
;
3460 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3464 r
= omap_hwmod_register_links(h
);
3469 * Register hwmod links specific to certain ES levels of a
3470 * particular family of silicon (e.g., 34xx ES1.0)
3473 if (rev
== OMAP3430_REV_ES1_0
) {
3474 h
= omap3430es1_hwmod_ocp_ifs
;
3475 } else if (rev
== OMAP3430_REV_ES2_0
|| rev
== OMAP3430_REV_ES2_1
||
3476 rev
== OMAP3430_REV_ES3_0
|| rev
== OMAP3430_REV_ES3_1
||
3477 rev
== OMAP3430_REV_ES3_1_2
) {
3478 h
= omap3430es2plus_hwmod_ocp_ifs
;
3482 r
= omap_hwmod_register_links(h
);
3488 if (rev
== OMAP3430_REV_ES1_0
|| rev
== OMAP3430_REV_ES2_0
||
3489 rev
== OMAP3430_REV_ES2_1
) {
3490 h
= omap3430_pre_es3_hwmod_ocp_ifs
;
3491 } else if (rev
== OMAP3430_REV_ES3_0
|| rev
== OMAP3430_REV_ES3_1
||
3492 rev
== OMAP3430_REV_ES3_1_2
) {
3493 h
= omap3430_es3plus_hwmod_ocp_ifs
;
3497 r
= omap_hwmod_register_links(h
);
3502 * DSS code presumes that dss_core hwmod is handled first,
3503 * _before_ any other DSS related hwmods so register common
3504 * DSS hwmod links last to ensure that dss_core is already
3505 * registered. Otherwise some change things may happen, for
3506 * ex. if dispc is handled before dss_core and DSS is enabled
3507 * in bootloader DISPC will be reset with outputs enabled
3508 * which sometimes leads to unrecoverable L3 error. XXX The
3509 * long-term fix to this is to ensure hwmods are set up in
3510 * dependency order in the hwmod core code.
3512 r
= omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs
);