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Merge branch 'for-chris' of git://git.jan-o-sch.net/btrfs-unstable into for-linus
[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_3xxx_data.c
1 /*
2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
3 *
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * The data in this file should be completely autogeneratable from
12 * the TI hardware database or other technical documentation.
13 *
14 * XXX these should be marked initdata for multi-OMAP kernels
15 */
16 #include <plat/omap_hwmod.h>
17 #include <mach/irqs.h>
18 #include <plat/cpu.h>
19 #include <plat/dma.h>
20 #include <plat/serial.h>
21 #include <plat/l3_3xxx.h>
22 #include <plat/l4_3xxx.h>
23 #include <plat/i2c.h>
24 #include <plat/gpio.h>
25 #include <plat/mmc.h>
26 #include <plat/mcbsp.h>
27 #include <plat/mcspi.h>
28 #include <plat/dmtimer.h>
29
30 #include "omap_hwmod_common_data.h"
31
32 #include "smartreflex.h"
33 #include "prm-regbits-34xx.h"
34 #include "cm-regbits-34xx.h"
35 #include "wd_timer.h"
36 #include <mach/am35xx.h>
37
38 /*
39 * OMAP3xxx hardware module integration data
40 *
41 * ALl of the data in this section should be autogeneratable from the
42 * TI hardware database or other technical documentation. Data that
43 * is driver-specific or driver-kernel integration-specific belongs
44 * elsewhere.
45 */
46
47 static struct omap_hwmod omap3xxx_mpu_hwmod;
48 static struct omap_hwmod omap3xxx_iva_hwmod;
49 static struct omap_hwmod omap3xxx_l3_main_hwmod;
50 static struct omap_hwmod omap3xxx_l4_core_hwmod;
51 static struct omap_hwmod omap3xxx_l4_per_hwmod;
52 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
53 static struct omap_hwmod omap3430es1_dss_core_hwmod;
54 static struct omap_hwmod omap3xxx_dss_core_hwmod;
55 static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
56 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
57 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
58 static struct omap_hwmod omap3xxx_dss_venc_hwmod;
59 static struct omap_hwmod omap3xxx_i2c1_hwmod;
60 static struct omap_hwmod omap3xxx_i2c2_hwmod;
61 static struct omap_hwmod omap3xxx_i2c3_hwmod;
62 static struct omap_hwmod omap3xxx_gpio1_hwmod;
63 static struct omap_hwmod omap3xxx_gpio2_hwmod;
64 static struct omap_hwmod omap3xxx_gpio3_hwmod;
65 static struct omap_hwmod omap3xxx_gpio4_hwmod;
66 static struct omap_hwmod omap3xxx_gpio5_hwmod;
67 static struct omap_hwmod omap3xxx_gpio6_hwmod;
68 static struct omap_hwmod omap34xx_sr1_hwmod;
69 static struct omap_hwmod omap34xx_sr2_hwmod;
70 static struct omap_hwmod omap34xx_mcspi1;
71 static struct omap_hwmod omap34xx_mcspi2;
72 static struct omap_hwmod omap34xx_mcspi3;
73 static struct omap_hwmod omap34xx_mcspi4;
74 static struct omap_hwmod omap3xxx_mmc1_hwmod;
75 static struct omap_hwmod omap3xxx_mmc2_hwmod;
76 static struct omap_hwmod omap3xxx_mmc3_hwmod;
77 static struct omap_hwmod am35xx_usbhsotg_hwmod;
78
79 static struct omap_hwmod omap3xxx_dma_system_hwmod;
80
81 static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
82 static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
83 static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
84 static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
85 static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
86 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
87 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
88 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod;
89 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod;
90
91 /* L3 -> L4_CORE interface */
92 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
93 .master = &omap3xxx_l3_main_hwmod,
94 .slave = &omap3xxx_l4_core_hwmod,
95 .user = OCP_USER_MPU | OCP_USER_SDMA,
96 };
97
98 /* L3 -> L4_PER interface */
99 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
100 .master = &omap3xxx_l3_main_hwmod,
101 .slave = &omap3xxx_l4_per_hwmod,
102 .user = OCP_USER_MPU | OCP_USER_SDMA,
103 };
104
105 /* L3 taret configuration and error log registers */
106 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
107 { .irq = INT_34XX_L3_DBG_IRQ },
108 { .irq = INT_34XX_L3_APP_IRQ },
109 { .irq = -1 }
110 };
111
112 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
113 {
114 .pa_start = 0x68000000,
115 .pa_end = 0x6800ffff,
116 .flags = ADDR_TYPE_RT,
117 },
118 { }
119 };
120
121 /* MPU -> L3 interface */
122 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
123 .master = &omap3xxx_mpu_hwmod,
124 .slave = &omap3xxx_l3_main_hwmod,
125 .addr = omap3xxx_l3_main_addrs,
126 .user = OCP_USER_MPU,
127 };
128
129 /* Slave interfaces on the L3 interconnect */
130 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
131 &omap3xxx_mpu__l3_main,
132 };
133
134 /* DSS -> l3 */
135 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
136 .master = &omap3xxx_dss_core_hwmod,
137 .slave = &omap3xxx_l3_main_hwmod,
138 .fw = {
139 .omap2 = {
140 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
141 .flags = OMAP_FIREWALL_L3,
142 }
143 },
144 .user = OCP_USER_MPU | OCP_USER_SDMA,
145 };
146
147 /* Master interfaces on the L3 interconnect */
148 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
149 &omap3xxx_l3_main__l4_core,
150 &omap3xxx_l3_main__l4_per,
151 };
152
153 /* L3 */
154 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
155 .name = "l3_main",
156 .class = &l3_hwmod_class,
157 .mpu_irqs = omap3xxx_l3_main_irqs,
158 .masters = omap3xxx_l3_main_masters,
159 .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
160 .slaves = omap3xxx_l3_main_slaves,
161 .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves),
162 .flags = HWMOD_NO_IDLEST,
163 };
164
165 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
166 static struct omap_hwmod omap3xxx_uart1_hwmod;
167 static struct omap_hwmod omap3xxx_uart2_hwmod;
168 static struct omap_hwmod omap3xxx_uart3_hwmod;
169 static struct omap_hwmod omap3xxx_uart4_hwmod;
170 static struct omap_hwmod am35xx_uart4_hwmod;
171 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
172
173 /* l3_core -> usbhsotg interface */
174 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
175 .master = &omap3xxx_usbhsotg_hwmod,
176 .slave = &omap3xxx_l3_main_hwmod,
177 .clk = "core_l3_ick",
178 .user = OCP_USER_MPU,
179 };
180
181 /* l3_core -> am35xx_usbhsotg interface */
182 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
183 .master = &am35xx_usbhsotg_hwmod,
184 .slave = &omap3xxx_l3_main_hwmod,
185 .clk = "core_l3_ick",
186 .user = OCP_USER_MPU,
187 };
188 /* L4_CORE -> L4_WKUP interface */
189 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
190 .master = &omap3xxx_l4_core_hwmod,
191 .slave = &omap3xxx_l4_wkup_hwmod,
192 .user = OCP_USER_MPU | OCP_USER_SDMA,
193 };
194
195 /* L4 CORE -> MMC1 interface */
196 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
197 .master = &omap3xxx_l4_core_hwmod,
198 .slave = &omap3xxx_mmc1_hwmod,
199 .clk = "mmchs1_ick",
200 .addr = omap2430_mmc1_addr_space,
201 .user = OCP_USER_MPU | OCP_USER_SDMA,
202 .flags = OMAP_FIREWALL_L4
203 };
204
205 /* L4 CORE -> MMC2 interface */
206 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
207 .master = &omap3xxx_l4_core_hwmod,
208 .slave = &omap3xxx_mmc2_hwmod,
209 .clk = "mmchs2_ick",
210 .addr = omap2430_mmc2_addr_space,
211 .user = OCP_USER_MPU | OCP_USER_SDMA,
212 .flags = OMAP_FIREWALL_L4
213 };
214
215 /* L4 CORE -> MMC3 interface */
216 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
217 {
218 .pa_start = 0x480ad000,
219 .pa_end = 0x480ad1ff,
220 .flags = ADDR_TYPE_RT,
221 },
222 { }
223 };
224
225 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
226 .master = &omap3xxx_l4_core_hwmod,
227 .slave = &omap3xxx_mmc3_hwmod,
228 .clk = "mmchs3_ick",
229 .addr = omap3xxx_mmc3_addr_space,
230 .user = OCP_USER_MPU | OCP_USER_SDMA,
231 .flags = OMAP_FIREWALL_L4
232 };
233
234 /* L4 CORE -> UART1 interface */
235 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
236 {
237 .pa_start = OMAP3_UART1_BASE,
238 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
239 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
240 },
241 { }
242 };
243
244 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
245 .master = &omap3xxx_l4_core_hwmod,
246 .slave = &omap3xxx_uart1_hwmod,
247 .clk = "uart1_ick",
248 .addr = omap3xxx_uart1_addr_space,
249 .user = OCP_USER_MPU | OCP_USER_SDMA,
250 };
251
252 /* L4 CORE -> UART2 interface */
253 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
254 {
255 .pa_start = OMAP3_UART2_BASE,
256 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
257 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
258 },
259 { }
260 };
261
262 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
263 .master = &omap3xxx_l4_core_hwmod,
264 .slave = &omap3xxx_uart2_hwmod,
265 .clk = "uart2_ick",
266 .addr = omap3xxx_uart2_addr_space,
267 .user = OCP_USER_MPU | OCP_USER_SDMA,
268 };
269
270 /* L4 PER -> UART3 interface */
271 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
272 {
273 .pa_start = OMAP3_UART3_BASE,
274 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
275 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
276 },
277 { }
278 };
279
280 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
281 .master = &omap3xxx_l4_per_hwmod,
282 .slave = &omap3xxx_uart3_hwmod,
283 .clk = "uart3_ick",
284 .addr = omap3xxx_uart3_addr_space,
285 .user = OCP_USER_MPU | OCP_USER_SDMA,
286 };
287
288 /* L4 PER -> UART4 interface */
289 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
290 {
291 .pa_start = OMAP3_UART4_BASE,
292 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
293 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
294 },
295 { }
296 };
297
298 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
299 .master = &omap3xxx_l4_per_hwmod,
300 .slave = &omap3xxx_uart4_hwmod,
301 .clk = "uart4_ick",
302 .addr = omap3xxx_uart4_addr_space,
303 .user = OCP_USER_MPU | OCP_USER_SDMA,
304 };
305
306 /* AM35xx: L4 CORE -> UART4 interface */
307 static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
308 {
309 .pa_start = OMAP3_UART4_AM35XX_BASE,
310 .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
311 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
312 },
313 };
314
315 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
316 .master = &omap3xxx_l4_core_hwmod,
317 .slave = &am35xx_uart4_hwmod,
318 .clk = "uart4_ick",
319 .addr = am35xx_uart4_addr_space,
320 .user = OCP_USER_MPU | OCP_USER_SDMA,
321 };
322
323 /* L4 CORE -> I2C1 interface */
324 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
325 .master = &omap3xxx_l4_core_hwmod,
326 .slave = &omap3xxx_i2c1_hwmod,
327 .clk = "i2c1_ick",
328 .addr = omap2_i2c1_addr_space,
329 .fw = {
330 .omap2 = {
331 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
332 .l4_prot_group = 7,
333 .flags = OMAP_FIREWALL_L4,
334 }
335 },
336 .user = OCP_USER_MPU | OCP_USER_SDMA,
337 };
338
339 /* L4 CORE -> I2C2 interface */
340 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
341 .master = &omap3xxx_l4_core_hwmod,
342 .slave = &omap3xxx_i2c2_hwmod,
343 .clk = "i2c2_ick",
344 .addr = omap2_i2c2_addr_space,
345 .fw = {
346 .omap2 = {
347 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
348 .l4_prot_group = 7,
349 .flags = OMAP_FIREWALL_L4,
350 }
351 },
352 .user = OCP_USER_MPU | OCP_USER_SDMA,
353 };
354
355 /* L4 CORE -> I2C3 interface */
356 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
357 {
358 .pa_start = 0x48060000,
359 .pa_end = 0x48060000 + SZ_128 - 1,
360 .flags = ADDR_TYPE_RT,
361 },
362 { }
363 };
364
365 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
366 .master = &omap3xxx_l4_core_hwmod,
367 .slave = &omap3xxx_i2c3_hwmod,
368 .clk = "i2c3_ick",
369 .addr = omap3xxx_i2c3_addr_space,
370 .fw = {
371 .omap2 = {
372 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
373 .l4_prot_group = 7,
374 .flags = OMAP_FIREWALL_L4,
375 }
376 },
377 .user = OCP_USER_MPU | OCP_USER_SDMA,
378 };
379
380 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
381 { .irq = 18},
382 { .irq = -1 }
383 };
384
385 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
386 { .irq = 19},
387 { .irq = -1 }
388 };
389
390 /* L4 CORE -> SR1 interface */
391 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
392 {
393 .pa_start = OMAP34XX_SR1_BASE,
394 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
395 .flags = ADDR_TYPE_RT,
396 },
397 { }
398 };
399
400 static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
401 .master = &omap3xxx_l4_core_hwmod,
402 .slave = &omap34xx_sr1_hwmod,
403 .clk = "sr_l4_ick",
404 .addr = omap3_sr1_addr_space,
405 .user = OCP_USER_MPU,
406 };
407
408 /* L4 CORE -> SR1 interface */
409 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
410 {
411 .pa_start = OMAP34XX_SR2_BASE,
412 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
413 .flags = ADDR_TYPE_RT,
414 },
415 { }
416 };
417
418 static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
419 .master = &omap3xxx_l4_core_hwmod,
420 .slave = &omap34xx_sr2_hwmod,
421 .clk = "sr_l4_ick",
422 .addr = omap3_sr2_addr_space,
423 .user = OCP_USER_MPU,
424 };
425
426 /*
427 * usbhsotg interface data
428 */
429
430 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
431 {
432 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
433 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
434 .flags = ADDR_TYPE_RT
435 },
436 { }
437 };
438
439 /* l4_core -> usbhsotg */
440 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
441 .master = &omap3xxx_l4_core_hwmod,
442 .slave = &omap3xxx_usbhsotg_hwmod,
443 .clk = "l4_ick",
444 .addr = omap3xxx_usbhsotg_addrs,
445 .user = OCP_USER_MPU,
446 };
447
448 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
449 &omap3xxx_usbhsotg__l3,
450 };
451
452 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
453 &omap3xxx_l4_core__usbhsotg,
454 };
455
456 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
457 {
458 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
459 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
460 .flags = ADDR_TYPE_RT
461 },
462 { }
463 };
464
465 /* l4_core -> usbhsotg */
466 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
467 .master = &omap3xxx_l4_core_hwmod,
468 .slave = &am35xx_usbhsotg_hwmod,
469 .clk = "l4_ick",
470 .addr = am35xx_usbhsotg_addrs,
471 .user = OCP_USER_MPU,
472 };
473
474 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
475 &am35xx_usbhsotg__l3,
476 };
477
478 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
479 &am35xx_l4_core__usbhsotg,
480 };
481 /* Slave interfaces on the L4_CORE interconnect */
482 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
483 &omap3xxx_l3_main__l4_core,
484 };
485
486 /* L4 CORE */
487 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
488 .name = "l4_core",
489 .class = &l4_hwmod_class,
490 .slaves = omap3xxx_l4_core_slaves,
491 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves),
492 .flags = HWMOD_NO_IDLEST,
493 };
494
495 /* Slave interfaces on the L4_PER interconnect */
496 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
497 &omap3xxx_l3_main__l4_per,
498 };
499
500 /* L4 PER */
501 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
502 .name = "l4_per",
503 .class = &l4_hwmod_class,
504 .slaves = omap3xxx_l4_per_slaves,
505 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves),
506 .flags = HWMOD_NO_IDLEST,
507 };
508
509 /* Slave interfaces on the L4_WKUP interconnect */
510 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
511 &omap3xxx_l4_core__l4_wkup,
512 };
513
514 /* L4 WKUP */
515 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
516 .name = "l4_wkup",
517 .class = &l4_hwmod_class,
518 .slaves = omap3xxx_l4_wkup_slaves,
519 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
520 .flags = HWMOD_NO_IDLEST,
521 };
522
523 /* Master interfaces on the MPU device */
524 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
525 &omap3xxx_mpu__l3_main,
526 };
527
528 /* MPU */
529 static struct omap_hwmod omap3xxx_mpu_hwmod = {
530 .name = "mpu",
531 .class = &mpu_hwmod_class,
532 .main_clk = "arm_fck",
533 .masters = omap3xxx_mpu_masters,
534 .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters),
535 };
536
537 /*
538 * IVA2_2 interface data
539 */
540
541 /* IVA2 <- L3 interface */
542 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
543 .master = &omap3xxx_l3_main_hwmod,
544 .slave = &omap3xxx_iva_hwmod,
545 .clk = "iva2_ck",
546 .user = OCP_USER_MPU | OCP_USER_SDMA,
547 };
548
549 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
550 &omap3xxx_l3__iva,
551 };
552
553 /*
554 * IVA2 (IVA2)
555 */
556
557 static struct omap_hwmod omap3xxx_iva_hwmod = {
558 .name = "iva",
559 .class = &iva_hwmod_class,
560 .masters = omap3xxx_iva_masters,
561 .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters),
562 };
563
564 /* timer class */
565 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
566 .rev_offs = 0x0000,
567 .sysc_offs = 0x0010,
568 .syss_offs = 0x0014,
569 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
570 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
571 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
572 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
573 .sysc_fields = &omap_hwmod_sysc_type1,
574 };
575
576 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
577 .name = "timer",
578 .sysc = &omap3xxx_timer_1ms_sysc,
579 .rev = OMAP_TIMER_IP_VERSION_1,
580 };
581
582 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
583 .rev_offs = 0x0000,
584 .sysc_offs = 0x0010,
585 .syss_offs = 0x0014,
586 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
587 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
588 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
589 .sysc_fields = &omap_hwmod_sysc_type1,
590 };
591
592 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
593 .name = "timer",
594 .sysc = &omap3xxx_timer_sysc,
595 .rev = OMAP_TIMER_IP_VERSION_1,
596 };
597
598 /* secure timers dev attribute */
599 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
600 .timer_capability = OMAP_TIMER_SECURE,
601 };
602
603 /* always-on timers dev attribute */
604 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
605 .timer_capability = OMAP_TIMER_ALWON,
606 };
607
608 /* pwm timers dev attribute */
609 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
610 .timer_capability = OMAP_TIMER_HAS_PWM,
611 };
612
613 /* timer1 */
614 static struct omap_hwmod omap3xxx_timer1_hwmod;
615
616 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
617 {
618 .pa_start = 0x48318000,
619 .pa_end = 0x48318000 + SZ_1K - 1,
620 .flags = ADDR_TYPE_RT
621 },
622 { }
623 };
624
625 /* l4_wkup -> timer1 */
626 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
627 .master = &omap3xxx_l4_wkup_hwmod,
628 .slave = &omap3xxx_timer1_hwmod,
629 .clk = "gpt1_ick",
630 .addr = omap3xxx_timer1_addrs,
631 .user = OCP_USER_MPU | OCP_USER_SDMA,
632 };
633
634 /* timer1 slave port */
635 static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
636 &omap3xxx_l4_wkup__timer1,
637 };
638
639 /* timer1 hwmod */
640 static struct omap_hwmod omap3xxx_timer1_hwmod = {
641 .name = "timer1",
642 .mpu_irqs = omap2_timer1_mpu_irqs,
643 .main_clk = "gpt1_fck",
644 .prcm = {
645 .omap2 = {
646 .prcm_reg_id = 1,
647 .module_bit = OMAP3430_EN_GPT1_SHIFT,
648 .module_offs = WKUP_MOD,
649 .idlest_reg_id = 1,
650 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
651 },
652 },
653 .dev_attr = &capability_alwon_dev_attr,
654 .slaves = omap3xxx_timer1_slaves,
655 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer1_slaves),
656 .class = &omap3xxx_timer_1ms_hwmod_class,
657 };
658
659 /* timer2 */
660 static struct omap_hwmod omap3xxx_timer2_hwmod;
661
662 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
663 {
664 .pa_start = 0x49032000,
665 .pa_end = 0x49032000 + SZ_1K - 1,
666 .flags = ADDR_TYPE_RT
667 },
668 { }
669 };
670
671 /* l4_per -> timer2 */
672 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
673 .master = &omap3xxx_l4_per_hwmod,
674 .slave = &omap3xxx_timer2_hwmod,
675 .clk = "gpt2_ick",
676 .addr = omap3xxx_timer2_addrs,
677 .user = OCP_USER_MPU | OCP_USER_SDMA,
678 };
679
680 /* timer2 slave port */
681 static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
682 &omap3xxx_l4_per__timer2,
683 };
684
685 /* timer2 hwmod */
686 static struct omap_hwmod omap3xxx_timer2_hwmod = {
687 .name = "timer2",
688 .mpu_irqs = omap2_timer2_mpu_irqs,
689 .main_clk = "gpt2_fck",
690 .prcm = {
691 .omap2 = {
692 .prcm_reg_id = 1,
693 .module_bit = OMAP3430_EN_GPT2_SHIFT,
694 .module_offs = OMAP3430_PER_MOD,
695 .idlest_reg_id = 1,
696 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
697 },
698 },
699 .dev_attr = &capability_alwon_dev_attr,
700 .slaves = omap3xxx_timer2_slaves,
701 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer2_slaves),
702 .class = &omap3xxx_timer_1ms_hwmod_class,
703 };
704
705 /* timer3 */
706 static struct omap_hwmod omap3xxx_timer3_hwmod;
707
708 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
709 {
710 .pa_start = 0x49034000,
711 .pa_end = 0x49034000 + SZ_1K - 1,
712 .flags = ADDR_TYPE_RT
713 },
714 { }
715 };
716
717 /* l4_per -> timer3 */
718 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
719 .master = &omap3xxx_l4_per_hwmod,
720 .slave = &omap3xxx_timer3_hwmod,
721 .clk = "gpt3_ick",
722 .addr = omap3xxx_timer3_addrs,
723 .user = OCP_USER_MPU | OCP_USER_SDMA,
724 };
725
726 /* timer3 slave port */
727 static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
728 &omap3xxx_l4_per__timer3,
729 };
730
731 /* timer3 hwmod */
732 static struct omap_hwmod omap3xxx_timer3_hwmod = {
733 .name = "timer3",
734 .mpu_irqs = omap2_timer3_mpu_irqs,
735 .main_clk = "gpt3_fck",
736 .prcm = {
737 .omap2 = {
738 .prcm_reg_id = 1,
739 .module_bit = OMAP3430_EN_GPT3_SHIFT,
740 .module_offs = OMAP3430_PER_MOD,
741 .idlest_reg_id = 1,
742 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
743 },
744 },
745 .dev_attr = &capability_alwon_dev_attr,
746 .slaves = omap3xxx_timer3_slaves,
747 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer3_slaves),
748 .class = &omap3xxx_timer_hwmod_class,
749 };
750
751 /* timer4 */
752 static struct omap_hwmod omap3xxx_timer4_hwmod;
753
754 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
755 {
756 .pa_start = 0x49036000,
757 .pa_end = 0x49036000 + SZ_1K - 1,
758 .flags = ADDR_TYPE_RT
759 },
760 { }
761 };
762
763 /* l4_per -> timer4 */
764 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
765 .master = &omap3xxx_l4_per_hwmod,
766 .slave = &omap3xxx_timer4_hwmod,
767 .clk = "gpt4_ick",
768 .addr = omap3xxx_timer4_addrs,
769 .user = OCP_USER_MPU | OCP_USER_SDMA,
770 };
771
772 /* timer4 slave port */
773 static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
774 &omap3xxx_l4_per__timer4,
775 };
776
777 /* timer4 hwmod */
778 static struct omap_hwmod omap3xxx_timer4_hwmod = {
779 .name = "timer4",
780 .mpu_irqs = omap2_timer4_mpu_irqs,
781 .main_clk = "gpt4_fck",
782 .prcm = {
783 .omap2 = {
784 .prcm_reg_id = 1,
785 .module_bit = OMAP3430_EN_GPT4_SHIFT,
786 .module_offs = OMAP3430_PER_MOD,
787 .idlest_reg_id = 1,
788 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
789 },
790 },
791 .dev_attr = &capability_alwon_dev_attr,
792 .slaves = omap3xxx_timer4_slaves,
793 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer4_slaves),
794 .class = &omap3xxx_timer_hwmod_class,
795 };
796
797 /* timer5 */
798 static struct omap_hwmod omap3xxx_timer5_hwmod;
799
800 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
801 {
802 .pa_start = 0x49038000,
803 .pa_end = 0x49038000 + SZ_1K - 1,
804 .flags = ADDR_TYPE_RT
805 },
806 { }
807 };
808
809 /* l4_per -> timer5 */
810 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
811 .master = &omap3xxx_l4_per_hwmod,
812 .slave = &omap3xxx_timer5_hwmod,
813 .clk = "gpt5_ick",
814 .addr = omap3xxx_timer5_addrs,
815 .user = OCP_USER_MPU | OCP_USER_SDMA,
816 };
817
818 /* timer5 slave port */
819 static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
820 &omap3xxx_l4_per__timer5,
821 };
822
823 /* timer5 hwmod */
824 static struct omap_hwmod omap3xxx_timer5_hwmod = {
825 .name = "timer5",
826 .mpu_irqs = omap2_timer5_mpu_irqs,
827 .main_clk = "gpt5_fck",
828 .prcm = {
829 .omap2 = {
830 .prcm_reg_id = 1,
831 .module_bit = OMAP3430_EN_GPT5_SHIFT,
832 .module_offs = OMAP3430_PER_MOD,
833 .idlest_reg_id = 1,
834 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
835 },
836 },
837 .dev_attr = &capability_alwon_dev_attr,
838 .slaves = omap3xxx_timer5_slaves,
839 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer5_slaves),
840 .class = &omap3xxx_timer_hwmod_class,
841 };
842
843 /* timer6 */
844 static struct omap_hwmod omap3xxx_timer6_hwmod;
845
846 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
847 {
848 .pa_start = 0x4903A000,
849 .pa_end = 0x4903A000 + SZ_1K - 1,
850 .flags = ADDR_TYPE_RT
851 },
852 { }
853 };
854
855 /* l4_per -> timer6 */
856 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
857 .master = &omap3xxx_l4_per_hwmod,
858 .slave = &omap3xxx_timer6_hwmod,
859 .clk = "gpt6_ick",
860 .addr = omap3xxx_timer6_addrs,
861 .user = OCP_USER_MPU | OCP_USER_SDMA,
862 };
863
864 /* timer6 slave port */
865 static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
866 &omap3xxx_l4_per__timer6,
867 };
868
869 /* timer6 hwmod */
870 static struct omap_hwmod omap3xxx_timer6_hwmod = {
871 .name = "timer6",
872 .mpu_irqs = omap2_timer6_mpu_irqs,
873 .main_clk = "gpt6_fck",
874 .prcm = {
875 .omap2 = {
876 .prcm_reg_id = 1,
877 .module_bit = OMAP3430_EN_GPT6_SHIFT,
878 .module_offs = OMAP3430_PER_MOD,
879 .idlest_reg_id = 1,
880 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
881 },
882 },
883 .dev_attr = &capability_alwon_dev_attr,
884 .slaves = omap3xxx_timer6_slaves,
885 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer6_slaves),
886 .class = &omap3xxx_timer_hwmod_class,
887 };
888
889 /* timer7 */
890 static struct omap_hwmod omap3xxx_timer7_hwmod;
891
892 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
893 {
894 .pa_start = 0x4903C000,
895 .pa_end = 0x4903C000 + SZ_1K - 1,
896 .flags = ADDR_TYPE_RT
897 },
898 { }
899 };
900
901 /* l4_per -> timer7 */
902 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
903 .master = &omap3xxx_l4_per_hwmod,
904 .slave = &omap3xxx_timer7_hwmod,
905 .clk = "gpt7_ick",
906 .addr = omap3xxx_timer7_addrs,
907 .user = OCP_USER_MPU | OCP_USER_SDMA,
908 };
909
910 /* timer7 slave port */
911 static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
912 &omap3xxx_l4_per__timer7,
913 };
914
915 /* timer7 hwmod */
916 static struct omap_hwmod omap3xxx_timer7_hwmod = {
917 .name = "timer7",
918 .mpu_irqs = omap2_timer7_mpu_irqs,
919 .main_clk = "gpt7_fck",
920 .prcm = {
921 .omap2 = {
922 .prcm_reg_id = 1,
923 .module_bit = OMAP3430_EN_GPT7_SHIFT,
924 .module_offs = OMAP3430_PER_MOD,
925 .idlest_reg_id = 1,
926 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
927 },
928 },
929 .dev_attr = &capability_alwon_dev_attr,
930 .slaves = omap3xxx_timer7_slaves,
931 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer7_slaves),
932 .class = &omap3xxx_timer_hwmod_class,
933 };
934
935 /* timer8 */
936 static struct omap_hwmod omap3xxx_timer8_hwmod;
937
938 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
939 {
940 .pa_start = 0x4903E000,
941 .pa_end = 0x4903E000 + SZ_1K - 1,
942 .flags = ADDR_TYPE_RT
943 },
944 { }
945 };
946
947 /* l4_per -> timer8 */
948 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
949 .master = &omap3xxx_l4_per_hwmod,
950 .slave = &omap3xxx_timer8_hwmod,
951 .clk = "gpt8_ick",
952 .addr = omap3xxx_timer8_addrs,
953 .user = OCP_USER_MPU | OCP_USER_SDMA,
954 };
955
956 /* timer8 slave port */
957 static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
958 &omap3xxx_l4_per__timer8,
959 };
960
961 /* timer8 hwmod */
962 static struct omap_hwmod omap3xxx_timer8_hwmod = {
963 .name = "timer8",
964 .mpu_irqs = omap2_timer8_mpu_irqs,
965 .main_clk = "gpt8_fck",
966 .prcm = {
967 .omap2 = {
968 .prcm_reg_id = 1,
969 .module_bit = OMAP3430_EN_GPT8_SHIFT,
970 .module_offs = OMAP3430_PER_MOD,
971 .idlest_reg_id = 1,
972 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
973 },
974 },
975 .dev_attr = &capability_pwm_dev_attr,
976 .slaves = omap3xxx_timer8_slaves,
977 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer8_slaves),
978 .class = &omap3xxx_timer_hwmod_class,
979 };
980
981 /* timer9 */
982 static struct omap_hwmod omap3xxx_timer9_hwmod;
983
984 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
985 {
986 .pa_start = 0x49040000,
987 .pa_end = 0x49040000 + SZ_1K - 1,
988 .flags = ADDR_TYPE_RT
989 },
990 { }
991 };
992
993 /* l4_per -> timer9 */
994 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
995 .master = &omap3xxx_l4_per_hwmod,
996 .slave = &omap3xxx_timer9_hwmod,
997 .clk = "gpt9_ick",
998 .addr = omap3xxx_timer9_addrs,
999 .user = OCP_USER_MPU | OCP_USER_SDMA,
1000 };
1001
1002 /* timer9 slave port */
1003 static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
1004 &omap3xxx_l4_per__timer9,
1005 };
1006
1007 /* timer9 hwmod */
1008 static struct omap_hwmod omap3xxx_timer9_hwmod = {
1009 .name = "timer9",
1010 .mpu_irqs = omap2_timer9_mpu_irqs,
1011 .main_clk = "gpt9_fck",
1012 .prcm = {
1013 .omap2 = {
1014 .prcm_reg_id = 1,
1015 .module_bit = OMAP3430_EN_GPT9_SHIFT,
1016 .module_offs = OMAP3430_PER_MOD,
1017 .idlest_reg_id = 1,
1018 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
1019 },
1020 },
1021 .dev_attr = &capability_pwm_dev_attr,
1022 .slaves = omap3xxx_timer9_slaves,
1023 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer9_slaves),
1024 .class = &omap3xxx_timer_hwmod_class,
1025 };
1026
1027 /* timer10 */
1028 static struct omap_hwmod omap3xxx_timer10_hwmod;
1029
1030 /* l4_core -> timer10 */
1031 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1032 .master = &omap3xxx_l4_core_hwmod,
1033 .slave = &omap3xxx_timer10_hwmod,
1034 .clk = "gpt10_ick",
1035 .addr = omap2_timer10_addrs,
1036 .user = OCP_USER_MPU | OCP_USER_SDMA,
1037 };
1038
1039 /* timer10 slave port */
1040 static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1041 &omap3xxx_l4_core__timer10,
1042 };
1043
1044 /* timer10 hwmod */
1045 static struct omap_hwmod omap3xxx_timer10_hwmod = {
1046 .name = "timer10",
1047 .mpu_irqs = omap2_timer10_mpu_irqs,
1048 .main_clk = "gpt10_fck",
1049 .prcm = {
1050 .omap2 = {
1051 .prcm_reg_id = 1,
1052 .module_bit = OMAP3430_EN_GPT10_SHIFT,
1053 .module_offs = CORE_MOD,
1054 .idlest_reg_id = 1,
1055 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
1056 },
1057 },
1058 .dev_attr = &capability_pwm_dev_attr,
1059 .slaves = omap3xxx_timer10_slaves,
1060 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer10_slaves),
1061 .class = &omap3xxx_timer_1ms_hwmod_class,
1062 };
1063
1064 /* timer11 */
1065 static struct omap_hwmod omap3xxx_timer11_hwmod;
1066
1067 /* l4_core -> timer11 */
1068 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1069 .master = &omap3xxx_l4_core_hwmod,
1070 .slave = &omap3xxx_timer11_hwmod,
1071 .clk = "gpt11_ick",
1072 .addr = omap2_timer11_addrs,
1073 .user = OCP_USER_MPU | OCP_USER_SDMA,
1074 };
1075
1076 /* timer11 slave port */
1077 static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1078 &omap3xxx_l4_core__timer11,
1079 };
1080
1081 /* timer11 hwmod */
1082 static struct omap_hwmod omap3xxx_timer11_hwmod = {
1083 .name = "timer11",
1084 .mpu_irqs = omap2_timer11_mpu_irqs,
1085 .main_clk = "gpt11_fck",
1086 .prcm = {
1087 .omap2 = {
1088 .prcm_reg_id = 1,
1089 .module_bit = OMAP3430_EN_GPT11_SHIFT,
1090 .module_offs = CORE_MOD,
1091 .idlest_reg_id = 1,
1092 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
1093 },
1094 },
1095 .dev_attr = &capability_pwm_dev_attr,
1096 .slaves = omap3xxx_timer11_slaves,
1097 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer11_slaves),
1098 .class = &omap3xxx_timer_hwmod_class,
1099 };
1100
1101 /* timer12*/
1102 static struct omap_hwmod omap3xxx_timer12_hwmod;
1103 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1104 { .irq = 95, },
1105 { .irq = -1 }
1106 };
1107
1108 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1109 {
1110 .pa_start = 0x48304000,
1111 .pa_end = 0x48304000 + SZ_1K - 1,
1112 .flags = ADDR_TYPE_RT
1113 },
1114 { }
1115 };
1116
1117 /* l4_core -> timer12 */
1118 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1119 .master = &omap3xxx_l4_core_hwmod,
1120 .slave = &omap3xxx_timer12_hwmod,
1121 .clk = "gpt12_ick",
1122 .addr = omap3xxx_timer12_addrs,
1123 .user = OCP_USER_MPU | OCP_USER_SDMA,
1124 };
1125
1126 /* timer12 slave port */
1127 static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1128 &omap3xxx_l4_core__timer12,
1129 };
1130
1131 /* timer12 hwmod */
1132 static struct omap_hwmod omap3xxx_timer12_hwmod = {
1133 .name = "timer12",
1134 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
1135 .main_clk = "gpt12_fck",
1136 .prcm = {
1137 .omap2 = {
1138 .prcm_reg_id = 1,
1139 .module_bit = OMAP3430_EN_GPT12_SHIFT,
1140 .module_offs = WKUP_MOD,
1141 .idlest_reg_id = 1,
1142 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
1143 },
1144 },
1145 .dev_attr = &capability_secure_dev_attr,
1146 .slaves = omap3xxx_timer12_slaves,
1147 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer12_slaves),
1148 .class = &omap3xxx_timer_hwmod_class,
1149 };
1150
1151 /* l4_wkup -> wd_timer2 */
1152 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1153 {
1154 .pa_start = 0x48314000,
1155 .pa_end = 0x4831407f,
1156 .flags = ADDR_TYPE_RT
1157 },
1158 { }
1159 };
1160
1161 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1162 .master = &omap3xxx_l4_wkup_hwmod,
1163 .slave = &omap3xxx_wd_timer2_hwmod,
1164 .clk = "wdt2_ick",
1165 .addr = omap3xxx_wd_timer2_addrs,
1166 .user = OCP_USER_MPU | OCP_USER_SDMA,
1167 };
1168
1169 /*
1170 * 'wd_timer' class
1171 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1172 * overflow condition
1173 */
1174
1175 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
1176 .rev_offs = 0x0000,
1177 .sysc_offs = 0x0010,
1178 .syss_offs = 0x0014,
1179 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
1180 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1181 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1182 SYSS_HAS_RESET_STATUS),
1183 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1184 .sysc_fields = &omap_hwmod_sysc_type1,
1185 };
1186
1187 /* I2C common */
1188 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1189 .rev_offs = 0x00,
1190 .sysc_offs = 0x20,
1191 .syss_offs = 0x10,
1192 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1193 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1194 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1195 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1196 .clockact = CLOCKACT_TEST_ICLK,
1197 .sysc_fields = &omap_hwmod_sysc_type1,
1198 };
1199
1200 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
1201 .name = "wd_timer",
1202 .sysc = &omap3xxx_wd_timer_sysc,
1203 .pre_shutdown = &omap2_wd_timer_disable
1204 };
1205
1206 /* wd_timer2 */
1207 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
1208 &omap3xxx_l4_wkup__wd_timer2,
1209 };
1210
1211 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1212 .name = "wd_timer2",
1213 .class = &omap3xxx_wd_timer_hwmod_class,
1214 .main_clk = "wdt2_fck",
1215 .prcm = {
1216 .omap2 = {
1217 .prcm_reg_id = 1,
1218 .module_bit = OMAP3430_EN_WDT2_SHIFT,
1219 .module_offs = WKUP_MOD,
1220 .idlest_reg_id = 1,
1221 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
1222 },
1223 },
1224 .slaves = omap3xxx_wd_timer2_slaves,
1225 .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1226 /*
1227 * XXX: Use software supervised mode, HW supervised smartidle seems to
1228 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
1229 */
1230 .flags = HWMOD_SWSUP_SIDLE,
1231 };
1232
1233 /* UART1 */
1234
1235 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1236 &omap3_l4_core__uart1,
1237 };
1238
1239 static struct omap_hwmod omap3xxx_uart1_hwmod = {
1240 .name = "uart1",
1241 .mpu_irqs = omap2_uart1_mpu_irqs,
1242 .sdma_reqs = omap2_uart1_sdma_reqs,
1243 .main_clk = "uart1_fck",
1244 .prcm = {
1245 .omap2 = {
1246 .module_offs = CORE_MOD,
1247 .prcm_reg_id = 1,
1248 .module_bit = OMAP3430_EN_UART1_SHIFT,
1249 .idlest_reg_id = 1,
1250 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
1251 },
1252 },
1253 .slaves = omap3xxx_uart1_slaves,
1254 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
1255 .class = &omap2_uart_class,
1256 };
1257
1258 /* UART2 */
1259
1260 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1261 &omap3_l4_core__uart2,
1262 };
1263
1264 static struct omap_hwmod omap3xxx_uart2_hwmod = {
1265 .name = "uart2",
1266 .mpu_irqs = omap2_uart2_mpu_irqs,
1267 .sdma_reqs = omap2_uart2_sdma_reqs,
1268 .main_clk = "uart2_fck",
1269 .prcm = {
1270 .omap2 = {
1271 .module_offs = CORE_MOD,
1272 .prcm_reg_id = 1,
1273 .module_bit = OMAP3430_EN_UART2_SHIFT,
1274 .idlest_reg_id = 1,
1275 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
1276 },
1277 },
1278 .slaves = omap3xxx_uart2_slaves,
1279 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
1280 .class = &omap2_uart_class,
1281 };
1282
1283 /* UART3 */
1284
1285 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1286 &omap3_l4_per__uart3,
1287 };
1288
1289 static struct omap_hwmod omap3xxx_uart3_hwmod = {
1290 .name = "uart3",
1291 .mpu_irqs = omap2_uart3_mpu_irqs,
1292 .sdma_reqs = omap2_uart3_sdma_reqs,
1293 .main_clk = "uart3_fck",
1294 .prcm = {
1295 .omap2 = {
1296 .module_offs = OMAP3430_PER_MOD,
1297 .prcm_reg_id = 1,
1298 .module_bit = OMAP3430_EN_UART3_SHIFT,
1299 .idlest_reg_id = 1,
1300 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
1301 },
1302 },
1303 .slaves = omap3xxx_uart3_slaves,
1304 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
1305 .class = &omap2_uart_class,
1306 };
1307
1308 /* UART4 */
1309
1310 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1311 { .irq = INT_36XX_UART4_IRQ, },
1312 { .irq = -1 }
1313 };
1314
1315 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1316 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
1317 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
1318 { .dma_req = -1 }
1319 };
1320
1321 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
1322 &omap3_l4_per__uart4,
1323 };
1324
1325 static struct omap_hwmod omap3xxx_uart4_hwmod = {
1326 .name = "uart4",
1327 .mpu_irqs = uart4_mpu_irqs,
1328 .sdma_reqs = uart4_sdma_reqs,
1329 .main_clk = "uart4_fck",
1330 .prcm = {
1331 .omap2 = {
1332 .module_offs = OMAP3430_PER_MOD,
1333 .prcm_reg_id = 1,
1334 .module_bit = OMAP3630_EN_UART4_SHIFT,
1335 .idlest_reg_id = 1,
1336 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
1337 },
1338 },
1339 .slaves = omap3xxx_uart4_slaves,
1340 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
1341 .class = &omap2_uart_class,
1342 };
1343
1344 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
1345 { .irq = INT_35XX_UART4_IRQ, },
1346 };
1347
1348 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
1349 { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
1350 { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
1351 };
1352
1353 static struct omap_hwmod_ocp_if *am35xx_uart4_slaves[] = {
1354 &am35xx_l4_core__uart4,
1355 };
1356
1357 static struct omap_hwmod am35xx_uart4_hwmod = {
1358 .name = "uart4",
1359 .mpu_irqs = am35xx_uart4_mpu_irqs,
1360 .sdma_reqs = am35xx_uart4_sdma_reqs,
1361 .main_clk = "uart4_fck",
1362 .prcm = {
1363 .omap2 = {
1364 .module_offs = CORE_MOD,
1365 .prcm_reg_id = 1,
1366 .module_bit = OMAP3430_EN_UART4_SHIFT,
1367 .idlest_reg_id = 1,
1368 .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT,
1369 },
1370 },
1371 .slaves = am35xx_uart4_slaves,
1372 .slaves_cnt = ARRAY_SIZE(am35xx_uart4_slaves),
1373 .class = &omap2_uart_class,
1374 };
1375
1376
1377 static struct omap_hwmod_class i2c_class = {
1378 .name = "i2c",
1379 .sysc = &i2c_sysc,
1380 .rev = OMAP_I2C_IP_VERSION_1,
1381 .reset = &omap_i2c_reset,
1382 };
1383
1384 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1385 { .name = "dispc", .dma_req = 5 },
1386 { .name = "dsi1", .dma_req = 74 },
1387 { .dma_req = -1 }
1388 };
1389
1390 /* dss */
1391 /* dss master ports */
1392 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1393 &omap3xxx_dss__l3,
1394 };
1395
1396 /* l4_core -> dss */
1397 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1398 .master = &omap3xxx_l4_core_hwmod,
1399 .slave = &omap3430es1_dss_core_hwmod,
1400 .clk = "dss_ick",
1401 .addr = omap2_dss_addrs,
1402 .fw = {
1403 .omap2 = {
1404 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1405 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1406 .flags = OMAP_FIREWALL_L4,
1407 }
1408 },
1409 .user = OCP_USER_MPU | OCP_USER_SDMA,
1410 };
1411
1412 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1413 .master = &omap3xxx_l4_core_hwmod,
1414 .slave = &omap3xxx_dss_core_hwmod,
1415 .clk = "dss_ick",
1416 .addr = omap2_dss_addrs,
1417 .fw = {
1418 .omap2 = {
1419 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1420 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1421 .flags = OMAP_FIREWALL_L4,
1422 }
1423 },
1424 .user = OCP_USER_MPU | OCP_USER_SDMA,
1425 };
1426
1427 /* dss slave ports */
1428 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
1429 &omap3430es1_l4_core__dss,
1430 };
1431
1432 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1433 &omap3xxx_l4_core__dss,
1434 };
1435
1436 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1437 /*
1438 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
1439 * driver does not use these clocks.
1440 */
1441 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1442 { .role = "tv_clk", .clk = "dss_tv_fck" },
1443 /* required only on OMAP3430 */
1444 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
1445 };
1446
1447 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1448 .name = "dss_core",
1449 .class = &omap2_dss_hwmod_class,
1450 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1451 .sdma_reqs = omap3xxx_dss_sdma_chs,
1452 .prcm = {
1453 .omap2 = {
1454 .prcm_reg_id = 1,
1455 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1456 .module_offs = OMAP3430_DSS_MOD,
1457 .idlest_reg_id = 1,
1458 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
1459 },
1460 },
1461 .opt_clks = dss_opt_clks,
1462 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1463 .slaves = omap3430es1_dss_slaves,
1464 .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves),
1465 .masters = omap3xxx_dss_masters,
1466 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1467 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1468 };
1469
1470 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1471 .name = "dss_core",
1472 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1473 .class = &omap2_dss_hwmod_class,
1474 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1475 .sdma_reqs = omap3xxx_dss_sdma_chs,
1476 .prcm = {
1477 .omap2 = {
1478 .prcm_reg_id = 1,
1479 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1480 .module_offs = OMAP3430_DSS_MOD,
1481 .idlest_reg_id = 1,
1482 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
1483 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
1484 },
1485 },
1486 .opt_clks = dss_opt_clks,
1487 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1488 .slaves = omap3xxx_dss_slaves,
1489 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves),
1490 .masters = omap3xxx_dss_masters,
1491 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1492 };
1493
1494 /*
1495 * 'dispc' class
1496 * display controller
1497 */
1498
1499 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
1500 .rev_offs = 0x0000,
1501 .sysc_offs = 0x0010,
1502 .syss_offs = 0x0014,
1503 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
1504 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1505 SYSC_HAS_ENAWAKEUP),
1506 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1507 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1508 .sysc_fields = &omap_hwmod_sysc_type1,
1509 };
1510
1511 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
1512 .name = "dispc",
1513 .sysc = &omap3_dispc_sysc,
1514 };
1515
1516 /* l4_core -> dss_dispc */
1517 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1518 .master = &omap3xxx_l4_core_hwmod,
1519 .slave = &omap3xxx_dss_dispc_hwmod,
1520 .clk = "dss_ick",
1521 .addr = omap2_dss_dispc_addrs,
1522 .fw = {
1523 .omap2 = {
1524 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1525 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1526 .flags = OMAP_FIREWALL_L4,
1527 }
1528 },
1529 .user = OCP_USER_MPU | OCP_USER_SDMA,
1530 };
1531
1532 /* dss_dispc slave ports */
1533 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1534 &omap3xxx_l4_core__dss_dispc,
1535 };
1536
1537 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1538 .name = "dss_dispc",
1539 .class = &omap3_dispc_hwmod_class,
1540 .mpu_irqs = omap2_dispc_irqs,
1541 .main_clk = "dss1_alwon_fck",
1542 .prcm = {
1543 .omap2 = {
1544 .prcm_reg_id = 1,
1545 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1546 .module_offs = OMAP3430_DSS_MOD,
1547 },
1548 },
1549 .slaves = omap3xxx_dss_dispc_slaves,
1550 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1551 .flags = HWMOD_NO_IDLEST,
1552 .dev_attr = &omap2_3_dss_dispc_dev_attr
1553 };
1554
1555 /*
1556 * 'dsi' class
1557 * display serial interface controller
1558 */
1559
1560 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1561 .name = "dsi",
1562 };
1563
1564 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
1565 { .irq = 25 },
1566 { .irq = -1 }
1567 };
1568
1569 /* dss_dsi1 */
1570 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1571 {
1572 .pa_start = 0x4804FC00,
1573 .pa_end = 0x4804FFFF,
1574 .flags = ADDR_TYPE_RT
1575 },
1576 { }
1577 };
1578
1579 /* l4_core -> dss_dsi1 */
1580 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1581 .master = &omap3xxx_l4_core_hwmod,
1582 .slave = &omap3xxx_dss_dsi1_hwmod,
1583 .clk = "dss_ick",
1584 .addr = omap3xxx_dss_dsi1_addrs,
1585 .fw = {
1586 .omap2 = {
1587 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1588 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1589 .flags = OMAP_FIREWALL_L4,
1590 }
1591 },
1592 .user = OCP_USER_MPU | OCP_USER_SDMA,
1593 };
1594
1595 /* dss_dsi1 slave ports */
1596 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1597 &omap3xxx_l4_core__dss_dsi1,
1598 };
1599
1600 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1601 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1602 };
1603
1604 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1605 .name = "dss_dsi1",
1606 .class = &omap3xxx_dsi_hwmod_class,
1607 .mpu_irqs = omap3xxx_dsi1_irqs,
1608 .main_clk = "dss1_alwon_fck",
1609 .prcm = {
1610 .omap2 = {
1611 .prcm_reg_id = 1,
1612 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1613 .module_offs = OMAP3430_DSS_MOD,
1614 },
1615 },
1616 .opt_clks = dss_dsi1_opt_clks,
1617 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
1618 .slaves = omap3xxx_dss_dsi1_slaves,
1619 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1620 .flags = HWMOD_NO_IDLEST,
1621 };
1622
1623 /* l4_core -> dss_rfbi */
1624 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1625 .master = &omap3xxx_l4_core_hwmod,
1626 .slave = &omap3xxx_dss_rfbi_hwmod,
1627 .clk = "dss_ick",
1628 .addr = omap2_dss_rfbi_addrs,
1629 .fw = {
1630 .omap2 = {
1631 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1632 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1633 .flags = OMAP_FIREWALL_L4,
1634 }
1635 },
1636 .user = OCP_USER_MPU | OCP_USER_SDMA,
1637 };
1638
1639 /* dss_rfbi slave ports */
1640 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1641 &omap3xxx_l4_core__dss_rfbi,
1642 };
1643
1644 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1645 { .role = "ick", .clk = "dss_ick" },
1646 };
1647
1648 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1649 .name = "dss_rfbi",
1650 .class = &omap2_rfbi_hwmod_class,
1651 .main_clk = "dss1_alwon_fck",
1652 .prcm = {
1653 .omap2 = {
1654 .prcm_reg_id = 1,
1655 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1656 .module_offs = OMAP3430_DSS_MOD,
1657 },
1658 },
1659 .opt_clks = dss_rfbi_opt_clks,
1660 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
1661 .slaves = omap3xxx_dss_rfbi_slaves,
1662 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1663 .flags = HWMOD_NO_IDLEST,
1664 };
1665
1666 /* l4_core -> dss_venc */
1667 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1668 .master = &omap3xxx_l4_core_hwmod,
1669 .slave = &omap3xxx_dss_venc_hwmod,
1670 .clk = "dss_ick",
1671 .addr = omap2_dss_venc_addrs,
1672 .fw = {
1673 .omap2 = {
1674 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1675 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1676 .flags = OMAP_FIREWALL_L4,
1677 }
1678 },
1679 .user = OCP_USER_MPU | OCP_USER_SDMA,
1680 };
1681
1682 /* dss_venc slave ports */
1683 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1684 &omap3xxx_l4_core__dss_venc,
1685 };
1686
1687 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
1688 /* required only on OMAP3430 */
1689 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
1690 };
1691
1692 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1693 .name = "dss_venc",
1694 .class = &omap2_venc_hwmod_class,
1695 .main_clk = "dss_tv_fck",
1696 .prcm = {
1697 .omap2 = {
1698 .prcm_reg_id = 1,
1699 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1700 .module_offs = OMAP3430_DSS_MOD,
1701 },
1702 },
1703 .opt_clks = dss_venc_opt_clks,
1704 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
1705 .slaves = omap3xxx_dss_venc_slaves,
1706 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1707 .flags = HWMOD_NO_IDLEST,
1708 };
1709
1710 /* I2C1 */
1711
1712 static struct omap_i2c_dev_attr i2c1_dev_attr = {
1713 .fifo_depth = 8, /* bytes */
1714 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1715 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1716 OMAP_I2C_FLAG_BUS_SHIFT_2,
1717 };
1718
1719 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1720 &omap3_l4_core__i2c1,
1721 };
1722
1723 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1724 .name = "i2c1",
1725 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1726 .mpu_irqs = omap2_i2c1_mpu_irqs,
1727 .sdma_reqs = omap2_i2c1_sdma_reqs,
1728 .main_clk = "i2c1_fck",
1729 .prcm = {
1730 .omap2 = {
1731 .module_offs = CORE_MOD,
1732 .prcm_reg_id = 1,
1733 .module_bit = OMAP3430_EN_I2C1_SHIFT,
1734 .idlest_reg_id = 1,
1735 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1736 },
1737 },
1738 .slaves = omap3xxx_i2c1_slaves,
1739 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1740 .class = &i2c_class,
1741 .dev_attr = &i2c1_dev_attr,
1742 };
1743
1744 /* I2C2 */
1745
1746 static struct omap_i2c_dev_attr i2c2_dev_attr = {
1747 .fifo_depth = 8, /* bytes */
1748 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1749 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1750 OMAP_I2C_FLAG_BUS_SHIFT_2,
1751 };
1752
1753 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1754 &omap3_l4_core__i2c2,
1755 };
1756
1757 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1758 .name = "i2c2",
1759 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1760 .mpu_irqs = omap2_i2c2_mpu_irqs,
1761 .sdma_reqs = omap2_i2c2_sdma_reqs,
1762 .main_clk = "i2c2_fck",
1763 .prcm = {
1764 .omap2 = {
1765 .module_offs = CORE_MOD,
1766 .prcm_reg_id = 1,
1767 .module_bit = OMAP3430_EN_I2C2_SHIFT,
1768 .idlest_reg_id = 1,
1769 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1770 },
1771 },
1772 .slaves = omap3xxx_i2c2_slaves,
1773 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1774 .class = &i2c_class,
1775 .dev_attr = &i2c2_dev_attr,
1776 };
1777
1778 /* I2C3 */
1779
1780 static struct omap_i2c_dev_attr i2c3_dev_attr = {
1781 .fifo_depth = 64, /* bytes */
1782 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1783 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1784 OMAP_I2C_FLAG_BUS_SHIFT_2,
1785 };
1786
1787 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1788 { .irq = INT_34XX_I2C3_IRQ, },
1789 { .irq = -1 }
1790 };
1791
1792 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1793 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1794 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1795 { .dma_req = -1 }
1796 };
1797
1798 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1799 &omap3_l4_core__i2c3,
1800 };
1801
1802 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1803 .name = "i2c3",
1804 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1805 .mpu_irqs = i2c3_mpu_irqs,
1806 .sdma_reqs = i2c3_sdma_reqs,
1807 .main_clk = "i2c3_fck",
1808 .prcm = {
1809 .omap2 = {
1810 .module_offs = CORE_MOD,
1811 .prcm_reg_id = 1,
1812 .module_bit = OMAP3430_EN_I2C3_SHIFT,
1813 .idlest_reg_id = 1,
1814 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1815 },
1816 },
1817 .slaves = omap3xxx_i2c3_slaves,
1818 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1819 .class = &i2c_class,
1820 .dev_attr = &i2c3_dev_attr,
1821 };
1822
1823 /* l4_wkup -> gpio1 */
1824 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
1825 {
1826 .pa_start = 0x48310000,
1827 .pa_end = 0x483101ff,
1828 .flags = ADDR_TYPE_RT
1829 },
1830 { }
1831 };
1832
1833 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
1834 .master = &omap3xxx_l4_wkup_hwmod,
1835 .slave = &omap3xxx_gpio1_hwmod,
1836 .addr = omap3xxx_gpio1_addrs,
1837 .user = OCP_USER_MPU | OCP_USER_SDMA,
1838 };
1839
1840 /* l4_per -> gpio2 */
1841 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
1842 {
1843 .pa_start = 0x49050000,
1844 .pa_end = 0x490501ff,
1845 .flags = ADDR_TYPE_RT
1846 },
1847 { }
1848 };
1849
1850 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
1851 .master = &omap3xxx_l4_per_hwmod,
1852 .slave = &omap3xxx_gpio2_hwmod,
1853 .addr = omap3xxx_gpio2_addrs,
1854 .user = OCP_USER_MPU | OCP_USER_SDMA,
1855 };
1856
1857 /* l4_per -> gpio3 */
1858 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
1859 {
1860 .pa_start = 0x49052000,
1861 .pa_end = 0x490521ff,
1862 .flags = ADDR_TYPE_RT
1863 },
1864 { }
1865 };
1866
1867 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
1868 .master = &omap3xxx_l4_per_hwmod,
1869 .slave = &omap3xxx_gpio3_hwmod,
1870 .addr = omap3xxx_gpio3_addrs,
1871 .user = OCP_USER_MPU | OCP_USER_SDMA,
1872 };
1873
1874 /* l4_per -> gpio4 */
1875 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
1876 {
1877 .pa_start = 0x49054000,
1878 .pa_end = 0x490541ff,
1879 .flags = ADDR_TYPE_RT
1880 },
1881 { }
1882 };
1883
1884 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
1885 .master = &omap3xxx_l4_per_hwmod,
1886 .slave = &omap3xxx_gpio4_hwmod,
1887 .addr = omap3xxx_gpio4_addrs,
1888 .user = OCP_USER_MPU | OCP_USER_SDMA,
1889 };
1890
1891 /* l4_per -> gpio5 */
1892 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
1893 {
1894 .pa_start = 0x49056000,
1895 .pa_end = 0x490561ff,
1896 .flags = ADDR_TYPE_RT
1897 },
1898 { }
1899 };
1900
1901 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
1902 .master = &omap3xxx_l4_per_hwmod,
1903 .slave = &omap3xxx_gpio5_hwmod,
1904 .addr = omap3xxx_gpio5_addrs,
1905 .user = OCP_USER_MPU | OCP_USER_SDMA,
1906 };
1907
1908 /* l4_per -> gpio6 */
1909 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
1910 {
1911 .pa_start = 0x49058000,
1912 .pa_end = 0x490581ff,
1913 .flags = ADDR_TYPE_RT
1914 },
1915 { }
1916 };
1917
1918 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
1919 .master = &omap3xxx_l4_per_hwmod,
1920 .slave = &omap3xxx_gpio6_hwmod,
1921 .addr = omap3xxx_gpio6_addrs,
1922 .user = OCP_USER_MPU | OCP_USER_SDMA,
1923 };
1924
1925 /*
1926 * 'gpio' class
1927 * general purpose io module
1928 */
1929
1930 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
1931 .rev_offs = 0x0000,
1932 .sysc_offs = 0x0010,
1933 .syss_offs = 0x0014,
1934 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1935 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1936 SYSS_HAS_RESET_STATUS),
1937 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1938 .sysc_fields = &omap_hwmod_sysc_type1,
1939 };
1940
1941 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
1942 .name = "gpio",
1943 .sysc = &omap3xxx_gpio_sysc,
1944 .rev = 1,
1945 };
1946
1947 /* gpio_dev_attr*/
1948 static struct omap_gpio_dev_attr gpio_dev_attr = {
1949 .bank_width = 32,
1950 .dbck_flag = true,
1951 };
1952
1953 /* gpio1 */
1954 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1955 { .role = "dbclk", .clk = "gpio1_dbck", },
1956 };
1957
1958 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
1959 &omap3xxx_l4_wkup__gpio1,
1960 };
1961
1962 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
1963 .name = "gpio1",
1964 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1965 .mpu_irqs = omap2_gpio1_irqs,
1966 .main_clk = "gpio1_ick",
1967 .opt_clks = gpio1_opt_clks,
1968 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1969 .prcm = {
1970 .omap2 = {
1971 .prcm_reg_id = 1,
1972 .module_bit = OMAP3430_EN_GPIO1_SHIFT,
1973 .module_offs = WKUP_MOD,
1974 .idlest_reg_id = 1,
1975 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
1976 },
1977 },
1978 .slaves = omap3xxx_gpio1_slaves,
1979 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves),
1980 .class = &omap3xxx_gpio_hwmod_class,
1981 .dev_attr = &gpio_dev_attr,
1982 };
1983
1984 /* gpio2 */
1985 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1986 { .role = "dbclk", .clk = "gpio2_dbck", },
1987 };
1988
1989 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
1990 &omap3xxx_l4_per__gpio2,
1991 };
1992
1993 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
1994 .name = "gpio2",
1995 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1996 .mpu_irqs = omap2_gpio2_irqs,
1997 .main_clk = "gpio2_ick",
1998 .opt_clks = gpio2_opt_clks,
1999 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
2000 .prcm = {
2001 .omap2 = {
2002 .prcm_reg_id = 1,
2003 .module_bit = OMAP3430_EN_GPIO2_SHIFT,
2004 .module_offs = OMAP3430_PER_MOD,
2005 .idlest_reg_id = 1,
2006 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
2007 },
2008 },
2009 .slaves = omap3xxx_gpio2_slaves,
2010 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves),
2011 .class = &omap3xxx_gpio_hwmod_class,
2012 .dev_attr = &gpio_dev_attr,
2013 };
2014
2015 /* gpio3 */
2016 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
2017 { .role = "dbclk", .clk = "gpio3_dbck", },
2018 };
2019
2020 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
2021 &omap3xxx_l4_per__gpio3,
2022 };
2023
2024 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
2025 .name = "gpio3",
2026 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2027 .mpu_irqs = omap2_gpio3_irqs,
2028 .main_clk = "gpio3_ick",
2029 .opt_clks = gpio3_opt_clks,
2030 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
2031 .prcm = {
2032 .omap2 = {
2033 .prcm_reg_id = 1,
2034 .module_bit = OMAP3430_EN_GPIO3_SHIFT,
2035 .module_offs = OMAP3430_PER_MOD,
2036 .idlest_reg_id = 1,
2037 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
2038 },
2039 },
2040 .slaves = omap3xxx_gpio3_slaves,
2041 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves),
2042 .class = &omap3xxx_gpio_hwmod_class,
2043 .dev_attr = &gpio_dev_attr,
2044 };
2045
2046 /* gpio4 */
2047 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2048 { .role = "dbclk", .clk = "gpio4_dbck", },
2049 };
2050
2051 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
2052 &omap3xxx_l4_per__gpio4,
2053 };
2054
2055 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
2056 .name = "gpio4",
2057 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2058 .mpu_irqs = omap2_gpio4_irqs,
2059 .main_clk = "gpio4_ick",
2060 .opt_clks = gpio4_opt_clks,
2061 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
2062 .prcm = {
2063 .omap2 = {
2064 .prcm_reg_id = 1,
2065 .module_bit = OMAP3430_EN_GPIO4_SHIFT,
2066 .module_offs = OMAP3430_PER_MOD,
2067 .idlest_reg_id = 1,
2068 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
2069 },
2070 },
2071 .slaves = omap3xxx_gpio4_slaves,
2072 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves),
2073 .class = &omap3xxx_gpio_hwmod_class,
2074 .dev_attr = &gpio_dev_attr,
2075 };
2076
2077 /* gpio5 */
2078 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
2079 { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
2080 { .irq = -1 }
2081 };
2082
2083 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2084 { .role = "dbclk", .clk = "gpio5_dbck", },
2085 };
2086
2087 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
2088 &omap3xxx_l4_per__gpio5,
2089 };
2090
2091 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2092 .name = "gpio5",
2093 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2094 .mpu_irqs = omap3xxx_gpio5_irqs,
2095 .main_clk = "gpio5_ick",
2096 .opt_clks = gpio5_opt_clks,
2097 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
2098 .prcm = {
2099 .omap2 = {
2100 .prcm_reg_id = 1,
2101 .module_bit = OMAP3430_EN_GPIO5_SHIFT,
2102 .module_offs = OMAP3430_PER_MOD,
2103 .idlest_reg_id = 1,
2104 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
2105 },
2106 },
2107 .slaves = omap3xxx_gpio5_slaves,
2108 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves),
2109 .class = &omap3xxx_gpio_hwmod_class,
2110 .dev_attr = &gpio_dev_attr,
2111 };
2112
2113 /* gpio6 */
2114 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
2115 { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
2116 { .irq = -1 }
2117 };
2118
2119 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2120 { .role = "dbclk", .clk = "gpio6_dbck", },
2121 };
2122
2123 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
2124 &omap3xxx_l4_per__gpio6,
2125 };
2126
2127 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2128 .name = "gpio6",
2129 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2130 .mpu_irqs = omap3xxx_gpio6_irqs,
2131 .main_clk = "gpio6_ick",
2132 .opt_clks = gpio6_opt_clks,
2133 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
2134 .prcm = {
2135 .omap2 = {
2136 .prcm_reg_id = 1,
2137 .module_bit = OMAP3430_EN_GPIO6_SHIFT,
2138 .module_offs = OMAP3430_PER_MOD,
2139 .idlest_reg_id = 1,
2140 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
2141 },
2142 },
2143 .slaves = omap3xxx_gpio6_slaves,
2144 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves),
2145 .class = &omap3xxx_gpio_hwmod_class,
2146 .dev_attr = &gpio_dev_attr,
2147 };
2148
2149 /* dma_system -> L3 */
2150 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2151 .master = &omap3xxx_dma_system_hwmod,
2152 .slave = &omap3xxx_l3_main_hwmod,
2153 .clk = "core_l3_ick",
2154 .user = OCP_USER_MPU | OCP_USER_SDMA,
2155 };
2156
2157 /* dma attributes */
2158 static struct omap_dma_dev_attr dma_dev_attr = {
2159 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
2160 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
2161 .lch_count = 32,
2162 };
2163
2164 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
2165 .rev_offs = 0x0000,
2166 .sysc_offs = 0x002c,
2167 .syss_offs = 0x0028,
2168 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2169 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
2170 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
2171 SYSS_HAS_RESET_STATUS),
2172 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2173 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2174 .sysc_fields = &omap_hwmod_sysc_type1,
2175 };
2176
2177 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2178 .name = "dma",
2179 .sysc = &omap3xxx_dma_sysc,
2180 };
2181
2182 /* dma_system */
2183 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2184 {
2185 .pa_start = 0x48056000,
2186 .pa_end = 0x48056fff,
2187 .flags = ADDR_TYPE_RT
2188 },
2189 { }
2190 };
2191
2192 /* dma_system master ports */
2193 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
2194 &omap3xxx_dma_system__l3,
2195 };
2196
2197 /* l4_cfg -> dma_system */
2198 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2199 .master = &omap3xxx_l4_core_hwmod,
2200 .slave = &omap3xxx_dma_system_hwmod,
2201 .clk = "core_l4_ick",
2202 .addr = omap3xxx_dma_system_addrs,
2203 .user = OCP_USER_MPU | OCP_USER_SDMA,
2204 };
2205
2206 /* dma_system slave ports */
2207 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2208 &omap3xxx_l4_core__dma_system,
2209 };
2210
2211 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2212 .name = "dma",
2213 .class = &omap3xxx_dma_hwmod_class,
2214 .mpu_irqs = omap2_dma_system_irqs,
2215 .main_clk = "core_l3_ick",
2216 .prcm = {
2217 .omap2 = {
2218 .module_offs = CORE_MOD,
2219 .prcm_reg_id = 1,
2220 .module_bit = OMAP3430_ST_SDMA_SHIFT,
2221 .idlest_reg_id = 1,
2222 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
2223 },
2224 },
2225 .slaves = omap3xxx_dma_system_slaves,
2226 .slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves),
2227 .masters = omap3xxx_dma_system_masters,
2228 .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters),
2229 .dev_attr = &dma_dev_attr,
2230 .flags = HWMOD_NO_IDLEST,
2231 };
2232
2233 /*
2234 * 'mcbsp' class
2235 * multi channel buffered serial port controller
2236 */
2237
2238 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
2239 .sysc_offs = 0x008c,
2240 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2241 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2242 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2243 .sysc_fields = &omap_hwmod_sysc_type1,
2244 .clockact = 0x2,
2245 };
2246
2247 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
2248 .name = "mcbsp",
2249 .sysc = &omap3xxx_mcbsp_sysc,
2250 .rev = MCBSP_CONFIG_TYPE3,
2251 };
2252
2253 /* mcbsp1 */
2254 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2255 { .name = "irq", .irq = 16 },
2256 { .name = "tx", .irq = 59 },
2257 { .name = "rx", .irq = 60 },
2258 { .irq = -1 }
2259 };
2260
2261 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2262 {
2263 .name = "mpu",
2264 .pa_start = 0x48074000,
2265 .pa_end = 0x480740ff,
2266 .flags = ADDR_TYPE_RT
2267 },
2268 { }
2269 };
2270
2271 /* l4_core -> mcbsp1 */
2272 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2273 .master = &omap3xxx_l4_core_hwmod,
2274 .slave = &omap3xxx_mcbsp1_hwmod,
2275 .clk = "mcbsp1_ick",
2276 .addr = omap3xxx_mcbsp1_addrs,
2277 .user = OCP_USER_MPU | OCP_USER_SDMA,
2278 };
2279
2280 /* mcbsp1 slave ports */
2281 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2282 &omap3xxx_l4_core__mcbsp1,
2283 };
2284
2285 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2286 .name = "mcbsp1",
2287 .class = &omap3xxx_mcbsp_hwmod_class,
2288 .mpu_irqs = omap3xxx_mcbsp1_irqs,
2289 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
2290 .main_clk = "mcbsp1_fck",
2291 .prcm = {
2292 .omap2 = {
2293 .prcm_reg_id = 1,
2294 .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
2295 .module_offs = CORE_MOD,
2296 .idlest_reg_id = 1,
2297 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2298 },
2299 },
2300 .slaves = omap3xxx_mcbsp1_slaves,
2301 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2302 };
2303
2304 /* mcbsp2 */
2305 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2306 { .name = "irq", .irq = 17 },
2307 { .name = "tx", .irq = 62 },
2308 { .name = "rx", .irq = 63 },
2309 { .irq = -1 }
2310 };
2311
2312 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2313 {
2314 .name = "mpu",
2315 .pa_start = 0x49022000,
2316 .pa_end = 0x490220ff,
2317 .flags = ADDR_TYPE_RT
2318 },
2319 { }
2320 };
2321
2322 /* l4_per -> mcbsp2 */
2323 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2324 .master = &omap3xxx_l4_per_hwmod,
2325 .slave = &omap3xxx_mcbsp2_hwmod,
2326 .clk = "mcbsp2_ick",
2327 .addr = omap3xxx_mcbsp2_addrs,
2328 .user = OCP_USER_MPU | OCP_USER_SDMA,
2329 };
2330
2331 /* mcbsp2 slave ports */
2332 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2333 &omap3xxx_l4_per__mcbsp2,
2334 };
2335
2336 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2337 .sidetone = "mcbsp2_sidetone",
2338 };
2339
2340 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2341 .name = "mcbsp2",
2342 .class = &omap3xxx_mcbsp_hwmod_class,
2343 .mpu_irqs = omap3xxx_mcbsp2_irqs,
2344 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
2345 .main_clk = "mcbsp2_fck",
2346 .prcm = {
2347 .omap2 = {
2348 .prcm_reg_id = 1,
2349 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2350 .module_offs = OMAP3430_PER_MOD,
2351 .idlest_reg_id = 1,
2352 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2353 },
2354 },
2355 .slaves = omap3xxx_mcbsp2_slaves,
2356 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2357 .dev_attr = &omap34xx_mcbsp2_dev_attr,
2358 };
2359
2360 /* mcbsp3 */
2361 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2362 { .name = "irq", .irq = 22 },
2363 { .name = "tx", .irq = 89 },
2364 { .name = "rx", .irq = 90 },
2365 { .irq = -1 }
2366 };
2367
2368 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2369 {
2370 .name = "mpu",
2371 .pa_start = 0x49024000,
2372 .pa_end = 0x490240ff,
2373 .flags = ADDR_TYPE_RT
2374 },
2375 { }
2376 };
2377
2378 /* l4_per -> mcbsp3 */
2379 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2380 .master = &omap3xxx_l4_per_hwmod,
2381 .slave = &omap3xxx_mcbsp3_hwmod,
2382 .clk = "mcbsp3_ick",
2383 .addr = omap3xxx_mcbsp3_addrs,
2384 .user = OCP_USER_MPU | OCP_USER_SDMA,
2385 };
2386
2387 /* mcbsp3 slave ports */
2388 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2389 &omap3xxx_l4_per__mcbsp3,
2390 };
2391
2392 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2393 .sidetone = "mcbsp3_sidetone",
2394 };
2395
2396 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2397 .name = "mcbsp3",
2398 .class = &omap3xxx_mcbsp_hwmod_class,
2399 .mpu_irqs = omap3xxx_mcbsp3_irqs,
2400 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
2401 .main_clk = "mcbsp3_fck",
2402 .prcm = {
2403 .omap2 = {
2404 .prcm_reg_id = 1,
2405 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2406 .module_offs = OMAP3430_PER_MOD,
2407 .idlest_reg_id = 1,
2408 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2409 },
2410 },
2411 .slaves = omap3xxx_mcbsp3_slaves,
2412 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2413 .dev_attr = &omap34xx_mcbsp3_dev_attr,
2414 };
2415
2416 /* mcbsp4 */
2417 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2418 { .name = "irq", .irq = 23 },
2419 { .name = "tx", .irq = 54 },
2420 { .name = "rx", .irq = 55 },
2421 { .irq = -1 }
2422 };
2423
2424 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2425 { .name = "rx", .dma_req = 20 },
2426 { .name = "tx", .dma_req = 19 },
2427 { .dma_req = -1 }
2428 };
2429
2430 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2431 {
2432 .name = "mpu",
2433 .pa_start = 0x49026000,
2434 .pa_end = 0x490260ff,
2435 .flags = ADDR_TYPE_RT
2436 },
2437 { }
2438 };
2439
2440 /* l4_per -> mcbsp4 */
2441 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2442 .master = &omap3xxx_l4_per_hwmod,
2443 .slave = &omap3xxx_mcbsp4_hwmod,
2444 .clk = "mcbsp4_ick",
2445 .addr = omap3xxx_mcbsp4_addrs,
2446 .user = OCP_USER_MPU | OCP_USER_SDMA,
2447 };
2448
2449 /* mcbsp4 slave ports */
2450 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2451 &omap3xxx_l4_per__mcbsp4,
2452 };
2453
2454 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2455 .name = "mcbsp4",
2456 .class = &omap3xxx_mcbsp_hwmod_class,
2457 .mpu_irqs = omap3xxx_mcbsp4_irqs,
2458 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
2459 .main_clk = "mcbsp4_fck",
2460 .prcm = {
2461 .omap2 = {
2462 .prcm_reg_id = 1,
2463 .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
2464 .module_offs = OMAP3430_PER_MOD,
2465 .idlest_reg_id = 1,
2466 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2467 },
2468 },
2469 .slaves = omap3xxx_mcbsp4_slaves,
2470 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2471 };
2472
2473 /* mcbsp5 */
2474 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2475 { .name = "irq", .irq = 27 },
2476 { .name = "tx", .irq = 81 },
2477 { .name = "rx", .irq = 82 },
2478 { .irq = -1 }
2479 };
2480
2481 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2482 { .name = "rx", .dma_req = 22 },
2483 { .name = "tx", .dma_req = 21 },
2484 { .dma_req = -1 }
2485 };
2486
2487 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2488 {
2489 .name = "mpu",
2490 .pa_start = 0x48096000,
2491 .pa_end = 0x480960ff,
2492 .flags = ADDR_TYPE_RT
2493 },
2494 { }
2495 };
2496
2497 /* l4_core -> mcbsp5 */
2498 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2499 .master = &omap3xxx_l4_core_hwmod,
2500 .slave = &omap3xxx_mcbsp5_hwmod,
2501 .clk = "mcbsp5_ick",
2502 .addr = omap3xxx_mcbsp5_addrs,
2503 .user = OCP_USER_MPU | OCP_USER_SDMA,
2504 };
2505
2506 /* mcbsp5 slave ports */
2507 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2508 &omap3xxx_l4_core__mcbsp5,
2509 };
2510
2511 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2512 .name = "mcbsp5",
2513 .class = &omap3xxx_mcbsp_hwmod_class,
2514 .mpu_irqs = omap3xxx_mcbsp5_irqs,
2515 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
2516 .main_clk = "mcbsp5_fck",
2517 .prcm = {
2518 .omap2 = {
2519 .prcm_reg_id = 1,
2520 .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
2521 .module_offs = CORE_MOD,
2522 .idlest_reg_id = 1,
2523 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2524 },
2525 },
2526 .slaves = omap3xxx_mcbsp5_slaves,
2527 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2528 };
2529 /* 'mcbsp sidetone' class */
2530
2531 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2532 .sysc_offs = 0x0010,
2533 .sysc_flags = SYSC_HAS_AUTOIDLE,
2534 .sysc_fields = &omap_hwmod_sysc_type1,
2535 };
2536
2537 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2538 .name = "mcbsp_sidetone",
2539 .sysc = &omap3xxx_mcbsp_sidetone_sysc,
2540 };
2541
2542 /* mcbsp2_sidetone */
2543 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2544 { .name = "irq", .irq = 4 },
2545 { .irq = -1 }
2546 };
2547
2548 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2549 {
2550 .name = "sidetone",
2551 .pa_start = 0x49028000,
2552 .pa_end = 0x490280ff,
2553 .flags = ADDR_TYPE_RT
2554 },
2555 { }
2556 };
2557
2558 /* l4_per -> mcbsp2_sidetone */
2559 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2560 .master = &omap3xxx_l4_per_hwmod,
2561 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
2562 .clk = "mcbsp2_ick",
2563 .addr = omap3xxx_mcbsp2_sidetone_addrs,
2564 .user = OCP_USER_MPU,
2565 };
2566
2567 /* mcbsp2_sidetone slave ports */
2568 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2569 &omap3xxx_l4_per__mcbsp2_sidetone,
2570 };
2571
2572 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2573 .name = "mcbsp2_sidetone",
2574 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2575 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
2576 .main_clk = "mcbsp2_fck",
2577 .prcm = {
2578 .omap2 = {
2579 .prcm_reg_id = 1,
2580 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2581 .module_offs = OMAP3430_PER_MOD,
2582 .idlest_reg_id = 1,
2583 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2584 },
2585 },
2586 .slaves = omap3xxx_mcbsp2_sidetone_slaves,
2587 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2588 };
2589
2590 /* mcbsp3_sidetone */
2591 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2592 { .name = "irq", .irq = 5 },
2593 { .irq = -1 }
2594 };
2595
2596 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2597 {
2598 .name = "sidetone",
2599 .pa_start = 0x4902A000,
2600 .pa_end = 0x4902A0ff,
2601 .flags = ADDR_TYPE_RT
2602 },
2603 { }
2604 };
2605
2606 /* l4_per -> mcbsp3_sidetone */
2607 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2608 .master = &omap3xxx_l4_per_hwmod,
2609 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
2610 .clk = "mcbsp3_ick",
2611 .addr = omap3xxx_mcbsp3_sidetone_addrs,
2612 .user = OCP_USER_MPU,
2613 };
2614
2615 /* mcbsp3_sidetone slave ports */
2616 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2617 &omap3xxx_l4_per__mcbsp3_sidetone,
2618 };
2619
2620 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2621 .name = "mcbsp3_sidetone",
2622 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2623 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
2624 .main_clk = "mcbsp3_fck",
2625 .prcm = {
2626 .omap2 = {
2627 .prcm_reg_id = 1,
2628 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2629 .module_offs = OMAP3430_PER_MOD,
2630 .idlest_reg_id = 1,
2631 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2632 },
2633 },
2634 .slaves = omap3xxx_mcbsp3_sidetone_slaves,
2635 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2636 };
2637
2638
2639 /* SR common */
2640 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2641 .clkact_shift = 20,
2642 };
2643
2644 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
2645 .sysc_offs = 0x24,
2646 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
2647 .clockact = CLOCKACT_TEST_ICLK,
2648 .sysc_fields = &omap34xx_sr_sysc_fields,
2649 };
2650
2651 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2652 .name = "smartreflex",
2653 .sysc = &omap34xx_sr_sysc,
2654 .rev = 1,
2655 };
2656
2657 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2658 .sidle_shift = 24,
2659 .enwkup_shift = 26
2660 };
2661
2662 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
2663 .sysc_offs = 0x38,
2664 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2665 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2666 SYSC_NO_CACHE),
2667 .sysc_fields = &omap36xx_sr_sysc_fields,
2668 };
2669
2670 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
2671 .name = "smartreflex",
2672 .sysc = &omap36xx_sr_sysc,
2673 .rev = 2,
2674 };
2675
2676 /* SR1 */
2677 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
2678 .sensor_voltdm_name = "mpu_iva",
2679 };
2680
2681 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
2682 &omap3_l4_core__sr1,
2683 };
2684
2685 static struct omap_hwmod omap34xx_sr1_hwmod = {
2686 .name = "sr1_hwmod",
2687 .class = &omap34xx_smartreflex_hwmod_class,
2688 .main_clk = "sr1_fck",
2689 .prcm = {
2690 .omap2 = {
2691 .prcm_reg_id = 1,
2692 .module_bit = OMAP3430_EN_SR1_SHIFT,
2693 .module_offs = WKUP_MOD,
2694 .idlest_reg_id = 1,
2695 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2696 },
2697 },
2698 .slaves = omap3_sr1_slaves,
2699 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
2700 .dev_attr = &sr1_dev_attr,
2701 .mpu_irqs = omap3_smartreflex_mpu_irqs,
2702 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2703 };
2704
2705 static struct omap_hwmod omap36xx_sr1_hwmod = {
2706 .name = "sr1_hwmod",
2707 .class = &omap36xx_smartreflex_hwmod_class,
2708 .main_clk = "sr1_fck",
2709 .prcm = {
2710 .omap2 = {
2711 .prcm_reg_id = 1,
2712 .module_bit = OMAP3430_EN_SR1_SHIFT,
2713 .module_offs = WKUP_MOD,
2714 .idlest_reg_id = 1,
2715 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2716 },
2717 },
2718 .slaves = omap3_sr1_slaves,
2719 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
2720 .dev_attr = &sr1_dev_attr,
2721 .mpu_irqs = omap3_smartreflex_mpu_irqs,
2722 };
2723
2724 /* SR2 */
2725 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
2726 .sensor_voltdm_name = "core",
2727 };
2728
2729 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
2730 &omap3_l4_core__sr2,
2731 };
2732
2733 static struct omap_hwmod omap34xx_sr2_hwmod = {
2734 .name = "sr2_hwmod",
2735 .class = &omap34xx_smartreflex_hwmod_class,
2736 .main_clk = "sr2_fck",
2737 .prcm = {
2738 .omap2 = {
2739 .prcm_reg_id = 1,
2740 .module_bit = OMAP3430_EN_SR2_SHIFT,
2741 .module_offs = WKUP_MOD,
2742 .idlest_reg_id = 1,
2743 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2744 },
2745 },
2746 .slaves = omap3_sr2_slaves,
2747 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
2748 .dev_attr = &sr2_dev_attr,
2749 .mpu_irqs = omap3_smartreflex_core_irqs,
2750 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2751 };
2752
2753 static struct omap_hwmod omap36xx_sr2_hwmod = {
2754 .name = "sr2_hwmod",
2755 .class = &omap36xx_smartreflex_hwmod_class,
2756 .main_clk = "sr2_fck",
2757 .prcm = {
2758 .omap2 = {
2759 .prcm_reg_id = 1,
2760 .module_bit = OMAP3430_EN_SR2_SHIFT,
2761 .module_offs = WKUP_MOD,
2762 .idlest_reg_id = 1,
2763 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2764 },
2765 },
2766 .slaves = omap3_sr2_slaves,
2767 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
2768 .dev_attr = &sr2_dev_attr,
2769 .mpu_irqs = omap3_smartreflex_core_irqs,
2770 };
2771
2772 /*
2773 * 'mailbox' class
2774 * mailbox module allowing communication between the on-chip processors
2775 * using a queued mailbox-interrupt mechanism.
2776 */
2777
2778 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
2779 .rev_offs = 0x000,
2780 .sysc_offs = 0x010,
2781 .syss_offs = 0x014,
2782 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2783 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2784 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2785 .sysc_fields = &omap_hwmod_sysc_type1,
2786 };
2787
2788 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
2789 .name = "mailbox",
2790 .sysc = &omap3xxx_mailbox_sysc,
2791 };
2792
2793 static struct omap_hwmod omap3xxx_mailbox_hwmod;
2794 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
2795 { .irq = 26 },
2796 { .irq = -1 }
2797 };
2798
2799 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2800 {
2801 .pa_start = 0x48094000,
2802 .pa_end = 0x480941ff,
2803 .flags = ADDR_TYPE_RT,
2804 },
2805 { }
2806 };
2807
2808 /* l4_core -> mailbox */
2809 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2810 .master = &omap3xxx_l4_core_hwmod,
2811 .slave = &omap3xxx_mailbox_hwmod,
2812 .addr = omap3xxx_mailbox_addrs,
2813 .user = OCP_USER_MPU | OCP_USER_SDMA,
2814 };
2815
2816 /* mailbox slave ports */
2817 static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
2818 &omap3xxx_l4_core__mailbox,
2819 };
2820
2821 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
2822 .name = "mailbox",
2823 .class = &omap3xxx_mailbox_hwmod_class,
2824 .mpu_irqs = omap3xxx_mailbox_irqs,
2825 .main_clk = "mailboxes_ick",
2826 .prcm = {
2827 .omap2 = {
2828 .prcm_reg_id = 1,
2829 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2830 .module_offs = CORE_MOD,
2831 .idlest_reg_id = 1,
2832 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
2833 },
2834 },
2835 .slaves = omap3xxx_mailbox_slaves,
2836 .slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves),
2837 };
2838
2839 /* l4 core -> mcspi1 interface */
2840 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2841 .master = &omap3xxx_l4_core_hwmod,
2842 .slave = &omap34xx_mcspi1,
2843 .clk = "mcspi1_ick",
2844 .addr = omap2_mcspi1_addr_space,
2845 .user = OCP_USER_MPU | OCP_USER_SDMA,
2846 };
2847
2848 /* l4 core -> mcspi2 interface */
2849 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2850 .master = &omap3xxx_l4_core_hwmod,
2851 .slave = &omap34xx_mcspi2,
2852 .clk = "mcspi2_ick",
2853 .addr = omap2_mcspi2_addr_space,
2854 .user = OCP_USER_MPU | OCP_USER_SDMA,
2855 };
2856
2857 /* l4 core -> mcspi3 interface */
2858 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2859 .master = &omap3xxx_l4_core_hwmod,
2860 .slave = &omap34xx_mcspi3,
2861 .clk = "mcspi3_ick",
2862 .addr = omap2430_mcspi3_addr_space,
2863 .user = OCP_USER_MPU | OCP_USER_SDMA,
2864 };
2865
2866 /* l4 core -> mcspi4 interface */
2867 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
2868 {
2869 .pa_start = 0x480ba000,
2870 .pa_end = 0x480ba0ff,
2871 .flags = ADDR_TYPE_RT,
2872 },
2873 { }
2874 };
2875
2876 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2877 .master = &omap3xxx_l4_core_hwmod,
2878 .slave = &omap34xx_mcspi4,
2879 .clk = "mcspi4_ick",
2880 .addr = omap34xx_mcspi4_addr_space,
2881 .user = OCP_USER_MPU | OCP_USER_SDMA,
2882 };
2883
2884 /*
2885 * 'mcspi' class
2886 * multichannel serial port interface (mcspi) / master/slave synchronous serial
2887 * bus
2888 */
2889
2890 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
2891 .rev_offs = 0x0000,
2892 .sysc_offs = 0x0010,
2893 .syss_offs = 0x0014,
2894 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2895 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2896 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2897 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2898 .sysc_fields = &omap_hwmod_sysc_type1,
2899 };
2900
2901 static struct omap_hwmod_class omap34xx_mcspi_class = {
2902 .name = "mcspi",
2903 .sysc = &omap34xx_mcspi_sysc,
2904 .rev = OMAP3_MCSPI_REV,
2905 };
2906
2907 /* mcspi1 */
2908 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
2909 &omap34xx_l4_core__mcspi1,
2910 };
2911
2912 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2913 .num_chipselect = 4,
2914 };
2915
2916 static struct omap_hwmod omap34xx_mcspi1 = {
2917 .name = "mcspi1",
2918 .mpu_irqs = omap2_mcspi1_mpu_irqs,
2919 .sdma_reqs = omap2_mcspi1_sdma_reqs,
2920 .main_clk = "mcspi1_fck",
2921 .prcm = {
2922 .omap2 = {
2923 .module_offs = CORE_MOD,
2924 .prcm_reg_id = 1,
2925 .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
2926 .idlest_reg_id = 1,
2927 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
2928 },
2929 },
2930 .slaves = omap34xx_mcspi1_slaves,
2931 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves),
2932 .class = &omap34xx_mcspi_class,
2933 .dev_attr = &omap_mcspi1_dev_attr,
2934 };
2935
2936 /* mcspi2 */
2937 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
2938 &omap34xx_l4_core__mcspi2,
2939 };
2940
2941 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2942 .num_chipselect = 2,
2943 };
2944
2945 static struct omap_hwmod omap34xx_mcspi2 = {
2946 .name = "mcspi2",
2947 .mpu_irqs = omap2_mcspi2_mpu_irqs,
2948 .sdma_reqs = omap2_mcspi2_sdma_reqs,
2949 .main_clk = "mcspi2_fck",
2950 .prcm = {
2951 .omap2 = {
2952 .module_offs = CORE_MOD,
2953 .prcm_reg_id = 1,
2954 .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
2955 .idlest_reg_id = 1,
2956 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
2957 },
2958 },
2959 .slaves = omap34xx_mcspi2_slaves,
2960 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves),
2961 .class = &omap34xx_mcspi_class,
2962 .dev_attr = &omap_mcspi2_dev_attr,
2963 };
2964
2965 /* mcspi3 */
2966 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
2967 { .name = "irq", .irq = 91 }, /* 91 */
2968 { .irq = -1 }
2969 };
2970
2971 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
2972 { .name = "tx0", .dma_req = 15 },
2973 { .name = "rx0", .dma_req = 16 },
2974 { .name = "tx1", .dma_req = 23 },
2975 { .name = "rx1", .dma_req = 24 },
2976 { .dma_req = -1 }
2977 };
2978
2979 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
2980 &omap34xx_l4_core__mcspi3,
2981 };
2982
2983 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
2984 .num_chipselect = 2,
2985 };
2986
2987 static struct omap_hwmod omap34xx_mcspi3 = {
2988 .name = "mcspi3",
2989 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
2990 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
2991 .main_clk = "mcspi3_fck",
2992 .prcm = {
2993 .omap2 = {
2994 .module_offs = CORE_MOD,
2995 .prcm_reg_id = 1,
2996 .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
2997 .idlest_reg_id = 1,
2998 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
2999 },
3000 },
3001 .slaves = omap34xx_mcspi3_slaves,
3002 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves),
3003 .class = &omap34xx_mcspi_class,
3004 .dev_attr = &omap_mcspi3_dev_attr,
3005 };
3006
3007 /* SPI4 */
3008 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
3009 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
3010 { .irq = -1 }
3011 };
3012
3013 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
3014 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
3015 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
3016 { .dma_req = -1 }
3017 };
3018
3019 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
3020 &omap34xx_l4_core__mcspi4,
3021 };
3022
3023 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
3024 .num_chipselect = 1,
3025 };
3026
3027 static struct omap_hwmod omap34xx_mcspi4 = {
3028 .name = "mcspi4",
3029 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
3030 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
3031 .main_clk = "mcspi4_fck",
3032 .prcm = {
3033 .omap2 = {
3034 .module_offs = CORE_MOD,
3035 .prcm_reg_id = 1,
3036 .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
3037 .idlest_reg_id = 1,
3038 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
3039 },
3040 },
3041 .slaves = omap34xx_mcspi4_slaves,
3042 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves),
3043 .class = &omap34xx_mcspi_class,
3044 .dev_attr = &omap_mcspi4_dev_attr,
3045 };
3046
3047 /*
3048 * usbhsotg
3049 */
3050 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
3051 .rev_offs = 0x0400,
3052 .sysc_offs = 0x0404,
3053 .syss_offs = 0x0408,
3054 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
3055 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3056 SYSC_HAS_AUTOIDLE),
3057 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3058 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
3059 .sysc_fields = &omap_hwmod_sysc_type1,
3060 };
3061
3062 static struct omap_hwmod_class usbotg_class = {
3063 .name = "usbotg",
3064 .sysc = &omap3xxx_usbhsotg_sysc,
3065 };
3066 /* usb_otg_hs */
3067 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
3068
3069 { .name = "mc", .irq = 92 },
3070 { .name = "dma", .irq = 93 },
3071 { .irq = -1 }
3072 };
3073
3074 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
3075 .name = "usb_otg_hs",
3076 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
3077 .main_clk = "hsotgusb_ick",
3078 .prcm = {
3079 .omap2 = {
3080 .prcm_reg_id = 1,
3081 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
3082 .module_offs = CORE_MOD,
3083 .idlest_reg_id = 1,
3084 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
3085 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
3086 },
3087 },
3088 .masters = omap3xxx_usbhsotg_masters,
3089 .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
3090 .slaves = omap3xxx_usbhsotg_slaves,
3091 .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
3092 .class = &usbotg_class,
3093
3094 /*
3095 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
3096 * broken when autoidle is enabled
3097 * workaround is to disable the autoidle bit at module level.
3098 */
3099 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
3100 | HWMOD_SWSUP_MSTANDBY,
3101 };
3102
3103 /* usb_otg_hs */
3104 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
3105
3106 { .name = "mc", .irq = 71 },
3107 { .irq = -1 }
3108 };
3109
3110 static struct omap_hwmod_class am35xx_usbotg_class = {
3111 .name = "am35xx_usbotg",
3112 .sysc = NULL,
3113 };
3114
3115 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
3116 .name = "am35x_otg_hs",
3117 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
3118 .main_clk = NULL,
3119 .prcm = {
3120 .omap2 = {
3121 },
3122 },
3123 .masters = am35xx_usbhsotg_masters,
3124 .masters_cnt = ARRAY_SIZE(am35xx_usbhsotg_masters),
3125 .slaves = am35xx_usbhsotg_slaves,
3126 .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves),
3127 .class = &am35xx_usbotg_class,
3128 };
3129
3130 /* MMC/SD/SDIO common */
3131
3132 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
3133 .rev_offs = 0x1fc,
3134 .sysc_offs = 0x10,
3135 .syss_offs = 0x14,
3136 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3137 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3138 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3139 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3140 .sysc_fields = &omap_hwmod_sysc_type1,
3141 };
3142
3143 static struct omap_hwmod_class omap34xx_mmc_class = {
3144 .name = "mmc",
3145 .sysc = &omap34xx_mmc_sysc,
3146 };
3147
3148 /* MMC/SD/SDIO1 */
3149
3150 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
3151 { .irq = 83, },
3152 { .irq = -1 }
3153 };
3154
3155 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
3156 { .name = "tx", .dma_req = 61, },
3157 { .name = "rx", .dma_req = 62, },
3158 { .dma_req = -1 }
3159 };
3160
3161 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
3162 { .role = "dbck", .clk = "omap_32k_fck", },
3163 };
3164
3165 static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
3166 &omap3xxx_l4_core__mmc1,
3167 };
3168
3169 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3170 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3171 };
3172
3173 /* See 35xx errata 2.1.1.128 in SPRZ278F */
3174 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
3175 .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
3176 OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
3177 };
3178
3179 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
3180 .name = "mmc1",
3181 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
3182 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
3183 .opt_clks = omap34xx_mmc1_opt_clks,
3184 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3185 .main_clk = "mmchs1_fck",
3186 .prcm = {
3187 .omap2 = {
3188 .module_offs = CORE_MOD,
3189 .prcm_reg_id = 1,
3190 .module_bit = OMAP3430_EN_MMC1_SHIFT,
3191 .idlest_reg_id = 1,
3192 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3193 },
3194 },
3195 .dev_attr = &mmc1_pre_es3_dev_attr,
3196 .slaves = omap3xxx_mmc1_slaves,
3197 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3198 .class = &omap34xx_mmc_class,
3199 };
3200
3201 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
3202 .name = "mmc1",
3203 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
3204 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
3205 .opt_clks = omap34xx_mmc1_opt_clks,
3206 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3207 .main_clk = "mmchs1_fck",
3208 .prcm = {
3209 .omap2 = {
3210 .module_offs = CORE_MOD,
3211 .prcm_reg_id = 1,
3212 .module_bit = OMAP3430_EN_MMC1_SHIFT,
3213 .idlest_reg_id = 1,
3214 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3215 },
3216 },
3217 .dev_attr = &mmc1_dev_attr,
3218 .slaves = omap3xxx_mmc1_slaves,
3219 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3220 .class = &omap34xx_mmc_class,
3221 };
3222
3223 /* MMC/SD/SDIO2 */
3224
3225 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
3226 { .irq = INT_24XX_MMC2_IRQ, },
3227 { .irq = -1 }
3228 };
3229
3230 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
3231 { .name = "tx", .dma_req = 47, },
3232 { .name = "rx", .dma_req = 48, },
3233 { .dma_req = -1 }
3234 };
3235
3236 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
3237 { .role = "dbck", .clk = "omap_32k_fck", },
3238 };
3239
3240 static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3241 &omap3xxx_l4_core__mmc2,
3242 };
3243
3244 /* See 35xx errata 2.1.1.128 in SPRZ278F */
3245 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
3246 .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
3247 };
3248
3249 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
3250 .name = "mmc2",
3251 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
3252 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
3253 .opt_clks = omap34xx_mmc2_opt_clks,
3254 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3255 .main_clk = "mmchs2_fck",
3256 .prcm = {
3257 .omap2 = {
3258 .module_offs = CORE_MOD,
3259 .prcm_reg_id = 1,
3260 .module_bit = OMAP3430_EN_MMC2_SHIFT,
3261 .idlest_reg_id = 1,
3262 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3263 },
3264 },
3265 .dev_attr = &mmc2_pre_es3_dev_attr,
3266 .slaves = omap3xxx_mmc2_slaves,
3267 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3268 .class = &omap34xx_mmc_class,
3269 };
3270
3271 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
3272 .name = "mmc2",
3273 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
3274 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
3275 .opt_clks = omap34xx_mmc2_opt_clks,
3276 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3277 .main_clk = "mmchs2_fck",
3278 .prcm = {
3279 .omap2 = {
3280 .module_offs = CORE_MOD,
3281 .prcm_reg_id = 1,
3282 .module_bit = OMAP3430_EN_MMC2_SHIFT,
3283 .idlest_reg_id = 1,
3284 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3285 },
3286 },
3287 .slaves = omap3xxx_mmc2_slaves,
3288 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3289 .class = &omap34xx_mmc_class,
3290 };
3291
3292 /* MMC/SD/SDIO3 */
3293
3294 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
3295 { .irq = 94, },
3296 { .irq = -1 }
3297 };
3298
3299 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
3300 { .name = "tx", .dma_req = 77, },
3301 { .name = "rx", .dma_req = 78, },
3302 { .dma_req = -1 }
3303 };
3304
3305 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
3306 { .role = "dbck", .clk = "omap_32k_fck", },
3307 };
3308
3309 static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3310 &omap3xxx_l4_core__mmc3,
3311 };
3312
3313 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3314 .name = "mmc3",
3315 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
3316 .sdma_reqs = omap34xx_mmc3_sdma_reqs,
3317 .opt_clks = omap34xx_mmc3_opt_clks,
3318 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
3319 .main_clk = "mmchs3_fck",
3320 .prcm = {
3321 .omap2 = {
3322 .prcm_reg_id = 1,
3323 .module_bit = OMAP3430_EN_MMC3_SHIFT,
3324 .idlest_reg_id = 1,
3325 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
3326 },
3327 },
3328 .slaves = omap3xxx_mmc3_slaves,
3329 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc3_slaves),
3330 .class = &omap34xx_mmc_class,
3331 };
3332
3333 /*
3334 * 'usb_host_hs' class
3335 * high-speed multi-port usb host controller
3336 */
3337 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3338 .master = &omap3xxx_usb_host_hs_hwmod,
3339 .slave = &omap3xxx_l3_main_hwmod,
3340 .clk = "core_l3_ick",
3341 .user = OCP_USER_MPU,
3342 };
3343
3344 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
3345 .rev_offs = 0x0000,
3346 .sysc_offs = 0x0010,
3347 .syss_offs = 0x0014,
3348 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
3349 SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
3350 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
3351 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3352 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
3353 .sysc_fields = &omap_hwmod_sysc_type1,
3354 };
3355
3356 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
3357 .name = "usb_host_hs",
3358 .sysc = &omap3xxx_usb_host_hs_sysc,
3359 };
3360
3361 static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_masters[] = {
3362 &omap3xxx_usb_host_hs__l3_main_2,
3363 };
3364
3365 static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3366 {
3367 .name = "uhh",
3368 .pa_start = 0x48064000,
3369 .pa_end = 0x480643ff,
3370 .flags = ADDR_TYPE_RT
3371 },
3372 {
3373 .name = "ohci",
3374 .pa_start = 0x48064400,
3375 .pa_end = 0x480647ff,
3376 },
3377 {
3378 .name = "ehci",
3379 .pa_start = 0x48064800,
3380 .pa_end = 0x48064cff,
3381 },
3382 {}
3383 };
3384
3385 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3386 .master = &omap3xxx_l4_core_hwmod,
3387 .slave = &omap3xxx_usb_host_hs_hwmod,
3388 .clk = "usbhost_ick",
3389 .addr = omap3xxx_usb_host_hs_addrs,
3390 .user = OCP_USER_MPU | OCP_USER_SDMA,
3391 };
3392
3393 static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_slaves[] = {
3394 &omap3xxx_l4_core__usb_host_hs,
3395 };
3396
3397 static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
3398 { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
3399 };
3400
3401 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
3402 { .name = "ohci-irq", .irq = 76 },
3403 { .name = "ehci-irq", .irq = 77 },
3404 { .irq = -1 }
3405 };
3406
3407 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
3408 .name = "usb_host_hs",
3409 .class = &omap3xxx_usb_host_hs_hwmod_class,
3410 .clkdm_name = "l3_init_clkdm",
3411 .mpu_irqs = omap3xxx_usb_host_hs_irqs,
3412 .main_clk = "usbhost_48m_fck",
3413 .prcm = {
3414 .omap2 = {
3415 .module_offs = OMAP3430ES2_USBHOST_MOD,
3416 .prcm_reg_id = 1,
3417 .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
3418 .idlest_reg_id = 1,
3419 .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
3420 .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
3421 },
3422 },
3423 .opt_clks = omap3xxx_usb_host_hs_opt_clks,
3424 .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
3425 .slaves = omap3xxx_usb_host_hs_slaves,
3426 .slaves_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_slaves),
3427 .masters = omap3xxx_usb_host_hs_masters,
3428 .masters_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_masters),
3429
3430 /*
3431 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3432 * id: i660
3433 *
3434 * Description:
3435 * In the following configuration :
3436 * - USBHOST module is set to smart-idle mode
3437 * - PRCM asserts idle_req to the USBHOST module ( This typically
3438 * happens when the system is going to a low power mode : all ports
3439 * have been suspended, the master part of the USBHOST module has
3440 * entered the standby state, and SW has cut the functional clocks)
3441 * - an USBHOST interrupt occurs before the module is able to answer
3442 * idle_ack, typically a remote wakeup IRQ.
3443 * Then the USB HOST module will enter a deadlock situation where it
3444 * is no more accessible nor functional.
3445 *
3446 * Workaround:
3447 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3448 */
3449
3450 /*
3451 * Errata: USB host EHCI may stall when entering smart-standby mode
3452 * Id: i571
3453 *
3454 * Description:
3455 * When the USBHOST module is set to smart-standby mode, and when it is
3456 * ready to enter the standby state (i.e. all ports are suspended and
3457 * all attached devices are in suspend mode), then it can wrongly assert
3458 * the Mstandby signal too early while there are still some residual OCP
3459 * transactions ongoing. If this condition occurs, the internal state
3460 * machine may go to an undefined state and the USB link may be stuck
3461 * upon the next resume.
3462 *
3463 * Workaround:
3464 * Don't use smart standby; use only force standby,
3465 * hence HWMOD_SWSUP_MSTANDBY
3466 */
3467
3468 /*
3469 * During system boot; If the hwmod framework resets the module
3470 * the module will have smart idle settings; which can lead to deadlock
3471 * (above Errata Id:i660); so, dont reset the module during boot;
3472 * Use HWMOD_INIT_NO_RESET.
3473 */
3474
3475 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3476 HWMOD_INIT_NO_RESET,
3477 };
3478
3479 /*
3480 * 'usb_tll_hs' class
3481 * usb_tll_hs module is the adapter on the usb_host_hs ports
3482 */
3483 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
3484 .rev_offs = 0x0000,
3485 .sysc_offs = 0x0010,
3486 .syss_offs = 0x0014,
3487 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3488 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3489 SYSC_HAS_AUTOIDLE),
3490 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3491 .sysc_fields = &omap_hwmod_sysc_type1,
3492 };
3493
3494 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
3495 .name = "usb_tll_hs",
3496 .sysc = &omap3xxx_usb_tll_hs_sysc,
3497 };
3498
3499 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
3500 { .name = "tll-irq", .irq = 78 },
3501 { .irq = -1 }
3502 };
3503
3504 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3505 {
3506 .name = "tll",
3507 .pa_start = 0x48062000,
3508 .pa_end = 0x48062fff,
3509 .flags = ADDR_TYPE_RT
3510 },
3511 {}
3512 };
3513
3514 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3515 .master = &omap3xxx_l4_core_hwmod,
3516 .slave = &omap3xxx_usb_tll_hs_hwmod,
3517 .clk = "usbtll_ick",
3518 .addr = omap3xxx_usb_tll_hs_addrs,
3519 .user = OCP_USER_MPU | OCP_USER_SDMA,
3520 };
3521
3522 static struct omap_hwmod_ocp_if *omap3xxx_usb_tll_hs_slaves[] = {
3523 &omap3xxx_l4_core__usb_tll_hs,
3524 };
3525
3526 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
3527 .name = "usb_tll_hs",
3528 .class = &omap3xxx_usb_tll_hs_hwmod_class,
3529 .clkdm_name = "l3_init_clkdm",
3530 .mpu_irqs = omap3xxx_usb_tll_hs_irqs,
3531 .main_clk = "usbtll_fck",
3532 .prcm = {
3533 .omap2 = {
3534 .module_offs = CORE_MOD,
3535 .prcm_reg_id = 3,
3536 .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
3537 .idlest_reg_id = 3,
3538 .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
3539 },
3540 },
3541 .slaves = omap3xxx_usb_tll_hs_slaves,
3542 .slaves_cnt = ARRAY_SIZE(omap3xxx_usb_tll_hs_slaves),
3543 };
3544
3545 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
3546 &omap3xxx_l3_main_hwmod,
3547 &omap3xxx_l4_core_hwmod,
3548 &omap3xxx_l4_per_hwmod,
3549 &omap3xxx_l4_wkup_hwmod,
3550 &omap3xxx_mmc3_hwmod,
3551 &omap3xxx_mpu_hwmod,
3552
3553 &omap3xxx_timer1_hwmod,
3554 &omap3xxx_timer2_hwmod,
3555 &omap3xxx_timer3_hwmod,
3556 &omap3xxx_timer4_hwmod,
3557 &omap3xxx_timer5_hwmod,
3558 &omap3xxx_timer6_hwmod,
3559 &omap3xxx_timer7_hwmod,
3560 &omap3xxx_timer8_hwmod,
3561 &omap3xxx_timer9_hwmod,
3562 &omap3xxx_timer10_hwmod,
3563 &omap3xxx_timer11_hwmod,
3564
3565 &omap3xxx_wd_timer2_hwmod,
3566 &omap3xxx_uart1_hwmod,
3567 &omap3xxx_uart2_hwmod,
3568 &omap3xxx_uart3_hwmod,
3569
3570 /* i2c class */
3571 &omap3xxx_i2c1_hwmod,
3572 &omap3xxx_i2c2_hwmod,
3573 &omap3xxx_i2c3_hwmod,
3574
3575 /* gpio class */
3576 &omap3xxx_gpio1_hwmod,
3577 &omap3xxx_gpio2_hwmod,
3578 &omap3xxx_gpio3_hwmod,
3579 &omap3xxx_gpio4_hwmod,
3580 &omap3xxx_gpio5_hwmod,
3581 &omap3xxx_gpio6_hwmod,
3582
3583 /* dma_system class*/
3584 &omap3xxx_dma_system_hwmod,
3585
3586 /* mcbsp class */
3587 &omap3xxx_mcbsp1_hwmod,
3588 &omap3xxx_mcbsp2_hwmod,
3589 &omap3xxx_mcbsp3_hwmod,
3590 &omap3xxx_mcbsp4_hwmod,
3591 &omap3xxx_mcbsp5_hwmod,
3592 &omap3xxx_mcbsp2_sidetone_hwmod,
3593 &omap3xxx_mcbsp3_sidetone_hwmod,
3594
3595
3596 /* mcspi class */
3597 &omap34xx_mcspi1,
3598 &omap34xx_mcspi2,
3599 &omap34xx_mcspi3,
3600 &omap34xx_mcspi4,
3601
3602 NULL,
3603 };
3604
3605 /* GP-only hwmods */
3606 static __initdata struct omap_hwmod *omap3xxx_gp_hwmods[] = {
3607 &omap3xxx_timer12_hwmod,
3608 NULL
3609 };
3610
3611 /* 3430ES1-only hwmods */
3612 static __initdata struct omap_hwmod *omap3430es1_hwmods[] = {
3613 &omap3430es1_dss_core_hwmod,
3614 NULL
3615 };
3616
3617 /* 3430ES2+-only hwmods */
3618 static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = {
3619 &omap3xxx_dss_core_hwmod,
3620 &omap3xxx_usbhsotg_hwmod,
3621 &omap3xxx_usb_host_hs_hwmod,
3622 &omap3xxx_usb_tll_hs_hwmod,
3623 NULL
3624 };
3625
3626 /* <= 3430ES3-only hwmods */
3627 static struct omap_hwmod *omap3430_pre_es3_hwmods[] __initdata = {
3628 &omap3xxx_pre_es3_mmc1_hwmod,
3629 &omap3xxx_pre_es3_mmc2_hwmod,
3630 NULL
3631 };
3632
3633 /* 3430ES3+-only hwmods */
3634 static struct omap_hwmod *omap3430_es3plus_hwmods[] __initdata = {
3635 &omap3xxx_es3plus_mmc1_hwmod,
3636 &omap3xxx_es3plus_mmc2_hwmod,
3637 NULL
3638 };
3639
3640 /* 34xx-only hwmods (all ES revisions) */
3641 static __initdata struct omap_hwmod *omap34xx_hwmods[] = {
3642 &omap3xxx_iva_hwmod,
3643 &omap34xx_sr1_hwmod,
3644 &omap34xx_sr2_hwmod,
3645 &omap3xxx_mailbox_hwmod,
3646 NULL
3647 };
3648
3649 /* 36xx-only hwmods (all ES revisions) */
3650 static __initdata struct omap_hwmod *omap36xx_hwmods[] = {
3651 &omap3xxx_iva_hwmod,
3652 &omap3xxx_uart4_hwmod,
3653 &omap3xxx_dss_core_hwmod,
3654 &omap36xx_sr1_hwmod,
3655 &omap36xx_sr2_hwmod,
3656 &omap3xxx_usbhsotg_hwmod,
3657 &omap3xxx_mailbox_hwmod,
3658 &omap3xxx_usb_host_hs_hwmod,
3659 &omap3xxx_usb_tll_hs_hwmod,
3660 &omap3xxx_es3plus_mmc1_hwmod,
3661 &omap3xxx_es3plus_mmc2_hwmod,
3662 NULL
3663 };
3664
3665 static __initdata struct omap_hwmod *am35xx_hwmods[] = {
3666 &omap3xxx_dss_core_hwmod, /* XXX ??? */
3667 &am35xx_usbhsotg_hwmod,
3668 &am35xx_uart4_hwmod,
3669 &omap3xxx_usb_host_hs_hwmod,
3670 &omap3xxx_usb_tll_hs_hwmod,
3671 &omap3xxx_es3plus_mmc1_hwmod,
3672 &omap3xxx_es3plus_mmc2_hwmod,
3673 NULL
3674 };
3675
3676 static __initdata struct omap_hwmod *omap3xxx_dss_hwmods[] = {
3677 /* dss class */
3678 &omap3xxx_dss_dispc_hwmod,
3679 &omap3xxx_dss_dsi1_hwmod,
3680 &omap3xxx_dss_rfbi_hwmod,
3681 &omap3xxx_dss_venc_hwmod,
3682 NULL
3683 };
3684
3685 int __init omap3xxx_hwmod_init(void)
3686 {
3687 int r;
3688 struct omap_hwmod **h = NULL;
3689 unsigned int rev;
3690
3691 /* Register hwmods common to all OMAP3 */
3692 r = omap_hwmod_register(omap3xxx_hwmods);
3693 if (r < 0)
3694 return r;
3695
3696 /* Register GP-only hwmods. */
3697 if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
3698 r = omap_hwmod_register(omap3xxx_gp_hwmods);
3699 if (r < 0)
3700 return r;
3701 }
3702
3703 rev = omap_rev();
3704
3705 /*
3706 * Register hwmods common to individual OMAP3 families, all
3707 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3708 * All possible revisions should be included in this conditional.
3709 */
3710 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3711 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3712 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3713 h = omap34xx_hwmods;
3714 } else if (rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1) {
3715 h = am35xx_hwmods;
3716 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3717 rev == OMAP3630_REV_ES1_2) {
3718 h = omap36xx_hwmods;
3719 } else {
3720 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3721 return -EINVAL;
3722 };
3723
3724 r = omap_hwmod_register(h);
3725 if (r < 0)
3726 return r;
3727
3728 /*
3729 * Register hwmods specific to certain ES levels of a
3730 * particular family of silicon (e.g., 34xx ES1.0)
3731 */
3732 h = NULL;
3733 if (rev == OMAP3430_REV_ES1_0) {
3734 h = omap3430es1_hwmods;
3735 } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3736 rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3737 rev == OMAP3430_REV_ES3_1_2) {
3738 h = omap3430es2plus_hwmods;
3739 };
3740
3741 if (h) {
3742 r = omap_hwmod_register(h);
3743 if (r < 0)
3744 return r;
3745 }
3746
3747 h = NULL;
3748 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3749 rev == OMAP3430_REV_ES2_1) {
3750 h = omap3430_pre_es3_hwmods;
3751 } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3752 rev == OMAP3430_REV_ES3_1_2) {
3753 h = omap3430_es3plus_hwmods;
3754 };
3755
3756 if (h)
3757 r = omap_hwmod_register(h);
3758 if (r < 0)
3759 return r;
3760
3761 /*
3762 * DSS code presumes that dss_core hwmod is handled first,
3763 * _before_ any other DSS related hwmods so register common
3764 * DSS hwmods last to ensure that dss_core is already registered.
3765 * Otherwise some change things may happen, for ex. if dispc
3766 * is handled before dss_core and DSS is enabled in bootloader
3767 * DIPSC will be reset with outputs enabled which sometimes leads
3768 * to unrecoverable L3 error.
3769 * XXX The long-term fix to this is to ensure modules are set up
3770 * in dependency order in the hwmod core code.
3771 */
3772 r = omap_hwmod_register(omap3xxx_dss_hwmods);
3773
3774 return r;
3775 }
Linux kernel - Deliverables
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