2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * The data in this file should be completely autogeneratable from
13 * the TI hardware database or other technical documentation.
15 * XXX these should be marked initdata for multi-OMAP kernels
17 #include <plat/omap_hwmod.h>
18 #include <mach/irqs.h>
21 #include <plat/serial.h>
22 #include <plat/l3_3xxx.h>
23 #include <plat/l4_3xxx.h>
25 #include <plat/gpio.h>
27 #include <plat/mcbsp.h>
28 #include <plat/mcspi.h>
29 #include <plat/dmtimer.h>
31 #include "omap_hwmod_common_data.h"
33 #include "smartreflex.h"
34 #include "prm-regbits-34xx.h"
35 #include "cm-regbits-34xx.h"
37 #include <mach/am35xx.h>
40 * OMAP3xxx hardware module integration data
42 * All of the data in this section should be autogeneratable from the
43 * TI hardware database or other technical documentation. Data that
44 * is driver-specific or driver-kernel integration-specific belongs
53 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs
[] = {
54 { .irq
= INT_34XX_L3_DBG_IRQ
},
55 { .irq
= INT_34XX_L3_APP_IRQ
},
59 static struct omap_hwmod omap3xxx_l3_main_hwmod
= {
61 .class = &l3_hwmod_class
,
62 .mpu_irqs
= omap3xxx_l3_main_irqs
,
63 .flags
= HWMOD_NO_IDLEST
,
67 static struct omap_hwmod omap3xxx_l4_core_hwmod
= {
69 .class = &l4_hwmod_class
,
70 .flags
= HWMOD_NO_IDLEST
,
74 static struct omap_hwmod omap3xxx_l4_per_hwmod
= {
76 .class = &l4_hwmod_class
,
77 .flags
= HWMOD_NO_IDLEST
,
81 static struct omap_hwmod omap3xxx_l4_wkup_hwmod
= {
83 .class = &l4_hwmod_class
,
84 .flags
= HWMOD_NO_IDLEST
,
88 static struct omap_hwmod omap3xxx_l4_sec_hwmod
= {
90 .class = &l4_hwmod_class
,
91 .flags
= HWMOD_NO_IDLEST
,
95 static struct omap_hwmod omap3xxx_mpu_hwmod
= {
97 .class = &mpu_hwmod_class
,
98 .main_clk
= "arm_fck",
102 static struct omap_hwmod_rst_info omap3xxx_iva_resets
[] = {
103 { .name
= "logic", .rst_shift
= 0 },
104 { .name
= "seq0", .rst_shift
= 1 },
105 { .name
= "seq1", .rst_shift
= 2 },
108 static struct omap_hwmod omap3xxx_iva_hwmod
= {
110 .class = &iva_hwmod_class
,
111 .clkdm_name
= "iva2_clkdm",
112 .rst_lines
= omap3xxx_iva_resets
,
113 .rst_lines_cnt
= ARRAY_SIZE(omap3xxx_iva_resets
),
114 .main_clk
= "iva2_ck",
118 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc
= {
122 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_CLOCKACTIVITY
|
123 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
124 SYSC_HAS_EMUFREE
| SYSC_HAS_AUTOIDLE
),
125 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
126 .sysc_fields
= &omap_hwmod_sysc_type1
,
129 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class
= {
131 .sysc
= &omap3xxx_timer_1ms_sysc
,
132 .rev
= OMAP_TIMER_IP_VERSION_1
,
135 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc
= {
139 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_ENAWAKEUP
|
140 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
),
141 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
142 .sysc_fields
= &omap_hwmod_sysc_type1
,
145 static struct omap_hwmod_class omap3xxx_timer_hwmod_class
= {
147 .sysc
= &omap3xxx_timer_sysc
,
148 .rev
= OMAP_TIMER_IP_VERSION_1
,
151 /* secure timers dev attribute */
152 static struct omap_timer_capability_dev_attr capability_secure_dev_attr
= {
153 .timer_capability
= OMAP_TIMER_SECURE
,
156 /* always-on timers dev attribute */
157 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr
= {
158 .timer_capability
= OMAP_TIMER_ALWON
,
161 /* pwm timers dev attribute */
162 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr
= {
163 .timer_capability
= OMAP_TIMER_HAS_PWM
,
167 static struct omap_hwmod omap3xxx_timer1_hwmod
= {
169 .mpu_irqs
= omap2_timer1_mpu_irqs
,
170 .main_clk
= "gpt1_fck",
174 .module_bit
= OMAP3430_EN_GPT1_SHIFT
,
175 .module_offs
= WKUP_MOD
,
177 .idlest_idle_bit
= OMAP3430_ST_GPT1_SHIFT
,
180 .dev_attr
= &capability_alwon_dev_attr
,
181 .class = &omap3xxx_timer_1ms_hwmod_class
,
185 static struct omap_hwmod omap3xxx_timer2_hwmod
= {
187 .mpu_irqs
= omap2_timer2_mpu_irqs
,
188 .main_clk
= "gpt2_fck",
192 .module_bit
= OMAP3430_EN_GPT2_SHIFT
,
193 .module_offs
= OMAP3430_PER_MOD
,
195 .idlest_idle_bit
= OMAP3430_ST_GPT2_SHIFT
,
198 .dev_attr
= &capability_alwon_dev_attr
,
199 .class = &omap3xxx_timer_1ms_hwmod_class
,
203 static struct omap_hwmod omap3xxx_timer3_hwmod
= {
205 .mpu_irqs
= omap2_timer3_mpu_irqs
,
206 .main_clk
= "gpt3_fck",
210 .module_bit
= OMAP3430_EN_GPT3_SHIFT
,
211 .module_offs
= OMAP3430_PER_MOD
,
213 .idlest_idle_bit
= OMAP3430_ST_GPT3_SHIFT
,
216 .dev_attr
= &capability_alwon_dev_attr
,
217 .class = &omap3xxx_timer_hwmod_class
,
221 static struct omap_hwmod omap3xxx_timer4_hwmod
= {
223 .mpu_irqs
= omap2_timer4_mpu_irqs
,
224 .main_clk
= "gpt4_fck",
228 .module_bit
= OMAP3430_EN_GPT4_SHIFT
,
229 .module_offs
= OMAP3430_PER_MOD
,
231 .idlest_idle_bit
= OMAP3430_ST_GPT4_SHIFT
,
234 .dev_attr
= &capability_alwon_dev_attr
,
235 .class = &omap3xxx_timer_hwmod_class
,
239 static struct omap_hwmod omap3xxx_timer5_hwmod
= {
241 .mpu_irqs
= omap2_timer5_mpu_irqs
,
242 .main_clk
= "gpt5_fck",
246 .module_bit
= OMAP3430_EN_GPT5_SHIFT
,
247 .module_offs
= OMAP3430_PER_MOD
,
249 .idlest_idle_bit
= OMAP3430_ST_GPT5_SHIFT
,
252 .dev_attr
= &capability_alwon_dev_attr
,
253 .class = &omap3xxx_timer_hwmod_class
,
257 static struct omap_hwmod omap3xxx_timer6_hwmod
= {
259 .mpu_irqs
= omap2_timer6_mpu_irqs
,
260 .main_clk
= "gpt6_fck",
264 .module_bit
= OMAP3430_EN_GPT6_SHIFT
,
265 .module_offs
= OMAP3430_PER_MOD
,
267 .idlest_idle_bit
= OMAP3430_ST_GPT6_SHIFT
,
270 .dev_attr
= &capability_alwon_dev_attr
,
271 .class = &omap3xxx_timer_hwmod_class
,
275 static struct omap_hwmod omap3xxx_timer7_hwmod
= {
277 .mpu_irqs
= omap2_timer7_mpu_irqs
,
278 .main_clk
= "gpt7_fck",
282 .module_bit
= OMAP3430_EN_GPT7_SHIFT
,
283 .module_offs
= OMAP3430_PER_MOD
,
285 .idlest_idle_bit
= OMAP3430_ST_GPT7_SHIFT
,
288 .dev_attr
= &capability_alwon_dev_attr
,
289 .class = &omap3xxx_timer_hwmod_class
,
293 static struct omap_hwmod omap3xxx_timer8_hwmod
= {
295 .mpu_irqs
= omap2_timer8_mpu_irqs
,
296 .main_clk
= "gpt8_fck",
300 .module_bit
= OMAP3430_EN_GPT8_SHIFT
,
301 .module_offs
= OMAP3430_PER_MOD
,
303 .idlest_idle_bit
= OMAP3430_ST_GPT8_SHIFT
,
306 .dev_attr
= &capability_pwm_dev_attr
,
307 .class = &omap3xxx_timer_hwmod_class
,
311 static struct omap_hwmod omap3xxx_timer9_hwmod
= {
313 .mpu_irqs
= omap2_timer9_mpu_irqs
,
314 .main_clk
= "gpt9_fck",
318 .module_bit
= OMAP3430_EN_GPT9_SHIFT
,
319 .module_offs
= OMAP3430_PER_MOD
,
321 .idlest_idle_bit
= OMAP3430_ST_GPT9_SHIFT
,
324 .dev_attr
= &capability_pwm_dev_attr
,
325 .class = &omap3xxx_timer_hwmod_class
,
329 static struct omap_hwmod omap3xxx_timer10_hwmod
= {
331 .mpu_irqs
= omap2_timer10_mpu_irqs
,
332 .main_clk
= "gpt10_fck",
336 .module_bit
= OMAP3430_EN_GPT10_SHIFT
,
337 .module_offs
= CORE_MOD
,
339 .idlest_idle_bit
= OMAP3430_ST_GPT10_SHIFT
,
342 .dev_attr
= &capability_pwm_dev_attr
,
343 .class = &omap3xxx_timer_1ms_hwmod_class
,
347 static struct omap_hwmod omap3xxx_timer11_hwmod
= {
349 .mpu_irqs
= omap2_timer11_mpu_irqs
,
350 .main_clk
= "gpt11_fck",
354 .module_bit
= OMAP3430_EN_GPT11_SHIFT
,
355 .module_offs
= CORE_MOD
,
357 .idlest_idle_bit
= OMAP3430_ST_GPT11_SHIFT
,
360 .dev_attr
= &capability_pwm_dev_attr
,
361 .class = &omap3xxx_timer_hwmod_class
,
365 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs
[] = {
370 static struct omap_hwmod omap3xxx_timer12_hwmod
= {
372 .mpu_irqs
= omap3xxx_timer12_mpu_irqs
,
373 .main_clk
= "gpt12_fck",
377 .module_bit
= OMAP3430_EN_GPT12_SHIFT
,
378 .module_offs
= WKUP_MOD
,
380 .idlest_idle_bit
= OMAP3430_ST_GPT12_SHIFT
,
383 .dev_attr
= &capability_secure_dev_attr
,
384 .class = &omap3xxx_timer_hwmod_class
,
389 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
393 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc
= {
397 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_EMUFREE
|
398 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
399 SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
400 SYSS_HAS_RESET_STATUS
),
401 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
402 .sysc_fields
= &omap_hwmod_sysc_type1
,
406 static struct omap_hwmod_class_sysconfig i2c_sysc
= {
410 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
411 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
412 SYSC_HAS_AUTOIDLE
| SYSS_HAS_RESET_STATUS
),
413 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
414 .clockact
= CLOCKACT_TEST_ICLK
,
415 .sysc_fields
= &omap_hwmod_sysc_type1
,
418 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class
= {
420 .sysc
= &omap3xxx_wd_timer_sysc
,
421 .pre_shutdown
= &omap2_wd_timer_disable
,
422 .reset
= &omap2_wd_timer_reset
,
425 static struct omap_hwmod omap3xxx_wd_timer2_hwmod
= {
427 .class = &omap3xxx_wd_timer_hwmod_class
,
428 .main_clk
= "wdt2_fck",
432 .module_bit
= OMAP3430_EN_WDT2_SHIFT
,
433 .module_offs
= WKUP_MOD
,
435 .idlest_idle_bit
= OMAP3430_ST_WDT2_SHIFT
,
439 * XXX: Use software supervised mode, HW supervised smartidle seems to
440 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
442 .flags
= HWMOD_SWSUP_SIDLE
,
446 static struct omap_hwmod omap3xxx_uart1_hwmod
= {
448 .mpu_irqs
= omap2_uart1_mpu_irqs
,
449 .sdma_reqs
= omap2_uart1_sdma_reqs
,
450 .main_clk
= "uart1_fck",
453 .module_offs
= CORE_MOD
,
455 .module_bit
= OMAP3430_EN_UART1_SHIFT
,
457 .idlest_idle_bit
= OMAP3430_EN_UART1_SHIFT
,
460 .class = &omap2_uart_class
,
464 static struct omap_hwmod omap3xxx_uart2_hwmod
= {
466 .mpu_irqs
= omap2_uart2_mpu_irqs
,
467 .sdma_reqs
= omap2_uart2_sdma_reqs
,
468 .main_clk
= "uart2_fck",
471 .module_offs
= CORE_MOD
,
473 .module_bit
= OMAP3430_EN_UART2_SHIFT
,
475 .idlest_idle_bit
= OMAP3430_EN_UART2_SHIFT
,
478 .class = &omap2_uart_class
,
482 static struct omap_hwmod omap3xxx_uart3_hwmod
= {
484 .mpu_irqs
= omap2_uart3_mpu_irqs
,
485 .sdma_reqs
= omap2_uart3_sdma_reqs
,
486 .main_clk
= "uart3_fck",
489 .module_offs
= OMAP3430_PER_MOD
,
491 .module_bit
= OMAP3430_EN_UART3_SHIFT
,
493 .idlest_idle_bit
= OMAP3430_EN_UART3_SHIFT
,
496 .class = &omap2_uart_class
,
500 static struct omap_hwmod_irq_info uart4_mpu_irqs
[] = {
501 { .irq
= INT_36XX_UART4_IRQ
, },
505 static struct omap_hwmod_dma_info uart4_sdma_reqs
[] = {
506 { .name
= "rx", .dma_req
= OMAP36XX_DMA_UART4_RX
, },
507 { .name
= "tx", .dma_req
= OMAP36XX_DMA_UART4_TX
, },
511 static struct omap_hwmod omap36xx_uart4_hwmod
= {
513 .mpu_irqs
= uart4_mpu_irqs
,
514 .sdma_reqs
= uart4_sdma_reqs
,
515 .main_clk
= "uart4_fck",
518 .module_offs
= OMAP3430_PER_MOD
,
520 .module_bit
= OMAP3630_EN_UART4_SHIFT
,
522 .idlest_idle_bit
= OMAP3630_EN_UART4_SHIFT
,
525 .class = &omap2_uart_class
,
528 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs
[] = {
529 { .irq
= INT_35XX_UART4_IRQ
, },
532 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs
[] = {
533 { .name
= "rx", .dma_req
= AM35XX_DMA_UART4_RX
, },
534 { .name
= "tx", .dma_req
= AM35XX_DMA_UART4_TX
, },
537 static struct omap_hwmod am35xx_uart4_hwmod
= {
539 .mpu_irqs
= am35xx_uart4_mpu_irqs
,
540 .sdma_reqs
= am35xx_uart4_sdma_reqs
,
541 .main_clk
= "uart4_fck",
544 .module_offs
= CORE_MOD
,
546 .module_bit
= OMAP3430_EN_UART4_SHIFT
,
548 .idlest_idle_bit
= OMAP3430_EN_UART4_SHIFT
,
551 .class = &omap2_uart_class
,
554 static struct omap_hwmod_class i2c_class
= {
557 .rev
= OMAP_I2C_IP_VERSION_1
,
558 .reset
= &omap_i2c_reset
,
561 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs
[] = {
562 { .name
= "dispc", .dma_req
= 5 },
563 { .name
= "dsi1", .dma_req
= 74 },
568 static struct omap_hwmod_opt_clk dss_opt_clks
[] = {
570 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
571 * driver does not use these clocks.
573 { .role
= "sys_clk", .clk
= "dss2_alwon_fck" },
574 { .role
= "tv_clk", .clk
= "dss_tv_fck" },
575 /* required only on OMAP3430 */
576 { .role
= "tv_dac_clk", .clk
= "dss_96m_fck" },
579 static struct omap_hwmod omap3430es1_dss_core_hwmod
= {
581 .class = &omap2_dss_hwmod_class
,
582 .main_clk
= "dss1_alwon_fck", /* instead of dss_fck */
583 .sdma_reqs
= omap3xxx_dss_sdma_chs
,
587 .module_bit
= OMAP3430_EN_DSS1_SHIFT
,
588 .module_offs
= OMAP3430_DSS_MOD
,
590 .idlest_stdby_bit
= OMAP3430ES1_ST_DSS_SHIFT
,
593 .opt_clks
= dss_opt_clks
,
594 .opt_clks_cnt
= ARRAY_SIZE(dss_opt_clks
),
595 .flags
= HWMOD_NO_IDLEST
| HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
598 static struct omap_hwmod omap3xxx_dss_core_hwmod
= {
600 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
601 .class = &omap2_dss_hwmod_class
,
602 .main_clk
= "dss1_alwon_fck", /* instead of dss_fck */
603 .sdma_reqs
= omap3xxx_dss_sdma_chs
,
607 .module_bit
= OMAP3430_EN_DSS1_SHIFT
,
608 .module_offs
= OMAP3430_DSS_MOD
,
610 .idlest_idle_bit
= OMAP3430ES2_ST_DSS_IDLE_SHIFT
,
611 .idlest_stdby_bit
= OMAP3430ES2_ST_DSS_STDBY_SHIFT
,
614 .opt_clks
= dss_opt_clks
,
615 .opt_clks_cnt
= ARRAY_SIZE(dss_opt_clks
),
623 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc
= {
627 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_MIDLEMODE
|
628 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
|
630 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
631 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
632 .sysc_fields
= &omap_hwmod_sysc_type1
,
635 static struct omap_hwmod_class omap3_dispc_hwmod_class
= {
637 .sysc
= &omap3_dispc_sysc
,
640 static struct omap_hwmod omap3xxx_dss_dispc_hwmod
= {
642 .class = &omap3_dispc_hwmod_class
,
643 .mpu_irqs
= omap2_dispc_irqs
,
644 .main_clk
= "dss1_alwon_fck",
648 .module_bit
= OMAP3430_EN_DSS1_SHIFT
,
649 .module_offs
= OMAP3430_DSS_MOD
,
652 .flags
= HWMOD_NO_IDLEST
,
653 .dev_attr
= &omap2_3_dss_dispc_dev_attr
658 * display serial interface controller
661 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class
= {
665 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs
[] = {
671 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks
[] = {
672 { .role
= "sys_clk", .clk
= "dss2_alwon_fck" },
675 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod
= {
677 .class = &omap3xxx_dsi_hwmod_class
,
678 .mpu_irqs
= omap3xxx_dsi1_irqs
,
679 .main_clk
= "dss1_alwon_fck",
683 .module_bit
= OMAP3430_EN_DSS1_SHIFT
,
684 .module_offs
= OMAP3430_DSS_MOD
,
687 .opt_clks
= dss_dsi1_opt_clks
,
688 .opt_clks_cnt
= ARRAY_SIZE(dss_dsi1_opt_clks
),
689 .flags
= HWMOD_NO_IDLEST
,
692 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks
[] = {
693 { .role
= "ick", .clk
= "dss_ick" },
696 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod
= {
698 .class = &omap2_rfbi_hwmod_class
,
699 .main_clk
= "dss1_alwon_fck",
703 .module_bit
= OMAP3430_EN_DSS1_SHIFT
,
704 .module_offs
= OMAP3430_DSS_MOD
,
707 .opt_clks
= dss_rfbi_opt_clks
,
708 .opt_clks_cnt
= ARRAY_SIZE(dss_rfbi_opt_clks
),
709 .flags
= HWMOD_NO_IDLEST
,
712 static struct omap_hwmod_opt_clk dss_venc_opt_clks
[] = {
713 /* required only on OMAP3430 */
714 { .role
= "tv_dac_clk", .clk
= "dss_96m_fck" },
717 static struct omap_hwmod omap3xxx_dss_venc_hwmod
= {
719 .class = &omap2_venc_hwmod_class
,
720 .main_clk
= "dss_tv_fck",
724 .module_bit
= OMAP3430_EN_DSS1_SHIFT
,
725 .module_offs
= OMAP3430_DSS_MOD
,
728 .opt_clks
= dss_venc_opt_clks
,
729 .opt_clks_cnt
= ARRAY_SIZE(dss_venc_opt_clks
),
730 .flags
= HWMOD_NO_IDLEST
,
734 static struct omap_i2c_dev_attr i2c1_dev_attr
= {
735 .fifo_depth
= 8, /* bytes */
736 .flags
= OMAP_I2C_FLAG_APPLY_ERRATA_I207
|
737 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE
|
738 OMAP_I2C_FLAG_BUS_SHIFT_2
,
741 static struct omap_hwmod omap3xxx_i2c1_hwmod
= {
743 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
744 .mpu_irqs
= omap2_i2c1_mpu_irqs
,
745 .sdma_reqs
= omap2_i2c1_sdma_reqs
,
746 .main_clk
= "i2c1_fck",
749 .module_offs
= CORE_MOD
,
751 .module_bit
= OMAP3430_EN_I2C1_SHIFT
,
753 .idlest_idle_bit
= OMAP3430_ST_I2C1_SHIFT
,
757 .dev_attr
= &i2c1_dev_attr
,
761 static struct omap_i2c_dev_attr i2c2_dev_attr
= {
762 .fifo_depth
= 8, /* bytes */
763 .flags
= OMAP_I2C_FLAG_APPLY_ERRATA_I207
|
764 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE
|
765 OMAP_I2C_FLAG_BUS_SHIFT_2
,
768 static struct omap_hwmod omap3xxx_i2c2_hwmod
= {
770 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
771 .mpu_irqs
= omap2_i2c2_mpu_irqs
,
772 .sdma_reqs
= omap2_i2c2_sdma_reqs
,
773 .main_clk
= "i2c2_fck",
776 .module_offs
= CORE_MOD
,
778 .module_bit
= OMAP3430_EN_I2C2_SHIFT
,
780 .idlest_idle_bit
= OMAP3430_ST_I2C2_SHIFT
,
784 .dev_attr
= &i2c2_dev_attr
,
788 static struct omap_i2c_dev_attr i2c3_dev_attr
= {
789 .fifo_depth
= 64, /* bytes */
790 .flags
= OMAP_I2C_FLAG_APPLY_ERRATA_I207
|
791 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE
|
792 OMAP_I2C_FLAG_BUS_SHIFT_2
,
795 static struct omap_hwmod_irq_info i2c3_mpu_irqs
[] = {
796 { .irq
= INT_34XX_I2C3_IRQ
, },
800 static struct omap_hwmod_dma_info i2c3_sdma_reqs
[] = {
801 { .name
= "tx", .dma_req
= OMAP34XX_DMA_I2C3_TX
},
802 { .name
= "rx", .dma_req
= OMAP34XX_DMA_I2C3_RX
},
806 static struct omap_hwmod omap3xxx_i2c3_hwmod
= {
808 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
809 .mpu_irqs
= i2c3_mpu_irqs
,
810 .sdma_reqs
= i2c3_sdma_reqs
,
811 .main_clk
= "i2c3_fck",
814 .module_offs
= CORE_MOD
,
816 .module_bit
= OMAP3430_EN_I2C3_SHIFT
,
818 .idlest_idle_bit
= OMAP3430_ST_I2C3_SHIFT
,
822 .dev_attr
= &i2c3_dev_attr
,
827 * general purpose io module
830 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc
= {
834 .sysc_flags
= (SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
835 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
|
836 SYSS_HAS_RESET_STATUS
),
837 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
838 .sysc_fields
= &omap_hwmod_sysc_type1
,
841 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class
= {
843 .sysc
= &omap3xxx_gpio_sysc
,
848 static struct omap_gpio_dev_attr gpio_dev_attr
= {
854 static struct omap_hwmod_opt_clk gpio1_opt_clks
[] = {
855 { .role
= "dbclk", .clk
= "gpio1_dbck", },
858 static struct omap_hwmod omap3xxx_gpio1_hwmod
= {
860 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
861 .mpu_irqs
= omap2_gpio1_irqs
,
862 .main_clk
= "gpio1_ick",
863 .opt_clks
= gpio1_opt_clks
,
864 .opt_clks_cnt
= ARRAY_SIZE(gpio1_opt_clks
),
868 .module_bit
= OMAP3430_EN_GPIO1_SHIFT
,
869 .module_offs
= WKUP_MOD
,
871 .idlest_idle_bit
= OMAP3430_ST_GPIO1_SHIFT
,
874 .class = &omap3xxx_gpio_hwmod_class
,
875 .dev_attr
= &gpio_dev_attr
,
879 static struct omap_hwmod_opt_clk gpio2_opt_clks
[] = {
880 { .role
= "dbclk", .clk
= "gpio2_dbck", },
883 static struct omap_hwmod omap3xxx_gpio2_hwmod
= {
885 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
886 .mpu_irqs
= omap2_gpio2_irqs
,
887 .main_clk
= "gpio2_ick",
888 .opt_clks
= gpio2_opt_clks
,
889 .opt_clks_cnt
= ARRAY_SIZE(gpio2_opt_clks
),
893 .module_bit
= OMAP3430_EN_GPIO2_SHIFT
,
894 .module_offs
= OMAP3430_PER_MOD
,
896 .idlest_idle_bit
= OMAP3430_ST_GPIO2_SHIFT
,
899 .class = &omap3xxx_gpio_hwmod_class
,
900 .dev_attr
= &gpio_dev_attr
,
904 static struct omap_hwmod_opt_clk gpio3_opt_clks
[] = {
905 { .role
= "dbclk", .clk
= "gpio3_dbck", },
908 static struct omap_hwmod omap3xxx_gpio3_hwmod
= {
910 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
911 .mpu_irqs
= omap2_gpio3_irqs
,
912 .main_clk
= "gpio3_ick",
913 .opt_clks
= gpio3_opt_clks
,
914 .opt_clks_cnt
= ARRAY_SIZE(gpio3_opt_clks
),
918 .module_bit
= OMAP3430_EN_GPIO3_SHIFT
,
919 .module_offs
= OMAP3430_PER_MOD
,
921 .idlest_idle_bit
= OMAP3430_ST_GPIO3_SHIFT
,
924 .class = &omap3xxx_gpio_hwmod_class
,
925 .dev_attr
= &gpio_dev_attr
,
929 static struct omap_hwmod_opt_clk gpio4_opt_clks
[] = {
930 { .role
= "dbclk", .clk
= "gpio4_dbck", },
933 static struct omap_hwmod omap3xxx_gpio4_hwmod
= {
935 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
936 .mpu_irqs
= omap2_gpio4_irqs
,
937 .main_clk
= "gpio4_ick",
938 .opt_clks
= gpio4_opt_clks
,
939 .opt_clks_cnt
= ARRAY_SIZE(gpio4_opt_clks
),
943 .module_bit
= OMAP3430_EN_GPIO4_SHIFT
,
944 .module_offs
= OMAP3430_PER_MOD
,
946 .idlest_idle_bit
= OMAP3430_ST_GPIO4_SHIFT
,
949 .class = &omap3xxx_gpio_hwmod_class
,
950 .dev_attr
= &gpio_dev_attr
,
954 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs
[] = {
955 { .irq
= 33 }, /* INT_34XX_GPIO_BANK5 */
959 static struct omap_hwmod_opt_clk gpio5_opt_clks
[] = {
960 { .role
= "dbclk", .clk
= "gpio5_dbck", },
963 static struct omap_hwmod omap3xxx_gpio5_hwmod
= {
965 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
966 .mpu_irqs
= omap3xxx_gpio5_irqs
,
967 .main_clk
= "gpio5_ick",
968 .opt_clks
= gpio5_opt_clks
,
969 .opt_clks_cnt
= ARRAY_SIZE(gpio5_opt_clks
),
973 .module_bit
= OMAP3430_EN_GPIO5_SHIFT
,
974 .module_offs
= OMAP3430_PER_MOD
,
976 .idlest_idle_bit
= OMAP3430_ST_GPIO5_SHIFT
,
979 .class = &omap3xxx_gpio_hwmod_class
,
980 .dev_attr
= &gpio_dev_attr
,
984 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs
[] = {
985 { .irq
= 34 }, /* INT_34XX_GPIO_BANK6 */
989 static struct omap_hwmod_opt_clk gpio6_opt_clks
[] = {
990 { .role
= "dbclk", .clk
= "gpio6_dbck", },
993 static struct omap_hwmod omap3xxx_gpio6_hwmod
= {
995 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
996 .mpu_irqs
= omap3xxx_gpio6_irqs
,
997 .main_clk
= "gpio6_ick",
998 .opt_clks
= gpio6_opt_clks
,
999 .opt_clks_cnt
= ARRAY_SIZE(gpio6_opt_clks
),
1003 .module_bit
= OMAP3430_EN_GPIO6_SHIFT
,
1004 .module_offs
= OMAP3430_PER_MOD
,
1006 .idlest_idle_bit
= OMAP3430_ST_GPIO6_SHIFT
,
1009 .class = &omap3xxx_gpio_hwmod_class
,
1010 .dev_attr
= &gpio_dev_attr
,
1013 /* dma attributes */
1014 static struct omap_dma_dev_attr dma_dev_attr
= {
1015 .dev_caps
= RESERVE_CHANNEL
| DMA_LINKED_LCH
| GLOBAL_PRIORITY
|
1016 IS_CSSA_32
| IS_CDSA_32
| IS_RW_PRIORITY
,
1020 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc
= {
1022 .sysc_offs
= 0x002c,
1023 .syss_offs
= 0x0028,
1024 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
1025 SYSC_HAS_MIDLEMODE
| SYSC_HAS_CLOCKACTIVITY
|
1026 SYSC_HAS_EMUFREE
| SYSC_HAS_AUTOIDLE
|
1027 SYSS_HAS_RESET_STATUS
),
1028 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1029 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
1030 .sysc_fields
= &omap_hwmod_sysc_type1
,
1033 static struct omap_hwmod_class omap3xxx_dma_hwmod_class
= {
1035 .sysc
= &omap3xxx_dma_sysc
,
1039 static struct omap_hwmod omap3xxx_dma_system_hwmod
= {
1041 .class = &omap3xxx_dma_hwmod_class
,
1042 .mpu_irqs
= omap2_dma_system_irqs
,
1043 .main_clk
= "core_l3_ick",
1046 .module_offs
= CORE_MOD
,
1048 .module_bit
= OMAP3430_ST_SDMA_SHIFT
,
1050 .idlest_idle_bit
= OMAP3430_ST_SDMA_SHIFT
,
1053 .dev_attr
= &dma_dev_attr
,
1054 .flags
= HWMOD_NO_IDLEST
,
1059 * multi channel buffered serial port controller
1062 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc
= {
1063 .sysc_offs
= 0x008c,
1064 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_ENAWAKEUP
|
1065 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1066 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1067 .sysc_fields
= &omap_hwmod_sysc_type1
,
1071 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class
= {
1073 .sysc
= &omap3xxx_mcbsp_sysc
,
1074 .rev
= MCBSP_CONFIG_TYPE3
,
1078 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs
[] = {
1079 { .name
= "common", .irq
= 16 },
1080 { .name
= "tx", .irq
= 59 },
1081 { .name
= "rx", .irq
= 60 },
1085 static struct omap_hwmod omap3xxx_mcbsp1_hwmod
= {
1087 .class = &omap3xxx_mcbsp_hwmod_class
,
1088 .mpu_irqs
= omap3xxx_mcbsp1_irqs
,
1089 .sdma_reqs
= omap2_mcbsp1_sdma_reqs
,
1090 .main_clk
= "mcbsp1_fck",
1094 .module_bit
= OMAP3430_EN_MCBSP1_SHIFT
,
1095 .module_offs
= CORE_MOD
,
1097 .idlest_idle_bit
= OMAP3430_ST_MCBSP1_SHIFT
,
1103 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs
[] = {
1104 { .name
= "common", .irq
= 17 },
1105 { .name
= "tx", .irq
= 62 },
1106 { .name
= "rx", .irq
= 63 },
1110 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr
= {
1111 .sidetone
= "mcbsp2_sidetone",
1114 static struct omap_hwmod omap3xxx_mcbsp2_hwmod
= {
1116 .class = &omap3xxx_mcbsp_hwmod_class
,
1117 .mpu_irqs
= omap3xxx_mcbsp2_irqs
,
1118 .sdma_reqs
= omap2_mcbsp2_sdma_reqs
,
1119 .main_clk
= "mcbsp2_fck",
1123 .module_bit
= OMAP3430_EN_MCBSP2_SHIFT
,
1124 .module_offs
= OMAP3430_PER_MOD
,
1126 .idlest_idle_bit
= OMAP3430_ST_MCBSP2_SHIFT
,
1129 .dev_attr
= &omap34xx_mcbsp2_dev_attr
,
1133 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs
[] = {
1134 { .name
= "common", .irq
= 22 },
1135 { .name
= "tx", .irq
= 89 },
1136 { .name
= "rx", .irq
= 90 },
1140 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr
= {
1141 .sidetone
= "mcbsp3_sidetone",
1144 static struct omap_hwmod omap3xxx_mcbsp3_hwmod
= {
1146 .class = &omap3xxx_mcbsp_hwmod_class
,
1147 .mpu_irqs
= omap3xxx_mcbsp3_irqs
,
1148 .sdma_reqs
= omap2_mcbsp3_sdma_reqs
,
1149 .main_clk
= "mcbsp3_fck",
1153 .module_bit
= OMAP3430_EN_MCBSP3_SHIFT
,
1154 .module_offs
= OMAP3430_PER_MOD
,
1156 .idlest_idle_bit
= OMAP3430_ST_MCBSP3_SHIFT
,
1159 .dev_attr
= &omap34xx_mcbsp3_dev_attr
,
1163 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs
[] = {
1164 { .name
= "common", .irq
= 23 },
1165 { .name
= "tx", .irq
= 54 },
1166 { .name
= "rx", .irq
= 55 },
1170 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs
[] = {
1171 { .name
= "rx", .dma_req
= 20 },
1172 { .name
= "tx", .dma_req
= 19 },
1176 static struct omap_hwmod omap3xxx_mcbsp4_hwmod
= {
1178 .class = &omap3xxx_mcbsp_hwmod_class
,
1179 .mpu_irqs
= omap3xxx_mcbsp4_irqs
,
1180 .sdma_reqs
= omap3xxx_mcbsp4_sdma_chs
,
1181 .main_clk
= "mcbsp4_fck",
1185 .module_bit
= OMAP3430_EN_MCBSP4_SHIFT
,
1186 .module_offs
= OMAP3430_PER_MOD
,
1188 .idlest_idle_bit
= OMAP3430_ST_MCBSP4_SHIFT
,
1194 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs
[] = {
1195 { .name
= "common", .irq
= 27 },
1196 { .name
= "tx", .irq
= 81 },
1197 { .name
= "rx", .irq
= 82 },
1201 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs
[] = {
1202 { .name
= "rx", .dma_req
= 22 },
1203 { .name
= "tx", .dma_req
= 21 },
1207 static struct omap_hwmod omap3xxx_mcbsp5_hwmod
= {
1209 .class = &omap3xxx_mcbsp_hwmod_class
,
1210 .mpu_irqs
= omap3xxx_mcbsp5_irqs
,
1211 .sdma_reqs
= omap3xxx_mcbsp5_sdma_chs
,
1212 .main_clk
= "mcbsp5_fck",
1216 .module_bit
= OMAP3430_EN_MCBSP5_SHIFT
,
1217 .module_offs
= CORE_MOD
,
1219 .idlest_idle_bit
= OMAP3430_ST_MCBSP5_SHIFT
,
1224 /* 'mcbsp sidetone' class */
1225 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc
= {
1226 .sysc_offs
= 0x0010,
1227 .sysc_flags
= SYSC_HAS_AUTOIDLE
,
1228 .sysc_fields
= &omap_hwmod_sysc_type1
,
1231 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class
= {
1232 .name
= "mcbsp_sidetone",
1233 .sysc
= &omap3xxx_mcbsp_sidetone_sysc
,
1236 /* mcbsp2_sidetone */
1237 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs
[] = {
1238 { .name
= "irq", .irq
= 4 },
1242 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod
= {
1243 .name
= "mcbsp2_sidetone",
1244 .class = &omap3xxx_mcbsp_sidetone_hwmod_class
,
1245 .mpu_irqs
= omap3xxx_mcbsp2_sidetone_irqs
,
1246 .main_clk
= "mcbsp2_fck",
1250 .module_bit
= OMAP3430_EN_MCBSP2_SHIFT
,
1251 .module_offs
= OMAP3430_PER_MOD
,
1253 .idlest_idle_bit
= OMAP3430_ST_MCBSP2_SHIFT
,
1258 /* mcbsp3_sidetone */
1259 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs
[] = {
1260 { .name
= "irq", .irq
= 5 },
1264 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod
= {
1265 .name
= "mcbsp3_sidetone",
1266 .class = &omap3xxx_mcbsp_sidetone_hwmod_class
,
1267 .mpu_irqs
= omap3xxx_mcbsp3_sidetone_irqs
,
1268 .main_clk
= "mcbsp3_fck",
1272 .module_bit
= OMAP3430_EN_MCBSP3_SHIFT
,
1273 .module_offs
= OMAP3430_PER_MOD
,
1275 .idlest_idle_bit
= OMAP3430_ST_MCBSP3_SHIFT
,
1281 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields
= {
1285 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc
= {
1287 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_NO_CACHE
),
1288 .clockact
= CLOCKACT_TEST_ICLK
,
1289 .sysc_fields
= &omap34xx_sr_sysc_fields
,
1292 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class
= {
1293 .name
= "smartreflex",
1294 .sysc
= &omap34xx_sr_sysc
,
1298 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields
= {
1303 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc
= {
1305 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1306 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_ENAWAKEUP
|
1308 .sysc_fields
= &omap36xx_sr_sysc_fields
,
1311 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class
= {
1312 .name
= "smartreflex",
1313 .sysc
= &omap36xx_sr_sysc
,
1318 static struct omap_smartreflex_dev_attr sr1_dev_attr
= {
1319 .sensor_voltdm_name
= "mpu_iva",
1322 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs
[] = {
1327 static struct omap_hwmod omap34xx_sr1_hwmod
= {
1329 .class = &omap34xx_smartreflex_hwmod_class
,
1330 .main_clk
= "sr1_fck",
1334 .module_bit
= OMAP3430_EN_SR1_SHIFT
,
1335 .module_offs
= WKUP_MOD
,
1337 .idlest_idle_bit
= OMAP3430_EN_SR1_SHIFT
,
1340 .dev_attr
= &sr1_dev_attr
,
1341 .mpu_irqs
= omap3_smartreflex_mpu_irqs
,
1342 .flags
= HWMOD_SET_DEFAULT_CLOCKACT
,
1345 static struct omap_hwmod omap36xx_sr1_hwmod
= {
1347 .class = &omap36xx_smartreflex_hwmod_class
,
1348 .main_clk
= "sr1_fck",
1352 .module_bit
= OMAP3430_EN_SR1_SHIFT
,
1353 .module_offs
= WKUP_MOD
,
1355 .idlest_idle_bit
= OMAP3430_EN_SR1_SHIFT
,
1358 .dev_attr
= &sr1_dev_attr
,
1359 .mpu_irqs
= omap3_smartreflex_mpu_irqs
,
1363 static struct omap_smartreflex_dev_attr sr2_dev_attr
= {
1364 .sensor_voltdm_name
= "core",
1367 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs
[] = {
1372 static struct omap_hwmod omap34xx_sr2_hwmod
= {
1374 .class = &omap34xx_smartreflex_hwmod_class
,
1375 .main_clk
= "sr2_fck",
1379 .module_bit
= OMAP3430_EN_SR2_SHIFT
,
1380 .module_offs
= WKUP_MOD
,
1382 .idlest_idle_bit
= OMAP3430_EN_SR2_SHIFT
,
1385 .dev_attr
= &sr2_dev_attr
,
1386 .mpu_irqs
= omap3_smartreflex_core_irqs
,
1387 .flags
= HWMOD_SET_DEFAULT_CLOCKACT
,
1390 static struct omap_hwmod omap36xx_sr2_hwmod
= {
1392 .class = &omap36xx_smartreflex_hwmod_class
,
1393 .main_clk
= "sr2_fck",
1397 .module_bit
= OMAP3430_EN_SR2_SHIFT
,
1398 .module_offs
= WKUP_MOD
,
1400 .idlest_idle_bit
= OMAP3430_EN_SR2_SHIFT
,
1403 .dev_attr
= &sr2_dev_attr
,
1404 .mpu_irqs
= omap3_smartreflex_core_irqs
,
1409 * mailbox module allowing communication between the on-chip processors
1410 * using a queued mailbox-interrupt mechanism.
1413 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc
= {
1417 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
1418 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
),
1419 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1420 .sysc_fields
= &omap_hwmod_sysc_type1
,
1423 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class
= {
1425 .sysc
= &omap3xxx_mailbox_sysc
,
1428 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs
[] = {
1433 static struct omap_hwmod omap3xxx_mailbox_hwmod
= {
1435 .class = &omap3xxx_mailbox_hwmod_class
,
1436 .mpu_irqs
= omap3xxx_mailbox_irqs
,
1437 .main_clk
= "mailboxes_ick",
1441 .module_bit
= OMAP3430_EN_MAILBOXES_SHIFT
,
1442 .module_offs
= CORE_MOD
,
1444 .idlest_idle_bit
= OMAP3430_ST_MAILBOXES_SHIFT
,
1451 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1455 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc
= {
1457 .sysc_offs
= 0x0010,
1458 .syss_offs
= 0x0014,
1459 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
1460 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
1461 SYSC_HAS_AUTOIDLE
| SYSS_HAS_RESET_STATUS
),
1462 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1463 .sysc_fields
= &omap_hwmod_sysc_type1
,
1466 static struct omap_hwmod_class omap34xx_mcspi_class
= {
1468 .sysc
= &omap34xx_mcspi_sysc
,
1469 .rev
= OMAP3_MCSPI_REV
,
1473 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr
= {
1474 .num_chipselect
= 4,
1477 static struct omap_hwmod omap34xx_mcspi1
= {
1479 .mpu_irqs
= omap2_mcspi1_mpu_irqs
,
1480 .sdma_reqs
= omap2_mcspi1_sdma_reqs
,
1481 .main_clk
= "mcspi1_fck",
1484 .module_offs
= CORE_MOD
,
1486 .module_bit
= OMAP3430_EN_MCSPI1_SHIFT
,
1488 .idlest_idle_bit
= OMAP3430_ST_MCSPI1_SHIFT
,
1491 .class = &omap34xx_mcspi_class
,
1492 .dev_attr
= &omap_mcspi1_dev_attr
,
1496 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr
= {
1497 .num_chipselect
= 2,
1500 static struct omap_hwmod omap34xx_mcspi2
= {
1502 .mpu_irqs
= omap2_mcspi2_mpu_irqs
,
1503 .sdma_reqs
= omap2_mcspi2_sdma_reqs
,
1504 .main_clk
= "mcspi2_fck",
1507 .module_offs
= CORE_MOD
,
1509 .module_bit
= OMAP3430_EN_MCSPI2_SHIFT
,
1511 .idlest_idle_bit
= OMAP3430_ST_MCSPI2_SHIFT
,
1514 .class = &omap34xx_mcspi_class
,
1515 .dev_attr
= &omap_mcspi2_dev_attr
,
1519 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs
[] = {
1520 { .name
= "irq", .irq
= 91 }, /* 91 */
1524 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs
[] = {
1525 { .name
= "tx0", .dma_req
= 15 },
1526 { .name
= "rx0", .dma_req
= 16 },
1527 { .name
= "tx1", .dma_req
= 23 },
1528 { .name
= "rx1", .dma_req
= 24 },
1532 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr
= {
1533 .num_chipselect
= 2,
1536 static struct omap_hwmod omap34xx_mcspi3
= {
1538 .mpu_irqs
= omap34xx_mcspi3_mpu_irqs
,
1539 .sdma_reqs
= omap34xx_mcspi3_sdma_reqs
,
1540 .main_clk
= "mcspi3_fck",
1543 .module_offs
= CORE_MOD
,
1545 .module_bit
= OMAP3430_EN_MCSPI3_SHIFT
,
1547 .idlest_idle_bit
= OMAP3430_ST_MCSPI3_SHIFT
,
1550 .class = &omap34xx_mcspi_class
,
1551 .dev_attr
= &omap_mcspi3_dev_attr
,
1555 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs
[] = {
1556 { .name
= "irq", .irq
= INT_34XX_SPI4_IRQ
}, /* 48 */
1560 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs
[] = {
1561 { .name
= "tx0", .dma_req
= 70 }, /* DMA_SPI4_TX0 */
1562 { .name
= "rx0", .dma_req
= 71 }, /* DMA_SPI4_RX0 */
1566 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr
= {
1567 .num_chipselect
= 1,
1570 static struct omap_hwmod omap34xx_mcspi4
= {
1572 .mpu_irqs
= omap34xx_mcspi4_mpu_irqs
,
1573 .sdma_reqs
= omap34xx_mcspi4_sdma_reqs
,
1574 .main_clk
= "mcspi4_fck",
1577 .module_offs
= CORE_MOD
,
1579 .module_bit
= OMAP3430_EN_MCSPI4_SHIFT
,
1581 .idlest_idle_bit
= OMAP3430_ST_MCSPI4_SHIFT
,
1584 .class = &omap34xx_mcspi_class
,
1585 .dev_attr
= &omap_mcspi4_dev_attr
,
1589 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc
= {
1591 .sysc_offs
= 0x0404,
1592 .syss_offs
= 0x0408,
1593 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_MIDLEMODE
|
1594 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
1596 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1597 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
1598 .sysc_fields
= &omap_hwmod_sysc_type1
,
1601 static struct omap_hwmod_class usbotg_class
= {
1603 .sysc
= &omap3xxx_usbhsotg_sysc
,
1607 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs
[] = {
1609 { .name
= "mc", .irq
= 92 },
1610 { .name
= "dma", .irq
= 93 },
1614 static struct omap_hwmod omap3xxx_usbhsotg_hwmod
= {
1615 .name
= "usb_otg_hs",
1616 .mpu_irqs
= omap3xxx_usbhsotg_mpu_irqs
,
1617 .main_clk
= "hsotgusb_ick",
1621 .module_bit
= OMAP3430_EN_HSOTGUSB_SHIFT
,
1622 .module_offs
= CORE_MOD
,
1624 .idlest_idle_bit
= OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT
,
1625 .idlest_stdby_bit
= OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
1628 .class = &usbotg_class
,
1631 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
1632 * broken when autoidle is enabled
1633 * workaround is to disable the autoidle bit at module level.
1635 .flags
= HWMOD_NO_OCP_AUTOIDLE
| HWMOD_SWSUP_SIDLE
1636 | HWMOD_SWSUP_MSTANDBY
,
1640 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs
[] = {
1642 { .name
= "mc", .irq
= 71 },
1646 static struct omap_hwmod_class am35xx_usbotg_class
= {
1647 .name
= "am35xx_usbotg",
1651 static struct omap_hwmod am35xx_usbhsotg_hwmod
= {
1652 .name
= "am35x_otg_hs",
1653 .mpu_irqs
= am35xx_usbhsotg_mpu_irqs
,
1659 .class = &am35xx_usbotg_class
,
1662 /* MMC/SD/SDIO common */
1663 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc
= {
1667 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
1668 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
1669 SYSC_HAS_AUTOIDLE
| SYSS_HAS_RESET_STATUS
),
1670 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1671 .sysc_fields
= &omap_hwmod_sysc_type1
,
1674 static struct omap_hwmod_class omap34xx_mmc_class
= {
1676 .sysc
= &omap34xx_mmc_sysc
,
1681 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs
[] = {
1686 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs
[] = {
1687 { .name
= "tx", .dma_req
= 61, },
1688 { .name
= "rx", .dma_req
= 62, },
1692 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks
[] = {
1693 { .role
= "dbck", .clk
= "omap_32k_fck", },
1696 static struct omap_mmc_dev_attr mmc1_dev_attr
= {
1697 .flags
= OMAP_HSMMC_SUPPORTS_DUAL_VOLT
,
1700 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1701 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr
= {
1702 .flags
= (OMAP_HSMMC_SUPPORTS_DUAL_VOLT
|
1703 OMAP_HSMMC_BROKEN_MULTIBLOCK_READ
),
1706 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod
= {
1708 .mpu_irqs
= omap34xx_mmc1_mpu_irqs
,
1709 .sdma_reqs
= omap34xx_mmc1_sdma_reqs
,
1710 .opt_clks
= omap34xx_mmc1_opt_clks
,
1711 .opt_clks_cnt
= ARRAY_SIZE(omap34xx_mmc1_opt_clks
),
1712 .main_clk
= "mmchs1_fck",
1715 .module_offs
= CORE_MOD
,
1717 .module_bit
= OMAP3430_EN_MMC1_SHIFT
,
1719 .idlest_idle_bit
= OMAP3430_ST_MMC1_SHIFT
,
1722 .dev_attr
= &mmc1_pre_es3_dev_attr
,
1723 .class = &omap34xx_mmc_class
,
1726 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod
= {
1728 .mpu_irqs
= omap34xx_mmc1_mpu_irqs
,
1729 .sdma_reqs
= omap34xx_mmc1_sdma_reqs
,
1730 .opt_clks
= omap34xx_mmc1_opt_clks
,
1731 .opt_clks_cnt
= ARRAY_SIZE(omap34xx_mmc1_opt_clks
),
1732 .main_clk
= "mmchs1_fck",
1735 .module_offs
= CORE_MOD
,
1737 .module_bit
= OMAP3430_EN_MMC1_SHIFT
,
1739 .idlest_idle_bit
= OMAP3430_ST_MMC1_SHIFT
,
1742 .dev_attr
= &mmc1_dev_attr
,
1743 .class = &omap34xx_mmc_class
,
1748 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs
[] = {
1749 { .irq
= INT_24XX_MMC2_IRQ
, },
1753 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs
[] = {
1754 { .name
= "tx", .dma_req
= 47, },
1755 { .name
= "rx", .dma_req
= 48, },
1759 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks
[] = {
1760 { .role
= "dbck", .clk
= "omap_32k_fck", },
1763 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1764 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr
= {
1765 .flags
= OMAP_HSMMC_BROKEN_MULTIBLOCK_READ
,
1768 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod
= {
1770 .mpu_irqs
= omap34xx_mmc2_mpu_irqs
,
1771 .sdma_reqs
= omap34xx_mmc2_sdma_reqs
,
1772 .opt_clks
= omap34xx_mmc2_opt_clks
,
1773 .opt_clks_cnt
= ARRAY_SIZE(omap34xx_mmc2_opt_clks
),
1774 .main_clk
= "mmchs2_fck",
1777 .module_offs
= CORE_MOD
,
1779 .module_bit
= OMAP3430_EN_MMC2_SHIFT
,
1781 .idlest_idle_bit
= OMAP3430_ST_MMC2_SHIFT
,
1784 .dev_attr
= &mmc2_pre_es3_dev_attr
,
1785 .class = &omap34xx_mmc_class
,
1788 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod
= {
1790 .mpu_irqs
= omap34xx_mmc2_mpu_irqs
,
1791 .sdma_reqs
= omap34xx_mmc2_sdma_reqs
,
1792 .opt_clks
= omap34xx_mmc2_opt_clks
,
1793 .opt_clks_cnt
= ARRAY_SIZE(omap34xx_mmc2_opt_clks
),
1794 .main_clk
= "mmchs2_fck",
1797 .module_offs
= CORE_MOD
,
1799 .module_bit
= OMAP3430_EN_MMC2_SHIFT
,
1801 .idlest_idle_bit
= OMAP3430_ST_MMC2_SHIFT
,
1804 .class = &omap34xx_mmc_class
,
1809 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs
[] = {
1814 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs
[] = {
1815 { .name
= "tx", .dma_req
= 77, },
1816 { .name
= "rx", .dma_req
= 78, },
1820 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks
[] = {
1821 { .role
= "dbck", .clk
= "omap_32k_fck", },
1824 static struct omap_hwmod omap3xxx_mmc3_hwmod
= {
1826 .mpu_irqs
= omap34xx_mmc3_mpu_irqs
,
1827 .sdma_reqs
= omap34xx_mmc3_sdma_reqs
,
1828 .opt_clks
= omap34xx_mmc3_opt_clks
,
1829 .opt_clks_cnt
= ARRAY_SIZE(omap34xx_mmc3_opt_clks
),
1830 .main_clk
= "mmchs3_fck",
1834 .module_bit
= OMAP3430_EN_MMC3_SHIFT
,
1836 .idlest_idle_bit
= OMAP3430_ST_MMC3_SHIFT
,
1839 .class = &omap34xx_mmc_class
,
1843 * 'usb_host_hs' class
1844 * high-speed multi-port usb host controller
1847 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc
= {
1849 .sysc_offs
= 0x0010,
1850 .syss_offs
= 0x0014,
1851 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_CLOCKACTIVITY
|
1852 SYSC_HAS_SIDLEMODE
| SYSC_HAS_ENAWAKEUP
|
1853 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
),
1854 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1855 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
1856 .sysc_fields
= &omap_hwmod_sysc_type1
,
1859 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class
= {
1860 .name
= "usb_host_hs",
1861 .sysc
= &omap3xxx_usb_host_hs_sysc
,
1864 static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks
[] = {
1865 { .role
= "ehci_logic_fck", .clk
= "usbhost_120m_fck", },
1868 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs
[] = {
1869 { .name
= "ohci-irq", .irq
= 76 },
1870 { .name
= "ehci-irq", .irq
= 77 },
1874 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod
= {
1875 .name
= "usb_host_hs",
1876 .class = &omap3xxx_usb_host_hs_hwmod_class
,
1877 .clkdm_name
= "l3_init_clkdm",
1878 .mpu_irqs
= omap3xxx_usb_host_hs_irqs
,
1879 .main_clk
= "usbhost_48m_fck",
1882 .module_offs
= OMAP3430ES2_USBHOST_MOD
,
1884 .module_bit
= OMAP3430ES2_EN_USBHOST1_SHIFT
,
1886 .idlest_idle_bit
= OMAP3430ES2_ST_USBHOST_IDLE_SHIFT
,
1887 .idlest_stdby_bit
= OMAP3430ES2_ST_USBHOST_STDBY_SHIFT
,
1890 .opt_clks
= omap3xxx_usb_host_hs_opt_clks
,
1891 .opt_clks_cnt
= ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks
),
1894 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1898 * In the following configuration :
1899 * - USBHOST module is set to smart-idle mode
1900 * - PRCM asserts idle_req to the USBHOST module ( This typically
1901 * happens when the system is going to a low power mode : all ports
1902 * have been suspended, the master part of the USBHOST module has
1903 * entered the standby state, and SW has cut the functional clocks)
1904 * - an USBHOST interrupt occurs before the module is able to answer
1905 * idle_ack, typically a remote wakeup IRQ.
1906 * Then the USB HOST module will enter a deadlock situation where it
1907 * is no more accessible nor functional.
1910 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1914 * Errata: USB host EHCI may stall when entering smart-standby mode
1918 * When the USBHOST module is set to smart-standby mode, and when it is
1919 * ready to enter the standby state (i.e. all ports are suspended and
1920 * all attached devices are in suspend mode), then it can wrongly assert
1921 * the Mstandby signal too early while there are still some residual OCP
1922 * transactions ongoing. If this condition occurs, the internal state
1923 * machine may go to an undefined state and the USB link may be stuck
1924 * upon the next resume.
1927 * Don't use smart standby; use only force standby,
1928 * hence HWMOD_SWSUP_MSTANDBY
1932 * During system boot; If the hwmod framework resets the module
1933 * the module will have smart idle settings; which can lead to deadlock
1934 * (above Errata Id:i660); so, dont reset the module during boot;
1935 * Use HWMOD_INIT_NO_RESET.
1938 .flags
= HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
|
1939 HWMOD_INIT_NO_RESET
,
1943 * 'usb_tll_hs' class
1944 * usb_tll_hs module is the adapter on the usb_host_hs ports
1946 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc
= {
1948 .sysc_offs
= 0x0010,
1949 .syss_offs
= 0x0014,
1950 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
1951 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
1953 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1954 .sysc_fields
= &omap_hwmod_sysc_type1
,
1957 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class
= {
1958 .name
= "usb_tll_hs",
1959 .sysc
= &omap3xxx_usb_tll_hs_sysc
,
1962 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs
[] = {
1963 { .name
= "tll-irq", .irq
= 78 },
1967 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod
= {
1968 .name
= "usb_tll_hs",
1969 .class = &omap3xxx_usb_tll_hs_hwmod_class
,
1970 .clkdm_name
= "l3_init_clkdm",
1971 .mpu_irqs
= omap3xxx_usb_tll_hs_irqs
,
1972 .main_clk
= "usbtll_fck",
1975 .module_offs
= CORE_MOD
,
1977 .module_bit
= OMAP3430ES2_EN_USBTLL_SHIFT
,
1979 .idlest_idle_bit
= OMAP3430ES2_ST_USBTLL_SHIFT
,
1984 static struct omap_hwmod omap3xxx_hdq1w_hwmod
= {
1986 .mpu_irqs
= omap2_hdq1w_mpu_irqs
,
1987 .main_clk
= "hdq_fck",
1990 .module_offs
= CORE_MOD
,
1992 .module_bit
= OMAP3430_EN_HDQ_SHIFT
,
1994 .idlest_idle_bit
= OMAP3430_ST_HDQ_SHIFT
,
1997 .class = &omap2_hdq1w_class
,
2001 * '32K sync counter' class
2002 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
2004 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc
= {
2006 .sysc_offs
= 0x0004,
2007 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
2008 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
),
2009 .sysc_fields
= &omap_hwmod_sysc_type1
,
2012 static struct omap_hwmod_class omap3xxx_counter_hwmod_class
= {
2014 .sysc
= &omap3xxx_counter_sysc
,
2017 static struct omap_hwmod omap3xxx_counter_32k_hwmod
= {
2018 .name
= "counter_32k",
2019 .class = &omap3xxx_counter_hwmod_class
,
2020 .clkdm_name
= "wkup_clkdm",
2021 .flags
= HWMOD_SWSUP_SIDLE
,
2022 .main_clk
= "wkup_32k_fck",
2025 .module_offs
= WKUP_MOD
,
2027 .module_bit
= OMAP3430_ST_32KSYNC_SHIFT
,
2029 .idlest_idle_bit
= OMAP3430_ST_32KSYNC_SHIFT
,
2038 /* L3 -> L4_CORE interface */
2039 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core
= {
2040 .master
= &omap3xxx_l3_main_hwmod
,
2041 .slave
= &omap3xxx_l4_core_hwmod
,
2042 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2045 /* L3 -> L4_PER interface */
2046 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per
= {
2047 .master
= &omap3xxx_l3_main_hwmod
,
2048 .slave
= &omap3xxx_l4_per_hwmod
,
2049 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2052 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs
[] = {
2054 .pa_start
= 0x68000000,
2055 .pa_end
= 0x6800ffff,
2056 .flags
= ADDR_TYPE_RT
,
2061 /* MPU -> L3 interface */
2062 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main
= {
2063 .master
= &omap3xxx_mpu_hwmod
,
2064 .slave
= &omap3xxx_l3_main_hwmod
,
2065 .addr
= omap3xxx_l3_main_addrs
,
2066 .user
= OCP_USER_MPU
,
2070 static struct omap_hwmod_ocp_if omap3430es1_dss__l3
= {
2071 .master
= &omap3430es1_dss_core_hwmod
,
2072 .slave
= &omap3xxx_l3_main_hwmod
,
2073 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2076 static struct omap_hwmod_ocp_if omap3xxx_dss__l3
= {
2077 .master
= &omap3xxx_dss_core_hwmod
,
2078 .slave
= &omap3xxx_l3_main_hwmod
,
2081 .l3_perm_bit
= OMAP3_L3_CORE_FW_INIT_ID_DSS
,
2082 .flags
= OMAP_FIREWALL_L3
,
2085 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2088 /* l3_core -> usbhsotg interface */
2089 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3
= {
2090 .master
= &omap3xxx_usbhsotg_hwmod
,
2091 .slave
= &omap3xxx_l3_main_hwmod
,
2092 .clk
= "core_l3_ick",
2093 .user
= OCP_USER_MPU
,
2096 /* l3_core -> am35xx_usbhsotg interface */
2097 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3
= {
2098 .master
= &am35xx_usbhsotg_hwmod
,
2099 .slave
= &omap3xxx_l3_main_hwmod
,
2100 .clk
= "core_l3_ick",
2101 .user
= OCP_USER_MPU
,
2103 /* L4_CORE -> L4_WKUP interface */
2104 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup
= {
2105 .master
= &omap3xxx_l4_core_hwmod
,
2106 .slave
= &omap3xxx_l4_wkup_hwmod
,
2107 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2110 /* L4 CORE -> MMC1 interface */
2111 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1
= {
2112 .master
= &omap3xxx_l4_core_hwmod
,
2113 .slave
= &omap3xxx_pre_es3_mmc1_hwmod
,
2114 .clk
= "mmchs1_ick",
2115 .addr
= omap2430_mmc1_addr_space
,
2116 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2117 .flags
= OMAP_FIREWALL_L4
2120 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1
= {
2121 .master
= &omap3xxx_l4_core_hwmod
,
2122 .slave
= &omap3xxx_es3plus_mmc1_hwmod
,
2123 .clk
= "mmchs1_ick",
2124 .addr
= omap2430_mmc1_addr_space
,
2125 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2126 .flags
= OMAP_FIREWALL_L4
2129 /* L4 CORE -> MMC2 interface */
2130 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2
= {
2131 .master
= &omap3xxx_l4_core_hwmod
,
2132 .slave
= &omap3xxx_pre_es3_mmc2_hwmod
,
2133 .clk
= "mmchs2_ick",
2134 .addr
= omap2430_mmc2_addr_space
,
2135 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2136 .flags
= OMAP_FIREWALL_L4
2139 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2
= {
2140 .master
= &omap3xxx_l4_core_hwmod
,
2141 .slave
= &omap3xxx_es3plus_mmc2_hwmod
,
2142 .clk
= "mmchs2_ick",
2143 .addr
= omap2430_mmc2_addr_space
,
2144 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2145 .flags
= OMAP_FIREWALL_L4
2148 /* L4 CORE -> MMC3 interface */
2149 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space
[] = {
2151 .pa_start
= 0x480ad000,
2152 .pa_end
= 0x480ad1ff,
2153 .flags
= ADDR_TYPE_RT
,
2158 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3
= {
2159 .master
= &omap3xxx_l4_core_hwmod
,
2160 .slave
= &omap3xxx_mmc3_hwmod
,
2161 .clk
= "mmchs3_ick",
2162 .addr
= omap3xxx_mmc3_addr_space
,
2163 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2164 .flags
= OMAP_FIREWALL_L4
2167 /* L4 CORE -> UART1 interface */
2168 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space
[] = {
2170 .pa_start
= OMAP3_UART1_BASE
,
2171 .pa_end
= OMAP3_UART1_BASE
+ SZ_8K
- 1,
2172 .flags
= ADDR_MAP_ON_INIT
| ADDR_TYPE_RT
,
2177 static struct omap_hwmod_ocp_if omap3_l4_core__uart1
= {
2178 .master
= &omap3xxx_l4_core_hwmod
,
2179 .slave
= &omap3xxx_uart1_hwmod
,
2181 .addr
= omap3xxx_uart1_addr_space
,
2182 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2185 /* L4 CORE -> UART2 interface */
2186 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space
[] = {
2188 .pa_start
= OMAP3_UART2_BASE
,
2189 .pa_end
= OMAP3_UART2_BASE
+ SZ_1K
- 1,
2190 .flags
= ADDR_MAP_ON_INIT
| ADDR_TYPE_RT
,
2195 static struct omap_hwmod_ocp_if omap3_l4_core__uart2
= {
2196 .master
= &omap3xxx_l4_core_hwmod
,
2197 .slave
= &omap3xxx_uart2_hwmod
,
2199 .addr
= omap3xxx_uart2_addr_space
,
2200 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2203 /* L4 PER -> UART3 interface */
2204 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space
[] = {
2206 .pa_start
= OMAP3_UART3_BASE
,
2207 .pa_end
= OMAP3_UART3_BASE
+ SZ_1K
- 1,
2208 .flags
= ADDR_MAP_ON_INIT
| ADDR_TYPE_RT
,
2213 static struct omap_hwmod_ocp_if omap3_l4_per__uart3
= {
2214 .master
= &omap3xxx_l4_per_hwmod
,
2215 .slave
= &omap3xxx_uart3_hwmod
,
2217 .addr
= omap3xxx_uart3_addr_space
,
2218 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2221 /* L4 PER -> UART4 interface */
2222 static struct omap_hwmod_addr_space omap36xx_uart4_addr_space
[] = {
2224 .pa_start
= OMAP3_UART4_BASE
,
2225 .pa_end
= OMAP3_UART4_BASE
+ SZ_1K
- 1,
2226 .flags
= ADDR_MAP_ON_INIT
| ADDR_TYPE_RT
,
2231 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4
= {
2232 .master
= &omap3xxx_l4_per_hwmod
,
2233 .slave
= &omap36xx_uart4_hwmod
,
2235 .addr
= omap36xx_uart4_addr_space
,
2236 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2239 /* AM35xx: L4 CORE -> UART4 interface */
2240 static struct omap_hwmod_addr_space am35xx_uart4_addr_space
[] = {
2242 .pa_start
= OMAP3_UART4_AM35XX_BASE
,
2243 .pa_end
= OMAP3_UART4_AM35XX_BASE
+ SZ_1K
- 1,
2244 .flags
= ADDR_MAP_ON_INIT
| ADDR_TYPE_RT
,
2248 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4
= {
2249 .master
= &omap3xxx_l4_core_hwmod
,
2250 .slave
= &am35xx_uart4_hwmod
,
2252 .addr
= am35xx_uart4_addr_space
,
2253 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2256 /* L4 CORE -> I2C1 interface */
2257 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1
= {
2258 .master
= &omap3xxx_l4_core_hwmod
,
2259 .slave
= &omap3xxx_i2c1_hwmod
,
2261 .addr
= omap2_i2c1_addr_space
,
2264 .l4_fw_region
= OMAP3_L4_CORE_FW_I2C1_REGION
,
2266 .flags
= OMAP_FIREWALL_L4
,
2269 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2272 /* L4 CORE -> I2C2 interface */
2273 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2
= {
2274 .master
= &omap3xxx_l4_core_hwmod
,
2275 .slave
= &omap3xxx_i2c2_hwmod
,
2277 .addr
= omap2_i2c2_addr_space
,
2280 .l4_fw_region
= OMAP3_L4_CORE_FW_I2C2_REGION
,
2282 .flags
= OMAP_FIREWALL_L4
,
2285 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2288 /* L4 CORE -> I2C3 interface */
2289 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space
[] = {
2291 .pa_start
= 0x48060000,
2292 .pa_end
= 0x48060000 + SZ_128
- 1,
2293 .flags
= ADDR_TYPE_RT
,
2298 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3
= {
2299 .master
= &omap3xxx_l4_core_hwmod
,
2300 .slave
= &omap3xxx_i2c3_hwmod
,
2302 .addr
= omap3xxx_i2c3_addr_space
,
2305 .l4_fw_region
= OMAP3_L4_CORE_FW_I2C3_REGION
,
2307 .flags
= OMAP_FIREWALL_L4
,
2310 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2313 /* L4 CORE -> SR1 interface */
2314 static struct omap_hwmod_addr_space omap3_sr1_addr_space
[] = {
2316 .pa_start
= OMAP34XX_SR1_BASE
,
2317 .pa_end
= OMAP34XX_SR1_BASE
+ SZ_1K
- 1,
2318 .flags
= ADDR_TYPE_RT
,
2323 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1
= {
2324 .master
= &omap3xxx_l4_core_hwmod
,
2325 .slave
= &omap34xx_sr1_hwmod
,
2327 .addr
= omap3_sr1_addr_space
,
2328 .user
= OCP_USER_MPU
,
2331 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1
= {
2332 .master
= &omap3xxx_l4_core_hwmod
,
2333 .slave
= &omap36xx_sr1_hwmod
,
2335 .addr
= omap3_sr1_addr_space
,
2336 .user
= OCP_USER_MPU
,
2339 /* L4 CORE -> SR1 interface */
2340 static struct omap_hwmod_addr_space omap3_sr2_addr_space
[] = {
2342 .pa_start
= OMAP34XX_SR2_BASE
,
2343 .pa_end
= OMAP34XX_SR2_BASE
+ SZ_1K
- 1,
2344 .flags
= ADDR_TYPE_RT
,
2349 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2
= {
2350 .master
= &omap3xxx_l4_core_hwmod
,
2351 .slave
= &omap34xx_sr2_hwmod
,
2353 .addr
= omap3_sr2_addr_space
,
2354 .user
= OCP_USER_MPU
,
2357 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2
= {
2358 .master
= &omap3xxx_l4_core_hwmod
,
2359 .slave
= &omap36xx_sr2_hwmod
,
2361 .addr
= omap3_sr2_addr_space
,
2362 .user
= OCP_USER_MPU
,
2365 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs
[] = {
2367 .pa_start
= OMAP34XX_HSUSB_OTG_BASE
,
2368 .pa_end
= OMAP34XX_HSUSB_OTG_BASE
+ SZ_4K
- 1,
2369 .flags
= ADDR_TYPE_RT
2374 /* l4_core -> usbhsotg */
2375 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg
= {
2376 .master
= &omap3xxx_l4_core_hwmod
,
2377 .slave
= &omap3xxx_usbhsotg_hwmod
,
2379 .addr
= omap3xxx_usbhsotg_addrs
,
2380 .user
= OCP_USER_MPU
,
2383 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs
[] = {
2385 .pa_start
= AM35XX_IPSS_USBOTGSS_BASE
,
2386 .pa_end
= AM35XX_IPSS_USBOTGSS_BASE
+ SZ_4K
- 1,
2387 .flags
= ADDR_TYPE_RT
2392 /* l4_core -> usbhsotg */
2393 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg
= {
2394 .master
= &omap3xxx_l4_core_hwmod
,
2395 .slave
= &am35xx_usbhsotg_hwmod
,
2397 .addr
= am35xx_usbhsotg_addrs
,
2398 .user
= OCP_USER_MPU
,
2401 /* L4_WKUP -> L4_SEC interface */
2402 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec
= {
2403 .master
= &omap3xxx_l4_wkup_hwmod
,
2404 .slave
= &omap3xxx_l4_sec_hwmod
,
2405 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2408 /* IVA2 <- L3 interface */
2409 static struct omap_hwmod_ocp_if omap3xxx_l3__iva
= {
2410 .master
= &omap3xxx_l3_main_hwmod
,
2411 .slave
= &omap3xxx_iva_hwmod
,
2412 .clk
= "core_l3_ick",
2413 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2416 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs
[] = {
2418 .pa_start
= 0x48318000,
2419 .pa_end
= 0x48318000 + SZ_1K
- 1,
2420 .flags
= ADDR_TYPE_RT
2425 /* l4_wkup -> timer1 */
2426 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1
= {
2427 .master
= &omap3xxx_l4_wkup_hwmod
,
2428 .slave
= &omap3xxx_timer1_hwmod
,
2430 .addr
= omap3xxx_timer1_addrs
,
2431 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2434 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs
[] = {
2436 .pa_start
= 0x49032000,
2437 .pa_end
= 0x49032000 + SZ_1K
- 1,
2438 .flags
= ADDR_TYPE_RT
2443 /* l4_per -> timer2 */
2444 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2
= {
2445 .master
= &omap3xxx_l4_per_hwmod
,
2446 .slave
= &omap3xxx_timer2_hwmod
,
2448 .addr
= omap3xxx_timer2_addrs
,
2449 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2452 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs
[] = {
2454 .pa_start
= 0x49034000,
2455 .pa_end
= 0x49034000 + SZ_1K
- 1,
2456 .flags
= ADDR_TYPE_RT
2461 /* l4_per -> timer3 */
2462 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3
= {
2463 .master
= &omap3xxx_l4_per_hwmod
,
2464 .slave
= &omap3xxx_timer3_hwmod
,
2466 .addr
= omap3xxx_timer3_addrs
,
2467 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2470 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs
[] = {
2472 .pa_start
= 0x49036000,
2473 .pa_end
= 0x49036000 + SZ_1K
- 1,
2474 .flags
= ADDR_TYPE_RT
2479 /* l4_per -> timer4 */
2480 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4
= {
2481 .master
= &omap3xxx_l4_per_hwmod
,
2482 .slave
= &omap3xxx_timer4_hwmod
,
2484 .addr
= omap3xxx_timer4_addrs
,
2485 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2488 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs
[] = {
2490 .pa_start
= 0x49038000,
2491 .pa_end
= 0x49038000 + SZ_1K
- 1,
2492 .flags
= ADDR_TYPE_RT
2497 /* l4_per -> timer5 */
2498 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5
= {
2499 .master
= &omap3xxx_l4_per_hwmod
,
2500 .slave
= &omap3xxx_timer5_hwmod
,
2502 .addr
= omap3xxx_timer5_addrs
,
2503 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2506 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs
[] = {
2508 .pa_start
= 0x4903A000,
2509 .pa_end
= 0x4903A000 + SZ_1K
- 1,
2510 .flags
= ADDR_TYPE_RT
2515 /* l4_per -> timer6 */
2516 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6
= {
2517 .master
= &omap3xxx_l4_per_hwmod
,
2518 .slave
= &omap3xxx_timer6_hwmod
,
2520 .addr
= omap3xxx_timer6_addrs
,
2521 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2524 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs
[] = {
2526 .pa_start
= 0x4903C000,
2527 .pa_end
= 0x4903C000 + SZ_1K
- 1,
2528 .flags
= ADDR_TYPE_RT
2533 /* l4_per -> timer7 */
2534 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7
= {
2535 .master
= &omap3xxx_l4_per_hwmod
,
2536 .slave
= &omap3xxx_timer7_hwmod
,
2538 .addr
= omap3xxx_timer7_addrs
,
2539 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2542 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs
[] = {
2544 .pa_start
= 0x4903E000,
2545 .pa_end
= 0x4903E000 + SZ_1K
- 1,
2546 .flags
= ADDR_TYPE_RT
2551 /* l4_per -> timer8 */
2552 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8
= {
2553 .master
= &omap3xxx_l4_per_hwmod
,
2554 .slave
= &omap3xxx_timer8_hwmod
,
2556 .addr
= omap3xxx_timer8_addrs
,
2557 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2560 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs
[] = {
2562 .pa_start
= 0x49040000,
2563 .pa_end
= 0x49040000 + SZ_1K
- 1,
2564 .flags
= ADDR_TYPE_RT
2569 /* l4_per -> timer9 */
2570 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9
= {
2571 .master
= &omap3xxx_l4_per_hwmod
,
2572 .slave
= &omap3xxx_timer9_hwmod
,
2574 .addr
= omap3xxx_timer9_addrs
,
2575 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2578 /* l4_core -> timer10 */
2579 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10
= {
2580 .master
= &omap3xxx_l4_core_hwmod
,
2581 .slave
= &omap3xxx_timer10_hwmod
,
2583 .addr
= omap2_timer10_addrs
,
2584 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2587 /* l4_core -> timer11 */
2588 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11
= {
2589 .master
= &omap3xxx_l4_core_hwmod
,
2590 .slave
= &omap3xxx_timer11_hwmod
,
2592 .addr
= omap2_timer11_addrs
,
2593 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2596 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs
[] = {
2598 .pa_start
= 0x48304000,
2599 .pa_end
= 0x48304000 + SZ_1K
- 1,
2600 .flags
= ADDR_TYPE_RT
2605 /* l4_core -> timer12 */
2606 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12
= {
2607 .master
= &omap3xxx_l4_sec_hwmod
,
2608 .slave
= &omap3xxx_timer12_hwmod
,
2610 .addr
= omap3xxx_timer12_addrs
,
2611 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2614 /* l4_wkup -> wd_timer2 */
2615 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs
[] = {
2617 .pa_start
= 0x48314000,
2618 .pa_end
= 0x4831407f,
2619 .flags
= ADDR_TYPE_RT
2624 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2
= {
2625 .master
= &omap3xxx_l4_wkup_hwmod
,
2626 .slave
= &omap3xxx_wd_timer2_hwmod
,
2628 .addr
= omap3xxx_wd_timer2_addrs
,
2629 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2632 /* l4_core -> dss */
2633 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss
= {
2634 .master
= &omap3xxx_l4_core_hwmod
,
2635 .slave
= &omap3430es1_dss_core_hwmod
,
2637 .addr
= omap2_dss_addrs
,
2640 .l4_fw_region
= OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION
,
2641 .l4_prot_group
= OMAP3_L4_CORE_FW_DSS_PROT_GROUP
,
2642 .flags
= OMAP_FIREWALL_L4
,
2645 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2648 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss
= {
2649 .master
= &omap3xxx_l4_core_hwmod
,
2650 .slave
= &omap3xxx_dss_core_hwmod
,
2652 .addr
= omap2_dss_addrs
,
2655 .l4_fw_region
= OMAP3_L4_CORE_FW_DSS_CORE_REGION
,
2656 .l4_prot_group
= OMAP3_L4_CORE_FW_DSS_PROT_GROUP
,
2657 .flags
= OMAP_FIREWALL_L4
,
2660 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2663 /* l4_core -> dss_dispc */
2664 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc
= {
2665 .master
= &omap3xxx_l4_core_hwmod
,
2666 .slave
= &omap3xxx_dss_dispc_hwmod
,
2668 .addr
= omap2_dss_dispc_addrs
,
2671 .l4_fw_region
= OMAP3_L4_CORE_FW_DSS_DISPC_REGION
,
2672 .l4_prot_group
= OMAP3_L4_CORE_FW_DSS_PROT_GROUP
,
2673 .flags
= OMAP_FIREWALL_L4
,
2676 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2679 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs
[] = {
2681 .pa_start
= 0x4804FC00,
2682 .pa_end
= 0x4804FFFF,
2683 .flags
= ADDR_TYPE_RT
2688 /* l4_core -> dss_dsi1 */
2689 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1
= {
2690 .master
= &omap3xxx_l4_core_hwmod
,
2691 .slave
= &omap3xxx_dss_dsi1_hwmod
,
2693 .addr
= omap3xxx_dss_dsi1_addrs
,
2696 .l4_fw_region
= OMAP3_L4_CORE_FW_DSS_DSI_REGION
,
2697 .l4_prot_group
= OMAP3_L4_CORE_FW_DSS_PROT_GROUP
,
2698 .flags
= OMAP_FIREWALL_L4
,
2701 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2704 /* l4_core -> dss_rfbi */
2705 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi
= {
2706 .master
= &omap3xxx_l4_core_hwmod
,
2707 .slave
= &omap3xxx_dss_rfbi_hwmod
,
2709 .addr
= omap2_dss_rfbi_addrs
,
2712 .l4_fw_region
= OMAP3_L4_CORE_FW_DSS_RFBI_REGION
,
2713 .l4_prot_group
= OMAP3_L4_CORE_FW_DSS_PROT_GROUP
,
2714 .flags
= OMAP_FIREWALL_L4
,
2717 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2720 /* l4_core -> dss_venc */
2721 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc
= {
2722 .master
= &omap3xxx_l4_core_hwmod
,
2723 .slave
= &omap3xxx_dss_venc_hwmod
,
2725 .addr
= omap2_dss_venc_addrs
,
2728 .l4_fw_region
= OMAP3_L4_CORE_FW_DSS_VENC_REGION
,
2729 .l4_prot_group
= OMAP3_L4_CORE_FW_DSS_PROT_GROUP
,
2730 .flags
= OMAP_FIREWALL_L4
,
2733 .flags
= OCPIF_SWSUP_IDLE
,
2734 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2737 /* l4_wkup -> gpio1 */
2738 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs
[] = {
2740 .pa_start
= 0x48310000,
2741 .pa_end
= 0x483101ff,
2742 .flags
= ADDR_TYPE_RT
2747 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1
= {
2748 .master
= &omap3xxx_l4_wkup_hwmod
,
2749 .slave
= &omap3xxx_gpio1_hwmod
,
2750 .addr
= omap3xxx_gpio1_addrs
,
2751 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2754 /* l4_per -> gpio2 */
2755 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs
[] = {
2757 .pa_start
= 0x49050000,
2758 .pa_end
= 0x490501ff,
2759 .flags
= ADDR_TYPE_RT
2764 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2
= {
2765 .master
= &omap3xxx_l4_per_hwmod
,
2766 .slave
= &omap3xxx_gpio2_hwmod
,
2767 .addr
= omap3xxx_gpio2_addrs
,
2768 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2771 /* l4_per -> gpio3 */
2772 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs
[] = {
2774 .pa_start
= 0x49052000,
2775 .pa_end
= 0x490521ff,
2776 .flags
= ADDR_TYPE_RT
2781 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3
= {
2782 .master
= &omap3xxx_l4_per_hwmod
,
2783 .slave
= &omap3xxx_gpio3_hwmod
,
2784 .addr
= omap3xxx_gpio3_addrs
,
2785 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2788 /* l4_per -> gpio4 */
2789 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs
[] = {
2791 .pa_start
= 0x49054000,
2792 .pa_end
= 0x490541ff,
2793 .flags
= ADDR_TYPE_RT
2798 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4
= {
2799 .master
= &omap3xxx_l4_per_hwmod
,
2800 .slave
= &omap3xxx_gpio4_hwmod
,
2801 .addr
= omap3xxx_gpio4_addrs
,
2802 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2805 /* l4_per -> gpio5 */
2806 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs
[] = {
2808 .pa_start
= 0x49056000,
2809 .pa_end
= 0x490561ff,
2810 .flags
= ADDR_TYPE_RT
2815 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5
= {
2816 .master
= &omap3xxx_l4_per_hwmod
,
2817 .slave
= &omap3xxx_gpio5_hwmod
,
2818 .addr
= omap3xxx_gpio5_addrs
,
2819 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2822 /* l4_per -> gpio6 */
2823 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs
[] = {
2825 .pa_start
= 0x49058000,
2826 .pa_end
= 0x490581ff,
2827 .flags
= ADDR_TYPE_RT
2832 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6
= {
2833 .master
= &omap3xxx_l4_per_hwmod
,
2834 .slave
= &omap3xxx_gpio6_hwmod
,
2835 .addr
= omap3xxx_gpio6_addrs
,
2836 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2839 /* dma_system -> L3 */
2840 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3
= {
2841 .master
= &omap3xxx_dma_system_hwmod
,
2842 .slave
= &omap3xxx_l3_main_hwmod
,
2843 .clk
= "core_l3_ick",
2844 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2847 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs
[] = {
2849 .pa_start
= 0x48056000,
2850 .pa_end
= 0x48056fff,
2851 .flags
= ADDR_TYPE_RT
2856 /* l4_cfg -> dma_system */
2857 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system
= {
2858 .master
= &omap3xxx_l4_core_hwmod
,
2859 .slave
= &omap3xxx_dma_system_hwmod
,
2860 .clk
= "core_l4_ick",
2861 .addr
= omap3xxx_dma_system_addrs
,
2862 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2865 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs
[] = {
2868 .pa_start
= 0x48074000,
2869 .pa_end
= 0x480740ff,
2870 .flags
= ADDR_TYPE_RT
2875 /* l4_core -> mcbsp1 */
2876 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1
= {
2877 .master
= &omap3xxx_l4_core_hwmod
,
2878 .slave
= &omap3xxx_mcbsp1_hwmod
,
2879 .clk
= "mcbsp1_ick",
2880 .addr
= omap3xxx_mcbsp1_addrs
,
2881 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2884 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs
[] = {
2887 .pa_start
= 0x49022000,
2888 .pa_end
= 0x490220ff,
2889 .flags
= ADDR_TYPE_RT
2894 /* l4_per -> mcbsp2 */
2895 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2
= {
2896 .master
= &omap3xxx_l4_per_hwmod
,
2897 .slave
= &omap3xxx_mcbsp2_hwmod
,
2898 .clk
= "mcbsp2_ick",
2899 .addr
= omap3xxx_mcbsp2_addrs
,
2900 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2903 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs
[] = {
2906 .pa_start
= 0x49024000,
2907 .pa_end
= 0x490240ff,
2908 .flags
= ADDR_TYPE_RT
2913 /* l4_per -> mcbsp3 */
2914 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3
= {
2915 .master
= &omap3xxx_l4_per_hwmod
,
2916 .slave
= &omap3xxx_mcbsp3_hwmod
,
2917 .clk
= "mcbsp3_ick",
2918 .addr
= omap3xxx_mcbsp3_addrs
,
2919 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2922 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs
[] = {
2925 .pa_start
= 0x49026000,
2926 .pa_end
= 0x490260ff,
2927 .flags
= ADDR_TYPE_RT
2932 /* l4_per -> mcbsp4 */
2933 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4
= {
2934 .master
= &omap3xxx_l4_per_hwmod
,
2935 .slave
= &omap3xxx_mcbsp4_hwmod
,
2936 .clk
= "mcbsp4_ick",
2937 .addr
= omap3xxx_mcbsp4_addrs
,
2938 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2941 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs
[] = {
2944 .pa_start
= 0x48096000,
2945 .pa_end
= 0x480960ff,
2946 .flags
= ADDR_TYPE_RT
2951 /* l4_core -> mcbsp5 */
2952 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5
= {
2953 .master
= &omap3xxx_l4_core_hwmod
,
2954 .slave
= &omap3xxx_mcbsp5_hwmod
,
2955 .clk
= "mcbsp5_ick",
2956 .addr
= omap3xxx_mcbsp5_addrs
,
2957 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2960 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs
[] = {
2963 .pa_start
= 0x49028000,
2964 .pa_end
= 0x490280ff,
2965 .flags
= ADDR_TYPE_RT
2970 /* l4_per -> mcbsp2_sidetone */
2971 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone
= {
2972 .master
= &omap3xxx_l4_per_hwmod
,
2973 .slave
= &omap3xxx_mcbsp2_sidetone_hwmod
,
2974 .clk
= "mcbsp2_ick",
2975 .addr
= omap3xxx_mcbsp2_sidetone_addrs
,
2976 .user
= OCP_USER_MPU
,
2979 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs
[] = {
2982 .pa_start
= 0x4902A000,
2983 .pa_end
= 0x4902A0ff,
2984 .flags
= ADDR_TYPE_RT
2989 /* l4_per -> mcbsp3_sidetone */
2990 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone
= {
2991 .master
= &omap3xxx_l4_per_hwmod
,
2992 .slave
= &omap3xxx_mcbsp3_sidetone_hwmod
,
2993 .clk
= "mcbsp3_ick",
2994 .addr
= omap3xxx_mcbsp3_sidetone_addrs
,
2995 .user
= OCP_USER_MPU
,
2998 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs
[] = {
3000 .pa_start
= 0x48094000,
3001 .pa_end
= 0x480941ff,
3002 .flags
= ADDR_TYPE_RT
,
3007 /* l4_core -> mailbox */
3008 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox
= {
3009 .master
= &omap3xxx_l4_core_hwmod
,
3010 .slave
= &omap3xxx_mailbox_hwmod
,
3011 .addr
= omap3xxx_mailbox_addrs
,
3012 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3015 /* l4 core -> mcspi1 interface */
3016 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1
= {
3017 .master
= &omap3xxx_l4_core_hwmod
,
3018 .slave
= &omap34xx_mcspi1
,
3019 .clk
= "mcspi1_ick",
3020 .addr
= omap2_mcspi1_addr_space
,
3021 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3024 /* l4 core -> mcspi2 interface */
3025 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2
= {
3026 .master
= &omap3xxx_l4_core_hwmod
,
3027 .slave
= &omap34xx_mcspi2
,
3028 .clk
= "mcspi2_ick",
3029 .addr
= omap2_mcspi2_addr_space
,
3030 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3033 /* l4 core -> mcspi3 interface */
3034 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3
= {
3035 .master
= &omap3xxx_l4_core_hwmod
,
3036 .slave
= &omap34xx_mcspi3
,
3037 .clk
= "mcspi3_ick",
3038 .addr
= omap2430_mcspi3_addr_space
,
3039 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3042 /* l4 core -> mcspi4 interface */
3043 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space
[] = {
3045 .pa_start
= 0x480ba000,
3046 .pa_end
= 0x480ba0ff,
3047 .flags
= ADDR_TYPE_RT
,
3052 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4
= {
3053 .master
= &omap3xxx_l4_core_hwmod
,
3054 .slave
= &omap34xx_mcspi4
,
3055 .clk
= "mcspi4_ick",
3056 .addr
= omap34xx_mcspi4_addr_space
,
3057 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3060 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2
= {
3061 .master
= &omap3xxx_usb_host_hs_hwmod
,
3062 .slave
= &omap3xxx_l3_main_hwmod
,
3063 .clk
= "core_l3_ick",
3064 .user
= OCP_USER_MPU
,
3067 static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs
[] = {
3070 .pa_start
= 0x48064000,
3071 .pa_end
= 0x480643ff,
3072 .flags
= ADDR_TYPE_RT
3076 .pa_start
= 0x48064400,
3077 .pa_end
= 0x480647ff,
3081 .pa_start
= 0x48064800,
3082 .pa_end
= 0x48064cff,
3087 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs
= {
3088 .master
= &omap3xxx_l4_core_hwmod
,
3089 .slave
= &omap3xxx_usb_host_hs_hwmod
,
3090 .clk
= "usbhost_ick",
3091 .addr
= omap3xxx_usb_host_hs_addrs
,
3092 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3095 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs
[] = {
3098 .pa_start
= 0x48062000,
3099 .pa_end
= 0x48062fff,
3100 .flags
= ADDR_TYPE_RT
3105 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs
= {
3106 .master
= &omap3xxx_l4_core_hwmod
,
3107 .slave
= &omap3xxx_usb_tll_hs_hwmod
,
3108 .clk
= "usbtll_ick",
3109 .addr
= omap3xxx_usb_tll_hs_addrs
,
3110 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3113 /* l4_core -> hdq1w interface */
3114 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w
= {
3115 .master
= &omap3xxx_l4_core_hwmod
,
3116 .slave
= &omap3xxx_hdq1w_hwmod
,
3118 .addr
= omap2_hdq1w_addr_space
,
3119 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3120 .flags
= OMAP_FIREWALL_L4
| OCPIF_SWSUP_IDLE
,
3123 /* l4_wkup -> 32ksync_counter */
3124 static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs
[] = {
3126 .pa_start
= 0x48320000,
3127 .pa_end
= 0x4832001f,
3128 .flags
= ADDR_TYPE_RT
3133 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k
= {
3134 .master
= &omap3xxx_l4_wkup_hwmod
,
3135 .slave
= &omap3xxx_counter_32k_hwmod
,
3136 .clk
= "omap_32ksync_ick",
3137 .addr
= omap3xxx_counter_32k_addrs
,
3138 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3141 static struct omap_hwmod_ocp_if
*omap3xxx_hwmod_ocp_ifs
[] __initdata
= {
3142 &omap3xxx_l3_main__l4_core
,
3143 &omap3xxx_l3_main__l4_per
,
3144 &omap3xxx_mpu__l3_main
,
3145 &omap3xxx_l4_core__l4_wkup
,
3146 &omap3xxx_l4_core__mmc3
,
3147 &omap3_l4_core__uart1
,
3148 &omap3_l4_core__uart2
,
3149 &omap3_l4_per__uart3
,
3150 &omap3_l4_core__i2c1
,
3151 &omap3_l4_core__i2c2
,
3152 &omap3_l4_core__i2c3
,
3153 &omap3xxx_l4_wkup__l4_sec
,
3154 &omap3xxx_l4_wkup__timer1
,
3155 &omap3xxx_l4_per__timer2
,
3156 &omap3xxx_l4_per__timer3
,
3157 &omap3xxx_l4_per__timer4
,
3158 &omap3xxx_l4_per__timer5
,
3159 &omap3xxx_l4_per__timer6
,
3160 &omap3xxx_l4_per__timer7
,
3161 &omap3xxx_l4_per__timer8
,
3162 &omap3xxx_l4_per__timer9
,
3163 &omap3xxx_l4_core__timer10
,
3164 &omap3xxx_l4_core__timer11
,
3165 &omap3xxx_l4_wkup__wd_timer2
,
3166 &omap3xxx_l4_wkup__gpio1
,
3167 &omap3xxx_l4_per__gpio2
,
3168 &omap3xxx_l4_per__gpio3
,
3169 &omap3xxx_l4_per__gpio4
,
3170 &omap3xxx_l4_per__gpio5
,
3171 &omap3xxx_l4_per__gpio6
,
3172 &omap3xxx_dma_system__l3
,
3173 &omap3xxx_l4_core__dma_system
,
3174 &omap3xxx_l4_core__mcbsp1
,
3175 &omap3xxx_l4_per__mcbsp2
,
3176 &omap3xxx_l4_per__mcbsp3
,
3177 &omap3xxx_l4_per__mcbsp4
,
3178 &omap3xxx_l4_core__mcbsp5
,
3179 &omap3xxx_l4_per__mcbsp2_sidetone
,
3180 &omap3xxx_l4_per__mcbsp3_sidetone
,
3181 &omap34xx_l4_core__mcspi1
,
3182 &omap34xx_l4_core__mcspi2
,
3183 &omap34xx_l4_core__mcspi3
,
3184 &omap34xx_l4_core__mcspi4
,
3185 &omap3xxx_l4_wkup__counter_32k
,
3189 /* GP-only hwmod links */
3190 static struct omap_hwmod_ocp_if
*omap3xxx_gp_hwmod_ocp_ifs
[] __initdata
= {
3191 &omap3xxx_l4_sec__timer12
,
3195 /* 3430ES1-only hwmod links */
3196 static struct omap_hwmod_ocp_if
*omap3430es1_hwmod_ocp_ifs
[] __initdata
= {
3197 &omap3430es1_dss__l3
,
3198 &omap3430es1_l4_core__dss
,
3202 /* 3430ES2+-only hwmod links */
3203 static struct omap_hwmod_ocp_if
*omap3430es2plus_hwmod_ocp_ifs
[] __initdata
= {
3205 &omap3xxx_l4_core__dss
,
3206 &omap3xxx_usbhsotg__l3
,
3207 &omap3xxx_l4_core__usbhsotg
,
3208 &omap3xxx_usb_host_hs__l3_main_2
,
3209 &omap3xxx_l4_core__usb_host_hs
,
3210 &omap3xxx_l4_core__usb_tll_hs
,
3214 /* <= 3430ES3-only hwmod links */
3215 static struct omap_hwmod_ocp_if
*omap3430_pre_es3_hwmod_ocp_ifs
[] __initdata
= {
3216 &omap3xxx_l4_core__pre_es3_mmc1
,
3217 &omap3xxx_l4_core__pre_es3_mmc2
,
3221 /* 3430ES3+-only hwmod links */
3222 static struct omap_hwmod_ocp_if
*omap3430_es3plus_hwmod_ocp_ifs
[] __initdata
= {
3223 &omap3xxx_l4_core__es3plus_mmc1
,
3224 &omap3xxx_l4_core__es3plus_mmc2
,
3228 /* 34xx-only hwmod links (all ES revisions) */
3229 static struct omap_hwmod_ocp_if
*omap34xx_hwmod_ocp_ifs
[] __initdata
= {
3231 &omap34xx_l4_core__sr1
,
3232 &omap34xx_l4_core__sr2
,
3233 &omap3xxx_l4_core__mailbox
,
3234 &omap3xxx_l4_core__hdq1w
,
3238 /* 36xx-only hwmod links (all ES revisions) */
3239 static struct omap_hwmod_ocp_if
*omap36xx_hwmod_ocp_ifs
[] __initdata
= {
3241 &omap36xx_l4_per__uart4
,
3243 &omap3xxx_l4_core__dss
,
3244 &omap36xx_l4_core__sr1
,
3245 &omap36xx_l4_core__sr2
,
3246 &omap3xxx_usbhsotg__l3
,
3247 &omap3xxx_l4_core__usbhsotg
,
3248 &omap3xxx_l4_core__mailbox
,
3249 &omap3xxx_usb_host_hs__l3_main_2
,
3250 &omap3xxx_l4_core__usb_host_hs
,
3251 &omap3xxx_l4_core__usb_tll_hs
,
3252 &omap3xxx_l4_core__es3plus_mmc1
,
3253 &omap3xxx_l4_core__es3plus_mmc2
,
3254 &omap3xxx_l4_core__hdq1w
,
3258 static struct omap_hwmod_ocp_if
*am35xx_hwmod_ocp_ifs
[] __initdata
= {
3260 &omap3xxx_l4_core__dss
,
3261 &am35xx_usbhsotg__l3
,
3262 &am35xx_l4_core__usbhsotg
,
3263 &am35xx_l4_core__uart4
,
3264 &omap3xxx_usb_host_hs__l3_main_2
,
3265 &omap3xxx_l4_core__usb_host_hs
,
3266 &omap3xxx_l4_core__usb_tll_hs
,
3267 &omap3xxx_l4_core__es3plus_mmc1
,
3268 &omap3xxx_l4_core__es3plus_mmc2
,
3272 static struct omap_hwmod_ocp_if
*omap3xxx_dss_hwmod_ocp_ifs
[] __initdata
= {
3273 &omap3xxx_l4_core__dss_dispc
,
3274 &omap3xxx_l4_core__dss_dsi1
,
3275 &omap3xxx_l4_core__dss_rfbi
,
3276 &omap3xxx_l4_core__dss_venc
,
3280 int __init
omap3xxx_hwmod_init(void)
3283 struct omap_hwmod_ocp_if
**h
= NULL
;
3286 /* Register hwmod links common to all OMAP3 */
3287 r
= omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs
);
3291 /* Register GP-only hwmod links. */
3292 if (omap_type() == OMAP2_DEVICE_TYPE_GP
) {
3293 r
= omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs
);
3301 * Register hwmod links common to individual OMAP3 families, all
3302 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3303 * All possible revisions should be included in this conditional.
3305 if (rev
== OMAP3430_REV_ES1_0
|| rev
== OMAP3430_REV_ES2_0
||
3306 rev
== OMAP3430_REV_ES2_1
|| rev
== OMAP3430_REV_ES3_0
||
3307 rev
== OMAP3430_REV_ES3_1
|| rev
== OMAP3430_REV_ES3_1_2
) {
3308 h
= omap34xx_hwmod_ocp_ifs
;
3309 } else if (rev
== AM35XX_REV_ES1_0
|| rev
== AM35XX_REV_ES1_1
) {
3310 h
= am35xx_hwmod_ocp_ifs
;
3311 } else if (rev
== OMAP3630_REV_ES1_0
|| rev
== OMAP3630_REV_ES1_1
||
3312 rev
== OMAP3630_REV_ES1_2
) {
3313 h
= omap36xx_hwmod_ocp_ifs
;
3315 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3319 r
= omap_hwmod_register_links(h
);
3324 * Register hwmod links specific to certain ES levels of a
3325 * particular family of silicon (e.g., 34xx ES1.0)
3328 if (rev
== OMAP3430_REV_ES1_0
) {
3329 h
= omap3430es1_hwmod_ocp_ifs
;
3330 } else if (rev
== OMAP3430_REV_ES2_0
|| rev
== OMAP3430_REV_ES2_1
||
3331 rev
== OMAP3430_REV_ES3_0
|| rev
== OMAP3430_REV_ES3_1
||
3332 rev
== OMAP3430_REV_ES3_1_2
) {
3333 h
= omap3430es2plus_hwmod_ocp_ifs
;
3337 r
= omap_hwmod_register_links(h
);
3343 if (rev
== OMAP3430_REV_ES1_0
|| rev
== OMAP3430_REV_ES2_0
||
3344 rev
== OMAP3430_REV_ES2_1
) {
3345 h
= omap3430_pre_es3_hwmod_ocp_ifs
;
3346 } else if (rev
== OMAP3430_REV_ES3_0
|| rev
== OMAP3430_REV_ES3_1
||
3347 rev
== OMAP3430_REV_ES3_1_2
) {
3348 h
= omap3430_es3plus_hwmod_ocp_ifs
;
3352 r
= omap_hwmod_register_links(h
);
3357 * DSS code presumes that dss_core hwmod is handled first,
3358 * _before_ any other DSS related hwmods so register common
3359 * DSS hwmod links last to ensure that dss_core is already
3360 * registered. Otherwise some change things may happen, for
3361 * ex. if dispc is handled before dss_core and DSS is enabled
3362 * in bootloader DISPC will be reset with outputs enabled
3363 * which sometimes leads to unrecoverable L3 error. XXX The
3364 * long-term fix to this is to ensure hwmods are set up in
3365 * dependency order in the hwmod core code.
3367 r
= omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs
);