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Merge tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_3xxx_data.c
1 /*
2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
3 *
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
6 * Paul Walmsley
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * The data in this file should be completely autogeneratable from
13 * the TI hardware database or other technical documentation.
14 *
15 * XXX these should be marked initdata for multi-OMAP kernels
16 */
17 #include <plat/omap_hwmod.h>
18 #include <mach/irqs.h>
19 #include <plat/cpu.h>
20 #include <plat/dma.h>
21 #include <plat/serial.h>
22 #include <plat/l3_3xxx.h>
23 #include <plat/l4_3xxx.h>
24 #include <plat/i2c.h>
25 #include <plat/gpio.h>
26 #include <plat/mmc.h>
27 #include <plat/mcbsp.h>
28 #include <plat/mcspi.h>
29 #include <plat/dmtimer.h>
30
31 #include "omap_hwmod_common_data.h"
32
33 #include "smartreflex.h"
34 #include "prm-regbits-34xx.h"
35 #include "cm-regbits-34xx.h"
36 #include "wd_timer.h"
37 #include <mach/am35xx.h>
38
39 /*
40 * OMAP3xxx hardware module integration data
41 *
42 * All of the data in this section should be autogeneratable from the
43 * TI hardware database or other technical documentation. Data that
44 * is driver-specific or driver-kernel integration-specific belongs
45 * elsewhere.
46 */
47
48 /*
49 * IP blocks
50 */
51
52 /* L3 */
53 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
54 { .irq = INT_34XX_L3_DBG_IRQ },
55 { .irq = INT_34XX_L3_APP_IRQ },
56 { .irq = -1 }
57 };
58
59 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
60 .name = "l3_main",
61 .class = &l3_hwmod_class,
62 .mpu_irqs = omap3xxx_l3_main_irqs,
63 .flags = HWMOD_NO_IDLEST,
64 };
65
66 /* L4 CORE */
67 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
68 .name = "l4_core",
69 .class = &l4_hwmod_class,
70 .flags = HWMOD_NO_IDLEST,
71 };
72
73 /* L4 PER */
74 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
75 .name = "l4_per",
76 .class = &l4_hwmod_class,
77 .flags = HWMOD_NO_IDLEST,
78 };
79
80 /* L4 WKUP */
81 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
82 .name = "l4_wkup",
83 .class = &l4_hwmod_class,
84 .flags = HWMOD_NO_IDLEST,
85 };
86
87 /* L4 SEC */
88 static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
89 .name = "l4_sec",
90 .class = &l4_hwmod_class,
91 .flags = HWMOD_NO_IDLEST,
92 };
93
94 /* MPU */
95 static struct omap_hwmod omap3xxx_mpu_hwmod = {
96 .name = "mpu",
97 .class = &mpu_hwmod_class,
98 .main_clk = "arm_fck",
99 };
100
101 /* IVA2 (IVA2) */
102 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
103 { .name = "logic", .rst_shift = 0 },
104 { .name = "seq0", .rst_shift = 1 },
105 { .name = "seq1", .rst_shift = 2 },
106 };
107
108 static struct omap_hwmod omap3xxx_iva_hwmod = {
109 .name = "iva",
110 .class = &iva_hwmod_class,
111 .clkdm_name = "iva2_clkdm",
112 .rst_lines = omap3xxx_iva_resets,
113 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets),
114 .main_clk = "iva2_ck",
115 };
116
117 /* timer class */
118 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
119 .rev_offs = 0x0000,
120 .sysc_offs = 0x0010,
121 .syss_offs = 0x0014,
122 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
123 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
124 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
125 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
126 .sysc_fields = &omap_hwmod_sysc_type1,
127 };
128
129 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
130 .name = "timer",
131 .sysc = &omap3xxx_timer_1ms_sysc,
132 .rev = OMAP_TIMER_IP_VERSION_1,
133 };
134
135 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
136 .rev_offs = 0x0000,
137 .sysc_offs = 0x0010,
138 .syss_offs = 0x0014,
139 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
140 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
141 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
142 .sysc_fields = &omap_hwmod_sysc_type1,
143 };
144
145 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
146 .name = "timer",
147 .sysc = &omap3xxx_timer_sysc,
148 .rev = OMAP_TIMER_IP_VERSION_1,
149 };
150
151 /* secure timers dev attribute */
152 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
153 .timer_capability = OMAP_TIMER_SECURE,
154 };
155
156 /* always-on timers dev attribute */
157 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
158 .timer_capability = OMAP_TIMER_ALWON,
159 };
160
161 /* pwm timers dev attribute */
162 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
163 .timer_capability = OMAP_TIMER_HAS_PWM,
164 };
165
166 /* timer1 */
167 static struct omap_hwmod omap3xxx_timer1_hwmod = {
168 .name = "timer1",
169 .mpu_irqs = omap2_timer1_mpu_irqs,
170 .main_clk = "gpt1_fck",
171 .prcm = {
172 .omap2 = {
173 .prcm_reg_id = 1,
174 .module_bit = OMAP3430_EN_GPT1_SHIFT,
175 .module_offs = WKUP_MOD,
176 .idlest_reg_id = 1,
177 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
178 },
179 },
180 .dev_attr = &capability_alwon_dev_attr,
181 .class = &omap3xxx_timer_1ms_hwmod_class,
182 };
183
184 /* timer2 */
185 static struct omap_hwmod omap3xxx_timer2_hwmod = {
186 .name = "timer2",
187 .mpu_irqs = omap2_timer2_mpu_irqs,
188 .main_clk = "gpt2_fck",
189 .prcm = {
190 .omap2 = {
191 .prcm_reg_id = 1,
192 .module_bit = OMAP3430_EN_GPT2_SHIFT,
193 .module_offs = OMAP3430_PER_MOD,
194 .idlest_reg_id = 1,
195 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
196 },
197 },
198 .dev_attr = &capability_alwon_dev_attr,
199 .class = &omap3xxx_timer_1ms_hwmod_class,
200 };
201
202 /* timer3 */
203 static struct omap_hwmod omap3xxx_timer3_hwmod = {
204 .name = "timer3",
205 .mpu_irqs = omap2_timer3_mpu_irqs,
206 .main_clk = "gpt3_fck",
207 .prcm = {
208 .omap2 = {
209 .prcm_reg_id = 1,
210 .module_bit = OMAP3430_EN_GPT3_SHIFT,
211 .module_offs = OMAP3430_PER_MOD,
212 .idlest_reg_id = 1,
213 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
214 },
215 },
216 .dev_attr = &capability_alwon_dev_attr,
217 .class = &omap3xxx_timer_hwmod_class,
218 };
219
220 /* timer4 */
221 static struct omap_hwmod omap3xxx_timer4_hwmod = {
222 .name = "timer4",
223 .mpu_irqs = omap2_timer4_mpu_irqs,
224 .main_clk = "gpt4_fck",
225 .prcm = {
226 .omap2 = {
227 .prcm_reg_id = 1,
228 .module_bit = OMAP3430_EN_GPT4_SHIFT,
229 .module_offs = OMAP3430_PER_MOD,
230 .idlest_reg_id = 1,
231 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
232 },
233 },
234 .dev_attr = &capability_alwon_dev_attr,
235 .class = &omap3xxx_timer_hwmod_class,
236 };
237
238 /* timer5 */
239 static struct omap_hwmod omap3xxx_timer5_hwmod = {
240 .name = "timer5",
241 .mpu_irqs = omap2_timer5_mpu_irqs,
242 .main_clk = "gpt5_fck",
243 .prcm = {
244 .omap2 = {
245 .prcm_reg_id = 1,
246 .module_bit = OMAP3430_EN_GPT5_SHIFT,
247 .module_offs = OMAP3430_PER_MOD,
248 .idlest_reg_id = 1,
249 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
250 },
251 },
252 .dev_attr = &capability_alwon_dev_attr,
253 .class = &omap3xxx_timer_hwmod_class,
254 };
255
256 /* timer6 */
257 static struct omap_hwmod omap3xxx_timer6_hwmod = {
258 .name = "timer6",
259 .mpu_irqs = omap2_timer6_mpu_irqs,
260 .main_clk = "gpt6_fck",
261 .prcm = {
262 .omap2 = {
263 .prcm_reg_id = 1,
264 .module_bit = OMAP3430_EN_GPT6_SHIFT,
265 .module_offs = OMAP3430_PER_MOD,
266 .idlest_reg_id = 1,
267 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
268 },
269 },
270 .dev_attr = &capability_alwon_dev_attr,
271 .class = &omap3xxx_timer_hwmod_class,
272 };
273
274 /* timer7 */
275 static struct omap_hwmod omap3xxx_timer7_hwmod = {
276 .name = "timer7",
277 .mpu_irqs = omap2_timer7_mpu_irqs,
278 .main_clk = "gpt7_fck",
279 .prcm = {
280 .omap2 = {
281 .prcm_reg_id = 1,
282 .module_bit = OMAP3430_EN_GPT7_SHIFT,
283 .module_offs = OMAP3430_PER_MOD,
284 .idlest_reg_id = 1,
285 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
286 },
287 },
288 .dev_attr = &capability_alwon_dev_attr,
289 .class = &omap3xxx_timer_hwmod_class,
290 };
291
292 /* timer8 */
293 static struct omap_hwmod omap3xxx_timer8_hwmod = {
294 .name = "timer8",
295 .mpu_irqs = omap2_timer8_mpu_irqs,
296 .main_clk = "gpt8_fck",
297 .prcm = {
298 .omap2 = {
299 .prcm_reg_id = 1,
300 .module_bit = OMAP3430_EN_GPT8_SHIFT,
301 .module_offs = OMAP3430_PER_MOD,
302 .idlest_reg_id = 1,
303 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
304 },
305 },
306 .dev_attr = &capability_pwm_dev_attr,
307 .class = &omap3xxx_timer_hwmod_class,
308 };
309
310 /* timer9 */
311 static struct omap_hwmod omap3xxx_timer9_hwmod = {
312 .name = "timer9",
313 .mpu_irqs = omap2_timer9_mpu_irqs,
314 .main_clk = "gpt9_fck",
315 .prcm = {
316 .omap2 = {
317 .prcm_reg_id = 1,
318 .module_bit = OMAP3430_EN_GPT9_SHIFT,
319 .module_offs = OMAP3430_PER_MOD,
320 .idlest_reg_id = 1,
321 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
322 },
323 },
324 .dev_attr = &capability_pwm_dev_attr,
325 .class = &omap3xxx_timer_hwmod_class,
326 };
327
328 /* timer10 */
329 static struct omap_hwmod omap3xxx_timer10_hwmod = {
330 .name = "timer10",
331 .mpu_irqs = omap2_timer10_mpu_irqs,
332 .main_clk = "gpt10_fck",
333 .prcm = {
334 .omap2 = {
335 .prcm_reg_id = 1,
336 .module_bit = OMAP3430_EN_GPT10_SHIFT,
337 .module_offs = CORE_MOD,
338 .idlest_reg_id = 1,
339 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
340 },
341 },
342 .dev_attr = &capability_pwm_dev_attr,
343 .class = &omap3xxx_timer_1ms_hwmod_class,
344 };
345
346 /* timer11 */
347 static struct omap_hwmod omap3xxx_timer11_hwmod = {
348 .name = "timer11",
349 .mpu_irqs = omap2_timer11_mpu_irqs,
350 .main_clk = "gpt11_fck",
351 .prcm = {
352 .omap2 = {
353 .prcm_reg_id = 1,
354 .module_bit = OMAP3430_EN_GPT11_SHIFT,
355 .module_offs = CORE_MOD,
356 .idlest_reg_id = 1,
357 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
358 },
359 },
360 .dev_attr = &capability_pwm_dev_attr,
361 .class = &omap3xxx_timer_hwmod_class,
362 };
363
364 /* timer12 */
365 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
366 { .irq = 95, },
367 { .irq = -1 }
368 };
369
370 static struct omap_hwmod omap3xxx_timer12_hwmod = {
371 .name = "timer12",
372 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
373 .main_clk = "gpt12_fck",
374 .prcm = {
375 .omap2 = {
376 .prcm_reg_id = 1,
377 .module_bit = OMAP3430_EN_GPT12_SHIFT,
378 .module_offs = WKUP_MOD,
379 .idlest_reg_id = 1,
380 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
381 },
382 },
383 .dev_attr = &capability_secure_dev_attr,
384 .class = &omap3xxx_timer_hwmod_class,
385 };
386
387 /*
388 * 'wd_timer' class
389 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
390 * overflow condition
391 */
392
393 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
394 .rev_offs = 0x0000,
395 .sysc_offs = 0x0010,
396 .syss_offs = 0x0014,
397 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
398 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
399 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
400 SYSS_HAS_RESET_STATUS),
401 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
402 .sysc_fields = &omap_hwmod_sysc_type1,
403 };
404
405 /* I2C common */
406 static struct omap_hwmod_class_sysconfig i2c_sysc = {
407 .rev_offs = 0x00,
408 .sysc_offs = 0x20,
409 .syss_offs = 0x10,
410 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
411 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
412 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
413 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
414 .clockact = CLOCKACT_TEST_ICLK,
415 .sysc_fields = &omap_hwmod_sysc_type1,
416 };
417
418 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
419 .name = "wd_timer",
420 .sysc = &omap3xxx_wd_timer_sysc,
421 .pre_shutdown = &omap2_wd_timer_disable,
422 .reset = &omap2_wd_timer_reset,
423 };
424
425 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
426 .name = "wd_timer2",
427 .class = &omap3xxx_wd_timer_hwmod_class,
428 .main_clk = "wdt2_fck",
429 .prcm = {
430 .omap2 = {
431 .prcm_reg_id = 1,
432 .module_bit = OMAP3430_EN_WDT2_SHIFT,
433 .module_offs = WKUP_MOD,
434 .idlest_reg_id = 1,
435 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
436 },
437 },
438 /*
439 * XXX: Use software supervised mode, HW supervised smartidle seems to
440 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
441 */
442 .flags = HWMOD_SWSUP_SIDLE,
443 };
444
445 /* UART1 */
446 static struct omap_hwmod omap3xxx_uart1_hwmod = {
447 .name = "uart1",
448 .mpu_irqs = omap2_uart1_mpu_irqs,
449 .sdma_reqs = omap2_uart1_sdma_reqs,
450 .main_clk = "uart1_fck",
451 .prcm = {
452 .omap2 = {
453 .module_offs = CORE_MOD,
454 .prcm_reg_id = 1,
455 .module_bit = OMAP3430_EN_UART1_SHIFT,
456 .idlest_reg_id = 1,
457 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
458 },
459 },
460 .class = &omap2_uart_class,
461 };
462
463 /* UART2 */
464 static struct omap_hwmod omap3xxx_uart2_hwmod = {
465 .name = "uart2",
466 .mpu_irqs = omap2_uart2_mpu_irqs,
467 .sdma_reqs = omap2_uart2_sdma_reqs,
468 .main_clk = "uart2_fck",
469 .prcm = {
470 .omap2 = {
471 .module_offs = CORE_MOD,
472 .prcm_reg_id = 1,
473 .module_bit = OMAP3430_EN_UART2_SHIFT,
474 .idlest_reg_id = 1,
475 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
476 },
477 },
478 .class = &omap2_uart_class,
479 };
480
481 /* UART3 */
482 static struct omap_hwmod omap3xxx_uart3_hwmod = {
483 .name = "uart3",
484 .mpu_irqs = omap2_uart3_mpu_irqs,
485 .sdma_reqs = omap2_uart3_sdma_reqs,
486 .main_clk = "uart3_fck",
487 .prcm = {
488 .omap2 = {
489 .module_offs = OMAP3430_PER_MOD,
490 .prcm_reg_id = 1,
491 .module_bit = OMAP3430_EN_UART3_SHIFT,
492 .idlest_reg_id = 1,
493 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
494 },
495 },
496 .class = &omap2_uart_class,
497 };
498
499 /* UART4 */
500 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
501 { .irq = INT_36XX_UART4_IRQ, },
502 { .irq = -1 }
503 };
504
505 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
506 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
507 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
508 { .dma_req = -1 }
509 };
510
511 static struct omap_hwmod omap36xx_uart4_hwmod = {
512 .name = "uart4",
513 .mpu_irqs = uart4_mpu_irqs,
514 .sdma_reqs = uart4_sdma_reqs,
515 .main_clk = "uart4_fck",
516 .prcm = {
517 .omap2 = {
518 .module_offs = OMAP3430_PER_MOD,
519 .prcm_reg_id = 1,
520 .module_bit = OMAP3630_EN_UART4_SHIFT,
521 .idlest_reg_id = 1,
522 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
523 },
524 },
525 .class = &omap2_uart_class,
526 };
527
528 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
529 { .irq = INT_35XX_UART4_IRQ, },
530 { .irq = -1 }
531 };
532
533 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
534 { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
535 { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
536 { .dma_req = -1 }
537 };
538
539 /*
540 * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
541 * uart2_fck being enabled. So we add uart1_fck as an optional clock,
542 * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET. This really
543 * should not be needed. The functional clock structure of the AM35xx
544 * UART4 is extremely unclear and opaque; it is unclear what the role
545 * of uart1/2_fck is for the UART4. Any clarification from either
546 * empirical testing or the AM3505/3517 hardware designers would be
547 * most welcome.
548 */
549 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
550 { .role = "softreset_uart1_fck", .clk = "uart1_fck" },
551 };
552
553 static struct omap_hwmod am35xx_uart4_hwmod = {
554 .name = "uart4",
555 .mpu_irqs = am35xx_uart4_mpu_irqs,
556 .sdma_reqs = am35xx_uart4_sdma_reqs,
557 .main_clk = "uart4_fck",
558 .prcm = {
559 .omap2 = {
560 .module_offs = CORE_MOD,
561 .prcm_reg_id = 1,
562 .module_bit = AM35XX_EN_UART4_SHIFT,
563 .idlest_reg_id = 1,
564 .idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
565 },
566 },
567 .opt_clks = am35xx_uart4_opt_clks,
568 .opt_clks_cnt = ARRAY_SIZE(am35xx_uart4_opt_clks),
569 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
570 .class = &omap2_uart_class,
571 };
572
573 static struct omap_hwmod_class i2c_class = {
574 .name = "i2c",
575 .sysc = &i2c_sysc,
576 .rev = OMAP_I2C_IP_VERSION_1,
577 .reset = &omap_i2c_reset,
578 };
579
580 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
581 { .name = "dispc", .dma_req = 5 },
582 { .name = "dsi1", .dma_req = 74 },
583 { .dma_req = -1 }
584 };
585
586 /* dss */
587 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
588 /*
589 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
590 * driver does not use these clocks.
591 */
592 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
593 { .role = "tv_clk", .clk = "dss_tv_fck" },
594 /* required only on OMAP3430 */
595 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
596 };
597
598 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
599 .name = "dss_core",
600 .class = &omap2_dss_hwmod_class,
601 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
602 .sdma_reqs = omap3xxx_dss_sdma_chs,
603 .prcm = {
604 .omap2 = {
605 .prcm_reg_id = 1,
606 .module_bit = OMAP3430_EN_DSS1_SHIFT,
607 .module_offs = OMAP3430_DSS_MOD,
608 .idlest_reg_id = 1,
609 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
610 },
611 },
612 .opt_clks = dss_opt_clks,
613 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
614 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
615 };
616
617 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
618 .name = "dss_core",
619 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
620 .class = &omap2_dss_hwmod_class,
621 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
622 .sdma_reqs = omap3xxx_dss_sdma_chs,
623 .prcm = {
624 .omap2 = {
625 .prcm_reg_id = 1,
626 .module_bit = OMAP3430_EN_DSS1_SHIFT,
627 .module_offs = OMAP3430_DSS_MOD,
628 .idlest_reg_id = 1,
629 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
630 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
631 },
632 },
633 .opt_clks = dss_opt_clks,
634 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
635 };
636
637 /*
638 * 'dispc' class
639 * display controller
640 */
641
642 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
643 .rev_offs = 0x0000,
644 .sysc_offs = 0x0010,
645 .syss_offs = 0x0014,
646 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
647 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
648 SYSC_HAS_ENAWAKEUP),
649 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
650 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
651 .sysc_fields = &omap_hwmod_sysc_type1,
652 };
653
654 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
655 .name = "dispc",
656 .sysc = &omap3_dispc_sysc,
657 };
658
659 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
660 .name = "dss_dispc",
661 .class = &omap3_dispc_hwmod_class,
662 .mpu_irqs = omap2_dispc_irqs,
663 .main_clk = "dss1_alwon_fck",
664 .prcm = {
665 .omap2 = {
666 .prcm_reg_id = 1,
667 .module_bit = OMAP3430_EN_DSS1_SHIFT,
668 .module_offs = OMAP3430_DSS_MOD,
669 },
670 },
671 .flags = HWMOD_NO_IDLEST,
672 .dev_attr = &omap2_3_dss_dispc_dev_attr
673 };
674
675 /*
676 * 'dsi' class
677 * display serial interface controller
678 */
679
680 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
681 .name = "dsi",
682 };
683
684 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
685 { .irq = 25 },
686 { .irq = -1 }
687 };
688
689 /* dss_dsi1 */
690 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
691 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
692 };
693
694 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
695 .name = "dss_dsi1",
696 .class = &omap3xxx_dsi_hwmod_class,
697 .mpu_irqs = omap3xxx_dsi1_irqs,
698 .main_clk = "dss1_alwon_fck",
699 .prcm = {
700 .omap2 = {
701 .prcm_reg_id = 1,
702 .module_bit = OMAP3430_EN_DSS1_SHIFT,
703 .module_offs = OMAP3430_DSS_MOD,
704 },
705 },
706 .opt_clks = dss_dsi1_opt_clks,
707 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
708 .flags = HWMOD_NO_IDLEST,
709 };
710
711 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
712 { .role = "ick", .clk = "dss_ick" },
713 };
714
715 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
716 .name = "dss_rfbi",
717 .class = &omap2_rfbi_hwmod_class,
718 .main_clk = "dss1_alwon_fck",
719 .prcm = {
720 .omap2 = {
721 .prcm_reg_id = 1,
722 .module_bit = OMAP3430_EN_DSS1_SHIFT,
723 .module_offs = OMAP3430_DSS_MOD,
724 },
725 },
726 .opt_clks = dss_rfbi_opt_clks,
727 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
728 .flags = HWMOD_NO_IDLEST,
729 };
730
731 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
732 /* required only on OMAP3430 */
733 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
734 };
735
736 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
737 .name = "dss_venc",
738 .class = &omap2_venc_hwmod_class,
739 .main_clk = "dss_tv_fck",
740 .prcm = {
741 .omap2 = {
742 .prcm_reg_id = 1,
743 .module_bit = OMAP3430_EN_DSS1_SHIFT,
744 .module_offs = OMAP3430_DSS_MOD,
745 },
746 },
747 .opt_clks = dss_venc_opt_clks,
748 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
749 .flags = HWMOD_NO_IDLEST,
750 };
751
752 /* I2C1 */
753 static struct omap_i2c_dev_attr i2c1_dev_attr = {
754 .fifo_depth = 8, /* bytes */
755 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
756 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
757 OMAP_I2C_FLAG_BUS_SHIFT_2,
758 };
759
760 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
761 .name = "i2c1",
762 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
763 .mpu_irqs = omap2_i2c1_mpu_irqs,
764 .sdma_reqs = omap2_i2c1_sdma_reqs,
765 .main_clk = "i2c1_fck",
766 .prcm = {
767 .omap2 = {
768 .module_offs = CORE_MOD,
769 .prcm_reg_id = 1,
770 .module_bit = OMAP3430_EN_I2C1_SHIFT,
771 .idlest_reg_id = 1,
772 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
773 },
774 },
775 .class = &i2c_class,
776 .dev_attr = &i2c1_dev_attr,
777 };
778
779 /* I2C2 */
780 static struct omap_i2c_dev_attr i2c2_dev_attr = {
781 .fifo_depth = 8, /* bytes */
782 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
783 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
784 OMAP_I2C_FLAG_BUS_SHIFT_2,
785 };
786
787 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
788 .name = "i2c2",
789 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
790 .mpu_irqs = omap2_i2c2_mpu_irqs,
791 .sdma_reqs = omap2_i2c2_sdma_reqs,
792 .main_clk = "i2c2_fck",
793 .prcm = {
794 .omap2 = {
795 .module_offs = CORE_MOD,
796 .prcm_reg_id = 1,
797 .module_bit = OMAP3430_EN_I2C2_SHIFT,
798 .idlest_reg_id = 1,
799 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
800 },
801 },
802 .class = &i2c_class,
803 .dev_attr = &i2c2_dev_attr,
804 };
805
806 /* I2C3 */
807 static struct omap_i2c_dev_attr i2c3_dev_attr = {
808 .fifo_depth = 64, /* bytes */
809 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
810 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
811 OMAP_I2C_FLAG_BUS_SHIFT_2,
812 };
813
814 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
815 { .irq = INT_34XX_I2C3_IRQ, },
816 { .irq = -1 }
817 };
818
819 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
820 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
821 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
822 { .dma_req = -1 }
823 };
824
825 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
826 .name = "i2c3",
827 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
828 .mpu_irqs = i2c3_mpu_irqs,
829 .sdma_reqs = i2c3_sdma_reqs,
830 .main_clk = "i2c3_fck",
831 .prcm = {
832 .omap2 = {
833 .module_offs = CORE_MOD,
834 .prcm_reg_id = 1,
835 .module_bit = OMAP3430_EN_I2C3_SHIFT,
836 .idlest_reg_id = 1,
837 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
838 },
839 },
840 .class = &i2c_class,
841 .dev_attr = &i2c3_dev_attr,
842 };
843
844 /*
845 * 'gpio' class
846 * general purpose io module
847 */
848
849 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
850 .rev_offs = 0x0000,
851 .sysc_offs = 0x0010,
852 .syss_offs = 0x0014,
853 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
854 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
855 SYSS_HAS_RESET_STATUS),
856 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
857 .sysc_fields = &omap_hwmod_sysc_type1,
858 };
859
860 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
861 .name = "gpio",
862 .sysc = &omap3xxx_gpio_sysc,
863 .rev = 1,
864 };
865
866 /* gpio_dev_attr */
867 static struct omap_gpio_dev_attr gpio_dev_attr = {
868 .bank_width = 32,
869 .dbck_flag = true,
870 };
871
872 /* gpio1 */
873 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
874 { .role = "dbclk", .clk = "gpio1_dbck", },
875 };
876
877 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
878 .name = "gpio1",
879 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
880 .mpu_irqs = omap2_gpio1_irqs,
881 .main_clk = "gpio1_ick",
882 .opt_clks = gpio1_opt_clks,
883 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
884 .prcm = {
885 .omap2 = {
886 .prcm_reg_id = 1,
887 .module_bit = OMAP3430_EN_GPIO1_SHIFT,
888 .module_offs = WKUP_MOD,
889 .idlest_reg_id = 1,
890 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
891 },
892 },
893 .class = &omap3xxx_gpio_hwmod_class,
894 .dev_attr = &gpio_dev_attr,
895 };
896
897 /* gpio2 */
898 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
899 { .role = "dbclk", .clk = "gpio2_dbck", },
900 };
901
902 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
903 .name = "gpio2",
904 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
905 .mpu_irqs = omap2_gpio2_irqs,
906 .main_clk = "gpio2_ick",
907 .opt_clks = gpio2_opt_clks,
908 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
909 .prcm = {
910 .omap2 = {
911 .prcm_reg_id = 1,
912 .module_bit = OMAP3430_EN_GPIO2_SHIFT,
913 .module_offs = OMAP3430_PER_MOD,
914 .idlest_reg_id = 1,
915 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
916 },
917 },
918 .class = &omap3xxx_gpio_hwmod_class,
919 .dev_attr = &gpio_dev_attr,
920 };
921
922 /* gpio3 */
923 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
924 { .role = "dbclk", .clk = "gpio3_dbck", },
925 };
926
927 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
928 .name = "gpio3",
929 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
930 .mpu_irqs = omap2_gpio3_irqs,
931 .main_clk = "gpio3_ick",
932 .opt_clks = gpio3_opt_clks,
933 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
934 .prcm = {
935 .omap2 = {
936 .prcm_reg_id = 1,
937 .module_bit = OMAP3430_EN_GPIO3_SHIFT,
938 .module_offs = OMAP3430_PER_MOD,
939 .idlest_reg_id = 1,
940 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
941 },
942 },
943 .class = &omap3xxx_gpio_hwmod_class,
944 .dev_attr = &gpio_dev_attr,
945 };
946
947 /* gpio4 */
948 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
949 { .role = "dbclk", .clk = "gpio4_dbck", },
950 };
951
952 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
953 .name = "gpio4",
954 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
955 .mpu_irqs = omap2_gpio4_irqs,
956 .main_clk = "gpio4_ick",
957 .opt_clks = gpio4_opt_clks,
958 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
959 .prcm = {
960 .omap2 = {
961 .prcm_reg_id = 1,
962 .module_bit = OMAP3430_EN_GPIO4_SHIFT,
963 .module_offs = OMAP3430_PER_MOD,
964 .idlest_reg_id = 1,
965 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
966 },
967 },
968 .class = &omap3xxx_gpio_hwmod_class,
969 .dev_attr = &gpio_dev_attr,
970 };
971
972 /* gpio5 */
973 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
974 { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
975 { .irq = -1 }
976 };
977
978 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
979 { .role = "dbclk", .clk = "gpio5_dbck", },
980 };
981
982 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
983 .name = "gpio5",
984 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
985 .mpu_irqs = omap3xxx_gpio5_irqs,
986 .main_clk = "gpio5_ick",
987 .opt_clks = gpio5_opt_clks,
988 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
989 .prcm = {
990 .omap2 = {
991 .prcm_reg_id = 1,
992 .module_bit = OMAP3430_EN_GPIO5_SHIFT,
993 .module_offs = OMAP3430_PER_MOD,
994 .idlest_reg_id = 1,
995 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
996 },
997 },
998 .class = &omap3xxx_gpio_hwmod_class,
999 .dev_attr = &gpio_dev_attr,
1000 };
1001
1002 /* gpio6 */
1003 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
1004 { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
1005 { .irq = -1 }
1006 };
1007
1008 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1009 { .role = "dbclk", .clk = "gpio6_dbck", },
1010 };
1011
1012 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
1013 .name = "gpio6",
1014 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1015 .mpu_irqs = omap3xxx_gpio6_irqs,
1016 .main_clk = "gpio6_ick",
1017 .opt_clks = gpio6_opt_clks,
1018 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1019 .prcm = {
1020 .omap2 = {
1021 .prcm_reg_id = 1,
1022 .module_bit = OMAP3430_EN_GPIO6_SHIFT,
1023 .module_offs = OMAP3430_PER_MOD,
1024 .idlest_reg_id = 1,
1025 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
1026 },
1027 },
1028 .class = &omap3xxx_gpio_hwmod_class,
1029 .dev_attr = &gpio_dev_attr,
1030 };
1031
1032 /* dma attributes */
1033 static struct omap_dma_dev_attr dma_dev_attr = {
1034 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1035 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1036 .lch_count = 32,
1037 };
1038
1039 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1040 .rev_offs = 0x0000,
1041 .sysc_offs = 0x002c,
1042 .syss_offs = 0x0028,
1043 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1044 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1045 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
1046 SYSS_HAS_RESET_STATUS),
1047 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1048 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1049 .sysc_fields = &omap_hwmod_sysc_type1,
1050 };
1051
1052 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1053 .name = "dma",
1054 .sysc = &omap3xxx_dma_sysc,
1055 };
1056
1057 /* dma_system */
1058 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1059 .name = "dma",
1060 .class = &omap3xxx_dma_hwmod_class,
1061 .mpu_irqs = omap2_dma_system_irqs,
1062 .main_clk = "core_l3_ick",
1063 .prcm = {
1064 .omap2 = {
1065 .module_offs = CORE_MOD,
1066 .prcm_reg_id = 1,
1067 .module_bit = OMAP3430_ST_SDMA_SHIFT,
1068 .idlest_reg_id = 1,
1069 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
1070 },
1071 },
1072 .dev_attr = &dma_dev_attr,
1073 .flags = HWMOD_NO_IDLEST,
1074 };
1075
1076 /*
1077 * 'mcbsp' class
1078 * multi channel buffered serial port controller
1079 */
1080
1081 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
1082 .sysc_offs = 0x008c,
1083 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1084 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1085 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1086 .sysc_fields = &omap_hwmod_sysc_type1,
1087 .clockact = 0x2,
1088 };
1089
1090 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1091 .name = "mcbsp",
1092 .sysc = &omap3xxx_mcbsp_sysc,
1093 .rev = MCBSP_CONFIG_TYPE3,
1094 };
1095
1096 /* McBSP functional clock mapping */
1097 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
1098 { .role = "pad_fck", .clk = "mcbsp_clks" },
1099 { .role = "prcm_fck", .clk = "core_96m_fck" },
1100 };
1101
1102 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
1103 { .role = "pad_fck", .clk = "mcbsp_clks" },
1104 { .role = "prcm_fck", .clk = "per_96m_fck" },
1105 };
1106
1107 /* mcbsp1 */
1108 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
1109 { .name = "common", .irq = 16 },
1110 { .name = "tx", .irq = 59 },
1111 { .name = "rx", .irq = 60 },
1112 { .irq = -1 }
1113 };
1114
1115 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1116 .name = "mcbsp1",
1117 .class = &omap3xxx_mcbsp_hwmod_class,
1118 .mpu_irqs = omap3xxx_mcbsp1_irqs,
1119 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
1120 .main_clk = "mcbsp1_fck",
1121 .prcm = {
1122 .omap2 = {
1123 .prcm_reg_id = 1,
1124 .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
1125 .module_offs = CORE_MOD,
1126 .idlest_reg_id = 1,
1127 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
1128 },
1129 },
1130 .opt_clks = mcbsp15_opt_clks,
1131 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
1132 };
1133
1134 /* mcbsp2 */
1135 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
1136 { .name = "common", .irq = 17 },
1137 { .name = "tx", .irq = 62 },
1138 { .name = "rx", .irq = 63 },
1139 { .irq = -1 }
1140 };
1141
1142 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1143 .sidetone = "mcbsp2_sidetone",
1144 };
1145
1146 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1147 .name = "mcbsp2",
1148 .class = &omap3xxx_mcbsp_hwmod_class,
1149 .mpu_irqs = omap3xxx_mcbsp2_irqs,
1150 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
1151 .main_clk = "mcbsp2_fck",
1152 .prcm = {
1153 .omap2 = {
1154 .prcm_reg_id = 1,
1155 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1156 .module_offs = OMAP3430_PER_MOD,
1157 .idlest_reg_id = 1,
1158 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1159 },
1160 },
1161 .opt_clks = mcbsp234_opt_clks,
1162 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1163 .dev_attr = &omap34xx_mcbsp2_dev_attr,
1164 };
1165
1166 /* mcbsp3 */
1167 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
1168 { .name = "common", .irq = 22 },
1169 { .name = "tx", .irq = 89 },
1170 { .name = "rx", .irq = 90 },
1171 { .irq = -1 }
1172 };
1173
1174 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1175 .sidetone = "mcbsp3_sidetone",
1176 };
1177
1178 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1179 .name = "mcbsp3",
1180 .class = &omap3xxx_mcbsp_hwmod_class,
1181 .mpu_irqs = omap3xxx_mcbsp3_irqs,
1182 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
1183 .main_clk = "mcbsp3_fck",
1184 .prcm = {
1185 .omap2 = {
1186 .prcm_reg_id = 1,
1187 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1188 .module_offs = OMAP3430_PER_MOD,
1189 .idlest_reg_id = 1,
1190 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1191 },
1192 },
1193 .opt_clks = mcbsp234_opt_clks,
1194 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1195 .dev_attr = &omap34xx_mcbsp3_dev_attr,
1196 };
1197
1198 /* mcbsp4 */
1199 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
1200 { .name = "common", .irq = 23 },
1201 { .name = "tx", .irq = 54 },
1202 { .name = "rx", .irq = 55 },
1203 { .irq = -1 }
1204 };
1205
1206 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
1207 { .name = "rx", .dma_req = 20 },
1208 { .name = "tx", .dma_req = 19 },
1209 { .dma_req = -1 }
1210 };
1211
1212 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1213 .name = "mcbsp4",
1214 .class = &omap3xxx_mcbsp_hwmod_class,
1215 .mpu_irqs = omap3xxx_mcbsp4_irqs,
1216 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
1217 .main_clk = "mcbsp4_fck",
1218 .prcm = {
1219 .omap2 = {
1220 .prcm_reg_id = 1,
1221 .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
1222 .module_offs = OMAP3430_PER_MOD,
1223 .idlest_reg_id = 1,
1224 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
1225 },
1226 },
1227 .opt_clks = mcbsp234_opt_clks,
1228 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1229 };
1230
1231 /* mcbsp5 */
1232 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
1233 { .name = "common", .irq = 27 },
1234 { .name = "tx", .irq = 81 },
1235 { .name = "rx", .irq = 82 },
1236 { .irq = -1 }
1237 };
1238
1239 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
1240 { .name = "rx", .dma_req = 22 },
1241 { .name = "tx", .dma_req = 21 },
1242 { .dma_req = -1 }
1243 };
1244
1245 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1246 .name = "mcbsp5",
1247 .class = &omap3xxx_mcbsp_hwmod_class,
1248 .mpu_irqs = omap3xxx_mcbsp5_irqs,
1249 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
1250 .main_clk = "mcbsp5_fck",
1251 .prcm = {
1252 .omap2 = {
1253 .prcm_reg_id = 1,
1254 .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
1255 .module_offs = CORE_MOD,
1256 .idlest_reg_id = 1,
1257 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
1258 },
1259 },
1260 .opt_clks = mcbsp15_opt_clks,
1261 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
1262 };
1263
1264 /* 'mcbsp sidetone' class */
1265 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
1266 .sysc_offs = 0x0010,
1267 .sysc_flags = SYSC_HAS_AUTOIDLE,
1268 .sysc_fields = &omap_hwmod_sysc_type1,
1269 };
1270
1271 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
1272 .name = "mcbsp_sidetone",
1273 .sysc = &omap3xxx_mcbsp_sidetone_sysc,
1274 };
1275
1276 /* mcbsp2_sidetone */
1277 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
1278 { .name = "irq", .irq = 4 },
1279 { .irq = -1 }
1280 };
1281
1282 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1283 .name = "mcbsp2_sidetone",
1284 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1285 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
1286 .main_clk = "mcbsp2_fck",
1287 .prcm = {
1288 .omap2 = {
1289 .prcm_reg_id = 1,
1290 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1291 .module_offs = OMAP3430_PER_MOD,
1292 .idlest_reg_id = 1,
1293 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1294 },
1295 },
1296 };
1297
1298 /* mcbsp3_sidetone */
1299 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
1300 { .name = "irq", .irq = 5 },
1301 { .irq = -1 }
1302 };
1303
1304 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1305 .name = "mcbsp3_sidetone",
1306 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1307 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
1308 .main_clk = "mcbsp3_fck",
1309 .prcm = {
1310 .omap2 = {
1311 .prcm_reg_id = 1,
1312 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1313 .module_offs = OMAP3430_PER_MOD,
1314 .idlest_reg_id = 1,
1315 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1316 },
1317 },
1318 };
1319
1320 /* SR common */
1321 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1322 .clkact_shift = 20,
1323 };
1324
1325 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1326 .sysc_offs = 0x24,
1327 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1328 .clockact = CLOCKACT_TEST_ICLK,
1329 .sysc_fields = &omap34xx_sr_sysc_fields,
1330 };
1331
1332 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1333 .name = "smartreflex",
1334 .sysc = &omap34xx_sr_sysc,
1335 .rev = 1,
1336 };
1337
1338 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
1339 .sidle_shift = 24,
1340 .enwkup_shift = 26,
1341 };
1342
1343 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1344 .sysc_offs = 0x38,
1345 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1346 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1347 SYSC_NO_CACHE),
1348 .sysc_fields = &omap36xx_sr_sysc_fields,
1349 };
1350
1351 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1352 .name = "smartreflex",
1353 .sysc = &omap36xx_sr_sysc,
1354 .rev = 2,
1355 };
1356
1357 /* SR1 */
1358 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1359 .sensor_voltdm_name = "mpu_iva",
1360 };
1361
1362 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
1363 { .irq = 18 },
1364 { .irq = -1 }
1365 };
1366
1367 static struct omap_hwmod omap34xx_sr1_hwmod = {
1368 .name = "sr1",
1369 .class = &omap34xx_smartreflex_hwmod_class,
1370 .main_clk = "sr1_fck",
1371 .prcm = {
1372 .omap2 = {
1373 .prcm_reg_id = 1,
1374 .module_bit = OMAP3430_EN_SR1_SHIFT,
1375 .module_offs = WKUP_MOD,
1376 .idlest_reg_id = 1,
1377 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1378 },
1379 },
1380 .dev_attr = &sr1_dev_attr,
1381 .mpu_irqs = omap3_smartreflex_mpu_irqs,
1382 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1383 };
1384
1385 static struct omap_hwmod omap36xx_sr1_hwmod = {
1386 .name = "sr1",
1387 .class = &omap36xx_smartreflex_hwmod_class,
1388 .main_clk = "sr1_fck",
1389 .prcm = {
1390 .omap2 = {
1391 .prcm_reg_id = 1,
1392 .module_bit = OMAP3430_EN_SR1_SHIFT,
1393 .module_offs = WKUP_MOD,
1394 .idlest_reg_id = 1,
1395 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1396 },
1397 },
1398 .dev_attr = &sr1_dev_attr,
1399 .mpu_irqs = omap3_smartreflex_mpu_irqs,
1400 };
1401
1402 /* SR2 */
1403 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1404 .sensor_voltdm_name = "core",
1405 };
1406
1407 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
1408 { .irq = 19 },
1409 { .irq = -1 }
1410 };
1411
1412 static struct omap_hwmod omap34xx_sr2_hwmod = {
1413 .name = "sr2",
1414 .class = &omap34xx_smartreflex_hwmod_class,
1415 .main_clk = "sr2_fck",
1416 .prcm = {
1417 .omap2 = {
1418 .prcm_reg_id = 1,
1419 .module_bit = OMAP3430_EN_SR2_SHIFT,
1420 .module_offs = WKUP_MOD,
1421 .idlest_reg_id = 1,
1422 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1423 },
1424 },
1425 .dev_attr = &sr2_dev_attr,
1426 .mpu_irqs = omap3_smartreflex_core_irqs,
1427 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1428 };
1429
1430 static struct omap_hwmod omap36xx_sr2_hwmod = {
1431 .name = "sr2",
1432 .class = &omap36xx_smartreflex_hwmod_class,
1433 .main_clk = "sr2_fck",
1434 .prcm = {
1435 .omap2 = {
1436 .prcm_reg_id = 1,
1437 .module_bit = OMAP3430_EN_SR2_SHIFT,
1438 .module_offs = WKUP_MOD,
1439 .idlest_reg_id = 1,
1440 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1441 },
1442 },
1443 .dev_attr = &sr2_dev_attr,
1444 .mpu_irqs = omap3_smartreflex_core_irqs,
1445 };
1446
1447 /*
1448 * 'mailbox' class
1449 * mailbox module allowing communication between the on-chip processors
1450 * using a queued mailbox-interrupt mechanism.
1451 */
1452
1453 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1454 .rev_offs = 0x000,
1455 .sysc_offs = 0x010,
1456 .syss_offs = 0x014,
1457 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1458 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1459 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1460 .sysc_fields = &omap_hwmod_sysc_type1,
1461 };
1462
1463 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1464 .name = "mailbox",
1465 .sysc = &omap3xxx_mailbox_sysc,
1466 };
1467
1468 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
1469 { .irq = 26 },
1470 { .irq = -1 }
1471 };
1472
1473 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1474 .name = "mailbox",
1475 .class = &omap3xxx_mailbox_hwmod_class,
1476 .mpu_irqs = omap3xxx_mailbox_irqs,
1477 .main_clk = "mailboxes_ick",
1478 .prcm = {
1479 .omap2 = {
1480 .prcm_reg_id = 1,
1481 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1482 .module_offs = CORE_MOD,
1483 .idlest_reg_id = 1,
1484 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1485 },
1486 },
1487 };
1488
1489 /*
1490 * 'mcspi' class
1491 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1492 * bus
1493 */
1494
1495 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1496 .rev_offs = 0x0000,
1497 .sysc_offs = 0x0010,
1498 .syss_offs = 0x0014,
1499 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1500 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1501 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1502 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1503 .sysc_fields = &omap_hwmod_sysc_type1,
1504 };
1505
1506 static struct omap_hwmod_class omap34xx_mcspi_class = {
1507 .name = "mcspi",
1508 .sysc = &omap34xx_mcspi_sysc,
1509 .rev = OMAP3_MCSPI_REV,
1510 };
1511
1512 /* mcspi1 */
1513 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1514 .num_chipselect = 4,
1515 };
1516
1517 static struct omap_hwmod omap34xx_mcspi1 = {
1518 .name = "mcspi1",
1519 .mpu_irqs = omap2_mcspi1_mpu_irqs,
1520 .sdma_reqs = omap2_mcspi1_sdma_reqs,
1521 .main_clk = "mcspi1_fck",
1522 .prcm = {
1523 .omap2 = {
1524 .module_offs = CORE_MOD,
1525 .prcm_reg_id = 1,
1526 .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
1527 .idlest_reg_id = 1,
1528 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1529 },
1530 },
1531 .class = &omap34xx_mcspi_class,
1532 .dev_attr = &omap_mcspi1_dev_attr,
1533 };
1534
1535 /* mcspi2 */
1536 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1537 .num_chipselect = 2,
1538 };
1539
1540 static struct omap_hwmod omap34xx_mcspi2 = {
1541 .name = "mcspi2",
1542 .mpu_irqs = omap2_mcspi2_mpu_irqs,
1543 .sdma_reqs = omap2_mcspi2_sdma_reqs,
1544 .main_clk = "mcspi2_fck",
1545 .prcm = {
1546 .omap2 = {
1547 .module_offs = CORE_MOD,
1548 .prcm_reg_id = 1,
1549 .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
1550 .idlest_reg_id = 1,
1551 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1552 },
1553 },
1554 .class = &omap34xx_mcspi_class,
1555 .dev_attr = &omap_mcspi2_dev_attr,
1556 };
1557
1558 /* mcspi3 */
1559 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
1560 { .name = "irq", .irq = 91 }, /* 91 */
1561 { .irq = -1 }
1562 };
1563
1564 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
1565 { .name = "tx0", .dma_req = 15 },
1566 { .name = "rx0", .dma_req = 16 },
1567 { .name = "tx1", .dma_req = 23 },
1568 { .name = "rx1", .dma_req = 24 },
1569 { .dma_req = -1 }
1570 };
1571
1572 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1573 .num_chipselect = 2,
1574 };
1575
1576 static struct omap_hwmod omap34xx_mcspi3 = {
1577 .name = "mcspi3",
1578 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
1579 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
1580 .main_clk = "mcspi3_fck",
1581 .prcm = {
1582 .omap2 = {
1583 .module_offs = CORE_MOD,
1584 .prcm_reg_id = 1,
1585 .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
1586 .idlest_reg_id = 1,
1587 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1588 },
1589 },
1590 .class = &omap34xx_mcspi_class,
1591 .dev_attr = &omap_mcspi3_dev_attr,
1592 };
1593
1594 /* mcspi4 */
1595 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
1596 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
1597 { .irq = -1 }
1598 };
1599
1600 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
1601 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
1602 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
1603 { .dma_req = -1 }
1604 };
1605
1606 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1607 .num_chipselect = 1,
1608 };
1609
1610 static struct omap_hwmod omap34xx_mcspi4 = {
1611 .name = "mcspi4",
1612 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
1613 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
1614 .main_clk = "mcspi4_fck",
1615 .prcm = {
1616 .omap2 = {
1617 .module_offs = CORE_MOD,
1618 .prcm_reg_id = 1,
1619 .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
1620 .idlest_reg_id = 1,
1621 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1622 },
1623 },
1624 .class = &omap34xx_mcspi_class,
1625 .dev_attr = &omap_mcspi4_dev_attr,
1626 };
1627
1628 /* usbhsotg */
1629 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1630 .rev_offs = 0x0400,
1631 .sysc_offs = 0x0404,
1632 .syss_offs = 0x0408,
1633 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1634 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1635 SYSC_HAS_AUTOIDLE),
1636 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1637 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1638 .sysc_fields = &omap_hwmod_sysc_type1,
1639 };
1640
1641 static struct omap_hwmod_class usbotg_class = {
1642 .name = "usbotg",
1643 .sysc = &omap3xxx_usbhsotg_sysc,
1644 };
1645
1646 /* usb_otg_hs */
1647 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
1648
1649 { .name = "mc", .irq = 92 },
1650 { .name = "dma", .irq = 93 },
1651 { .irq = -1 }
1652 };
1653
1654 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1655 .name = "usb_otg_hs",
1656 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
1657 .main_clk = "hsotgusb_ick",
1658 .prcm = {
1659 .omap2 = {
1660 .prcm_reg_id = 1,
1661 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1662 .module_offs = CORE_MOD,
1663 .idlest_reg_id = 1,
1664 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1665 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
1666 },
1667 },
1668 .class = &usbotg_class,
1669
1670 /*
1671 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
1672 * broken when autoidle is enabled
1673 * workaround is to disable the autoidle bit at module level.
1674 */
1675 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
1676 | HWMOD_SWSUP_MSTANDBY,
1677 };
1678
1679 /* usb_otg_hs */
1680 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
1681 { .name = "mc", .irq = 71 },
1682 { .irq = -1 }
1683 };
1684
1685 static struct omap_hwmod_class am35xx_usbotg_class = {
1686 .name = "am35xx_usbotg",
1687 };
1688
1689 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1690 .name = "am35x_otg_hs",
1691 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
1692 .main_clk = "hsotgusb_fck",
1693 .class = &am35xx_usbotg_class,
1694 .flags = HWMOD_NO_IDLEST,
1695 };
1696
1697 /* MMC/SD/SDIO common */
1698 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1699 .rev_offs = 0x1fc,
1700 .sysc_offs = 0x10,
1701 .syss_offs = 0x14,
1702 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1703 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1704 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1705 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1706 .sysc_fields = &omap_hwmod_sysc_type1,
1707 };
1708
1709 static struct omap_hwmod_class omap34xx_mmc_class = {
1710 .name = "mmc",
1711 .sysc = &omap34xx_mmc_sysc,
1712 };
1713
1714 /* MMC/SD/SDIO1 */
1715
1716 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
1717 { .irq = 83, },
1718 { .irq = -1 }
1719 };
1720
1721 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
1722 { .name = "tx", .dma_req = 61, },
1723 { .name = "rx", .dma_req = 62, },
1724 { .dma_req = -1 }
1725 };
1726
1727 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1728 { .role = "dbck", .clk = "omap_32k_fck", },
1729 };
1730
1731 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1732 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1733 };
1734
1735 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1736 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
1737 .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1738 OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1739 };
1740
1741 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1742 .name = "mmc1",
1743 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
1744 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
1745 .opt_clks = omap34xx_mmc1_opt_clks,
1746 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1747 .main_clk = "mmchs1_fck",
1748 .prcm = {
1749 .omap2 = {
1750 .module_offs = CORE_MOD,
1751 .prcm_reg_id = 1,
1752 .module_bit = OMAP3430_EN_MMC1_SHIFT,
1753 .idlest_reg_id = 1,
1754 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1755 },
1756 },
1757 .dev_attr = &mmc1_pre_es3_dev_attr,
1758 .class = &omap34xx_mmc_class,
1759 };
1760
1761 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1762 .name = "mmc1",
1763 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
1764 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
1765 .opt_clks = omap34xx_mmc1_opt_clks,
1766 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1767 .main_clk = "mmchs1_fck",
1768 .prcm = {
1769 .omap2 = {
1770 .module_offs = CORE_MOD,
1771 .prcm_reg_id = 1,
1772 .module_bit = OMAP3430_EN_MMC1_SHIFT,
1773 .idlest_reg_id = 1,
1774 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1775 },
1776 },
1777 .dev_attr = &mmc1_dev_attr,
1778 .class = &omap34xx_mmc_class,
1779 };
1780
1781 /* MMC/SD/SDIO2 */
1782
1783 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
1784 { .irq = INT_24XX_MMC2_IRQ, },
1785 { .irq = -1 }
1786 };
1787
1788 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
1789 { .name = "tx", .dma_req = 47, },
1790 { .name = "rx", .dma_req = 48, },
1791 { .dma_req = -1 }
1792 };
1793
1794 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1795 { .role = "dbck", .clk = "omap_32k_fck", },
1796 };
1797
1798 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1799 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
1800 .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1801 };
1802
1803 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1804 .name = "mmc2",
1805 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
1806 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
1807 .opt_clks = omap34xx_mmc2_opt_clks,
1808 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1809 .main_clk = "mmchs2_fck",
1810 .prcm = {
1811 .omap2 = {
1812 .module_offs = CORE_MOD,
1813 .prcm_reg_id = 1,
1814 .module_bit = OMAP3430_EN_MMC2_SHIFT,
1815 .idlest_reg_id = 1,
1816 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1817 },
1818 },
1819 .dev_attr = &mmc2_pre_es3_dev_attr,
1820 .class = &omap34xx_mmc_class,
1821 };
1822
1823 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1824 .name = "mmc2",
1825 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
1826 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
1827 .opt_clks = omap34xx_mmc2_opt_clks,
1828 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1829 .main_clk = "mmchs2_fck",
1830 .prcm = {
1831 .omap2 = {
1832 .module_offs = CORE_MOD,
1833 .prcm_reg_id = 1,
1834 .module_bit = OMAP3430_EN_MMC2_SHIFT,
1835 .idlest_reg_id = 1,
1836 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1837 },
1838 },
1839 .class = &omap34xx_mmc_class,
1840 };
1841
1842 /* MMC/SD/SDIO3 */
1843
1844 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
1845 { .irq = 94, },
1846 { .irq = -1 }
1847 };
1848
1849 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
1850 { .name = "tx", .dma_req = 77, },
1851 { .name = "rx", .dma_req = 78, },
1852 { .dma_req = -1 }
1853 };
1854
1855 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1856 { .role = "dbck", .clk = "omap_32k_fck", },
1857 };
1858
1859 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1860 .name = "mmc3",
1861 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
1862 .sdma_reqs = omap34xx_mmc3_sdma_reqs,
1863 .opt_clks = omap34xx_mmc3_opt_clks,
1864 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1865 .main_clk = "mmchs3_fck",
1866 .prcm = {
1867 .omap2 = {
1868 .prcm_reg_id = 1,
1869 .module_bit = OMAP3430_EN_MMC3_SHIFT,
1870 .idlest_reg_id = 1,
1871 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1872 },
1873 },
1874 .class = &omap34xx_mmc_class,
1875 };
1876
1877 /*
1878 * 'usb_host_hs' class
1879 * high-speed multi-port usb host controller
1880 */
1881
1882 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1883 .rev_offs = 0x0000,
1884 .sysc_offs = 0x0010,
1885 .syss_offs = 0x0014,
1886 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1887 SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1888 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1889 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1890 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1891 .sysc_fields = &omap_hwmod_sysc_type1,
1892 };
1893
1894 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1895 .name = "usb_host_hs",
1896 .sysc = &omap3xxx_usb_host_hs_sysc,
1897 };
1898
1899 static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
1900 { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
1901 };
1902
1903 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
1904 { .name = "ohci-irq", .irq = 76 },
1905 { .name = "ehci-irq", .irq = 77 },
1906 { .irq = -1 }
1907 };
1908
1909 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1910 .name = "usb_host_hs",
1911 .class = &omap3xxx_usb_host_hs_hwmod_class,
1912 .clkdm_name = "l3_init_clkdm",
1913 .mpu_irqs = omap3xxx_usb_host_hs_irqs,
1914 .main_clk = "usbhost_48m_fck",
1915 .prcm = {
1916 .omap2 = {
1917 .module_offs = OMAP3430ES2_USBHOST_MOD,
1918 .prcm_reg_id = 1,
1919 .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
1920 .idlest_reg_id = 1,
1921 .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1922 .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
1923 },
1924 },
1925 .opt_clks = omap3xxx_usb_host_hs_opt_clks,
1926 .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
1927
1928 /*
1929 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1930 * id: i660
1931 *
1932 * Description:
1933 * In the following configuration :
1934 * - USBHOST module is set to smart-idle mode
1935 * - PRCM asserts idle_req to the USBHOST module ( This typically
1936 * happens when the system is going to a low power mode : all ports
1937 * have been suspended, the master part of the USBHOST module has
1938 * entered the standby state, and SW has cut the functional clocks)
1939 * - an USBHOST interrupt occurs before the module is able to answer
1940 * idle_ack, typically a remote wakeup IRQ.
1941 * Then the USB HOST module will enter a deadlock situation where it
1942 * is no more accessible nor functional.
1943 *
1944 * Workaround:
1945 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1946 */
1947
1948 /*
1949 * Errata: USB host EHCI may stall when entering smart-standby mode
1950 * Id: i571
1951 *
1952 * Description:
1953 * When the USBHOST module is set to smart-standby mode, and when it is
1954 * ready to enter the standby state (i.e. all ports are suspended and
1955 * all attached devices are in suspend mode), then it can wrongly assert
1956 * the Mstandby signal too early while there are still some residual OCP
1957 * transactions ongoing. If this condition occurs, the internal state
1958 * machine may go to an undefined state and the USB link may be stuck
1959 * upon the next resume.
1960 *
1961 * Workaround:
1962 * Don't use smart standby; use only force standby,
1963 * hence HWMOD_SWSUP_MSTANDBY
1964 */
1965
1966 /*
1967 * During system boot; If the hwmod framework resets the module
1968 * the module will have smart idle settings; which can lead to deadlock
1969 * (above Errata Id:i660); so, dont reset the module during boot;
1970 * Use HWMOD_INIT_NO_RESET.
1971 */
1972
1973 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
1974 HWMOD_INIT_NO_RESET,
1975 };
1976
1977 /*
1978 * 'usb_tll_hs' class
1979 * usb_tll_hs module is the adapter on the usb_host_hs ports
1980 */
1981 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
1982 .rev_offs = 0x0000,
1983 .sysc_offs = 0x0010,
1984 .syss_offs = 0x0014,
1985 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1986 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1987 SYSC_HAS_AUTOIDLE),
1988 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1989 .sysc_fields = &omap_hwmod_sysc_type1,
1990 };
1991
1992 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
1993 .name = "usb_tll_hs",
1994 .sysc = &omap3xxx_usb_tll_hs_sysc,
1995 };
1996
1997 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
1998 { .name = "tll-irq", .irq = 78 },
1999 { .irq = -1 }
2000 };
2001
2002 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
2003 .name = "usb_tll_hs",
2004 .class = &omap3xxx_usb_tll_hs_hwmod_class,
2005 .clkdm_name = "l3_init_clkdm",
2006 .mpu_irqs = omap3xxx_usb_tll_hs_irqs,
2007 .main_clk = "usbtll_fck",
2008 .prcm = {
2009 .omap2 = {
2010 .module_offs = CORE_MOD,
2011 .prcm_reg_id = 3,
2012 .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
2013 .idlest_reg_id = 3,
2014 .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
2015 },
2016 },
2017 };
2018
2019 static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
2020 .name = "hdq1w",
2021 .mpu_irqs = omap2_hdq1w_mpu_irqs,
2022 .main_clk = "hdq_fck",
2023 .prcm = {
2024 .omap2 = {
2025 .module_offs = CORE_MOD,
2026 .prcm_reg_id = 1,
2027 .module_bit = OMAP3430_EN_HDQ_SHIFT,
2028 .idlest_reg_id = 1,
2029 .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
2030 },
2031 },
2032 .class = &omap2_hdq1w_class,
2033 };
2034
2035 /*
2036 * '32K sync counter' class
2037 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
2038 */
2039 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
2040 .rev_offs = 0x0000,
2041 .sysc_offs = 0x0004,
2042 .sysc_flags = SYSC_HAS_SIDLEMODE,
2043 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
2044 .sysc_fields = &omap_hwmod_sysc_type1,
2045 };
2046
2047 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
2048 .name = "counter",
2049 .sysc = &omap3xxx_counter_sysc,
2050 };
2051
2052 static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
2053 .name = "counter_32k",
2054 .class = &omap3xxx_counter_hwmod_class,
2055 .clkdm_name = "wkup_clkdm",
2056 .flags = HWMOD_SWSUP_SIDLE,
2057 .main_clk = "wkup_32k_fck",
2058 .prcm = {
2059 .omap2 = {
2060 .module_offs = WKUP_MOD,
2061 .prcm_reg_id = 1,
2062 .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
2063 .idlest_reg_id = 1,
2064 .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
2065 },
2066 },
2067 };
2068
2069 /*
2070 * interfaces
2071 */
2072
2073 /* L3 -> L4_CORE interface */
2074 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
2075 .master = &omap3xxx_l3_main_hwmod,
2076 .slave = &omap3xxx_l4_core_hwmod,
2077 .user = OCP_USER_MPU | OCP_USER_SDMA,
2078 };
2079
2080 /* L3 -> L4_PER interface */
2081 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
2082 .master = &omap3xxx_l3_main_hwmod,
2083 .slave = &omap3xxx_l4_per_hwmod,
2084 .user = OCP_USER_MPU | OCP_USER_SDMA,
2085 };
2086
2087 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
2088 {
2089 .pa_start = 0x68000000,
2090 .pa_end = 0x6800ffff,
2091 .flags = ADDR_TYPE_RT,
2092 },
2093 { }
2094 };
2095
2096 /* MPU -> L3 interface */
2097 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
2098 .master = &omap3xxx_mpu_hwmod,
2099 .slave = &omap3xxx_l3_main_hwmod,
2100 .addr = omap3xxx_l3_main_addrs,
2101 .user = OCP_USER_MPU,
2102 };
2103
2104 /* DSS -> l3 */
2105 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
2106 .master = &omap3430es1_dss_core_hwmod,
2107 .slave = &omap3xxx_l3_main_hwmod,
2108 .user = OCP_USER_MPU | OCP_USER_SDMA,
2109 };
2110
2111 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
2112 .master = &omap3xxx_dss_core_hwmod,
2113 .slave = &omap3xxx_l3_main_hwmod,
2114 .fw = {
2115 .omap2 = {
2116 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
2117 .flags = OMAP_FIREWALL_L3,
2118 }
2119 },
2120 .user = OCP_USER_MPU | OCP_USER_SDMA,
2121 };
2122
2123 /* l3_core -> usbhsotg interface */
2124 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
2125 .master = &omap3xxx_usbhsotg_hwmod,
2126 .slave = &omap3xxx_l3_main_hwmod,
2127 .clk = "core_l3_ick",
2128 .user = OCP_USER_MPU,
2129 };
2130
2131 /* l3_core -> am35xx_usbhsotg interface */
2132 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
2133 .master = &am35xx_usbhsotg_hwmod,
2134 .slave = &omap3xxx_l3_main_hwmod,
2135 .clk = "hsotgusb_ick",
2136 .user = OCP_USER_MPU,
2137 };
2138
2139 /* L4_CORE -> L4_WKUP interface */
2140 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
2141 .master = &omap3xxx_l4_core_hwmod,
2142 .slave = &omap3xxx_l4_wkup_hwmod,
2143 .user = OCP_USER_MPU | OCP_USER_SDMA,
2144 };
2145
2146 /* L4 CORE -> MMC1 interface */
2147 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
2148 .master = &omap3xxx_l4_core_hwmod,
2149 .slave = &omap3xxx_pre_es3_mmc1_hwmod,
2150 .clk = "mmchs1_ick",
2151 .addr = omap2430_mmc1_addr_space,
2152 .user = OCP_USER_MPU | OCP_USER_SDMA,
2153 .flags = OMAP_FIREWALL_L4
2154 };
2155
2156 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
2157 .master = &omap3xxx_l4_core_hwmod,
2158 .slave = &omap3xxx_es3plus_mmc1_hwmod,
2159 .clk = "mmchs1_ick",
2160 .addr = omap2430_mmc1_addr_space,
2161 .user = OCP_USER_MPU | OCP_USER_SDMA,
2162 .flags = OMAP_FIREWALL_L4
2163 };
2164
2165 /* L4 CORE -> MMC2 interface */
2166 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
2167 .master = &omap3xxx_l4_core_hwmod,
2168 .slave = &omap3xxx_pre_es3_mmc2_hwmod,
2169 .clk = "mmchs2_ick",
2170 .addr = omap2430_mmc2_addr_space,
2171 .user = OCP_USER_MPU | OCP_USER_SDMA,
2172 .flags = OMAP_FIREWALL_L4
2173 };
2174
2175 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2176 .master = &omap3xxx_l4_core_hwmod,
2177 .slave = &omap3xxx_es3plus_mmc2_hwmod,
2178 .clk = "mmchs2_ick",
2179 .addr = omap2430_mmc2_addr_space,
2180 .user = OCP_USER_MPU | OCP_USER_SDMA,
2181 .flags = OMAP_FIREWALL_L4
2182 };
2183
2184 /* L4 CORE -> MMC3 interface */
2185 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
2186 {
2187 .pa_start = 0x480ad000,
2188 .pa_end = 0x480ad1ff,
2189 .flags = ADDR_TYPE_RT,
2190 },
2191 { }
2192 };
2193
2194 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2195 .master = &omap3xxx_l4_core_hwmod,
2196 .slave = &omap3xxx_mmc3_hwmod,
2197 .clk = "mmchs3_ick",
2198 .addr = omap3xxx_mmc3_addr_space,
2199 .user = OCP_USER_MPU | OCP_USER_SDMA,
2200 .flags = OMAP_FIREWALL_L4
2201 };
2202
2203 /* L4 CORE -> UART1 interface */
2204 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
2205 {
2206 .pa_start = OMAP3_UART1_BASE,
2207 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
2208 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2209 },
2210 { }
2211 };
2212
2213 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2214 .master = &omap3xxx_l4_core_hwmod,
2215 .slave = &omap3xxx_uart1_hwmod,
2216 .clk = "uart1_ick",
2217 .addr = omap3xxx_uart1_addr_space,
2218 .user = OCP_USER_MPU | OCP_USER_SDMA,
2219 };
2220
2221 /* L4 CORE -> UART2 interface */
2222 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
2223 {
2224 .pa_start = OMAP3_UART2_BASE,
2225 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
2226 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2227 },
2228 { }
2229 };
2230
2231 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2232 .master = &omap3xxx_l4_core_hwmod,
2233 .slave = &omap3xxx_uart2_hwmod,
2234 .clk = "uart2_ick",
2235 .addr = omap3xxx_uart2_addr_space,
2236 .user = OCP_USER_MPU | OCP_USER_SDMA,
2237 };
2238
2239 /* L4 PER -> UART3 interface */
2240 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
2241 {
2242 .pa_start = OMAP3_UART3_BASE,
2243 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
2244 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2245 },
2246 { }
2247 };
2248
2249 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2250 .master = &omap3xxx_l4_per_hwmod,
2251 .slave = &omap3xxx_uart3_hwmod,
2252 .clk = "uart3_ick",
2253 .addr = omap3xxx_uart3_addr_space,
2254 .user = OCP_USER_MPU | OCP_USER_SDMA,
2255 };
2256
2257 /* L4 PER -> UART4 interface */
2258 static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
2259 {
2260 .pa_start = OMAP3_UART4_BASE,
2261 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
2262 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2263 },
2264 { }
2265 };
2266
2267 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2268 .master = &omap3xxx_l4_per_hwmod,
2269 .slave = &omap36xx_uart4_hwmod,
2270 .clk = "uart4_ick",
2271 .addr = omap36xx_uart4_addr_space,
2272 .user = OCP_USER_MPU | OCP_USER_SDMA,
2273 };
2274
2275 /* AM35xx: L4 CORE -> UART4 interface */
2276 static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
2277 {
2278 .pa_start = OMAP3_UART4_AM35XX_BASE,
2279 .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
2280 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2281 },
2282 { }
2283 };
2284
2285 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2286 .master = &omap3xxx_l4_core_hwmod,
2287 .slave = &am35xx_uart4_hwmod,
2288 .clk = "uart4_ick",
2289 .addr = am35xx_uart4_addr_space,
2290 .user = OCP_USER_MPU | OCP_USER_SDMA,
2291 };
2292
2293 /* L4 CORE -> I2C1 interface */
2294 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2295 .master = &omap3xxx_l4_core_hwmod,
2296 .slave = &omap3xxx_i2c1_hwmod,
2297 .clk = "i2c1_ick",
2298 .addr = omap2_i2c1_addr_space,
2299 .fw = {
2300 .omap2 = {
2301 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
2302 .l4_prot_group = 7,
2303 .flags = OMAP_FIREWALL_L4,
2304 }
2305 },
2306 .user = OCP_USER_MPU | OCP_USER_SDMA,
2307 };
2308
2309 /* L4 CORE -> I2C2 interface */
2310 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2311 .master = &omap3xxx_l4_core_hwmod,
2312 .slave = &omap3xxx_i2c2_hwmod,
2313 .clk = "i2c2_ick",
2314 .addr = omap2_i2c2_addr_space,
2315 .fw = {
2316 .omap2 = {
2317 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
2318 .l4_prot_group = 7,
2319 .flags = OMAP_FIREWALL_L4,
2320 }
2321 },
2322 .user = OCP_USER_MPU | OCP_USER_SDMA,
2323 };
2324
2325 /* L4 CORE -> I2C3 interface */
2326 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
2327 {
2328 .pa_start = 0x48060000,
2329 .pa_end = 0x48060000 + SZ_128 - 1,
2330 .flags = ADDR_TYPE_RT,
2331 },
2332 { }
2333 };
2334
2335 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2336 .master = &omap3xxx_l4_core_hwmod,
2337 .slave = &omap3xxx_i2c3_hwmod,
2338 .clk = "i2c3_ick",
2339 .addr = omap3xxx_i2c3_addr_space,
2340 .fw = {
2341 .omap2 = {
2342 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
2343 .l4_prot_group = 7,
2344 .flags = OMAP_FIREWALL_L4,
2345 }
2346 },
2347 .user = OCP_USER_MPU | OCP_USER_SDMA,
2348 };
2349
2350 /* L4 CORE -> SR1 interface */
2351 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
2352 {
2353 .pa_start = OMAP34XX_SR1_BASE,
2354 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
2355 .flags = ADDR_TYPE_RT,
2356 },
2357 { }
2358 };
2359
2360 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2361 .master = &omap3xxx_l4_core_hwmod,
2362 .slave = &omap34xx_sr1_hwmod,
2363 .clk = "sr_l4_ick",
2364 .addr = omap3_sr1_addr_space,
2365 .user = OCP_USER_MPU,
2366 };
2367
2368 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2369 .master = &omap3xxx_l4_core_hwmod,
2370 .slave = &omap36xx_sr1_hwmod,
2371 .clk = "sr_l4_ick",
2372 .addr = omap3_sr1_addr_space,
2373 .user = OCP_USER_MPU,
2374 };
2375
2376 /* L4 CORE -> SR1 interface */
2377 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
2378 {
2379 .pa_start = OMAP34XX_SR2_BASE,
2380 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
2381 .flags = ADDR_TYPE_RT,
2382 },
2383 { }
2384 };
2385
2386 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2387 .master = &omap3xxx_l4_core_hwmod,
2388 .slave = &omap34xx_sr2_hwmod,
2389 .clk = "sr_l4_ick",
2390 .addr = omap3_sr2_addr_space,
2391 .user = OCP_USER_MPU,
2392 };
2393
2394 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2395 .master = &omap3xxx_l4_core_hwmod,
2396 .slave = &omap36xx_sr2_hwmod,
2397 .clk = "sr_l4_ick",
2398 .addr = omap3_sr2_addr_space,
2399 .user = OCP_USER_MPU,
2400 };
2401
2402 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
2403 {
2404 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
2405 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
2406 .flags = ADDR_TYPE_RT
2407 },
2408 { }
2409 };
2410
2411 /* l4_core -> usbhsotg */
2412 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2413 .master = &omap3xxx_l4_core_hwmod,
2414 .slave = &omap3xxx_usbhsotg_hwmod,
2415 .clk = "l4_ick",
2416 .addr = omap3xxx_usbhsotg_addrs,
2417 .user = OCP_USER_MPU,
2418 };
2419
2420 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
2421 {
2422 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
2423 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
2424 .flags = ADDR_TYPE_RT
2425 },
2426 { }
2427 };
2428
2429 /* l4_core -> usbhsotg */
2430 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2431 .master = &omap3xxx_l4_core_hwmod,
2432 .slave = &am35xx_usbhsotg_hwmod,
2433 .clk = "hsotgusb_ick",
2434 .addr = am35xx_usbhsotg_addrs,
2435 .user = OCP_USER_MPU,
2436 };
2437
2438 /* L4_WKUP -> L4_SEC interface */
2439 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2440 .master = &omap3xxx_l4_wkup_hwmod,
2441 .slave = &omap3xxx_l4_sec_hwmod,
2442 .user = OCP_USER_MPU | OCP_USER_SDMA,
2443 };
2444
2445 /* IVA2 <- L3 interface */
2446 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2447 .master = &omap3xxx_l3_main_hwmod,
2448 .slave = &omap3xxx_iva_hwmod,
2449 .clk = "core_l3_ick",
2450 .user = OCP_USER_MPU | OCP_USER_SDMA,
2451 };
2452
2453 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
2454 {
2455 .pa_start = 0x48318000,
2456 .pa_end = 0x48318000 + SZ_1K - 1,
2457 .flags = ADDR_TYPE_RT
2458 },
2459 { }
2460 };
2461
2462 /* l4_wkup -> timer1 */
2463 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2464 .master = &omap3xxx_l4_wkup_hwmod,
2465 .slave = &omap3xxx_timer1_hwmod,
2466 .clk = "gpt1_ick",
2467 .addr = omap3xxx_timer1_addrs,
2468 .user = OCP_USER_MPU | OCP_USER_SDMA,
2469 };
2470
2471 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
2472 {
2473 .pa_start = 0x49032000,
2474 .pa_end = 0x49032000 + SZ_1K - 1,
2475 .flags = ADDR_TYPE_RT
2476 },
2477 { }
2478 };
2479
2480 /* l4_per -> timer2 */
2481 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2482 .master = &omap3xxx_l4_per_hwmod,
2483 .slave = &omap3xxx_timer2_hwmod,
2484 .clk = "gpt2_ick",
2485 .addr = omap3xxx_timer2_addrs,
2486 .user = OCP_USER_MPU | OCP_USER_SDMA,
2487 };
2488
2489 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
2490 {
2491 .pa_start = 0x49034000,
2492 .pa_end = 0x49034000 + SZ_1K - 1,
2493 .flags = ADDR_TYPE_RT
2494 },
2495 { }
2496 };
2497
2498 /* l4_per -> timer3 */
2499 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2500 .master = &omap3xxx_l4_per_hwmod,
2501 .slave = &omap3xxx_timer3_hwmod,
2502 .clk = "gpt3_ick",
2503 .addr = omap3xxx_timer3_addrs,
2504 .user = OCP_USER_MPU | OCP_USER_SDMA,
2505 };
2506
2507 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
2508 {
2509 .pa_start = 0x49036000,
2510 .pa_end = 0x49036000 + SZ_1K - 1,
2511 .flags = ADDR_TYPE_RT
2512 },
2513 { }
2514 };
2515
2516 /* l4_per -> timer4 */
2517 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2518 .master = &omap3xxx_l4_per_hwmod,
2519 .slave = &omap3xxx_timer4_hwmod,
2520 .clk = "gpt4_ick",
2521 .addr = omap3xxx_timer4_addrs,
2522 .user = OCP_USER_MPU | OCP_USER_SDMA,
2523 };
2524
2525 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
2526 {
2527 .pa_start = 0x49038000,
2528 .pa_end = 0x49038000 + SZ_1K - 1,
2529 .flags = ADDR_TYPE_RT
2530 },
2531 { }
2532 };
2533
2534 /* l4_per -> timer5 */
2535 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2536 .master = &omap3xxx_l4_per_hwmod,
2537 .slave = &omap3xxx_timer5_hwmod,
2538 .clk = "gpt5_ick",
2539 .addr = omap3xxx_timer5_addrs,
2540 .user = OCP_USER_MPU | OCP_USER_SDMA,
2541 };
2542
2543 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
2544 {
2545 .pa_start = 0x4903A000,
2546 .pa_end = 0x4903A000 + SZ_1K - 1,
2547 .flags = ADDR_TYPE_RT
2548 },
2549 { }
2550 };
2551
2552 /* l4_per -> timer6 */
2553 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2554 .master = &omap3xxx_l4_per_hwmod,
2555 .slave = &omap3xxx_timer6_hwmod,
2556 .clk = "gpt6_ick",
2557 .addr = omap3xxx_timer6_addrs,
2558 .user = OCP_USER_MPU | OCP_USER_SDMA,
2559 };
2560
2561 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
2562 {
2563 .pa_start = 0x4903C000,
2564 .pa_end = 0x4903C000 + SZ_1K - 1,
2565 .flags = ADDR_TYPE_RT
2566 },
2567 { }
2568 };
2569
2570 /* l4_per -> timer7 */
2571 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2572 .master = &omap3xxx_l4_per_hwmod,
2573 .slave = &omap3xxx_timer7_hwmod,
2574 .clk = "gpt7_ick",
2575 .addr = omap3xxx_timer7_addrs,
2576 .user = OCP_USER_MPU | OCP_USER_SDMA,
2577 };
2578
2579 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
2580 {
2581 .pa_start = 0x4903E000,
2582 .pa_end = 0x4903E000 + SZ_1K - 1,
2583 .flags = ADDR_TYPE_RT
2584 },
2585 { }
2586 };
2587
2588 /* l4_per -> timer8 */
2589 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2590 .master = &omap3xxx_l4_per_hwmod,
2591 .slave = &omap3xxx_timer8_hwmod,
2592 .clk = "gpt8_ick",
2593 .addr = omap3xxx_timer8_addrs,
2594 .user = OCP_USER_MPU | OCP_USER_SDMA,
2595 };
2596
2597 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
2598 {
2599 .pa_start = 0x49040000,
2600 .pa_end = 0x49040000 + SZ_1K - 1,
2601 .flags = ADDR_TYPE_RT
2602 },
2603 { }
2604 };
2605
2606 /* l4_per -> timer9 */
2607 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2608 .master = &omap3xxx_l4_per_hwmod,
2609 .slave = &omap3xxx_timer9_hwmod,
2610 .clk = "gpt9_ick",
2611 .addr = omap3xxx_timer9_addrs,
2612 .user = OCP_USER_MPU | OCP_USER_SDMA,
2613 };
2614
2615 /* l4_core -> timer10 */
2616 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2617 .master = &omap3xxx_l4_core_hwmod,
2618 .slave = &omap3xxx_timer10_hwmod,
2619 .clk = "gpt10_ick",
2620 .addr = omap2_timer10_addrs,
2621 .user = OCP_USER_MPU | OCP_USER_SDMA,
2622 };
2623
2624 /* l4_core -> timer11 */
2625 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2626 .master = &omap3xxx_l4_core_hwmod,
2627 .slave = &omap3xxx_timer11_hwmod,
2628 .clk = "gpt11_ick",
2629 .addr = omap2_timer11_addrs,
2630 .user = OCP_USER_MPU | OCP_USER_SDMA,
2631 };
2632
2633 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
2634 {
2635 .pa_start = 0x48304000,
2636 .pa_end = 0x48304000 + SZ_1K - 1,
2637 .flags = ADDR_TYPE_RT
2638 },
2639 { }
2640 };
2641
2642 /* l4_core -> timer12 */
2643 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2644 .master = &omap3xxx_l4_sec_hwmod,
2645 .slave = &omap3xxx_timer12_hwmod,
2646 .clk = "gpt12_ick",
2647 .addr = omap3xxx_timer12_addrs,
2648 .user = OCP_USER_MPU | OCP_USER_SDMA,
2649 };
2650
2651 /* l4_wkup -> wd_timer2 */
2652 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
2653 {
2654 .pa_start = 0x48314000,
2655 .pa_end = 0x4831407f,
2656 .flags = ADDR_TYPE_RT
2657 },
2658 { }
2659 };
2660
2661 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2662 .master = &omap3xxx_l4_wkup_hwmod,
2663 .slave = &omap3xxx_wd_timer2_hwmod,
2664 .clk = "wdt2_ick",
2665 .addr = omap3xxx_wd_timer2_addrs,
2666 .user = OCP_USER_MPU | OCP_USER_SDMA,
2667 };
2668
2669 /* l4_core -> dss */
2670 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2671 .master = &omap3xxx_l4_core_hwmod,
2672 .slave = &omap3430es1_dss_core_hwmod,
2673 .clk = "dss_ick",
2674 .addr = omap2_dss_addrs,
2675 .fw = {
2676 .omap2 = {
2677 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2678 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2679 .flags = OMAP_FIREWALL_L4,
2680 }
2681 },
2682 .user = OCP_USER_MPU | OCP_USER_SDMA,
2683 };
2684
2685 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2686 .master = &omap3xxx_l4_core_hwmod,
2687 .slave = &omap3xxx_dss_core_hwmod,
2688 .clk = "dss_ick",
2689 .addr = omap2_dss_addrs,
2690 .fw = {
2691 .omap2 = {
2692 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2693 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2694 .flags = OMAP_FIREWALL_L4,
2695 }
2696 },
2697 .user = OCP_USER_MPU | OCP_USER_SDMA,
2698 };
2699
2700 /* l4_core -> dss_dispc */
2701 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2702 .master = &omap3xxx_l4_core_hwmod,
2703 .slave = &omap3xxx_dss_dispc_hwmod,
2704 .clk = "dss_ick",
2705 .addr = omap2_dss_dispc_addrs,
2706 .fw = {
2707 .omap2 = {
2708 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2709 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2710 .flags = OMAP_FIREWALL_L4,
2711 }
2712 },
2713 .user = OCP_USER_MPU | OCP_USER_SDMA,
2714 };
2715
2716 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
2717 {
2718 .pa_start = 0x4804FC00,
2719 .pa_end = 0x4804FFFF,
2720 .flags = ADDR_TYPE_RT
2721 },
2722 { }
2723 };
2724
2725 /* l4_core -> dss_dsi1 */
2726 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2727 .master = &omap3xxx_l4_core_hwmod,
2728 .slave = &omap3xxx_dss_dsi1_hwmod,
2729 .clk = "dss_ick",
2730 .addr = omap3xxx_dss_dsi1_addrs,
2731 .fw = {
2732 .omap2 = {
2733 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2734 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2735 .flags = OMAP_FIREWALL_L4,
2736 }
2737 },
2738 .user = OCP_USER_MPU | OCP_USER_SDMA,
2739 };
2740
2741 /* l4_core -> dss_rfbi */
2742 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2743 .master = &omap3xxx_l4_core_hwmod,
2744 .slave = &omap3xxx_dss_rfbi_hwmod,
2745 .clk = "dss_ick",
2746 .addr = omap2_dss_rfbi_addrs,
2747 .fw = {
2748 .omap2 = {
2749 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2750 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2751 .flags = OMAP_FIREWALL_L4,
2752 }
2753 },
2754 .user = OCP_USER_MPU | OCP_USER_SDMA,
2755 };
2756
2757 /* l4_core -> dss_venc */
2758 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2759 .master = &omap3xxx_l4_core_hwmod,
2760 .slave = &omap3xxx_dss_venc_hwmod,
2761 .clk = "dss_ick",
2762 .addr = omap2_dss_venc_addrs,
2763 .fw = {
2764 .omap2 = {
2765 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2766 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2767 .flags = OMAP_FIREWALL_L4,
2768 }
2769 },
2770 .flags = OCPIF_SWSUP_IDLE,
2771 .user = OCP_USER_MPU | OCP_USER_SDMA,
2772 };
2773
2774 /* l4_wkup -> gpio1 */
2775 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2776 {
2777 .pa_start = 0x48310000,
2778 .pa_end = 0x483101ff,
2779 .flags = ADDR_TYPE_RT
2780 },
2781 { }
2782 };
2783
2784 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2785 .master = &omap3xxx_l4_wkup_hwmod,
2786 .slave = &omap3xxx_gpio1_hwmod,
2787 .addr = omap3xxx_gpio1_addrs,
2788 .user = OCP_USER_MPU | OCP_USER_SDMA,
2789 };
2790
2791 /* l4_per -> gpio2 */
2792 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2793 {
2794 .pa_start = 0x49050000,
2795 .pa_end = 0x490501ff,
2796 .flags = ADDR_TYPE_RT
2797 },
2798 { }
2799 };
2800
2801 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2802 .master = &omap3xxx_l4_per_hwmod,
2803 .slave = &omap3xxx_gpio2_hwmod,
2804 .addr = omap3xxx_gpio2_addrs,
2805 .user = OCP_USER_MPU | OCP_USER_SDMA,
2806 };
2807
2808 /* l4_per -> gpio3 */
2809 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2810 {
2811 .pa_start = 0x49052000,
2812 .pa_end = 0x490521ff,
2813 .flags = ADDR_TYPE_RT
2814 },
2815 { }
2816 };
2817
2818 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2819 .master = &omap3xxx_l4_per_hwmod,
2820 .slave = &omap3xxx_gpio3_hwmod,
2821 .addr = omap3xxx_gpio3_addrs,
2822 .user = OCP_USER_MPU | OCP_USER_SDMA,
2823 };
2824
2825 /* l4_per -> gpio4 */
2826 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
2827 {
2828 .pa_start = 0x49054000,
2829 .pa_end = 0x490541ff,
2830 .flags = ADDR_TYPE_RT
2831 },
2832 { }
2833 };
2834
2835 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
2836 .master = &omap3xxx_l4_per_hwmod,
2837 .slave = &omap3xxx_gpio4_hwmod,
2838 .addr = omap3xxx_gpio4_addrs,
2839 .user = OCP_USER_MPU | OCP_USER_SDMA,
2840 };
2841
2842 /* l4_per -> gpio5 */
2843 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
2844 {
2845 .pa_start = 0x49056000,
2846 .pa_end = 0x490561ff,
2847 .flags = ADDR_TYPE_RT
2848 },
2849 { }
2850 };
2851
2852 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
2853 .master = &omap3xxx_l4_per_hwmod,
2854 .slave = &omap3xxx_gpio5_hwmod,
2855 .addr = omap3xxx_gpio5_addrs,
2856 .user = OCP_USER_MPU | OCP_USER_SDMA,
2857 };
2858
2859 /* l4_per -> gpio6 */
2860 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
2861 {
2862 .pa_start = 0x49058000,
2863 .pa_end = 0x490581ff,
2864 .flags = ADDR_TYPE_RT
2865 },
2866 { }
2867 };
2868
2869 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
2870 .master = &omap3xxx_l4_per_hwmod,
2871 .slave = &omap3xxx_gpio6_hwmod,
2872 .addr = omap3xxx_gpio6_addrs,
2873 .user = OCP_USER_MPU | OCP_USER_SDMA,
2874 };
2875
2876 /* dma_system -> L3 */
2877 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2878 .master = &omap3xxx_dma_system_hwmod,
2879 .slave = &omap3xxx_l3_main_hwmod,
2880 .clk = "core_l3_ick",
2881 .user = OCP_USER_MPU | OCP_USER_SDMA,
2882 };
2883
2884 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2885 {
2886 .pa_start = 0x48056000,
2887 .pa_end = 0x48056fff,
2888 .flags = ADDR_TYPE_RT
2889 },
2890 { }
2891 };
2892
2893 /* l4_cfg -> dma_system */
2894 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2895 .master = &omap3xxx_l4_core_hwmod,
2896 .slave = &omap3xxx_dma_system_hwmod,
2897 .clk = "core_l4_ick",
2898 .addr = omap3xxx_dma_system_addrs,
2899 .user = OCP_USER_MPU | OCP_USER_SDMA,
2900 };
2901
2902 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2903 {
2904 .name = "mpu",
2905 .pa_start = 0x48074000,
2906 .pa_end = 0x480740ff,
2907 .flags = ADDR_TYPE_RT
2908 },
2909 { }
2910 };
2911
2912 /* l4_core -> mcbsp1 */
2913 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2914 .master = &omap3xxx_l4_core_hwmod,
2915 .slave = &omap3xxx_mcbsp1_hwmod,
2916 .clk = "mcbsp1_ick",
2917 .addr = omap3xxx_mcbsp1_addrs,
2918 .user = OCP_USER_MPU | OCP_USER_SDMA,
2919 };
2920
2921 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2922 {
2923 .name = "mpu",
2924 .pa_start = 0x49022000,
2925 .pa_end = 0x490220ff,
2926 .flags = ADDR_TYPE_RT
2927 },
2928 { }
2929 };
2930
2931 /* l4_per -> mcbsp2 */
2932 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2933 .master = &omap3xxx_l4_per_hwmod,
2934 .slave = &omap3xxx_mcbsp2_hwmod,
2935 .clk = "mcbsp2_ick",
2936 .addr = omap3xxx_mcbsp2_addrs,
2937 .user = OCP_USER_MPU | OCP_USER_SDMA,
2938 };
2939
2940 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2941 {
2942 .name = "mpu",
2943 .pa_start = 0x49024000,
2944 .pa_end = 0x490240ff,
2945 .flags = ADDR_TYPE_RT
2946 },
2947 { }
2948 };
2949
2950 /* l4_per -> mcbsp3 */
2951 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2952 .master = &omap3xxx_l4_per_hwmod,
2953 .slave = &omap3xxx_mcbsp3_hwmod,
2954 .clk = "mcbsp3_ick",
2955 .addr = omap3xxx_mcbsp3_addrs,
2956 .user = OCP_USER_MPU | OCP_USER_SDMA,
2957 };
2958
2959 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2960 {
2961 .name = "mpu",
2962 .pa_start = 0x49026000,
2963 .pa_end = 0x490260ff,
2964 .flags = ADDR_TYPE_RT
2965 },
2966 { }
2967 };
2968
2969 /* l4_per -> mcbsp4 */
2970 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2971 .master = &omap3xxx_l4_per_hwmod,
2972 .slave = &omap3xxx_mcbsp4_hwmod,
2973 .clk = "mcbsp4_ick",
2974 .addr = omap3xxx_mcbsp4_addrs,
2975 .user = OCP_USER_MPU | OCP_USER_SDMA,
2976 };
2977
2978 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2979 {
2980 .name = "mpu",
2981 .pa_start = 0x48096000,
2982 .pa_end = 0x480960ff,
2983 .flags = ADDR_TYPE_RT
2984 },
2985 { }
2986 };
2987
2988 /* l4_core -> mcbsp5 */
2989 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2990 .master = &omap3xxx_l4_core_hwmod,
2991 .slave = &omap3xxx_mcbsp5_hwmod,
2992 .clk = "mcbsp5_ick",
2993 .addr = omap3xxx_mcbsp5_addrs,
2994 .user = OCP_USER_MPU | OCP_USER_SDMA,
2995 };
2996
2997 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2998 {
2999 .name = "sidetone",
3000 .pa_start = 0x49028000,
3001 .pa_end = 0x490280ff,
3002 .flags = ADDR_TYPE_RT
3003 },
3004 { }
3005 };
3006
3007 /* l4_per -> mcbsp2_sidetone */
3008 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
3009 .master = &omap3xxx_l4_per_hwmod,
3010 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
3011 .clk = "mcbsp2_ick",
3012 .addr = omap3xxx_mcbsp2_sidetone_addrs,
3013 .user = OCP_USER_MPU,
3014 };
3015
3016 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
3017 {
3018 .name = "sidetone",
3019 .pa_start = 0x4902A000,
3020 .pa_end = 0x4902A0ff,
3021 .flags = ADDR_TYPE_RT
3022 },
3023 { }
3024 };
3025
3026 /* l4_per -> mcbsp3_sidetone */
3027 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
3028 .master = &omap3xxx_l4_per_hwmod,
3029 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
3030 .clk = "mcbsp3_ick",
3031 .addr = omap3xxx_mcbsp3_sidetone_addrs,
3032 .user = OCP_USER_MPU,
3033 };
3034
3035 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
3036 {
3037 .pa_start = 0x48094000,
3038 .pa_end = 0x480941ff,
3039 .flags = ADDR_TYPE_RT,
3040 },
3041 { }
3042 };
3043
3044 /* l4_core -> mailbox */
3045 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3046 .master = &omap3xxx_l4_core_hwmod,
3047 .slave = &omap3xxx_mailbox_hwmod,
3048 .addr = omap3xxx_mailbox_addrs,
3049 .user = OCP_USER_MPU | OCP_USER_SDMA,
3050 };
3051
3052 /* l4 core -> mcspi1 interface */
3053 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3054 .master = &omap3xxx_l4_core_hwmod,
3055 .slave = &omap34xx_mcspi1,
3056 .clk = "mcspi1_ick",
3057 .addr = omap2_mcspi1_addr_space,
3058 .user = OCP_USER_MPU | OCP_USER_SDMA,
3059 };
3060
3061 /* l4 core -> mcspi2 interface */
3062 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3063 .master = &omap3xxx_l4_core_hwmod,
3064 .slave = &omap34xx_mcspi2,
3065 .clk = "mcspi2_ick",
3066 .addr = omap2_mcspi2_addr_space,
3067 .user = OCP_USER_MPU | OCP_USER_SDMA,
3068 };
3069
3070 /* l4 core -> mcspi3 interface */
3071 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3072 .master = &omap3xxx_l4_core_hwmod,
3073 .slave = &omap34xx_mcspi3,
3074 .clk = "mcspi3_ick",
3075 .addr = omap2430_mcspi3_addr_space,
3076 .user = OCP_USER_MPU | OCP_USER_SDMA,
3077 };
3078
3079 /* l4 core -> mcspi4 interface */
3080 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3081 {
3082 .pa_start = 0x480ba000,
3083 .pa_end = 0x480ba0ff,
3084 .flags = ADDR_TYPE_RT,
3085 },
3086 { }
3087 };
3088
3089 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3090 .master = &omap3xxx_l4_core_hwmod,
3091 .slave = &omap34xx_mcspi4,
3092 .clk = "mcspi4_ick",
3093 .addr = omap34xx_mcspi4_addr_space,
3094 .user = OCP_USER_MPU | OCP_USER_SDMA,
3095 };
3096
3097 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3098 .master = &omap3xxx_usb_host_hs_hwmod,
3099 .slave = &omap3xxx_l3_main_hwmod,
3100 .clk = "core_l3_ick",
3101 .user = OCP_USER_MPU,
3102 };
3103
3104 static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3105 {
3106 .name = "uhh",
3107 .pa_start = 0x48064000,
3108 .pa_end = 0x480643ff,
3109 .flags = ADDR_TYPE_RT
3110 },
3111 {
3112 .name = "ohci",
3113 .pa_start = 0x48064400,
3114 .pa_end = 0x480647ff,
3115 },
3116 {
3117 .name = "ehci",
3118 .pa_start = 0x48064800,
3119 .pa_end = 0x48064cff,
3120 },
3121 {}
3122 };
3123
3124 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3125 .master = &omap3xxx_l4_core_hwmod,
3126 .slave = &omap3xxx_usb_host_hs_hwmod,
3127 .clk = "usbhost_ick",
3128 .addr = omap3xxx_usb_host_hs_addrs,
3129 .user = OCP_USER_MPU | OCP_USER_SDMA,
3130 };
3131
3132 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3133 {
3134 .name = "tll",
3135 .pa_start = 0x48062000,
3136 .pa_end = 0x48062fff,
3137 .flags = ADDR_TYPE_RT
3138 },
3139 {}
3140 };
3141
3142 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3143 .master = &omap3xxx_l4_core_hwmod,
3144 .slave = &omap3xxx_usb_tll_hs_hwmod,
3145 .clk = "usbtll_ick",
3146 .addr = omap3xxx_usb_tll_hs_addrs,
3147 .user = OCP_USER_MPU | OCP_USER_SDMA,
3148 };
3149
3150 /* l4_core -> hdq1w interface */
3151 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
3152 .master = &omap3xxx_l4_core_hwmod,
3153 .slave = &omap3xxx_hdq1w_hwmod,
3154 .clk = "hdq_ick",
3155 .addr = omap2_hdq1w_addr_space,
3156 .user = OCP_USER_MPU | OCP_USER_SDMA,
3157 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
3158 };
3159
3160 /* l4_wkup -> 32ksync_counter */
3161 static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
3162 {
3163 .pa_start = 0x48320000,
3164 .pa_end = 0x4832001f,
3165 .flags = ADDR_TYPE_RT
3166 },
3167 { }
3168 };
3169
3170 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
3171 .master = &omap3xxx_l4_wkup_hwmod,
3172 .slave = &omap3xxx_counter_32k_hwmod,
3173 .clk = "omap_32ksync_ick",
3174 .addr = omap3xxx_counter_32k_addrs,
3175 .user = OCP_USER_MPU | OCP_USER_SDMA,
3176 };
3177
3178 /* am35xx has Davinci MDIO & EMAC */
3179 static struct omap_hwmod_class am35xx_mdio_class = {
3180 .name = "davinci_mdio",
3181 };
3182
3183 static struct omap_hwmod am35xx_mdio_hwmod = {
3184 .name = "davinci_mdio",
3185 .class = &am35xx_mdio_class,
3186 .flags = HWMOD_NO_IDLEST,
3187 };
3188
3189 /*
3190 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3191 * but this will probably require some additional hwmod core support,
3192 * so is left as a future to-do item.
3193 */
3194 static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
3195 .master = &am35xx_mdio_hwmod,
3196 .slave = &omap3xxx_l3_main_hwmod,
3197 .clk = "emac_fck",
3198 .user = OCP_USER_MPU,
3199 };
3200
3201 static struct omap_hwmod_addr_space am35xx_mdio_addrs[] = {
3202 {
3203 .pa_start = AM35XX_IPSS_MDIO_BASE,
3204 .pa_end = AM35XX_IPSS_MDIO_BASE + SZ_4K - 1,
3205 .flags = ADDR_TYPE_RT,
3206 },
3207 { }
3208 };
3209
3210 /* l4_core -> davinci mdio */
3211 /*
3212 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3213 * but this will probably require some additional hwmod core support,
3214 * so is left as a future to-do item.
3215 */
3216 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
3217 .master = &omap3xxx_l4_core_hwmod,
3218 .slave = &am35xx_mdio_hwmod,
3219 .clk = "emac_fck",
3220 .addr = am35xx_mdio_addrs,
3221 .user = OCP_USER_MPU,
3222 };
3223
3224 static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = {
3225 { .name = "rxthresh", .irq = INT_35XX_EMAC_C0_RXTHRESH_IRQ },
3226 { .name = "rx_pulse", .irq = INT_35XX_EMAC_C0_RX_PULSE_IRQ },
3227 { .name = "tx_pulse", .irq = INT_35XX_EMAC_C0_TX_PULSE_IRQ },
3228 { .name = "misc_pulse", .irq = INT_35XX_EMAC_C0_MISC_PULSE_IRQ },
3229 { .irq = -1 }
3230 };
3231
3232 static struct omap_hwmod_class am35xx_emac_class = {
3233 .name = "davinci_emac",
3234 };
3235
3236 static struct omap_hwmod am35xx_emac_hwmod = {
3237 .name = "davinci_emac",
3238 .mpu_irqs = am35xx_emac_mpu_irqs,
3239 .class = &am35xx_emac_class,
3240 .flags = HWMOD_NO_IDLEST,
3241 };
3242
3243 /* l3_core -> davinci emac interface */
3244 /*
3245 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3246 * but this will probably require some additional hwmod core support,
3247 * so is left as a future to-do item.
3248 */
3249 static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
3250 .master = &am35xx_emac_hwmod,
3251 .slave = &omap3xxx_l3_main_hwmod,
3252 .clk = "emac_ick",
3253 .user = OCP_USER_MPU,
3254 };
3255
3256 static struct omap_hwmod_addr_space am35xx_emac_addrs[] = {
3257 {
3258 .pa_start = AM35XX_IPSS_EMAC_BASE,
3259 .pa_end = AM35XX_IPSS_EMAC_BASE + 0x30000 - 1,
3260 .flags = ADDR_TYPE_RT,
3261 },
3262 { }
3263 };
3264
3265 /* l4_core -> davinci emac */
3266 /*
3267 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3268 * but this will probably require some additional hwmod core support,
3269 * so is left as a future to-do item.
3270 */
3271 static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
3272 .master = &omap3xxx_l4_core_hwmod,
3273 .slave = &am35xx_emac_hwmod,
3274 .clk = "emac_ick",
3275 .addr = am35xx_emac_addrs,
3276 .user = OCP_USER_MPU,
3277 };
3278
3279 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3280 &omap3xxx_l3_main__l4_core,
3281 &omap3xxx_l3_main__l4_per,
3282 &omap3xxx_mpu__l3_main,
3283 &omap3xxx_l4_core__l4_wkup,
3284 &omap3xxx_l4_core__mmc3,
3285 &omap3_l4_core__uart1,
3286 &omap3_l4_core__uart2,
3287 &omap3_l4_per__uart3,
3288 &omap3_l4_core__i2c1,
3289 &omap3_l4_core__i2c2,
3290 &omap3_l4_core__i2c3,
3291 &omap3xxx_l4_wkup__l4_sec,
3292 &omap3xxx_l4_wkup__timer1,
3293 &omap3xxx_l4_per__timer2,
3294 &omap3xxx_l4_per__timer3,
3295 &omap3xxx_l4_per__timer4,
3296 &omap3xxx_l4_per__timer5,
3297 &omap3xxx_l4_per__timer6,
3298 &omap3xxx_l4_per__timer7,
3299 &omap3xxx_l4_per__timer8,
3300 &omap3xxx_l4_per__timer9,
3301 &omap3xxx_l4_core__timer10,
3302 &omap3xxx_l4_core__timer11,
3303 &omap3xxx_l4_wkup__wd_timer2,
3304 &omap3xxx_l4_wkup__gpio1,
3305 &omap3xxx_l4_per__gpio2,
3306 &omap3xxx_l4_per__gpio3,
3307 &omap3xxx_l4_per__gpio4,
3308 &omap3xxx_l4_per__gpio5,
3309 &omap3xxx_l4_per__gpio6,
3310 &omap3xxx_dma_system__l3,
3311 &omap3xxx_l4_core__dma_system,
3312 &omap3xxx_l4_core__mcbsp1,
3313 &omap3xxx_l4_per__mcbsp2,
3314 &omap3xxx_l4_per__mcbsp3,
3315 &omap3xxx_l4_per__mcbsp4,
3316 &omap3xxx_l4_core__mcbsp5,
3317 &omap3xxx_l4_per__mcbsp2_sidetone,
3318 &omap3xxx_l4_per__mcbsp3_sidetone,
3319 &omap34xx_l4_core__mcspi1,
3320 &omap34xx_l4_core__mcspi2,
3321 &omap34xx_l4_core__mcspi3,
3322 &omap34xx_l4_core__mcspi4,
3323 &omap3xxx_l4_wkup__counter_32k,
3324 NULL,
3325 };
3326
3327 /* GP-only hwmod links */
3328 static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = {
3329 &omap3xxx_l4_sec__timer12,
3330 NULL
3331 };
3332
3333 /* 3430ES1-only hwmod links */
3334 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
3335 &omap3430es1_dss__l3,
3336 &omap3430es1_l4_core__dss,
3337 NULL
3338 };
3339
3340 /* 3430ES2+-only hwmod links */
3341 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
3342 &omap3xxx_dss__l3,
3343 &omap3xxx_l4_core__dss,
3344 &omap3xxx_usbhsotg__l3,
3345 &omap3xxx_l4_core__usbhsotg,
3346 &omap3xxx_usb_host_hs__l3_main_2,
3347 &omap3xxx_l4_core__usb_host_hs,
3348 &omap3xxx_l4_core__usb_tll_hs,
3349 NULL
3350 };
3351
3352 /* <= 3430ES3-only hwmod links */
3353 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
3354 &omap3xxx_l4_core__pre_es3_mmc1,
3355 &omap3xxx_l4_core__pre_es3_mmc2,
3356 NULL
3357 };
3358
3359 /* 3430ES3+-only hwmod links */
3360 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3361 &omap3xxx_l4_core__es3plus_mmc1,
3362 &omap3xxx_l4_core__es3plus_mmc2,
3363 NULL
3364 };
3365
3366 /* 34xx-only hwmod links (all ES revisions) */
3367 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3368 &omap3xxx_l3__iva,
3369 &omap34xx_l4_core__sr1,
3370 &omap34xx_l4_core__sr2,
3371 &omap3xxx_l4_core__mailbox,
3372 &omap3xxx_l4_core__hdq1w,
3373 NULL
3374 };
3375
3376 /* 36xx-only hwmod links (all ES revisions) */
3377 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3378 &omap3xxx_l3__iva,
3379 &omap36xx_l4_per__uart4,
3380 &omap3xxx_dss__l3,
3381 &omap3xxx_l4_core__dss,
3382 &omap36xx_l4_core__sr1,
3383 &omap36xx_l4_core__sr2,
3384 &omap3xxx_usbhsotg__l3,
3385 &omap3xxx_l4_core__usbhsotg,
3386 &omap3xxx_l4_core__mailbox,
3387 &omap3xxx_usb_host_hs__l3_main_2,
3388 &omap3xxx_l4_core__usb_host_hs,
3389 &omap3xxx_l4_core__usb_tll_hs,
3390 &omap3xxx_l4_core__es3plus_mmc1,
3391 &omap3xxx_l4_core__es3plus_mmc2,
3392 &omap3xxx_l4_core__hdq1w,
3393 NULL
3394 };
3395
3396 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3397 &omap3xxx_dss__l3,
3398 &omap3xxx_l4_core__dss,
3399 &am35xx_usbhsotg__l3,
3400 &am35xx_l4_core__usbhsotg,
3401 &am35xx_l4_core__uart4,
3402 &omap3xxx_usb_host_hs__l3_main_2,
3403 &omap3xxx_l4_core__usb_host_hs,
3404 &omap3xxx_l4_core__usb_tll_hs,
3405 &omap3xxx_l4_core__es3plus_mmc1,
3406 &omap3xxx_l4_core__es3plus_mmc2,
3407 &am35xx_mdio__l3,
3408 &am35xx_l4_core__mdio,
3409 &am35xx_emac__l3,
3410 &am35xx_l4_core__emac,
3411 NULL
3412 };
3413
3414 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3415 &omap3xxx_l4_core__dss_dispc,
3416 &omap3xxx_l4_core__dss_dsi1,
3417 &omap3xxx_l4_core__dss_rfbi,
3418 &omap3xxx_l4_core__dss_venc,
3419 NULL
3420 };
3421
3422 int __init omap3xxx_hwmod_init(void)
3423 {
3424 int r;
3425 struct omap_hwmod_ocp_if **h = NULL;
3426 unsigned int rev;
3427
3428 omap_hwmod_init();
3429
3430 /* Register hwmod links common to all OMAP3 */
3431 r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
3432 if (r < 0)
3433 return r;
3434
3435 /* Register GP-only hwmod links. */
3436 if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
3437 r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs);
3438 if (r < 0)
3439 return r;
3440 }
3441
3442 rev = omap_rev();
3443
3444 /*
3445 * Register hwmod links common to individual OMAP3 families, all
3446 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3447 * All possible revisions should be included in this conditional.
3448 */
3449 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3450 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3451 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3452 h = omap34xx_hwmod_ocp_ifs;
3453 } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
3454 h = am35xx_hwmod_ocp_ifs;
3455 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3456 rev == OMAP3630_REV_ES1_2) {
3457 h = omap36xx_hwmod_ocp_ifs;
3458 } else {
3459 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3460 return -EINVAL;
3461 };
3462
3463 r = omap_hwmod_register_links(h);
3464 if (r < 0)
3465 return r;
3466
3467 /*
3468 * Register hwmod links specific to certain ES levels of a
3469 * particular family of silicon (e.g., 34xx ES1.0)
3470 */
3471 h = NULL;
3472 if (rev == OMAP3430_REV_ES1_0) {
3473 h = omap3430es1_hwmod_ocp_ifs;
3474 } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3475 rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3476 rev == OMAP3430_REV_ES3_1_2) {
3477 h = omap3430es2plus_hwmod_ocp_ifs;
3478 };
3479
3480 if (h) {
3481 r = omap_hwmod_register_links(h);
3482 if (r < 0)
3483 return r;
3484 }
3485
3486 h = NULL;
3487 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3488 rev == OMAP3430_REV_ES2_1) {
3489 h = omap3430_pre_es3_hwmod_ocp_ifs;
3490 } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3491 rev == OMAP3430_REV_ES3_1_2) {
3492 h = omap3430_es3plus_hwmod_ocp_ifs;
3493 };
3494
3495 if (h)
3496 r = omap_hwmod_register_links(h);
3497 if (r < 0)
3498 return r;
3499
3500 /*
3501 * DSS code presumes that dss_core hwmod is handled first,
3502 * _before_ any other DSS related hwmods so register common
3503 * DSS hwmod links last to ensure that dss_core is already
3504 * registered. Otherwise some change things may happen, for
3505 * ex. if dispc is handled before dss_core and DSS is enabled
3506 * in bootloader DISPC will be reset with outputs enabled
3507 * which sometimes leads to unrecoverable L3 error. XXX The
3508 * long-term fix to this is to ensure hwmods are set up in
3509 * dependency order in the hwmod core code.
3510 */
3511 r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
3512
3513 return r;
3514 }
Linux kernel - Deliverables
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