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Merge tag 'omap-devel-dmtimer-for-v3.6' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_3xxx_data.c
1 /*
2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
3 *
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
6 * Paul Walmsley
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * The data in this file should be completely autogeneratable from
13 * the TI hardware database or other technical documentation.
14 *
15 * XXX these should be marked initdata for multi-OMAP kernels
16 */
17 #include <plat/omap_hwmod.h>
18 #include <mach/irqs.h>
19 #include <plat/cpu.h>
20 #include <plat/dma.h>
21 #include <plat/serial.h>
22 #include <plat/l3_3xxx.h>
23 #include <plat/l4_3xxx.h>
24 #include <plat/i2c.h>
25 #include <plat/gpio.h>
26 #include <plat/mmc.h>
27 #include <plat/mcbsp.h>
28 #include <plat/mcspi.h>
29 #include <plat/dmtimer.h>
30
31 #include "omap_hwmod_common_data.h"
32
33 #include "smartreflex.h"
34 #include "prm-regbits-34xx.h"
35 #include "cm-regbits-34xx.h"
36 #include "wd_timer.h"
37 #include <mach/am35xx.h>
38
39 /*
40 * OMAP3xxx hardware module integration data
41 *
42 * All of the data in this section should be autogeneratable from the
43 * TI hardware database or other technical documentation. Data that
44 * is driver-specific or driver-kernel integration-specific belongs
45 * elsewhere.
46 */
47
48 /*
49 * IP blocks
50 */
51
52 /* L3 */
53 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
54 { .irq = INT_34XX_L3_DBG_IRQ },
55 { .irq = INT_34XX_L3_APP_IRQ },
56 { .irq = -1 }
57 };
58
59 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
60 .name = "l3_main",
61 .class = &l3_hwmod_class,
62 .mpu_irqs = omap3xxx_l3_main_irqs,
63 .flags = HWMOD_NO_IDLEST,
64 };
65
66 /* L4 CORE */
67 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
68 .name = "l4_core",
69 .class = &l4_hwmod_class,
70 .flags = HWMOD_NO_IDLEST,
71 };
72
73 /* L4 PER */
74 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
75 .name = "l4_per",
76 .class = &l4_hwmod_class,
77 .flags = HWMOD_NO_IDLEST,
78 };
79
80 /* L4 WKUP */
81 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
82 .name = "l4_wkup",
83 .class = &l4_hwmod_class,
84 .flags = HWMOD_NO_IDLEST,
85 };
86
87 /* L4 SEC */
88 static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
89 .name = "l4_sec",
90 .class = &l4_hwmod_class,
91 .flags = HWMOD_NO_IDLEST,
92 };
93
94 /* MPU */
95 static struct omap_hwmod omap3xxx_mpu_hwmod = {
96 .name = "mpu",
97 .class = &mpu_hwmod_class,
98 .main_clk = "arm_fck",
99 };
100
101 /* IVA2 (IVA2) */
102 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
103 { .name = "logic", .rst_shift = 0 },
104 { .name = "seq0", .rst_shift = 1 },
105 { .name = "seq1", .rst_shift = 2 },
106 };
107
108 static struct omap_hwmod omap3xxx_iva_hwmod = {
109 .name = "iva",
110 .class = &iva_hwmod_class,
111 .clkdm_name = "iva2_clkdm",
112 .rst_lines = omap3xxx_iva_resets,
113 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets),
114 .main_clk = "iva2_ck",
115 };
116
117 /* timer class */
118 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
119 .rev_offs = 0x0000,
120 .sysc_offs = 0x0010,
121 .syss_offs = 0x0014,
122 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
123 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
124 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
125 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
126 .sysc_fields = &omap_hwmod_sysc_type1,
127 };
128
129 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
130 .name = "timer",
131 .sysc = &omap3xxx_timer_1ms_sysc,
132 };
133
134 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
135 .rev_offs = 0x0000,
136 .sysc_offs = 0x0010,
137 .syss_offs = 0x0014,
138 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
139 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
140 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
141 .sysc_fields = &omap_hwmod_sysc_type1,
142 };
143
144 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
145 .name = "timer",
146 .sysc = &omap3xxx_timer_sysc,
147 };
148
149 /* secure timers dev attribute */
150 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
151 .timer_capability = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE,
152 };
153
154 /* always-on timers dev attribute */
155 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
156 .timer_capability = OMAP_TIMER_ALWON,
157 };
158
159 /* pwm timers dev attribute */
160 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
161 .timer_capability = OMAP_TIMER_HAS_PWM,
162 };
163
164 /* timer1 */
165 static struct omap_hwmod omap3xxx_timer1_hwmod = {
166 .name = "timer1",
167 .mpu_irqs = omap2_timer1_mpu_irqs,
168 .main_clk = "gpt1_fck",
169 .prcm = {
170 .omap2 = {
171 .prcm_reg_id = 1,
172 .module_bit = OMAP3430_EN_GPT1_SHIFT,
173 .module_offs = WKUP_MOD,
174 .idlest_reg_id = 1,
175 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
176 },
177 },
178 .dev_attr = &capability_alwon_dev_attr,
179 .class = &omap3xxx_timer_1ms_hwmod_class,
180 };
181
182 /* timer2 */
183 static struct omap_hwmod omap3xxx_timer2_hwmod = {
184 .name = "timer2",
185 .mpu_irqs = omap2_timer2_mpu_irqs,
186 .main_clk = "gpt2_fck",
187 .prcm = {
188 .omap2 = {
189 .prcm_reg_id = 1,
190 .module_bit = OMAP3430_EN_GPT2_SHIFT,
191 .module_offs = OMAP3430_PER_MOD,
192 .idlest_reg_id = 1,
193 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
194 },
195 },
196 .class = &omap3xxx_timer_1ms_hwmod_class,
197 };
198
199 /* timer3 */
200 static struct omap_hwmod omap3xxx_timer3_hwmod = {
201 .name = "timer3",
202 .mpu_irqs = omap2_timer3_mpu_irqs,
203 .main_clk = "gpt3_fck",
204 .prcm = {
205 .omap2 = {
206 .prcm_reg_id = 1,
207 .module_bit = OMAP3430_EN_GPT3_SHIFT,
208 .module_offs = OMAP3430_PER_MOD,
209 .idlest_reg_id = 1,
210 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
211 },
212 },
213 .class = &omap3xxx_timer_hwmod_class,
214 };
215
216 /* timer4 */
217 static struct omap_hwmod omap3xxx_timer4_hwmod = {
218 .name = "timer4",
219 .mpu_irqs = omap2_timer4_mpu_irqs,
220 .main_clk = "gpt4_fck",
221 .prcm = {
222 .omap2 = {
223 .prcm_reg_id = 1,
224 .module_bit = OMAP3430_EN_GPT4_SHIFT,
225 .module_offs = OMAP3430_PER_MOD,
226 .idlest_reg_id = 1,
227 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
228 },
229 },
230 .class = &omap3xxx_timer_hwmod_class,
231 };
232
233 /* timer5 */
234 static struct omap_hwmod omap3xxx_timer5_hwmod = {
235 .name = "timer5",
236 .mpu_irqs = omap2_timer5_mpu_irqs,
237 .main_clk = "gpt5_fck",
238 .prcm = {
239 .omap2 = {
240 .prcm_reg_id = 1,
241 .module_bit = OMAP3430_EN_GPT5_SHIFT,
242 .module_offs = OMAP3430_PER_MOD,
243 .idlest_reg_id = 1,
244 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
245 },
246 },
247 .class = &omap3xxx_timer_hwmod_class,
248 };
249
250 /* timer6 */
251 static struct omap_hwmod omap3xxx_timer6_hwmod = {
252 .name = "timer6",
253 .mpu_irqs = omap2_timer6_mpu_irqs,
254 .main_clk = "gpt6_fck",
255 .prcm = {
256 .omap2 = {
257 .prcm_reg_id = 1,
258 .module_bit = OMAP3430_EN_GPT6_SHIFT,
259 .module_offs = OMAP3430_PER_MOD,
260 .idlest_reg_id = 1,
261 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
262 },
263 },
264 .class = &omap3xxx_timer_hwmod_class,
265 };
266
267 /* timer7 */
268 static struct omap_hwmod omap3xxx_timer7_hwmod = {
269 .name = "timer7",
270 .mpu_irqs = omap2_timer7_mpu_irqs,
271 .main_clk = "gpt7_fck",
272 .prcm = {
273 .omap2 = {
274 .prcm_reg_id = 1,
275 .module_bit = OMAP3430_EN_GPT7_SHIFT,
276 .module_offs = OMAP3430_PER_MOD,
277 .idlest_reg_id = 1,
278 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
279 },
280 },
281 .class = &omap3xxx_timer_hwmod_class,
282 };
283
284 /* timer8 */
285 static struct omap_hwmod omap3xxx_timer8_hwmod = {
286 .name = "timer8",
287 .mpu_irqs = omap2_timer8_mpu_irqs,
288 .main_clk = "gpt8_fck",
289 .prcm = {
290 .omap2 = {
291 .prcm_reg_id = 1,
292 .module_bit = OMAP3430_EN_GPT8_SHIFT,
293 .module_offs = OMAP3430_PER_MOD,
294 .idlest_reg_id = 1,
295 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
296 },
297 },
298 .dev_attr = &capability_pwm_dev_attr,
299 .class = &omap3xxx_timer_hwmod_class,
300 };
301
302 /* timer9 */
303 static struct omap_hwmod omap3xxx_timer9_hwmod = {
304 .name = "timer9",
305 .mpu_irqs = omap2_timer9_mpu_irqs,
306 .main_clk = "gpt9_fck",
307 .prcm = {
308 .omap2 = {
309 .prcm_reg_id = 1,
310 .module_bit = OMAP3430_EN_GPT9_SHIFT,
311 .module_offs = OMAP3430_PER_MOD,
312 .idlest_reg_id = 1,
313 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
314 },
315 },
316 .dev_attr = &capability_pwm_dev_attr,
317 .class = &omap3xxx_timer_hwmod_class,
318 };
319
320 /* timer10 */
321 static struct omap_hwmod omap3xxx_timer10_hwmod = {
322 .name = "timer10",
323 .mpu_irqs = omap2_timer10_mpu_irqs,
324 .main_clk = "gpt10_fck",
325 .prcm = {
326 .omap2 = {
327 .prcm_reg_id = 1,
328 .module_bit = OMAP3430_EN_GPT10_SHIFT,
329 .module_offs = CORE_MOD,
330 .idlest_reg_id = 1,
331 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
332 },
333 },
334 .dev_attr = &capability_pwm_dev_attr,
335 .class = &omap3xxx_timer_1ms_hwmod_class,
336 };
337
338 /* timer11 */
339 static struct omap_hwmod omap3xxx_timer11_hwmod = {
340 .name = "timer11",
341 .mpu_irqs = omap2_timer11_mpu_irqs,
342 .main_clk = "gpt11_fck",
343 .prcm = {
344 .omap2 = {
345 .prcm_reg_id = 1,
346 .module_bit = OMAP3430_EN_GPT11_SHIFT,
347 .module_offs = CORE_MOD,
348 .idlest_reg_id = 1,
349 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
350 },
351 },
352 .dev_attr = &capability_pwm_dev_attr,
353 .class = &omap3xxx_timer_hwmod_class,
354 };
355
356 /* timer12 */
357 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
358 { .irq = 95, },
359 { .irq = -1 }
360 };
361
362 static struct omap_hwmod omap3xxx_timer12_hwmod = {
363 .name = "timer12",
364 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
365 .main_clk = "gpt12_fck",
366 .prcm = {
367 .omap2 = {
368 .prcm_reg_id = 1,
369 .module_bit = OMAP3430_EN_GPT12_SHIFT,
370 .module_offs = WKUP_MOD,
371 .idlest_reg_id = 1,
372 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
373 },
374 },
375 .dev_attr = &capability_secure_dev_attr,
376 .class = &omap3xxx_timer_hwmod_class,
377 };
378
379 /*
380 * 'wd_timer' class
381 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
382 * overflow condition
383 */
384
385 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
386 .rev_offs = 0x0000,
387 .sysc_offs = 0x0010,
388 .syss_offs = 0x0014,
389 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
390 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
391 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
392 SYSS_HAS_RESET_STATUS),
393 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
394 .sysc_fields = &omap_hwmod_sysc_type1,
395 };
396
397 /* I2C common */
398 static struct omap_hwmod_class_sysconfig i2c_sysc = {
399 .rev_offs = 0x00,
400 .sysc_offs = 0x20,
401 .syss_offs = 0x10,
402 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
403 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
404 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
405 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
406 .clockact = CLOCKACT_TEST_ICLK,
407 .sysc_fields = &omap_hwmod_sysc_type1,
408 };
409
410 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
411 .name = "wd_timer",
412 .sysc = &omap3xxx_wd_timer_sysc,
413 .pre_shutdown = &omap2_wd_timer_disable,
414 .reset = &omap2_wd_timer_reset,
415 };
416
417 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
418 .name = "wd_timer2",
419 .class = &omap3xxx_wd_timer_hwmod_class,
420 .main_clk = "wdt2_fck",
421 .prcm = {
422 .omap2 = {
423 .prcm_reg_id = 1,
424 .module_bit = OMAP3430_EN_WDT2_SHIFT,
425 .module_offs = WKUP_MOD,
426 .idlest_reg_id = 1,
427 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
428 },
429 },
430 /*
431 * XXX: Use software supervised mode, HW supervised smartidle seems to
432 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
433 */
434 .flags = HWMOD_SWSUP_SIDLE,
435 };
436
437 /* UART1 */
438 static struct omap_hwmod omap3xxx_uart1_hwmod = {
439 .name = "uart1",
440 .mpu_irqs = omap2_uart1_mpu_irqs,
441 .sdma_reqs = omap2_uart1_sdma_reqs,
442 .main_clk = "uart1_fck",
443 .prcm = {
444 .omap2 = {
445 .module_offs = CORE_MOD,
446 .prcm_reg_id = 1,
447 .module_bit = OMAP3430_EN_UART1_SHIFT,
448 .idlest_reg_id = 1,
449 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
450 },
451 },
452 .class = &omap2_uart_class,
453 };
454
455 /* UART2 */
456 static struct omap_hwmod omap3xxx_uart2_hwmod = {
457 .name = "uart2",
458 .mpu_irqs = omap2_uart2_mpu_irqs,
459 .sdma_reqs = omap2_uart2_sdma_reqs,
460 .main_clk = "uart2_fck",
461 .prcm = {
462 .omap2 = {
463 .module_offs = CORE_MOD,
464 .prcm_reg_id = 1,
465 .module_bit = OMAP3430_EN_UART2_SHIFT,
466 .idlest_reg_id = 1,
467 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
468 },
469 },
470 .class = &omap2_uart_class,
471 };
472
473 /* UART3 */
474 static struct omap_hwmod omap3xxx_uart3_hwmod = {
475 .name = "uart3",
476 .mpu_irqs = omap2_uart3_mpu_irqs,
477 .sdma_reqs = omap2_uart3_sdma_reqs,
478 .main_clk = "uart3_fck",
479 .prcm = {
480 .omap2 = {
481 .module_offs = OMAP3430_PER_MOD,
482 .prcm_reg_id = 1,
483 .module_bit = OMAP3430_EN_UART3_SHIFT,
484 .idlest_reg_id = 1,
485 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
486 },
487 },
488 .class = &omap2_uart_class,
489 };
490
491 /* UART4 */
492 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
493 { .irq = INT_36XX_UART4_IRQ, },
494 { .irq = -1 }
495 };
496
497 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
498 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
499 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
500 { .dma_req = -1 }
501 };
502
503 static struct omap_hwmod omap36xx_uart4_hwmod = {
504 .name = "uart4",
505 .mpu_irqs = uart4_mpu_irqs,
506 .sdma_reqs = uart4_sdma_reqs,
507 .main_clk = "uart4_fck",
508 .prcm = {
509 .omap2 = {
510 .module_offs = OMAP3430_PER_MOD,
511 .prcm_reg_id = 1,
512 .module_bit = OMAP3630_EN_UART4_SHIFT,
513 .idlest_reg_id = 1,
514 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
515 },
516 },
517 .class = &omap2_uart_class,
518 };
519
520 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
521 { .irq = INT_35XX_UART4_IRQ, },
522 };
523
524 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
525 { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
526 { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
527 };
528
529 static struct omap_hwmod am35xx_uart4_hwmod = {
530 .name = "uart4",
531 .mpu_irqs = am35xx_uart4_mpu_irqs,
532 .sdma_reqs = am35xx_uart4_sdma_reqs,
533 .main_clk = "uart4_fck",
534 .prcm = {
535 .omap2 = {
536 .module_offs = CORE_MOD,
537 .prcm_reg_id = 1,
538 .module_bit = OMAP3430_EN_UART4_SHIFT,
539 .idlest_reg_id = 1,
540 .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT,
541 },
542 },
543 .class = &omap2_uart_class,
544 };
545
546 static struct omap_hwmod_class i2c_class = {
547 .name = "i2c",
548 .sysc = &i2c_sysc,
549 .rev = OMAP_I2C_IP_VERSION_1,
550 .reset = &omap_i2c_reset,
551 };
552
553 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
554 { .name = "dispc", .dma_req = 5 },
555 { .name = "dsi1", .dma_req = 74 },
556 { .dma_req = -1 }
557 };
558
559 /* dss */
560 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
561 /*
562 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
563 * driver does not use these clocks.
564 */
565 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
566 { .role = "tv_clk", .clk = "dss_tv_fck" },
567 /* required only on OMAP3430 */
568 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
569 };
570
571 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
572 .name = "dss_core",
573 .class = &omap2_dss_hwmod_class,
574 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
575 .sdma_reqs = omap3xxx_dss_sdma_chs,
576 .prcm = {
577 .omap2 = {
578 .prcm_reg_id = 1,
579 .module_bit = OMAP3430_EN_DSS1_SHIFT,
580 .module_offs = OMAP3430_DSS_MOD,
581 .idlest_reg_id = 1,
582 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
583 },
584 },
585 .opt_clks = dss_opt_clks,
586 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
587 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
588 };
589
590 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
591 .name = "dss_core",
592 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
593 .class = &omap2_dss_hwmod_class,
594 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
595 .sdma_reqs = omap3xxx_dss_sdma_chs,
596 .prcm = {
597 .omap2 = {
598 .prcm_reg_id = 1,
599 .module_bit = OMAP3430_EN_DSS1_SHIFT,
600 .module_offs = OMAP3430_DSS_MOD,
601 .idlest_reg_id = 1,
602 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
603 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
604 },
605 },
606 .opt_clks = dss_opt_clks,
607 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
608 };
609
610 /*
611 * 'dispc' class
612 * display controller
613 */
614
615 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
616 .rev_offs = 0x0000,
617 .sysc_offs = 0x0010,
618 .syss_offs = 0x0014,
619 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
620 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
621 SYSC_HAS_ENAWAKEUP),
622 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
623 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
624 .sysc_fields = &omap_hwmod_sysc_type1,
625 };
626
627 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
628 .name = "dispc",
629 .sysc = &omap3_dispc_sysc,
630 };
631
632 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
633 .name = "dss_dispc",
634 .class = &omap3_dispc_hwmod_class,
635 .mpu_irqs = omap2_dispc_irqs,
636 .main_clk = "dss1_alwon_fck",
637 .prcm = {
638 .omap2 = {
639 .prcm_reg_id = 1,
640 .module_bit = OMAP3430_EN_DSS1_SHIFT,
641 .module_offs = OMAP3430_DSS_MOD,
642 },
643 },
644 .flags = HWMOD_NO_IDLEST,
645 .dev_attr = &omap2_3_dss_dispc_dev_attr
646 };
647
648 /*
649 * 'dsi' class
650 * display serial interface controller
651 */
652
653 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
654 .name = "dsi",
655 };
656
657 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
658 { .irq = 25 },
659 { .irq = -1 }
660 };
661
662 /* dss_dsi1 */
663 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
664 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
665 };
666
667 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
668 .name = "dss_dsi1",
669 .class = &omap3xxx_dsi_hwmod_class,
670 .mpu_irqs = omap3xxx_dsi1_irqs,
671 .main_clk = "dss1_alwon_fck",
672 .prcm = {
673 .omap2 = {
674 .prcm_reg_id = 1,
675 .module_bit = OMAP3430_EN_DSS1_SHIFT,
676 .module_offs = OMAP3430_DSS_MOD,
677 },
678 },
679 .opt_clks = dss_dsi1_opt_clks,
680 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
681 .flags = HWMOD_NO_IDLEST,
682 };
683
684 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
685 { .role = "ick", .clk = "dss_ick" },
686 };
687
688 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
689 .name = "dss_rfbi",
690 .class = &omap2_rfbi_hwmod_class,
691 .main_clk = "dss1_alwon_fck",
692 .prcm = {
693 .omap2 = {
694 .prcm_reg_id = 1,
695 .module_bit = OMAP3430_EN_DSS1_SHIFT,
696 .module_offs = OMAP3430_DSS_MOD,
697 },
698 },
699 .opt_clks = dss_rfbi_opt_clks,
700 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
701 .flags = HWMOD_NO_IDLEST,
702 };
703
704 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
705 /* required only on OMAP3430 */
706 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
707 };
708
709 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
710 .name = "dss_venc",
711 .class = &omap2_venc_hwmod_class,
712 .main_clk = "dss_tv_fck",
713 .prcm = {
714 .omap2 = {
715 .prcm_reg_id = 1,
716 .module_bit = OMAP3430_EN_DSS1_SHIFT,
717 .module_offs = OMAP3430_DSS_MOD,
718 },
719 },
720 .opt_clks = dss_venc_opt_clks,
721 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
722 .flags = HWMOD_NO_IDLEST,
723 };
724
725 /* I2C1 */
726 static struct omap_i2c_dev_attr i2c1_dev_attr = {
727 .fifo_depth = 8, /* bytes */
728 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
729 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
730 OMAP_I2C_FLAG_BUS_SHIFT_2,
731 };
732
733 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
734 .name = "i2c1",
735 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
736 .mpu_irqs = omap2_i2c1_mpu_irqs,
737 .sdma_reqs = omap2_i2c1_sdma_reqs,
738 .main_clk = "i2c1_fck",
739 .prcm = {
740 .omap2 = {
741 .module_offs = CORE_MOD,
742 .prcm_reg_id = 1,
743 .module_bit = OMAP3430_EN_I2C1_SHIFT,
744 .idlest_reg_id = 1,
745 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
746 },
747 },
748 .class = &i2c_class,
749 .dev_attr = &i2c1_dev_attr,
750 };
751
752 /* I2C2 */
753 static struct omap_i2c_dev_attr i2c2_dev_attr = {
754 .fifo_depth = 8, /* bytes */
755 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
756 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
757 OMAP_I2C_FLAG_BUS_SHIFT_2,
758 };
759
760 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
761 .name = "i2c2",
762 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
763 .mpu_irqs = omap2_i2c2_mpu_irqs,
764 .sdma_reqs = omap2_i2c2_sdma_reqs,
765 .main_clk = "i2c2_fck",
766 .prcm = {
767 .omap2 = {
768 .module_offs = CORE_MOD,
769 .prcm_reg_id = 1,
770 .module_bit = OMAP3430_EN_I2C2_SHIFT,
771 .idlest_reg_id = 1,
772 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
773 },
774 },
775 .class = &i2c_class,
776 .dev_attr = &i2c2_dev_attr,
777 };
778
779 /* I2C3 */
780 static struct omap_i2c_dev_attr i2c3_dev_attr = {
781 .fifo_depth = 64, /* bytes */
782 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
783 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
784 OMAP_I2C_FLAG_BUS_SHIFT_2,
785 };
786
787 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
788 { .irq = INT_34XX_I2C3_IRQ, },
789 { .irq = -1 }
790 };
791
792 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
793 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
794 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
795 { .dma_req = -1 }
796 };
797
798 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
799 .name = "i2c3",
800 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
801 .mpu_irqs = i2c3_mpu_irqs,
802 .sdma_reqs = i2c3_sdma_reqs,
803 .main_clk = "i2c3_fck",
804 .prcm = {
805 .omap2 = {
806 .module_offs = CORE_MOD,
807 .prcm_reg_id = 1,
808 .module_bit = OMAP3430_EN_I2C3_SHIFT,
809 .idlest_reg_id = 1,
810 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
811 },
812 },
813 .class = &i2c_class,
814 .dev_attr = &i2c3_dev_attr,
815 };
816
817 /*
818 * 'gpio' class
819 * general purpose io module
820 */
821
822 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
823 .rev_offs = 0x0000,
824 .sysc_offs = 0x0010,
825 .syss_offs = 0x0014,
826 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
827 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
828 SYSS_HAS_RESET_STATUS),
829 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
830 .sysc_fields = &omap_hwmod_sysc_type1,
831 };
832
833 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
834 .name = "gpio",
835 .sysc = &omap3xxx_gpio_sysc,
836 .rev = 1,
837 };
838
839 /* gpio_dev_attr */
840 static struct omap_gpio_dev_attr gpio_dev_attr = {
841 .bank_width = 32,
842 .dbck_flag = true,
843 };
844
845 /* gpio1 */
846 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
847 { .role = "dbclk", .clk = "gpio1_dbck", },
848 };
849
850 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
851 .name = "gpio1",
852 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
853 .mpu_irqs = omap2_gpio1_irqs,
854 .main_clk = "gpio1_ick",
855 .opt_clks = gpio1_opt_clks,
856 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
857 .prcm = {
858 .omap2 = {
859 .prcm_reg_id = 1,
860 .module_bit = OMAP3430_EN_GPIO1_SHIFT,
861 .module_offs = WKUP_MOD,
862 .idlest_reg_id = 1,
863 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
864 },
865 },
866 .class = &omap3xxx_gpio_hwmod_class,
867 .dev_attr = &gpio_dev_attr,
868 };
869
870 /* gpio2 */
871 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
872 { .role = "dbclk", .clk = "gpio2_dbck", },
873 };
874
875 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
876 .name = "gpio2",
877 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
878 .mpu_irqs = omap2_gpio2_irqs,
879 .main_clk = "gpio2_ick",
880 .opt_clks = gpio2_opt_clks,
881 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
882 .prcm = {
883 .omap2 = {
884 .prcm_reg_id = 1,
885 .module_bit = OMAP3430_EN_GPIO2_SHIFT,
886 .module_offs = OMAP3430_PER_MOD,
887 .idlest_reg_id = 1,
888 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
889 },
890 },
891 .class = &omap3xxx_gpio_hwmod_class,
892 .dev_attr = &gpio_dev_attr,
893 };
894
895 /* gpio3 */
896 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
897 { .role = "dbclk", .clk = "gpio3_dbck", },
898 };
899
900 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
901 .name = "gpio3",
902 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
903 .mpu_irqs = omap2_gpio3_irqs,
904 .main_clk = "gpio3_ick",
905 .opt_clks = gpio3_opt_clks,
906 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
907 .prcm = {
908 .omap2 = {
909 .prcm_reg_id = 1,
910 .module_bit = OMAP3430_EN_GPIO3_SHIFT,
911 .module_offs = OMAP3430_PER_MOD,
912 .idlest_reg_id = 1,
913 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
914 },
915 },
916 .class = &omap3xxx_gpio_hwmod_class,
917 .dev_attr = &gpio_dev_attr,
918 };
919
920 /* gpio4 */
921 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
922 { .role = "dbclk", .clk = "gpio4_dbck", },
923 };
924
925 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
926 .name = "gpio4",
927 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
928 .mpu_irqs = omap2_gpio4_irqs,
929 .main_clk = "gpio4_ick",
930 .opt_clks = gpio4_opt_clks,
931 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
932 .prcm = {
933 .omap2 = {
934 .prcm_reg_id = 1,
935 .module_bit = OMAP3430_EN_GPIO4_SHIFT,
936 .module_offs = OMAP3430_PER_MOD,
937 .idlest_reg_id = 1,
938 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
939 },
940 },
941 .class = &omap3xxx_gpio_hwmod_class,
942 .dev_attr = &gpio_dev_attr,
943 };
944
945 /* gpio5 */
946 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
947 { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
948 { .irq = -1 }
949 };
950
951 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
952 { .role = "dbclk", .clk = "gpio5_dbck", },
953 };
954
955 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
956 .name = "gpio5",
957 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
958 .mpu_irqs = omap3xxx_gpio5_irqs,
959 .main_clk = "gpio5_ick",
960 .opt_clks = gpio5_opt_clks,
961 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
962 .prcm = {
963 .omap2 = {
964 .prcm_reg_id = 1,
965 .module_bit = OMAP3430_EN_GPIO5_SHIFT,
966 .module_offs = OMAP3430_PER_MOD,
967 .idlest_reg_id = 1,
968 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
969 },
970 },
971 .class = &omap3xxx_gpio_hwmod_class,
972 .dev_attr = &gpio_dev_attr,
973 };
974
975 /* gpio6 */
976 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
977 { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
978 { .irq = -1 }
979 };
980
981 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
982 { .role = "dbclk", .clk = "gpio6_dbck", },
983 };
984
985 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
986 .name = "gpio6",
987 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
988 .mpu_irqs = omap3xxx_gpio6_irqs,
989 .main_clk = "gpio6_ick",
990 .opt_clks = gpio6_opt_clks,
991 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
992 .prcm = {
993 .omap2 = {
994 .prcm_reg_id = 1,
995 .module_bit = OMAP3430_EN_GPIO6_SHIFT,
996 .module_offs = OMAP3430_PER_MOD,
997 .idlest_reg_id = 1,
998 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
999 },
1000 },
1001 .class = &omap3xxx_gpio_hwmod_class,
1002 .dev_attr = &gpio_dev_attr,
1003 };
1004
1005 /* dma attributes */
1006 static struct omap_dma_dev_attr dma_dev_attr = {
1007 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1008 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1009 .lch_count = 32,
1010 };
1011
1012 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1013 .rev_offs = 0x0000,
1014 .sysc_offs = 0x002c,
1015 .syss_offs = 0x0028,
1016 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1017 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1018 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
1019 SYSS_HAS_RESET_STATUS),
1020 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1021 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1022 .sysc_fields = &omap_hwmod_sysc_type1,
1023 };
1024
1025 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1026 .name = "dma",
1027 .sysc = &omap3xxx_dma_sysc,
1028 };
1029
1030 /* dma_system */
1031 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1032 .name = "dma",
1033 .class = &omap3xxx_dma_hwmod_class,
1034 .mpu_irqs = omap2_dma_system_irqs,
1035 .main_clk = "core_l3_ick",
1036 .prcm = {
1037 .omap2 = {
1038 .module_offs = CORE_MOD,
1039 .prcm_reg_id = 1,
1040 .module_bit = OMAP3430_ST_SDMA_SHIFT,
1041 .idlest_reg_id = 1,
1042 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
1043 },
1044 },
1045 .dev_attr = &dma_dev_attr,
1046 .flags = HWMOD_NO_IDLEST,
1047 };
1048
1049 /*
1050 * 'mcbsp' class
1051 * multi channel buffered serial port controller
1052 */
1053
1054 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
1055 .sysc_offs = 0x008c,
1056 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1057 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1058 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1059 .sysc_fields = &omap_hwmod_sysc_type1,
1060 .clockact = 0x2,
1061 };
1062
1063 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1064 .name = "mcbsp",
1065 .sysc = &omap3xxx_mcbsp_sysc,
1066 .rev = MCBSP_CONFIG_TYPE3,
1067 };
1068
1069 /* mcbsp1 */
1070 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
1071 { .name = "common", .irq = 16 },
1072 { .name = "tx", .irq = 59 },
1073 { .name = "rx", .irq = 60 },
1074 { .irq = -1 }
1075 };
1076
1077 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1078 .name = "mcbsp1",
1079 .class = &omap3xxx_mcbsp_hwmod_class,
1080 .mpu_irqs = omap3xxx_mcbsp1_irqs,
1081 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
1082 .main_clk = "mcbsp1_fck",
1083 .prcm = {
1084 .omap2 = {
1085 .prcm_reg_id = 1,
1086 .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
1087 .module_offs = CORE_MOD,
1088 .idlest_reg_id = 1,
1089 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
1090 },
1091 },
1092 };
1093
1094 /* mcbsp2 */
1095 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
1096 { .name = "common", .irq = 17 },
1097 { .name = "tx", .irq = 62 },
1098 { .name = "rx", .irq = 63 },
1099 { .irq = -1 }
1100 };
1101
1102 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1103 .sidetone = "mcbsp2_sidetone",
1104 };
1105
1106 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1107 .name = "mcbsp2",
1108 .class = &omap3xxx_mcbsp_hwmod_class,
1109 .mpu_irqs = omap3xxx_mcbsp2_irqs,
1110 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
1111 .main_clk = "mcbsp2_fck",
1112 .prcm = {
1113 .omap2 = {
1114 .prcm_reg_id = 1,
1115 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1116 .module_offs = OMAP3430_PER_MOD,
1117 .idlest_reg_id = 1,
1118 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1119 },
1120 },
1121 .dev_attr = &omap34xx_mcbsp2_dev_attr,
1122 };
1123
1124 /* mcbsp3 */
1125 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
1126 { .name = "common", .irq = 22 },
1127 { .name = "tx", .irq = 89 },
1128 { .name = "rx", .irq = 90 },
1129 { .irq = -1 }
1130 };
1131
1132 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1133 .sidetone = "mcbsp3_sidetone",
1134 };
1135
1136 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1137 .name = "mcbsp3",
1138 .class = &omap3xxx_mcbsp_hwmod_class,
1139 .mpu_irqs = omap3xxx_mcbsp3_irqs,
1140 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
1141 .main_clk = "mcbsp3_fck",
1142 .prcm = {
1143 .omap2 = {
1144 .prcm_reg_id = 1,
1145 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1146 .module_offs = OMAP3430_PER_MOD,
1147 .idlest_reg_id = 1,
1148 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1149 },
1150 },
1151 .dev_attr = &omap34xx_mcbsp3_dev_attr,
1152 };
1153
1154 /* mcbsp4 */
1155 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
1156 { .name = "common", .irq = 23 },
1157 { .name = "tx", .irq = 54 },
1158 { .name = "rx", .irq = 55 },
1159 { .irq = -1 }
1160 };
1161
1162 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
1163 { .name = "rx", .dma_req = 20 },
1164 { .name = "tx", .dma_req = 19 },
1165 { .dma_req = -1 }
1166 };
1167
1168 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1169 .name = "mcbsp4",
1170 .class = &omap3xxx_mcbsp_hwmod_class,
1171 .mpu_irqs = omap3xxx_mcbsp4_irqs,
1172 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
1173 .main_clk = "mcbsp4_fck",
1174 .prcm = {
1175 .omap2 = {
1176 .prcm_reg_id = 1,
1177 .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
1178 .module_offs = OMAP3430_PER_MOD,
1179 .idlest_reg_id = 1,
1180 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
1181 },
1182 },
1183 };
1184
1185 /* mcbsp5 */
1186 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
1187 { .name = "common", .irq = 27 },
1188 { .name = "tx", .irq = 81 },
1189 { .name = "rx", .irq = 82 },
1190 { .irq = -1 }
1191 };
1192
1193 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
1194 { .name = "rx", .dma_req = 22 },
1195 { .name = "tx", .dma_req = 21 },
1196 { .dma_req = -1 }
1197 };
1198
1199 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1200 .name = "mcbsp5",
1201 .class = &omap3xxx_mcbsp_hwmod_class,
1202 .mpu_irqs = omap3xxx_mcbsp5_irqs,
1203 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
1204 .main_clk = "mcbsp5_fck",
1205 .prcm = {
1206 .omap2 = {
1207 .prcm_reg_id = 1,
1208 .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
1209 .module_offs = CORE_MOD,
1210 .idlest_reg_id = 1,
1211 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
1212 },
1213 },
1214 };
1215
1216 /* 'mcbsp sidetone' class */
1217 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
1218 .sysc_offs = 0x0010,
1219 .sysc_flags = SYSC_HAS_AUTOIDLE,
1220 .sysc_fields = &omap_hwmod_sysc_type1,
1221 };
1222
1223 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
1224 .name = "mcbsp_sidetone",
1225 .sysc = &omap3xxx_mcbsp_sidetone_sysc,
1226 };
1227
1228 /* mcbsp2_sidetone */
1229 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
1230 { .name = "irq", .irq = 4 },
1231 { .irq = -1 }
1232 };
1233
1234 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1235 .name = "mcbsp2_sidetone",
1236 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1237 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
1238 .main_clk = "mcbsp2_fck",
1239 .prcm = {
1240 .omap2 = {
1241 .prcm_reg_id = 1,
1242 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1243 .module_offs = OMAP3430_PER_MOD,
1244 .idlest_reg_id = 1,
1245 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1246 },
1247 },
1248 };
1249
1250 /* mcbsp3_sidetone */
1251 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
1252 { .name = "irq", .irq = 5 },
1253 { .irq = -1 }
1254 };
1255
1256 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1257 .name = "mcbsp3_sidetone",
1258 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1259 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
1260 .main_clk = "mcbsp3_fck",
1261 .prcm = {
1262 .omap2 = {
1263 .prcm_reg_id = 1,
1264 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1265 .module_offs = OMAP3430_PER_MOD,
1266 .idlest_reg_id = 1,
1267 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1268 },
1269 },
1270 };
1271
1272 /* SR common */
1273 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1274 .clkact_shift = 20,
1275 };
1276
1277 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1278 .sysc_offs = 0x24,
1279 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1280 .clockact = CLOCKACT_TEST_ICLK,
1281 .sysc_fields = &omap34xx_sr_sysc_fields,
1282 };
1283
1284 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1285 .name = "smartreflex",
1286 .sysc = &omap34xx_sr_sysc,
1287 .rev = 1,
1288 };
1289
1290 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
1291 .sidle_shift = 24,
1292 .enwkup_shift = 26,
1293 };
1294
1295 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1296 .sysc_offs = 0x38,
1297 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1298 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1299 SYSC_NO_CACHE),
1300 .sysc_fields = &omap36xx_sr_sysc_fields,
1301 };
1302
1303 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1304 .name = "smartreflex",
1305 .sysc = &omap36xx_sr_sysc,
1306 .rev = 2,
1307 };
1308
1309 /* SR1 */
1310 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1311 .sensor_voltdm_name = "mpu_iva",
1312 };
1313
1314 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
1315 { .irq = 18 },
1316 { .irq = -1 }
1317 };
1318
1319 static struct omap_hwmod omap34xx_sr1_hwmod = {
1320 .name = "sr1",
1321 .class = &omap34xx_smartreflex_hwmod_class,
1322 .main_clk = "sr1_fck",
1323 .prcm = {
1324 .omap2 = {
1325 .prcm_reg_id = 1,
1326 .module_bit = OMAP3430_EN_SR1_SHIFT,
1327 .module_offs = WKUP_MOD,
1328 .idlest_reg_id = 1,
1329 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1330 },
1331 },
1332 .dev_attr = &sr1_dev_attr,
1333 .mpu_irqs = omap3_smartreflex_mpu_irqs,
1334 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1335 };
1336
1337 static struct omap_hwmod omap36xx_sr1_hwmod = {
1338 .name = "sr1",
1339 .class = &omap36xx_smartreflex_hwmod_class,
1340 .main_clk = "sr1_fck",
1341 .prcm = {
1342 .omap2 = {
1343 .prcm_reg_id = 1,
1344 .module_bit = OMAP3430_EN_SR1_SHIFT,
1345 .module_offs = WKUP_MOD,
1346 .idlest_reg_id = 1,
1347 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1348 },
1349 },
1350 .dev_attr = &sr1_dev_attr,
1351 .mpu_irqs = omap3_smartreflex_mpu_irqs,
1352 };
1353
1354 /* SR2 */
1355 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1356 .sensor_voltdm_name = "core",
1357 };
1358
1359 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
1360 { .irq = 19 },
1361 { .irq = -1 }
1362 };
1363
1364 static struct omap_hwmod omap34xx_sr2_hwmod = {
1365 .name = "sr2",
1366 .class = &omap34xx_smartreflex_hwmod_class,
1367 .main_clk = "sr2_fck",
1368 .prcm = {
1369 .omap2 = {
1370 .prcm_reg_id = 1,
1371 .module_bit = OMAP3430_EN_SR2_SHIFT,
1372 .module_offs = WKUP_MOD,
1373 .idlest_reg_id = 1,
1374 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1375 },
1376 },
1377 .dev_attr = &sr2_dev_attr,
1378 .mpu_irqs = omap3_smartreflex_core_irqs,
1379 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1380 };
1381
1382 static struct omap_hwmod omap36xx_sr2_hwmod = {
1383 .name = "sr2",
1384 .class = &omap36xx_smartreflex_hwmod_class,
1385 .main_clk = "sr2_fck",
1386 .prcm = {
1387 .omap2 = {
1388 .prcm_reg_id = 1,
1389 .module_bit = OMAP3430_EN_SR2_SHIFT,
1390 .module_offs = WKUP_MOD,
1391 .idlest_reg_id = 1,
1392 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1393 },
1394 },
1395 .dev_attr = &sr2_dev_attr,
1396 .mpu_irqs = omap3_smartreflex_core_irqs,
1397 };
1398
1399 /*
1400 * 'mailbox' class
1401 * mailbox module allowing communication between the on-chip processors
1402 * using a queued mailbox-interrupt mechanism.
1403 */
1404
1405 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1406 .rev_offs = 0x000,
1407 .sysc_offs = 0x010,
1408 .syss_offs = 0x014,
1409 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1410 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1411 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1412 .sysc_fields = &omap_hwmod_sysc_type1,
1413 };
1414
1415 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1416 .name = "mailbox",
1417 .sysc = &omap3xxx_mailbox_sysc,
1418 };
1419
1420 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
1421 { .irq = 26 },
1422 { .irq = -1 }
1423 };
1424
1425 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1426 .name = "mailbox",
1427 .class = &omap3xxx_mailbox_hwmod_class,
1428 .mpu_irqs = omap3xxx_mailbox_irqs,
1429 .main_clk = "mailboxes_ick",
1430 .prcm = {
1431 .omap2 = {
1432 .prcm_reg_id = 1,
1433 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1434 .module_offs = CORE_MOD,
1435 .idlest_reg_id = 1,
1436 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1437 },
1438 },
1439 };
1440
1441 /*
1442 * 'mcspi' class
1443 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1444 * bus
1445 */
1446
1447 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1448 .rev_offs = 0x0000,
1449 .sysc_offs = 0x0010,
1450 .syss_offs = 0x0014,
1451 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1452 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1453 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1454 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1455 .sysc_fields = &omap_hwmod_sysc_type1,
1456 };
1457
1458 static struct omap_hwmod_class omap34xx_mcspi_class = {
1459 .name = "mcspi",
1460 .sysc = &omap34xx_mcspi_sysc,
1461 .rev = OMAP3_MCSPI_REV,
1462 };
1463
1464 /* mcspi1 */
1465 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1466 .num_chipselect = 4,
1467 };
1468
1469 static struct omap_hwmod omap34xx_mcspi1 = {
1470 .name = "mcspi1",
1471 .mpu_irqs = omap2_mcspi1_mpu_irqs,
1472 .sdma_reqs = omap2_mcspi1_sdma_reqs,
1473 .main_clk = "mcspi1_fck",
1474 .prcm = {
1475 .omap2 = {
1476 .module_offs = CORE_MOD,
1477 .prcm_reg_id = 1,
1478 .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
1479 .idlest_reg_id = 1,
1480 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1481 },
1482 },
1483 .class = &omap34xx_mcspi_class,
1484 .dev_attr = &omap_mcspi1_dev_attr,
1485 };
1486
1487 /* mcspi2 */
1488 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1489 .num_chipselect = 2,
1490 };
1491
1492 static struct omap_hwmod omap34xx_mcspi2 = {
1493 .name = "mcspi2",
1494 .mpu_irqs = omap2_mcspi2_mpu_irqs,
1495 .sdma_reqs = omap2_mcspi2_sdma_reqs,
1496 .main_clk = "mcspi2_fck",
1497 .prcm = {
1498 .omap2 = {
1499 .module_offs = CORE_MOD,
1500 .prcm_reg_id = 1,
1501 .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
1502 .idlest_reg_id = 1,
1503 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1504 },
1505 },
1506 .class = &omap34xx_mcspi_class,
1507 .dev_attr = &omap_mcspi2_dev_attr,
1508 };
1509
1510 /* mcspi3 */
1511 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
1512 { .name = "irq", .irq = 91 }, /* 91 */
1513 { .irq = -1 }
1514 };
1515
1516 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
1517 { .name = "tx0", .dma_req = 15 },
1518 { .name = "rx0", .dma_req = 16 },
1519 { .name = "tx1", .dma_req = 23 },
1520 { .name = "rx1", .dma_req = 24 },
1521 { .dma_req = -1 }
1522 };
1523
1524 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1525 .num_chipselect = 2,
1526 };
1527
1528 static struct omap_hwmod omap34xx_mcspi3 = {
1529 .name = "mcspi3",
1530 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
1531 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
1532 .main_clk = "mcspi3_fck",
1533 .prcm = {
1534 .omap2 = {
1535 .module_offs = CORE_MOD,
1536 .prcm_reg_id = 1,
1537 .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
1538 .idlest_reg_id = 1,
1539 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1540 },
1541 },
1542 .class = &omap34xx_mcspi_class,
1543 .dev_attr = &omap_mcspi3_dev_attr,
1544 };
1545
1546 /* mcspi4 */
1547 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
1548 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
1549 { .irq = -1 }
1550 };
1551
1552 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
1553 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
1554 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
1555 { .dma_req = -1 }
1556 };
1557
1558 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1559 .num_chipselect = 1,
1560 };
1561
1562 static struct omap_hwmod omap34xx_mcspi4 = {
1563 .name = "mcspi4",
1564 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
1565 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
1566 .main_clk = "mcspi4_fck",
1567 .prcm = {
1568 .omap2 = {
1569 .module_offs = CORE_MOD,
1570 .prcm_reg_id = 1,
1571 .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
1572 .idlest_reg_id = 1,
1573 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1574 },
1575 },
1576 .class = &omap34xx_mcspi_class,
1577 .dev_attr = &omap_mcspi4_dev_attr,
1578 };
1579
1580 /* usbhsotg */
1581 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1582 .rev_offs = 0x0400,
1583 .sysc_offs = 0x0404,
1584 .syss_offs = 0x0408,
1585 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1586 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1587 SYSC_HAS_AUTOIDLE),
1588 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1589 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1590 .sysc_fields = &omap_hwmod_sysc_type1,
1591 };
1592
1593 static struct omap_hwmod_class usbotg_class = {
1594 .name = "usbotg",
1595 .sysc = &omap3xxx_usbhsotg_sysc,
1596 };
1597
1598 /* usb_otg_hs */
1599 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
1600
1601 { .name = "mc", .irq = 92 },
1602 { .name = "dma", .irq = 93 },
1603 { .irq = -1 }
1604 };
1605
1606 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1607 .name = "usb_otg_hs",
1608 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
1609 .main_clk = "hsotgusb_ick",
1610 .prcm = {
1611 .omap2 = {
1612 .prcm_reg_id = 1,
1613 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1614 .module_offs = CORE_MOD,
1615 .idlest_reg_id = 1,
1616 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1617 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
1618 },
1619 },
1620 .class = &usbotg_class,
1621
1622 /*
1623 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
1624 * broken when autoidle is enabled
1625 * workaround is to disable the autoidle bit at module level.
1626 */
1627 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
1628 | HWMOD_SWSUP_MSTANDBY,
1629 };
1630
1631 /* usb_otg_hs */
1632 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
1633
1634 { .name = "mc", .irq = 71 },
1635 { .irq = -1 }
1636 };
1637
1638 static struct omap_hwmod_class am35xx_usbotg_class = {
1639 .name = "am35xx_usbotg",
1640 .sysc = NULL,
1641 };
1642
1643 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1644 .name = "am35x_otg_hs",
1645 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
1646 .main_clk = NULL,
1647 .prcm = {
1648 .omap2 = {
1649 },
1650 },
1651 .class = &am35xx_usbotg_class,
1652 };
1653
1654 /* MMC/SD/SDIO common */
1655 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1656 .rev_offs = 0x1fc,
1657 .sysc_offs = 0x10,
1658 .syss_offs = 0x14,
1659 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1660 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1661 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1662 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1663 .sysc_fields = &omap_hwmod_sysc_type1,
1664 };
1665
1666 static struct omap_hwmod_class omap34xx_mmc_class = {
1667 .name = "mmc",
1668 .sysc = &omap34xx_mmc_sysc,
1669 };
1670
1671 /* MMC/SD/SDIO1 */
1672
1673 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
1674 { .irq = 83, },
1675 { .irq = -1 }
1676 };
1677
1678 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
1679 { .name = "tx", .dma_req = 61, },
1680 { .name = "rx", .dma_req = 62, },
1681 { .dma_req = -1 }
1682 };
1683
1684 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1685 { .role = "dbck", .clk = "omap_32k_fck", },
1686 };
1687
1688 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1689 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1690 };
1691
1692 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1693 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
1694 .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1695 OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1696 };
1697
1698 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1699 .name = "mmc1",
1700 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
1701 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
1702 .opt_clks = omap34xx_mmc1_opt_clks,
1703 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1704 .main_clk = "mmchs1_fck",
1705 .prcm = {
1706 .omap2 = {
1707 .module_offs = CORE_MOD,
1708 .prcm_reg_id = 1,
1709 .module_bit = OMAP3430_EN_MMC1_SHIFT,
1710 .idlest_reg_id = 1,
1711 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1712 },
1713 },
1714 .dev_attr = &mmc1_pre_es3_dev_attr,
1715 .class = &omap34xx_mmc_class,
1716 };
1717
1718 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1719 .name = "mmc1",
1720 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
1721 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
1722 .opt_clks = omap34xx_mmc1_opt_clks,
1723 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1724 .main_clk = "mmchs1_fck",
1725 .prcm = {
1726 .omap2 = {
1727 .module_offs = CORE_MOD,
1728 .prcm_reg_id = 1,
1729 .module_bit = OMAP3430_EN_MMC1_SHIFT,
1730 .idlest_reg_id = 1,
1731 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1732 },
1733 },
1734 .dev_attr = &mmc1_dev_attr,
1735 .class = &omap34xx_mmc_class,
1736 };
1737
1738 /* MMC/SD/SDIO2 */
1739
1740 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
1741 { .irq = INT_24XX_MMC2_IRQ, },
1742 { .irq = -1 }
1743 };
1744
1745 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
1746 { .name = "tx", .dma_req = 47, },
1747 { .name = "rx", .dma_req = 48, },
1748 { .dma_req = -1 }
1749 };
1750
1751 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1752 { .role = "dbck", .clk = "omap_32k_fck", },
1753 };
1754
1755 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1756 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
1757 .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1758 };
1759
1760 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1761 .name = "mmc2",
1762 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
1763 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
1764 .opt_clks = omap34xx_mmc2_opt_clks,
1765 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1766 .main_clk = "mmchs2_fck",
1767 .prcm = {
1768 .omap2 = {
1769 .module_offs = CORE_MOD,
1770 .prcm_reg_id = 1,
1771 .module_bit = OMAP3430_EN_MMC2_SHIFT,
1772 .idlest_reg_id = 1,
1773 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1774 },
1775 },
1776 .dev_attr = &mmc2_pre_es3_dev_attr,
1777 .class = &omap34xx_mmc_class,
1778 };
1779
1780 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1781 .name = "mmc2",
1782 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
1783 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
1784 .opt_clks = omap34xx_mmc2_opt_clks,
1785 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1786 .main_clk = "mmchs2_fck",
1787 .prcm = {
1788 .omap2 = {
1789 .module_offs = CORE_MOD,
1790 .prcm_reg_id = 1,
1791 .module_bit = OMAP3430_EN_MMC2_SHIFT,
1792 .idlest_reg_id = 1,
1793 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1794 },
1795 },
1796 .class = &omap34xx_mmc_class,
1797 };
1798
1799 /* MMC/SD/SDIO3 */
1800
1801 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
1802 { .irq = 94, },
1803 { .irq = -1 }
1804 };
1805
1806 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
1807 { .name = "tx", .dma_req = 77, },
1808 { .name = "rx", .dma_req = 78, },
1809 { .dma_req = -1 }
1810 };
1811
1812 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1813 { .role = "dbck", .clk = "omap_32k_fck", },
1814 };
1815
1816 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1817 .name = "mmc3",
1818 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
1819 .sdma_reqs = omap34xx_mmc3_sdma_reqs,
1820 .opt_clks = omap34xx_mmc3_opt_clks,
1821 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1822 .main_clk = "mmchs3_fck",
1823 .prcm = {
1824 .omap2 = {
1825 .prcm_reg_id = 1,
1826 .module_bit = OMAP3430_EN_MMC3_SHIFT,
1827 .idlest_reg_id = 1,
1828 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1829 },
1830 },
1831 .class = &omap34xx_mmc_class,
1832 };
1833
1834 /*
1835 * 'usb_host_hs' class
1836 * high-speed multi-port usb host controller
1837 */
1838
1839 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1840 .rev_offs = 0x0000,
1841 .sysc_offs = 0x0010,
1842 .syss_offs = 0x0014,
1843 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1844 SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1845 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1846 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1847 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1848 .sysc_fields = &omap_hwmod_sysc_type1,
1849 };
1850
1851 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1852 .name = "usb_host_hs",
1853 .sysc = &omap3xxx_usb_host_hs_sysc,
1854 };
1855
1856 static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
1857 { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
1858 };
1859
1860 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
1861 { .name = "ohci-irq", .irq = 76 },
1862 { .name = "ehci-irq", .irq = 77 },
1863 { .irq = -1 }
1864 };
1865
1866 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1867 .name = "usb_host_hs",
1868 .class = &omap3xxx_usb_host_hs_hwmod_class,
1869 .clkdm_name = "l3_init_clkdm",
1870 .mpu_irqs = omap3xxx_usb_host_hs_irqs,
1871 .main_clk = "usbhost_48m_fck",
1872 .prcm = {
1873 .omap2 = {
1874 .module_offs = OMAP3430ES2_USBHOST_MOD,
1875 .prcm_reg_id = 1,
1876 .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
1877 .idlest_reg_id = 1,
1878 .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1879 .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
1880 },
1881 },
1882 .opt_clks = omap3xxx_usb_host_hs_opt_clks,
1883 .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
1884
1885 /*
1886 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1887 * id: i660
1888 *
1889 * Description:
1890 * In the following configuration :
1891 * - USBHOST module is set to smart-idle mode
1892 * - PRCM asserts idle_req to the USBHOST module ( This typically
1893 * happens when the system is going to a low power mode : all ports
1894 * have been suspended, the master part of the USBHOST module has
1895 * entered the standby state, and SW has cut the functional clocks)
1896 * - an USBHOST interrupt occurs before the module is able to answer
1897 * idle_ack, typically a remote wakeup IRQ.
1898 * Then the USB HOST module will enter a deadlock situation where it
1899 * is no more accessible nor functional.
1900 *
1901 * Workaround:
1902 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1903 */
1904
1905 /*
1906 * Errata: USB host EHCI may stall when entering smart-standby mode
1907 * Id: i571
1908 *
1909 * Description:
1910 * When the USBHOST module is set to smart-standby mode, and when it is
1911 * ready to enter the standby state (i.e. all ports are suspended and
1912 * all attached devices are in suspend mode), then it can wrongly assert
1913 * the Mstandby signal too early while there are still some residual OCP
1914 * transactions ongoing. If this condition occurs, the internal state
1915 * machine may go to an undefined state and the USB link may be stuck
1916 * upon the next resume.
1917 *
1918 * Workaround:
1919 * Don't use smart standby; use only force standby,
1920 * hence HWMOD_SWSUP_MSTANDBY
1921 */
1922
1923 /*
1924 * During system boot; If the hwmod framework resets the module
1925 * the module will have smart idle settings; which can lead to deadlock
1926 * (above Errata Id:i660); so, dont reset the module during boot;
1927 * Use HWMOD_INIT_NO_RESET.
1928 */
1929
1930 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
1931 HWMOD_INIT_NO_RESET,
1932 };
1933
1934 /*
1935 * 'usb_tll_hs' class
1936 * usb_tll_hs module is the adapter on the usb_host_hs ports
1937 */
1938 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
1939 .rev_offs = 0x0000,
1940 .sysc_offs = 0x0010,
1941 .syss_offs = 0x0014,
1942 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1943 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1944 SYSC_HAS_AUTOIDLE),
1945 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1946 .sysc_fields = &omap_hwmod_sysc_type1,
1947 };
1948
1949 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
1950 .name = "usb_tll_hs",
1951 .sysc = &omap3xxx_usb_tll_hs_sysc,
1952 };
1953
1954 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
1955 { .name = "tll-irq", .irq = 78 },
1956 { .irq = -1 }
1957 };
1958
1959 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
1960 .name = "usb_tll_hs",
1961 .class = &omap3xxx_usb_tll_hs_hwmod_class,
1962 .clkdm_name = "l3_init_clkdm",
1963 .mpu_irqs = omap3xxx_usb_tll_hs_irqs,
1964 .main_clk = "usbtll_fck",
1965 .prcm = {
1966 .omap2 = {
1967 .module_offs = CORE_MOD,
1968 .prcm_reg_id = 3,
1969 .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1970 .idlest_reg_id = 3,
1971 .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
1972 },
1973 },
1974 };
1975
1976 static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
1977 .name = "hdq1w",
1978 .mpu_irqs = omap2_hdq1w_mpu_irqs,
1979 .main_clk = "hdq_fck",
1980 .prcm = {
1981 .omap2 = {
1982 .module_offs = CORE_MOD,
1983 .prcm_reg_id = 1,
1984 .module_bit = OMAP3430_EN_HDQ_SHIFT,
1985 .idlest_reg_id = 1,
1986 .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
1987 },
1988 },
1989 .class = &omap2_hdq1w_class,
1990 };
1991
1992 /*
1993 * '32K sync counter' class
1994 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
1995 */
1996 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
1997 .rev_offs = 0x0000,
1998 .sysc_offs = 0x0004,
1999 .sysc_flags = SYSC_HAS_SIDLEMODE,
2000 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
2001 .sysc_fields = &omap_hwmod_sysc_type1,
2002 };
2003
2004 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
2005 .name = "counter",
2006 .sysc = &omap3xxx_counter_sysc,
2007 };
2008
2009 static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
2010 .name = "counter_32k",
2011 .class = &omap3xxx_counter_hwmod_class,
2012 .clkdm_name = "wkup_clkdm",
2013 .flags = HWMOD_SWSUP_SIDLE,
2014 .main_clk = "wkup_32k_fck",
2015 .prcm = {
2016 .omap2 = {
2017 .module_offs = WKUP_MOD,
2018 .prcm_reg_id = 1,
2019 .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
2020 .idlest_reg_id = 1,
2021 .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
2022 },
2023 },
2024 };
2025
2026 /*
2027 * interfaces
2028 */
2029
2030 /* L3 -> L4_CORE interface */
2031 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
2032 .master = &omap3xxx_l3_main_hwmod,
2033 .slave = &omap3xxx_l4_core_hwmod,
2034 .user = OCP_USER_MPU | OCP_USER_SDMA,
2035 };
2036
2037 /* L3 -> L4_PER interface */
2038 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
2039 .master = &omap3xxx_l3_main_hwmod,
2040 .slave = &omap3xxx_l4_per_hwmod,
2041 .user = OCP_USER_MPU | OCP_USER_SDMA,
2042 };
2043
2044 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
2045 {
2046 .pa_start = 0x68000000,
2047 .pa_end = 0x6800ffff,
2048 .flags = ADDR_TYPE_RT,
2049 },
2050 { }
2051 };
2052
2053 /* MPU -> L3 interface */
2054 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
2055 .master = &omap3xxx_mpu_hwmod,
2056 .slave = &omap3xxx_l3_main_hwmod,
2057 .addr = omap3xxx_l3_main_addrs,
2058 .user = OCP_USER_MPU,
2059 };
2060
2061 /* DSS -> l3 */
2062 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
2063 .master = &omap3430es1_dss_core_hwmod,
2064 .slave = &omap3xxx_l3_main_hwmod,
2065 .user = OCP_USER_MPU | OCP_USER_SDMA,
2066 };
2067
2068 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
2069 .master = &omap3xxx_dss_core_hwmod,
2070 .slave = &omap3xxx_l3_main_hwmod,
2071 .fw = {
2072 .omap2 = {
2073 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
2074 .flags = OMAP_FIREWALL_L3,
2075 }
2076 },
2077 .user = OCP_USER_MPU | OCP_USER_SDMA,
2078 };
2079
2080 /* l3_core -> usbhsotg interface */
2081 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
2082 .master = &omap3xxx_usbhsotg_hwmod,
2083 .slave = &omap3xxx_l3_main_hwmod,
2084 .clk = "core_l3_ick",
2085 .user = OCP_USER_MPU,
2086 };
2087
2088 /* l3_core -> am35xx_usbhsotg interface */
2089 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
2090 .master = &am35xx_usbhsotg_hwmod,
2091 .slave = &omap3xxx_l3_main_hwmod,
2092 .clk = "core_l3_ick",
2093 .user = OCP_USER_MPU,
2094 };
2095 /* L4_CORE -> L4_WKUP interface */
2096 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
2097 .master = &omap3xxx_l4_core_hwmod,
2098 .slave = &omap3xxx_l4_wkup_hwmod,
2099 .user = OCP_USER_MPU | OCP_USER_SDMA,
2100 };
2101
2102 /* L4 CORE -> MMC1 interface */
2103 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
2104 .master = &omap3xxx_l4_core_hwmod,
2105 .slave = &omap3xxx_pre_es3_mmc1_hwmod,
2106 .clk = "mmchs1_ick",
2107 .addr = omap2430_mmc1_addr_space,
2108 .user = OCP_USER_MPU | OCP_USER_SDMA,
2109 .flags = OMAP_FIREWALL_L4
2110 };
2111
2112 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
2113 .master = &omap3xxx_l4_core_hwmod,
2114 .slave = &omap3xxx_es3plus_mmc1_hwmod,
2115 .clk = "mmchs1_ick",
2116 .addr = omap2430_mmc1_addr_space,
2117 .user = OCP_USER_MPU | OCP_USER_SDMA,
2118 .flags = OMAP_FIREWALL_L4
2119 };
2120
2121 /* L4 CORE -> MMC2 interface */
2122 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
2123 .master = &omap3xxx_l4_core_hwmod,
2124 .slave = &omap3xxx_pre_es3_mmc2_hwmod,
2125 .clk = "mmchs2_ick",
2126 .addr = omap2430_mmc2_addr_space,
2127 .user = OCP_USER_MPU | OCP_USER_SDMA,
2128 .flags = OMAP_FIREWALL_L4
2129 };
2130
2131 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2132 .master = &omap3xxx_l4_core_hwmod,
2133 .slave = &omap3xxx_es3plus_mmc2_hwmod,
2134 .clk = "mmchs2_ick",
2135 .addr = omap2430_mmc2_addr_space,
2136 .user = OCP_USER_MPU | OCP_USER_SDMA,
2137 .flags = OMAP_FIREWALL_L4
2138 };
2139
2140 /* L4 CORE -> MMC3 interface */
2141 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
2142 {
2143 .pa_start = 0x480ad000,
2144 .pa_end = 0x480ad1ff,
2145 .flags = ADDR_TYPE_RT,
2146 },
2147 { }
2148 };
2149
2150 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2151 .master = &omap3xxx_l4_core_hwmod,
2152 .slave = &omap3xxx_mmc3_hwmod,
2153 .clk = "mmchs3_ick",
2154 .addr = omap3xxx_mmc3_addr_space,
2155 .user = OCP_USER_MPU | OCP_USER_SDMA,
2156 .flags = OMAP_FIREWALL_L4
2157 };
2158
2159 /* L4 CORE -> UART1 interface */
2160 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
2161 {
2162 .pa_start = OMAP3_UART1_BASE,
2163 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
2164 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2165 },
2166 { }
2167 };
2168
2169 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2170 .master = &omap3xxx_l4_core_hwmod,
2171 .slave = &omap3xxx_uart1_hwmod,
2172 .clk = "uart1_ick",
2173 .addr = omap3xxx_uart1_addr_space,
2174 .user = OCP_USER_MPU | OCP_USER_SDMA,
2175 };
2176
2177 /* L4 CORE -> UART2 interface */
2178 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
2179 {
2180 .pa_start = OMAP3_UART2_BASE,
2181 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
2182 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2183 },
2184 { }
2185 };
2186
2187 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2188 .master = &omap3xxx_l4_core_hwmod,
2189 .slave = &omap3xxx_uart2_hwmod,
2190 .clk = "uart2_ick",
2191 .addr = omap3xxx_uart2_addr_space,
2192 .user = OCP_USER_MPU | OCP_USER_SDMA,
2193 };
2194
2195 /* L4 PER -> UART3 interface */
2196 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
2197 {
2198 .pa_start = OMAP3_UART3_BASE,
2199 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
2200 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2201 },
2202 { }
2203 };
2204
2205 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2206 .master = &omap3xxx_l4_per_hwmod,
2207 .slave = &omap3xxx_uart3_hwmod,
2208 .clk = "uart3_ick",
2209 .addr = omap3xxx_uart3_addr_space,
2210 .user = OCP_USER_MPU | OCP_USER_SDMA,
2211 };
2212
2213 /* L4 PER -> UART4 interface */
2214 static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
2215 {
2216 .pa_start = OMAP3_UART4_BASE,
2217 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
2218 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2219 },
2220 { }
2221 };
2222
2223 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2224 .master = &omap3xxx_l4_per_hwmod,
2225 .slave = &omap36xx_uart4_hwmod,
2226 .clk = "uart4_ick",
2227 .addr = omap36xx_uart4_addr_space,
2228 .user = OCP_USER_MPU | OCP_USER_SDMA,
2229 };
2230
2231 /* AM35xx: L4 CORE -> UART4 interface */
2232 static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
2233 {
2234 .pa_start = OMAP3_UART4_AM35XX_BASE,
2235 .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
2236 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2237 },
2238 };
2239
2240 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2241 .master = &omap3xxx_l4_core_hwmod,
2242 .slave = &am35xx_uart4_hwmod,
2243 .clk = "uart4_ick",
2244 .addr = am35xx_uart4_addr_space,
2245 .user = OCP_USER_MPU | OCP_USER_SDMA,
2246 };
2247
2248 /* L4 CORE -> I2C1 interface */
2249 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2250 .master = &omap3xxx_l4_core_hwmod,
2251 .slave = &omap3xxx_i2c1_hwmod,
2252 .clk = "i2c1_ick",
2253 .addr = omap2_i2c1_addr_space,
2254 .fw = {
2255 .omap2 = {
2256 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
2257 .l4_prot_group = 7,
2258 .flags = OMAP_FIREWALL_L4,
2259 }
2260 },
2261 .user = OCP_USER_MPU | OCP_USER_SDMA,
2262 };
2263
2264 /* L4 CORE -> I2C2 interface */
2265 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2266 .master = &omap3xxx_l4_core_hwmod,
2267 .slave = &omap3xxx_i2c2_hwmod,
2268 .clk = "i2c2_ick",
2269 .addr = omap2_i2c2_addr_space,
2270 .fw = {
2271 .omap2 = {
2272 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
2273 .l4_prot_group = 7,
2274 .flags = OMAP_FIREWALL_L4,
2275 }
2276 },
2277 .user = OCP_USER_MPU | OCP_USER_SDMA,
2278 };
2279
2280 /* L4 CORE -> I2C3 interface */
2281 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
2282 {
2283 .pa_start = 0x48060000,
2284 .pa_end = 0x48060000 + SZ_128 - 1,
2285 .flags = ADDR_TYPE_RT,
2286 },
2287 { }
2288 };
2289
2290 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2291 .master = &omap3xxx_l4_core_hwmod,
2292 .slave = &omap3xxx_i2c3_hwmod,
2293 .clk = "i2c3_ick",
2294 .addr = omap3xxx_i2c3_addr_space,
2295 .fw = {
2296 .omap2 = {
2297 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
2298 .l4_prot_group = 7,
2299 .flags = OMAP_FIREWALL_L4,
2300 }
2301 },
2302 .user = OCP_USER_MPU | OCP_USER_SDMA,
2303 };
2304
2305 /* L4 CORE -> SR1 interface */
2306 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
2307 {
2308 .pa_start = OMAP34XX_SR1_BASE,
2309 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
2310 .flags = ADDR_TYPE_RT,
2311 },
2312 { }
2313 };
2314
2315 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2316 .master = &omap3xxx_l4_core_hwmod,
2317 .slave = &omap34xx_sr1_hwmod,
2318 .clk = "sr_l4_ick",
2319 .addr = omap3_sr1_addr_space,
2320 .user = OCP_USER_MPU,
2321 };
2322
2323 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2324 .master = &omap3xxx_l4_core_hwmod,
2325 .slave = &omap36xx_sr1_hwmod,
2326 .clk = "sr_l4_ick",
2327 .addr = omap3_sr1_addr_space,
2328 .user = OCP_USER_MPU,
2329 };
2330
2331 /* L4 CORE -> SR1 interface */
2332 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
2333 {
2334 .pa_start = OMAP34XX_SR2_BASE,
2335 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
2336 .flags = ADDR_TYPE_RT,
2337 },
2338 { }
2339 };
2340
2341 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2342 .master = &omap3xxx_l4_core_hwmod,
2343 .slave = &omap34xx_sr2_hwmod,
2344 .clk = "sr_l4_ick",
2345 .addr = omap3_sr2_addr_space,
2346 .user = OCP_USER_MPU,
2347 };
2348
2349 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2350 .master = &omap3xxx_l4_core_hwmod,
2351 .slave = &omap36xx_sr2_hwmod,
2352 .clk = "sr_l4_ick",
2353 .addr = omap3_sr2_addr_space,
2354 .user = OCP_USER_MPU,
2355 };
2356
2357 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
2358 {
2359 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
2360 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
2361 .flags = ADDR_TYPE_RT
2362 },
2363 { }
2364 };
2365
2366 /* l4_core -> usbhsotg */
2367 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2368 .master = &omap3xxx_l4_core_hwmod,
2369 .slave = &omap3xxx_usbhsotg_hwmod,
2370 .clk = "l4_ick",
2371 .addr = omap3xxx_usbhsotg_addrs,
2372 .user = OCP_USER_MPU,
2373 };
2374
2375 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
2376 {
2377 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
2378 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
2379 .flags = ADDR_TYPE_RT
2380 },
2381 { }
2382 };
2383
2384 /* l4_core -> usbhsotg */
2385 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2386 .master = &omap3xxx_l4_core_hwmod,
2387 .slave = &am35xx_usbhsotg_hwmod,
2388 .clk = "l4_ick",
2389 .addr = am35xx_usbhsotg_addrs,
2390 .user = OCP_USER_MPU,
2391 };
2392
2393 /* L4_WKUP -> L4_SEC interface */
2394 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2395 .master = &omap3xxx_l4_wkup_hwmod,
2396 .slave = &omap3xxx_l4_sec_hwmod,
2397 .user = OCP_USER_MPU | OCP_USER_SDMA,
2398 };
2399
2400 /* IVA2 <- L3 interface */
2401 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2402 .master = &omap3xxx_l3_main_hwmod,
2403 .slave = &omap3xxx_iva_hwmod,
2404 .clk = "core_l3_ick",
2405 .user = OCP_USER_MPU | OCP_USER_SDMA,
2406 };
2407
2408 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
2409 {
2410 .pa_start = 0x48318000,
2411 .pa_end = 0x48318000 + SZ_1K - 1,
2412 .flags = ADDR_TYPE_RT
2413 },
2414 { }
2415 };
2416
2417 /* l4_wkup -> timer1 */
2418 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2419 .master = &omap3xxx_l4_wkup_hwmod,
2420 .slave = &omap3xxx_timer1_hwmod,
2421 .clk = "gpt1_ick",
2422 .addr = omap3xxx_timer1_addrs,
2423 .user = OCP_USER_MPU | OCP_USER_SDMA,
2424 };
2425
2426 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
2427 {
2428 .pa_start = 0x49032000,
2429 .pa_end = 0x49032000 + SZ_1K - 1,
2430 .flags = ADDR_TYPE_RT
2431 },
2432 { }
2433 };
2434
2435 /* l4_per -> timer2 */
2436 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2437 .master = &omap3xxx_l4_per_hwmod,
2438 .slave = &omap3xxx_timer2_hwmod,
2439 .clk = "gpt2_ick",
2440 .addr = omap3xxx_timer2_addrs,
2441 .user = OCP_USER_MPU | OCP_USER_SDMA,
2442 };
2443
2444 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
2445 {
2446 .pa_start = 0x49034000,
2447 .pa_end = 0x49034000 + SZ_1K - 1,
2448 .flags = ADDR_TYPE_RT
2449 },
2450 { }
2451 };
2452
2453 /* l4_per -> timer3 */
2454 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2455 .master = &omap3xxx_l4_per_hwmod,
2456 .slave = &omap3xxx_timer3_hwmod,
2457 .clk = "gpt3_ick",
2458 .addr = omap3xxx_timer3_addrs,
2459 .user = OCP_USER_MPU | OCP_USER_SDMA,
2460 };
2461
2462 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
2463 {
2464 .pa_start = 0x49036000,
2465 .pa_end = 0x49036000 + SZ_1K - 1,
2466 .flags = ADDR_TYPE_RT
2467 },
2468 { }
2469 };
2470
2471 /* l4_per -> timer4 */
2472 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2473 .master = &omap3xxx_l4_per_hwmod,
2474 .slave = &omap3xxx_timer4_hwmod,
2475 .clk = "gpt4_ick",
2476 .addr = omap3xxx_timer4_addrs,
2477 .user = OCP_USER_MPU | OCP_USER_SDMA,
2478 };
2479
2480 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
2481 {
2482 .pa_start = 0x49038000,
2483 .pa_end = 0x49038000 + SZ_1K - 1,
2484 .flags = ADDR_TYPE_RT
2485 },
2486 { }
2487 };
2488
2489 /* l4_per -> timer5 */
2490 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2491 .master = &omap3xxx_l4_per_hwmod,
2492 .slave = &omap3xxx_timer5_hwmod,
2493 .clk = "gpt5_ick",
2494 .addr = omap3xxx_timer5_addrs,
2495 .user = OCP_USER_MPU | OCP_USER_SDMA,
2496 };
2497
2498 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
2499 {
2500 .pa_start = 0x4903A000,
2501 .pa_end = 0x4903A000 + SZ_1K - 1,
2502 .flags = ADDR_TYPE_RT
2503 },
2504 { }
2505 };
2506
2507 /* l4_per -> timer6 */
2508 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2509 .master = &omap3xxx_l4_per_hwmod,
2510 .slave = &omap3xxx_timer6_hwmod,
2511 .clk = "gpt6_ick",
2512 .addr = omap3xxx_timer6_addrs,
2513 .user = OCP_USER_MPU | OCP_USER_SDMA,
2514 };
2515
2516 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
2517 {
2518 .pa_start = 0x4903C000,
2519 .pa_end = 0x4903C000 + SZ_1K - 1,
2520 .flags = ADDR_TYPE_RT
2521 },
2522 { }
2523 };
2524
2525 /* l4_per -> timer7 */
2526 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2527 .master = &omap3xxx_l4_per_hwmod,
2528 .slave = &omap3xxx_timer7_hwmod,
2529 .clk = "gpt7_ick",
2530 .addr = omap3xxx_timer7_addrs,
2531 .user = OCP_USER_MPU | OCP_USER_SDMA,
2532 };
2533
2534 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
2535 {
2536 .pa_start = 0x4903E000,
2537 .pa_end = 0x4903E000 + SZ_1K - 1,
2538 .flags = ADDR_TYPE_RT
2539 },
2540 { }
2541 };
2542
2543 /* l4_per -> timer8 */
2544 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2545 .master = &omap3xxx_l4_per_hwmod,
2546 .slave = &omap3xxx_timer8_hwmod,
2547 .clk = "gpt8_ick",
2548 .addr = omap3xxx_timer8_addrs,
2549 .user = OCP_USER_MPU | OCP_USER_SDMA,
2550 };
2551
2552 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
2553 {
2554 .pa_start = 0x49040000,
2555 .pa_end = 0x49040000 + SZ_1K - 1,
2556 .flags = ADDR_TYPE_RT
2557 },
2558 { }
2559 };
2560
2561 /* l4_per -> timer9 */
2562 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2563 .master = &omap3xxx_l4_per_hwmod,
2564 .slave = &omap3xxx_timer9_hwmod,
2565 .clk = "gpt9_ick",
2566 .addr = omap3xxx_timer9_addrs,
2567 .user = OCP_USER_MPU | OCP_USER_SDMA,
2568 };
2569
2570 /* l4_core -> timer10 */
2571 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2572 .master = &omap3xxx_l4_core_hwmod,
2573 .slave = &omap3xxx_timer10_hwmod,
2574 .clk = "gpt10_ick",
2575 .addr = omap2_timer10_addrs,
2576 .user = OCP_USER_MPU | OCP_USER_SDMA,
2577 };
2578
2579 /* l4_core -> timer11 */
2580 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2581 .master = &omap3xxx_l4_core_hwmod,
2582 .slave = &omap3xxx_timer11_hwmod,
2583 .clk = "gpt11_ick",
2584 .addr = omap2_timer11_addrs,
2585 .user = OCP_USER_MPU | OCP_USER_SDMA,
2586 };
2587
2588 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
2589 {
2590 .pa_start = 0x48304000,
2591 .pa_end = 0x48304000 + SZ_1K - 1,
2592 .flags = ADDR_TYPE_RT
2593 },
2594 { }
2595 };
2596
2597 /* l4_core -> timer12 */
2598 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2599 .master = &omap3xxx_l4_sec_hwmod,
2600 .slave = &omap3xxx_timer12_hwmod,
2601 .clk = "gpt12_ick",
2602 .addr = omap3xxx_timer12_addrs,
2603 .user = OCP_USER_MPU | OCP_USER_SDMA,
2604 };
2605
2606 /* l4_wkup -> wd_timer2 */
2607 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
2608 {
2609 .pa_start = 0x48314000,
2610 .pa_end = 0x4831407f,
2611 .flags = ADDR_TYPE_RT
2612 },
2613 { }
2614 };
2615
2616 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2617 .master = &omap3xxx_l4_wkup_hwmod,
2618 .slave = &omap3xxx_wd_timer2_hwmod,
2619 .clk = "wdt2_ick",
2620 .addr = omap3xxx_wd_timer2_addrs,
2621 .user = OCP_USER_MPU | OCP_USER_SDMA,
2622 };
2623
2624 /* l4_core -> dss */
2625 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2626 .master = &omap3xxx_l4_core_hwmod,
2627 .slave = &omap3430es1_dss_core_hwmod,
2628 .clk = "dss_ick",
2629 .addr = omap2_dss_addrs,
2630 .fw = {
2631 .omap2 = {
2632 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2633 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2634 .flags = OMAP_FIREWALL_L4,
2635 }
2636 },
2637 .user = OCP_USER_MPU | OCP_USER_SDMA,
2638 };
2639
2640 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2641 .master = &omap3xxx_l4_core_hwmod,
2642 .slave = &omap3xxx_dss_core_hwmod,
2643 .clk = "dss_ick",
2644 .addr = omap2_dss_addrs,
2645 .fw = {
2646 .omap2 = {
2647 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2648 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2649 .flags = OMAP_FIREWALL_L4,
2650 }
2651 },
2652 .user = OCP_USER_MPU | OCP_USER_SDMA,
2653 };
2654
2655 /* l4_core -> dss_dispc */
2656 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2657 .master = &omap3xxx_l4_core_hwmod,
2658 .slave = &omap3xxx_dss_dispc_hwmod,
2659 .clk = "dss_ick",
2660 .addr = omap2_dss_dispc_addrs,
2661 .fw = {
2662 .omap2 = {
2663 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2664 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2665 .flags = OMAP_FIREWALL_L4,
2666 }
2667 },
2668 .user = OCP_USER_MPU | OCP_USER_SDMA,
2669 };
2670
2671 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
2672 {
2673 .pa_start = 0x4804FC00,
2674 .pa_end = 0x4804FFFF,
2675 .flags = ADDR_TYPE_RT
2676 },
2677 { }
2678 };
2679
2680 /* l4_core -> dss_dsi1 */
2681 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2682 .master = &omap3xxx_l4_core_hwmod,
2683 .slave = &omap3xxx_dss_dsi1_hwmod,
2684 .clk = "dss_ick",
2685 .addr = omap3xxx_dss_dsi1_addrs,
2686 .fw = {
2687 .omap2 = {
2688 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2689 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2690 .flags = OMAP_FIREWALL_L4,
2691 }
2692 },
2693 .user = OCP_USER_MPU | OCP_USER_SDMA,
2694 };
2695
2696 /* l4_core -> dss_rfbi */
2697 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2698 .master = &omap3xxx_l4_core_hwmod,
2699 .slave = &omap3xxx_dss_rfbi_hwmod,
2700 .clk = "dss_ick",
2701 .addr = omap2_dss_rfbi_addrs,
2702 .fw = {
2703 .omap2 = {
2704 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2705 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2706 .flags = OMAP_FIREWALL_L4,
2707 }
2708 },
2709 .user = OCP_USER_MPU | OCP_USER_SDMA,
2710 };
2711
2712 /* l4_core -> dss_venc */
2713 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2714 .master = &omap3xxx_l4_core_hwmod,
2715 .slave = &omap3xxx_dss_venc_hwmod,
2716 .clk = "dss_ick",
2717 .addr = omap2_dss_venc_addrs,
2718 .fw = {
2719 .omap2 = {
2720 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2721 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2722 .flags = OMAP_FIREWALL_L4,
2723 }
2724 },
2725 .flags = OCPIF_SWSUP_IDLE,
2726 .user = OCP_USER_MPU | OCP_USER_SDMA,
2727 };
2728
2729 /* l4_wkup -> gpio1 */
2730 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2731 {
2732 .pa_start = 0x48310000,
2733 .pa_end = 0x483101ff,
2734 .flags = ADDR_TYPE_RT
2735 },
2736 { }
2737 };
2738
2739 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2740 .master = &omap3xxx_l4_wkup_hwmod,
2741 .slave = &omap3xxx_gpio1_hwmod,
2742 .addr = omap3xxx_gpio1_addrs,
2743 .user = OCP_USER_MPU | OCP_USER_SDMA,
2744 };
2745
2746 /* l4_per -> gpio2 */
2747 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2748 {
2749 .pa_start = 0x49050000,
2750 .pa_end = 0x490501ff,
2751 .flags = ADDR_TYPE_RT
2752 },
2753 { }
2754 };
2755
2756 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2757 .master = &omap3xxx_l4_per_hwmod,
2758 .slave = &omap3xxx_gpio2_hwmod,
2759 .addr = omap3xxx_gpio2_addrs,
2760 .user = OCP_USER_MPU | OCP_USER_SDMA,
2761 };
2762
2763 /* l4_per -> gpio3 */
2764 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2765 {
2766 .pa_start = 0x49052000,
2767 .pa_end = 0x490521ff,
2768 .flags = ADDR_TYPE_RT
2769 },
2770 { }
2771 };
2772
2773 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2774 .master = &omap3xxx_l4_per_hwmod,
2775 .slave = &omap3xxx_gpio3_hwmod,
2776 .addr = omap3xxx_gpio3_addrs,
2777 .user = OCP_USER_MPU | OCP_USER_SDMA,
2778 };
2779
2780 /* l4_per -> gpio4 */
2781 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
2782 {
2783 .pa_start = 0x49054000,
2784 .pa_end = 0x490541ff,
2785 .flags = ADDR_TYPE_RT
2786 },
2787 { }
2788 };
2789
2790 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
2791 .master = &omap3xxx_l4_per_hwmod,
2792 .slave = &omap3xxx_gpio4_hwmod,
2793 .addr = omap3xxx_gpio4_addrs,
2794 .user = OCP_USER_MPU | OCP_USER_SDMA,
2795 };
2796
2797 /* l4_per -> gpio5 */
2798 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
2799 {
2800 .pa_start = 0x49056000,
2801 .pa_end = 0x490561ff,
2802 .flags = ADDR_TYPE_RT
2803 },
2804 { }
2805 };
2806
2807 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
2808 .master = &omap3xxx_l4_per_hwmod,
2809 .slave = &omap3xxx_gpio5_hwmod,
2810 .addr = omap3xxx_gpio5_addrs,
2811 .user = OCP_USER_MPU | OCP_USER_SDMA,
2812 };
2813
2814 /* l4_per -> gpio6 */
2815 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
2816 {
2817 .pa_start = 0x49058000,
2818 .pa_end = 0x490581ff,
2819 .flags = ADDR_TYPE_RT
2820 },
2821 { }
2822 };
2823
2824 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
2825 .master = &omap3xxx_l4_per_hwmod,
2826 .slave = &omap3xxx_gpio6_hwmod,
2827 .addr = omap3xxx_gpio6_addrs,
2828 .user = OCP_USER_MPU | OCP_USER_SDMA,
2829 };
2830
2831 /* dma_system -> L3 */
2832 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2833 .master = &omap3xxx_dma_system_hwmod,
2834 .slave = &omap3xxx_l3_main_hwmod,
2835 .clk = "core_l3_ick",
2836 .user = OCP_USER_MPU | OCP_USER_SDMA,
2837 };
2838
2839 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2840 {
2841 .pa_start = 0x48056000,
2842 .pa_end = 0x48056fff,
2843 .flags = ADDR_TYPE_RT
2844 },
2845 { }
2846 };
2847
2848 /* l4_cfg -> dma_system */
2849 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2850 .master = &omap3xxx_l4_core_hwmod,
2851 .slave = &omap3xxx_dma_system_hwmod,
2852 .clk = "core_l4_ick",
2853 .addr = omap3xxx_dma_system_addrs,
2854 .user = OCP_USER_MPU | OCP_USER_SDMA,
2855 };
2856
2857 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2858 {
2859 .name = "mpu",
2860 .pa_start = 0x48074000,
2861 .pa_end = 0x480740ff,
2862 .flags = ADDR_TYPE_RT
2863 },
2864 { }
2865 };
2866
2867 /* l4_core -> mcbsp1 */
2868 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2869 .master = &omap3xxx_l4_core_hwmod,
2870 .slave = &omap3xxx_mcbsp1_hwmod,
2871 .clk = "mcbsp1_ick",
2872 .addr = omap3xxx_mcbsp1_addrs,
2873 .user = OCP_USER_MPU | OCP_USER_SDMA,
2874 };
2875
2876 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2877 {
2878 .name = "mpu",
2879 .pa_start = 0x49022000,
2880 .pa_end = 0x490220ff,
2881 .flags = ADDR_TYPE_RT
2882 },
2883 { }
2884 };
2885
2886 /* l4_per -> mcbsp2 */
2887 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2888 .master = &omap3xxx_l4_per_hwmod,
2889 .slave = &omap3xxx_mcbsp2_hwmod,
2890 .clk = "mcbsp2_ick",
2891 .addr = omap3xxx_mcbsp2_addrs,
2892 .user = OCP_USER_MPU | OCP_USER_SDMA,
2893 };
2894
2895 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2896 {
2897 .name = "mpu",
2898 .pa_start = 0x49024000,
2899 .pa_end = 0x490240ff,
2900 .flags = ADDR_TYPE_RT
2901 },
2902 { }
2903 };
2904
2905 /* l4_per -> mcbsp3 */
2906 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2907 .master = &omap3xxx_l4_per_hwmod,
2908 .slave = &omap3xxx_mcbsp3_hwmod,
2909 .clk = "mcbsp3_ick",
2910 .addr = omap3xxx_mcbsp3_addrs,
2911 .user = OCP_USER_MPU | OCP_USER_SDMA,
2912 };
2913
2914 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2915 {
2916 .name = "mpu",
2917 .pa_start = 0x49026000,
2918 .pa_end = 0x490260ff,
2919 .flags = ADDR_TYPE_RT
2920 },
2921 { }
2922 };
2923
2924 /* l4_per -> mcbsp4 */
2925 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2926 .master = &omap3xxx_l4_per_hwmod,
2927 .slave = &omap3xxx_mcbsp4_hwmod,
2928 .clk = "mcbsp4_ick",
2929 .addr = omap3xxx_mcbsp4_addrs,
2930 .user = OCP_USER_MPU | OCP_USER_SDMA,
2931 };
2932
2933 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2934 {
2935 .name = "mpu",
2936 .pa_start = 0x48096000,
2937 .pa_end = 0x480960ff,
2938 .flags = ADDR_TYPE_RT
2939 },
2940 { }
2941 };
2942
2943 /* l4_core -> mcbsp5 */
2944 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2945 .master = &omap3xxx_l4_core_hwmod,
2946 .slave = &omap3xxx_mcbsp5_hwmod,
2947 .clk = "mcbsp5_ick",
2948 .addr = omap3xxx_mcbsp5_addrs,
2949 .user = OCP_USER_MPU | OCP_USER_SDMA,
2950 };
2951
2952 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2953 {
2954 .name = "sidetone",
2955 .pa_start = 0x49028000,
2956 .pa_end = 0x490280ff,
2957 .flags = ADDR_TYPE_RT
2958 },
2959 { }
2960 };
2961
2962 /* l4_per -> mcbsp2_sidetone */
2963 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2964 .master = &omap3xxx_l4_per_hwmod,
2965 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
2966 .clk = "mcbsp2_ick",
2967 .addr = omap3xxx_mcbsp2_sidetone_addrs,
2968 .user = OCP_USER_MPU,
2969 };
2970
2971 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2972 {
2973 .name = "sidetone",
2974 .pa_start = 0x4902A000,
2975 .pa_end = 0x4902A0ff,
2976 .flags = ADDR_TYPE_RT
2977 },
2978 { }
2979 };
2980
2981 /* l4_per -> mcbsp3_sidetone */
2982 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2983 .master = &omap3xxx_l4_per_hwmod,
2984 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
2985 .clk = "mcbsp3_ick",
2986 .addr = omap3xxx_mcbsp3_sidetone_addrs,
2987 .user = OCP_USER_MPU,
2988 };
2989
2990 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2991 {
2992 .pa_start = 0x48094000,
2993 .pa_end = 0x480941ff,
2994 .flags = ADDR_TYPE_RT,
2995 },
2996 { }
2997 };
2998
2999 /* l4_core -> mailbox */
3000 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3001 .master = &omap3xxx_l4_core_hwmod,
3002 .slave = &omap3xxx_mailbox_hwmod,
3003 .addr = omap3xxx_mailbox_addrs,
3004 .user = OCP_USER_MPU | OCP_USER_SDMA,
3005 };
3006
3007 /* l4 core -> mcspi1 interface */
3008 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3009 .master = &omap3xxx_l4_core_hwmod,
3010 .slave = &omap34xx_mcspi1,
3011 .clk = "mcspi1_ick",
3012 .addr = omap2_mcspi1_addr_space,
3013 .user = OCP_USER_MPU | OCP_USER_SDMA,
3014 };
3015
3016 /* l4 core -> mcspi2 interface */
3017 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3018 .master = &omap3xxx_l4_core_hwmod,
3019 .slave = &omap34xx_mcspi2,
3020 .clk = "mcspi2_ick",
3021 .addr = omap2_mcspi2_addr_space,
3022 .user = OCP_USER_MPU | OCP_USER_SDMA,
3023 };
3024
3025 /* l4 core -> mcspi3 interface */
3026 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3027 .master = &omap3xxx_l4_core_hwmod,
3028 .slave = &omap34xx_mcspi3,
3029 .clk = "mcspi3_ick",
3030 .addr = omap2430_mcspi3_addr_space,
3031 .user = OCP_USER_MPU | OCP_USER_SDMA,
3032 };
3033
3034 /* l4 core -> mcspi4 interface */
3035 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3036 {
3037 .pa_start = 0x480ba000,
3038 .pa_end = 0x480ba0ff,
3039 .flags = ADDR_TYPE_RT,
3040 },
3041 { }
3042 };
3043
3044 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3045 .master = &omap3xxx_l4_core_hwmod,
3046 .slave = &omap34xx_mcspi4,
3047 .clk = "mcspi4_ick",
3048 .addr = omap34xx_mcspi4_addr_space,
3049 .user = OCP_USER_MPU | OCP_USER_SDMA,
3050 };
3051
3052 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3053 .master = &omap3xxx_usb_host_hs_hwmod,
3054 .slave = &omap3xxx_l3_main_hwmod,
3055 .clk = "core_l3_ick",
3056 .user = OCP_USER_MPU,
3057 };
3058
3059 static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3060 {
3061 .name = "uhh",
3062 .pa_start = 0x48064000,
3063 .pa_end = 0x480643ff,
3064 .flags = ADDR_TYPE_RT
3065 },
3066 {
3067 .name = "ohci",
3068 .pa_start = 0x48064400,
3069 .pa_end = 0x480647ff,
3070 },
3071 {
3072 .name = "ehci",
3073 .pa_start = 0x48064800,
3074 .pa_end = 0x48064cff,
3075 },
3076 {}
3077 };
3078
3079 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3080 .master = &omap3xxx_l4_core_hwmod,
3081 .slave = &omap3xxx_usb_host_hs_hwmod,
3082 .clk = "usbhost_ick",
3083 .addr = omap3xxx_usb_host_hs_addrs,
3084 .user = OCP_USER_MPU | OCP_USER_SDMA,
3085 };
3086
3087 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3088 {
3089 .name = "tll",
3090 .pa_start = 0x48062000,
3091 .pa_end = 0x48062fff,
3092 .flags = ADDR_TYPE_RT
3093 },
3094 {}
3095 };
3096
3097 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3098 .master = &omap3xxx_l4_core_hwmod,
3099 .slave = &omap3xxx_usb_tll_hs_hwmod,
3100 .clk = "usbtll_ick",
3101 .addr = omap3xxx_usb_tll_hs_addrs,
3102 .user = OCP_USER_MPU | OCP_USER_SDMA,
3103 };
3104
3105 /* l4_core -> hdq1w interface */
3106 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
3107 .master = &omap3xxx_l4_core_hwmod,
3108 .slave = &omap3xxx_hdq1w_hwmod,
3109 .clk = "hdq_ick",
3110 .addr = omap2_hdq1w_addr_space,
3111 .user = OCP_USER_MPU | OCP_USER_SDMA,
3112 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
3113 };
3114
3115 /* l4_wkup -> 32ksync_counter */
3116 static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
3117 {
3118 .pa_start = 0x48320000,
3119 .pa_end = 0x4832001f,
3120 .flags = ADDR_TYPE_RT
3121 },
3122 { }
3123 };
3124
3125 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
3126 .master = &omap3xxx_l4_wkup_hwmod,
3127 .slave = &omap3xxx_counter_32k_hwmod,
3128 .clk = "omap_32ksync_ick",
3129 .addr = omap3xxx_counter_32k_addrs,
3130 .user = OCP_USER_MPU | OCP_USER_SDMA,
3131 };
3132
3133 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3134 &omap3xxx_l3_main__l4_core,
3135 &omap3xxx_l3_main__l4_per,
3136 &omap3xxx_mpu__l3_main,
3137 &omap3xxx_l4_core__l4_wkup,
3138 &omap3xxx_l4_core__mmc3,
3139 &omap3_l4_core__uart1,
3140 &omap3_l4_core__uart2,
3141 &omap3_l4_per__uart3,
3142 &omap3_l4_core__i2c1,
3143 &omap3_l4_core__i2c2,
3144 &omap3_l4_core__i2c3,
3145 &omap3xxx_l4_wkup__l4_sec,
3146 &omap3xxx_l4_wkup__timer1,
3147 &omap3xxx_l4_per__timer2,
3148 &omap3xxx_l4_per__timer3,
3149 &omap3xxx_l4_per__timer4,
3150 &omap3xxx_l4_per__timer5,
3151 &omap3xxx_l4_per__timer6,
3152 &omap3xxx_l4_per__timer7,
3153 &omap3xxx_l4_per__timer8,
3154 &omap3xxx_l4_per__timer9,
3155 &omap3xxx_l4_core__timer10,
3156 &omap3xxx_l4_core__timer11,
3157 &omap3xxx_l4_wkup__wd_timer2,
3158 &omap3xxx_l4_wkup__gpio1,
3159 &omap3xxx_l4_per__gpio2,
3160 &omap3xxx_l4_per__gpio3,
3161 &omap3xxx_l4_per__gpio4,
3162 &omap3xxx_l4_per__gpio5,
3163 &omap3xxx_l4_per__gpio6,
3164 &omap3xxx_dma_system__l3,
3165 &omap3xxx_l4_core__dma_system,
3166 &omap3xxx_l4_core__mcbsp1,
3167 &omap3xxx_l4_per__mcbsp2,
3168 &omap3xxx_l4_per__mcbsp3,
3169 &omap3xxx_l4_per__mcbsp4,
3170 &omap3xxx_l4_core__mcbsp5,
3171 &omap3xxx_l4_per__mcbsp2_sidetone,
3172 &omap3xxx_l4_per__mcbsp3_sidetone,
3173 &omap34xx_l4_core__mcspi1,
3174 &omap34xx_l4_core__mcspi2,
3175 &omap34xx_l4_core__mcspi3,
3176 &omap34xx_l4_core__mcspi4,
3177 &omap3xxx_l4_wkup__counter_32k,
3178 NULL,
3179 };
3180
3181 /* GP-only hwmod links */
3182 static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = {
3183 &omap3xxx_l4_sec__timer12,
3184 NULL
3185 };
3186
3187 /* 3430ES1-only hwmod links */
3188 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
3189 &omap3430es1_dss__l3,
3190 &omap3430es1_l4_core__dss,
3191 NULL
3192 };
3193
3194 /* 3430ES2+-only hwmod links */
3195 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
3196 &omap3xxx_dss__l3,
3197 &omap3xxx_l4_core__dss,
3198 &omap3xxx_usbhsotg__l3,
3199 &omap3xxx_l4_core__usbhsotg,
3200 &omap3xxx_usb_host_hs__l3_main_2,
3201 &omap3xxx_l4_core__usb_host_hs,
3202 &omap3xxx_l4_core__usb_tll_hs,
3203 NULL
3204 };
3205
3206 /* <= 3430ES3-only hwmod links */
3207 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
3208 &omap3xxx_l4_core__pre_es3_mmc1,
3209 &omap3xxx_l4_core__pre_es3_mmc2,
3210 NULL
3211 };
3212
3213 /* 3430ES3+-only hwmod links */
3214 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3215 &omap3xxx_l4_core__es3plus_mmc1,
3216 &omap3xxx_l4_core__es3plus_mmc2,
3217 NULL
3218 };
3219
3220 /* 34xx-only hwmod links (all ES revisions) */
3221 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3222 &omap3xxx_l3__iva,
3223 &omap34xx_l4_core__sr1,
3224 &omap34xx_l4_core__sr2,
3225 &omap3xxx_l4_core__mailbox,
3226 &omap3xxx_l4_core__hdq1w,
3227 NULL
3228 };
3229
3230 /* 36xx-only hwmod links (all ES revisions) */
3231 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3232 &omap3xxx_l3__iva,
3233 &omap36xx_l4_per__uart4,
3234 &omap3xxx_dss__l3,
3235 &omap3xxx_l4_core__dss,
3236 &omap36xx_l4_core__sr1,
3237 &omap36xx_l4_core__sr2,
3238 &omap3xxx_usbhsotg__l3,
3239 &omap3xxx_l4_core__usbhsotg,
3240 &omap3xxx_l4_core__mailbox,
3241 &omap3xxx_usb_host_hs__l3_main_2,
3242 &omap3xxx_l4_core__usb_host_hs,
3243 &omap3xxx_l4_core__usb_tll_hs,
3244 &omap3xxx_l4_core__es3plus_mmc1,
3245 &omap3xxx_l4_core__es3plus_mmc2,
3246 &omap3xxx_l4_core__hdq1w,
3247 NULL
3248 };
3249
3250 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3251 &omap3xxx_dss__l3,
3252 &omap3xxx_l4_core__dss,
3253 &am35xx_usbhsotg__l3,
3254 &am35xx_l4_core__usbhsotg,
3255 &am35xx_l4_core__uart4,
3256 &omap3xxx_usb_host_hs__l3_main_2,
3257 &omap3xxx_l4_core__usb_host_hs,
3258 &omap3xxx_l4_core__usb_tll_hs,
3259 &omap3xxx_l4_core__es3plus_mmc1,
3260 &omap3xxx_l4_core__es3plus_mmc2,
3261 NULL
3262 };
3263
3264 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3265 &omap3xxx_l4_core__dss_dispc,
3266 &omap3xxx_l4_core__dss_dsi1,
3267 &omap3xxx_l4_core__dss_rfbi,
3268 &omap3xxx_l4_core__dss_venc,
3269 NULL
3270 };
3271
3272 int __init omap3xxx_hwmod_init(void)
3273 {
3274 int r;
3275 struct omap_hwmod_ocp_if **h = NULL;
3276 unsigned int rev;
3277
3278 /* Register hwmod links common to all OMAP3 */
3279 r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
3280 if (r < 0)
3281 return r;
3282
3283 /* Register GP-only hwmod links. */
3284 if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
3285 r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs);
3286 if (r < 0)
3287 return r;
3288 }
3289
3290 rev = omap_rev();
3291
3292 /*
3293 * Register hwmod links common to individual OMAP3 families, all
3294 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3295 * All possible revisions should be included in this conditional.
3296 */
3297 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3298 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3299 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3300 h = omap34xx_hwmod_ocp_ifs;
3301 } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
3302 h = am35xx_hwmod_ocp_ifs;
3303 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3304 rev == OMAP3630_REV_ES1_2) {
3305 h = omap36xx_hwmod_ocp_ifs;
3306 } else {
3307 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3308 return -EINVAL;
3309 };
3310
3311 r = omap_hwmod_register_links(h);
3312 if (r < 0)
3313 return r;
3314
3315 /*
3316 * Register hwmod links specific to certain ES levels of a
3317 * particular family of silicon (e.g., 34xx ES1.0)
3318 */
3319 h = NULL;
3320 if (rev == OMAP3430_REV_ES1_0) {
3321 h = omap3430es1_hwmod_ocp_ifs;
3322 } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3323 rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3324 rev == OMAP3430_REV_ES3_1_2) {
3325 h = omap3430es2plus_hwmod_ocp_ifs;
3326 };
3327
3328 if (h) {
3329 r = omap_hwmod_register_links(h);
3330 if (r < 0)
3331 return r;
3332 }
3333
3334 h = NULL;
3335 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3336 rev == OMAP3430_REV_ES2_1) {
3337 h = omap3430_pre_es3_hwmod_ocp_ifs;
3338 } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3339 rev == OMAP3430_REV_ES3_1_2) {
3340 h = omap3430_es3plus_hwmod_ocp_ifs;
3341 };
3342
3343 if (h)
3344 r = omap_hwmod_register_links(h);
3345 if (r < 0)
3346 return r;
3347
3348 /*
3349 * DSS code presumes that dss_core hwmod is handled first,
3350 * _before_ any other DSS related hwmods so register common
3351 * DSS hwmod links last to ensure that dss_core is already
3352 * registered. Otherwise some change things may happen, for
3353 * ex. if dispc is handled before dss_core and DSS is enabled
3354 * in bootloader DISPC will be reset with outputs enabled
3355 * which sometimes leads to unrecoverable L3 error. XXX The
3356 * long-term fix to this is to ensure hwmods are set up in
3357 * dependency order in the hwmod core code.
3358 */
3359 r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
3360
3361 return r;
3362 }
Linux kernel - Deliverables
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