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Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_3xxx_data.c
1 /*
2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
3 *
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
6 * Paul Walmsley
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * The data in this file should be completely autogeneratable from
13 * the TI hardware database or other technical documentation.
14 *
15 * XXX these should be marked initdata for multi-OMAP kernels
16 */
17 #include <linux/power/smartreflex.h>
18
19 #include <plat/omap_hwmod.h>
20 #include <mach/irqs.h>
21 #include <plat/cpu.h>
22 #include <plat/dma.h>
23 #include <plat/serial.h>
24 #include <plat/l3_3xxx.h>
25 #include <plat/l4_3xxx.h>
26 #include <plat/i2c.h>
27 #include <plat/gpio.h>
28 #include <plat/mmc.h>
29 #include <plat/mcbsp.h>
30 #include <plat/mcspi.h>
31 #include <plat/dmtimer.h>
32
33 #include "omap_hwmod_common_data.h"
34 #include "prm-regbits-34xx.h"
35 #include "cm-regbits-34xx.h"
36 #include "wd_timer.h"
37 #include <mach/am35xx.h>
38
39 /*
40 * OMAP3xxx hardware module integration data
41 *
42 * All of the data in this section should be autogeneratable from the
43 * TI hardware database or other technical documentation. Data that
44 * is driver-specific or driver-kernel integration-specific belongs
45 * elsewhere.
46 */
47
48 /*
49 * IP blocks
50 */
51
52 /* L3 */
53 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
54 { .irq = INT_34XX_L3_DBG_IRQ },
55 { .irq = INT_34XX_L3_APP_IRQ },
56 { .irq = -1 }
57 };
58
59 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
60 .name = "l3_main",
61 .class = &l3_hwmod_class,
62 .mpu_irqs = omap3xxx_l3_main_irqs,
63 .flags = HWMOD_NO_IDLEST,
64 };
65
66 /* L4 CORE */
67 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
68 .name = "l4_core",
69 .class = &l4_hwmod_class,
70 .flags = HWMOD_NO_IDLEST,
71 };
72
73 /* L4 PER */
74 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
75 .name = "l4_per",
76 .class = &l4_hwmod_class,
77 .flags = HWMOD_NO_IDLEST,
78 };
79
80 /* L4 WKUP */
81 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
82 .name = "l4_wkup",
83 .class = &l4_hwmod_class,
84 .flags = HWMOD_NO_IDLEST,
85 };
86
87 /* L4 SEC */
88 static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
89 .name = "l4_sec",
90 .class = &l4_hwmod_class,
91 .flags = HWMOD_NO_IDLEST,
92 };
93
94 /* MPU */
95 static struct omap_hwmod omap3xxx_mpu_hwmod = {
96 .name = "mpu",
97 .class = &mpu_hwmod_class,
98 .main_clk = "arm_fck",
99 };
100
101 /* IVA2 (IVA2) */
102 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
103 { .name = "logic", .rst_shift = 0, .st_shift = 8 },
104 { .name = "seq0", .rst_shift = 1, .st_shift = 9 },
105 { .name = "seq1", .rst_shift = 2, .st_shift = 10 },
106 };
107
108 static struct omap_hwmod omap3xxx_iva_hwmod = {
109 .name = "iva",
110 .class = &iva_hwmod_class,
111 .clkdm_name = "iva2_clkdm",
112 .rst_lines = omap3xxx_iva_resets,
113 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets),
114 .main_clk = "iva2_ck",
115 .prcm = {
116 .omap2 = {
117 .module_offs = OMAP3430_IVA2_MOD,
118 .prcm_reg_id = 1,
119 .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
120 .idlest_reg_id = 1,
121 .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
122 }
123 },
124 };
125
126 /* timer class */
127 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
128 .rev_offs = 0x0000,
129 .sysc_offs = 0x0010,
130 .syss_offs = 0x0014,
131 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
132 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
133 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
134 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
135 .sysc_fields = &omap_hwmod_sysc_type1,
136 };
137
138 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
139 .name = "timer",
140 .sysc = &omap3xxx_timer_1ms_sysc,
141 };
142
143 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
144 .rev_offs = 0x0000,
145 .sysc_offs = 0x0010,
146 .syss_offs = 0x0014,
147 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
148 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
149 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
150 .sysc_fields = &omap_hwmod_sysc_type1,
151 };
152
153 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
154 .name = "timer",
155 .sysc = &omap3xxx_timer_sysc,
156 };
157
158 /* secure timers dev attribute */
159 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
160 .timer_capability = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE,
161 };
162
163 /* always-on timers dev attribute */
164 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
165 .timer_capability = OMAP_TIMER_ALWON,
166 };
167
168 /* pwm timers dev attribute */
169 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
170 .timer_capability = OMAP_TIMER_HAS_PWM,
171 };
172
173 /* timer1 */
174 static struct omap_hwmod omap3xxx_timer1_hwmod = {
175 .name = "timer1",
176 .mpu_irqs = omap2_timer1_mpu_irqs,
177 .main_clk = "gpt1_fck",
178 .prcm = {
179 .omap2 = {
180 .prcm_reg_id = 1,
181 .module_bit = OMAP3430_EN_GPT1_SHIFT,
182 .module_offs = WKUP_MOD,
183 .idlest_reg_id = 1,
184 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
185 },
186 },
187 .dev_attr = &capability_alwon_dev_attr,
188 .class = &omap3xxx_timer_1ms_hwmod_class,
189 };
190
191 /* timer2 */
192 static struct omap_hwmod omap3xxx_timer2_hwmod = {
193 .name = "timer2",
194 .mpu_irqs = omap2_timer2_mpu_irqs,
195 .main_clk = "gpt2_fck",
196 .prcm = {
197 .omap2 = {
198 .prcm_reg_id = 1,
199 .module_bit = OMAP3430_EN_GPT2_SHIFT,
200 .module_offs = OMAP3430_PER_MOD,
201 .idlest_reg_id = 1,
202 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
203 },
204 },
205 .class = &omap3xxx_timer_1ms_hwmod_class,
206 };
207
208 /* timer3 */
209 static struct omap_hwmod omap3xxx_timer3_hwmod = {
210 .name = "timer3",
211 .mpu_irqs = omap2_timer3_mpu_irqs,
212 .main_clk = "gpt3_fck",
213 .prcm = {
214 .omap2 = {
215 .prcm_reg_id = 1,
216 .module_bit = OMAP3430_EN_GPT3_SHIFT,
217 .module_offs = OMAP3430_PER_MOD,
218 .idlest_reg_id = 1,
219 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
220 },
221 },
222 .class = &omap3xxx_timer_hwmod_class,
223 };
224
225 /* timer4 */
226 static struct omap_hwmod omap3xxx_timer4_hwmod = {
227 .name = "timer4",
228 .mpu_irqs = omap2_timer4_mpu_irqs,
229 .main_clk = "gpt4_fck",
230 .prcm = {
231 .omap2 = {
232 .prcm_reg_id = 1,
233 .module_bit = OMAP3430_EN_GPT4_SHIFT,
234 .module_offs = OMAP3430_PER_MOD,
235 .idlest_reg_id = 1,
236 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
237 },
238 },
239 .class = &omap3xxx_timer_hwmod_class,
240 };
241
242 /* timer5 */
243 static struct omap_hwmod omap3xxx_timer5_hwmod = {
244 .name = "timer5",
245 .mpu_irqs = omap2_timer5_mpu_irqs,
246 .main_clk = "gpt5_fck",
247 .prcm = {
248 .omap2 = {
249 .prcm_reg_id = 1,
250 .module_bit = OMAP3430_EN_GPT5_SHIFT,
251 .module_offs = OMAP3430_PER_MOD,
252 .idlest_reg_id = 1,
253 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
254 },
255 },
256 .class = &omap3xxx_timer_hwmod_class,
257 };
258
259 /* timer6 */
260 static struct omap_hwmod omap3xxx_timer6_hwmod = {
261 .name = "timer6",
262 .mpu_irqs = omap2_timer6_mpu_irqs,
263 .main_clk = "gpt6_fck",
264 .prcm = {
265 .omap2 = {
266 .prcm_reg_id = 1,
267 .module_bit = OMAP3430_EN_GPT6_SHIFT,
268 .module_offs = OMAP3430_PER_MOD,
269 .idlest_reg_id = 1,
270 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
271 },
272 },
273 .class = &omap3xxx_timer_hwmod_class,
274 };
275
276 /* timer7 */
277 static struct omap_hwmod omap3xxx_timer7_hwmod = {
278 .name = "timer7",
279 .mpu_irqs = omap2_timer7_mpu_irqs,
280 .main_clk = "gpt7_fck",
281 .prcm = {
282 .omap2 = {
283 .prcm_reg_id = 1,
284 .module_bit = OMAP3430_EN_GPT7_SHIFT,
285 .module_offs = OMAP3430_PER_MOD,
286 .idlest_reg_id = 1,
287 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
288 },
289 },
290 .class = &omap3xxx_timer_hwmod_class,
291 };
292
293 /* timer8 */
294 static struct omap_hwmod omap3xxx_timer8_hwmod = {
295 .name = "timer8",
296 .mpu_irqs = omap2_timer8_mpu_irqs,
297 .main_clk = "gpt8_fck",
298 .prcm = {
299 .omap2 = {
300 .prcm_reg_id = 1,
301 .module_bit = OMAP3430_EN_GPT8_SHIFT,
302 .module_offs = OMAP3430_PER_MOD,
303 .idlest_reg_id = 1,
304 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
305 },
306 },
307 .dev_attr = &capability_pwm_dev_attr,
308 .class = &omap3xxx_timer_hwmod_class,
309 };
310
311 /* timer9 */
312 static struct omap_hwmod omap3xxx_timer9_hwmod = {
313 .name = "timer9",
314 .mpu_irqs = omap2_timer9_mpu_irqs,
315 .main_clk = "gpt9_fck",
316 .prcm = {
317 .omap2 = {
318 .prcm_reg_id = 1,
319 .module_bit = OMAP3430_EN_GPT9_SHIFT,
320 .module_offs = OMAP3430_PER_MOD,
321 .idlest_reg_id = 1,
322 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
323 },
324 },
325 .dev_attr = &capability_pwm_dev_attr,
326 .class = &omap3xxx_timer_hwmod_class,
327 };
328
329 /* timer10 */
330 static struct omap_hwmod omap3xxx_timer10_hwmod = {
331 .name = "timer10",
332 .mpu_irqs = omap2_timer10_mpu_irqs,
333 .main_clk = "gpt10_fck",
334 .prcm = {
335 .omap2 = {
336 .prcm_reg_id = 1,
337 .module_bit = OMAP3430_EN_GPT10_SHIFT,
338 .module_offs = CORE_MOD,
339 .idlest_reg_id = 1,
340 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
341 },
342 },
343 .dev_attr = &capability_pwm_dev_attr,
344 .class = &omap3xxx_timer_1ms_hwmod_class,
345 };
346
347 /* timer11 */
348 static struct omap_hwmod omap3xxx_timer11_hwmod = {
349 .name = "timer11",
350 .mpu_irqs = omap2_timer11_mpu_irqs,
351 .main_clk = "gpt11_fck",
352 .prcm = {
353 .omap2 = {
354 .prcm_reg_id = 1,
355 .module_bit = OMAP3430_EN_GPT11_SHIFT,
356 .module_offs = CORE_MOD,
357 .idlest_reg_id = 1,
358 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
359 },
360 },
361 .dev_attr = &capability_pwm_dev_attr,
362 .class = &omap3xxx_timer_hwmod_class,
363 };
364
365 /* timer12 */
366 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
367 { .irq = 95, },
368 { .irq = -1 }
369 };
370
371 static struct omap_hwmod omap3xxx_timer12_hwmod = {
372 .name = "timer12",
373 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
374 .main_clk = "gpt12_fck",
375 .prcm = {
376 .omap2 = {
377 .prcm_reg_id = 1,
378 .module_bit = OMAP3430_EN_GPT12_SHIFT,
379 .module_offs = WKUP_MOD,
380 .idlest_reg_id = 1,
381 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
382 },
383 },
384 .dev_attr = &capability_secure_dev_attr,
385 .class = &omap3xxx_timer_hwmod_class,
386 };
387
388 /*
389 * 'wd_timer' class
390 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
391 * overflow condition
392 */
393
394 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
395 .rev_offs = 0x0000,
396 .sysc_offs = 0x0010,
397 .syss_offs = 0x0014,
398 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
399 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
400 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
401 SYSS_HAS_RESET_STATUS),
402 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
403 .sysc_fields = &omap_hwmod_sysc_type1,
404 };
405
406 /* I2C common */
407 static struct omap_hwmod_class_sysconfig i2c_sysc = {
408 .rev_offs = 0x00,
409 .sysc_offs = 0x20,
410 .syss_offs = 0x10,
411 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
412 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
413 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
414 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
415 .clockact = CLOCKACT_TEST_ICLK,
416 .sysc_fields = &omap_hwmod_sysc_type1,
417 };
418
419 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
420 .name = "wd_timer",
421 .sysc = &omap3xxx_wd_timer_sysc,
422 .pre_shutdown = &omap2_wd_timer_disable,
423 .reset = &omap2_wd_timer_reset,
424 };
425
426 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
427 .name = "wd_timer2",
428 .class = &omap3xxx_wd_timer_hwmod_class,
429 .main_clk = "wdt2_fck",
430 .prcm = {
431 .omap2 = {
432 .prcm_reg_id = 1,
433 .module_bit = OMAP3430_EN_WDT2_SHIFT,
434 .module_offs = WKUP_MOD,
435 .idlest_reg_id = 1,
436 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
437 },
438 },
439 /*
440 * XXX: Use software supervised mode, HW supervised smartidle seems to
441 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
442 */
443 .flags = HWMOD_SWSUP_SIDLE,
444 };
445
446 /* UART1 */
447 static struct omap_hwmod omap3xxx_uart1_hwmod = {
448 .name = "uart1",
449 .mpu_irqs = omap2_uart1_mpu_irqs,
450 .sdma_reqs = omap2_uart1_sdma_reqs,
451 .main_clk = "uart1_fck",
452 .prcm = {
453 .omap2 = {
454 .module_offs = CORE_MOD,
455 .prcm_reg_id = 1,
456 .module_bit = OMAP3430_EN_UART1_SHIFT,
457 .idlest_reg_id = 1,
458 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
459 },
460 },
461 .class = &omap2_uart_class,
462 };
463
464 /* UART2 */
465 static struct omap_hwmod omap3xxx_uart2_hwmod = {
466 .name = "uart2",
467 .mpu_irqs = omap2_uart2_mpu_irqs,
468 .sdma_reqs = omap2_uart2_sdma_reqs,
469 .main_clk = "uart2_fck",
470 .prcm = {
471 .omap2 = {
472 .module_offs = CORE_MOD,
473 .prcm_reg_id = 1,
474 .module_bit = OMAP3430_EN_UART2_SHIFT,
475 .idlest_reg_id = 1,
476 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
477 },
478 },
479 .class = &omap2_uart_class,
480 };
481
482 /* UART3 */
483 static struct omap_hwmod omap3xxx_uart3_hwmod = {
484 .name = "uart3",
485 .mpu_irqs = omap2_uart3_mpu_irqs,
486 .sdma_reqs = omap2_uart3_sdma_reqs,
487 .main_clk = "uart3_fck",
488 .prcm = {
489 .omap2 = {
490 .module_offs = OMAP3430_PER_MOD,
491 .prcm_reg_id = 1,
492 .module_bit = OMAP3430_EN_UART3_SHIFT,
493 .idlest_reg_id = 1,
494 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
495 },
496 },
497 .class = &omap2_uart_class,
498 };
499
500 /* UART4 */
501 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
502 { .irq = INT_36XX_UART4_IRQ, },
503 { .irq = -1 }
504 };
505
506 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
507 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
508 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
509 { .dma_req = -1 }
510 };
511
512 static struct omap_hwmod omap36xx_uart4_hwmod = {
513 .name = "uart4",
514 .mpu_irqs = uart4_mpu_irqs,
515 .sdma_reqs = uart4_sdma_reqs,
516 .main_clk = "uart4_fck",
517 .prcm = {
518 .omap2 = {
519 .module_offs = OMAP3430_PER_MOD,
520 .prcm_reg_id = 1,
521 .module_bit = OMAP3630_EN_UART4_SHIFT,
522 .idlest_reg_id = 1,
523 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
524 },
525 },
526 .class = &omap2_uart_class,
527 };
528
529 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
530 { .irq = INT_35XX_UART4_IRQ, },
531 { .irq = -1 }
532 };
533
534 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
535 { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
536 { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
537 { .dma_req = -1 }
538 };
539
540 /*
541 * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
542 * uart2_fck being enabled. So we add uart1_fck as an optional clock,
543 * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET. This really
544 * should not be needed. The functional clock structure of the AM35xx
545 * UART4 is extremely unclear and opaque; it is unclear what the role
546 * of uart1/2_fck is for the UART4. Any clarification from either
547 * empirical testing or the AM3505/3517 hardware designers would be
548 * most welcome.
549 */
550 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
551 { .role = "softreset_uart1_fck", .clk = "uart1_fck" },
552 };
553
554 static struct omap_hwmod am35xx_uart4_hwmod = {
555 .name = "uart4",
556 .mpu_irqs = am35xx_uart4_mpu_irqs,
557 .sdma_reqs = am35xx_uart4_sdma_reqs,
558 .main_clk = "uart4_fck",
559 .prcm = {
560 .omap2 = {
561 .module_offs = CORE_MOD,
562 .prcm_reg_id = 1,
563 .module_bit = AM35XX_EN_UART4_SHIFT,
564 .idlest_reg_id = 1,
565 .idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
566 },
567 },
568 .opt_clks = am35xx_uart4_opt_clks,
569 .opt_clks_cnt = ARRAY_SIZE(am35xx_uart4_opt_clks),
570 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
571 .class = &omap2_uart_class,
572 };
573
574 static struct omap_hwmod_class i2c_class = {
575 .name = "i2c",
576 .sysc = &i2c_sysc,
577 .rev = OMAP_I2C_IP_VERSION_1,
578 .reset = &omap_i2c_reset,
579 };
580
581 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
582 { .name = "dispc", .dma_req = 5 },
583 { .name = "dsi1", .dma_req = 74 },
584 { .dma_req = -1 }
585 };
586
587 /* dss */
588 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
589 /*
590 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
591 * driver does not use these clocks.
592 */
593 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
594 { .role = "tv_clk", .clk = "dss_tv_fck" },
595 /* required only on OMAP3430 */
596 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
597 };
598
599 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
600 .name = "dss_core",
601 .class = &omap2_dss_hwmod_class,
602 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
603 .sdma_reqs = omap3xxx_dss_sdma_chs,
604 .prcm = {
605 .omap2 = {
606 .prcm_reg_id = 1,
607 .module_bit = OMAP3430_EN_DSS1_SHIFT,
608 .module_offs = OMAP3430_DSS_MOD,
609 .idlest_reg_id = 1,
610 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
611 },
612 },
613 .opt_clks = dss_opt_clks,
614 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
615 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
616 };
617
618 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
619 .name = "dss_core",
620 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
621 .class = &omap2_dss_hwmod_class,
622 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
623 .sdma_reqs = omap3xxx_dss_sdma_chs,
624 .prcm = {
625 .omap2 = {
626 .prcm_reg_id = 1,
627 .module_bit = OMAP3430_EN_DSS1_SHIFT,
628 .module_offs = OMAP3430_DSS_MOD,
629 .idlest_reg_id = 1,
630 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
631 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
632 },
633 },
634 .opt_clks = dss_opt_clks,
635 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
636 };
637
638 /*
639 * 'dispc' class
640 * display controller
641 */
642
643 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
644 .rev_offs = 0x0000,
645 .sysc_offs = 0x0010,
646 .syss_offs = 0x0014,
647 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
648 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
649 SYSC_HAS_ENAWAKEUP),
650 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
651 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
652 .sysc_fields = &omap_hwmod_sysc_type1,
653 };
654
655 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
656 .name = "dispc",
657 .sysc = &omap3_dispc_sysc,
658 };
659
660 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
661 .name = "dss_dispc",
662 .class = &omap3_dispc_hwmod_class,
663 .mpu_irqs = omap2_dispc_irqs,
664 .main_clk = "dss1_alwon_fck",
665 .prcm = {
666 .omap2 = {
667 .prcm_reg_id = 1,
668 .module_bit = OMAP3430_EN_DSS1_SHIFT,
669 .module_offs = OMAP3430_DSS_MOD,
670 },
671 },
672 .flags = HWMOD_NO_IDLEST,
673 .dev_attr = &omap2_3_dss_dispc_dev_attr
674 };
675
676 /*
677 * 'dsi' class
678 * display serial interface controller
679 */
680
681 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
682 .name = "dsi",
683 };
684
685 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
686 { .irq = 25 },
687 { .irq = -1 }
688 };
689
690 /* dss_dsi1 */
691 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
692 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
693 };
694
695 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
696 .name = "dss_dsi1",
697 .class = &omap3xxx_dsi_hwmod_class,
698 .mpu_irqs = omap3xxx_dsi1_irqs,
699 .main_clk = "dss1_alwon_fck",
700 .prcm = {
701 .omap2 = {
702 .prcm_reg_id = 1,
703 .module_bit = OMAP3430_EN_DSS1_SHIFT,
704 .module_offs = OMAP3430_DSS_MOD,
705 },
706 },
707 .opt_clks = dss_dsi1_opt_clks,
708 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
709 .flags = HWMOD_NO_IDLEST,
710 };
711
712 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
713 { .role = "ick", .clk = "dss_ick" },
714 };
715
716 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
717 .name = "dss_rfbi",
718 .class = &omap2_rfbi_hwmod_class,
719 .main_clk = "dss1_alwon_fck",
720 .prcm = {
721 .omap2 = {
722 .prcm_reg_id = 1,
723 .module_bit = OMAP3430_EN_DSS1_SHIFT,
724 .module_offs = OMAP3430_DSS_MOD,
725 },
726 },
727 .opt_clks = dss_rfbi_opt_clks,
728 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
729 .flags = HWMOD_NO_IDLEST,
730 };
731
732 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
733 /* required only on OMAP3430 */
734 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
735 };
736
737 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
738 .name = "dss_venc",
739 .class = &omap2_venc_hwmod_class,
740 .main_clk = "dss_tv_fck",
741 .prcm = {
742 .omap2 = {
743 .prcm_reg_id = 1,
744 .module_bit = OMAP3430_EN_DSS1_SHIFT,
745 .module_offs = OMAP3430_DSS_MOD,
746 },
747 },
748 .opt_clks = dss_venc_opt_clks,
749 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
750 .flags = HWMOD_NO_IDLEST,
751 };
752
753 /* I2C1 */
754 static struct omap_i2c_dev_attr i2c1_dev_attr = {
755 .fifo_depth = 8, /* bytes */
756 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
757 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
758 OMAP_I2C_FLAG_BUS_SHIFT_2,
759 };
760
761 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
762 .name = "i2c1",
763 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
764 .mpu_irqs = omap2_i2c1_mpu_irqs,
765 .sdma_reqs = omap2_i2c1_sdma_reqs,
766 .main_clk = "i2c1_fck",
767 .prcm = {
768 .omap2 = {
769 .module_offs = CORE_MOD,
770 .prcm_reg_id = 1,
771 .module_bit = OMAP3430_EN_I2C1_SHIFT,
772 .idlest_reg_id = 1,
773 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
774 },
775 },
776 .class = &i2c_class,
777 .dev_attr = &i2c1_dev_attr,
778 };
779
780 /* I2C2 */
781 static struct omap_i2c_dev_attr i2c2_dev_attr = {
782 .fifo_depth = 8, /* bytes */
783 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
784 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
785 OMAP_I2C_FLAG_BUS_SHIFT_2,
786 };
787
788 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
789 .name = "i2c2",
790 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
791 .mpu_irqs = omap2_i2c2_mpu_irqs,
792 .sdma_reqs = omap2_i2c2_sdma_reqs,
793 .main_clk = "i2c2_fck",
794 .prcm = {
795 .omap2 = {
796 .module_offs = CORE_MOD,
797 .prcm_reg_id = 1,
798 .module_bit = OMAP3430_EN_I2C2_SHIFT,
799 .idlest_reg_id = 1,
800 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
801 },
802 },
803 .class = &i2c_class,
804 .dev_attr = &i2c2_dev_attr,
805 };
806
807 /* I2C3 */
808 static struct omap_i2c_dev_attr i2c3_dev_attr = {
809 .fifo_depth = 64, /* bytes */
810 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
811 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
812 OMAP_I2C_FLAG_BUS_SHIFT_2,
813 };
814
815 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
816 { .irq = INT_34XX_I2C3_IRQ, },
817 { .irq = -1 }
818 };
819
820 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
821 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
822 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
823 { .dma_req = -1 }
824 };
825
826 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
827 .name = "i2c3",
828 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
829 .mpu_irqs = i2c3_mpu_irqs,
830 .sdma_reqs = i2c3_sdma_reqs,
831 .main_clk = "i2c3_fck",
832 .prcm = {
833 .omap2 = {
834 .module_offs = CORE_MOD,
835 .prcm_reg_id = 1,
836 .module_bit = OMAP3430_EN_I2C3_SHIFT,
837 .idlest_reg_id = 1,
838 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
839 },
840 },
841 .class = &i2c_class,
842 .dev_attr = &i2c3_dev_attr,
843 };
844
845 /*
846 * 'gpio' class
847 * general purpose io module
848 */
849
850 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
851 .rev_offs = 0x0000,
852 .sysc_offs = 0x0010,
853 .syss_offs = 0x0014,
854 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
855 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
856 SYSS_HAS_RESET_STATUS),
857 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
858 .sysc_fields = &omap_hwmod_sysc_type1,
859 };
860
861 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
862 .name = "gpio",
863 .sysc = &omap3xxx_gpio_sysc,
864 .rev = 1,
865 };
866
867 /* gpio_dev_attr */
868 static struct omap_gpio_dev_attr gpio_dev_attr = {
869 .bank_width = 32,
870 .dbck_flag = true,
871 };
872
873 /* gpio1 */
874 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
875 { .role = "dbclk", .clk = "gpio1_dbck", },
876 };
877
878 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
879 .name = "gpio1",
880 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
881 .mpu_irqs = omap2_gpio1_irqs,
882 .main_clk = "gpio1_ick",
883 .opt_clks = gpio1_opt_clks,
884 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
885 .prcm = {
886 .omap2 = {
887 .prcm_reg_id = 1,
888 .module_bit = OMAP3430_EN_GPIO1_SHIFT,
889 .module_offs = WKUP_MOD,
890 .idlest_reg_id = 1,
891 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
892 },
893 },
894 .class = &omap3xxx_gpio_hwmod_class,
895 .dev_attr = &gpio_dev_attr,
896 };
897
898 /* gpio2 */
899 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
900 { .role = "dbclk", .clk = "gpio2_dbck", },
901 };
902
903 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
904 .name = "gpio2",
905 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
906 .mpu_irqs = omap2_gpio2_irqs,
907 .main_clk = "gpio2_ick",
908 .opt_clks = gpio2_opt_clks,
909 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
910 .prcm = {
911 .omap2 = {
912 .prcm_reg_id = 1,
913 .module_bit = OMAP3430_EN_GPIO2_SHIFT,
914 .module_offs = OMAP3430_PER_MOD,
915 .idlest_reg_id = 1,
916 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
917 },
918 },
919 .class = &omap3xxx_gpio_hwmod_class,
920 .dev_attr = &gpio_dev_attr,
921 };
922
923 /* gpio3 */
924 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
925 { .role = "dbclk", .clk = "gpio3_dbck", },
926 };
927
928 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
929 .name = "gpio3",
930 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
931 .mpu_irqs = omap2_gpio3_irqs,
932 .main_clk = "gpio3_ick",
933 .opt_clks = gpio3_opt_clks,
934 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
935 .prcm = {
936 .omap2 = {
937 .prcm_reg_id = 1,
938 .module_bit = OMAP3430_EN_GPIO3_SHIFT,
939 .module_offs = OMAP3430_PER_MOD,
940 .idlest_reg_id = 1,
941 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
942 },
943 },
944 .class = &omap3xxx_gpio_hwmod_class,
945 .dev_attr = &gpio_dev_attr,
946 };
947
948 /* gpio4 */
949 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
950 { .role = "dbclk", .clk = "gpio4_dbck", },
951 };
952
953 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
954 .name = "gpio4",
955 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
956 .mpu_irqs = omap2_gpio4_irqs,
957 .main_clk = "gpio4_ick",
958 .opt_clks = gpio4_opt_clks,
959 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
960 .prcm = {
961 .omap2 = {
962 .prcm_reg_id = 1,
963 .module_bit = OMAP3430_EN_GPIO4_SHIFT,
964 .module_offs = OMAP3430_PER_MOD,
965 .idlest_reg_id = 1,
966 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
967 },
968 },
969 .class = &omap3xxx_gpio_hwmod_class,
970 .dev_attr = &gpio_dev_attr,
971 };
972
973 /* gpio5 */
974 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
975 { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
976 { .irq = -1 }
977 };
978
979 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
980 { .role = "dbclk", .clk = "gpio5_dbck", },
981 };
982
983 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
984 .name = "gpio5",
985 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
986 .mpu_irqs = omap3xxx_gpio5_irqs,
987 .main_clk = "gpio5_ick",
988 .opt_clks = gpio5_opt_clks,
989 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
990 .prcm = {
991 .omap2 = {
992 .prcm_reg_id = 1,
993 .module_bit = OMAP3430_EN_GPIO5_SHIFT,
994 .module_offs = OMAP3430_PER_MOD,
995 .idlest_reg_id = 1,
996 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
997 },
998 },
999 .class = &omap3xxx_gpio_hwmod_class,
1000 .dev_attr = &gpio_dev_attr,
1001 };
1002
1003 /* gpio6 */
1004 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
1005 { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
1006 { .irq = -1 }
1007 };
1008
1009 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1010 { .role = "dbclk", .clk = "gpio6_dbck", },
1011 };
1012
1013 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
1014 .name = "gpio6",
1015 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1016 .mpu_irqs = omap3xxx_gpio6_irqs,
1017 .main_clk = "gpio6_ick",
1018 .opt_clks = gpio6_opt_clks,
1019 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1020 .prcm = {
1021 .omap2 = {
1022 .prcm_reg_id = 1,
1023 .module_bit = OMAP3430_EN_GPIO6_SHIFT,
1024 .module_offs = OMAP3430_PER_MOD,
1025 .idlest_reg_id = 1,
1026 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
1027 },
1028 },
1029 .class = &omap3xxx_gpio_hwmod_class,
1030 .dev_attr = &gpio_dev_attr,
1031 };
1032
1033 /* dma attributes */
1034 static struct omap_dma_dev_attr dma_dev_attr = {
1035 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1036 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1037 .lch_count = 32,
1038 };
1039
1040 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1041 .rev_offs = 0x0000,
1042 .sysc_offs = 0x002c,
1043 .syss_offs = 0x0028,
1044 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1045 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1046 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
1047 SYSS_HAS_RESET_STATUS),
1048 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1049 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1050 .sysc_fields = &omap_hwmod_sysc_type1,
1051 };
1052
1053 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1054 .name = "dma",
1055 .sysc = &omap3xxx_dma_sysc,
1056 };
1057
1058 /* dma_system */
1059 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1060 .name = "dma",
1061 .class = &omap3xxx_dma_hwmod_class,
1062 .mpu_irqs = omap2_dma_system_irqs,
1063 .main_clk = "core_l3_ick",
1064 .prcm = {
1065 .omap2 = {
1066 .module_offs = CORE_MOD,
1067 .prcm_reg_id = 1,
1068 .module_bit = OMAP3430_ST_SDMA_SHIFT,
1069 .idlest_reg_id = 1,
1070 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
1071 },
1072 },
1073 .dev_attr = &dma_dev_attr,
1074 .flags = HWMOD_NO_IDLEST,
1075 };
1076
1077 /*
1078 * 'mcbsp' class
1079 * multi channel buffered serial port controller
1080 */
1081
1082 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
1083 .sysc_offs = 0x008c,
1084 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1085 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1086 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1087 .sysc_fields = &omap_hwmod_sysc_type1,
1088 .clockact = 0x2,
1089 };
1090
1091 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1092 .name = "mcbsp",
1093 .sysc = &omap3xxx_mcbsp_sysc,
1094 .rev = MCBSP_CONFIG_TYPE3,
1095 };
1096
1097 /* McBSP functional clock mapping */
1098 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
1099 { .role = "pad_fck", .clk = "mcbsp_clks" },
1100 { .role = "prcm_fck", .clk = "core_96m_fck" },
1101 };
1102
1103 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
1104 { .role = "pad_fck", .clk = "mcbsp_clks" },
1105 { .role = "prcm_fck", .clk = "per_96m_fck" },
1106 };
1107
1108 /* mcbsp1 */
1109 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
1110 { .name = "common", .irq = 16 },
1111 { .name = "tx", .irq = 59 },
1112 { .name = "rx", .irq = 60 },
1113 { .irq = -1 }
1114 };
1115
1116 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1117 .name = "mcbsp1",
1118 .class = &omap3xxx_mcbsp_hwmod_class,
1119 .mpu_irqs = omap3xxx_mcbsp1_irqs,
1120 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
1121 .main_clk = "mcbsp1_fck",
1122 .prcm = {
1123 .omap2 = {
1124 .prcm_reg_id = 1,
1125 .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
1126 .module_offs = CORE_MOD,
1127 .idlest_reg_id = 1,
1128 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
1129 },
1130 },
1131 .opt_clks = mcbsp15_opt_clks,
1132 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
1133 };
1134
1135 /* mcbsp2 */
1136 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
1137 { .name = "common", .irq = 17 },
1138 { .name = "tx", .irq = 62 },
1139 { .name = "rx", .irq = 63 },
1140 { .irq = -1 }
1141 };
1142
1143 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1144 .sidetone = "mcbsp2_sidetone",
1145 };
1146
1147 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1148 .name = "mcbsp2",
1149 .class = &omap3xxx_mcbsp_hwmod_class,
1150 .mpu_irqs = omap3xxx_mcbsp2_irqs,
1151 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
1152 .main_clk = "mcbsp2_fck",
1153 .prcm = {
1154 .omap2 = {
1155 .prcm_reg_id = 1,
1156 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1157 .module_offs = OMAP3430_PER_MOD,
1158 .idlest_reg_id = 1,
1159 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1160 },
1161 },
1162 .opt_clks = mcbsp234_opt_clks,
1163 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1164 .dev_attr = &omap34xx_mcbsp2_dev_attr,
1165 };
1166
1167 /* mcbsp3 */
1168 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
1169 { .name = "common", .irq = 22 },
1170 { .name = "tx", .irq = 89 },
1171 { .name = "rx", .irq = 90 },
1172 { .irq = -1 }
1173 };
1174
1175 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1176 .sidetone = "mcbsp3_sidetone",
1177 };
1178
1179 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1180 .name = "mcbsp3",
1181 .class = &omap3xxx_mcbsp_hwmod_class,
1182 .mpu_irqs = omap3xxx_mcbsp3_irqs,
1183 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
1184 .main_clk = "mcbsp3_fck",
1185 .prcm = {
1186 .omap2 = {
1187 .prcm_reg_id = 1,
1188 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1189 .module_offs = OMAP3430_PER_MOD,
1190 .idlest_reg_id = 1,
1191 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1192 },
1193 },
1194 .opt_clks = mcbsp234_opt_clks,
1195 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1196 .dev_attr = &omap34xx_mcbsp3_dev_attr,
1197 };
1198
1199 /* mcbsp4 */
1200 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
1201 { .name = "common", .irq = 23 },
1202 { .name = "tx", .irq = 54 },
1203 { .name = "rx", .irq = 55 },
1204 { .irq = -1 }
1205 };
1206
1207 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
1208 { .name = "rx", .dma_req = 20 },
1209 { .name = "tx", .dma_req = 19 },
1210 { .dma_req = -1 }
1211 };
1212
1213 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1214 .name = "mcbsp4",
1215 .class = &omap3xxx_mcbsp_hwmod_class,
1216 .mpu_irqs = omap3xxx_mcbsp4_irqs,
1217 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
1218 .main_clk = "mcbsp4_fck",
1219 .prcm = {
1220 .omap2 = {
1221 .prcm_reg_id = 1,
1222 .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
1223 .module_offs = OMAP3430_PER_MOD,
1224 .idlest_reg_id = 1,
1225 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
1226 },
1227 },
1228 .opt_clks = mcbsp234_opt_clks,
1229 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1230 };
1231
1232 /* mcbsp5 */
1233 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
1234 { .name = "common", .irq = 27 },
1235 { .name = "tx", .irq = 81 },
1236 { .name = "rx", .irq = 82 },
1237 { .irq = -1 }
1238 };
1239
1240 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
1241 { .name = "rx", .dma_req = 22 },
1242 { .name = "tx", .dma_req = 21 },
1243 { .dma_req = -1 }
1244 };
1245
1246 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1247 .name = "mcbsp5",
1248 .class = &omap3xxx_mcbsp_hwmod_class,
1249 .mpu_irqs = omap3xxx_mcbsp5_irqs,
1250 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
1251 .main_clk = "mcbsp5_fck",
1252 .prcm = {
1253 .omap2 = {
1254 .prcm_reg_id = 1,
1255 .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
1256 .module_offs = CORE_MOD,
1257 .idlest_reg_id = 1,
1258 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
1259 },
1260 },
1261 .opt_clks = mcbsp15_opt_clks,
1262 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
1263 };
1264
1265 /* 'mcbsp sidetone' class */
1266 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
1267 .sysc_offs = 0x0010,
1268 .sysc_flags = SYSC_HAS_AUTOIDLE,
1269 .sysc_fields = &omap_hwmod_sysc_type1,
1270 };
1271
1272 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
1273 .name = "mcbsp_sidetone",
1274 .sysc = &omap3xxx_mcbsp_sidetone_sysc,
1275 };
1276
1277 /* mcbsp2_sidetone */
1278 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
1279 { .name = "irq", .irq = 4 },
1280 { .irq = -1 }
1281 };
1282
1283 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1284 .name = "mcbsp2_sidetone",
1285 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1286 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
1287 .main_clk = "mcbsp2_fck",
1288 .prcm = {
1289 .omap2 = {
1290 .prcm_reg_id = 1,
1291 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1292 .module_offs = OMAP3430_PER_MOD,
1293 .idlest_reg_id = 1,
1294 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1295 },
1296 },
1297 };
1298
1299 /* mcbsp3_sidetone */
1300 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
1301 { .name = "irq", .irq = 5 },
1302 { .irq = -1 }
1303 };
1304
1305 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1306 .name = "mcbsp3_sidetone",
1307 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1308 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
1309 .main_clk = "mcbsp3_fck",
1310 .prcm = {
1311 .omap2 = {
1312 .prcm_reg_id = 1,
1313 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1314 .module_offs = OMAP3430_PER_MOD,
1315 .idlest_reg_id = 1,
1316 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1317 },
1318 },
1319 };
1320
1321 /* SR common */
1322 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1323 .clkact_shift = 20,
1324 };
1325
1326 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1327 .sysc_offs = 0x24,
1328 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1329 .clockact = CLOCKACT_TEST_ICLK,
1330 .sysc_fields = &omap34xx_sr_sysc_fields,
1331 };
1332
1333 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1334 .name = "smartreflex",
1335 .sysc = &omap34xx_sr_sysc,
1336 .rev = 1,
1337 };
1338
1339 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
1340 .sidle_shift = 24,
1341 .enwkup_shift = 26,
1342 };
1343
1344 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1345 .sysc_offs = 0x38,
1346 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1347 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1348 SYSC_NO_CACHE),
1349 .sysc_fields = &omap36xx_sr_sysc_fields,
1350 };
1351
1352 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1353 .name = "smartreflex",
1354 .sysc = &omap36xx_sr_sysc,
1355 .rev = 2,
1356 };
1357
1358 /* SR1 */
1359 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1360 .sensor_voltdm_name = "mpu_iva",
1361 };
1362
1363 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
1364 { .irq = 18 },
1365 { .irq = -1 }
1366 };
1367
1368 static struct omap_hwmod omap34xx_sr1_hwmod = {
1369 .name = "smartreflex_mpu_iva",
1370 .class = &omap34xx_smartreflex_hwmod_class,
1371 .main_clk = "sr1_fck",
1372 .prcm = {
1373 .omap2 = {
1374 .prcm_reg_id = 1,
1375 .module_bit = OMAP3430_EN_SR1_SHIFT,
1376 .module_offs = WKUP_MOD,
1377 .idlest_reg_id = 1,
1378 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1379 },
1380 },
1381 .dev_attr = &sr1_dev_attr,
1382 .mpu_irqs = omap3_smartreflex_mpu_irqs,
1383 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1384 };
1385
1386 static struct omap_hwmod omap36xx_sr1_hwmod = {
1387 .name = "smartreflex_mpu_iva",
1388 .class = &omap36xx_smartreflex_hwmod_class,
1389 .main_clk = "sr1_fck",
1390 .prcm = {
1391 .omap2 = {
1392 .prcm_reg_id = 1,
1393 .module_bit = OMAP3430_EN_SR1_SHIFT,
1394 .module_offs = WKUP_MOD,
1395 .idlest_reg_id = 1,
1396 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1397 },
1398 },
1399 .dev_attr = &sr1_dev_attr,
1400 .mpu_irqs = omap3_smartreflex_mpu_irqs,
1401 };
1402
1403 /* SR2 */
1404 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1405 .sensor_voltdm_name = "core",
1406 };
1407
1408 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
1409 { .irq = 19 },
1410 { .irq = -1 }
1411 };
1412
1413 static struct omap_hwmod omap34xx_sr2_hwmod = {
1414 .name = "smartreflex_core",
1415 .class = &omap34xx_smartreflex_hwmod_class,
1416 .main_clk = "sr2_fck",
1417 .prcm = {
1418 .omap2 = {
1419 .prcm_reg_id = 1,
1420 .module_bit = OMAP3430_EN_SR2_SHIFT,
1421 .module_offs = WKUP_MOD,
1422 .idlest_reg_id = 1,
1423 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1424 },
1425 },
1426 .dev_attr = &sr2_dev_attr,
1427 .mpu_irqs = omap3_smartreflex_core_irqs,
1428 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1429 };
1430
1431 static struct omap_hwmod omap36xx_sr2_hwmod = {
1432 .name = "smartreflex_core",
1433 .class = &omap36xx_smartreflex_hwmod_class,
1434 .main_clk = "sr2_fck",
1435 .prcm = {
1436 .omap2 = {
1437 .prcm_reg_id = 1,
1438 .module_bit = OMAP3430_EN_SR2_SHIFT,
1439 .module_offs = WKUP_MOD,
1440 .idlest_reg_id = 1,
1441 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1442 },
1443 },
1444 .dev_attr = &sr2_dev_attr,
1445 .mpu_irqs = omap3_smartreflex_core_irqs,
1446 };
1447
1448 /*
1449 * 'mailbox' class
1450 * mailbox module allowing communication between the on-chip processors
1451 * using a queued mailbox-interrupt mechanism.
1452 */
1453
1454 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1455 .rev_offs = 0x000,
1456 .sysc_offs = 0x010,
1457 .syss_offs = 0x014,
1458 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1459 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1460 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1461 .sysc_fields = &omap_hwmod_sysc_type1,
1462 };
1463
1464 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1465 .name = "mailbox",
1466 .sysc = &omap3xxx_mailbox_sysc,
1467 };
1468
1469 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
1470 { .irq = 26 },
1471 { .irq = -1 }
1472 };
1473
1474 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1475 .name = "mailbox",
1476 .class = &omap3xxx_mailbox_hwmod_class,
1477 .mpu_irqs = omap3xxx_mailbox_irqs,
1478 .main_clk = "mailboxes_ick",
1479 .prcm = {
1480 .omap2 = {
1481 .prcm_reg_id = 1,
1482 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1483 .module_offs = CORE_MOD,
1484 .idlest_reg_id = 1,
1485 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1486 },
1487 },
1488 };
1489
1490 /*
1491 * 'mcspi' class
1492 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1493 * bus
1494 */
1495
1496 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1497 .rev_offs = 0x0000,
1498 .sysc_offs = 0x0010,
1499 .syss_offs = 0x0014,
1500 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1501 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1502 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1503 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1504 .sysc_fields = &omap_hwmod_sysc_type1,
1505 };
1506
1507 static struct omap_hwmod_class omap34xx_mcspi_class = {
1508 .name = "mcspi",
1509 .sysc = &omap34xx_mcspi_sysc,
1510 .rev = OMAP3_MCSPI_REV,
1511 };
1512
1513 /* mcspi1 */
1514 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1515 .num_chipselect = 4,
1516 };
1517
1518 static struct omap_hwmod omap34xx_mcspi1 = {
1519 .name = "mcspi1",
1520 .mpu_irqs = omap2_mcspi1_mpu_irqs,
1521 .sdma_reqs = omap2_mcspi1_sdma_reqs,
1522 .main_clk = "mcspi1_fck",
1523 .prcm = {
1524 .omap2 = {
1525 .module_offs = CORE_MOD,
1526 .prcm_reg_id = 1,
1527 .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
1528 .idlest_reg_id = 1,
1529 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1530 },
1531 },
1532 .class = &omap34xx_mcspi_class,
1533 .dev_attr = &omap_mcspi1_dev_attr,
1534 };
1535
1536 /* mcspi2 */
1537 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1538 .num_chipselect = 2,
1539 };
1540
1541 static struct omap_hwmod omap34xx_mcspi2 = {
1542 .name = "mcspi2",
1543 .mpu_irqs = omap2_mcspi2_mpu_irqs,
1544 .sdma_reqs = omap2_mcspi2_sdma_reqs,
1545 .main_clk = "mcspi2_fck",
1546 .prcm = {
1547 .omap2 = {
1548 .module_offs = CORE_MOD,
1549 .prcm_reg_id = 1,
1550 .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
1551 .idlest_reg_id = 1,
1552 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1553 },
1554 },
1555 .class = &omap34xx_mcspi_class,
1556 .dev_attr = &omap_mcspi2_dev_attr,
1557 };
1558
1559 /* mcspi3 */
1560 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
1561 { .name = "irq", .irq = 91 }, /* 91 */
1562 { .irq = -1 }
1563 };
1564
1565 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
1566 { .name = "tx0", .dma_req = 15 },
1567 { .name = "rx0", .dma_req = 16 },
1568 { .name = "tx1", .dma_req = 23 },
1569 { .name = "rx1", .dma_req = 24 },
1570 { .dma_req = -1 }
1571 };
1572
1573 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1574 .num_chipselect = 2,
1575 };
1576
1577 static struct omap_hwmod omap34xx_mcspi3 = {
1578 .name = "mcspi3",
1579 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
1580 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
1581 .main_clk = "mcspi3_fck",
1582 .prcm = {
1583 .omap2 = {
1584 .module_offs = CORE_MOD,
1585 .prcm_reg_id = 1,
1586 .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
1587 .idlest_reg_id = 1,
1588 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1589 },
1590 },
1591 .class = &omap34xx_mcspi_class,
1592 .dev_attr = &omap_mcspi3_dev_attr,
1593 };
1594
1595 /* mcspi4 */
1596 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
1597 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
1598 { .irq = -1 }
1599 };
1600
1601 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
1602 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
1603 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
1604 { .dma_req = -1 }
1605 };
1606
1607 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1608 .num_chipselect = 1,
1609 };
1610
1611 static struct omap_hwmod omap34xx_mcspi4 = {
1612 .name = "mcspi4",
1613 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
1614 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
1615 .main_clk = "mcspi4_fck",
1616 .prcm = {
1617 .omap2 = {
1618 .module_offs = CORE_MOD,
1619 .prcm_reg_id = 1,
1620 .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
1621 .idlest_reg_id = 1,
1622 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1623 },
1624 },
1625 .class = &omap34xx_mcspi_class,
1626 .dev_attr = &omap_mcspi4_dev_attr,
1627 };
1628
1629 /* usbhsotg */
1630 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1631 .rev_offs = 0x0400,
1632 .sysc_offs = 0x0404,
1633 .syss_offs = 0x0408,
1634 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1635 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1636 SYSC_HAS_AUTOIDLE),
1637 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1638 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1639 .sysc_fields = &omap_hwmod_sysc_type1,
1640 };
1641
1642 static struct omap_hwmod_class usbotg_class = {
1643 .name = "usbotg",
1644 .sysc = &omap3xxx_usbhsotg_sysc,
1645 };
1646
1647 /* usb_otg_hs */
1648 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
1649
1650 { .name = "mc", .irq = 92 },
1651 { .name = "dma", .irq = 93 },
1652 { .irq = -1 }
1653 };
1654
1655 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1656 .name = "usb_otg_hs",
1657 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
1658 .main_clk = "hsotgusb_ick",
1659 .prcm = {
1660 .omap2 = {
1661 .prcm_reg_id = 1,
1662 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1663 .module_offs = CORE_MOD,
1664 .idlest_reg_id = 1,
1665 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1666 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
1667 },
1668 },
1669 .class = &usbotg_class,
1670
1671 /*
1672 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
1673 * broken when autoidle is enabled
1674 * workaround is to disable the autoidle bit at module level.
1675 */
1676 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
1677 | HWMOD_SWSUP_MSTANDBY,
1678 };
1679
1680 /* usb_otg_hs */
1681 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
1682 { .name = "mc", .irq = 71 },
1683 { .irq = -1 }
1684 };
1685
1686 static struct omap_hwmod_class am35xx_usbotg_class = {
1687 .name = "am35xx_usbotg",
1688 };
1689
1690 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1691 .name = "am35x_otg_hs",
1692 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
1693 .main_clk = "hsotgusb_fck",
1694 .class = &am35xx_usbotg_class,
1695 .flags = HWMOD_NO_IDLEST,
1696 };
1697
1698 /* MMC/SD/SDIO common */
1699 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1700 .rev_offs = 0x1fc,
1701 .sysc_offs = 0x10,
1702 .syss_offs = 0x14,
1703 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1704 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1705 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1706 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1707 .sysc_fields = &omap_hwmod_sysc_type1,
1708 };
1709
1710 static struct omap_hwmod_class omap34xx_mmc_class = {
1711 .name = "mmc",
1712 .sysc = &omap34xx_mmc_sysc,
1713 };
1714
1715 /* MMC/SD/SDIO1 */
1716
1717 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
1718 { .irq = 83, },
1719 { .irq = -1 }
1720 };
1721
1722 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
1723 { .name = "tx", .dma_req = 61, },
1724 { .name = "rx", .dma_req = 62, },
1725 { .dma_req = -1 }
1726 };
1727
1728 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1729 { .role = "dbck", .clk = "omap_32k_fck", },
1730 };
1731
1732 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1733 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1734 };
1735
1736 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1737 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
1738 .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1739 OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1740 };
1741
1742 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1743 .name = "mmc1",
1744 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
1745 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
1746 .opt_clks = omap34xx_mmc1_opt_clks,
1747 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1748 .main_clk = "mmchs1_fck",
1749 .prcm = {
1750 .omap2 = {
1751 .module_offs = CORE_MOD,
1752 .prcm_reg_id = 1,
1753 .module_bit = OMAP3430_EN_MMC1_SHIFT,
1754 .idlest_reg_id = 1,
1755 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1756 },
1757 },
1758 .dev_attr = &mmc1_pre_es3_dev_attr,
1759 .class = &omap34xx_mmc_class,
1760 };
1761
1762 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1763 .name = "mmc1",
1764 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
1765 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
1766 .opt_clks = omap34xx_mmc1_opt_clks,
1767 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1768 .main_clk = "mmchs1_fck",
1769 .prcm = {
1770 .omap2 = {
1771 .module_offs = CORE_MOD,
1772 .prcm_reg_id = 1,
1773 .module_bit = OMAP3430_EN_MMC1_SHIFT,
1774 .idlest_reg_id = 1,
1775 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1776 },
1777 },
1778 .dev_attr = &mmc1_dev_attr,
1779 .class = &omap34xx_mmc_class,
1780 };
1781
1782 /* MMC/SD/SDIO2 */
1783
1784 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
1785 { .irq = INT_24XX_MMC2_IRQ, },
1786 { .irq = -1 }
1787 };
1788
1789 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
1790 { .name = "tx", .dma_req = 47, },
1791 { .name = "rx", .dma_req = 48, },
1792 { .dma_req = -1 }
1793 };
1794
1795 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1796 { .role = "dbck", .clk = "omap_32k_fck", },
1797 };
1798
1799 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1800 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
1801 .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1802 };
1803
1804 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1805 .name = "mmc2",
1806 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
1807 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
1808 .opt_clks = omap34xx_mmc2_opt_clks,
1809 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1810 .main_clk = "mmchs2_fck",
1811 .prcm = {
1812 .omap2 = {
1813 .module_offs = CORE_MOD,
1814 .prcm_reg_id = 1,
1815 .module_bit = OMAP3430_EN_MMC2_SHIFT,
1816 .idlest_reg_id = 1,
1817 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1818 },
1819 },
1820 .dev_attr = &mmc2_pre_es3_dev_attr,
1821 .class = &omap34xx_mmc_class,
1822 };
1823
1824 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1825 .name = "mmc2",
1826 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
1827 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
1828 .opt_clks = omap34xx_mmc2_opt_clks,
1829 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1830 .main_clk = "mmchs2_fck",
1831 .prcm = {
1832 .omap2 = {
1833 .module_offs = CORE_MOD,
1834 .prcm_reg_id = 1,
1835 .module_bit = OMAP3430_EN_MMC2_SHIFT,
1836 .idlest_reg_id = 1,
1837 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1838 },
1839 },
1840 .class = &omap34xx_mmc_class,
1841 };
1842
1843 /* MMC/SD/SDIO3 */
1844
1845 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
1846 { .irq = 94, },
1847 { .irq = -1 }
1848 };
1849
1850 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
1851 { .name = "tx", .dma_req = 77, },
1852 { .name = "rx", .dma_req = 78, },
1853 { .dma_req = -1 }
1854 };
1855
1856 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1857 { .role = "dbck", .clk = "omap_32k_fck", },
1858 };
1859
1860 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1861 .name = "mmc3",
1862 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
1863 .sdma_reqs = omap34xx_mmc3_sdma_reqs,
1864 .opt_clks = omap34xx_mmc3_opt_clks,
1865 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1866 .main_clk = "mmchs3_fck",
1867 .prcm = {
1868 .omap2 = {
1869 .prcm_reg_id = 1,
1870 .module_bit = OMAP3430_EN_MMC3_SHIFT,
1871 .idlest_reg_id = 1,
1872 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1873 },
1874 },
1875 .class = &omap34xx_mmc_class,
1876 };
1877
1878 /*
1879 * 'usb_host_hs' class
1880 * high-speed multi-port usb host controller
1881 */
1882
1883 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1884 .rev_offs = 0x0000,
1885 .sysc_offs = 0x0010,
1886 .syss_offs = 0x0014,
1887 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1888 SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1889 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1890 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1891 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1892 .sysc_fields = &omap_hwmod_sysc_type1,
1893 };
1894
1895 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1896 .name = "usb_host_hs",
1897 .sysc = &omap3xxx_usb_host_hs_sysc,
1898 };
1899
1900 static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
1901 { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
1902 };
1903
1904 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
1905 { .name = "ohci-irq", .irq = 76 },
1906 { .name = "ehci-irq", .irq = 77 },
1907 { .irq = -1 }
1908 };
1909
1910 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1911 .name = "usb_host_hs",
1912 .class = &omap3xxx_usb_host_hs_hwmod_class,
1913 .clkdm_name = "l3_init_clkdm",
1914 .mpu_irqs = omap3xxx_usb_host_hs_irqs,
1915 .main_clk = "usbhost_48m_fck",
1916 .prcm = {
1917 .omap2 = {
1918 .module_offs = OMAP3430ES2_USBHOST_MOD,
1919 .prcm_reg_id = 1,
1920 .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
1921 .idlest_reg_id = 1,
1922 .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1923 .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
1924 },
1925 },
1926 .opt_clks = omap3xxx_usb_host_hs_opt_clks,
1927 .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
1928
1929 /*
1930 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1931 * id: i660
1932 *
1933 * Description:
1934 * In the following configuration :
1935 * - USBHOST module is set to smart-idle mode
1936 * - PRCM asserts idle_req to the USBHOST module ( This typically
1937 * happens when the system is going to a low power mode : all ports
1938 * have been suspended, the master part of the USBHOST module has
1939 * entered the standby state, and SW has cut the functional clocks)
1940 * - an USBHOST interrupt occurs before the module is able to answer
1941 * idle_ack, typically a remote wakeup IRQ.
1942 * Then the USB HOST module will enter a deadlock situation where it
1943 * is no more accessible nor functional.
1944 *
1945 * Workaround:
1946 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1947 */
1948
1949 /*
1950 * Errata: USB host EHCI may stall when entering smart-standby mode
1951 * Id: i571
1952 *
1953 * Description:
1954 * When the USBHOST module is set to smart-standby mode, and when it is
1955 * ready to enter the standby state (i.e. all ports are suspended and
1956 * all attached devices are in suspend mode), then it can wrongly assert
1957 * the Mstandby signal too early while there are still some residual OCP
1958 * transactions ongoing. If this condition occurs, the internal state
1959 * machine may go to an undefined state and the USB link may be stuck
1960 * upon the next resume.
1961 *
1962 * Workaround:
1963 * Don't use smart standby; use only force standby,
1964 * hence HWMOD_SWSUP_MSTANDBY
1965 */
1966
1967 /*
1968 * During system boot; If the hwmod framework resets the module
1969 * the module will have smart idle settings; which can lead to deadlock
1970 * (above Errata Id:i660); so, dont reset the module during boot;
1971 * Use HWMOD_INIT_NO_RESET.
1972 */
1973
1974 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
1975 HWMOD_INIT_NO_RESET,
1976 };
1977
1978 /*
1979 * 'usb_tll_hs' class
1980 * usb_tll_hs module is the adapter on the usb_host_hs ports
1981 */
1982 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
1983 .rev_offs = 0x0000,
1984 .sysc_offs = 0x0010,
1985 .syss_offs = 0x0014,
1986 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1987 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1988 SYSC_HAS_AUTOIDLE),
1989 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1990 .sysc_fields = &omap_hwmod_sysc_type1,
1991 };
1992
1993 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
1994 .name = "usb_tll_hs",
1995 .sysc = &omap3xxx_usb_tll_hs_sysc,
1996 };
1997
1998 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
1999 { .name = "tll-irq", .irq = 78 },
2000 { .irq = -1 }
2001 };
2002
2003 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
2004 .name = "usb_tll_hs",
2005 .class = &omap3xxx_usb_tll_hs_hwmod_class,
2006 .clkdm_name = "l3_init_clkdm",
2007 .mpu_irqs = omap3xxx_usb_tll_hs_irqs,
2008 .main_clk = "usbtll_fck",
2009 .prcm = {
2010 .omap2 = {
2011 .module_offs = CORE_MOD,
2012 .prcm_reg_id = 3,
2013 .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
2014 .idlest_reg_id = 3,
2015 .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
2016 },
2017 },
2018 };
2019
2020 static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
2021 .name = "hdq1w",
2022 .mpu_irqs = omap2_hdq1w_mpu_irqs,
2023 .main_clk = "hdq_fck",
2024 .prcm = {
2025 .omap2 = {
2026 .module_offs = CORE_MOD,
2027 .prcm_reg_id = 1,
2028 .module_bit = OMAP3430_EN_HDQ_SHIFT,
2029 .idlest_reg_id = 1,
2030 .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
2031 },
2032 },
2033 .class = &omap2_hdq1w_class,
2034 };
2035
2036 /*
2037 * '32K sync counter' class
2038 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
2039 */
2040 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
2041 .rev_offs = 0x0000,
2042 .sysc_offs = 0x0004,
2043 .sysc_flags = SYSC_HAS_SIDLEMODE,
2044 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
2045 .sysc_fields = &omap_hwmod_sysc_type1,
2046 };
2047
2048 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
2049 .name = "counter",
2050 .sysc = &omap3xxx_counter_sysc,
2051 };
2052
2053 static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
2054 .name = "counter_32k",
2055 .class = &omap3xxx_counter_hwmod_class,
2056 .clkdm_name = "wkup_clkdm",
2057 .flags = HWMOD_SWSUP_SIDLE,
2058 .main_clk = "wkup_32k_fck",
2059 .prcm = {
2060 .omap2 = {
2061 .module_offs = WKUP_MOD,
2062 .prcm_reg_id = 1,
2063 .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
2064 .idlest_reg_id = 1,
2065 .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
2066 },
2067 },
2068 };
2069
2070 /*
2071 * interfaces
2072 */
2073
2074 /* L3 -> L4_CORE interface */
2075 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
2076 .master = &omap3xxx_l3_main_hwmod,
2077 .slave = &omap3xxx_l4_core_hwmod,
2078 .user = OCP_USER_MPU | OCP_USER_SDMA,
2079 };
2080
2081 /* L3 -> L4_PER interface */
2082 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
2083 .master = &omap3xxx_l3_main_hwmod,
2084 .slave = &omap3xxx_l4_per_hwmod,
2085 .user = OCP_USER_MPU | OCP_USER_SDMA,
2086 };
2087
2088 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
2089 {
2090 .pa_start = 0x68000000,
2091 .pa_end = 0x6800ffff,
2092 .flags = ADDR_TYPE_RT,
2093 },
2094 { }
2095 };
2096
2097 /* MPU -> L3 interface */
2098 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
2099 .master = &omap3xxx_mpu_hwmod,
2100 .slave = &omap3xxx_l3_main_hwmod,
2101 .addr = omap3xxx_l3_main_addrs,
2102 .user = OCP_USER_MPU,
2103 };
2104
2105 /* DSS -> l3 */
2106 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
2107 .master = &omap3430es1_dss_core_hwmod,
2108 .slave = &omap3xxx_l3_main_hwmod,
2109 .user = OCP_USER_MPU | OCP_USER_SDMA,
2110 };
2111
2112 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
2113 .master = &omap3xxx_dss_core_hwmod,
2114 .slave = &omap3xxx_l3_main_hwmod,
2115 .fw = {
2116 .omap2 = {
2117 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
2118 .flags = OMAP_FIREWALL_L3,
2119 }
2120 },
2121 .user = OCP_USER_MPU | OCP_USER_SDMA,
2122 };
2123
2124 /* l3_core -> usbhsotg interface */
2125 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
2126 .master = &omap3xxx_usbhsotg_hwmod,
2127 .slave = &omap3xxx_l3_main_hwmod,
2128 .clk = "core_l3_ick",
2129 .user = OCP_USER_MPU,
2130 };
2131
2132 /* l3_core -> am35xx_usbhsotg interface */
2133 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
2134 .master = &am35xx_usbhsotg_hwmod,
2135 .slave = &omap3xxx_l3_main_hwmod,
2136 .clk = "hsotgusb_ick",
2137 .user = OCP_USER_MPU,
2138 };
2139
2140 /* L4_CORE -> L4_WKUP interface */
2141 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
2142 .master = &omap3xxx_l4_core_hwmod,
2143 .slave = &omap3xxx_l4_wkup_hwmod,
2144 .user = OCP_USER_MPU | OCP_USER_SDMA,
2145 };
2146
2147 /* L4 CORE -> MMC1 interface */
2148 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
2149 .master = &omap3xxx_l4_core_hwmod,
2150 .slave = &omap3xxx_pre_es3_mmc1_hwmod,
2151 .clk = "mmchs1_ick",
2152 .addr = omap2430_mmc1_addr_space,
2153 .user = OCP_USER_MPU | OCP_USER_SDMA,
2154 .flags = OMAP_FIREWALL_L4
2155 };
2156
2157 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
2158 .master = &omap3xxx_l4_core_hwmod,
2159 .slave = &omap3xxx_es3plus_mmc1_hwmod,
2160 .clk = "mmchs1_ick",
2161 .addr = omap2430_mmc1_addr_space,
2162 .user = OCP_USER_MPU | OCP_USER_SDMA,
2163 .flags = OMAP_FIREWALL_L4
2164 };
2165
2166 /* L4 CORE -> MMC2 interface */
2167 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
2168 .master = &omap3xxx_l4_core_hwmod,
2169 .slave = &omap3xxx_pre_es3_mmc2_hwmod,
2170 .clk = "mmchs2_ick",
2171 .addr = omap2430_mmc2_addr_space,
2172 .user = OCP_USER_MPU | OCP_USER_SDMA,
2173 .flags = OMAP_FIREWALL_L4
2174 };
2175
2176 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2177 .master = &omap3xxx_l4_core_hwmod,
2178 .slave = &omap3xxx_es3plus_mmc2_hwmod,
2179 .clk = "mmchs2_ick",
2180 .addr = omap2430_mmc2_addr_space,
2181 .user = OCP_USER_MPU | OCP_USER_SDMA,
2182 .flags = OMAP_FIREWALL_L4
2183 };
2184
2185 /* L4 CORE -> MMC3 interface */
2186 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
2187 {
2188 .pa_start = 0x480ad000,
2189 .pa_end = 0x480ad1ff,
2190 .flags = ADDR_TYPE_RT,
2191 },
2192 { }
2193 };
2194
2195 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2196 .master = &omap3xxx_l4_core_hwmod,
2197 .slave = &omap3xxx_mmc3_hwmod,
2198 .clk = "mmchs3_ick",
2199 .addr = omap3xxx_mmc3_addr_space,
2200 .user = OCP_USER_MPU | OCP_USER_SDMA,
2201 .flags = OMAP_FIREWALL_L4
2202 };
2203
2204 /* L4 CORE -> UART1 interface */
2205 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
2206 {
2207 .pa_start = OMAP3_UART1_BASE,
2208 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
2209 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2210 },
2211 { }
2212 };
2213
2214 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2215 .master = &omap3xxx_l4_core_hwmod,
2216 .slave = &omap3xxx_uart1_hwmod,
2217 .clk = "uart1_ick",
2218 .addr = omap3xxx_uart1_addr_space,
2219 .user = OCP_USER_MPU | OCP_USER_SDMA,
2220 };
2221
2222 /* L4 CORE -> UART2 interface */
2223 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
2224 {
2225 .pa_start = OMAP3_UART2_BASE,
2226 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
2227 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2228 },
2229 { }
2230 };
2231
2232 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2233 .master = &omap3xxx_l4_core_hwmod,
2234 .slave = &omap3xxx_uart2_hwmod,
2235 .clk = "uart2_ick",
2236 .addr = omap3xxx_uart2_addr_space,
2237 .user = OCP_USER_MPU | OCP_USER_SDMA,
2238 };
2239
2240 /* L4 PER -> UART3 interface */
2241 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
2242 {
2243 .pa_start = OMAP3_UART3_BASE,
2244 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
2245 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2246 },
2247 { }
2248 };
2249
2250 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2251 .master = &omap3xxx_l4_per_hwmod,
2252 .slave = &omap3xxx_uart3_hwmod,
2253 .clk = "uart3_ick",
2254 .addr = omap3xxx_uart3_addr_space,
2255 .user = OCP_USER_MPU | OCP_USER_SDMA,
2256 };
2257
2258 /* L4 PER -> UART4 interface */
2259 static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
2260 {
2261 .pa_start = OMAP3_UART4_BASE,
2262 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
2263 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2264 },
2265 { }
2266 };
2267
2268 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2269 .master = &omap3xxx_l4_per_hwmod,
2270 .slave = &omap36xx_uart4_hwmod,
2271 .clk = "uart4_ick",
2272 .addr = omap36xx_uart4_addr_space,
2273 .user = OCP_USER_MPU | OCP_USER_SDMA,
2274 };
2275
2276 /* AM35xx: L4 CORE -> UART4 interface */
2277 static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
2278 {
2279 .pa_start = OMAP3_UART4_AM35XX_BASE,
2280 .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
2281 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2282 },
2283 { }
2284 };
2285
2286 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2287 .master = &omap3xxx_l4_core_hwmod,
2288 .slave = &am35xx_uart4_hwmod,
2289 .clk = "uart4_ick",
2290 .addr = am35xx_uart4_addr_space,
2291 .user = OCP_USER_MPU | OCP_USER_SDMA,
2292 };
2293
2294 /* L4 CORE -> I2C1 interface */
2295 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2296 .master = &omap3xxx_l4_core_hwmod,
2297 .slave = &omap3xxx_i2c1_hwmod,
2298 .clk = "i2c1_ick",
2299 .addr = omap2_i2c1_addr_space,
2300 .fw = {
2301 .omap2 = {
2302 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
2303 .l4_prot_group = 7,
2304 .flags = OMAP_FIREWALL_L4,
2305 }
2306 },
2307 .user = OCP_USER_MPU | OCP_USER_SDMA,
2308 };
2309
2310 /* L4 CORE -> I2C2 interface */
2311 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2312 .master = &omap3xxx_l4_core_hwmod,
2313 .slave = &omap3xxx_i2c2_hwmod,
2314 .clk = "i2c2_ick",
2315 .addr = omap2_i2c2_addr_space,
2316 .fw = {
2317 .omap2 = {
2318 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
2319 .l4_prot_group = 7,
2320 .flags = OMAP_FIREWALL_L4,
2321 }
2322 },
2323 .user = OCP_USER_MPU | OCP_USER_SDMA,
2324 };
2325
2326 /* L4 CORE -> I2C3 interface */
2327 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
2328 {
2329 .pa_start = 0x48060000,
2330 .pa_end = 0x48060000 + SZ_128 - 1,
2331 .flags = ADDR_TYPE_RT,
2332 },
2333 { }
2334 };
2335
2336 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2337 .master = &omap3xxx_l4_core_hwmod,
2338 .slave = &omap3xxx_i2c3_hwmod,
2339 .clk = "i2c3_ick",
2340 .addr = omap3xxx_i2c3_addr_space,
2341 .fw = {
2342 .omap2 = {
2343 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
2344 .l4_prot_group = 7,
2345 .flags = OMAP_FIREWALL_L4,
2346 }
2347 },
2348 .user = OCP_USER_MPU | OCP_USER_SDMA,
2349 };
2350
2351 /* L4 CORE -> SR1 interface */
2352 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
2353 {
2354 .pa_start = OMAP34XX_SR1_BASE,
2355 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
2356 .flags = ADDR_TYPE_RT,
2357 },
2358 { }
2359 };
2360
2361 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2362 .master = &omap3xxx_l4_core_hwmod,
2363 .slave = &omap34xx_sr1_hwmod,
2364 .clk = "sr_l4_ick",
2365 .addr = omap3_sr1_addr_space,
2366 .user = OCP_USER_MPU,
2367 };
2368
2369 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2370 .master = &omap3xxx_l4_core_hwmod,
2371 .slave = &omap36xx_sr1_hwmod,
2372 .clk = "sr_l4_ick",
2373 .addr = omap3_sr1_addr_space,
2374 .user = OCP_USER_MPU,
2375 };
2376
2377 /* L4 CORE -> SR1 interface */
2378 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
2379 {
2380 .pa_start = OMAP34XX_SR2_BASE,
2381 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
2382 .flags = ADDR_TYPE_RT,
2383 },
2384 { }
2385 };
2386
2387 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2388 .master = &omap3xxx_l4_core_hwmod,
2389 .slave = &omap34xx_sr2_hwmod,
2390 .clk = "sr_l4_ick",
2391 .addr = omap3_sr2_addr_space,
2392 .user = OCP_USER_MPU,
2393 };
2394
2395 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2396 .master = &omap3xxx_l4_core_hwmod,
2397 .slave = &omap36xx_sr2_hwmod,
2398 .clk = "sr_l4_ick",
2399 .addr = omap3_sr2_addr_space,
2400 .user = OCP_USER_MPU,
2401 };
2402
2403 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
2404 {
2405 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
2406 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
2407 .flags = ADDR_TYPE_RT
2408 },
2409 { }
2410 };
2411
2412 /* l4_core -> usbhsotg */
2413 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2414 .master = &omap3xxx_l4_core_hwmod,
2415 .slave = &omap3xxx_usbhsotg_hwmod,
2416 .clk = "l4_ick",
2417 .addr = omap3xxx_usbhsotg_addrs,
2418 .user = OCP_USER_MPU,
2419 };
2420
2421 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
2422 {
2423 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
2424 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
2425 .flags = ADDR_TYPE_RT
2426 },
2427 { }
2428 };
2429
2430 /* l4_core -> usbhsotg */
2431 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2432 .master = &omap3xxx_l4_core_hwmod,
2433 .slave = &am35xx_usbhsotg_hwmod,
2434 .clk = "hsotgusb_ick",
2435 .addr = am35xx_usbhsotg_addrs,
2436 .user = OCP_USER_MPU,
2437 };
2438
2439 /* L4_WKUP -> L4_SEC interface */
2440 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2441 .master = &omap3xxx_l4_wkup_hwmod,
2442 .slave = &omap3xxx_l4_sec_hwmod,
2443 .user = OCP_USER_MPU | OCP_USER_SDMA,
2444 };
2445
2446 /* IVA2 <- L3 interface */
2447 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2448 .master = &omap3xxx_l3_main_hwmod,
2449 .slave = &omap3xxx_iva_hwmod,
2450 .clk = "core_l3_ick",
2451 .user = OCP_USER_MPU | OCP_USER_SDMA,
2452 };
2453
2454 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
2455 {
2456 .pa_start = 0x48318000,
2457 .pa_end = 0x48318000 + SZ_1K - 1,
2458 .flags = ADDR_TYPE_RT
2459 },
2460 { }
2461 };
2462
2463 /* l4_wkup -> timer1 */
2464 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2465 .master = &omap3xxx_l4_wkup_hwmod,
2466 .slave = &omap3xxx_timer1_hwmod,
2467 .clk = "gpt1_ick",
2468 .addr = omap3xxx_timer1_addrs,
2469 .user = OCP_USER_MPU | OCP_USER_SDMA,
2470 };
2471
2472 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
2473 {
2474 .pa_start = 0x49032000,
2475 .pa_end = 0x49032000 + SZ_1K - 1,
2476 .flags = ADDR_TYPE_RT
2477 },
2478 { }
2479 };
2480
2481 /* l4_per -> timer2 */
2482 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2483 .master = &omap3xxx_l4_per_hwmod,
2484 .slave = &omap3xxx_timer2_hwmod,
2485 .clk = "gpt2_ick",
2486 .addr = omap3xxx_timer2_addrs,
2487 .user = OCP_USER_MPU | OCP_USER_SDMA,
2488 };
2489
2490 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
2491 {
2492 .pa_start = 0x49034000,
2493 .pa_end = 0x49034000 + SZ_1K - 1,
2494 .flags = ADDR_TYPE_RT
2495 },
2496 { }
2497 };
2498
2499 /* l4_per -> timer3 */
2500 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2501 .master = &omap3xxx_l4_per_hwmod,
2502 .slave = &omap3xxx_timer3_hwmod,
2503 .clk = "gpt3_ick",
2504 .addr = omap3xxx_timer3_addrs,
2505 .user = OCP_USER_MPU | OCP_USER_SDMA,
2506 };
2507
2508 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
2509 {
2510 .pa_start = 0x49036000,
2511 .pa_end = 0x49036000 + SZ_1K - 1,
2512 .flags = ADDR_TYPE_RT
2513 },
2514 { }
2515 };
2516
2517 /* l4_per -> timer4 */
2518 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2519 .master = &omap3xxx_l4_per_hwmod,
2520 .slave = &omap3xxx_timer4_hwmod,
2521 .clk = "gpt4_ick",
2522 .addr = omap3xxx_timer4_addrs,
2523 .user = OCP_USER_MPU | OCP_USER_SDMA,
2524 };
2525
2526 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
2527 {
2528 .pa_start = 0x49038000,
2529 .pa_end = 0x49038000 + SZ_1K - 1,
2530 .flags = ADDR_TYPE_RT
2531 },
2532 { }
2533 };
2534
2535 /* l4_per -> timer5 */
2536 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2537 .master = &omap3xxx_l4_per_hwmod,
2538 .slave = &omap3xxx_timer5_hwmod,
2539 .clk = "gpt5_ick",
2540 .addr = omap3xxx_timer5_addrs,
2541 .user = OCP_USER_MPU | OCP_USER_SDMA,
2542 };
2543
2544 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
2545 {
2546 .pa_start = 0x4903A000,
2547 .pa_end = 0x4903A000 + SZ_1K - 1,
2548 .flags = ADDR_TYPE_RT
2549 },
2550 { }
2551 };
2552
2553 /* l4_per -> timer6 */
2554 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2555 .master = &omap3xxx_l4_per_hwmod,
2556 .slave = &omap3xxx_timer6_hwmod,
2557 .clk = "gpt6_ick",
2558 .addr = omap3xxx_timer6_addrs,
2559 .user = OCP_USER_MPU | OCP_USER_SDMA,
2560 };
2561
2562 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
2563 {
2564 .pa_start = 0x4903C000,
2565 .pa_end = 0x4903C000 + SZ_1K - 1,
2566 .flags = ADDR_TYPE_RT
2567 },
2568 { }
2569 };
2570
2571 /* l4_per -> timer7 */
2572 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2573 .master = &omap3xxx_l4_per_hwmod,
2574 .slave = &omap3xxx_timer7_hwmod,
2575 .clk = "gpt7_ick",
2576 .addr = omap3xxx_timer7_addrs,
2577 .user = OCP_USER_MPU | OCP_USER_SDMA,
2578 };
2579
2580 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
2581 {
2582 .pa_start = 0x4903E000,
2583 .pa_end = 0x4903E000 + SZ_1K - 1,
2584 .flags = ADDR_TYPE_RT
2585 },
2586 { }
2587 };
2588
2589 /* l4_per -> timer8 */
2590 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2591 .master = &omap3xxx_l4_per_hwmod,
2592 .slave = &omap3xxx_timer8_hwmod,
2593 .clk = "gpt8_ick",
2594 .addr = omap3xxx_timer8_addrs,
2595 .user = OCP_USER_MPU | OCP_USER_SDMA,
2596 };
2597
2598 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
2599 {
2600 .pa_start = 0x49040000,
2601 .pa_end = 0x49040000 + SZ_1K - 1,
2602 .flags = ADDR_TYPE_RT
2603 },
2604 { }
2605 };
2606
2607 /* l4_per -> timer9 */
2608 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2609 .master = &omap3xxx_l4_per_hwmod,
2610 .slave = &omap3xxx_timer9_hwmod,
2611 .clk = "gpt9_ick",
2612 .addr = omap3xxx_timer9_addrs,
2613 .user = OCP_USER_MPU | OCP_USER_SDMA,
2614 };
2615
2616 /* l4_core -> timer10 */
2617 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2618 .master = &omap3xxx_l4_core_hwmod,
2619 .slave = &omap3xxx_timer10_hwmod,
2620 .clk = "gpt10_ick",
2621 .addr = omap2_timer10_addrs,
2622 .user = OCP_USER_MPU | OCP_USER_SDMA,
2623 };
2624
2625 /* l4_core -> timer11 */
2626 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2627 .master = &omap3xxx_l4_core_hwmod,
2628 .slave = &omap3xxx_timer11_hwmod,
2629 .clk = "gpt11_ick",
2630 .addr = omap2_timer11_addrs,
2631 .user = OCP_USER_MPU | OCP_USER_SDMA,
2632 };
2633
2634 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
2635 {
2636 .pa_start = 0x48304000,
2637 .pa_end = 0x48304000 + SZ_1K - 1,
2638 .flags = ADDR_TYPE_RT
2639 },
2640 { }
2641 };
2642
2643 /* l4_core -> timer12 */
2644 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2645 .master = &omap3xxx_l4_sec_hwmod,
2646 .slave = &omap3xxx_timer12_hwmod,
2647 .clk = "gpt12_ick",
2648 .addr = omap3xxx_timer12_addrs,
2649 .user = OCP_USER_MPU | OCP_USER_SDMA,
2650 };
2651
2652 /* l4_wkup -> wd_timer2 */
2653 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
2654 {
2655 .pa_start = 0x48314000,
2656 .pa_end = 0x4831407f,
2657 .flags = ADDR_TYPE_RT
2658 },
2659 { }
2660 };
2661
2662 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2663 .master = &omap3xxx_l4_wkup_hwmod,
2664 .slave = &omap3xxx_wd_timer2_hwmod,
2665 .clk = "wdt2_ick",
2666 .addr = omap3xxx_wd_timer2_addrs,
2667 .user = OCP_USER_MPU | OCP_USER_SDMA,
2668 };
2669
2670 /* l4_core -> dss */
2671 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2672 .master = &omap3xxx_l4_core_hwmod,
2673 .slave = &omap3430es1_dss_core_hwmod,
2674 .clk = "dss_ick",
2675 .addr = omap2_dss_addrs,
2676 .fw = {
2677 .omap2 = {
2678 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2679 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2680 .flags = OMAP_FIREWALL_L4,
2681 }
2682 },
2683 .user = OCP_USER_MPU | OCP_USER_SDMA,
2684 };
2685
2686 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2687 .master = &omap3xxx_l4_core_hwmod,
2688 .slave = &omap3xxx_dss_core_hwmod,
2689 .clk = "dss_ick",
2690 .addr = omap2_dss_addrs,
2691 .fw = {
2692 .omap2 = {
2693 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2694 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2695 .flags = OMAP_FIREWALL_L4,
2696 }
2697 },
2698 .user = OCP_USER_MPU | OCP_USER_SDMA,
2699 };
2700
2701 /* l4_core -> dss_dispc */
2702 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2703 .master = &omap3xxx_l4_core_hwmod,
2704 .slave = &omap3xxx_dss_dispc_hwmod,
2705 .clk = "dss_ick",
2706 .addr = omap2_dss_dispc_addrs,
2707 .fw = {
2708 .omap2 = {
2709 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2710 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2711 .flags = OMAP_FIREWALL_L4,
2712 }
2713 },
2714 .user = OCP_USER_MPU | OCP_USER_SDMA,
2715 };
2716
2717 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
2718 {
2719 .pa_start = 0x4804FC00,
2720 .pa_end = 0x4804FFFF,
2721 .flags = ADDR_TYPE_RT
2722 },
2723 { }
2724 };
2725
2726 /* l4_core -> dss_dsi1 */
2727 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2728 .master = &omap3xxx_l4_core_hwmod,
2729 .slave = &omap3xxx_dss_dsi1_hwmod,
2730 .clk = "dss_ick",
2731 .addr = omap3xxx_dss_dsi1_addrs,
2732 .fw = {
2733 .omap2 = {
2734 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2735 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2736 .flags = OMAP_FIREWALL_L4,
2737 }
2738 },
2739 .user = OCP_USER_MPU | OCP_USER_SDMA,
2740 };
2741
2742 /* l4_core -> dss_rfbi */
2743 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2744 .master = &omap3xxx_l4_core_hwmod,
2745 .slave = &omap3xxx_dss_rfbi_hwmod,
2746 .clk = "dss_ick",
2747 .addr = omap2_dss_rfbi_addrs,
2748 .fw = {
2749 .omap2 = {
2750 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2751 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2752 .flags = OMAP_FIREWALL_L4,
2753 }
2754 },
2755 .user = OCP_USER_MPU | OCP_USER_SDMA,
2756 };
2757
2758 /* l4_core -> dss_venc */
2759 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2760 .master = &omap3xxx_l4_core_hwmod,
2761 .slave = &omap3xxx_dss_venc_hwmod,
2762 .clk = "dss_ick",
2763 .addr = omap2_dss_venc_addrs,
2764 .fw = {
2765 .omap2 = {
2766 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2767 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2768 .flags = OMAP_FIREWALL_L4,
2769 }
2770 },
2771 .flags = OCPIF_SWSUP_IDLE,
2772 .user = OCP_USER_MPU | OCP_USER_SDMA,
2773 };
2774
2775 /* l4_wkup -> gpio1 */
2776 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2777 {
2778 .pa_start = 0x48310000,
2779 .pa_end = 0x483101ff,
2780 .flags = ADDR_TYPE_RT
2781 },
2782 { }
2783 };
2784
2785 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2786 .master = &omap3xxx_l4_wkup_hwmod,
2787 .slave = &omap3xxx_gpio1_hwmod,
2788 .addr = omap3xxx_gpio1_addrs,
2789 .user = OCP_USER_MPU | OCP_USER_SDMA,
2790 };
2791
2792 /* l4_per -> gpio2 */
2793 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2794 {
2795 .pa_start = 0x49050000,
2796 .pa_end = 0x490501ff,
2797 .flags = ADDR_TYPE_RT
2798 },
2799 { }
2800 };
2801
2802 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2803 .master = &omap3xxx_l4_per_hwmod,
2804 .slave = &omap3xxx_gpio2_hwmod,
2805 .addr = omap3xxx_gpio2_addrs,
2806 .user = OCP_USER_MPU | OCP_USER_SDMA,
2807 };
2808
2809 /* l4_per -> gpio3 */
2810 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2811 {
2812 .pa_start = 0x49052000,
2813 .pa_end = 0x490521ff,
2814 .flags = ADDR_TYPE_RT
2815 },
2816 { }
2817 };
2818
2819 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2820 .master = &omap3xxx_l4_per_hwmod,
2821 .slave = &omap3xxx_gpio3_hwmod,
2822 .addr = omap3xxx_gpio3_addrs,
2823 .user = OCP_USER_MPU | OCP_USER_SDMA,
2824 };
2825
2826 /* l4_per -> gpio4 */
2827 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
2828 {
2829 .pa_start = 0x49054000,
2830 .pa_end = 0x490541ff,
2831 .flags = ADDR_TYPE_RT
2832 },
2833 { }
2834 };
2835
2836 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
2837 .master = &omap3xxx_l4_per_hwmod,
2838 .slave = &omap3xxx_gpio4_hwmod,
2839 .addr = omap3xxx_gpio4_addrs,
2840 .user = OCP_USER_MPU | OCP_USER_SDMA,
2841 };
2842
2843 /* l4_per -> gpio5 */
2844 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
2845 {
2846 .pa_start = 0x49056000,
2847 .pa_end = 0x490561ff,
2848 .flags = ADDR_TYPE_RT
2849 },
2850 { }
2851 };
2852
2853 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
2854 .master = &omap3xxx_l4_per_hwmod,
2855 .slave = &omap3xxx_gpio5_hwmod,
2856 .addr = omap3xxx_gpio5_addrs,
2857 .user = OCP_USER_MPU | OCP_USER_SDMA,
2858 };
2859
2860 /* l4_per -> gpio6 */
2861 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
2862 {
2863 .pa_start = 0x49058000,
2864 .pa_end = 0x490581ff,
2865 .flags = ADDR_TYPE_RT
2866 },
2867 { }
2868 };
2869
2870 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
2871 .master = &omap3xxx_l4_per_hwmod,
2872 .slave = &omap3xxx_gpio6_hwmod,
2873 .addr = omap3xxx_gpio6_addrs,
2874 .user = OCP_USER_MPU | OCP_USER_SDMA,
2875 };
2876
2877 /* dma_system -> L3 */
2878 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2879 .master = &omap3xxx_dma_system_hwmod,
2880 .slave = &omap3xxx_l3_main_hwmod,
2881 .clk = "core_l3_ick",
2882 .user = OCP_USER_MPU | OCP_USER_SDMA,
2883 };
2884
2885 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2886 {
2887 .pa_start = 0x48056000,
2888 .pa_end = 0x48056fff,
2889 .flags = ADDR_TYPE_RT
2890 },
2891 { }
2892 };
2893
2894 /* l4_cfg -> dma_system */
2895 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2896 .master = &omap3xxx_l4_core_hwmod,
2897 .slave = &omap3xxx_dma_system_hwmod,
2898 .clk = "core_l4_ick",
2899 .addr = omap3xxx_dma_system_addrs,
2900 .user = OCP_USER_MPU | OCP_USER_SDMA,
2901 };
2902
2903 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2904 {
2905 .name = "mpu",
2906 .pa_start = 0x48074000,
2907 .pa_end = 0x480740ff,
2908 .flags = ADDR_TYPE_RT
2909 },
2910 { }
2911 };
2912
2913 /* l4_core -> mcbsp1 */
2914 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2915 .master = &omap3xxx_l4_core_hwmod,
2916 .slave = &omap3xxx_mcbsp1_hwmod,
2917 .clk = "mcbsp1_ick",
2918 .addr = omap3xxx_mcbsp1_addrs,
2919 .user = OCP_USER_MPU | OCP_USER_SDMA,
2920 };
2921
2922 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2923 {
2924 .name = "mpu",
2925 .pa_start = 0x49022000,
2926 .pa_end = 0x490220ff,
2927 .flags = ADDR_TYPE_RT
2928 },
2929 { }
2930 };
2931
2932 /* l4_per -> mcbsp2 */
2933 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2934 .master = &omap3xxx_l4_per_hwmod,
2935 .slave = &omap3xxx_mcbsp2_hwmod,
2936 .clk = "mcbsp2_ick",
2937 .addr = omap3xxx_mcbsp2_addrs,
2938 .user = OCP_USER_MPU | OCP_USER_SDMA,
2939 };
2940
2941 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2942 {
2943 .name = "mpu",
2944 .pa_start = 0x49024000,
2945 .pa_end = 0x490240ff,
2946 .flags = ADDR_TYPE_RT
2947 },
2948 { }
2949 };
2950
2951 /* l4_per -> mcbsp3 */
2952 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2953 .master = &omap3xxx_l4_per_hwmod,
2954 .slave = &omap3xxx_mcbsp3_hwmod,
2955 .clk = "mcbsp3_ick",
2956 .addr = omap3xxx_mcbsp3_addrs,
2957 .user = OCP_USER_MPU | OCP_USER_SDMA,
2958 };
2959
2960 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2961 {
2962 .name = "mpu",
2963 .pa_start = 0x49026000,
2964 .pa_end = 0x490260ff,
2965 .flags = ADDR_TYPE_RT
2966 },
2967 { }
2968 };
2969
2970 /* l4_per -> mcbsp4 */
2971 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2972 .master = &omap3xxx_l4_per_hwmod,
2973 .slave = &omap3xxx_mcbsp4_hwmod,
2974 .clk = "mcbsp4_ick",
2975 .addr = omap3xxx_mcbsp4_addrs,
2976 .user = OCP_USER_MPU | OCP_USER_SDMA,
2977 };
2978
2979 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2980 {
2981 .name = "mpu",
2982 .pa_start = 0x48096000,
2983 .pa_end = 0x480960ff,
2984 .flags = ADDR_TYPE_RT
2985 },
2986 { }
2987 };
2988
2989 /* l4_core -> mcbsp5 */
2990 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2991 .master = &omap3xxx_l4_core_hwmod,
2992 .slave = &omap3xxx_mcbsp5_hwmod,
2993 .clk = "mcbsp5_ick",
2994 .addr = omap3xxx_mcbsp5_addrs,
2995 .user = OCP_USER_MPU | OCP_USER_SDMA,
2996 };
2997
2998 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2999 {
3000 .name = "sidetone",
3001 .pa_start = 0x49028000,
3002 .pa_end = 0x490280ff,
3003 .flags = ADDR_TYPE_RT
3004 },
3005 { }
3006 };
3007
3008 /* l4_per -> mcbsp2_sidetone */
3009 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
3010 .master = &omap3xxx_l4_per_hwmod,
3011 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
3012 .clk = "mcbsp2_ick",
3013 .addr = omap3xxx_mcbsp2_sidetone_addrs,
3014 .user = OCP_USER_MPU,
3015 };
3016
3017 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
3018 {
3019 .name = "sidetone",
3020 .pa_start = 0x4902A000,
3021 .pa_end = 0x4902A0ff,
3022 .flags = ADDR_TYPE_RT
3023 },
3024 { }
3025 };
3026
3027 /* l4_per -> mcbsp3_sidetone */
3028 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
3029 .master = &omap3xxx_l4_per_hwmod,
3030 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
3031 .clk = "mcbsp3_ick",
3032 .addr = omap3xxx_mcbsp3_sidetone_addrs,
3033 .user = OCP_USER_MPU,
3034 };
3035
3036 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
3037 {
3038 .pa_start = 0x48094000,
3039 .pa_end = 0x480941ff,
3040 .flags = ADDR_TYPE_RT,
3041 },
3042 { }
3043 };
3044
3045 /* l4_core -> mailbox */
3046 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3047 .master = &omap3xxx_l4_core_hwmod,
3048 .slave = &omap3xxx_mailbox_hwmod,
3049 .addr = omap3xxx_mailbox_addrs,
3050 .user = OCP_USER_MPU | OCP_USER_SDMA,
3051 };
3052
3053 /* l4 core -> mcspi1 interface */
3054 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3055 .master = &omap3xxx_l4_core_hwmod,
3056 .slave = &omap34xx_mcspi1,
3057 .clk = "mcspi1_ick",
3058 .addr = omap2_mcspi1_addr_space,
3059 .user = OCP_USER_MPU | OCP_USER_SDMA,
3060 };
3061
3062 /* l4 core -> mcspi2 interface */
3063 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3064 .master = &omap3xxx_l4_core_hwmod,
3065 .slave = &omap34xx_mcspi2,
3066 .clk = "mcspi2_ick",
3067 .addr = omap2_mcspi2_addr_space,
3068 .user = OCP_USER_MPU | OCP_USER_SDMA,
3069 };
3070
3071 /* l4 core -> mcspi3 interface */
3072 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3073 .master = &omap3xxx_l4_core_hwmod,
3074 .slave = &omap34xx_mcspi3,
3075 .clk = "mcspi3_ick",
3076 .addr = omap2430_mcspi3_addr_space,
3077 .user = OCP_USER_MPU | OCP_USER_SDMA,
3078 };
3079
3080 /* l4 core -> mcspi4 interface */
3081 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3082 {
3083 .pa_start = 0x480ba000,
3084 .pa_end = 0x480ba0ff,
3085 .flags = ADDR_TYPE_RT,
3086 },
3087 { }
3088 };
3089
3090 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3091 .master = &omap3xxx_l4_core_hwmod,
3092 .slave = &omap34xx_mcspi4,
3093 .clk = "mcspi4_ick",
3094 .addr = omap34xx_mcspi4_addr_space,
3095 .user = OCP_USER_MPU | OCP_USER_SDMA,
3096 };
3097
3098 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3099 .master = &omap3xxx_usb_host_hs_hwmod,
3100 .slave = &omap3xxx_l3_main_hwmod,
3101 .clk = "core_l3_ick",
3102 .user = OCP_USER_MPU,
3103 };
3104
3105 static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3106 {
3107 .name = "uhh",
3108 .pa_start = 0x48064000,
3109 .pa_end = 0x480643ff,
3110 .flags = ADDR_TYPE_RT
3111 },
3112 {
3113 .name = "ohci",
3114 .pa_start = 0x48064400,
3115 .pa_end = 0x480647ff,
3116 },
3117 {
3118 .name = "ehci",
3119 .pa_start = 0x48064800,
3120 .pa_end = 0x48064cff,
3121 },
3122 {}
3123 };
3124
3125 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3126 .master = &omap3xxx_l4_core_hwmod,
3127 .slave = &omap3xxx_usb_host_hs_hwmod,
3128 .clk = "usbhost_ick",
3129 .addr = omap3xxx_usb_host_hs_addrs,
3130 .user = OCP_USER_MPU | OCP_USER_SDMA,
3131 };
3132
3133 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3134 {
3135 .name = "tll",
3136 .pa_start = 0x48062000,
3137 .pa_end = 0x48062fff,
3138 .flags = ADDR_TYPE_RT
3139 },
3140 {}
3141 };
3142
3143 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3144 .master = &omap3xxx_l4_core_hwmod,
3145 .slave = &omap3xxx_usb_tll_hs_hwmod,
3146 .clk = "usbtll_ick",
3147 .addr = omap3xxx_usb_tll_hs_addrs,
3148 .user = OCP_USER_MPU | OCP_USER_SDMA,
3149 };
3150
3151 /* l4_core -> hdq1w interface */
3152 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
3153 .master = &omap3xxx_l4_core_hwmod,
3154 .slave = &omap3xxx_hdq1w_hwmod,
3155 .clk = "hdq_ick",
3156 .addr = omap2_hdq1w_addr_space,
3157 .user = OCP_USER_MPU | OCP_USER_SDMA,
3158 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
3159 };
3160
3161 /* l4_wkup -> 32ksync_counter */
3162 static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
3163 {
3164 .pa_start = 0x48320000,
3165 .pa_end = 0x4832001f,
3166 .flags = ADDR_TYPE_RT
3167 },
3168 { }
3169 };
3170
3171 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
3172 .master = &omap3xxx_l4_wkup_hwmod,
3173 .slave = &omap3xxx_counter_32k_hwmod,
3174 .clk = "omap_32ksync_ick",
3175 .addr = omap3xxx_counter_32k_addrs,
3176 .user = OCP_USER_MPU | OCP_USER_SDMA,
3177 };
3178
3179 /* am35xx has Davinci MDIO & EMAC */
3180 static struct omap_hwmod_class am35xx_mdio_class = {
3181 .name = "davinci_mdio",
3182 };
3183
3184 static struct omap_hwmod am35xx_mdio_hwmod = {
3185 .name = "davinci_mdio",
3186 .class = &am35xx_mdio_class,
3187 .flags = HWMOD_NO_IDLEST,
3188 };
3189
3190 /*
3191 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3192 * but this will probably require some additional hwmod core support,
3193 * so is left as a future to-do item.
3194 */
3195 static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
3196 .master = &am35xx_mdio_hwmod,
3197 .slave = &omap3xxx_l3_main_hwmod,
3198 .clk = "emac_fck",
3199 .user = OCP_USER_MPU,
3200 };
3201
3202 static struct omap_hwmod_addr_space am35xx_mdio_addrs[] = {
3203 {
3204 .pa_start = AM35XX_IPSS_MDIO_BASE,
3205 .pa_end = AM35XX_IPSS_MDIO_BASE + SZ_4K - 1,
3206 .flags = ADDR_TYPE_RT,
3207 },
3208 { }
3209 };
3210
3211 /* l4_core -> davinci mdio */
3212 /*
3213 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3214 * but this will probably require some additional hwmod core support,
3215 * so is left as a future to-do item.
3216 */
3217 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
3218 .master = &omap3xxx_l4_core_hwmod,
3219 .slave = &am35xx_mdio_hwmod,
3220 .clk = "emac_fck",
3221 .addr = am35xx_mdio_addrs,
3222 .user = OCP_USER_MPU,
3223 };
3224
3225 static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = {
3226 { .name = "rxthresh", .irq = INT_35XX_EMAC_C0_RXTHRESH_IRQ },
3227 { .name = "rx_pulse", .irq = INT_35XX_EMAC_C0_RX_PULSE_IRQ },
3228 { .name = "tx_pulse", .irq = INT_35XX_EMAC_C0_TX_PULSE_IRQ },
3229 { .name = "misc_pulse", .irq = INT_35XX_EMAC_C0_MISC_PULSE_IRQ },
3230 { .irq = -1 }
3231 };
3232
3233 static struct omap_hwmod_class am35xx_emac_class = {
3234 .name = "davinci_emac",
3235 };
3236
3237 static struct omap_hwmod am35xx_emac_hwmod = {
3238 .name = "davinci_emac",
3239 .mpu_irqs = am35xx_emac_mpu_irqs,
3240 .class = &am35xx_emac_class,
3241 .flags = HWMOD_NO_IDLEST,
3242 };
3243
3244 /* l3_core -> davinci emac interface */
3245 /*
3246 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3247 * but this will probably require some additional hwmod core support,
3248 * so is left as a future to-do item.
3249 */
3250 static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
3251 .master = &am35xx_emac_hwmod,
3252 .slave = &omap3xxx_l3_main_hwmod,
3253 .clk = "emac_ick",
3254 .user = OCP_USER_MPU,
3255 };
3256
3257 static struct omap_hwmod_addr_space am35xx_emac_addrs[] = {
3258 {
3259 .pa_start = AM35XX_IPSS_EMAC_BASE,
3260 .pa_end = AM35XX_IPSS_EMAC_BASE + 0x30000 - 1,
3261 .flags = ADDR_TYPE_RT,
3262 },
3263 { }
3264 };
3265
3266 /* l4_core -> davinci emac */
3267 /*
3268 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3269 * but this will probably require some additional hwmod core support,
3270 * so is left as a future to-do item.
3271 */
3272 static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
3273 .master = &omap3xxx_l4_core_hwmod,
3274 .slave = &am35xx_emac_hwmod,
3275 .clk = "emac_ick",
3276 .addr = am35xx_emac_addrs,
3277 .user = OCP_USER_MPU,
3278 };
3279
3280 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3281 &omap3xxx_l3_main__l4_core,
3282 &omap3xxx_l3_main__l4_per,
3283 &omap3xxx_mpu__l3_main,
3284 &omap3xxx_l4_core__l4_wkup,
3285 &omap3xxx_l4_core__mmc3,
3286 &omap3_l4_core__uart1,
3287 &omap3_l4_core__uart2,
3288 &omap3_l4_per__uart3,
3289 &omap3_l4_core__i2c1,
3290 &omap3_l4_core__i2c2,
3291 &omap3_l4_core__i2c3,
3292 &omap3xxx_l4_wkup__l4_sec,
3293 &omap3xxx_l4_wkup__timer1,
3294 &omap3xxx_l4_per__timer2,
3295 &omap3xxx_l4_per__timer3,
3296 &omap3xxx_l4_per__timer4,
3297 &omap3xxx_l4_per__timer5,
3298 &omap3xxx_l4_per__timer6,
3299 &omap3xxx_l4_per__timer7,
3300 &omap3xxx_l4_per__timer8,
3301 &omap3xxx_l4_per__timer9,
3302 &omap3xxx_l4_core__timer10,
3303 &omap3xxx_l4_core__timer11,
3304 &omap3xxx_l4_wkup__wd_timer2,
3305 &omap3xxx_l4_wkup__gpio1,
3306 &omap3xxx_l4_per__gpio2,
3307 &omap3xxx_l4_per__gpio3,
3308 &omap3xxx_l4_per__gpio4,
3309 &omap3xxx_l4_per__gpio5,
3310 &omap3xxx_l4_per__gpio6,
3311 &omap3xxx_dma_system__l3,
3312 &omap3xxx_l4_core__dma_system,
3313 &omap3xxx_l4_core__mcbsp1,
3314 &omap3xxx_l4_per__mcbsp2,
3315 &omap3xxx_l4_per__mcbsp3,
3316 &omap3xxx_l4_per__mcbsp4,
3317 &omap3xxx_l4_core__mcbsp5,
3318 &omap3xxx_l4_per__mcbsp2_sidetone,
3319 &omap3xxx_l4_per__mcbsp3_sidetone,
3320 &omap34xx_l4_core__mcspi1,
3321 &omap34xx_l4_core__mcspi2,
3322 &omap34xx_l4_core__mcspi3,
3323 &omap34xx_l4_core__mcspi4,
3324 &omap3xxx_l4_wkup__counter_32k,
3325 NULL,
3326 };
3327
3328 /* GP-only hwmod links */
3329 static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = {
3330 &omap3xxx_l4_sec__timer12,
3331 NULL
3332 };
3333
3334 /* 3430ES1-only hwmod links */
3335 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
3336 &omap3430es1_dss__l3,
3337 &omap3430es1_l4_core__dss,
3338 NULL
3339 };
3340
3341 /* 3430ES2+-only hwmod links */
3342 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
3343 &omap3xxx_dss__l3,
3344 &omap3xxx_l4_core__dss,
3345 &omap3xxx_usbhsotg__l3,
3346 &omap3xxx_l4_core__usbhsotg,
3347 &omap3xxx_usb_host_hs__l3_main_2,
3348 &omap3xxx_l4_core__usb_host_hs,
3349 &omap3xxx_l4_core__usb_tll_hs,
3350 NULL
3351 };
3352
3353 /* <= 3430ES3-only hwmod links */
3354 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
3355 &omap3xxx_l4_core__pre_es3_mmc1,
3356 &omap3xxx_l4_core__pre_es3_mmc2,
3357 NULL
3358 };
3359
3360 /* 3430ES3+-only hwmod links */
3361 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3362 &omap3xxx_l4_core__es3plus_mmc1,
3363 &omap3xxx_l4_core__es3plus_mmc2,
3364 NULL
3365 };
3366
3367 /* 34xx-only hwmod links (all ES revisions) */
3368 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3369 &omap3xxx_l3__iva,
3370 &omap34xx_l4_core__sr1,
3371 &omap34xx_l4_core__sr2,
3372 &omap3xxx_l4_core__mailbox,
3373 &omap3xxx_l4_core__hdq1w,
3374 NULL
3375 };
3376
3377 /* 36xx-only hwmod links (all ES revisions) */
3378 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3379 &omap3xxx_l3__iva,
3380 &omap36xx_l4_per__uart4,
3381 &omap3xxx_dss__l3,
3382 &omap3xxx_l4_core__dss,
3383 &omap36xx_l4_core__sr1,
3384 &omap36xx_l4_core__sr2,
3385 &omap3xxx_usbhsotg__l3,
3386 &omap3xxx_l4_core__usbhsotg,
3387 &omap3xxx_l4_core__mailbox,
3388 &omap3xxx_usb_host_hs__l3_main_2,
3389 &omap3xxx_l4_core__usb_host_hs,
3390 &omap3xxx_l4_core__usb_tll_hs,
3391 &omap3xxx_l4_core__es3plus_mmc1,
3392 &omap3xxx_l4_core__es3plus_mmc2,
3393 &omap3xxx_l4_core__hdq1w,
3394 NULL
3395 };
3396
3397 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3398 &omap3xxx_dss__l3,
3399 &omap3xxx_l4_core__dss,
3400 &am35xx_usbhsotg__l3,
3401 &am35xx_l4_core__usbhsotg,
3402 &am35xx_l4_core__uart4,
3403 &omap3xxx_usb_host_hs__l3_main_2,
3404 &omap3xxx_l4_core__usb_host_hs,
3405 &omap3xxx_l4_core__usb_tll_hs,
3406 &omap3xxx_l4_core__es3plus_mmc1,
3407 &omap3xxx_l4_core__es3plus_mmc2,
3408 &am35xx_mdio__l3,
3409 &am35xx_l4_core__mdio,
3410 &am35xx_emac__l3,
3411 &am35xx_l4_core__emac,
3412 NULL
3413 };
3414
3415 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3416 &omap3xxx_l4_core__dss_dispc,
3417 &omap3xxx_l4_core__dss_dsi1,
3418 &omap3xxx_l4_core__dss_rfbi,
3419 &omap3xxx_l4_core__dss_venc,
3420 NULL
3421 };
3422
3423 int __init omap3xxx_hwmod_init(void)
3424 {
3425 int r;
3426 struct omap_hwmod_ocp_if **h = NULL;
3427 unsigned int rev;
3428
3429 omap_hwmod_init();
3430
3431 /* Register hwmod links common to all OMAP3 */
3432 r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
3433 if (r < 0)
3434 return r;
3435
3436 /* Register GP-only hwmod links. */
3437 if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
3438 r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs);
3439 if (r < 0)
3440 return r;
3441 }
3442
3443 rev = omap_rev();
3444
3445 /*
3446 * Register hwmod links common to individual OMAP3 families, all
3447 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3448 * All possible revisions should be included in this conditional.
3449 */
3450 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3451 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3452 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3453 h = omap34xx_hwmod_ocp_ifs;
3454 } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
3455 h = am35xx_hwmod_ocp_ifs;
3456 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3457 rev == OMAP3630_REV_ES1_2) {
3458 h = omap36xx_hwmod_ocp_ifs;
3459 } else {
3460 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3461 return -EINVAL;
3462 };
3463
3464 r = omap_hwmod_register_links(h);
3465 if (r < 0)
3466 return r;
3467
3468 /*
3469 * Register hwmod links specific to certain ES levels of a
3470 * particular family of silicon (e.g., 34xx ES1.0)
3471 */
3472 h = NULL;
3473 if (rev == OMAP3430_REV_ES1_0) {
3474 h = omap3430es1_hwmod_ocp_ifs;
3475 } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3476 rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3477 rev == OMAP3430_REV_ES3_1_2) {
3478 h = omap3430es2plus_hwmod_ocp_ifs;
3479 };
3480
3481 if (h) {
3482 r = omap_hwmod_register_links(h);
3483 if (r < 0)
3484 return r;
3485 }
3486
3487 h = NULL;
3488 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3489 rev == OMAP3430_REV_ES2_1) {
3490 h = omap3430_pre_es3_hwmod_ocp_ifs;
3491 } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3492 rev == OMAP3430_REV_ES3_1_2) {
3493 h = omap3430_es3plus_hwmod_ocp_ifs;
3494 };
3495
3496 if (h)
3497 r = omap_hwmod_register_links(h);
3498 if (r < 0)
3499 return r;
3500
3501 /*
3502 * DSS code presumes that dss_core hwmod is handled first,
3503 * _before_ any other DSS related hwmods so register common
3504 * DSS hwmod links last to ensure that dss_core is already
3505 * registered. Otherwise some change things may happen, for
3506 * ex. if dispc is handled before dss_core and DSS is enabled
3507 * in bootloader DISPC will be reset with outputs enabled
3508 * which sometimes leads to unrecoverable L3 error. XXX The
3509 * long-term fix to this is to ensure hwmods are set up in
3510 * dependency order in the hwmod core code.
3511 */
3512 r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
3513
3514 return r;
3515 }
Linux kernel - Deliverables
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