arch/arm/mach-omap2/omap_hwmod_43xx_data.c

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated
   3  *
   4  * Hwmod present only in AM43x and those that differ other than register
   5  * offsets as compared to AM335x.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/platform_data/gpio-omap.h>
  18 #include <linux/platform_data/spi-omap2-mcspi.h>
  19 #include "omap_hwmod.h"
  20 #include "omap_hwmod_33xx_43xx_common_data.h"
  21 #include "prcm43xx.h"
  22 #include "omap_hwmod_common_data.h"
  23
  24
  25 /* IP blocks */
  26 static struct omap_hwmod am43xx_l4_hs_hwmod = {
  27         .name           = "l4_hs",
  28         .class          = &am33xx_l4_hwmod_class,
  29         .clkdm_name     = "l3_clkdm",
  30         .flags          = HWMOD_INIT_NO_IDLE,
  31         .main_clk       = "l4hs_gclk",
  32         .prcm           = {
  33                 .omap4  = {
  34                         .clkctrl_offs   = AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET,
  35                         .modulemode     = MODULEMODE_SWCTRL,
  36                 },
  37         },
  38 };
  39
  40 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
  41         { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
  42 };
  43
  44 static struct omap_hwmod am43xx_wkup_m3_hwmod = {
  45         .name           = "wkup_m3",
  46         .class          = &am33xx_wkup_m3_hwmod_class,
  47         .clkdm_name     = "l4_wkup_aon_clkdm",
  48         /* Keep hardreset asserted */
  49         .flags          = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
  50         .main_clk       = "sys_clkin_ck",
  51         .prcm           = {
  52                 .omap4  = {
  53                         .clkctrl_offs   = AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
  54                         .rstctrl_offs   = AM43XX_RM_WKUP_RSTCTRL_OFFSET,
  55                         .rstst_offs     = AM43XX_RM_WKUP_RSTST_OFFSET,
  56                         .modulemode     = MODULEMODE_SWCTRL,
  57                 },
  58         },
  59         .rst_lines      = am33xx_wkup_m3_resets,
  60         .rst_lines_cnt  = ARRAY_SIZE(am33xx_wkup_m3_resets),
  61 };
  62
  63 static struct omap_hwmod am43xx_control_hwmod = {
  64         .name           = "control",
  65         .class          = &am33xx_control_hwmod_class,
  66         .clkdm_name     = "l4_wkup_clkdm",
  67         .flags          = HWMOD_INIT_NO_IDLE,
  68         .main_clk       = "sys_clkin_ck",
  69         .prcm           = {
  70                 .omap4  = {
  71                         .clkctrl_offs   = AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
  72                         .modulemode     = MODULEMODE_SWCTRL,
  73                 },
  74         },
  75 };
  76
  77 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
  78         { .role = "dbclk", .clk = "gpio0_dbclk" },
  79 };
  80
  81 static struct omap_hwmod am43xx_gpio0_hwmod = {
  82         .name           = "gpio1",
  83         .class          = &am33xx_gpio_hwmod_class,
  84         .clkdm_name     = "l4_wkup_clkdm",
  85         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
  86         .main_clk       = "sys_clkin_ck",
  87         .prcm           = {
  88                 .omap4  = {
  89                         .clkctrl_offs   = AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
  90                         .modulemode     = MODULEMODE_SWCTRL,
  91                 },
  92         },
  93         .opt_clks       = gpio0_opt_clks,
  94         .opt_clks_cnt   = ARRAY_SIZE(gpio0_opt_clks),
  95         .dev_attr       = &gpio_dev_attr,
  96 };
  97
  98 static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = {
  99         .rev_offs       = 0x0,
 100         .sysc_offs      = 0x4,
 101         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 102         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 103         .sysc_fields    = &omap_hwmod_sysc_type1,
 104 };
 105
 106 static struct omap_hwmod_class am43xx_synctimer_hwmod_class = {
 107         .name   = "synctimer",
 108         .sysc   = &am43xx_synctimer_sysc,
 109 };
 110
 111 static struct omap_hwmod am43xx_synctimer_hwmod = {
 112         .name           = "counter_32k",
 113         .class          = &am43xx_synctimer_hwmod_class,
 114         .clkdm_name     = "l4_wkup_aon_clkdm",
 115         .flags          = HWMOD_SWSUP_SIDLE,
 116         .main_clk       = "synctimer_32kclk",
 117         .prcm = {
 118                 .omap4 = {
 119                         .clkctrl_offs = AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 120                         .modulemode   = MODULEMODE_SWCTRL,
 121                 },
 122         },
 123 };
 124
 125 static struct omap_hwmod am43xx_timer8_hwmod = {
 126         .name           = "timer8",
 127         .class          = &am33xx_timer_hwmod_class,
 128         .clkdm_name     = "l4ls_clkdm",
 129         .main_clk       = "timer8_fck",
 130         .prcm           = {
 131                 .omap4  = {
 132                         .clkctrl_offs   = AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET,
 133                         .modulemode     = MODULEMODE_SWCTRL,
 134                 },
 135         },
 136 };
 137
 138 static struct omap_hwmod am43xx_timer9_hwmod = {
 139         .name           = "timer9",
 140         .class          = &am33xx_timer_hwmod_class,
 141         .clkdm_name     = "l4ls_clkdm",
 142         .main_clk       = "timer9_fck",
 143         .prcm           = {
 144                 .omap4  = {
 145                         .clkctrl_offs   = AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET,
 146                         .modulemode     = MODULEMODE_SWCTRL,
 147                 },
 148         },
 149 };
 150
 151 static struct omap_hwmod am43xx_timer10_hwmod = {
 152         .name           = "timer10",
 153         .class          = &am33xx_timer_hwmod_class,
 154         .clkdm_name     = "l4ls_clkdm",
 155         .main_clk       = "timer10_fck",
 156         .prcm           = {
 157                 .omap4  = {
 158                         .clkctrl_offs   = AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET,
 159                         .modulemode     = MODULEMODE_SWCTRL,
 160                 },
 161         },
 162 };
 163
 164 static struct omap_hwmod am43xx_timer11_hwmod = {
 165         .name           = "timer11",
 166         .class          = &am33xx_timer_hwmod_class,
 167         .clkdm_name     = "l4ls_clkdm",
 168         .main_clk       = "timer11_fck",
 169         .prcm           = {
 170                 .omap4  = {
 171                         .clkctrl_offs   = AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET,
 172                         .modulemode     = MODULEMODE_SWCTRL,
 173                 },
 174         },
 175 };
 176
 177 static struct omap_hwmod am43xx_epwmss3_hwmod = {
 178         .name           = "epwmss3",
 179         .class          = &am33xx_epwmss_hwmod_class,
 180         .clkdm_name     = "l4ls_clkdm",
 181         .main_clk       = "l4ls_gclk",
 182         .prcm           = {
 183                 .omap4  = {
 184                         .clkctrl_offs = AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET,
 185                         .modulemode   = MODULEMODE_SWCTRL,
 186                 },
 187         },
 188 };
 189
 190 static struct omap_hwmod am43xx_ehrpwm3_hwmod = {
 191         .name           = "ehrpwm3",
 192         .class          = &am33xx_ehrpwm_hwmod_class,
 193         .clkdm_name     = "l4ls_clkdm",
 194         .main_clk       = "l4ls_gclk",
 195 };
 196
 197 static struct omap_hwmod am43xx_epwmss4_hwmod = {
 198         .name           = "epwmss4",
 199         .class          = &am33xx_epwmss_hwmod_class,
 200         .clkdm_name     = "l4ls_clkdm",
 201         .main_clk       = "l4ls_gclk",
 202         .prcm           = {
 203                 .omap4  = {
 204                         .clkctrl_offs = AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET,
 205                         .modulemode   = MODULEMODE_SWCTRL,
 206                 },
 207         },
 208 };
 209
 210 static struct omap_hwmod am43xx_ehrpwm4_hwmod = {
 211         .name           = "ehrpwm4",
 212         .class          = &am33xx_ehrpwm_hwmod_class,
 213         .clkdm_name     = "l4ls_clkdm",
 214         .main_clk       = "l4ls_gclk",
 215 };
 216
 217 static struct omap_hwmod am43xx_epwmss5_hwmod = {
 218         .name           = "epwmss5",
 219         .class          = &am33xx_epwmss_hwmod_class,
 220         .clkdm_name     = "l4ls_clkdm",
 221         .main_clk       = "l4ls_gclk",
 222         .prcm           = {
 223                 .omap4  = {
 224                         .clkctrl_offs = AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET,
 225                         .modulemode   = MODULEMODE_SWCTRL,
 226                 },
 227         },
 228 };
 229
 230 static struct omap_hwmod am43xx_ehrpwm5_hwmod = {
 231         .name           = "ehrpwm5",
 232         .class          = &am33xx_ehrpwm_hwmod_class,
 233         .clkdm_name     = "l4ls_clkdm",
 234         .main_clk       = "l4ls_gclk",
 235 };
 236
 237 static struct omap_hwmod am43xx_spi2_hwmod = {
 238         .name           = "spi2",
 239         .class          = &am33xx_spi_hwmod_class,
 240         .clkdm_name     = "l4ls_clkdm",
 241         .main_clk       = "dpll_per_m2_div4_ck",
 242         .prcm           = {
 243                 .omap4  = {
 244                         .clkctrl_offs = AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET,
 245                         .modulemode   = MODULEMODE_SWCTRL,
 246                 },
 247         },
 248         .dev_attr       = &mcspi_attrib,
 249 };
 250
 251 static struct omap_hwmod am43xx_spi3_hwmod = {
 252         .name           = "spi3",
 253         .class          = &am33xx_spi_hwmod_class,
 254         .clkdm_name     = "l4ls_clkdm",
 255         .main_clk       = "dpll_per_m2_div4_ck",
 256         .prcm           = {
 257                 .omap4  = {
 258                         .clkctrl_offs = AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET,
 259                         .modulemode   = MODULEMODE_SWCTRL,
 260                 },
 261         },
 262         .dev_attr       = &mcspi_attrib,
 263 };
 264
 265 static struct omap_hwmod am43xx_spi4_hwmod = {
 266         .name           = "spi4",
 267         .class          = &am33xx_spi_hwmod_class,
 268         .clkdm_name     = "l4ls_clkdm",
 269         .main_clk       = "dpll_per_m2_div4_ck",
 270         .prcm           = {
 271                 .omap4  = {
 272                         .clkctrl_offs = AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET,
 273                         .modulemode   = MODULEMODE_SWCTRL,
 274                 },
 275         },
 276         .dev_attr       = &mcspi_attrib,
 277 };
 278
 279 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 280         { .role = "dbclk", .clk = "gpio4_dbclk" },
 281 };
 282
 283 static struct omap_hwmod am43xx_gpio4_hwmod = {
 284         .name           = "gpio5",
 285         .class          = &am33xx_gpio_hwmod_class,
 286         .clkdm_name     = "l4ls_clkdm",
 287         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 288         .main_clk       = "l4ls_gclk",
 289         .prcm           = {
 290                 .omap4  = {
 291                         .clkctrl_offs = AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET,
 292                         .modulemode   = MODULEMODE_SWCTRL,
 293                 },
 294         },
 295         .opt_clks       = gpio4_opt_clks,
 296         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 297         .dev_attr       = &gpio_dev_attr,
 298 };
 299
 300 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 301         { .role = "dbclk", .clk = "gpio5_dbclk" },
 302 };
 303
 304 static struct omap_hwmod am43xx_gpio5_hwmod = {
 305         .name           = "gpio6",
 306         .class          = &am33xx_gpio_hwmod_class,
 307         .clkdm_name     = "l4ls_clkdm",
 308         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 309         .main_clk       = "l4ls_gclk",
 310         .prcm           = {
 311                 .omap4  = {
 312                         .clkctrl_offs = AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET,
 313                         .modulemode   = MODULEMODE_SWCTRL,
 314                 },
 315         },
 316         .opt_clks       = gpio5_opt_clks,
 317         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
 318         .dev_attr       = &gpio_dev_attr,
 319 };
 320
 321 static struct omap_hwmod_class am43xx_ocp2scp_hwmod_class = {
 322         .name   = "ocp2scp",
 323 };
 324
 325 static struct omap_hwmod am43xx_ocp2scp0_hwmod = {
 326         .name           = "ocp2scp0",
 327         .class          = &am43xx_ocp2scp_hwmod_class,
 328         .clkdm_name     = "l4ls_clkdm",
 329         .main_clk       = "l4ls_gclk",
 330         .prcm = {
 331                 .omap4 = {
 332                         .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET,
 333                         .modulemode   = MODULEMODE_SWCTRL,
 334                 },
 335         },
 336 };
 337
 338 static struct omap_hwmod am43xx_ocp2scp1_hwmod = {
 339         .name           = "ocp2scp1",
 340         .class          = &am43xx_ocp2scp_hwmod_class,
 341         .clkdm_name     = "l4ls_clkdm",
 342         .main_clk       = "l4ls_gclk",
 343         .prcm = {
 344                 .omap4 = {
 345                         .clkctrl_offs   = AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET,
 346                         .modulemode     = MODULEMODE_SWCTRL,
 347                 },
 348         },
 349 };
 350
 351 static struct omap_hwmod_class_sysconfig am43xx_usb_otg_ss_sysc = {
 352         .rev_offs       = 0x0000,
 353         .sysc_offs      = 0x0010,
 354         .sysc_flags     = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
 355                                 SYSC_HAS_SIDLEMODE),
 356         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 357                                 SIDLE_SMART_WKUP | MSTANDBY_FORCE |
 358                                 MSTANDBY_NO | MSTANDBY_SMART |
 359                                 MSTANDBY_SMART_WKUP),
 360         .sysc_fields    = &omap_hwmod_sysc_type2,
 361 };
 362
 363 static struct omap_hwmod_class am43xx_usb_otg_ss_hwmod_class = {
 364         .name   = "usb_otg_ss",
 365         .sysc   = &am43xx_usb_otg_ss_sysc,
 366 };
 367
 368 static struct omap_hwmod am43xx_usb_otg_ss0_hwmod = {
 369         .name           = "usb_otg_ss0",
 370         .class          = &am43xx_usb_otg_ss_hwmod_class,
 371         .clkdm_name     = "l3s_clkdm",
 372         .main_clk       = "l3s_gclk",
 373         .prcm = {
 374                 .omap4 = {
 375                         .clkctrl_offs   = AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET,
 376                         .modulemode     = MODULEMODE_SWCTRL,
 377                 },
 378         },
 379 };
 380
 381 static struct omap_hwmod am43xx_usb_otg_ss1_hwmod = {
 382         .name           = "usb_otg_ss1",
 383         .class          = &am43xx_usb_otg_ss_hwmod_class,
 384         .clkdm_name     = "l3s_clkdm",
 385         .main_clk       = "l3s_gclk",
 386         .prcm = {
 387                 .omap4 = {
 388                         .clkctrl_offs   = AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET,
 389                         .modulemode     = MODULEMODE_SWCTRL,
 390                 },
 391         },
 392 };
 393
 394 static struct omap_hwmod_class_sysconfig am43xx_qspi_sysc = {
 395         .sysc_offs      = 0x0010,
 396         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 397         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 398                                 SIDLE_SMART_WKUP),
 399         .sysc_fields    = &omap_hwmod_sysc_type2,
 400 };
 401
 402 static struct omap_hwmod_class am43xx_qspi_hwmod_class = {
 403         .name   = "qspi",
 404         .sysc   = &am43xx_qspi_sysc,
 405 };
 406
 407 static struct omap_hwmod am43xx_qspi_hwmod = {
 408         .name           = "qspi",
 409         .class          = &am43xx_qspi_hwmod_class,
 410         .clkdm_name     = "l3s_clkdm",
 411         .main_clk       = "l3s_gclk",
 412         .prcm = {
 413                 .omap4 = {
 414                         .clkctrl_offs = AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET,
 415                         .modulemode   = MODULEMODE_SWCTRL,
 416                 },
 417         },
 418 };
 419
 420 /*
 421  * 'adc/tsc' class
 422  * TouchScreen Controller (Analog-To-Digital Converter)
 423  */
 424 static struct omap_hwmod_class_sysconfig am43xx_adc_tsc_sysc = {
 425         .rev_offs       = 0x00,
 426         .sysc_offs      = 0x10,
 427         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 428         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 429                           SIDLE_SMART_WKUP),
 430         .sysc_fields    = &omap_hwmod_sysc_type2,
 431 };
 432
 433 static struct omap_hwmod_class am43xx_adc_tsc_hwmod_class = {
 434         .name           = "adc_tsc",
 435         .sysc           = &am43xx_adc_tsc_sysc,
 436 };
 437
 438 static struct omap_hwmod am43xx_adc_tsc_hwmod = {
 439         .name           = "adc_tsc",
 440         .class          = &am43xx_adc_tsc_hwmod_class,
 441         .clkdm_name     = "l3s_tsc_clkdm",
 442         .main_clk       = "adc_tsc_fck",
 443         .prcm           = {
 444                 .omap4  = {
 445                         .clkctrl_offs   = AM43XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
 446                         .modulemode     = MODULEMODE_SWCTRL,
 447                 },
 448         },
 449 };
 450
 451 /* dss */
 452
 453 static struct omap_hwmod am43xx_dss_core_hwmod = {
 454         .name           = "dss_core",
 455         .class          = &omap2_dss_hwmod_class,
 456         .clkdm_name     = "dss_clkdm",
 457         .main_clk       = "disp_clk",
 458         .prcm = {
 459                 .omap4 = {
 460                         .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
 461                         .modulemode   = MODULEMODE_SWCTRL,
 462                 },
 463         },
 464 };
 465
 466 /* dispc */
 467
 468 struct omap_dss_dispc_dev_attr am43xx_dss_dispc_dev_attr = {
 469         .manager_count          = 1,
 470         .has_framedonetv_irq    = 0
 471 };
 472
 473 static struct omap_hwmod_class_sysconfig am43xx_dispc_sysc = {
 474         .rev_offs       = 0x0000,
 475         .sysc_offs      = 0x0010,
 476         .syss_offs      = 0x0014,
 477         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
 478                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 479                            SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_MIDLEMODE),
 480         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 481                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 482         .sysc_fields    = &omap_hwmod_sysc_type1,
 483 };
 484
 485 static struct omap_hwmod_class am43xx_dispc_hwmod_class = {
 486         .name   = "dispc",
 487         .sysc   = &am43xx_dispc_sysc,
 488 };
 489
 490 static struct omap_hwmod am43xx_dss_dispc_hwmod = {
 491         .name           = "dss_dispc",
 492         .class          = &am43xx_dispc_hwmod_class,
 493         .clkdm_name     = "dss_clkdm",
 494         .main_clk       = "disp_clk",
 495         .prcm = {
 496                 .omap4 = {
 497                         .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
 498                 },
 499         },
 500         .dev_attr       = &am43xx_dss_dispc_dev_attr,
 501 };
 502
 503 /* rfbi */
 504
 505 static struct omap_hwmod am43xx_dss_rfbi_hwmod = {
 506         .name           = "dss_rfbi",
 507         .class          = &omap2_rfbi_hwmod_class,
 508         .clkdm_name     = "dss_clkdm",
 509         .main_clk       = "disp_clk",
 510         .prcm = {
 511                 .omap4 = {
 512                         .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
 513                 },
 514         },
 515 };
 516
 517 /* Interfaces */
 518 static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {
 519         .master         = &am33xx_l3_main_hwmod,
 520         .slave          = &am43xx_l4_hs_hwmod,
 521         .clk            = "l3s_gclk",
 522         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 523 };
 524
 525 static struct omap_hwmod_ocp_if am43xx_wkup_m3__l4_wkup = {
 526         .master         = &am43xx_wkup_m3_hwmod,
 527         .slave          = &am33xx_l4_wkup_hwmod,
 528         .clk            = "sys_clkin_ck",
 529         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 530 };
 531
 532 static struct omap_hwmod_ocp_if am43xx_l4_wkup__wkup_m3 = {
 533         .master         = &am33xx_l4_wkup_hwmod,
 534         .slave          = &am43xx_wkup_m3_hwmod,
 535         .clk            = "sys_clkin_ck",
 536         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 537 };
 538
 539 static struct omap_hwmod_ocp_if am43xx_l3_main__pruss = {
 540         .master         = &am33xx_l3_main_hwmod,
 541         .slave          = &am33xx_pruss_hwmod,
 542         .clk            = "dpll_core_m4_ck",
 543         .user           = OCP_USER_MPU,
 544 };
 545
 546 static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex0 = {
 547         .master         = &am33xx_l4_wkup_hwmod,
 548         .slave          = &am33xx_smartreflex0_hwmod,
 549         .clk            = "sys_clkin_ck",
 550         .user           = OCP_USER_MPU,
 551 };
 552
 553 static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex1 = {
 554         .master         = &am33xx_l4_wkup_hwmod,
 555         .slave          = &am33xx_smartreflex1_hwmod,
 556         .clk            = "sys_clkin_ck",
 557         .user           = OCP_USER_MPU,
 558 };
 559
 560 static struct omap_hwmod_ocp_if am43xx_l4_wkup__control = {
 561         .master         = &am33xx_l4_wkup_hwmod,
 562         .slave          = &am43xx_control_hwmod,
 563         .clk            = "sys_clkin_ck",
 564         .user           = OCP_USER_MPU,
 565 };
 566
 567 static struct omap_hwmod_ocp_if am43xx_l4_wkup__i2c1 = {
 568         .master         = &am33xx_l4_wkup_hwmod,
 569         .slave          = &am33xx_i2c1_hwmod,
 570         .clk            = "sys_clkin_ck",
 571         .user           = OCP_USER_MPU,
 572 };
 573
 574 static struct omap_hwmod_ocp_if am43xx_l4_wkup__gpio0 = {
 575         .master         = &am33xx_l4_wkup_hwmod,
 576         .slave          = &am43xx_gpio0_hwmod,
 577         .clk            = "sys_clkin_ck",
 578         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 579 };
 580
 581 static struct omap_hwmod_ocp_if am43xx_l4_wkup__adc_tsc = {
 582         .master         = &am33xx_l4_wkup_hwmod,
 583         .slave          = &am43xx_adc_tsc_hwmod,
 584         .clk            = "dpll_core_m4_div2_ck",
 585         .user           = OCP_USER_MPU,
 586 };
 587
 588 static struct omap_hwmod_ocp_if am43xx_l4_hs__cpgmac0 = {
 589         .master         = &am43xx_l4_hs_hwmod,
 590         .slave          = &am33xx_cpgmac0_hwmod,
 591         .clk            = "cpsw_125mhz_gclk",
 592         .user           = OCP_USER_MPU,
 593 };
 594
 595 static struct omap_hwmod_ocp_if am43xx_l4_wkup__timer1 = {
 596         .master         = &am33xx_l4_wkup_hwmod,
 597         .slave          = &am33xx_timer1_hwmod,
 598         .clk            = "sys_clkin_ck",
 599         .user           = OCP_USER_MPU,
 600 };
 601
 602 static struct omap_hwmod_ocp_if am43xx_l4_wkup__uart1 = {
 603         .master         = &am33xx_l4_wkup_hwmod,
 604         .slave          = &am33xx_uart1_hwmod,
 605         .clk            = "sys_clkin_ck",
 606         .user           = OCP_USER_MPU,
 607 };
 608
 609 static struct omap_hwmod_ocp_if am43xx_l4_wkup__wd_timer1 = {
 610         .master         = &am33xx_l4_wkup_hwmod,
 611         .slave          = &am33xx_wd_timer1_hwmod,
 612         .clk            = "sys_clkin_ck",
 613         .user           = OCP_USER_MPU,
 614 };
 615
 616 static struct omap_hwmod_ocp_if am33xx_l4_wkup__synctimer = {
 617         .master         = &am33xx_l4_wkup_hwmod,
 618         .slave          = &am43xx_synctimer_hwmod,
 619         .clk            = "sys_clkin_ck",
 620         .user           = OCP_USER_MPU,
 621 };
 622
 623 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer8 = {
 624         .master         = &am33xx_l4_ls_hwmod,
 625         .slave          = &am43xx_timer8_hwmod,
 626         .clk            = "l4ls_gclk",
 627         .user           = OCP_USER_MPU,
 628 };
 629
 630 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer9 = {
 631         .master         = &am33xx_l4_ls_hwmod,
 632         .slave          = &am43xx_timer9_hwmod,
 633         .clk            = "l4ls_gclk",
 634         .user           = OCP_USER_MPU,
 635 };
 636
 637 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer10 = {
 638         .master         = &am33xx_l4_ls_hwmod,
 639         .slave          = &am43xx_timer10_hwmod,
 640         .clk            = "l4ls_gclk",
 641         .user           = OCP_USER_MPU,
 642 };
 643
 644 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer11 = {
 645         .master         = &am33xx_l4_ls_hwmod,
 646         .slave          = &am43xx_timer11_hwmod,
 647         .clk            = "l4ls_gclk",
 648         .user           = OCP_USER_MPU,
 649 };
 650
 651 static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss3 = {
 652         .master         = &am33xx_l4_ls_hwmod,
 653         .slave          = &am43xx_epwmss3_hwmod,
 654         .clk            = "l4ls_gclk",
 655         .user           = OCP_USER_MPU,
 656 };
 657
 658 static struct omap_hwmod_ocp_if am43xx_epwmss3__ehrpwm3 = {
 659         .master         = &am43xx_epwmss3_hwmod,
 660         .slave          = &am43xx_ehrpwm3_hwmod,
 661         .clk            = "l4ls_gclk",
 662         .user           = OCP_USER_MPU,
 663 };
 664
 665 static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss4 = {
 666         .master         = &am33xx_l4_ls_hwmod,
 667         .slave          = &am43xx_epwmss4_hwmod,
 668         .clk            = "l4ls_gclk",
 669         .user           = OCP_USER_MPU,
 670 };
 671
 672 static struct omap_hwmod_ocp_if am43xx_epwmss4__ehrpwm4 = {
 673         .master         = &am43xx_epwmss4_hwmod,
 674         .slave          = &am43xx_ehrpwm4_hwmod,
 675         .clk            = "l4ls_gclk",
 676         .user           = OCP_USER_MPU,
 677 };
 678
 679 static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss5 = {
 680         .master         = &am33xx_l4_ls_hwmod,
 681         .slave          = &am43xx_epwmss5_hwmod,
 682         .clk            = "l4ls_gclk",
 683         .user           = OCP_USER_MPU,
 684 };
 685
 686 static struct omap_hwmod_ocp_if am43xx_epwmss5__ehrpwm5 = {
 687         .master         = &am43xx_epwmss5_hwmod,
 688         .slave          = &am43xx_ehrpwm5_hwmod,
 689         .clk            = "l4ls_gclk",
 690         .user           = OCP_USER_MPU,
 691 };
 692
 693 static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi2 = {
 694         .master         = &am33xx_l4_ls_hwmod,
 695         .slave          = &am43xx_spi2_hwmod,
 696         .clk            = "l4ls_gclk",
 697         .user           = OCP_USER_MPU,
 698 };
 699
 700 static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi3 = {
 701         .master         = &am33xx_l4_ls_hwmod,
 702         .slave          = &am43xx_spi3_hwmod,
 703         .clk            = "l4ls_gclk",
 704         .user           = OCP_USER_MPU,
 705 };
 706
 707 static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi4 = {
 708         .master         = &am33xx_l4_ls_hwmod,
 709         .slave          = &am43xx_spi4_hwmod,
 710         .clk            = "l4ls_gclk",
 711         .user           = OCP_USER_MPU,
 712 };
 713
 714 static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio4 = {
 715         .master         = &am33xx_l4_ls_hwmod,
 716         .slave          = &am43xx_gpio4_hwmod,
 717         .clk            = "l4ls_gclk",
 718         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 719 };
 720
 721 static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio5 = {
 722         .master         = &am33xx_l4_ls_hwmod,
 723         .slave          = &am43xx_gpio5_hwmod,
 724         .clk            = "l4ls_gclk",
 725         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 726 };
 727
 728 static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp0 = {
 729         .master         = &am33xx_l4_ls_hwmod,
 730         .slave          = &am43xx_ocp2scp0_hwmod,
 731         .clk            = "l4ls_gclk",
 732         .user           = OCP_USER_MPU,
 733 };
 734
 735 static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp1 = {
 736         .master         = &am33xx_l4_ls_hwmod,
 737         .slave          = &am43xx_ocp2scp1_hwmod,
 738         .clk            = "l4ls_gclk",
 739         .user           = OCP_USER_MPU,
 740 };
 741
 742 static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss0 = {
 743         .master         = &am33xx_l3_s_hwmod,
 744         .slave          = &am43xx_usb_otg_ss0_hwmod,
 745         .clk            = "l3s_gclk",
 746         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 747 };
 748
 749 static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss1 = {
 750         .master         = &am33xx_l3_s_hwmod,
 751         .slave          = &am43xx_usb_otg_ss1_hwmod,
 752         .clk            = "l3s_gclk",
 753         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 754 };
 755
 756 static struct omap_hwmod_ocp_if am43xx_l3_s__qspi = {
 757         .master         = &am33xx_l3_s_hwmod,
 758         .slave          = &am43xx_qspi_hwmod,
 759         .clk            = "l3s_gclk",
 760         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 761 };
 762
 763 static struct omap_hwmod_ocp_if am43xx_dss__l3_main = {
 764         .master         = &am43xx_dss_core_hwmod,
 765         .slave          = &am33xx_l3_main_hwmod,
 766         .clk            = "l3_gclk",
 767         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 768 };
 769
 770 static struct omap_hwmod_ocp_if am43xx_l4_ls__dss = {
 771         .master         = &am33xx_l4_ls_hwmod,
 772         .slave          = &am43xx_dss_core_hwmod,
 773         .clk            = "l4ls_gclk",
 774         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 775 };
 776
 777 static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_dispc = {
 778         .master         = &am33xx_l4_ls_hwmod,
 779         .slave          = &am43xx_dss_dispc_hwmod,
 780         .clk            = "l4ls_gclk",
 781         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 782 };
 783
 784 static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_rfbi = {
 785         .master         = &am33xx_l4_ls_hwmod,
 786         .slave          = &am43xx_dss_rfbi_hwmod,
 787         .clk            = "l4ls_gclk",
 788         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 789 };
 790
 791 static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
 792         &am33xx_l4_wkup__synctimer,
 793         &am43xx_l4_ls__timer8,
 794         &am43xx_l4_ls__timer9,
 795         &am43xx_l4_ls__timer10,
 796         &am43xx_l4_ls__timer11,
 797         &am43xx_l4_ls__epwmss3,
 798         &am43xx_epwmss3__ehrpwm3,
 799         &am43xx_l4_ls__epwmss4,
 800         &am43xx_epwmss4__ehrpwm4,
 801         &am43xx_l4_ls__epwmss5,
 802         &am43xx_epwmss5__ehrpwm5,
 803         &am43xx_l4_ls__mcspi2,
 804         &am43xx_l4_ls__mcspi3,
 805         &am43xx_l4_ls__mcspi4,
 806         &am43xx_l4_ls__gpio4,
 807         &am43xx_l4_ls__gpio5,
 808         &am43xx_l3_main__pruss,
 809         &am33xx_mpu__l3_main,
 810         &am33xx_mpu__prcm,
 811         &am33xx_l3_s__l4_ls,
 812         &am33xx_l3_s__l4_wkup,
 813         &am43xx_l3_main__l4_hs,
 814         &am33xx_l3_main__l3_s,
 815         &am33xx_l3_main__l3_instr,
 816         &am33xx_l3_main__gfx,
 817         &am33xx_l3_s__l3_main,
 818         &am33xx_pruss__l3_main,
 819         &am43xx_wkup_m3__l4_wkup,
 820         &am33xx_gfx__l3_main,
 821         &am43xx_l4_wkup__wkup_m3,
 822         &am43xx_l4_wkup__control,
 823         &am43xx_l4_wkup__smartreflex0,
 824         &am43xx_l4_wkup__smartreflex1,
 825         &am43xx_l4_wkup__uart1,
 826         &am43xx_l4_wkup__timer1,
 827         &am43xx_l4_wkup__i2c1,
 828         &am43xx_l4_wkup__gpio0,
 829         &am43xx_l4_wkup__wd_timer1,
 830         &am43xx_l4_wkup__adc_tsc,
 831         &am43xx_l3_s__qspi,
 832         &am33xx_l4_per__dcan0,
 833         &am33xx_l4_per__dcan1,
 834         &am33xx_l4_per__gpio1,
 835         &am33xx_l4_per__gpio2,
 836         &am33xx_l4_per__gpio3,
 837         &am33xx_l4_per__i2c2,
 838         &am33xx_l4_per__i2c3,
 839         &am33xx_l4_per__mailbox,
 840         &am33xx_l4_ls__mcasp0,
 841         &am33xx_l4_ls__mcasp1,
 842         &am33xx_l4_ls__mmc0,
 843         &am33xx_l4_ls__mmc1,
 844         &am33xx_l3_s__mmc2,
 845         &am33xx_l4_ls__timer2,
 846         &am33xx_l4_ls__timer3,
 847         &am33xx_l4_ls__timer4,
 848         &am33xx_l4_ls__timer5,
 849         &am33xx_l4_ls__timer6,
 850         &am33xx_l4_ls__timer7,
 851         &am33xx_l3_main__tpcc,
 852         &am33xx_l4_ls__uart2,
 853         &am33xx_l4_ls__uart3,
 854         &am33xx_l4_ls__uart4,
 855         &am33xx_l4_ls__uart5,
 856         &am33xx_l4_ls__uart6,
 857         &am33xx_l4_ls__spinlock,
 858         &am33xx_l4_ls__elm,
 859         &am33xx_l4_ls__epwmss0,
 860         &am33xx_epwmss0__ecap0,
 861         &am33xx_epwmss0__eqep0,
 862         &am33xx_epwmss0__ehrpwm0,
 863         &am33xx_l4_ls__epwmss1,
 864         &am33xx_epwmss1__ecap1,
 865         &am33xx_epwmss1__eqep1,
 866         &am33xx_epwmss1__ehrpwm1,
 867         &am33xx_l4_ls__epwmss2,
 868         &am33xx_epwmss2__ecap2,
 869         &am33xx_epwmss2__eqep2,
 870         &am33xx_epwmss2__ehrpwm2,
 871         &am33xx_l3_s__gpmc,
 872         &am33xx_l4_ls__mcspi0,
 873         &am33xx_l4_ls__mcspi1,
 874         &am33xx_l3_main__tptc0,
 875         &am33xx_l3_main__tptc1,
 876         &am33xx_l3_main__tptc2,
 877         &am33xx_l3_main__ocmc,
 878         &am43xx_l4_hs__cpgmac0,
 879         &am33xx_cpgmac0__mdio,
 880         &am33xx_l3_main__sha0,
 881         &am33xx_l3_main__aes0,
 882         &am43xx_l4_ls__ocp2scp0,
 883         &am43xx_l4_ls__ocp2scp1,
 884         &am43xx_l3_s__usbotgss0,
 885         &am43xx_l3_s__usbotgss1,
 886         &am43xx_dss__l3_main,
 887         &am43xx_l4_ls__dss,
 888         &am43xx_l4_ls__dss_dispc,
 889         &am43xx_l4_ls__dss_rfbi,
 890         NULL,
 891 };
 892
 893 int __init am43xx_hwmod_init(void)
 894 {
 895         omap_hwmod_am43xx_reg();
 896         omap_hwmod_init();
 897         return omap_hwmod_register_links(am43xx_hwmod_ocp_ifs);
 898 }