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Merge tag 'virtio-next-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_44xx_data.c
1 /*
2 * Hardware modules present on the OMAP44xx chips
3 *
4 * Copyright (C) 2009-2012 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley
8 * Benoit Cousson
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 * Note that this file is currently not in sync with autogeneration scripts.
16 * The above note to be removed, once it is synced up.
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21 */
22
23 #include <linux/io.h>
24 #include <linux/platform_data/gpio-omap.h>
25 #include <linux/power/smartreflex.h>
26 #include <linux/i2c-omap.h>
27
28 #include <linux/omap-dma.h>
29
30 #include <linux/platform_data/spi-omap2-mcspi.h>
31 #include <linux/platform_data/asoc-ti-mcbsp.h>
32 #include <linux/platform_data/iommu-omap.h>
33 #include <plat/dmtimer.h>
34
35 #include "omap_hwmod.h"
36 #include "omap_hwmod_common_data.h"
37 #include "cm1_44xx.h"
38 #include "cm2_44xx.h"
39 #include "prm44xx.h"
40 #include "prm-regbits-44xx.h"
41 #include "i2c.h"
42 #include "mmc.h"
43 #include "wd_timer.h"
44
45 /* Base offset for all OMAP4 interrupts external to MPUSS */
46 #define OMAP44XX_IRQ_GIC_START 32
47
48 /* Base offset for all OMAP4 dma requests */
49 #define OMAP44XX_DMA_REQ_START 1
50
51 /*
52 * IP blocks
53 */
54
55 /*
56 * 'dmm' class
57 * instance(s): dmm
58 */
59 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
60 .name = "dmm",
61 };
62
63 /* dmm */
64 static struct omap_hwmod omap44xx_dmm_hwmod = {
65 .name = "dmm",
66 .class = &omap44xx_dmm_hwmod_class,
67 .clkdm_name = "l3_emif_clkdm",
68 .prcm = {
69 .omap4 = {
70 .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
71 .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
72 },
73 },
74 };
75
76 /*
77 * 'l3' class
78 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
79 */
80 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
81 .name = "l3",
82 };
83
84 /* l3_instr */
85 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
86 .name = "l3_instr",
87 .class = &omap44xx_l3_hwmod_class,
88 .clkdm_name = "l3_instr_clkdm",
89 .prcm = {
90 .omap4 = {
91 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
92 .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
93 .modulemode = MODULEMODE_HWCTRL,
94 },
95 },
96 };
97
98 /* l3_main_1 */
99 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
100 .name = "l3_main_1",
101 .class = &omap44xx_l3_hwmod_class,
102 .clkdm_name = "l3_1_clkdm",
103 .prcm = {
104 .omap4 = {
105 .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
106 .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
107 },
108 },
109 };
110
111 /* l3_main_2 */
112 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
113 .name = "l3_main_2",
114 .class = &omap44xx_l3_hwmod_class,
115 .clkdm_name = "l3_2_clkdm",
116 .prcm = {
117 .omap4 = {
118 .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
119 .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
120 },
121 },
122 };
123
124 /* l3_main_3 */
125 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
126 .name = "l3_main_3",
127 .class = &omap44xx_l3_hwmod_class,
128 .clkdm_name = "l3_instr_clkdm",
129 .prcm = {
130 .omap4 = {
131 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
132 .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
133 .modulemode = MODULEMODE_HWCTRL,
134 },
135 },
136 };
137
138 /*
139 * 'l4' class
140 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
141 */
142 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
143 .name = "l4",
144 };
145
146 /* l4_abe */
147 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
148 .name = "l4_abe",
149 .class = &omap44xx_l4_hwmod_class,
150 .clkdm_name = "abe_clkdm",
151 .prcm = {
152 .omap4 = {
153 .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
154 .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
155 .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
156 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
157 },
158 },
159 };
160
161 /* l4_cfg */
162 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
163 .name = "l4_cfg",
164 .class = &omap44xx_l4_hwmod_class,
165 .clkdm_name = "l4_cfg_clkdm",
166 .prcm = {
167 .omap4 = {
168 .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
169 .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
170 },
171 },
172 };
173
174 /* l4_per */
175 static struct omap_hwmod omap44xx_l4_per_hwmod = {
176 .name = "l4_per",
177 .class = &omap44xx_l4_hwmod_class,
178 .clkdm_name = "l4_per_clkdm",
179 .prcm = {
180 .omap4 = {
181 .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
182 .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
183 },
184 },
185 };
186
187 /* l4_wkup */
188 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
189 .name = "l4_wkup",
190 .class = &omap44xx_l4_hwmod_class,
191 .clkdm_name = "l4_wkup_clkdm",
192 .prcm = {
193 .omap4 = {
194 .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
195 .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
196 },
197 },
198 };
199
200 /*
201 * 'mpu_bus' class
202 * instance(s): mpu_private
203 */
204 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
205 .name = "mpu_bus",
206 };
207
208 /* mpu_private */
209 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
210 .name = "mpu_private",
211 .class = &omap44xx_mpu_bus_hwmod_class,
212 .clkdm_name = "mpuss_clkdm",
213 .prcm = {
214 .omap4 = {
215 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
216 },
217 },
218 };
219
220 /*
221 * 'ocp_wp_noc' class
222 * instance(s): ocp_wp_noc
223 */
224 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
225 .name = "ocp_wp_noc",
226 };
227
228 /* ocp_wp_noc */
229 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
230 .name = "ocp_wp_noc",
231 .class = &omap44xx_ocp_wp_noc_hwmod_class,
232 .clkdm_name = "l3_instr_clkdm",
233 .prcm = {
234 .omap4 = {
235 .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
236 .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
237 .modulemode = MODULEMODE_HWCTRL,
238 },
239 },
240 };
241
242 /*
243 * Modules omap_hwmod structures
244 *
245 * The following IPs are excluded for the moment because:
246 * - They do not need an explicit SW control using omap_hwmod API.
247 * - They still need to be validated with the driver
248 * properly adapted to omap_hwmod / omap_device
249 *
250 * usim
251 */
252
253 /*
254 * 'aess' class
255 * audio engine sub system
256 */
257
258 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
259 .rev_offs = 0x0000,
260 .sysc_offs = 0x0010,
261 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
262 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
263 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
264 MSTANDBY_SMART_WKUP),
265 .sysc_fields = &omap_hwmod_sysc_type2,
266 };
267
268 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
269 .name = "aess",
270 .sysc = &omap44xx_aess_sysc,
271 .enable_preprogram = omap_hwmod_aess_preprogram,
272 };
273
274 /* aess */
275 static struct omap_hwmod omap44xx_aess_hwmod = {
276 .name = "aess",
277 .class = &omap44xx_aess_hwmod_class,
278 .clkdm_name = "abe_clkdm",
279 .main_clk = "aess_fclk",
280 .prcm = {
281 .omap4 = {
282 .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
283 .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
284 .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
285 .modulemode = MODULEMODE_SWCTRL,
286 },
287 },
288 };
289
290 /*
291 * 'c2c' class
292 * chip 2 chip interface used to plug the ape soc (omap) with an external modem
293 * soc
294 */
295
296 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
297 .name = "c2c",
298 };
299
300 /* c2c */
301 static struct omap_hwmod omap44xx_c2c_hwmod = {
302 .name = "c2c",
303 .class = &omap44xx_c2c_hwmod_class,
304 .clkdm_name = "d2d_clkdm",
305 .prcm = {
306 .omap4 = {
307 .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
308 .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
309 },
310 },
311 };
312
313 /*
314 * 'counter' class
315 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
316 */
317
318 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
319 .rev_offs = 0x0000,
320 .sysc_offs = 0x0004,
321 .sysc_flags = SYSC_HAS_SIDLEMODE,
322 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
323 .sysc_fields = &omap_hwmod_sysc_type1,
324 };
325
326 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
327 .name = "counter",
328 .sysc = &omap44xx_counter_sysc,
329 };
330
331 /* counter_32k */
332 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
333 .name = "counter_32k",
334 .class = &omap44xx_counter_hwmod_class,
335 .clkdm_name = "l4_wkup_clkdm",
336 .flags = HWMOD_SWSUP_SIDLE,
337 .main_clk = "sys_32k_ck",
338 .prcm = {
339 .omap4 = {
340 .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
341 .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
342 },
343 },
344 };
345
346 /*
347 * 'ctrl_module' class
348 * attila core control module + core pad control module + wkup pad control
349 * module + attila wkup control module
350 */
351
352 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
353 .rev_offs = 0x0000,
354 .sysc_offs = 0x0010,
355 .sysc_flags = SYSC_HAS_SIDLEMODE,
356 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
357 SIDLE_SMART_WKUP),
358 .sysc_fields = &omap_hwmod_sysc_type2,
359 };
360
361 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
362 .name = "ctrl_module",
363 .sysc = &omap44xx_ctrl_module_sysc,
364 };
365
366 /* ctrl_module_core */
367 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
368 .name = "ctrl_module_core",
369 .class = &omap44xx_ctrl_module_hwmod_class,
370 .clkdm_name = "l4_cfg_clkdm",
371 .prcm = {
372 .omap4 = {
373 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
374 },
375 },
376 };
377
378 /* ctrl_module_pad_core */
379 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
380 .name = "ctrl_module_pad_core",
381 .class = &omap44xx_ctrl_module_hwmod_class,
382 .clkdm_name = "l4_cfg_clkdm",
383 .prcm = {
384 .omap4 = {
385 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
386 },
387 },
388 };
389
390 /* ctrl_module_wkup */
391 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
392 .name = "ctrl_module_wkup",
393 .class = &omap44xx_ctrl_module_hwmod_class,
394 .clkdm_name = "l4_wkup_clkdm",
395 .prcm = {
396 .omap4 = {
397 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
398 },
399 },
400 };
401
402 /* ctrl_module_pad_wkup */
403 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
404 .name = "ctrl_module_pad_wkup",
405 .class = &omap44xx_ctrl_module_hwmod_class,
406 .clkdm_name = "l4_wkup_clkdm",
407 .prcm = {
408 .omap4 = {
409 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
410 },
411 },
412 };
413
414 /*
415 * 'debugss' class
416 * debug and emulation sub system
417 */
418
419 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
420 .name = "debugss",
421 };
422
423 /* debugss */
424 static struct omap_hwmod omap44xx_debugss_hwmod = {
425 .name = "debugss",
426 .class = &omap44xx_debugss_hwmod_class,
427 .clkdm_name = "emu_sys_clkdm",
428 .main_clk = "trace_clk_div_ck",
429 .prcm = {
430 .omap4 = {
431 .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
432 .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
433 },
434 },
435 };
436
437 /*
438 * 'dma' class
439 * dma controller for data exchange between memory to memory (i.e. internal or
440 * external memory) and gp peripherals to memory or memory to gp peripherals
441 */
442
443 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
444 .rev_offs = 0x0000,
445 .sysc_offs = 0x002c,
446 .syss_offs = 0x0028,
447 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
448 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
449 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
450 SYSS_HAS_RESET_STATUS),
451 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
452 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
453 .sysc_fields = &omap_hwmod_sysc_type1,
454 };
455
456 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
457 .name = "dma",
458 .sysc = &omap44xx_dma_sysc,
459 };
460
461 /* dma dev_attr */
462 static struct omap_dma_dev_attr dma_dev_attr = {
463 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
464 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
465 .lch_count = 32,
466 };
467
468 /* dma_system */
469 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
470 { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
471 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
472 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
473 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
474 { .irq = -1 }
475 };
476
477 static struct omap_hwmod omap44xx_dma_system_hwmod = {
478 .name = "dma_system",
479 .class = &omap44xx_dma_hwmod_class,
480 .clkdm_name = "l3_dma_clkdm",
481 .mpu_irqs = omap44xx_dma_system_irqs,
482 .main_clk = "l3_div_ck",
483 .prcm = {
484 .omap4 = {
485 .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
486 .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
487 },
488 },
489 .dev_attr = &dma_dev_attr,
490 };
491
492 /*
493 * 'dmic' class
494 * digital microphone controller
495 */
496
497 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
498 .rev_offs = 0x0000,
499 .sysc_offs = 0x0010,
500 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
501 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
502 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
503 SIDLE_SMART_WKUP),
504 .sysc_fields = &omap_hwmod_sysc_type2,
505 };
506
507 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
508 .name = "dmic",
509 .sysc = &omap44xx_dmic_sysc,
510 };
511
512 /* dmic */
513 static struct omap_hwmod omap44xx_dmic_hwmod = {
514 .name = "dmic",
515 .class = &omap44xx_dmic_hwmod_class,
516 .clkdm_name = "abe_clkdm",
517 .main_clk = "func_dmic_abe_gfclk",
518 .prcm = {
519 .omap4 = {
520 .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
521 .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
522 .modulemode = MODULEMODE_SWCTRL,
523 },
524 },
525 };
526
527 /*
528 * 'dsp' class
529 * dsp sub-system
530 */
531
532 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
533 .name = "dsp",
534 };
535
536 /* dsp */
537 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
538 { .name = "dsp", .rst_shift = 0 },
539 };
540
541 static struct omap_hwmod omap44xx_dsp_hwmod = {
542 .name = "dsp",
543 .class = &omap44xx_dsp_hwmod_class,
544 .clkdm_name = "tesla_clkdm",
545 .rst_lines = omap44xx_dsp_resets,
546 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
547 .main_clk = "dpll_iva_m4x2_ck",
548 .prcm = {
549 .omap4 = {
550 .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
551 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
552 .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
553 .modulemode = MODULEMODE_HWCTRL,
554 },
555 },
556 };
557
558 /*
559 * 'dss' class
560 * display sub-system
561 */
562
563 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
564 .rev_offs = 0x0000,
565 .syss_offs = 0x0014,
566 .sysc_flags = SYSS_HAS_RESET_STATUS,
567 };
568
569 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
570 .name = "dss",
571 .sysc = &omap44xx_dss_sysc,
572 .reset = omap_dss_reset,
573 };
574
575 /* dss */
576 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
577 { .role = "sys_clk", .clk = "dss_sys_clk" },
578 { .role = "tv_clk", .clk = "dss_tv_clk" },
579 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
580 };
581
582 static struct omap_hwmod omap44xx_dss_hwmod = {
583 .name = "dss_core",
584 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
585 .class = &omap44xx_dss_hwmod_class,
586 .clkdm_name = "l3_dss_clkdm",
587 .main_clk = "dss_dss_clk",
588 .prcm = {
589 .omap4 = {
590 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
591 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
592 },
593 },
594 .opt_clks = dss_opt_clks,
595 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
596 };
597
598 /*
599 * 'dispc' class
600 * display controller
601 */
602
603 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
604 .rev_offs = 0x0000,
605 .sysc_offs = 0x0010,
606 .syss_offs = 0x0014,
607 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
608 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
609 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
610 SYSS_HAS_RESET_STATUS),
611 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
612 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
613 .sysc_fields = &omap_hwmod_sysc_type1,
614 };
615
616 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
617 .name = "dispc",
618 .sysc = &omap44xx_dispc_sysc,
619 };
620
621 /* dss_dispc */
622 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
623 { .irq = 25 + OMAP44XX_IRQ_GIC_START },
624 { .irq = -1 }
625 };
626
627 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
628 { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
629 { .dma_req = -1 }
630 };
631
632 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
633 .manager_count = 3,
634 .has_framedonetv_irq = 1
635 };
636
637 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
638 .name = "dss_dispc",
639 .class = &omap44xx_dispc_hwmod_class,
640 .clkdm_name = "l3_dss_clkdm",
641 .mpu_irqs = omap44xx_dss_dispc_irqs,
642 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
643 .main_clk = "dss_dss_clk",
644 .prcm = {
645 .omap4 = {
646 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
647 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
648 },
649 },
650 .dev_attr = &omap44xx_dss_dispc_dev_attr
651 };
652
653 /*
654 * 'dsi' class
655 * display serial interface controller
656 */
657
658 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
659 .rev_offs = 0x0000,
660 .sysc_offs = 0x0010,
661 .syss_offs = 0x0014,
662 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
663 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
664 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
665 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
666 .sysc_fields = &omap_hwmod_sysc_type1,
667 };
668
669 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
670 .name = "dsi",
671 .sysc = &omap44xx_dsi_sysc,
672 };
673
674 /* dss_dsi1 */
675 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
676 { .irq = 53 + OMAP44XX_IRQ_GIC_START },
677 { .irq = -1 }
678 };
679
680 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
681 { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
682 { .dma_req = -1 }
683 };
684
685 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
686 { .role = "sys_clk", .clk = "dss_sys_clk" },
687 };
688
689 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
690 .name = "dss_dsi1",
691 .class = &omap44xx_dsi_hwmod_class,
692 .clkdm_name = "l3_dss_clkdm",
693 .mpu_irqs = omap44xx_dss_dsi1_irqs,
694 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
695 .main_clk = "dss_dss_clk",
696 .prcm = {
697 .omap4 = {
698 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
699 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
700 },
701 },
702 .opt_clks = dss_dsi1_opt_clks,
703 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
704 };
705
706 /* dss_dsi2 */
707 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
708 { .irq = 84 + OMAP44XX_IRQ_GIC_START },
709 { .irq = -1 }
710 };
711
712 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
713 { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
714 { .dma_req = -1 }
715 };
716
717 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
718 { .role = "sys_clk", .clk = "dss_sys_clk" },
719 };
720
721 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
722 .name = "dss_dsi2",
723 .class = &omap44xx_dsi_hwmod_class,
724 .clkdm_name = "l3_dss_clkdm",
725 .mpu_irqs = omap44xx_dss_dsi2_irqs,
726 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
727 .main_clk = "dss_dss_clk",
728 .prcm = {
729 .omap4 = {
730 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
731 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
732 },
733 },
734 .opt_clks = dss_dsi2_opt_clks,
735 .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
736 };
737
738 /*
739 * 'hdmi' class
740 * hdmi controller
741 */
742
743 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
744 .rev_offs = 0x0000,
745 .sysc_offs = 0x0010,
746 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
747 SYSC_HAS_SOFTRESET),
748 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
749 SIDLE_SMART_WKUP),
750 .sysc_fields = &omap_hwmod_sysc_type2,
751 };
752
753 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
754 .name = "hdmi",
755 .sysc = &omap44xx_hdmi_sysc,
756 };
757
758 /* dss_hdmi */
759 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
760 { .irq = 101 + OMAP44XX_IRQ_GIC_START },
761 { .irq = -1 }
762 };
763
764 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
765 { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
766 { .dma_req = -1 }
767 };
768
769 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
770 { .role = "sys_clk", .clk = "dss_sys_clk" },
771 };
772
773 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
774 .name = "dss_hdmi",
775 .class = &omap44xx_hdmi_hwmod_class,
776 .clkdm_name = "l3_dss_clkdm",
777 /*
778 * HDMI audio requires to use no-idle mode. Hence,
779 * set idle mode by software.
780 */
781 .flags = HWMOD_SWSUP_SIDLE,
782 .mpu_irqs = omap44xx_dss_hdmi_irqs,
783 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
784 .main_clk = "dss_48mhz_clk",
785 .prcm = {
786 .omap4 = {
787 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
788 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
789 },
790 },
791 .opt_clks = dss_hdmi_opt_clks,
792 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
793 };
794
795 /*
796 * 'rfbi' class
797 * remote frame buffer interface
798 */
799
800 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
801 .rev_offs = 0x0000,
802 .sysc_offs = 0x0010,
803 .syss_offs = 0x0014,
804 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
805 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
806 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
807 .sysc_fields = &omap_hwmod_sysc_type1,
808 };
809
810 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
811 .name = "rfbi",
812 .sysc = &omap44xx_rfbi_sysc,
813 };
814
815 /* dss_rfbi */
816 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
817 { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
818 { .dma_req = -1 }
819 };
820
821 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
822 { .role = "ick", .clk = "dss_fck" },
823 };
824
825 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
826 .name = "dss_rfbi",
827 .class = &omap44xx_rfbi_hwmod_class,
828 .clkdm_name = "l3_dss_clkdm",
829 .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
830 .main_clk = "dss_dss_clk",
831 .prcm = {
832 .omap4 = {
833 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
834 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
835 },
836 },
837 .opt_clks = dss_rfbi_opt_clks,
838 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
839 };
840
841 /*
842 * 'venc' class
843 * video encoder
844 */
845
846 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
847 .name = "venc",
848 };
849
850 /* dss_venc */
851 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
852 .name = "dss_venc",
853 .class = &omap44xx_venc_hwmod_class,
854 .clkdm_name = "l3_dss_clkdm",
855 .main_clk = "dss_tv_clk",
856 .prcm = {
857 .omap4 = {
858 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
859 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
860 },
861 },
862 };
863
864 /*
865 * 'elm' class
866 * bch error location module
867 */
868
869 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
870 .rev_offs = 0x0000,
871 .sysc_offs = 0x0010,
872 .syss_offs = 0x0014,
873 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
874 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
875 SYSS_HAS_RESET_STATUS),
876 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
877 .sysc_fields = &omap_hwmod_sysc_type1,
878 };
879
880 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
881 .name = "elm",
882 .sysc = &omap44xx_elm_sysc,
883 };
884
885 /* elm */
886 static struct omap_hwmod omap44xx_elm_hwmod = {
887 .name = "elm",
888 .class = &omap44xx_elm_hwmod_class,
889 .clkdm_name = "l4_per_clkdm",
890 .prcm = {
891 .omap4 = {
892 .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
893 .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
894 },
895 },
896 };
897
898 /*
899 * 'emif' class
900 * external memory interface no1
901 */
902
903 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
904 .rev_offs = 0x0000,
905 };
906
907 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
908 .name = "emif",
909 .sysc = &omap44xx_emif_sysc,
910 };
911
912 /* emif1 */
913 static struct omap_hwmod omap44xx_emif1_hwmod = {
914 .name = "emif1",
915 .class = &omap44xx_emif_hwmod_class,
916 .clkdm_name = "l3_emif_clkdm",
917 .flags = HWMOD_INIT_NO_IDLE,
918 .main_clk = "ddrphy_ck",
919 .prcm = {
920 .omap4 = {
921 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
922 .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
923 .modulemode = MODULEMODE_HWCTRL,
924 },
925 },
926 };
927
928 /* emif2 */
929 static struct omap_hwmod omap44xx_emif2_hwmod = {
930 .name = "emif2",
931 .class = &omap44xx_emif_hwmod_class,
932 .clkdm_name = "l3_emif_clkdm",
933 .flags = HWMOD_INIT_NO_IDLE,
934 .main_clk = "ddrphy_ck",
935 .prcm = {
936 .omap4 = {
937 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
938 .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
939 .modulemode = MODULEMODE_HWCTRL,
940 },
941 },
942 };
943
944 /*
945 * 'fdif' class
946 * face detection hw accelerator module
947 */
948
949 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
950 .rev_offs = 0x0000,
951 .sysc_offs = 0x0010,
952 /*
953 * FDIF needs 100 OCP clk cycles delay after a softreset before
954 * accessing sysconfig again.
955 * The lowest frequency at the moment for L3 bus is 100 MHz, so
956 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
957 *
958 * TODO: Indicate errata when available.
959 */
960 .srst_udelay = 2,
961 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
962 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
963 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
964 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
965 .sysc_fields = &omap_hwmod_sysc_type2,
966 };
967
968 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
969 .name = "fdif",
970 .sysc = &omap44xx_fdif_sysc,
971 };
972
973 /* fdif */
974 static struct omap_hwmod omap44xx_fdif_hwmod = {
975 .name = "fdif",
976 .class = &omap44xx_fdif_hwmod_class,
977 .clkdm_name = "iss_clkdm",
978 .main_clk = "fdif_fck",
979 .prcm = {
980 .omap4 = {
981 .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
982 .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
983 .modulemode = MODULEMODE_SWCTRL,
984 },
985 },
986 };
987
988 /*
989 * 'gpio' class
990 * general purpose io module
991 */
992
993 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
994 .rev_offs = 0x0000,
995 .sysc_offs = 0x0010,
996 .syss_offs = 0x0114,
997 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
998 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
999 SYSS_HAS_RESET_STATUS),
1000 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1001 SIDLE_SMART_WKUP),
1002 .sysc_fields = &omap_hwmod_sysc_type1,
1003 };
1004
1005 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1006 .name = "gpio",
1007 .sysc = &omap44xx_gpio_sysc,
1008 .rev = 2,
1009 };
1010
1011 /* gpio dev_attr */
1012 static struct omap_gpio_dev_attr gpio_dev_attr = {
1013 .bank_width = 32,
1014 .dbck_flag = true,
1015 };
1016
1017 /* gpio1 */
1018 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1019 { .role = "dbclk", .clk = "gpio1_dbclk" },
1020 };
1021
1022 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1023 .name = "gpio1",
1024 .class = &omap44xx_gpio_hwmod_class,
1025 .clkdm_name = "l4_wkup_clkdm",
1026 .main_clk = "l4_wkup_clk_mux_ck",
1027 .prcm = {
1028 .omap4 = {
1029 .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1030 .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1031 .modulemode = MODULEMODE_HWCTRL,
1032 },
1033 },
1034 .opt_clks = gpio1_opt_clks,
1035 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1036 .dev_attr = &gpio_dev_attr,
1037 };
1038
1039 /* gpio2 */
1040 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1041 { .role = "dbclk", .clk = "gpio2_dbclk" },
1042 };
1043
1044 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1045 .name = "gpio2",
1046 .class = &omap44xx_gpio_hwmod_class,
1047 .clkdm_name = "l4_per_clkdm",
1048 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1049 .main_clk = "l4_div_ck",
1050 .prcm = {
1051 .omap4 = {
1052 .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1053 .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1054 .modulemode = MODULEMODE_HWCTRL,
1055 },
1056 },
1057 .opt_clks = gpio2_opt_clks,
1058 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1059 .dev_attr = &gpio_dev_attr,
1060 };
1061
1062 /* gpio3 */
1063 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1064 { .role = "dbclk", .clk = "gpio3_dbclk" },
1065 };
1066
1067 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1068 .name = "gpio3",
1069 .class = &omap44xx_gpio_hwmod_class,
1070 .clkdm_name = "l4_per_clkdm",
1071 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1072 .main_clk = "l4_div_ck",
1073 .prcm = {
1074 .omap4 = {
1075 .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1076 .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1077 .modulemode = MODULEMODE_HWCTRL,
1078 },
1079 },
1080 .opt_clks = gpio3_opt_clks,
1081 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1082 .dev_attr = &gpio_dev_attr,
1083 };
1084
1085 /* gpio4 */
1086 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1087 { .role = "dbclk", .clk = "gpio4_dbclk" },
1088 };
1089
1090 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1091 .name = "gpio4",
1092 .class = &omap44xx_gpio_hwmod_class,
1093 .clkdm_name = "l4_per_clkdm",
1094 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1095 .main_clk = "l4_div_ck",
1096 .prcm = {
1097 .omap4 = {
1098 .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1099 .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1100 .modulemode = MODULEMODE_HWCTRL,
1101 },
1102 },
1103 .opt_clks = gpio4_opt_clks,
1104 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1105 .dev_attr = &gpio_dev_attr,
1106 };
1107
1108 /* gpio5 */
1109 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1110 { .role = "dbclk", .clk = "gpio5_dbclk" },
1111 };
1112
1113 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1114 .name = "gpio5",
1115 .class = &omap44xx_gpio_hwmod_class,
1116 .clkdm_name = "l4_per_clkdm",
1117 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1118 .main_clk = "l4_div_ck",
1119 .prcm = {
1120 .omap4 = {
1121 .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1122 .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1123 .modulemode = MODULEMODE_HWCTRL,
1124 },
1125 },
1126 .opt_clks = gpio5_opt_clks,
1127 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1128 .dev_attr = &gpio_dev_attr,
1129 };
1130
1131 /* gpio6 */
1132 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1133 { .role = "dbclk", .clk = "gpio6_dbclk" },
1134 };
1135
1136 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1137 .name = "gpio6",
1138 .class = &omap44xx_gpio_hwmod_class,
1139 .clkdm_name = "l4_per_clkdm",
1140 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1141 .main_clk = "l4_div_ck",
1142 .prcm = {
1143 .omap4 = {
1144 .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1145 .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1146 .modulemode = MODULEMODE_HWCTRL,
1147 },
1148 },
1149 .opt_clks = gpio6_opt_clks,
1150 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1151 .dev_attr = &gpio_dev_attr,
1152 };
1153
1154 /*
1155 * 'gpmc' class
1156 * general purpose memory controller
1157 */
1158
1159 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1160 .rev_offs = 0x0000,
1161 .sysc_offs = 0x0010,
1162 .syss_offs = 0x0014,
1163 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1164 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1165 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1166 .sysc_fields = &omap_hwmod_sysc_type1,
1167 };
1168
1169 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1170 .name = "gpmc",
1171 .sysc = &omap44xx_gpmc_sysc,
1172 };
1173
1174 /* gpmc */
1175 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1176 .name = "gpmc",
1177 .class = &omap44xx_gpmc_hwmod_class,
1178 .clkdm_name = "l3_2_clkdm",
1179 /*
1180 * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
1181 * block. It is not being added due to any known bugs with
1182 * resetting the GPMC IP block, but rather because any timings
1183 * set by the bootloader are not being correctly programmed by
1184 * the kernel from the board file or DT data.
1185 * HWMOD_INIT_NO_RESET should be removed ASAP.
1186 */
1187 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1188 .prcm = {
1189 .omap4 = {
1190 .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1191 .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1192 .modulemode = MODULEMODE_HWCTRL,
1193 },
1194 },
1195 };
1196
1197 /*
1198 * 'gpu' class
1199 * 2d/3d graphics accelerator
1200 */
1201
1202 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1203 .rev_offs = 0x1fc00,
1204 .sysc_offs = 0x1fc10,
1205 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1206 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1207 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1208 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1209 .sysc_fields = &omap_hwmod_sysc_type2,
1210 };
1211
1212 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1213 .name = "gpu",
1214 .sysc = &omap44xx_gpu_sysc,
1215 };
1216
1217 /* gpu */
1218 static struct omap_hwmod omap44xx_gpu_hwmod = {
1219 .name = "gpu",
1220 .class = &omap44xx_gpu_hwmod_class,
1221 .clkdm_name = "l3_gfx_clkdm",
1222 .main_clk = "sgx_clk_mux",
1223 .prcm = {
1224 .omap4 = {
1225 .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1226 .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1227 .modulemode = MODULEMODE_SWCTRL,
1228 },
1229 },
1230 };
1231
1232 /*
1233 * 'hdq1w' class
1234 * hdq / 1-wire serial interface controller
1235 */
1236
1237 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1238 .rev_offs = 0x0000,
1239 .sysc_offs = 0x0014,
1240 .syss_offs = 0x0018,
1241 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1242 SYSS_HAS_RESET_STATUS),
1243 .sysc_fields = &omap_hwmod_sysc_type1,
1244 };
1245
1246 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1247 .name = "hdq1w",
1248 .sysc = &omap44xx_hdq1w_sysc,
1249 };
1250
1251 /* hdq1w */
1252 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1253 .name = "hdq1w",
1254 .class = &omap44xx_hdq1w_hwmod_class,
1255 .clkdm_name = "l4_per_clkdm",
1256 .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */
1257 .main_clk = "func_12m_fclk",
1258 .prcm = {
1259 .omap4 = {
1260 .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1261 .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1262 .modulemode = MODULEMODE_SWCTRL,
1263 },
1264 },
1265 };
1266
1267 /*
1268 * 'hsi' class
1269 * mipi high-speed synchronous serial interface (multichannel and full-duplex
1270 * serial if)
1271 */
1272
1273 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1274 .rev_offs = 0x0000,
1275 .sysc_offs = 0x0010,
1276 .syss_offs = 0x0014,
1277 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1278 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1279 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1280 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1281 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1282 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1283 .sysc_fields = &omap_hwmod_sysc_type1,
1284 };
1285
1286 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1287 .name = "hsi",
1288 .sysc = &omap44xx_hsi_sysc,
1289 };
1290
1291 /* hsi */
1292 static struct omap_hwmod omap44xx_hsi_hwmod = {
1293 .name = "hsi",
1294 .class = &omap44xx_hsi_hwmod_class,
1295 .clkdm_name = "l3_init_clkdm",
1296 .main_clk = "hsi_fck",
1297 .prcm = {
1298 .omap4 = {
1299 .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1300 .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1301 .modulemode = MODULEMODE_HWCTRL,
1302 },
1303 },
1304 };
1305
1306 /*
1307 * 'i2c' class
1308 * multimaster high-speed i2c controller
1309 */
1310
1311 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1312 .sysc_offs = 0x0010,
1313 .syss_offs = 0x0090,
1314 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1315 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1316 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1317 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1318 SIDLE_SMART_WKUP),
1319 .clockact = CLOCKACT_TEST_ICLK,
1320 .sysc_fields = &omap_hwmod_sysc_type1,
1321 };
1322
1323 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1324 .name = "i2c",
1325 .sysc = &omap44xx_i2c_sysc,
1326 .rev = OMAP_I2C_IP_VERSION_2,
1327 .reset = &omap_i2c_reset,
1328 };
1329
1330 static struct omap_i2c_dev_attr i2c_dev_attr = {
1331 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1332 };
1333
1334 /* i2c1 */
1335 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1336 .name = "i2c1",
1337 .class = &omap44xx_i2c_hwmod_class,
1338 .clkdm_name = "l4_per_clkdm",
1339 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1340 .main_clk = "func_96m_fclk",
1341 .prcm = {
1342 .omap4 = {
1343 .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1344 .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1345 .modulemode = MODULEMODE_SWCTRL,
1346 },
1347 },
1348 .dev_attr = &i2c_dev_attr,
1349 };
1350
1351 /* i2c2 */
1352 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1353 .name = "i2c2",
1354 .class = &omap44xx_i2c_hwmod_class,
1355 .clkdm_name = "l4_per_clkdm",
1356 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1357 .main_clk = "func_96m_fclk",
1358 .prcm = {
1359 .omap4 = {
1360 .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1361 .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1362 .modulemode = MODULEMODE_SWCTRL,
1363 },
1364 },
1365 .dev_attr = &i2c_dev_attr,
1366 };
1367
1368 /* i2c3 */
1369 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1370 .name = "i2c3",
1371 .class = &omap44xx_i2c_hwmod_class,
1372 .clkdm_name = "l4_per_clkdm",
1373 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1374 .main_clk = "func_96m_fclk",
1375 .prcm = {
1376 .omap4 = {
1377 .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1378 .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1379 .modulemode = MODULEMODE_SWCTRL,
1380 },
1381 },
1382 .dev_attr = &i2c_dev_attr,
1383 };
1384
1385 /* i2c4 */
1386 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1387 .name = "i2c4",
1388 .class = &omap44xx_i2c_hwmod_class,
1389 .clkdm_name = "l4_per_clkdm",
1390 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1391 .main_clk = "func_96m_fclk",
1392 .prcm = {
1393 .omap4 = {
1394 .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1395 .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1396 .modulemode = MODULEMODE_SWCTRL,
1397 },
1398 },
1399 .dev_attr = &i2c_dev_attr,
1400 };
1401
1402 /*
1403 * 'ipu' class
1404 * imaging processor unit
1405 */
1406
1407 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1408 .name = "ipu",
1409 };
1410
1411 /* ipu */
1412 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1413 { .name = "cpu0", .rst_shift = 0 },
1414 { .name = "cpu1", .rst_shift = 1 },
1415 };
1416
1417 static struct omap_hwmod omap44xx_ipu_hwmod = {
1418 .name = "ipu",
1419 .class = &omap44xx_ipu_hwmod_class,
1420 .clkdm_name = "ducati_clkdm",
1421 .rst_lines = omap44xx_ipu_resets,
1422 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
1423 .main_clk = "ducati_clk_mux_ck",
1424 .prcm = {
1425 .omap4 = {
1426 .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1427 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1428 .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1429 .modulemode = MODULEMODE_HWCTRL,
1430 },
1431 },
1432 };
1433
1434 /*
1435 * 'iss' class
1436 * external images sensor pixel data processor
1437 */
1438
1439 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1440 .rev_offs = 0x0000,
1441 .sysc_offs = 0x0010,
1442 /*
1443 * ISS needs 100 OCP clk cycles delay after a softreset before
1444 * accessing sysconfig again.
1445 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1446 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1447 *
1448 * TODO: Indicate errata when available.
1449 */
1450 .srst_udelay = 2,
1451 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1452 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1453 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1454 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1455 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1456 .sysc_fields = &omap_hwmod_sysc_type2,
1457 };
1458
1459 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1460 .name = "iss",
1461 .sysc = &omap44xx_iss_sysc,
1462 };
1463
1464 /* iss */
1465 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1466 { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1467 };
1468
1469 static struct omap_hwmod omap44xx_iss_hwmod = {
1470 .name = "iss",
1471 .class = &omap44xx_iss_hwmod_class,
1472 .clkdm_name = "iss_clkdm",
1473 .main_clk = "ducati_clk_mux_ck",
1474 .prcm = {
1475 .omap4 = {
1476 .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1477 .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1478 .modulemode = MODULEMODE_SWCTRL,
1479 },
1480 },
1481 .opt_clks = iss_opt_clks,
1482 .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
1483 };
1484
1485 /*
1486 * 'iva' class
1487 * multi-standard video encoder/decoder hardware accelerator
1488 */
1489
1490 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1491 .name = "iva",
1492 };
1493
1494 /* iva */
1495 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1496 { .name = "seq0", .rst_shift = 0 },
1497 { .name = "seq1", .rst_shift = 1 },
1498 { .name = "logic", .rst_shift = 2 },
1499 };
1500
1501 static struct omap_hwmod omap44xx_iva_hwmod = {
1502 .name = "iva",
1503 .class = &omap44xx_iva_hwmod_class,
1504 .clkdm_name = "ivahd_clkdm",
1505 .rst_lines = omap44xx_iva_resets,
1506 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
1507 .main_clk = "dpll_iva_m5x2_ck",
1508 .prcm = {
1509 .omap4 = {
1510 .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1511 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1512 .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1513 .modulemode = MODULEMODE_HWCTRL,
1514 },
1515 },
1516 };
1517
1518 /*
1519 * 'kbd' class
1520 * keyboard controller
1521 */
1522
1523 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1524 .rev_offs = 0x0000,
1525 .sysc_offs = 0x0010,
1526 .syss_offs = 0x0014,
1527 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1528 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1529 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1530 SYSS_HAS_RESET_STATUS),
1531 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1532 .sysc_fields = &omap_hwmod_sysc_type1,
1533 };
1534
1535 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1536 .name = "kbd",
1537 .sysc = &omap44xx_kbd_sysc,
1538 };
1539
1540 /* kbd */
1541 static struct omap_hwmod omap44xx_kbd_hwmod = {
1542 .name = "kbd",
1543 .class = &omap44xx_kbd_hwmod_class,
1544 .clkdm_name = "l4_wkup_clkdm",
1545 .main_clk = "sys_32k_ck",
1546 .prcm = {
1547 .omap4 = {
1548 .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1549 .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1550 .modulemode = MODULEMODE_SWCTRL,
1551 },
1552 },
1553 };
1554
1555 /*
1556 * 'mailbox' class
1557 * mailbox module allowing communication between the on-chip processors using a
1558 * queued mailbox-interrupt mechanism.
1559 */
1560
1561 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1562 .rev_offs = 0x0000,
1563 .sysc_offs = 0x0010,
1564 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1565 SYSC_HAS_SOFTRESET),
1566 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1567 .sysc_fields = &omap_hwmod_sysc_type2,
1568 };
1569
1570 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1571 .name = "mailbox",
1572 .sysc = &omap44xx_mailbox_sysc,
1573 };
1574
1575 /* mailbox */
1576 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1577 .name = "mailbox",
1578 .class = &omap44xx_mailbox_hwmod_class,
1579 .clkdm_name = "l4_cfg_clkdm",
1580 .prcm = {
1581 .omap4 = {
1582 .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1583 .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1584 },
1585 },
1586 };
1587
1588 /*
1589 * 'mcasp' class
1590 * multi-channel audio serial port controller
1591 */
1592
1593 /* The IP is not compliant to type1 / type2 scheme */
1594 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1595 .sidle_shift = 0,
1596 };
1597
1598 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1599 .sysc_offs = 0x0004,
1600 .sysc_flags = SYSC_HAS_SIDLEMODE,
1601 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1602 SIDLE_SMART_WKUP),
1603 .sysc_fields = &omap_hwmod_sysc_type_mcasp,
1604 };
1605
1606 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1607 .name = "mcasp",
1608 .sysc = &omap44xx_mcasp_sysc,
1609 };
1610
1611 /* mcasp */
1612 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1613 .name = "mcasp",
1614 .class = &omap44xx_mcasp_hwmod_class,
1615 .clkdm_name = "abe_clkdm",
1616 .main_clk = "func_mcasp_abe_gfclk",
1617 .prcm = {
1618 .omap4 = {
1619 .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1620 .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1621 .modulemode = MODULEMODE_SWCTRL,
1622 },
1623 },
1624 };
1625
1626 /*
1627 * 'mcbsp' class
1628 * multi channel buffered serial port controller
1629 */
1630
1631 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1632 .sysc_offs = 0x008c,
1633 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1634 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1635 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1636 .sysc_fields = &omap_hwmod_sysc_type1,
1637 };
1638
1639 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1640 .name = "mcbsp",
1641 .sysc = &omap44xx_mcbsp_sysc,
1642 .rev = MCBSP_CONFIG_TYPE4,
1643 };
1644
1645 /* mcbsp1 */
1646 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1647 { .role = "pad_fck", .clk = "pad_clks_ck" },
1648 { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1649 };
1650
1651 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1652 .name = "mcbsp1",
1653 .class = &omap44xx_mcbsp_hwmod_class,
1654 .clkdm_name = "abe_clkdm",
1655 .main_clk = "func_mcbsp1_gfclk",
1656 .prcm = {
1657 .omap4 = {
1658 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1659 .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1660 .modulemode = MODULEMODE_SWCTRL,
1661 },
1662 },
1663 .opt_clks = mcbsp1_opt_clks,
1664 .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
1665 };
1666
1667 /* mcbsp2 */
1668 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1669 { .role = "pad_fck", .clk = "pad_clks_ck" },
1670 { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
1671 };
1672
1673 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
1674 .name = "mcbsp2",
1675 .class = &omap44xx_mcbsp_hwmod_class,
1676 .clkdm_name = "abe_clkdm",
1677 .main_clk = "func_mcbsp2_gfclk",
1678 .prcm = {
1679 .omap4 = {
1680 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
1681 .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
1682 .modulemode = MODULEMODE_SWCTRL,
1683 },
1684 },
1685 .opt_clks = mcbsp2_opt_clks,
1686 .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
1687 };
1688
1689 /* mcbsp3 */
1690 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
1691 { .role = "pad_fck", .clk = "pad_clks_ck" },
1692 { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
1693 };
1694
1695 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
1696 .name = "mcbsp3",
1697 .class = &omap44xx_mcbsp_hwmod_class,
1698 .clkdm_name = "abe_clkdm",
1699 .main_clk = "func_mcbsp3_gfclk",
1700 .prcm = {
1701 .omap4 = {
1702 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
1703 .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
1704 .modulemode = MODULEMODE_SWCTRL,
1705 },
1706 },
1707 .opt_clks = mcbsp3_opt_clks,
1708 .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
1709 };
1710
1711 /* mcbsp4 */
1712 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
1713 { .role = "pad_fck", .clk = "pad_clks_ck" },
1714 { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
1715 };
1716
1717 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
1718 .name = "mcbsp4",
1719 .class = &omap44xx_mcbsp_hwmod_class,
1720 .clkdm_name = "l4_per_clkdm",
1721 .main_clk = "per_mcbsp4_gfclk",
1722 .prcm = {
1723 .omap4 = {
1724 .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
1725 .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
1726 .modulemode = MODULEMODE_SWCTRL,
1727 },
1728 },
1729 .opt_clks = mcbsp4_opt_clks,
1730 .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks),
1731 };
1732
1733 /*
1734 * 'mcpdm' class
1735 * multi channel pdm controller (proprietary interface with phoenix power
1736 * ic)
1737 */
1738
1739 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
1740 .rev_offs = 0x0000,
1741 .sysc_offs = 0x0010,
1742 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1743 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1744 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1745 SIDLE_SMART_WKUP),
1746 .sysc_fields = &omap_hwmod_sysc_type2,
1747 };
1748
1749 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
1750 .name = "mcpdm",
1751 .sysc = &omap44xx_mcpdm_sysc,
1752 };
1753
1754 /* mcpdm */
1755 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
1756 .name = "mcpdm",
1757 .class = &omap44xx_mcpdm_hwmod_class,
1758 .clkdm_name = "abe_clkdm",
1759 /*
1760 * It's suspected that the McPDM requires an off-chip main
1761 * functional clock, controlled via I2C. This IP block is
1762 * currently reset very early during boot, before I2C is
1763 * available, so it doesn't seem that we have any choice in
1764 * the kernel other than to avoid resetting it.
1765 *
1766 * Also, McPDM needs to be configured to NO_IDLE mode when it
1767 * is in used otherwise vital clocks will be gated which
1768 * results 'slow motion' audio playback.
1769 */
1770 .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
1771 .main_clk = "pad_clks_ck",
1772 .prcm = {
1773 .omap4 = {
1774 .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
1775 .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
1776 .modulemode = MODULEMODE_SWCTRL,
1777 },
1778 },
1779 };
1780
1781 /*
1782 * 'mcspi' class
1783 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1784 * bus
1785 */
1786
1787 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
1788 .rev_offs = 0x0000,
1789 .sysc_offs = 0x0010,
1790 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1791 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1792 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1793 SIDLE_SMART_WKUP),
1794 .sysc_fields = &omap_hwmod_sysc_type2,
1795 };
1796
1797 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
1798 .name = "mcspi",
1799 .sysc = &omap44xx_mcspi_sysc,
1800 .rev = OMAP4_MCSPI_REV,
1801 };
1802
1803 /* mcspi1 */
1804 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
1805 { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
1806 { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
1807 { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
1808 { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
1809 { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
1810 { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
1811 { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
1812 { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
1813 { .dma_req = -1 }
1814 };
1815
1816 /* mcspi1 dev_attr */
1817 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1818 .num_chipselect = 4,
1819 };
1820
1821 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
1822 .name = "mcspi1",
1823 .class = &omap44xx_mcspi_hwmod_class,
1824 .clkdm_name = "l4_per_clkdm",
1825 .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
1826 .main_clk = "func_48m_fclk",
1827 .prcm = {
1828 .omap4 = {
1829 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1830 .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1831 .modulemode = MODULEMODE_SWCTRL,
1832 },
1833 },
1834 .dev_attr = &mcspi1_dev_attr,
1835 };
1836
1837 /* mcspi2 */
1838 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
1839 { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
1840 { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
1841 { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
1842 { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
1843 { .dma_req = -1 }
1844 };
1845
1846 /* mcspi2 dev_attr */
1847 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1848 .num_chipselect = 2,
1849 };
1850
1851 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
1852 .name = "mcspi2",
1853 .class = &omap44xx_mcspi_hwmod_class,
1854 .clkdm_name = "l4_per_clkdm",
1855 .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
1856 .main_clk = "func_48m_fclk",
1857 .prcm = {
1858 .omap4 = {
1859 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1860 .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1861 .modulemode = MODULEMODE_SWCTRL,
1862 },
1863 },
1864 .dev_attr = &mcspi2_dev_attr,
1865 };
1866
1867 /* mcspi3 */
1868 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
1869 { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
1870 { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
1871 { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
1872 { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
1873 { .dma_req = -1 }
1874 };
1875
1876 /* mcspi3 dev_attr */
1877 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1878 .num_chipselect = 2,
1879 };
1880
1881 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
1882 .name = "mcspi3",
1883 .class = &omap44xx_mcspi_hwmod_class,
1884 .clkdm_name = "l4_per_clkdm",
1885 .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
1886 .main_clk = "func_48m_fclk",
1887 .prcm = {
1888 .omap4 = {
1889 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1890 .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1891 .modulemode = MODULEMODE_SWCTRL,
1892 },
1893 },
1894 .dev_attr = &mcspi3_dev_attr,
1895 };
1896
1897 /* mcspi4 */
1898 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
1899 { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
1900 { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
1901 { .dma_req = -1 }
1902 };
1903
1904 /* mcspi4 dev_attr */
1905 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1906 .num_chipselect = 1,
1907 };
1908
1909 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
1910 .name = "mcspi4",
1911 .class = &omap44xx_mcspi_hwmod_class,
1912 .clkdm_name = "l4_per_clkdm",
1913 .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
1914 .main_clk = "func_48m_fclk",
1915 .prcm = {
1916 .omap4 = {
1917 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1918 .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1919 .modulemode = MODULEMODE_SWCTRL,
1920 },
1921 },
1922 .dev_attr = &mcspi4_dev_attr,
1923 };
1924
1925 /*
1926 * 'mmc' class
1927 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
1928 */
1929
1930 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
1931 .rev_offs = 0x0000,
1932 .sysc_offs = 0x0010,
1933 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1934 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1935 SYSC_HAS_SOFTRESET),
1936 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1937 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1938 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1939 .sysc_fields = &omap_hwmod_sysc_type2,
1940 };
1941
1942 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
1943 .name = "mmc",
1944 .sysc = &omap44xx_mmc_sysc,
1945 };
1946
1947 /* mmc1 */
1948 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
1949 { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
1950 { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
1951 { .dma_req = -1 }
1952 };
1953
1954 /* mmc1 dev_attr */
1955 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1956 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1957 };
1958
1959 static struct omap_hwmod omap44xx_mmc1_hwmod = {
1960 .name = "mmc1",
1961 .class = &omap44xx_mmc_hwmod_class,
1962 .clkdm_name = "l3_init_clkdm",
1963 .sdma_reqs = omap44xx_mmc1_sdma_reqs,
1964 .main_clk = "hsmmc1_fclk",
1965 .prcm = {
1966 .omap4 = {
1967 .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1968 .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1969 .modulemode = MODULEMODE_SWCTRL,
1970 },
1971 },
1972 .dev_attr = &mmc1_dev_attr,
1973 };
1974
1975 /* mmc2 */
1976 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
1977 { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
1978 { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
1979 { .dma_req = -1 }
1980 };
1981
1982 static struct omap_hwmod omap44xx_mmc2_hwmod = {
1983 .name = "mmc2",
1984 .class = &omap44xx_mmc_hwmod_class,
1985 .clkdm_name = "l3_init_clkdm",
1986 .sdma_reqs = omap44xx_mmc2_sdma_reqs,
1987 .main_clk = "hsmmc2_fclk",
1988 .prcm = {
1989 .omap4 = {
1990 .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1991 .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1992 .modulemode = MODULEMODE_SWCTRL,
1993 },
1994 },
1995 };
1996
1997 /* mmc3 */
1998 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
1999 { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2000 { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2001 { .dma_req = -1 }
2002 };
2003
2004 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2005 .name = "mmc3",
2006 .class = &omap44xx_mmc_hwmod_class,
2007 .clkdm_name = "l4_per_clkdm",
2008 .sdma_reqs = omap44xx_mmc3_sdma_reqs,
2009 .main_clk = "func_48m_fclk",
2010 .prcm = {
2011 .omap4 = {
2012 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2013 .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2014 .modulemode = MODULEMODE_SWCTRL,
2015 },
2016 },
2017 };
2018
2019 /* mmc4 */
2020 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2021 { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2022 { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2023 { .dma_req = -1 }
2024 };
2025
2026 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2027 .name = "mmc4",
2028 .class = &omap44xx_mmc_hwmod_class,
2029 .clkdm_name = "l4_per_clkdm",
2030 .sdma_reqs = omap44xx_mmc4_sdma_reqs,
2031 .main_clk = "func_48m_fclk",
2032 .prcm = {
2033 .omap4 = {
2034 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2035 .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2036 .modulemode = MODULEMODE_SWCTRL,
2037 },
2038 },
2039 };
2040
2041 /* mmc5 */
2042 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2043 { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2044 { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2045 { .dma_req = -1 }
2046 };
2047
2048 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2049 .name = "mmc5",
2050 .class = &omap44xx_mmc_hwmod_class,
2051 .clkdm_name = "l4_per_clkdm",
2052 .sdma_reqs = omap44xx_mmc5_sdma_reqs,
2053 .main_clk = "func_48m_fclk",
2054 .prcm = {
2055 .omap4 = {
2056 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2057 .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2058 .modulemode = MODULEMODE_SWCTRL,
2059 },
2060 },
2061 };
2062
2063 /*
2064 * 'mmu' class
2065 * The memory management unit performs virtual to physical address translation
2066 * for its requestors.
2067 */
2068
2069 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2070 .rev_offs = 0x000,
2071 .sysc_offs = 0x010,
2072 .syss_offs = 0x014,
2073 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2074 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2075 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2076 .sysc_fields = &omap_hwmod_sysc_type1,
2077 };
2078
2079 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
2080 .name = "mmu",
2081 .sysc = &mmu_sysc,
2082 };
2083
2084 /* mmu ipu */
2085
2086 static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
2087 .nr_tlb_entries = 32,
2088 };
2089
2090 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2091 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2092 { .name = "mmu_cache", .rst_shift = 2 },
2093 };
2094
2095 static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = {
2096 {
2097 .pa_start = 0x55082000,
2098 .pa_end = 0x550820ff,
2099 .flags = ADDR_TYPE_RT,
2100 },
2101 { }
2102 };
2103
2104 /* l3_main_2 -> mmu_ipu */
2105 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
2106 .master = &omap44xx_l3_main_2_hwmod,
2107 .slave = &omap44xx_mmu_ipu_hwmod,
2108 .clk = "l3_div_ck",
2109 .addr = omap44xx_mmu_ipu_addrs,
2110 .user = OCP_USER_MPU | OCP_USER_SDMA,
2111 };
2112
2113 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2114 .name = "mmu_ipu",
2115 .class = &omap44xx_mmu_hwmod_class,
2116 .clkdm_name = "ducati_clkdm",
2117 .rst_lines = omap44xx_mmu_ipu_resets,
2118 .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2119 .main_clk = "ducati_clk_mux_ck",
2120 .prcm = {
2121 .omap4 = {
2122 .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2123 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2124 .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2125 .modulemode = MODULEMODE_HWCTRL,
2126 },
2127 },
2128 .dev_attr = &mmu_ipu_dev_attr,
2129 };
2130
2131 /* mmu dsp */
2132
2133 static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
2134 .nr_tlb_entries = 32,
2135 };
2136
2137 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2138 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2139 { .name = "mmu_cache", .rst_shift = 1 },
2140 };
2141
2142 static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = {
2143 {
2144 .pa_start = 0x4a066000,
2145 .pa_end = 0x4a0660ff,
2146 .flags = ADDR_TYPE_RT,
2147 },
2148 { }
2149 };
2150
2151 /* l4_cfg -> dsp */
2152 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
2153 .master = &omap44xx_l4_cfg_hwmod,
2154 .slave = &omap44xx_mmu_dsp_hwmod,
2155 .clk = "l4_div_ck",
2156 .addr = omap44xx_mmu_dsp_addrs,
2157 .user = OCP_USER_MPU | OCP_USER_SDMA,
2158 };
2159
2160 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2161 .name = "mmu_dsp",
2162 .class = &omap44xx_mmu_hwmod_class,
2163 .clkdm_name = "tesla_clkdm",
2164 .rst_lines = omap44xx_mmu_dsp_resets,
2165 .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2166 .main_clk = "dpll_iva_m4x2_ck",
2167 .prcm = {
2168 .omap4 = {
2169 .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
2170 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
2171 .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
2172 .modulemode = MODULEMODE_HWCTRL,
2173 },
2174 },
2175 .dev_attr = &mmu_dsp_dev_attr,
2176 };
2177
2178 /*
2179 * 'mpu' class
2180 * mpu sub-system
2181 */
2182
2183 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2184 .name = "mpu",
2185 };
2186
2187 /* mpu */
2188 static struct omap_hwmod omap44xx_mpu_hwmod = {
2189 .name = "mpu",
2190 .class = &omap44xx_mpu_hwmod_class,
2191 .clkdm_name = "mpuss_clkdm",
2192 .flags = HWMOD_INIT_NO_IDLE,
2193 .main_clk = "dpll_mpu_m2_ck",
2194 .prcm = {
2195 .omap4 = {
2196 .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2197 .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2198 },
2199 },
2200 };
2201
2202 /*
2203 * 'ocmc_ram' class
2204 * top-level core on-chip ram
2205 */
2206
2207 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2208 .name = "ocmc_ram",
2209 };
2210
2211 /* ocmc_ram */
2212 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2213 .name = "ocmc_ram",
2214 .class = &omap44xx_ocmc_ram_hwmod_class,
2215 .clkdm_name = "l3_2_clkdm",
2216 .prcm = {
2217 .omap4 = {
2218 .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2219 .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2220 },
2221 },
2222 };
2223
2224 /*
2225 * 'ocp2scp' class
2226 * bridge to transform ocp interface protocol to scp (serial control port)
2227 * protocol
2228 */
2229
2230 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2231 .rev_offs = 0x0000,
2232 .sysc_offs = 0x0010,
2233 .syss_offs = 0x0014,
2234 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2235 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2236 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2237 .sysc_fields = &omap_hwmod_sysc_type1,
2238 };
2239
2240 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2241 .name = "ocp2scp",
2242 .sysc = &omap44xx_ocp2scp_sysc,
2243 };
2244
2245 /* ocp2scp_usb_phy */
2246 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2247 .name = "ocp2scp_usb_phy",
2248 .class = &omap44xx_ocp2scp_hwmod_class,
2249 .clkdm_name = "l3_init_clkdm",
2250 /*
2251 * ocp2scp_usb_phy_phy_48m is provided by the OMAP4 PRCM IP
2252 * block as an "optional clock," and normally should never be
2253 * specified as the main_clk for an OMAP IP block. However it
2254 * turns out that this clock is actually the main clock for
2255 * the ocp2scp_usb_phy IP block:
2256 * http://lists.infradead.org/pipermail/linux-arm-kernel/2012-September/119943.html
2257 * So listing ocp2scp_usb_phy_phy_48m as a main_clk here seems
2258 * to be the best workaround.
2259 */
2260 .main_clk = "ocp2scp_usb_phy_phy_48m",
2261 .prcm = {
2262 .omap4 = {
2263 .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2264 .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2265 .modulemode = MODULEMODE_HWCTRL,
2266 },
2267 },
2268 };
2269
2270 /*
2271 * 'prcm' class
2272 * power and reset manager (part of the prcm infrastructure) + clock manager 2
2273 * + clock manager 1 (in always on power domain) + local prm in mpu
2274 */
2275
2276 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2277 .name = "prcm",
2278 };
2279
2280 /* prcm_mpu */
2281 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2282 .name = "prcm_mpu",
2283 .class = &omap44xx_prcm_hwmod_class,
2284 .clkdm_name = "l4_wkup_clkdm",
2285 .flags = HWMOD_NO_IDLEST,
2286 .prcm = {
2287 .omap4 = {
2288 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2289 },
2290 },
2291 };
2292
2293 /* cm_core_aon */
2294 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2295 .name = "cm_core_aon",
2296 .class = &omap44xx_prcm_hwmod_class,
2297 .flags = HWMOD_NO_IDLEST,
2298 .prcm = {
2299 .omap4 = {
2300 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2301 },
2302 },
2303 };
2304
2305 /* cm_core */
2306 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2307 .name = "cm_core",
2308 .class = &omap44xx_prcm_hwmod_class,
2309 .flags = HWMOD_NO_IDLEST,
2310 .prcm = {
2311 .omap4 = {
2312 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2313 },
2314 },
2315 };
2316
2317 /* prm */
2318 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2319 { .name = "rst_global_warm_sw", .rst_shift = 0 },
2320 { .name = "rst_global_cold_sw", .rst_shift = 1 },
2321 };
2322
2323 static struct omap_hwmod omap44xx_prm_hwmod = {
2324 .name = "prm",
2325 .class = &omap44xx_prcm_hwmod_class,
2326 .rst_lines = omap44xx_prm_resets,
2327 .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets),
2328 };
2329
2330 /*
2331 * 'scrm' class
2332 * system clock and reset manager
2333 */
2334
2335 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2336 .name = "scrm",
2337 };
2338
2339 /* scrm */
2340 static struct omap_hwmod omap44xx_scrm_hwmod = {
2341 .name = "scrm",
2342 .class = &omap44xx_scrm_hwmod_class,
2343 .clkdm_name = "l4_wkup_clkdm",
2344 .prcm = {
2345 .omap4 = {
2346 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2347 },
2348 },
2349 };
2350
2351 /*
2352 * 'sl2if' class
2353 * shared level 2 memory interface
2354 */
2355
2356 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2357 .name = "sl2if",
2358 };
2359
2360 /* sl2if */
2361 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2362 .name = "sl2if",
2363 .class = &omap44xx_sl2if_hwmod_class,
2364 .clkdm_name = "ivahd_clkdm",
2365 .prcm = {
2366 .omap4 = {
2367 .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2368 .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2369 .modulemode = MODULEMODE_HWCTRL,
2370 },
2371 },
2372 };
2373
2374 /*
2375 * 'slimbus' class
2376 * bidirectional, multi-drop, multi-channel two-line serial interface between
2377 * the device and external components
2378 */
2379
2380 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2381 .rev_offs = 0x0000,
2382 .sysc_offs = 0x0010,
2383 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2384 SYSC_HAS_SOFTRESET),
2385 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2386 SIDLE_SMART_WKUP),
2387 .sysc_fields = &omap_hwmod_sysc_type2,
2388 };
2389
2390 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2391 .name = "slimbus",
2392 .sysc = &omap44xx_slimbus_sysc,
2393 };
2394
2395 /* slimbus1 */
2396 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2397 { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2398 { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2399 { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2400 { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2401 };
2402
2403 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2404 .name = "slimbus1",
2405 .class = &omap44xx_slimbus_hwmod_class,
2406 .clkdm_name = "abe_clkdm",
2407 .prcm = {
2408 .omap4 = {
2409 .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2410 .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2411 .modulemode = MODULEMODE_SWCTRL,
2412 },
2413 },
2414 .opt_clks = slimbus1_opt_clks,
2415 .opt_clks_cnt = ARRAY_SIZE(slimbus1_opt_clks),
2416 };
2417
2418 /* slimbus2 */
2419 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2420 { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2421 { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2422 { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2423 };
2424
2425 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2426 .name = "slimbus2",
2427 .class = &omap44xx_slimbus_hwmod_class,
2428 .clkdm_name = "l4_per_clkdm",
2429 .prcm = {
2430 .omap4 = {
2431 .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2432 .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2433 .modulemode = MODULEMODE_SWCTRL,
2434 },
2435 },
2436 .opt_clks = slimbus2_opt_clks,
2437 .opt_clks_cnt = ARRAY_SIZE(slimbus2_opt_clks),
2438 };
2439
2440 /*
2441 * 'smartreflex' class
2442 * smartreflex module (monitor silicon performance and outputs a measure of
2443 * performance error)
2444 */
2445
2446 /* The IP is not compliant to type1 / type2 scheme */
2447 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2448 .sidle_shift = 24,
2449 .enwkup_shift = 26,
2450 };
2451
2452 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2453 .sysc_offs = 0x0038,
2454 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2455 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2456 SIDLE_SMART_WKUP),
2457 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
2458 };
2459
2460 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2461 .name = "smartreflex",
2462 .sysc = &omap44xx_smartreflex_sysc,
2463 .rev = 2,
2464 };
2465
2466 /* smartreflex_core */
2467 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2468 .sensor_voltdm_name = "core",
2469 };
2470
2471 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2472 .name = "smartreflex_core",
2473 .class = &omap44xx_smartreflex_hwmod_class,
2474 .clkdm_name = "l4_ao_clkdm",
2475
2476 .main_clk = "smartreflex_core_fck",
2477 .prcm = {
2478 .omap4 = {
2479 .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2480 .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2481 .modulemode = MODULEMODE_SWCTRL,
2482 },
2483 },
2484 .dev_attr = &smartreflex_core_dev_attr,
2485 };
2486
2487 /* smartreflex_iva */
2488 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
2489 .sensor_voltdm_name = "iva",
2490 };
2491
2492 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2493 .name = "smartreflex_iva",
2494 .class = &omap44xx_smartreflex_hwmod_class,
2495 .clkdm_name = "l4_ao_clkdm",
2496 .main_clk = "smartreflex_iva_fck",
2497 .prcm = {
2498 .omap4 = {
2499 .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
2500 .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
2501 .modulemode = MODULEMODE_SWCTRL,
2502 },
2503 },
2504 .dev_attr = &smartreflex_iva_dev_attr,
2505 };
2506
2507 /* smartreflex_mpu */
2508 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2509 .sensor_voltdm_name = "mpu",
2510 };
2511
2512 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
2513 .name = "smartreflex_mpu",
2514 .class = &omap44xx_smartreflex_hwmod_class,
2515 .clkdm_name = "l4_ao_clkdm",
2516 .main_clk = "smartreflex_mpu_fck",
2517 .prcm = {
2518 .omap4 = {
2519 .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
2520 .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
2521 .modulemode = MODULEMODE_SWCTRL,
2522 },
2523 },
2524 .dev_attr = &smartreflex_mpu_dev_attr,
2525 };
2526
2527 /*
2528 * 'spinlock' class
2529 * spinlock provides hardware assistance for synchronizing the processes
2530 * running on multiple processors
2531 */
2532
2533 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
2534 .rev_offs = 0x0000,
2535 .sysc_offs = 0x0010,
2536 .syss_offs = 0x0014,
2537 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2538 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2539 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2540 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2541 .sysc_fields = &omap_hwmod_sysc_type1,
2542 };
2543
2544 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
2545 .name = "spinlock",
2546 .sysc = &omap44xx_spinlock_sysc,
2547 };
2548
2549 /* spinlock */
2550 static struct omap_hwmod omap44xx_spinlock_hwmod = {
2551 .name = "spinlock",
2552 .class = &omap44xx_spinlock_hwmod_class,
2553 .clkdm_name = "l4_cfg_clkdm",
2554 .prcm = {
2555 .omap4 = {
2556 .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
2557 .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
2558 },
2559 },
2560 };
2561
2562 /*
2563 * 'timer' class
2564 * general purpose timer module with accurate 1ms tick
2565 * This class contains several variants: ['timer_1ms', 'timer']
2566 */
2567
2568 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
2569 .rev_offs = 0x0000,
2570 .sysc_offs = 0x0010,
2571 .syss_offs = 0x0014,
2572 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2573 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2574 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2575 SYSS_HAS_RESET_STATUS),
2576 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2577 .clockact = CLOCKACT_TEST_ICLK,
2578 .sysc_fields = &omap_hwmod_sysc_type1,
2579 };
2580
2581 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
2582 .name = "timer",
2583 .sysc = &omap44xx_timer_1ms_sysc,
2584 };
2585
2586 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
2587 .rev_offs = 0x0000,
2588 .sysc_offs = 0x0010,
2589 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2590 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2591 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2592 SIDLE_SMART_WKUP),
2593 .sysc_fields = &omap_hwmod_sysc_type2,
2594 };
2595
2596 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
2597 .name = "timer",
2598 .sysc = &omap44xx_timer_sysc,
2599 };
2600
2601 /* always-on timers dev attribute */
2602 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
2603 .timer_capability = OMAP_TIMER_ALWON,
2604 };
2605
2606 /* pwm timers dev attribute */
2607 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
2608 .timer_capability = OMAP_TIMER_HAS_PWM,
2609 };
2610
2611 /* timers with DSP interrupt dev attribute */
2612 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
2613 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
2614 };
2615
2616 /* pwm timers with DSP interrupt dev attribute */
2617 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
2618 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
2619 };
2620
2621 /* timer1 */
2622 static struct omap_hwmod omap44xx_timer1_hwmod = {
2623 .name = "timer1",
2624 .class = &omap44xx_timer_1ms_hwmod_class,
2625 .clkdm_name = "l4_wkup_clkdm",
2626 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2627 .main_clk = "dmt1_clk_mux",
2628 .prcm = {
2629 .omap4 = {
2630 .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2631 .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
2632 .modulemode = MODULEMODE_SWCTRL,
2633 },
2634 },
2635 .dev_attr = &capability_alwon_dev_attr,
2636 };
2637
2638 /* timer2 */
2639 static struct omap_hwmod omap44xx_timer2_hwmod = {
2640 .name = "timer2",
2641 .class = &omap44xx_timer_1ms_hwmod_class,
2642 .clkdm_name = "l4_per_clkdm",
2643 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2644 .main_clk = "cm2_dm2_mux",
2645 .prcm = {
2646 .omap4 = {
2647 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
2648 .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
2649 .modulemode = MODULEMODE_SWCTRL,
2650 },
2651 },
2652 };
2653
2654 /* timer3 */
2655 static struct omap_hwmod omap44xx_timer3_hwmod = {
2656 .name = "timer3",
2657 .class = &omap44xx_timer_hwmod_class,
2658 .clkdm_name = "l4_per_clkdm",
2659 .main_clk = "cm2_dm3_mux",
2660 .prcm = {
2661 .omap4 = {
2662 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
2663 .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
2664 .modulemode = MODULEMODE_SWCTRL,
2665 },
2666 },
2667 };
2668
2669 /* timer4 */
2670 static struct omap_hwmod omap44xx_timer4_hwmod = {
2671 .name = "timer4",
2672 .class = &omap44xx_timer_hwmod_class,
2673 .clkdm_name = "l4_per_clkdm",
2674 .main_clk = "cm2_dm4_mux",
2675 .prcm = {
2676 .omap4 = {
2677 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
2678 .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
2679 .modulemode = MODULEMODE_SWCTRL,
2680 },
2681 },
2682 };
2683
2684 /* timer5 */
2685 static struct omap_hwmod omap44xx_timer5_hwmod = {
2686 .name = "timer5",
2687 .class = &omap44xx_timer_hwmod_class,
2688 .clkdm_name = "abe_clkdm",
2689 .main_clk = "timer5_sync_mux",
2690 .prcm = {
2691 .omap4 = {
2692 .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
2693 .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
2694 .modulemode = MODULEMODE_SWCTRL,
2695 },
2696 },
2697 .dev_attr = &capability_dsp_dev_attr,
2698 };
2699
2700 /* timer6 */
2701 static struct omap_hwmod omap44xx_timer6_hwmod = {
2702 .name = "timer6",
2703 .class = &omap44xx_timer_hwmod_class,
2704 .clkdm_name = "abe_clkdm",
2705 .main_clk = "timer6_sync_mux",
2706 .prcm = {
2707 .omap4 = {
2708 .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
2709 .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
2710 .modulemode = MODULEMODE_SWCTRL,
2711 },
2712 },
2713 .dev_attr = &capability_dsp_dev_attr,
2714 };
2715
2716 /* timer7 */
2717 static struct omap_hwmod omap44xx_timer7_hwmod = {
2718 .name = "timer7",
2719 .class = &omap44xx_timer_hwmod_class,
2720 .clkdm_name = "abe_clkdm",
2721 .main_clk = "timer7_sync_mux",
2722 .prcm = {
2723 .omap4 = {
2724 .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
2725 .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
2726 .modulemode = MODULEMODE_SWCTRL,
2727 },
2728 },
2729 .dev_attr = &capability_dsp_dev_attr,
2730 };
2731
2732 /* timer8 */
2733 static struct omap_hwmod omap44xx_timer8_hwmod = {
2734 .name = "timer8",
2735 .class = &omap44xx_timer_hwmod_class,
2736 .clkdm_name = "abe_clkdm",
2737 .main_clk = "timer8_sync_mux",
2738 .prcm = {
2739 .omap4 = {
2740 .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
2741 .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
2742 .modulemode = MODULEMODE_SWCTRL,
2743 },
2744 },
2745 .dev_attr = &capability_dsp_pwm_dev_attr,
2746 };
2747
2748 /* timer9 */
2749 static struct omap_hwmod omap44xx_timer9_hwmod = {
2750 .name = "timer9",
2751 .class = &omap44xx_timer_hwmod_class,
2752 .clkdm_name = "l4_per_clkdm",
2753 .main_clk = "cm2_dm9_mux",
2754 .prcm = {
2755 .omap4 = {
2756 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
2757 .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
2758 .modulemode = MODULEMODE_SWCTRL,
2759 },
2760 },
2761 .dev_attr = &capability_pwm_dev_attr,
2762 };
2763
2764 /* timer10 */
2765 static struct omap_hwmod omap44xx_timer10_hwmod = {
2766 .name = "timer10",
2767 .class = &omap44xx_timer_1ms_hwmod_class,
2768 .clkdm_name = "l4_per_clkdm",
2769 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2770 .main_clk = "cm2_dm10_mux",
2771 .prcm = {
2772 .omap4 = {
2773 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
2774 .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
2775 .modulemode = MODULEMODE_SWCTRL,
2776 },
2777 },
2778 .dev_attr = &capability_pwm_dev_attr,
2779 };
2780
2781 /* timer11 */
2782 static struct omap_hwmod omap44xx_timer11_hwmod = {
2783 .name = "timer11",
2784 .class = &omap44xx_timer_hwmod_class,
2785 .clkdm_name = "l4_per_clkdm",
2786 .main_clk = "cm2_dm11_mux",
2787 .prcm = {
2788 .omap4 = {
2789 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
2790 .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
2791 .modulemode = MODULEMODE_SWCTRL,
2792 },
2793 },
2794 .dev_attr = &capability_pwm_dev_attr,
2795 };
2796
2797 /*
2798 * 'uart' class
2799 * universal asynchronous receiver/transmitter (uart)
2800 */
2801
2802 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
2803 .rev_offs = 0x0050,
2804 .sysc_offs = 0x0054,
2805 .syss_offs = 0x0058,
2806 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2807 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2808 SYSS_HAS_RESET_STATUS),
2809 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2810 SIDLE_SMART_WKUP),
2811 .sysc_fields = &omap_hwmod_sysc_type1,
2812 };
2813
2814 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
2815 .name = "uart",
2816 .sysc = &omap44xx_uart_sysc,
2817 };
2818
2819 /* uart1 */
2820 static struct omap_hwmod omap44xx_uart1_hwmod = {
2821 .name = "uart1",
2822 .class = &omap44xx_uart_hwmod_class,
2823 .clkdm_name = "l4_per_clkdm",
2824 .flags = HWMOD_SWSUP_SIDLE_ACT,
2825 .main_clk = "func_48m_fclk",
2826 .prcm = {
2827 .omap4 = {
2828 .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
2829 .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
2830 .modulemode = MODULEMODE_SWCTRL,
2831 },
2832 },
2833 };
2834
2835 /* uart2 */
2836 static struct omap_hwmod omap44xx_uart2_hwmod = {
2837 .name = "uart2",
2838 .class = &omap44xx_uart_hwmod_class,
2839 .clkdm_name = "l4_per_clkdm",
2840 .flags = HWMOD_SWSUP_SIDLE_ACT,
2841 .main_clk = "func_48m_fclk",
2842 .prcm = {
2843 .omap4 = {
2844 .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
2845 .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
2846 .modulemode = MODULEMODE_SWCTRL,
2847 },
2848 },
2849 };
2850
2851 /* uart3 */
2852 static struct omap_hwmod omap44xx_uart3_hwmod = {
2853 .name = "uart3",
2854 .class = &omap44xx_uart_hwmod_class,
2855 .clkdm_name = "l4_per_clkdm",
2856 .flags = DEBUG_OMAP4UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
2857 .main_clk = "func_48m_fclk",
2858 .prcm = {
2859 .omap4 = {
2860 .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
2861 .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
2862 .modulemode = MODULEMODE_SWCTRL,
2863 },
2864 },
2865 };
2866
2867 /* uart4 */
2868 static struct omap_hwmod omap44xx_uart4_hwmod = {
2869 .name = "uart4",
2870 .class = &omap44xx_uart_hwmod_class,
2871 .clkdm_name = "l4_per_clkdm",
2872 .flags = DEBUG_OMAP4UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
2873 .main_clk = "func_48m_fclk",
2874 .prcm = {
2875 .omap4 = {
2876 .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
2877 .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
2878 .modulemode = MODULEMODE_SWCTRL,
2879 },
2880 },
2881 };
2882
2883 /*
2884 * 'usb_host_fs' class
2885 * full-speed usb host controller
2886 */
2887
2888 /* The IP is not compliant to type1 / type2 scheme */
2889 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
2890 .midle_shift = 4,
2891 .sidle_shift = 2,
2892 .srst_shift = 1,
2893 };
2894
2895 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
2896 .rev_offs = 0x0000,
2897 .sysc_offs = 0x0210,
2898 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2899 SYSC_HAS_SOFTRESET),
2900 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2901 SIDLE_SMART_WKUP),
2902 .sysc_fields = &omap_hwmod_sysc_type_usb_host_fs,
2903 };
2904
2905 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
2906 .name = "usb_host_fs",
2907 .sysc = &omap44xx_usb_host_fs_sysc,
2908 };
2909
2910 /* usb_host_fs */
2911 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
2912 .name = "usb_host_fs",
2913 .class = &omap44xx_usb_host_fs_hwmod_class,
2914 .clkdm_name = "l3_init_clkdm",
2915 .main_clk = "usb_host_fs_fck",
2916 .prcm = {
2917 .omap4 = {
2918 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
2919 .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
2920 .modulemode = MODULEMODE_SWCTRL,
2921 },
2922 },
2923 };
2924
2925 /*
2926 * 'usb_host_hs' class
2927 * high-speed multi-port usb host controller
2928 */
2929
2930 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
2931 .rev_offs = 0x0000,
2932 .sysc_offs = 0x0010,
2933 .syss_offs = 0x0014,
2934 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2935 SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS),
2936 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2937 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2938 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2939 .sysc_fields = &omap_hwmod_sysc_type2,
2940 };
2941
2942 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
2943 .name = "usb_host_hs",
2944 .sysc = &omap44xx_usb_host_hs_sysc,
2945 };
2946
2947 /* usb_host_hs */
2948 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
2949 .name = "usb_host_hs",
2950 .class = &omap44xx_usb_host_hs_hwmod_class,
2951 .clkdm_name = "l3_init_clkdm",
2952 .main_clk = "usb_host_hs_fck",
2953 .prcm = {
2954 .omap4 = {
2955 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
2956 .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
2957 .modulemode = MODULEMODE_SWCTRL,
2958 },
2959 },
2960
2961 /*
2962 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
2963 * id: i660
2964 *
2965 * Description:
2966 * In the following configuration :
2967 * - USBHOST module is set to smart-idle mode
2968 * - PRCM asserts idle_req to the USBHOST module ( This typically
2969 * happens when the system is going to a low power mode : all ports
2970 * have been suspended, the master part of the USBHOST module has
2971 * entered the standby state, and SW has cut the functional clocks)
2972 * - an USBHOST interrupt occurs before the module is able to answer
2973 * idle_ack, typically a remote wakeup IRQ.
2974 * Then the USB HOST module will enter a deadlock situation where it
2975 * is no more accessible nor functional.
2976 *
2977 * Workaround:
2978 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
2979 */
2980
2981 /*
2982 * Errata: USB host EHCI may stall when entering smart-standby mode
2983 * Id: i571
2984 *
2985 * Description:
2986 * When the USBHOST module is set to smart-standby mode, and when it is
2987 * ready to enter the standby state (i.e. all ports are suspended and
2988 * all attached devices are in suspend mode), then it can wrongly assert
2989 * the Mstandby signal too early while there are still some residual OCP
2990 * transactions ongoing. If this condition occurs, the internal state
2991 * machine may go to an undefined state and the USB link may be stuck
2992 * upon the next resume.
2993 *
2994 * Workaround:
2995 * Don't use smart standby; use only force standby,
2996 * hence HWMOD_SWSUP_MSTANDBY
2997 */
2998
2999 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3000 };
3001
3002 /*
3003 * 'usb_otg_hs' class
3004 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3005 */
3006
3007 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3008 .rev_offs = 0x0400,
3009 .sysc_offs = 0x0404,
3010 .syss_offs = 0x0408,
3011 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3012 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3013 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3014 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3015 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3016 MSTANDBY_SMART),
3017 .sysc_fields = &omap_hwmod_sysc_type1,
3018 };
3019
3020 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3021 .name = "usb_otg_hs",
3022 .sysc = &omap44xx_usb_otg_hs_sysc,
3023 };
3024
3025 /* usb_otg_hs */
3026 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3027 { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3028 };
3029
3030 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3031 .name = "usb_otg_hs",
3032 .class = &omap44xx_usb_otg_hs_hwmod_class,
3033 .clkdm_name = "l3_init_clkdm",
3034 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3035 .main_clk = "usb_otg_hs_ick",
3036 .prcm = {
3037 .omap4 = {
3038 .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3039 .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3040 .modulemode = MODULEMODE_HWCTRL,
3041 },
3042 },
3043 .opt_clks = usb_otg_hs_opt_clks,
3044 .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
3045 };
3046
3047 /*
3048 * 'usb_tll_hs' class
3049 * usb_tll_hs module is the adapter on the usb_host_hs ports
3050 */
3051
3052 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3053 .rev_offs = 0x0000,
3054 .sysc_offs = 0x0010,
3055 .syss_offs = 0x0014,
3056 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3057 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3058 SYSC_HAS_AUTOIDLE),
3059 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3060 .sysc_fields = &omap_hwmod_sysc_type1,
3061 };
3062
3063 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3064 .name = "usb_tll_hs",
3065 .sysc = &omap44xx_usb_tll_hs_sysc,
3066 };
3067
3068 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3069 .name = "usb_tll_hs",
3070 .class = &omap44xx_usb_tll_hs_hwmod_class,
3071 .clkdm_name = "l3_init_clkdm",
3072 .main_clk = "usb_tll_hs_ick",
3073 .prcm = {
3074 .omap4 = {
3075 .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3076 .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3077 .modulemode = MODULEMODE_HWCTRL,
3078 },
3079 },
3080 };
3081
3082 /*
3083 * 'wd_timer' class
3084 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3085 * overflow condition
3086 */
3087
3088 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3089 .rev_offs = 0x0000,
3090 .sysc_offs = 0x0010,
3091 .syss_offs = 0x0014,
3092 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3093 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3094 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3095 SIDLE_SMART_WKUP),
3096 .sysc_fields = &omap_hwmod_sysc_type1,
3097 };
3098
3099 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3100 .name = "wd_timer",
3101 .sysc = &omap44xx_wd_timer_sysc,
3102 .pre_shutdown = &omap2_wd_timer_disable,
3103 .reset = &omap2_wd_timer_reset,
3104 };
3105
3106 /* wd_timer2 */
3107 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3108 .name = "wd_timer2",
3109 .class = &omap44xx_wd_timer_hwmod_class,
3110 .clkdm_name = "l4_wkup_clkdm",
3111 .main_clk = "sys_32k_ck",
3112 .prcm = {
3113 .omap4 = {
3114 .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3115 .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3116 .modulemode = MODULEMODE_SWCTRL,
3117 },
3118 },
3119 };
3120
3121 /* wd_timer3 */
3122 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3123 .name = "wd_timer3",
3124 .class = &omap44xx_wd_timer_hwmod_class,
3125 .clkdm_name = "abe_clkdm",
3126 .main_clk = "sys_32k_ck",
3127 .prcm = {
3128 .omap4 = {
3129 .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3130 .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3131 .modulemode = MODULEMODE_SWCTRL,
3132 },
3133 },
3134 };
3135
3136
3137 /*
3138 * interfaces
3139 */
3140
3141 /* l3_main_1 -> dmm */
3142 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3143 .master = &omap44xx_l3_main_1_hwmod,
3144 .slave = &omap44xx_dmm_hwmod,
3145 .clk = "l3_div_ck",
3146 .user = OCP_USER_SDMA,
3147 };
3148
3149 /* mpu -> dmm */
3150 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3151 .master = &omap44xx_mpu_hwmod,
3152 .slave = &omap44xx_dmm_hwmod,
3153 .clk = "l3_div_ck",
3154 .user = OCP_USER_MPU,
3155 };
3156
3157 /* iva -> l3_instr */
3158 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3159 .master = &omap44xx_iva_hwmod,
3160 .slave = &omap44xx_l3_instr_hwmod,
3161 .clk = "l3_div_ck",
3162 .user = OCP_USER_MPU | OCP_USER_SDMA,
3163 };
3164
3165 /* l3_main_3 -> l3_instr */
3166 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3167 .master = &omap44xx_l3_main_3_hwmod,
3168 .slave = &omap44xx_l3_instr_hwmod,
3169 .clk = "l3_div_ck",
3170 .user = OCP_USER_MPU | OCP_USER_SDMA,
3171 };
3172
3173 /* ocp_wp_noc -> l3_instr */
3174 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3175 .master = &omap44xx_ocp_wp_noc_hwmod,
3176 .slave = &omap44xx_l3_instr_hwmod,
3177 .clk = "l3_div_ck",
3178 .user = OCP_USER_MPU | OCP_USER_SDMA,
3179 };
3180
3181 /* dsp -> l3_main_1 */
3182 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3183 .master = &omap44xx_dsp_hwmod,
3184 .slave = &omap44xx_l3_main_1_hwmod,
3185 .clk = "l3_div_ck",
3186 .user = OCP_USER_MPU | OCP_USER_SDMA,
3187 };
3188
3189 /* dss -> l3_main_1 */
3190 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3191 .master = &omap44xx_dss_hwmod,
3192 .slave = &omap44xx_l3_main_1_hwmod,
3193 .clk = "l3_div_ck",
3194 .user = OCP_USER_MPU | OCP_USER_SDMA,
3195 };
3196
3197 /* l3_main_2 -> l3_main_1 */
3198 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3199 .master = &omap44xx_l3_main_2_hwmod,
3200 .slave = &omap44xx_l3_main_1_hwmod,
3201 .clk = "l3_div_ck",
3202 .user = OCP_USER_MPU | OCP_USER_SDMA,
3203 };
3204
3205 /* l4_cfg -> l3_main_1 */
3206 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3207 .master = &omap44xx_l4_cfg_hwmod,
3208 .slave = &omap44xx_l3_main_1_hwmod,
3209 .clk = "l4_div_ck",
3210 .user = OCP_USER_MPU | OCP_USER_SDMA,
3211 };
3212
3213 /* mmc1 -> l3_main_1 */
3214 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3215 .master = &omap44xx_mmc1_hwmod,
3216 .slave = &omap44xx_l3_main_1_hwmod,
3217 .clk = "l3_div_ck",
3218 .user = OCP_USER_MPU | OCP_USER_SDMA,
3219 };
3220
3221 /* mmc2 -> l3_main_1 */
3222 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3223 .master = &omap44xx_mmc2_hwmod,
3224 .slave = &omap44xx_l3_main_1_hwmod,
3225 .clk = "l3_div_ck",
3226 .user = OCP_USER_MPU | OCP_USER_SDMA,
3227 };
3228
3229 /* mpu -> l3_main_1 */
3230 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3231 .master = &omap44xx_mpu_hwmod,
3232 .slave = &omap44xx_l3_main_1_hwmod,
3233 .clk = "l3_div_ck",
3234 .user = OCP_USER_MPU,
3235 };
3236
3237 /* debugss -> l3_main_2 */
3238 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
3239 .master = &omap44xx_debugss_hwmod,
3240 .slave = &omap44xx_l3_main_2_hwmod,
3241 .clk = "dbgclk_mux_ck",
3242 .user = OCP_USER_MPU | OCP_USER_SDMA,
3243 };
3244
3245 /* dma_system -> l3_main_2 */
3246 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
3247 .master = &omap44xx_dma_system_hwmod,
3248 .slave = &omap44xx_l3_main_2_hwmod,
3249 .clk = "l3_div_ck",
3250 .user = OCP_USER_MPU | OCP_USER_SDMA,
3251 };
3252
3253 /* fdif -> l3_main_2 */
3254 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3255 .master = &omap44xx_fdif_hwmod,
3256 .slave = &omap44xx_l3_main_2_hwmod,
3257 .clk = "l3_div_ck",
3258 .user = OCP_USER_MPU | OCP_USER_SDMA,
3259 };
3260
3261 /* gpu -> l3_main_2 */
3262 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
3263 .master = &omap44xx_gpu_hwmod,
3264 .slave = &omap44xx_l3_main_2_hwmod,
3265 .clk = "l3_div_ck",
3266 .user = OCP_USER_MPU | OCP_USER_SDMA,
3267 };
3268
3269 /* hsi -> l3_main_2 */
3270 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
3271 .master = &omap44xx_hsi_hwmod,
3272 .slave = &omap44xx_l3_main_2_hwmod,
3273 .clk = "l3_div_ck",
3274 .user = OCP_USER_MPU | OCP_USER_SDMA,
3275 };
3276
3277 /* ipu -> l3_main_2 */
3278 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
3279 .master = &omap44xx_ipu_hwmod,
3280 .slave = &omap44xx_l3_main_2_hwmod,
3281 .clk = "l3_div_ck",
3282 .user = OCP_USER_MPU | OCP_USER_SDMA,
3283 };
3284
3285 /* iss -> l3_main_2 */
3286 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
3287 .master = &omap44xx_iss_hwmod,
3288 .slave = &omap44xx_l3_main_2_hwmod,
3289 .clk = "l3_div_ck",
3290 .user = OCP_USER_MPU | OCP_USER_SDMA,
3291 };
3292
3293 /* iva -> l3_main_2 */
3294 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
3295 .master = &omap44xx_iva_hwmod,
3296 .slave = &omap44xx_l3_main_2_hwmod,
3297 .clk = "l3_div_ck",
3298 .user = OCP_USER_MPU | OCP_USER_SDMA,
3299 };
3300
3301 /* l3_main_1 -> l3_main_2 */
3302 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
3303 .master = &omap44xx_l3_main_1_hwmod,
3304 .slave = &omap44xx_l3_main_2_hwmod,
3305 .clk = "l3_div_ck",
3306 .user = OCP_USER_MPU,
3307 };
3308
3309 /* l4_cfg -> l3_main_2 */
3310 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
3311 .master = &omap44xx_l4_cfg_hwmod,
3312 .slave = &omap44xx_l3_main_2_hwmod,
3313 .clk = "l4_div_ck",
3314 .user = OCP_USER_MPU | OCP_USER_SDMA,
3315 };
3316
3317 /* usb_host_fs -> l3_main_2 */
3318 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
3319 .master = &omap44xx_usb_host_fs_hwmod,
3320 .slave = &omap44xx_l3_main_2_hwmod,
3321 .clk = "l3_div_ck",
3322 .user = OCP_USER_MPU | OCP_USER_SDMA,
3323 };
3324
3325 /* usb_host_hs -> l3_main_2 */
3326 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
3327 .master = &omap44xx_usb_host_hs_hwmod,
3328 .slave = &omap44xx_l3_main_2_hwmod,
3329 .clk = "l3_div_ck",
3330 .user = OCP_USER_MPU | OCP_USER_SDMA,
3331 };
3332
3333 /* usb_otg_hs -> l3_main_2 */
3334 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
3335 .master = &omap44xx_usb_otg_hs_hwmod,
3336 .slave = &omap44xx_l3_main_2_hwmod,
3337 .clk = "l3_div_ck",
3338 .user = OCP_USER_MPU | OCP_USER_SDMA,
3339 };
3340
3341 /* l3_main_1 -> l3_main_3 */
3342 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
3343 .master = &omap44xx_l3_main_1_hwmod,
3344 .slave = &omap44xx_l3_main_3_hwmod,
3345 .clk = "l3_div_ck",
3346 .user = OCP_USER_MPU,
3347 };
3348
3349 /* l3_main_2 -> l3_main_3 */
3350 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
3351 .master = &omap44xx_l3_main_2_hwmod,
3352 .slave = &omap44xx_l3_main_3_hwmod,
3353 .clk = "l3_div_ck",
3354 .user = OCP_USER_MPU | OCP_USER_SDMA,
3355 };
3356
3357 /* l4_cfg -> l3_main_3 */
3358 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
3359 .master = &omap44xx_l4_cfg_hwmod,
3360 .slave = &omap44xx_l3_main_3_hwmod,
3361 .clk = "l4_div_ck",
3362 .user = OCP_USER_MPU | OCP_USER_SDMA,
3363 };
3364
3365 /* aess -> l4_abe */
3366 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
3367 .master = &omap44xx_aess_hwmod,
3368 .slave = &omap44xx_l4_abe_hwmod,
3369 .clk = "ocp_abe_iclk",
3370 .user = OCP_USER_MPU | OCP_USER_SDMA,
3371 };
3372
3373 /* dsp -> l4_abe */
3374 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
3375 .master = &omap44xx_dsp_hwmod,
3376 .slave = &omap44xx_l4_abe_hwmod,
3377 .clk = "ocp_abe_iclk",
3378 .user = OCP_USER_MPU | OCP_USER_SDMA,
3379 };
3380
3381 /* l3_main_1 -> l4_abe */
3382 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
3383 .master = &omap44xx_l3_main_1_hwmod,
3384 .slave = &omap44xx_l4_abe_hwmod,
3385 .clk = "l3_div_ck",
3386 .user = OCP_USER_MPU | OCP_USER_SDMA,
3387 };
3388
3389 /* mpu -> l4_abe */
3390 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
3391 .master = &omap44xx_mpu_hwmod,
3392 .slave = &omap44xx_l4_abe_hwmod,
3393 .clk = "ocp_abe_iclk",
3394 .user = OCP_USER_MPU | OCP_USER_SDMA,
3395 };
3396
3397 /* l3_main_1 -> l4_cfg */
3398 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
3399 .master = &omap44xx_l3_main_1_hwmod,
3400 .slave = &omap44xx_l4_cfg_hwmod,
3401 .clk = "l3_div_ck",
3402 .user = OCP_USER_MPU | OCP_USER_SDMA,
3403 };
3404
3405 /* l3_main_2 -> l4_per */
3406 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
3407 .master = &omap44xx_l3_main_2_hwmod,
3408 .slave = &omap44xx_l4_per_hwmod,
3409 .clk = "l3_div_ck",
3410 .user = OCP_USER_MPU | OCP_USER_SDMA,
3411 };
3412
3413 /* l4_cfg -> l4_wkup */
3414 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
3415 .master = &omap44xx_l4_cfg_hwmod,
3416 .slave = &omap44xx_l4_wkup_hwmod,
3417 .clk = "l4_div_ck",
3418 .user = OCP_USER_MPU | OCP_USER_SDMA,
3419 };
3420
3421 /* mpu -> mpu_private */
3422 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
3423 .master = &omap44xx_mpu_hwmod,
3424 .slave = &omap44xx_mpu_private_hwmod,
3425 .clk = "l3_div_ck",
3426 .user = OCP_USER_MPU | OCP_USER_SDMA,
3427 };
3428
3429 /* l4_cfg -> ocp_wp_noc */
3430 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
3431 .master = &omap44xx_l4_cfg_hwmod,
3432 .slave = &omap44xx_ocp_wp_noc_hwmod,
3433 .clk = "l4_div_ck",
3434 .user = OCP_USER_MPU | OCP_USER_SDMA,
3435 };
3436
3437 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
3438 {
3439 .name = "dmem",
3440 .pa_start = 0x40180000,
3441 .pa_end = 0x4018ffff
3442 },
3443 {
3444 .name = "cmem",
3445 .pa_start = 0x401a0000,
3446 .pa_end = 0x401a1fff
3447 },
3448 {
3449 .name = "smem",
3450 .pa_start = 0x401c0000,
3451 .pa_end = 0x401c5fff
3452 },
3453 {
3454 .name = "pmem",
3455 .pa_start = 0x401e0000,
3456 .pa_end = 0x401e1fff
3457 },
3458 {
3459 .name = "mpu",
3460 .pa_start = 0x401f1000,
3461 .pa_end = 0x401f13ff,
3462 .flags = ADDR_TYPE_RT
3463 },
3464 { }
3465 };
3466
3467 /* l4_abe -> aess */
3468 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
3469 .master = &omap44xx_l4_abe_hwmod,
3470 .slave = &omap44xx_aess_hwmod,
3471 .clk = "ocp_abe_iclk",
3472 .addr = omap44xx_aess_addrs,
3473 .user = OCP_USER_MPU,
3474 };
3475
3476 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
3477 {
3478 .name = "dmem_dma",
3479 .pa_start = 0x49080000,
3480 .pa_end = 0x4908ffff
3481 },
3482 {
3483 .name = "cmem_dma",
3484 .pa_start = 0x490a0000,
3485 .pa_end = 0x490a1fff
3486 },
3487 {
3488 .name = "smem_dma",
3489 .pa_start = 0x490c0000,
3490 .pa_end = 0x490c5fff
3491 },
3492 {
3493 .name = "pmem_dma",
3494 .pa_start = 0x490e0000,
3495 .pa_end = 0x490e1fff
3496 },
3497 {
3498 .name = "dma",
3499 .pa_start = 0x490f1000,
3500 .pa_end = 0x490f13ff,
3501 .flags = ADDR_TYPE_RT
3502 },
3503 { }
3504 };
3505
3506 /* l4_abe -> aess (dma) */
3507 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
3508 .master = &omap44xx_l4_abe_hwmod,
3509 .slave = &omap44xx_aess_hwmod,
3510 .clk = "ocp_abe_iclk",
3511 .addr = omap44xx_aess_dma_addrs,
3512 .user = OCP_USER_SDMA,
3513 };
3514
3515 /* l3_main_2 -> c2c */
3516 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
3517 .master = &omap44xx_l3_main_2_hwmod,
3518 .slave = &omap44xx_c2c_hwmod,
3519 .clk = "l3_div_ck",
3520 .user = OCP_USER_MPU | OCP_USER_SDMA,
3521 };
3522
3523 /* l4_wkup -> counter_32k */
3524 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
3525 .master = &omap44xx_l4_wkup_hwmod,
3526 .slave = &omap44xx_counter_32k_hwmod,
3527 .clk = "l4_wkup_clk_mux_ck",
3528 .user = OCP_USER_MPU | OCP_USER_SDMA,
3529 };
3530
3531 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
3532 {
3533 .pa_start = 0x4a002000,
3534 .pa_end = 0x4a0027ff,
3535 .flags = ADDR_TYPE_RT
3536 },
3537 { }
3538 };
3539
3540 /* l4_cfg -> ctrl_module_core */
3541 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
3542 .master = &omap44xx_l4_cfg_hwmod,
3543 .slave = &omap44xx_ctrl_module_core_hwmod,
3544 .clk = "l4_div_ck",
3545 .addr = omap44xx_ctrl_module_core_addrs,
3546 .user = OCP_USER_MPU | OCP_USER_SDMA,
3547 };
3548
3549 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
3550 {
3551 .pa_start = 0x4a100000,
3552 .pa_end = 0x4a1007ff,
3553 .flags = ADDR_TYPE_RT
3554 },
3555 { }
3556 };
3557
3558 /* l4_cfg -> ctrl_module_pad_core */
3559 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
3560 .master = &omap44xx_l4_cfg_hwmod,
3561 .slave = &omap44xx_ctrl_module_pad_core_hwmod,
3562 .clk = "l4_div_ck",
3563 .addr = omap44xx_ctrl_module_pad_core_addrs,
3564 .user = OCP_USER_MPU | OCP_USER_SDMA,
3565 };
3566
3567 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
3568 {
3569 .pa_start = 0x4a30c000,
3570 .pa_end = 0x4a30c7ff,
3571 .flags = ADDR_TYPE_RT
3572 },
3573 { }
3574 };
3575
3576 /* l4_wkup -> ctrl_module_wkup */
3577 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
3578 .master = &omap44xx_l4_wkup_hwmod,
3579 .slave = &omap44xx_ctrl_module_wkup_hwmod,
3580 .clk = "l4_wkup_clk_mux_ck",
3581 .addr = omap44xx_ctrl_module_wkup_addrs,
3582 .user = OCP_USER_MPU | OCP_USER_SDMA,
3583 };
3584
3585 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
3586 {
3587 .pa_start = 0x4a31e000,
3588 .pa_end = 0x4a31e7ff,
3589 .flags = ADDR_TYPE_RT
3590 },
3591 { }
3592 };
3593
3594 /* l4_wkup -> ctrl_module_pad_wkup */
3595 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
3596 .master = &omap44xx_l4_wkup_hwmod,
3597 .slave = &omap44xx_ctrl_module_pad_wkup_hwmod,
3598 .clk = "l4_wkup_clk_mux_ck",
3599 .addr = omap44xx_ctrl_module_pad_wkup_addrs,
3600 .user = OCP_USER_MPU | OCP_USER_SDMA,
3601 };
3602
3603 /* l3_instr -> debugss */
3604 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
3605 .master = &omap44xx_l3_instr_hwmod,
3606 .slave = &omap44xx_debugss_hwmod,
3607 .clk = "l3_div_ck",
3608 .user = OCP_USER_MPU | OCP_USER_SDMA,
3609 };
3610
3611 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
3612 {
3613 .pa_start = 0x4a056000,
3614 .pa_end = 0x4a056fff,
3615 .flags = ADDR_TYPE_RT
3616 },
3617 { }
3618 };
3619
3620 /* l4_cfg -> dma_system */
3621 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
3622 .master = &omap44xx_l4_cfg_hwmod,
3623 .slave = &omap44xx_dma_system_hwmod,
3624 .clk = "l4_div_ck",
3625 .addr = omap44xx_dma_system_addrs,
3626 .user = OCP_USER_MPU | OCP_USER_SDMA,
3627 };
3628
3629 /* l4_abe -> dmic */
3630 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
3631 .master = &omap44xx_l4_abe_hwmod,
3632 .slave = &omap44xx_dmic_hwmod,
3633 .clk = "ocp_abe_iclk",
3634 .user = OCP_USER_MPU | OCP_USER_SDMA,
3635 };
3636
3637 /* dsp -> iva */
3638 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
3639 .master = &omap44xx_dsp_hwmod,
3640 .slave = &omap44xx_iva_hwmod,
3641 .clk = "dpll_iva_m5x2_ck",
3642 .user = OCP_USER_DSP,
3643 };
3644
3645 /* dsp -> sl2if */
3646 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
3647 .master = &omap44xx_dsp_hwmod,
3648 .slave = &omap44xx_sl2if_hwmod,
3649 .clk = "dpll_iva_m5x2_ck",
3650 .user = OCP_USER_DSP,
3651 };
3652
3653 /* l4_cfg -> dsp */
3654 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
3655 .master = &omap44xx_l4_cfg_hwmod,
3656 .slave = &omap44xx_dsp_hwmod,
3657 .clk = "l4_div_ck",
3658 .user = OCP_USER_MPU | OCP_USER_SDMA,
3659 };
3660
3661 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
3662 {
3663 .pa_start = 0x58000000,
3664 .pa_end = 0x5800007f,
3665 .flags = ADDR_TYPE_RT
3666 },
3667 { }
3668 };
3669
3670 /* l3_main_2 -> dss */
3671 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
3672 .master = &omap44xx_l3_main_2_hwmod,
3673 .slave = &omap44xx_dss_hwmod,
3674 .clk = "dss_fck",
3675 .addr = omap44xx_dss_dma_addrs,
3676 .user = OCP_USER_SDMA,
3677 };
3678
3679 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
3680 {
3681 .pa_start = 0x48040000,
3682 .pa_end = 0x4804007f,
3683 .flags = ADDR_TYPE_RT
3684 },
3685 { }
3686 };
3687
3688 /* l4_per -> dss */
3689 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
3690 .master = &omap44xx_l4_per_hwmod,
3691 .slave = &omap44xx_dss_hwmod,
3692 .clk = "l4_div_ck",
3693 .addr = omap44xx_dss_addrs,
3694 .user = OCP_USER_MPU,
3695 };
3696
3697 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
3698 {
3699 .pa_start = 0x58001000,
3700 .pa_end = 0x58001fff,
3701 .flags = ADDR_TYPE_RT
3702 },
3703 { }
3704 };
3705
3706 /* l3_main_2 -> dss_dispc */
3707 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
3708 .master = &omap44xx_l3_main_2_hwmod,
3709 .slave = &omap44xx_dss_dispc_hwmod,
3710 .clk = "dss_fck",
3711 .addr = omap44xx_dss_dispc_dma_addrs,
3712 .user = OCP_USER_SDMA,
3713 };
3714
3715 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
3716 {
3717 .pa_start = 0x48041000,
3718 .pa_end = 0x48041fff,
3719 .flags = ADDR_TYPE_RT
3720 },
3721 { }
3722 };
3723
3724 /* l4_per -> dss_dispc */
3725 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
3726 .master = &omap44xx_l4_per_hwmod,
3727 .slave = &omap44xx_dss_dispc_hwmod,
3728 .clk = "l4_div_ck",
3729 .addr = omap44xx_dss_dispc_addrs,
3730 .user = OCP_USER_MPU,
3731 };
3732
3733 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
3734 {
3735 .pa_start = 0x58004000,
3736 .pa_end = 0x580041ff,
3737 .flags = ADDR_TYPE_RT
3738 },
3739 { }
3740 };
3741
3742 /* l3_main_2 -> dss_dsi1 */
3743 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
3744 .master = &omap44xx_l3_main_2_hwmod,
3745 .slave = &omap44xx_dss_dsi1_hwmod,
3746 .clk = "dss_fck",
3747 .addr = omap44xx_dss_dsi1_dma_addrs,
3748 .user = OCP_USER_SDMA,
3749 };
3750
3751 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
3752 {
3753 .pa_start = 0x48044000,
3754 .pa_end = 0x480441ff,
3755 .flags = ADDR_TYPE_RT
3756 },
3757 { }
3758 };
3759
3760 /* l4_per -> dss_dsi1 */
3761 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
3762 .master = &omap44xx_l4_per_hwmod,
3763 .slave = &omap44xx_dss_dsi1_hwmod,
3764 .clk = "l4_div_ck",
3765 .addr = omap44xx_dss_dsi1_addrs,
3766 .user = OCP_USER_MPU,
3767 };
3768
3769 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
3770 {
3771 .pa_start = 0x58005000,
3772 .pa_end = 0x580051ff,
3773 .flags = ADDR_TYPE_RT
3774 },
3775 { }
3776 };
3777
3778 /* l3_main_2 -> dss_dsi2 */
3779 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
3780 .master = &omap44xx_l3_main_2_hwmod,
3781 .slave = &omap44xx_dss_dsi2_hwmod,
3782 .clk = "dss_fck",
3783 .addr = omap44xx_dss_dsi2_dma_addrs,
3784 .user = OCP_USER_SDMA,
3785 };
3786
3787 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
3788 {
3789 .pa_start = 0x48045000,
3790 .pa_end = 0x480451ff,
3791 .flags = ADDR_TYPE_RT
3792 },
3793 { }
3794 };
3795
3796 /* l4_per -> dss_dsi2 */
3797 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
3798 .master = &omap44xx_l4_per_hwmod,
3799 .slave = &omap44xx_dss_dsi2_hwmod,
3800 .clk = "l4_div_ck",
3801 .addr = omap44xx_dss_dsi2_addrs,
3802 .user = OCP_USER_MPU,
3803 };
3804
3805 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
3806 {
3807 .pa_start = 0x58006000,
3808 .pa_end = 0x58006fff,
3809 .flags = ADDR_TYPE_RT
3810 },
3811 { }
3812 };
3813
3814 /* l3_main_2 -> dss_hdmi */
3815 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
3816 .master = &omap44xx_l3_main_2_hwmod,
3817 .slave = &omap44xx_dss_hdmi_hwmod,
3818 .clk = "dss_fck",
3819 .addr = omap44xx_dss_hdmi_dma_addrs,
3820 .user = OCP_USER_SDMA,
3821 };
3822
3823 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
3824 {
3825 .pa_start = 0x48046000,
3826 .pa_end = 0x48046fff,
3827 .flags = ADDR_TYPE_RT
3828 },
3829 { }
3830 };
3831
3832 /* l4_per -> dss_hdmi */
3833 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
3834 .master = &omap44xx_l4_per_hwmod,
3835 .slave = &omap44xx_dss_hdmi_hwmod,
3836 .clk = "l4_div_ck",
3837 .addr = omap44xx_dss_hdmi_addrs,
3838 .user = OCP_USER_MPU,
3839 };
3840
3841 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
3842 {
3843 .pa_start = 0x58002000,
3844 .pa_end = 0x580020ff,
3845 .flags = ADDR_TYPE_RT
3846 },
3847 { }
3848 };
3849
3850 /* l3_main_2 -> dss_rfbi */
3851 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
3852 .master = &omap44xx_l3_main_2_hwmod,
3853 .slave = &omap44xx_dss_rfbi_hwmod,
3854 .clk = "dss_fck",
3855 .addr = omap44xx_dss_rfbi_dma_addrs,
3856 .user = OCP_USER_SDMA,
3857 };
3858
3859 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
3860 {
3861 .pa_start = 0x48042000,
3862 .pa_end = 0x480420ff,
3863 .flags = ADDR_TYPE_RT
3864 },
3865 { }
3866 };
3867
3868 /* l4_per -> dss_rfbi */
3869 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
3870 .master = &omap44xx_l4_per_hwmod,
3871 .slave = &omap44xx_dss_rfbi_hwmod,
3872 .clk = "l4_div_ck",
3873 .addr = omap44xx_dss_rfbi_addrs,
3874 .user = OCP_USER_MPU,
3875 };
3876
3877 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
3878 {
3879 .pa_start = 0x58003000,
3880 .pa_end = 0x580030ff,
3881 .flags = ADDR_TYPE_RT
3882 },
3883 { }
3884 };
3885
3886 /* l3_main_2 -> dss_venc */
3887 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
3888 .master = &omap44xx_l3_main_2_hwmod,
3889 .slave = &omap44xx_dss_venc_hwmod,
3890 .clk = "dss_fck",
3891 .addr = omap44xx_dss_venc_dma_addrs,
3892 .user = OCP_USER_SDMA,
3893 };
3894
3895 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
3896 {
3897 .pa_start = 0x48043000,
3898 .pa_end = 0x480430ff,
3899 .flags = ADDR_TYPE_RT
3900 },
3901 { }
3902 };
3903
3904 /* l4_per -> dss_venc */
3905 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
3906 .master = &omap44xx_l4_per_hwmod,
3907 .slave = &omap44xx_dss_venc_hwmod,
3908 .clk = "l4_div_ck",
3909 .addr = omap44xx_dss_venc_addrs,
3910 .user = OCP_USER_MPU,
3911 };
3912
3913 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
3914 {
3915 .pa_start = 0x48078000,
3916 .pa_end = 0x48078fff,
3917 .flags = ADDR_TYPE_RT
3918 },
3919 { }
3920 };
3921
3922 /* l4_per -> elm */
3923 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
3924 .master = &omap44xx_l4_per_hwmod,
3925 .slave = &omap44xx_elm_hwmod,
3926 .clk = "l4_div_ck",
3927 .addr = omap44xx_elm_addrs,
3928 .user = OCP_USER_MPU | OCP_USER_SDMA,
3929 };
3930
3931 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
3932 {
3933 .pa_start = 0x4a10a000,
3934 .pa_end = 0x4a10a1ff,
3935 .flags = ADDR_TYPE_RT
3936 },
3937 { }
3938 };
3939
3940 /* l4_cfg -> fdif */
3941 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
3942 .master = &omap44xx_l4_cfg_hwmod,
3943 .slave = &omap44xx_fdif_hwmod,
3944 .clk = "l4_div_ck",
3945 .addr = omap44xx_fdif_addrs,
3946 .user = OCP_USER_MPU | OCP_USER_SDMA,
3947 };
3948
3949 /* l4_wkup -> gpio1 */
3950 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
3951 .master = &omap44xx_l4_wkup_hwmod,
3952 .slave = &omap44xx_gpio1_hwmod,
3953 .clk = "l4_wkup_clk_mux_ck",
3954 .user = OCP_USER_MPU | OCP_USER_SDMA,
3955 };
3956
3957 /* l4_per -> gpio2 */
3958 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
3959 .master = &omap44xx_l4_per_hwmod,
3960 .slave = &omap44xx_gpio2_hwmod,
3961 .clk = "l4_div_ck",
3962 .user = OCP_USER_MPU | OCP_USER_SDMA,
3963 };
3964
3965 /* l4_per -> gpio3 */
3966 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
3967 .master = &omap44xx_l4_per_hwmod,
3968 .slave = &omap44xx_gpio3_hwmod,
3969 .clk = "l4_div_ck",
3970 .user = OCP_USER_MPU | OCP_USER_SDMA,
3971 };
3972
3973 /* l4_per -> gpio4 */
3974 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
3975 .master = &omap44xx_l4_per_hwmod,
3976 .slave = &omap44xx_gpio4_hwmod,
3977 .clk = "l4_div_ck",
3978 .user = OCP_USER_MPU | OCP_USER_SDMA,
3979 };
3980
3981 /* l4_per -> gpio5 */
3982 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
3983 .master = &omap44xx_l4_per_hwmod,
3984 .slave = &omap44xx_gpio5_hwmod,
3985 .clk = "l4_div_ck",
3986 .user = OCP_USER_MPU | OCP_USER_SDMA,
3987 };
3988
3989 /* l4_per -> gpio6 */
3990 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
3991 .master = &omap44xx_l4_per_hwmod,
3992 .slave = &omap44xx_gpio6_hwmod,
3993 .clk = "l4_div_ck",
3994 .user = OCP_USER_MPU | OCP_USER_SDMA,
3995 };
3996
3997 /* l3_main_2 -> gpmc */
3998 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
3999 .master = &omap44xx_l3_main_2_hwmod,
4000 .slave = &omap44xx_gpmc_hwmod,
4001 .clk = "l3_div_ck",
4002 .user = OCP_USER_MPU | OCP_USER_SDMA,
4003 };
4004
4005 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4006 {
4007 .pa_start = 0x56000000,
4008 .pa_end = 0x5600ffff,
4009 .flags = ADDR_TYPE_RT
4010 },
4011 { }
4012 };
4013
4014 /* l3_main_2 -> gpu */
4015 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4016 .master = &omap44xx_l3_main_2_hwmod,
4017 .slave = &omap44xx_gpu_hwmod,
4018 .clk = "l3_div_ck",
4019 .addr = omap44xx_gpu_addrs,
4020 .user = OCP_USER_MPU | OCP_USER_SDMA,
4021 };
4022
4023 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4024 {
4025 .pa_start = 0x480b2000,
4026 .pa_end = 0x480b201f,
4027 .flags = ADDR_TYPE_RT
4028 },
4029 { }
4030 };
4031
4032 /* l4_per -> hdq1w */
4033 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4034 .master = &omap44xx_l4_per_hwmod,
4035 .slave = &omap44xx_hdq1w_hwmod,
4036 .clk = "l4_div_ck",
4037 .addr = omap44xx_hdq1w_addrs,
4038 .user = OCP_USER_MPU | OCP_USER_SDMA,
4039 };
4040
4041 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4042 {
4043 .pa_start = 0x4a058000,
4044 .pa_end = 0x4a05bfff,
4045 .flags = ADDR_TYPE_RT
4046 },
4047 { }
4048 };
4049
4050 /* l4_cfg -> hsi */
4051 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4052 .master = &omap44xx_l4_cfg_hwmod,
4053 .slave = &omap44xx_hsi_hwmod,
4054 .clk = "l4_div_ck",
4055 .addr = omap44xx_hsi_addrs,
4056 .user = OCP_USER_MPU | OCP_USER_SDMA,
4057 };
4058
4059 /* l4_per -> i2c1 */
4060 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4061 .master = &omap44xx_l4_per_hwmod,
4062 .slave = &omap44xx_i2c1_hwmod,
4063 .clk = "l4_div_ck",
4064 .user = OCP_USER_MPU | OCP_USER_SDMA,
4065 };
4066
4067 /* l4_per -> i2c2 */
4068 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
4069 .master = &omap44xx_l4_per_hwmod,
4070 .slave = &omap44xx_i2c2_hwmod,
4071 .clk = "l4_div_ck",
4072 .user = OCP_USER_MPU | OCP_USER_SDMA,
4073 };
4074
4075 /* l4_per -> i2c3 */
4076 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
4077 .master = &omap44xx_l4_per_hwmod,
4078 .slave = &omap44xx_i2c3_hwmod,
4079 .clk = "l4_div_ck",
4080 .user = OCP_USER_MPU | OCP_USER_SDMA,
4081 };
4082
4083 /* l4_per -> i2c4 */
4084 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
4085 .master = &omap44xx_l4_per_hwmod,
4086 .slave = &omap44xx_i2c4_hwmod,
4087 .clk = "l4_div_ck",
4088 .user = OCP_USER_MPU | OCP_USER_SDMA,
4089 };
4090
4091 /* l3_main_2 -> ipu */
4092 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
4093 .master = &omap44xx_l3_main_2_hwmod,
4094 .slave = &omap44xx_ipu_hwmod,
4095 .clk = "l3_div_ck",
4096 .user = OCP_USER_MPU | OCP_USER_SDMA,
4097 };
4098
4099 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
4100 {
4101 .pa_start = 0x52000000,
4102 .pa_end = 0x520000ff,
4103 .flags = ADDR_TYPE_RT
4104 },
4105 { }
4106 };
4107
4108 /* l3_main_2 -> iss */
4109 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
4110 .master = &omap44xx_l3_main_2_hwmod,
4111 .slave = &omap44xx_iss_hwmod,
4112 .clk = "l3_div_ck",
4113 .addr = omap44xx_iss_addrs,
4114 .user = OCP_USER_MPU | OCP_USER_SDMA,
4115 };
4116
4117 /* iva -> sl2if */
4118 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
4119 .master = &omap44xx_iva_hwmod,
4120 .slave = &omap44xx_sl2if_hwmod,
4121 .clk = "dpll_iva_m5x2_ck",
4122 .user = OCP_USER_IVA,
4123 };
4124
4125 /* l3_main_2 -> iva */
4126 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
4127 .master = &omap44xx_l3_main_2_hwmod,
4128 .slave = &omap44xx_iva_hwmod,
4129 .clk = "l3_div_ck",
4130 .user = OCP_USER_MPU,
4131 };
4132
4133 /* l4_wkup -> kbd */
4134 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
4135 .master = &omap44xx_l4_wkup_hwmod,
4136 .slave = &omap44xx_kbd_hwmod,
4137 .clk = "l4_wkup_clk_mux_ck",
4138 .user = OCP_USER_MPU | OCP_USER_SDMA,
4139 };
4140
4141 /* l4_cfg -> mailbox */
4142 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
4143 .master = &omap44xx_l4_cfg_hwmod,
4144 .slave = &omap44xx_mailbox_hwmod,
4145 .clk = "l4_div_ck",
4146 .user = OCP_USER_MPU | OCP_USER_SDMA,
4147 };
4148
4149 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
4150 {
4151 .pa_start = 0x40128000,
4152 .pa_end = 0x401283ff,
4153 .flags = ADDR_TYPE_RT
4154 },
4155 { }
4156 };
4157
4158 /* l4_abe -> mcasp */
4159 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
4160 .master = &omap44xx_l4_abe_hwmod,
4161 .slave = &omap44xx_mcasp_hwmod,
4162 .clk = "ocp_abe_iclk",
4163 .addr = omap44xx_mcasp_addrs,
4164 .user = OCP_USER_MPU,
4165 };
4166
4167 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
4168 {
4169 .pa_start = 0x49028000,
4170 .pa_end = 0x490283ff,
4171 .flags = ADDR_TYPE_RT
4172 },
4173 { }
4174 };
4175
4176 /* l4_abe -> mcasp (dma) */
4177 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
4178 .master = &omap44xx_l4_abe_hwmod,
4179 .slave = &omap44xx_mcasp_hwmod,
4180 .clk = "ocp_abe_iclk",
4181 .addr = omap44xx_mcasp_dma_addrs,
4182 .user = OCP_USER_SDMA,
4183 };
4184
4185 /* l4_abe -> mcbsp1 */
4186 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
4187 .master = &omap44xx_l4_abe_hwmod,
4188 .slave = &omap44xx_mcbsp1_hwmod,
4189 .clk = "ocp_abe_iclk",
4190 .user = OCP_USER_MPU | OCP_USER_SDMA,
4191 };
4192
4193 /* l4_abe -> mcbsp2 */
4194 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
4195 .master = &omap44xx_l4_abe_hwmod,
4196 .slave = &omap44xx_mcbsp2_hwmod,
4197 .clk = "ocp_abe_iclk",
4198 .user = OCP_USER_MPU | OCP_USER_SDMA,
4199 };
4200
4201 /* l4_abe -> mcbsp3 */
4202 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
4203 .master = &omap44xx_l4_abe_hwmod,
4204 .slave = &omap44xx_mcbsp3_hwmod,
4205 .clk = "ocp_abe_iclk",
4206 .user = OCP_USER_MPU | OCP_USER_SDMA,
4207 };
4208
4209 /* l4_per -> mcbsp4 */
4210 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
4211 .master = &omap44xx_l4_per_hwmod,
4212 .slave = &omap44xx_mcbsp4_hwmod,
4213 .clk = "l4_div_ck",
4214 .user = OCP_USER_MPU | OCP_USER_SDMA,
4215 };
4216
4217 /* l4_abe -> mcpdm */
4218 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
4219 .master = &omap44xx_l4_abe_hwmod,
4220 .slave = &omap44xx_mcpdm_hwmod,
4221 .clk = "ocp_abe_iclk",
4222 .user = OCP_USER_MPU | OCP_USER_SDMA,
4223 };
4224
4225 /* l4_per -> mcspi1 */
4226 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
4227 .master = &omap44xx_l4_per_hwmod,
4228 .slave = &omap44xx_mcspi1_hwmod,
4229 .clk = "l4_div_ck",
4230 .user = OCP_USER_MPU | OCP_USER_SDMA,
4231 };
4232
4233 /* l4_per -> mcspi2 */
4234 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
4235 .master = &omap44xx_l4_per_hwmod,
4236 .slave = &omap44xx_mcspi2_hwmod,
4237 .clk = "l4_div_ck",
4238 .user = OCP_USER_MPU | OCP_USER_SDMA,
4239 };
4240
4241 /* l4_per -> mcspi3 */
4242 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
4243 .master = &omap44xx_l4_per_hwmod,
4244 .slave = &omap44xx_mcspi3_hwmod,
4245 .clk = "l4_div_ck",
4246 .user = OCP_USER_MPU | OCP_USER_SDMA,
4247 };
4248
4249 /* l4_per -> mcspi4 */
4250 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
4251 .master = &omap44xx_l4_per_hwmod,
4252 .slave = &omap44xx_mcspi4_hwmod,
4253 .clk = "l4_div_ck",
4254 .user = OCP_USER_MPU | OCP_USER_SDMA,
4255 };
4256
4257 /* l4_per -> mmc1 */
4258 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
4259 .master = &omap44xx_l4_per_hwmod,
4260 .slave = &omap44xx_mmc1_hwmod,
4261 .clk = "l4_div_ck",
4262 .user = OCP_USER_MPU | OCP_USER_SDMA,
4263 };
4264
4265 /* l4_per -> mmc2 */
4266 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
4267 .master = &omap44xx_l4_per_hwmod,
4268 .slave = &omap44xx_mmc2_hwmod,
4269 .clk = "l4_div_ck",
4270 .user = OCP_USER_MPU | OCP_USER_SDMA,
4271 };
4272
4273 /* l4_per -> mmc3 */
4274 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
4275 .master = &omap44xx_l4_per_hwmod,
4276 .slave = &omap44xx_mmc3_hwmod,
4277 .clk = "l4_div_ck",
4278 .user = OCP_USER_MPU | OCP_USER_SDMA,
4279 };
4280
4281 /* l4_per -> mmc4 */
4282 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
4283 .master = &omap44xx_l4_per_hwmod,
4284 .slave = &omap44xx_mmc4_hwmod,
4285 .clk = "l4_div_ck",
4286 .user = OCP_USER_MPU | OCP_USER_SDMA,
4287 };
4288
4289 /* l4_per -> mmc5 */
4290 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
4291 .master = &omap44xx_l4_per_hwmod,
4292 .slave = &omap44xx_mmc5_hwmod,
4293 .clk = "l4_div_ck",
4294 .user = OCP_USER_MPU | OCP_USER_SDMA,
4295 };
4296
4297 /* l3_main_2 -> ocmc_ram */
4298 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
4299 .master = &omap44xx_l3_main_2_hwmod,
4300 .slave = &omap44xx_ocmc_ram_hwmod,
4301 .clk = "l3_div_ck",
4302 .user = OCP_USER_MPU | OCP_USER_SDMA,
4303 };
4304
4305 /* l4_cfg -> ocp2scp_usb_phy */
4306 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
4307 .master = &omap44xx_l4_cfg_hwmod,
4308 .slave = &omap44xx_ocp2scp_usb_phy_hwmod,
4309 .clk = "l4_div_ck",
4310 .user = OCP_USER_MPU | OCP_USER_SDMA,
4311 };
4312
4313 /* mpu_private -> prcm_mpu */
4314 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
4315 .master = &omap44xx_mpu_private_hwmod,
4316 .slave = &omap44xx_prcm_mpu_hwmod,
4317 .clk = "l3_div_ck",
4318 .user = OCP_USER_MPU | OCP_USER_SDMA,
4319 };
4320
4321 /* l4_wkup -> cm_core_aon */
4322 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
4323 .master = &omap44xx_l4_wkup_hwmod,
4324 .slave = &omap44xx_cm_core_aon_hwmod,
4325 .clk = "l4_wkup_clk_mux_ck",
4326 .user = OCP_USER_MPU | OCP_USER_SDMA,
4327 };
4328
4329 /* l4_cfg -> cm_core */
4330 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
4331 .master = &omap44xx_l4_cfg_hwmod,
4332 .slave = &omap44xx_cm_core_hwmod,
4333 .clk = "l4_div_ck",
4334 .user = OCP_USER_MPU | OCP_USER_SDMA,
4335 };
4336
4337 /* l4_wkup -> prm */
4338 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
4339 .master = &omap44xx_l4_wkup_hwmod,
4340 .slave = &omap44xx_prm_hwmod,
4341 .clk = "l4_wkup_clk_mux_ck",
4342 .user = OCP_USER_MPU | OCP_USER_SDMA,
4343 };
4344
4345 /* l4_wkup -> scrm */
4346 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
4347 .master = &omap44xx_l4_wkup_hwmod,
4348 .slave = &omap44xx_scrm_hwmod,
4349 .clk = "l4_wkup_clk_mux_ck",
4350 .user = OCP_USER_MPU | OCP_USER_SDMA,
4351 };
4352
4353 /* l3_main_2 -> sl2if */
4354 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
4355 .master = &omap44xx_l3_main_2_hwmod,
4356 .slave = &omap44xx_sl2if_hwmod,
4357 .clk = "l3_div_ck",
4358 .user = OCP_USER_MPU | OCP_USER_SDMA,
4359 };
4360
4361 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
4362 {
4363 .pa_start = 0x4012c000,
4364 .pa_end = 0x4012c3ff,
4365 .flags = ADDR_TYPE_RT
4366 },
4367 { }
4368 };
4369
4370 /* l4_abe -> slimbus1 */
4371 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
4372 .master = &omap44xx_l4_abe_hwmod,
4373 .slave = &omap44xx_slimbus1_hwmod,
4374 .clk = "ocp_abe_iclk",
4375 .addr = omap44xx_slimbus1_addrs,
4376 .user = OCP_USER_MPU,
4377 };
4378
4379 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
4380 {
4381 .pa_start = 0x4902c000,
4382 .pa_end = 0x4902c3ff,
4383 .flags = ADDR_TYPE_RT
4384 },
4385 { }
4386 };
4387
4388 /* l4_abe -> slimbus1 (dma) */
4389 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
4390 .master = &omap44xx_l4_abe_hwmod,
4391 .slave = &omap44xx_slimbus1_hwmod,
4392 .clk = "ocp_abe_iclk",
4393 .addr = omap44xx_slimbus1_dma_addrs,
4394 .user = OCP_USER_SDMA,
4395 };
4396
4397 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
4398 {
4399 .pa_start = 0x48076000,
4400 .pa_end = 0x480763ff,
4401 .flags = ADDR_TYPE_RT
4402 },
4403 { }
4404 };
4405
4406 /* l4_per -> slimbus2 */
4407 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
4408 .master = &omap44xx_l4_per_hwmod,
4409 .slave = &omap44xx_slimbus2_hwmod,
4410 .clk = "l4_div_ck",
4411 .addr = omap44xx_slimbus2_addrs,
4412 .user = OCP_USER_MPU | OCP_USER_SDMA,
4413 };
4414
4415 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
4416 {
4417 .pa_start = 0x4a0dd000,
4418 .pa_end = 0x4a0dd03f,
4419 .flags = ADDR_TYPE_RT
4420 },
4421 { }
4422 };
4423
4424 /* l4_cfg -> smartreflex_core */
4425 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
4426 .master = &omap44xx_l4_cfg_hwmod,
4427 .slave = &omap44xx_smartreflex_core_hwmod,
4428 .clk = "l4_div_ck",
4429 .addr = omap44xx_smartreflex_core_addrs,
4430 .user = OCP_USER_MPU | OCP_USER_SDMA,
4431 };
4432
4433 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
4434 {
4435 .pa_start = 0x4a0db000,
4436 .pa_end = 0x4a0db03f,
4437 .flags = ADDR_TYPE_RT
4438 },
4439 { }
4440 };
4441
4442 /* l4_cfg -> smartreflex_iva */
4443 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
4444 .master = &omap44xx_l4_cfg_hwmod,
4445 .slave = &omap44xx_smartreflex_iva_hwmod,
4446 .clk = "l4_div_ck",
4447 .addr = omap44xx_smartreflex_iva_addrs,
4448 .user = OCP_USER_MPU | OCP_USER_SDMA,
4449 };
4450
4451 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
4452 {
4453 .pa_start = 0x4a0d9000,
4454 .pa_end = 0x4a0d903f,
4455 .flags = ADDR_TYPE_RT
4456 },
4457 { }
4458 };
4459
4460 /* l4_cfg -> smartreflex_mpu */
4461 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
4462 .master = &omap44xx_l4_cfg_hwmod,
4463 .slave = &omap44xx_smartreflex_mpu_hwmod,
4464 .clk = "l4_div_ck",
4465 .addr = omap44xx_smartreflex_mpu_addrs,
4466 .user = OCP_USER_MPU | OCP_USER_SDMA,
4467 };
4468
4469 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
4470 {
4471 .pa_start = 0x4a0f6000,
4472 .pa_end = 0x4a0f6fff,
4473 .flags = ADDR_TYPE_RT
4474 },
4475 { }
4476 };
4477
4478 /* l4_cfg -> spinlock */
4479 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
4480 .master = &omap44xx_l4_cfg_hwmod,
4481 .slave = &omap44xx_spinlock_hwmod,
4482 .clk = "l4_div_ck",
4483 .addr = omap44xx_spinlock_addrs,
4484 .user = OCP_USER_MPU | OCP_USER_SDMA,
4485 };
4486
4487 /* l4_wkup -> timer1 */
4488 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4489 .master = &omap44xx_l4_wkup_hwmod,
4490 .slave = &omap44xx_timer1_hwmod,
4491 .clk = "l4_wkup_clk_mux_ck",
4492 .user = OCP_USER_MPU | OCP_USER_SDMA,
4493 };
4494
4495 /* l4_per -> timer2 */
4496 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4497 .master = &omap44xx_l4_per_hwmod,
4498 .slave = &omap44xx_timer2_hwmod,
4499 .clk = "l4_div_ck",
4500 .user = OCP_USER_MPU | OCP_USER_SDMA,
4501 };
4502
4503 /* l4_per -> timer3 */
4504 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4505 .master = &omap44xx_l4_per_hwmod,
4506 .slave = &omap44xx_timer3_hwmod,
4507 .clk = "l4_div_ck",
4508 .user = OCP_USER_MPU | OCP_USER_SDMA,
4509 };
4510
4511 /* l4_per -> timer4 */
4512 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4513 .master = &omap44xx_l4_per_hwmod,
4514 .slave = &omap44xx_timer4_hwmod,
4515 .clk = "l4_div_ck",
4516 .user = OCP_USER_MPU | OCP_USER_SDMA,
4517 };
4518
4519 /* l4_abe -> timer5 */
4520 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4521 .master = &omap44xx_l4_abe_hwmod,
4522 .slave = &omap44xx_timer5_hwmod,
4523 .clk = "ocp_abe_iclk",
4524 .user = OCP_USER_MPU | OCP_USER_SDMA,
4525 };
4526
4527 /* l4_abe -> timer6 */
4528 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4529 .master = &omap44xx_l4_abe_hwmod,
4530 .slave = &omap44xx_timer6_hwmod,
4531 .clk = "ocp_abe_iclk",
4532 .user = OCP_USER_MPU | OCP_USER_SDMA,
4533 };
4534
4535 /* l4_abe -> timer7 */
4536 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4537 .master = &omap44xx_l4_abe_hwmod,
4538 .slave = &omap44xx_timer7_hwmod,
4539 .clk = "ocp_abe_iclk",
4540 .user = OCP_USER_MPU | OCP_USER_SDMA,
4541 };
4542
4543 /* l4_abe -> timer8 */
4544 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4545 .master = &omap44xx_l4_abe_hwmod,
4546 .slave = &omap44xx_timer8_hwmod,
4547 .clk = "ocp_abe_iclk",
4548 .user = OCP_USER_MPU | OCP_USER_SDMA,
4549 };
4550
4551 /* l4_per -> timer9 */
4552 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4553 .master = &omap44xx_l4_per_hwmod,
4554 .slave = &omap44xx_timer9_hwmod,
4555 .clk = "l4_div_ck",
4556 .user = OCP_USER_MPU | OCP_USER_SDMA,
4557 };
4558
4559 /* l4_per -> timer10 */
4560 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4561 .master = &omap44xx_l4_per_hwmod,
4562 .slave = &omap44xx_timer10_hwmod,
4563 .clk = "l4_div_ck",
4564 .user = OCP_USER_MPU | OCP_USER_SDMA,
4565 };
4566
4567 /* l4_per -> timer11 */
4568 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4569 .master = &omap44xx_l4_per_hwmod,
4570 .slave = &omap44xx_timer11_hwmod,
4571 .clk = "l4_div_ck",
4572 .user = OCP_USER_MPU | OCP_USER_SDMA,
4573 };
4574
4575 /* l4_per -> uart1 */
4576 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4577 .master = &omap44xx_l4_per_hwmod,
4578 .slave = &omap44xx_uart1_hwmod,
4579 .clk = "l4_div_ck",
4580 .user = OCP_USER_MPU | OCP_USER_SDMA,
4581 };
4582
4583 /* l4_per -> uart2 */
4584 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4585 .master = &omap44xx_l4_per_hwmod,
4586 .slave = &omap44xx_uart2_hwmod,
4587 .clk = "l4_div_ck",
4588 .user = OCP_USER_MPU | OCP_USER_SDMA,
4589 };
4590
4591 /* l4_per -> uart3 */
4592 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4593 .master = &omap44xx_l4_per_hwmod,
4594 .slave = &omap44xx_uart3_hwmod,
4595 .clk = "l4_div_ck",
4596 .user = OCP_USER_MPU | OCP_USER_SDMA,
4597 };
4598
4599 /* l4_per -> uart4 */
4600 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
4601 .master = &omap44xx_l4_per_hwmod,
4602 .slave = &omap44xx_uart4_hwmod,
4603 .clk = "l4_div_ck",
4604 .user = OCP_USER_MPU | OCP_USER_SDMA,
4605 };
4606
4607 /* l4_cfg -> usb_host_fs */
4608 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
4609 .master = &omap44xx_l4_cfg_hwmod,
4610 .slave = &omap44xx_usb_host_fs_hwmod,
4611 .clk = "l4_div_ck",
4612 .user = OCP_USER_MPU | OCP_USER_SDMA,
4613 };
4614
4615 /* l4_cfg -> usb_host_hs */
4616 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
4617 .master = &omap44xx_l4_cfg_hwmod,
4618 .slave = &omap44xx_usb_host_hs_hwmod,
4619 .clk = "l4_div_ck",
4620 .user = OCP_USER_MPU | OCP_USER_SDMA,
4621 };
4622
4623 /* l4_cfg -> usb_otg_hs */
4624 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
4625 .master = &omap44xx_l4_cfg_hwmod,
4626 .slave = &omap44xx_usb_otg_hs_hwmod,
4627 .clk = "l4_div_ck",
4628 .user = OCP_USER_MPU | OCP_USER_SDMA,
4629 };
4630
4631 /* l4_cfg -> usb_tll_hs */
4632 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
4633 .master = &omap44xx_l4_cfg_hwmod,
4634 .slave = &omap44xx_usb_tll_hs_hwmod,
4635 .clk = "l4_div_ck",
4636 .user = OCP_USER_MPU | OCP_USER_SDMA,
4637 };
4638
4639 /* l4_wkup -> wd_timer2 */
4640 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
4641 .master = &omap44xx_l4_wkup_hwmod,
4642 .slave = &omap44xx_wd_timer2_hwmod,
4643 .clk = "l4_wkup_clk_mux_ck",
4644 .user = OCP_USER_MPU | OCP_USER_SDMA,
4645 };
4646
4647 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
4648 {
4649 .pa_start = 0x40130000,
4650 .pa_end = 0x4013007f,
4651 .flags = ADDR_TYPE_RT
4652 },
4653 { }
4654 };
4655
4656 /* l4_abe -> wd_timer3 */
4657 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
4658 .master = &omap44xx_l4_abe_hwmod,
4659 .slave = &omap44xx_wd_timer3_hwmod,
4660 .clk = "ocp_abe_iclk",
4661 .addr = omap44xx_wd_timer3_addrs,
4662 .user = OCP_USER_MPU,
4663 };
4664
4665 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
4666 {
4667 .pa_start = 0x49030000,
4668 .pa_end = 0x4903007f,
4669 .flags = ADDR_TYPE_RT
4670 },
4671 { }
4672 };
4673
4674 /* l4_abe -> wd_timer3 (dma) */
4675 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
4676 .master = &omap44xx_l4_abe_hwmod,
4677 .slave = &omap44xx_wd_timer3_hwmod,
4678 .clk = "ocp_abe_iclk",
4679 .addr = omap44xx_wd_timer3_dma_addrs,
4680 .user = OCP_USER_SDMA,
4681 };
4682
4683 /* mpu -> emif1 */
4684 static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
4685 .master = &omap44xx_mpu_hwmod,
4686 .slave = &omap44xx_emif1_hwmod,
4687 .clk = "l3_div_ck",
4688 .user = OCP_USER_MPU | OCP_USER_SDMA,
4689 };
4690
4691 /* mpu -> emif2 */
4692 static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
4693 .master = &omap44xx_mpu_hwmod,
4694 .slave = &omap44xx_emif2_hwmod,
4695 .clk = "l3_div_ck",
4696 .user = OCP_USER_MPU | OCP_USER_SDMA,
4697 };
4698
4699 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
4700 &omap44xx_l3_main_1__dmm,
4701 &omap44xx_mpu__dmm,
4702 &omap44xx_iva__l3_instr,
4703 &omap44xx_l3_main_3__l3_instr,
4704 &omap44xx_ocp_wp_noc__l3_instr,
4705 &omap44xx_dsp__l3_main_1,
4706 &omap44xx_dss__l3_main_1,
4707 &omap44xx_l3_main_2__l3_main_1,
4708 &omap44xx_l4_cfg__l3_main_1,
4709 &omap44xx_mmc1__l3_main_1,
4710 &omap44xx_mmc2__l3_main_1,
4711 &omap44xx_mpu__l3_main_1,
4712 &omap44xx_debugss__l3_main_2,
4713 &omap44xx_dma_system__l3_main_2,
4714 &omap44xx_fdif__l3_main_2,
4715 &omap44xx_gpu__l3_main_2,
4716 &omap44xx_hsi__l3_main_2,
4717 &omap44xx_ipu__l3_main_2,
4718 &omap44xx_iss__l3_main_2,
4719 &omap44xx_iva__l3_main_2,
4720 &omap44xx_l3_main_1__l3_main_2,
4721 &omap44xx_l4_cfg__l3_main_2,
4722 /* &omap44xx_usb_host_fs__l3_main_2, */
4723 &omap44xx_usb_host_hs__l3_main_2,
4724 &omap44xx_usb_otg_hs__l3_main_2,
4725 &omap44xx_l3_main_1__l3_main_3,
4726 &omap44xx_l3_main_2__l3_main_3,
4727 &omap44xx_l4_cfg__l3_main_3,
4728 &omap44xx_aess__l4_abe,
4729 &omap44xx_dsp__l4_abe,
4730 &omap44xx_l3_main_1__l4_abe,
4731 &omap44xx_mpu__l4_abe,
4732 &omap44xx_l3_main_1__l4_cfg,
4733 &omap44xx_l3_main_2__l4_per,
4734 &omap44xx_l4_cfg__l4_wkup,
4735 &omap44xx_mpu__mpu_private,
4736 &omap44xx_l4_cfg__ocp_wp_noc,
4737 &omap44xx_l4_abe__aess,
4738 &omap44xx_l4_abe__aess_dma,
4739 &omap44xx_l3_main_2__c2c,
4740 &omap44xx_l4_wkup__counter_32k,
4741 &omap44xx_l4_cfg__ctrl_module_core,
4742 &omap44xx_l4_cfg__ctrl_module_pad_core,
4743 &omap44xx_l4_wkup__ctrl_module_wkup,
4744 &omap44xx_l4_wkup__ctrl_module_pad_wkup,
4745 &omap44xx_l3_instr__debugss,
4746 &omap44xx_l4_cfg__dma_system,
4747 &omap44xx_l4_abe__dmic,
4748 &omap44xx_dsp__iva,
4749 /* &omap44xx_dsp__sl2if, */
4750 &omap44xx_l4_cfg__dsp,
4751 &omap44xx_l3_main_2__dss,
4752 &omap44xx_l4_per__dss,
4753 &omap44xx_l3_main_2__dss_dispc,
4754 &omap44xx_l4_per__dss_dispc,
4755 &omap44xx_l3_main_2__dss_dsi1,
4756 &omap44xx_l4_per__dss_dsi1,
4757 &omap44xx_l3_main_2__dss_dsi2,
4758 &omap44xx_l4_per__dss_dsi2,
4759 &omap44xx_l3_main_2__dss_hdmi,
4760 &omap44xx_l4_per__dss_hdmi,
4761 &omap44xx_l3_main_2__dss_rfbi,
4762 &omap44xx_l4_per__dss_rfbi,
4763 &omap44xx_l3_main_2__dss_venc,
4764 &omap44xx_l4_per__dss_venc,
4765 &omap44xx_l4_per__elm,
4766 &omap44xx_l4_cfg__fdif,
4767 &omap44xx_l4_wkup__gpio1,
4768 &omap44xx_l4_per__gpio2,
4769 &omap44xx_l4_per__gpio3,
4770 &omap44xx_l4_per__gpio4,
4771 &omap44xx_l4_per__gpio5,
4772 &omap44xx_l4_per__gpio6,
4773 &omap44xx_l3_main_2__gpmc,
4774 &omap44xx_l3_main_2__gpu,
4775 &omap44xx_l4_per__hdq1w,
4776 &omap44xx_l4_cfg__hsi,
4777 &omap44xx_l4_per__i2c1,
4778 &omap44xx_l4_per__i2c2,
4779 &omap44xx_l4_per__i2c3,
4780 &omap44xx_l4_per__i2c4,
4781 &omap44xx_l3_main_2__ipu,
4782 &omap44xx_l3_main_2__iss,
4783 /* &omap44xx_iva__sl2if, */
4784 &omap44xx_l3_main_2__iva,
4785 &omap44xx_l4_wkup__kbd,
4786 &omap44xx_l4_cfg__mailbox,
4787 &omap44xx_l4_abe__mcasp,
4788 &omap44xx_l4_abe__mcasp_dma,
4789 &omap44xx_l4_abe__mcbsp1,
4790 &omap44xx_l4_abe__mcbsp2,
4791 &omap44xx_l4_abe__mcbsp3,
4792 &omap44xx_l4_per__mcbsp4,
4793 &omap44xx_l4_abe__mcpdm,
4794 &omap44xx_l4_per__mcspi1,
4795 &omap44xx_l4_per__mcspi2,
4796 &omap44xx_l4_per__mcspi3,
4797 &omap44xx_l4_per__mcspi4,
4798 &omap44xx_l4_per__mmc1,
4799 &omap44xx_l4_per__mmc2,
4800 &omap44xx_l4_per__mmc3,
4801 &omap44xx_l4_per__mmc4,
4802 &omap44xx_l4_per__mmc5,
4803 &omap44xx_l3_main_2__mmu_ipu,
4804 &omap44xx_l4_cfg__mmu_dsp,
4805 &omap44xx_l3_main_2__ocmc_ram,
4806 &omap44xx_l4_cfg__ocp2scp_usb_phy,
4807 &omap44xx_mpu_private__prcm_mpu,
4808 &omap44xx_l4_wkup__cm_core_aon,
4809 &omap44xx_l4_cfg__cm_core,
4810 &omap44xx_l4_wkup__prm,
4811 &omap44xx_l4_wkup__scrm,
4812 /* &omap44xx_l3_main_2__sl2if, */
4813 &omap44xx_l4_abe__slimbus1,
4814 &omap44xx_l4_abe__slimbus1_dma,
4815 &omap44xx_l4_per__slimbus2,
4816 &omap44xx_l4_cfg__smartreflex_core,
4817 &omap44xx_l4_cfg__smartreflex_iva,
4818 &omap44xx_l4_cfg__smartreflex_mpu,
4819 &omap44xx_l4_cfg__spinlock,
4820 &omap44xx_l4_wkup__timer1,
4821 &omap44xx_l4_per__timer2,
4822 &omap44xx_l4_per__timer3,
4823 &omap44xx_l4_per__timer4,
4824 &omap44xx_l4_abe__timer5,
4825 &omap44xx_l4_abe__timer6,
4826 &omap44xx_l4_abe__timer7,
4827 &omap44xx_l4_abe__timer8,
4828 &omap44xx_l4_per__timer9,
4829 &omap44xx_l4_per__timer10,
4830 &omap44xx_l4_per__timer11,
4831 &omap44xx_l4_per__uart1,
4832 &omap44xx_l4_per__uart2,
4833 &omap44xx_l4_per__uart3,
4834 &omap44xx_l4_per__uart4,
4835 /* &omap44xx_l4_cfg__usb_host_fs, */
4836 &omap44xx_l4_cfg__usb_host_hs,
4837 &omap44xx_l4_cfg__usb_otg_hs,
4838 &omap44xx_l4_cfg__usb_tll_hs,
4839 &omap44xx_l4_wkup__wd_timer2,
4840 &omap44xx_l4_abe__wd_timer3,
4841 &omap44xx_l4_abe__wd_timer3_dma,
4842 &omap44xx_mpu__emif1,
4843 &omap44xx_mpu__emif2,
4844 NULL,
4845 };
4846
4847 int __init omap44xx_hwmod_init(void)
4848 {
4849 omap_hwmod_init();
4850 return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
4851 }
4852
Linux kernel - Deliverables
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