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Merge tag 'please-pull-misc-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_44xx_data.c
1 /*
2 * Hardware modules present on the OMAP44xx chips
3 *
4 * Copyright (C) 2009-2012 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley
8 * Benoit Cousson
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 * Note that this file is currently not in sync with autogeneration scripts.
16 * The above note to be removed, once it is synced up.
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21 */
22
23 #include <linux/io.h>
24 #include <linux/platform_data/gpio-omap.h>
25 #include <linux/platform_data/hsmmc-omap.h>
26 #include <linux/power/smartreflex.h>
27 #include <linux/i2c-omap.h>
28
29 #include <linux/omap-dma.h>
30
31 #include <linux/platform_data/spi-omap2-mcspi.h>
32 #include <linux/platform_data/asoc-ti-mcbsp.h>
33 #include <linux/platform_data/iommu-omap.h>
34 #include <plat/dmtimer.h>
35
36 #include "omap_hwmod.h"
37 #include "omap_hwmod_common_data.h"
38 #include "cm1_44xx.h"
39 #include "cm2_44xx.h"
40 #include "prm44xx.h"
41 #include "prm-regbits-44xx.h"
42 #include "i2c.h"
43 #include "wd_timer.h"
44
45 /* Base offset for all OMAP4 interrupts external to MPUSS */
46 #define OMAP44XX_IRQ_GIC_START 32
47
48 /* Base offset for all OMAP4 dma requests */
49 #define OMAP44XX_DMA_REQ_START 1
50
51 /*
52 * IP blocks
53 */
54
55 /*
56 * 'dmm' class
57 * instance(s): dmm
58 */
59 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
60 .name = "dmm",
61 };
62
63 /* dmm */
64 static struct omap_hwmod omap44xx_dmm_hwmod = {
65 .name = "dmm",
66 .class = &omap44xx_dmm_hwmod_class,
67 .clkdm_name = "l3_emif_clkdm",
68 .prcm = {
69 .omap4 = {
70 .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
71 .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
72 },
73 },
74 };
75
76 /*
77 * 'l3' class
78 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
79 */
80 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
81 .name = "l3",
82 };
83
84 /* l3_instr */
85 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
86 .name = "l3_instr",
87 .class = &omap44xx_l3_hwmod_class,
88 .clkdm_name = "l3_instr_clkdm",
89 .prcm = {
90 .omap4 = {
91 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
92 .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
93 .modulemode = MODULEMODE_HWCTRL,
94 },
95 },
96 };
97
98 /* l3_main_1 */
99 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
100 .name = "l3_main_1",
101 .class = &omap44xx_l3_hwmod_class,
102 .clkdm_name = "l3_1_clkdm",
103 .prcm = {
104 .omap4 = {
105 .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
106 .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
107 },
108 },
109 };
110
111 /* l3_main_2 */
112 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
113 .name = "l3_main_2",
114 .class = &omap44xx_l3_hwmod_class,
115 .clkdm_name = "l3_2_clkdm",
116 .prcm = {
117 .omap4 = {
118 .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
119 .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
120 },
121 },
122 };
123
124 /* l3_main_3 */
125 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
126 .name = "l3_main_3",
127 .class = &omap44xx_l3_hwmod_class,
128 .clkdm_name = "l3_instr_clkdm",
129 .prcm = {
130 .omap4 = {
131 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
132 .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
133 .modulemode = MODULEMODE_HWCTRL,
134 },
135 },
136 };
137
138 /*
139 * 'l4' class
140 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
141 */
142 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
143 .name = "l4",
144 };
145
146 /* l4_abe */
147 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
148 .name = "l4_abe",
149 .class = &omap44xx_l4_hwmod_class,
150 .clkdm_name = "abe_clkdm",
151 .prcm = {
152 .omap4 = {
153 .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
154 .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
155 .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
156 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
157 },
158 },
159 };
160
161 /* l4_cfg */
162 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
163 .name = "l4_cfg",
164 .class = &omap44xx_l4_hwmod_class,
165 .clkdm_name = "l4_cfg_clkdm",
166 .prcm = {
167 .omap4 = {
168 .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
169 .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
170 },
171 },
172 };
173
174 /* l4_per */
175 static struct omap_hwmod omap44xx_l4_per_hwmod = {
176 .name = "l4_per",
177 .class = &omap44xx_l4_hwmod_class,
178 .clkdm_name = "l4_per_clkdm",
179 .prcm = {
180 .omap4 = {
181 .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
182 .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
183 },
184 },
185 };
186
187 /* l4_wkup */
188 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
189 .name = "l4_wkup",
190 .class = &omap44xx_l4_hwmod_class,
191 .clkdm_name = "l4_wkup_clkdm",
192 .prcm = {
193 .omap4 = {
194 .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
195 .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
196 },
197 },
198 };
199
200 /*
201 * 'mpu_bus' class
202 * instance(s): mpu_private
203 */
204 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
205 .name = "mpu_bus",
206 };
207
208 /* mpu_private */
209 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
210 .name = "mpu_private",
211 .class = &omap44xx_mpu_bus_hwmod_class,
212 .clkdm_name = "mpuss_clkdm",
213 .prcm = {
214 .omap4 = {
215 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
216 },
217 },
218 };
219
220 /*
221 * 'ocp_wp_noc' class
222 * instance(s): ocp_wp_noc
223 */
224 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
225 .name = "ocp_wp_noc",
226 };
227
228 /* ocp_wp_noc */
229 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
230 .name = "ocp_wp_noc",
231 .class = &omap44xx_ocp_wp_noc_hwmod_class,
232 .clkdm_name = "l3_instr_clkdm",
233 .prcm = {
234 .omap4 = {
235 .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
236 .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
237 .modulemode = MODULEMODE_HWCTRL,
238 },
239 },
240 };
241
242 /*
243 * Modules omap_hwmod structures
244 *
245 * The following IPs are excluded for the moment because:
246 * - They do not need an explicit SW control using omap_hwmod API.
247 * - They still need to be validated with the driver
248 * properly adapted to omap_hwmod / omap_device
249 *
250 * usim
251 */
252
253 /*
254 * 'aess' class
255 * audio engine sub system
256 */
257
258 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
259 .rev_offs = 0x0000,
260 .sysc_offs = 0x0010,
261 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
262 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
263 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
264 MSTANDBY_SMART_WKUP),
265 .sysc_fields = &omap_hwmod_sysc_type2,
266 };
267
268 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
269 .name = "aess",
270 .sysc = &omap44xx_aess_sysc,
271 .enable_preprogram = omap_hwmod_aess_preprogram,
272 };
273
274 /* aess */
275 static struct omap_hwmod omap44xx_aess_hwmod = {
276 .name = "aess",
277 .class = &omap44xx_aess_hwmod_class,
278 .clkdm_name = "abe_clkdm",
279 .main_clk = "aess_fclk",
280 .prcm = {
281 .omap4 = {
282 .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
283 .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
284 .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
285 .modulemode = MODULEMODE_SWCTRL,
286 },
287 },
288 };
289
290 /*
291 * 'c2c' class
292 * chip 2 chip interface used to plug the ape soc (omap) with an external modem
293 * soc
294 */
295
296 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
297 .name = "c2c",
298 };
299
300 /* c2c */
301 static struct omap_hwmod omap44xx_c2c_hwmod = {
302 .name = "c2c",
303 .class = &omap44xx_c2c_hwmod_class,
304 .clkdm_name = "d2d_clkdm",
305 .prcm = {
306 .omap4 = {
307 .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
308 .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
309 },
310 },
311 };
312
313 /*
314 * 'counter' class
315 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
316 */
317
318 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
319 .rev_offs = 0x0000,
320 .sysc_offs = 0x0004,
321 .sysc_flags = SYSC_HAS_SIDLEMODE,
322 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
323 .sysc_fields = &omap_hwmod_sysc_type1,
324 };
325
326 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
327 .name = "counter",
328 .sysc = &omap44xx_counter_sysc,
329 };
330
331 /* counter_32k */
332 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
333 .name = "counter_32k",
334 .class = &omap44xx_counter_hwmod_class,
335 .clkdm_name = "l4_wkup_clkdm",
336 .flags = HWMOD_SWSUP_SIDLE,
337 .main_clk = "sys_32k_ck",
338 .prcm = {
339 .omap4 = {
340 .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
341 .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
342 },
343 },
344 };
345
346 /*
347 * 'ctrl_module' class
348 * attila core control module + core pad control module + wkup pad control
349 * module + attila wkup control module
350 */
351
352 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
353 .rev_offs = 0x0000,
354 .sysc_offs = 0x0010,
355 .sysc_flags = SYSC_HAS_SIDLEMODE,
356 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
357 SIDLE_SMART_WKUP),
358 .sysc_fields = &omap_hwmod_sysc_type2,
359 };
360
361 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
362 .name = "ctrl_module",
363 .sysc = &omap44xx_ctrl_module_sysc,
364 };
365
366 /* ctrl_module_core */
367 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
368 .name = "ctrl_module_core",
369 .class = &omap44xx_ctrl_module_hwmod_class,
370 .clkdm_name = "l4_cfg_clkdm",
371 .prcm = {
372 .omap4 = {
373 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
374 },
375 },
376 };
377
378 /* ctrl_module_pad_core */
379 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
380 .name = "ctrl_module_pad_core",
381 .class = &omap44xx_ctrl_module_hwmod_class,
382 .clkdm_name = "l4_cfg_clkdm",
383 .prcm = {
384 .omap4 = {
385 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
386 },
387 },
388 };
389
390 /* ctrl_module_wkup */
391 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
392 .name = "ctrl_module_wkup",
393 .class = &omap44xx_ctrl_module_hwmod_class,
394 .clkdm_name = "l4_wkup_clkdm",
395 .prcm = {
396 .omap4 = {
397 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
398 },
399 },
400 };
401
402 /* ctrl_module_pad_wkup */
403 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
404 .name = "ctrl_module_pad_wkup",
405 .class = &omap44xx_ctrl_module_hwmod_class,
406 .clkdm_name = "l4_wkup_clkdm",
407 .prcm = {
408 .omap4 = {
409 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
410 },
411 },
412 };
413
414 /*
415 * 'debugss' class
416 * debug and emulation sub system
417 */
418
419 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
420 .name = "debugss",
421 };
422
423 /* debugss */
424 static struct omap_hwmod omap44xx_debugss_hwmod = {
425 .name = "debugss",
426 .class = &omap44xx_debugss_hwmod_class,
427 .clkdm_name = "emu_sys_clkdm",
428 .main_clk = "trace_clk_div_ck",
429 .prcm = {
430 .omap4 = {
431 .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
432 .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
433 },
434 },
435 };
436
437 /*
438 * 'dma' class
439 * dma controller for data exchange between memory to memory (i.e. internal or
440 * external memory) and gp peripherals to memory or memory to gp peripherals
441 */
442
443 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
444 .rev_offs = 0x0000,
445 .sysc_offs = 0x002c,
446 .syss_offs = 0x0028,
447 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
448 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
449 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
450 SYSS_HAS_RESET_STATUS),
451 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
452 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
453 .sysc_fields = &omap_hwmod_sysc_type1,
454 };
455
456 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
457 .name = "dma",
458 .sysc = &omap44xx_dma_sysc,
459 };
460
461 /* dma dev_attr */
462 static struct omap_dma_dev_attr dma_dev_attr = {
463 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
464 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
465 .lch_count = 32,
466 };
467
468 /* dma_system */
469 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
470 { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
471 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
472 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
473 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
474 { .irq = -1 }
475 };
476
477 static struct omap_hwmod omap44xx_dma_system_hwmod = {
478 .name = "dma_system",
479 .class = &omap44xx_dma_hwmod_class,
480 .clkdm_name = "l3_dma_clkdm",
481 .mpu_irqs = omap44xx_dma_system_irqs,
482 .main_clk = "l3_div_ck",
483 .prcm = {
484 .omap4 = {
485 .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
486 .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
487 },
488 },
489 .dev_attr = &dma_dev_attr,
490 };
491
492 /*
493 * 'dmic' class
494 * digital microphone controller
495 */
496
497 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
498 .rev_offs = 0x0000,
499 .sysc_offs = 0x0010,
500 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
501 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
502 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
503 SIDLE_SMART_WKUP),
504 .sysc_fields = &omap_hwmod_sysc_type2,
505 };
506
507 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
508 .name = "dmic",
509 .sysc = &omap44xx_dmic_sysc,
510 };
511
512 /* dmic */
513 static struct omap_hwmod omap44xx_dmic_hwmod = {
514 .name = "dmic",
515 .class = &omap44xx_dmic_hwmod_class,
516 .clkdm_name = "abe_clkdm",
517 .main_clk = "func_dmic_abe_gfclk",
518 .prcm = {
519 .omap4 = {
520 .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
521 .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
522 .modulemode = MODULEMODE_SWCTRL,
523 },
524 },
525 };
526
527 /*
528 * 'dsp' class
529 * dsp sub-system
530 */
531
532 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
533 .name = "dsp",
534 };
535
536 /* dsp */
537 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
538 { .name = "dsp", .rst_shift = 0 },
539 };
540
541 static struct omap_hwmod omap44xx_dsp_hwmod = {
542 .name = "dsp",
543 .class = &omap44xx_dsp_hwmod_class,
544 .clkdm_name = "tesla_clkdm",
545 .rst_lines = omap44xx_dsp_resets,
546 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
547 .main_clk = "dpll_iva_m4x2_ck",
548 .prcm = {
549 .omap4 = {
550 .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
551 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
552 .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
553 .modulemode = MODULEMODE_HWCTRL,
554 },
555 },
556 };
557
558 /*
559 * 'dss' class
560 * display sub-system
561 */
562
563 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
564 .rev_offs = 0x0000,
565 .syss_offs = 0x0014,
566 .sysc_flags = SYSS_HAS_RESET_STATUS,
567 };
568
569 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
570 .name = "dss",
571 .sysc = &omap44xx_dss_sysc,
572 .reset = omap_dss_reset,
573 };
574
575 /* dss */
576 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
577 { .role = "sys_clk", .clk = "dss_sys_clk" },
578 { .role = "tv_clk", .clk = "dss_tv_clk" },
579 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
580 };
581
582 static struct omap_hwmod omap44xx_dss_hwmod = {
583 .name = "dss_core",
584 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
585 .class = &omap44xx_dss_hwmod_class,
586 .clkdm_name = "l3_dss_clkdm",
587 .main_clk = "dss_dss_clk",
588 .prcm = {
589 .omap4 = {
590 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
591 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
592 .modulemode = MODULEMODE_SWCTRL,
593 },
594 },
595 .opt_clks = dss_opt_clks,
596 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
597 };
598
599 /*
600 * 'dispc' class
601 * display controller
602 */
603
604 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
605 .rev_offs = 0x0000,
606 .sysc_offs = 0x0010,
607 .syss_offs = 0x0014,
608 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
609 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
610 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
611 SYSS_HAS_RESET_STATUS),
612 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
613 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
614 .sysc_fields = &omap_hwmod_sysc_type1,
615 };
616
617 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
618 .name = "dispc",
619 .sysc = &omap44xx_dispc_sysc,
620 };
621
622 /* dss_dispc */
623 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
624 { .irq = 25 + OMAP44XX_IRQ_GIC_START },
625 { .irq = -1 }
626 };
627
628 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
629 { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
630 { .dma_req = -1 }
631 };
632
633 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
634 .manager_count = 3,
635 .has_framedonetv_irq = 1
636 };
637
638 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
639 .name = "dss_dispc",
640 .class = &omap44xx_dispc_hwmod_class,
641 .clkdm_name = "l3_dss_clkdm",
642 .mpu_irqs = omap44xx_dss_dispc_irqs,
643 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
644 .main_clk = "dss_dss_clk",
645 .prcm = {
646 .omap4 = {
647 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
648 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
649 },
650 },
651 .dev_attr = &omap44xx_dss_dispc_dev_attr,
652 .parent_hwmod = &omap44xx_dss_hwmod,
653 };
654
655 /*
656 * 'dsi' class
657 * display serial interface controller
658 */
659
660 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
661 .rev_offs = 0x0000,
662 .sysc_offs = 0x0010,
663 .syss_offs = 0x0014,
664 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
665 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
666 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
667 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
668 .sysc_fields = &omap_hwmod_sysc_type1,
669 };
670
671 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
672 .name = "dsi",
673 .sysc = &omap44xx_dsi_sysc,
674 };
675
676 /* dss_dsi1 */
677 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
678 { .irq = 53 + OMAP44XX_IRQ_GIC_START },
679 { .irq = -1 }
680 };
681
682 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
683 { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
684 { .dma_req = -1 }
685 };
686
687 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
688 { .role = "sys_clk", .clk = "dss_sys_clk" },
689 };
690
691 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
692 .name = "dss_dsi1",
693 .class = &omap44xx_dsi_hwmod_class,
694 .clkdm_name = "l3_dss_clkdm",
695 .mpu_irqs = omap44xx_dss_dsi1_irqs,
696 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
697 .main_clk = "dss_dss_clk",
698 .prcm = {
699 .omap4 = {
700 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
701 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
702 },
703 },
704 .opt_clks = dss_dsi1_opt_clks,
705 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
706 .parent_hwmod = &omap44xx_dss_hwmod,
707 };
708
709 /* dss_dsi2 */
710 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
711 { .irq = 84 + OMAP44XX_IRQ_GIC_START },
712 { .irq = -1 }
713 };
714
715 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
716 { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
717 { .dma_req = -1 }
718 };
719
720 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
721 { .role = "sys_clk", .clk = "dss_sys_clk" },
722 };
723
724 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
725 .name = "dss_dsi2",
726 .class = &omap44xx_dsi_hwmod_class,
727 .clkdm_name = "l3_dss_clkdm",
728 .mpu_irqs = omap44xx_dss_dsi2_irqs,
729 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
730 .main_clk = "dss_dss_clk",
731 .prcm = {
732 .omap4 = {
733 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
734 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
735 },
736 },
737 .opt_clks = dss_dsi2_opt_clks,
738 .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
739 .parent_hwmod = &omap44xx_dss_hwmod,
740 };
741
742 /*
743 * 'hdmi' class
744 * hdmi controller
745 */
746
747 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
748 .rev_offs = 0x0000,
749 .sysc_offs = 0x0010,
750 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
751 SYSC_HAS_SOFTRESET),
752 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
753 SIDLE_SMART_WKUP),
754 .sysc_fields = &omap_hwmod_sysc_type2,
755 };
756
757 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
758 .name = "hdmi",
759 .sysc = &omap44xx_hdmi_sysc,
760 };
761
762 /* dss_hdmi */
763 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
764 { .irq = 101 + OMAP44XX_IRQ_GIC_START },
765 { .irq = -1 }
766 };
767
768 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
769 { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
770 { .dma_req = -1 }
771 };
772
773 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
774 { .role = "sys_clk", .clk = "dss_sys_clk" },
775 };
776
777 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
778 .name = "dss_hdmi",
779 .class = &omap44xx_hdmi_hwmod_class,
780 .clkdm_name = "l3_dss_clkdm",
781 /*
782 * HDMI audio requires to use no-idle mode. Hence,
783 * set idle mode by software.
784 */
785 .flags = HWMOD_SWSUP_SIDLE,
786 .mpu_irqs = omap44xx_dss_hdmi_irqs,
787 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
788 .main_clk = "dss_48mhz_clk",
789 .prcm = {
790 .omap4 = {
791 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
792 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
793 },
794 },
795 .opt_clks = dss_hdmi_opt_clks,
796 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
797 .parent_hwmod = &omap44xx_dss_hwmod,
798 };
799
800 /*
801 * 'rfbi' class
802 * remote frame buffer interface
803 */
804
805 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
806 .rev_offs = 0x0000,
807 .sysc_offs = 0x0010,
808 .syss_offs = 0x0014,
809 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
810 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
811 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
812 .sysc_fields = &omap_hwmod_sysc_type1,
813 };
814
815 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
816 .name = "rfbi",
817 .sysc = &omap44xx_rfbi_sysc,
818 };
819
820 /* dss_rfbi */
821 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
822 { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
823 { .dma_req = -1 }
824 };
825
826 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
827 { .role = "ick", .clk = "l3_div_ck" },
828 };
829
830 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
831 .name = "dss_rfbi",
832 .class = &omap44xx_rfbi_hwmod_class,
833 .clkdm_name = "l3_dss_clkdm",
834 .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
835 .main_clk = "dss_dss_clk",
836 .prcm = {
837 .omap4 = {
838 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
839 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
840 },
841 },
842 .opt_clks = dss_rfbi_opt_clks,
843 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
844 .parent_hwmod = &omap44xx_dss_hwmod,
845 };
846
847 /*
848 * 'venc' class
849 * video encoder
850 */
851
852 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
853 .name = "venc",
854 };
855
856 /* dss_venc */
857 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
858 .name = "dss_venc",
859 .class = &omap44xx_venc_hwmod_class,
860 .clkdm_name = "l3_dss_clkdm",
861 .main_clk = "dss_tv_clk",
862 .prcm = {
863 .omap4 = {
864 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
865 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
866 },
867 },
868 .parent_hwmod = &omap44xx_dss_hwmod,
869 };
870
871 /*
872 * 'elm' class
873 * bch error location module
874 */
875
876 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
877 .rev_offs = 0x0000,
878 .sysc_offs = 0x0010,
879 .syss_offs = 0x0014,
880 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
881 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
882 SYSS_HAS_RESET_STATUS),
883 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
884 .sysc_fields = &omap_hwmod_sysc_type1,
885 };
886
887 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
888 .name = "elm",
889 .sysc = &omap44xx_elm_sysc,
890 };
891
892 /* elm */
893 static struct omap_hwmod omap44xx_elm_hwmod = {
894 .name = "elm",
895 .class = &omap44xx_elm_hwmod_class,
896 .clkdm_name = "l4_per_clkdm",
897 .prcm = {
898 .omap4 = {
899 .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
900 .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
901 },
902 },
903 };
904
905 /*
906 * 'emif' class
907 * external memory interface no1
908 */
909
910 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
911 .rev_offs = 0x0000,
912 };
913
914 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
915 .name = "emif",
916 .sysc = &omap44xx_emif_sysc,
917 };
918
919 /* emif1 */
920 static struct omap_hwmod omap44xx_emif1_hwmod = {
921 .name = "emif1",
922 .class = &omap44xx_emif_hwmod_class,
923 .clkdm_name = "l3_emif_clkdm",
924 .flags = HWMOD_INIT_NO_IDLE,
925 .main_clk = "ddrphy_ck",
926 .prcm = {
927 .omap4 = {
928 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
929 .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
930 .modulemode = MODULEMODE_HWCTRL,
931 },
932 },
933 };
934
935 /* emif2 */
936 static struct omap_hwmod omap44xx_emif2_hwmod = {
937 .name = "emif2",
938 .class = &omap44xx_emif_hwmod_class,
939 .clkdm_name = "l3_emif_clkdm",
940 .flags = HWMOD_INIT_NO_IDLE,
941 .main_clk = "ddrphy_ck",
942 .prcm = {
943 .omap4 = {
944 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
945 .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
946 .modulemode = MODULEMODE_HWCTRL,
947 },
948 },
949 };
950
951 /*
952 * 'fdif' class
953 * face detection hw accelerator module
954 */
955
956 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
957 .rev_offs = 0x0000,
958 .sysc_offs = 0x0010,
959 /*
960 * FDIF needs 100 OCP clk cycles delay after a softreset before
961 * accessing sysconfig again.
962 * The lowest frequency at the moment for L3 bus is 100 MHz, so
963 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
964 *
965 * TODO: Indicate errata when available.
966 */
967 .srst_udelay = 2,
968 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
969 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
970 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
971 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
972 .sysc_fields = &omap_hwmod_sysc_type2,
973 };
974
975 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
976 .name = "fdif",
977 .sysc = &omap44xx_fdif_sysc,
978 };
979
980 /* fdif */
981 static struct omap_hwmod omap44xx_fdif_hwmod = {
982 .name = "fdif",
983 .class = &omap44xx_fdif_hwmod_class,
984 .clkdm_name = "iss_clkdm",
985 .main_clk = "fdif_fck",
986 .prcm = {
987 .omap4 = {
988 .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
989 .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
990 .modulemode = MODULEMODE_SWCTRL,
991 },
992 },
993 };
994
995 /*
996 * 'gpio' class
997 * general purpose io module
998 */
999
1000 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1001 .rev_offs = 0x0000,
1002 .sysc_offs = 0x0010,
1003 .syss_offs = 0x0114,
1004 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1005 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1006 SYSS_HAS_RESET_STATUS),
1007 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1008 SIDLE_SMART_WKUP),
1009 .sysc_fields = &omap_hwmod_sysc_type1,
1010 };
1011
1012 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1013 .name = "gpio",
1014 .sysc = &omap44xx_gpio_sysc,
1015 .rev = 2,
1016 };
1017
1018 /* gpio dev_attr */
1019 static struct omap_gpio_dev_attr gpio_dev_attr = {
1020 .bank_width = 32,
1021 .dbck_flag = true,
1022 };
1023
1024 /* gpio1 */
1025 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1026 { .role = "dbclk", .clk = "gpio1_dbclk" },
1027 };
1028
1029 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1030 .name = "gpio1",
1031 .class = &omap44xx_gpio_hwmod_class,
1032 .clkdm_name = "l4_wkup_clkdm",
1033 .main_clk = "l4_wkup_clk_mux_ck",
1034 .prcm = {
1035 .omap4 = {
1036 .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1037 .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1038 .modulemode = MODULEMODE_HWCTRL,
1039 },
1040 },
1041 .opt_clks = gpio1_opt_clks,
1042 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1043 .dev_attr = &gpio_dev_attr,
1044 };
1045
1046 /* gpio2 */
1047 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1048 { .role = "dbclk", .clk = "gpio2_dbclk" },
1049 };
1050
1051 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1052 .name = "gpio2",
1053 .class = &omap44xx_gpio_hwmod_class,
1054 .clkdm_name = "l4_per_clkdm",
1055 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1056 .main_clk = "l4_div_ck",
1057 .prcm = {
1058 .omap4 = {
1059 .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1060 .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1061 .modulemode = MODULEMODE_HWCTRL,
1062 },
1063 },
1064 .opt_clks = gpio2_opt_clks,
1065 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1066 .dev_attr = &gpio_dev_attr,
1067 };
1068
1069 /* gpio3 */
1070 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1071 { .role = "dbclk", .clk = "gpio3_dbclk" },
1072 };
1073
1074 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1075 .name = "gpio3",
1076 .class = &omap44xx_gpio_hwmod_class,
1077 .clkdm_name = "l4_per_clkdm",
1078 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1079 .main_clk = "l4_div_ck",
1080 .prcm = {
1081 .omap4 = {
1082 .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1083 .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1084 .modulemode = MODULEMODE_HWCTRL,
1085 },
1086 },
1087 .opt_clks = gpio3_opt_clks,
1088 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1089 .dev_attr = &gpio_dev_attr,
1090 };
1091
1092 /* gpio4 */
1093 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1094 { .role = "dbclk", .clk = "gpio4_dbclk" },
1095 };
1096
1097 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1098 .name = "gpio4",
1099 .class = &omap44xx_gpio_hwmod_class,
1100 .clkdm_name = "l4_per_clkdm",
1101 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1102 .main_clk = "l4_div_ck",
1103 .prcm = {
1104 .omap4 = {
1105 .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1106 .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1107 .modulemode = MODULEMODE_HWCTRL,
1108 },
1109 },
1110 .opt_clks = gpio4_opt_clks,
1111 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1112 .dev_attr = &gpio_dev_attr,
1113 };
1114
1115 /* gpio5 */
1116 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1117 { .role = "dbclk", .clk = "gpio5_dbclk" },
1118 };
1119
1120 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1121 .name = "gpio5",
1122 .class = &omap44xx_gpio_hwmod_class,
1123 .clkdm_name = "l4_per_clkdm",
1124 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1125 .main_clk = "l4_div_ck",
1126 .prcm = {
1127 .omap4 = {
1128 .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1129 .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1130 .modulemode = MODULEMODE_HWCTRL,
1131 },
1132 },
1133 .opt_clks = gpio5_opt_clks,
1134 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1135 .dev_attr = &gpio_dev_attr,
1136 };
1137
1138 /* gpio6 */
1139 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1140 { .role = "dbclk", .clk = "gpio6_dbclk" },
1141 };
1142
1143 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1144 .name = "gpio6",
1145 .class = &omap44xx_gpio_hwmod_class,
1146 .clkdm_name = "l4_per_clkdm",
1147 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1148 .main_clk = "l4_div_ck",
1149 .prcm = {
1150 .omap4 = {
1151 .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1152 .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1153 .modulemode = MODULEMODE_HWCTRL,
1154 },
1155 },
1156 .opt_clks = gpio6_opt_clks,
1157 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1158 .dev_attr = &gpio_dev_attr,
1159 };
1160
1161 /*
1162 * 'gpmc' class
1163 * general purpose memory controller
1164 */
1165
1166 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1167 .rev_offs = 0x0000,
1168 .sysc_offs = 0x0010,
1169 .syss_offs = 0x0014,
1170 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1171 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1172 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1173 .sysc_fields = &omap_hwmod_sysc_type1,
1174 };
1175
1176 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1177 .name = "gpmc",
1178 .sysc = &omap44xx_gpmc_sysc,
1179 };
1180
1181 /* gpmc */
1182 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1183 .name = "gpmc",
1184 .class = &omap44xx_gpmc_hwmod_class,
1185 .clkdm_name = "l3_2_clkdm",
1186 /*
1187 * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
1188 * block. It is not being added due to any known bugs with
1189 * resetting the GPMC IP block, but rather because any timings
1190 * set by the bootloader are not being correctly programmed by
1191 * the kernel from the board file or DT data.
1192 * HWMOD_INIT_NO_RESET should be removed ASAP.
1193 */
1194 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1195 .prcm = {
1196 .omap4 = {
1197 .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1198 .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1199 .modulemode = MODULEMODE_HWCTRL,
1200 },
1201 },
1202 };
1203
1204 /*
1205 * 'gpu' class
1206 * 2d/3d graphics accelerator
1207 */
1208
1209 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1210 .rev_offs = 0x1fc00,
1211 .sysc_offs = 0x1fc10,
1212 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1213 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1214 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1215 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1216 .sysc_fields = &omap_hwmod_sysc_type2,
1217 };
1218
1219 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1220 .name = "gpu",
1221 .sysc = &omap44xx_gpu_sysc,
1222 };
1223
1224 /* gpu */
1225 static struct omap_hwmod omap44xx_gpu_hwmod = {
1226 .name = "gpu",
1227 .class = &omap44xx_gpu_hwmod_class,
1228 .clkdm_name = "l3_gfx_clkdm",
1229 .main_clk = "sgx_clk_mux",
1230 .prcm = {
1231 .omap4 = {
1232 .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1233 .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1234 .modulemode = MODULEMODE_SWCTRL,
1235 },
1236 },
1237 };
1238
1239 /*
1240 * 'hdq1w' class
1241 * hdq / 1-wire serial interface controller
1242 */
1243
1244 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1245 .rev_offs = 0x0000,
1246 .sysc_offs = 0x0014,
1247 .syss_offs = 0x0018,
1248 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1249 SYSS_HAS_RESET_STATUS),
1250 .sysc_fields = &omap_hwmod_sysc_type1,
1251 };
1252
1253 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1254 .name = "hdq1w",
1255 .sysc = &omap44xx_hdq1w_sysc,
1256 };
1257
1258 /* hdq1w */
1259 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1260 .name = "hdq1w",
1261 .class = &omap44xx_hdq1w_hwmod_class,
1262 .clkdm_name = "l4_per_clkdm",
1263 .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */
1264 .main_clk = "func_12m_fclk",
1265 .prcm = {
1266 .omap4 = {
1267 .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1268 .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1269 .modulemode = MODULEMODE_SWCTRL,
1270 },
1271 },
1272 };
1273
1274 /*
1275 * 'hsi' class
1276 * mipi high-speed synchronous serial interface (multichannel and full-duplex
1277 * serial if)
1278 */
1279
1280 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1281 .rev_offs = 0x0000,
1282 .sysc_offs = 0x0010,
1283 .syss_offs = 0x0014,
1284 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1285 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1286 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1287 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1288 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1289 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1290 .sysc_fields = &omap_hwmod_sysc_type1,
1291 };
1292
1293 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1294 .name = "hsi",
1295 .sysc = &omap44xx_hsi_sysc,
1296 };
1297
1298 /* hsi */
1299 static struct omap_hwmod omap44xx_hsi_hwmod = {
1300 .name = "hsi",
1301 .class = &omap44xx_hsi_hwmod_class,
1302 .clkdm_name = "l3_init_clkdm",
1303 .main_clk = "hsi_fck",
1304 .prcm = {
1305 .omap4 = {
1306 .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1307 .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1308 .modulemode = MODULEMODE_HWCTRL,
1309 },
1310 },
1311 };
1312
1313 /*
1314 * 'i2c' class
1315 * multimaster high-speed i2c controller
1316 */
1317
1318 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1319 .sysc_offs = 0x0010,
1320 .syss_offs = 0x0090,
1321 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1322 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1323 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1324 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1325 SIDLE_SMART_WKUP),
1326 .clockact = CLOCKACT_TEST_ICLK,
1327 .sysc_fields = &omap_hwmod_sysc_type1,
1328 };
1329
1330 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1331 .name = "i2c",
1332 .sysc = &omap44xx_i2c_sysc,
1333 .rev = OMAP_I2C_IP_VERSION_2,
1334 .reset = &omap_i2c_reset,
1335 };
1336
1337 static struct omap_i2c_dev_attr i2c_dev_attr = {
1338 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1339 };
1340
1341 /* i2c1 */
1342 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1343 .name = "i2c1",
1344 .class = &omap44xx_i2c_hwmod_class,
1345 .clkdm_name = "l4_per_clkdm",
1346 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1347 .main_clk = "func_96m_fclk",
1348 .prcm = {
1349 .omap4 = {
1350 .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1351 .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1352 .modulemode = MODULEMODE_SWCTRL,
1353 },
1354 },
1355 .dev_attr = &i2c_dev_attr,
1356 };
1357
1358 /* i2c2 */
1359 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1360 .name = "i2c2",
1361 .class = &omap44xx_i2c_hwmod_class,
1362 .clkdm_name = "l4_per_clkdm",
1363 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1364 .main_clk = "func_96m_fclk",
1365 .prcm = {
1366 .omap4 = {
1367 .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1368 .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1369 .modulemode = MODULEMODE_SWCTRL,
1370 },
1371 },
1372 .dev_attr = &i2c_dev_attr,
1373 };
1374
1375 /* i2c3 */
1376 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1377 .name = "i2c3",
1378 .class = &omap44xx_i2c_hwmod_class,
1379 .clkdm_name = "l4_per_clkdm",
1380 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1381 .main_clk = "func_96m_fclk",
1382 .prcm = {
1383 .omap4 = {
1384 .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1385 .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1386 .modulemode = MODULEMODE_SWCTRL,
1387 },
1388 },
1389 .dev_attr = &i2c_dev_attr,
1390 };
1391
1392 /* i2c4 */
1393 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1394 .name = "i2c4",
1395 .class = &omap44xx_i2c_hwmod_class,
1396 .clkdm_name = "l4_per_clkdm",
1397 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1398 .main_clk = "func_96m_fclk",
1399 .prcm = {
1400 .omap4 = {
1401 .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1402 .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1403 .modulemode = MODULEMODE_SWCTRL,
1404 },
1405 },
1406 .dev_attr = &i2c_dev_attr,
1407 };
1408
1409 /*
1410 * 'ipu' class
1411 * imaging processor unit
1412 */
1413
1414 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1415 .name = "ipu",
1416 };
1417
1418 /* ipu */
1419 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1420 { .name = "cpu0", .rst_shift = 0 },
1421 { .name = "cpu1", .rst_shift = 1 },
1422 };
1423
1424 static struct omap_hwmod omap44xx_ipu_hwmod = {
1425 .name = "ipu",
1426 .class = &omap44xx_ipu_hwmod_class,
1427 .clkdm_name = "ducati_clkdm",
1428 .rst_lines = omap44xx_ipu_resets,
1429 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
1430 .main_clk = "ducati_clk_mux_ck",
1431 .prcm = {
1432 .omap4 = {
1433 .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1434 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1435 .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1436 .modulemode = MODULEMODE_HWCTRL,
1437 },
1438 },
1439 };
1440
1441 /*
1442 * 'iss' class
1443 * external images sensor pixel data processor
1444 */
1445
1446 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1447 .rev_offs = 0x0000,
1448 .sysc_offs = 0x0010,
1449 /*
1450 * ISS needs 100 OCP clk cycles delay after a softreset before
1451 * accessing sysconfig again.
1452 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1453 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1454 *
1455 * TODO: Indicate errata when available.
1456 */
1457 .srst_udelay = 2,
1458 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1459 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1460 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1461 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1462 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1463 .sysc_fields = &omap_hwmod_sysc_type2,
1464 };
1465
1466 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1467 .name = "iss",
1468 .sysc = &omap44xx_iss_sysc,
1469 };
1470
1471 /* iss */
1472 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1473 { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1474 };
1475
1476 static struct omap_hwmod omap44xx_iss_hwmod = {
1477 .name = "iss",
1478 .class = &omap44xx_iss_hwmod_class,
1479 .clkdm_name = "iss_clkdm",
1480 .main_clk = "ducati_clk_mux_ck",
1481 .prcm = {
1482 .omap4 = {
1483 .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1484 .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1485 .modulemode = MODULEMODE_SWCTRL,
1486 },
1487 },
1488 .opt_clks = iss_opt_clks,
1489 .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
1490 };
1491
1492 /*
1493 * 'iva' class
1494 * multi-standard video encoder/decoder hardware accelerator
1495 */
1496
1497 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1498 .name = "iva",
1499 };
1500
1501 /* iva */
1502 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1503 { .name = "seq0", .rst_shift = 0 },
1504 { .name = "seq1", .rst_shift = 1 },
1505 { .name = "logic", .rst_shift = 2 },
1506 };
1507
1508 static struct omap_hwmod omap44xx_iva_hwmod = {
1509 .name = "iva",
1510 .class = &omap44xx_iva_hwmod_class,
1511 .clkdm_name = "ivahd_clkdm",
1512 .rst_lines = omap44xx_iva_resets,
1513 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
1514 .main_clk = "dpll_iva_m5x2_ck",
1515 .prcm = {
1516 .omap4 = {
1517 .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1518 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1519 .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1520 .modulemode = MODULEMODE_HWCTRL,
1521 },
1522 },
1523 };
1524
1525 /*
1526 * 'kbd' class
1527 * keyboard controller
1528 */
1529
1530 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1531 .rev_offs = 0x0000,
1532 .sysc_offs = 0x0010,
1533 .syss_offs = 0x0014,
1534 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1535 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1536 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1537 SYSS_HAS_RESET_STATUS),
1538 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1539 .sysc_fields = &omap_hwmod_sysc_type1,
1540 };
1541
1542 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1543 .name = "kbd",
1544 .sysc = &omap44xx_kbd_sysc,
1545 };
1546
1547 /* kbd */
1548 static struct omap_hwmod omap44xx_kbd_hwmod = {
1549 .name = "kbd",
1550 .class = &omap44xx_kbd_hwmod_class,
1551 .clkdm_name = "l4_wkup_clkdm",
1552 .main_clk = "sys_32k_ck",
1553 .prcm = {
1554 .omap4 = {
1555 .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1556 .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1557 .modulemode = MODULEMODE_SWCTRL,
1558 },
1559 },
1560 };
1561
1562 /*
1563 * 'mailbox' class
1564 * mailbox module allowing communication between the on-chip processors using a
1565 * queued mailbox-interrupt mechanism.
1566 */
1567
1568 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1569 .rev_offs = 0x0000,
1570 .sysc_offs = 0x0010,
1571 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1572 SYSC_HAS_SOFTRESET),
1573 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1574 .sysc_fields = &omap_hwmod_sysc_type2,
1575 };
1576
1577 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1578 .name = "mailbox",
1579 .sysc = &omap44xx_mailbox_sysc,
1580 };
1581
1582 /* mailbox */
1583 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1584 .name = "mailbox",
1585 .class = &omap44xx_mailbox_hwmod_class,
1586 .clkdm_name = "l4_cfg_clkdm",
1587 .prcm = {
1588 .omap4 = {
1589 .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1590 .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1591 },
1592 },
1593 };
1594
1595 /*
1596 * 'mcasp' class
1597 * multi-channel audio serial port controller
1598 */
1599
1600 /* The IP is not compliant to type1 / type2 scheme */
1601 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1602 .sidle_shift = 0,
1603 };
1604
1605 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1606 .sysc_offs = 0x0004,
1607 .sysc_flags = SYSC_HAS_SIDLEMODE,
1608 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1609 SIDLE_SMART_WKUP),
1610 .sysc_fields = &omap_hwmod_sysc_type_mcasp,
1611 };
1612
1613 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1614 .name = "mcasp",
1615 .sysc = &omap44xx_mcasp_sysc,
1616 };
1617
1618 /* mcasp */
1619 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1620 .name = "mcasp",
1621 .class = &omap44xx_mcasp_hwmod_class,
1622 .clkdm_name = "abe_clkdm",
1623 .main_clk = "func_mcasp_abe_gfclk",
1624 .prcm = {
1625 .omap4 = {
1626 .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1627 .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1628 .modulemode = MODULEMODE_SWCTRL,
1629 },
1630 },
1631 };
1632
1633 /*
1634 * 'mcbsp' class
1635 * multi channel buffered serial port controller
1636 */
1637
1638 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1639 .sysc_offs = 0x008c,
1640 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1641 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1642 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1643 .sysc_fields = &omap_hwmod_sysc_type1,
1644 };
1645
1646 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1647 .name = "mcbsp",
1648 .sysc = &omap44xx_mcbsp_sysc,
1649 .rev = MCBSP_CONFIG_TYPE4,
1650 };
1651
1652 /* mcbsp1 */
1653 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1654 { .role = "pad_fck", .clk = "pad_clks_ck" },
1655 { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1656 };
1657
1658 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1659 .name = "mcbsp1",
1660 .class = &omap44xx_mcbsp_hwmod_class,
1661 .clkdm_name = "abe_clkdm",
1662 .main_clk = "func_mcbsp1_gfclk",
1663 .prcm = {
1664 .omap4 = {
1665 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1666 .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1667 .modulemode = MODULEMODE_SWCTRL,
1668 },
1669 },
1670 .opt_clks = mcbsp1_opt_clks,
1671 .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
1672 };
1673
1674 /* mcbsp2 */
1675 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1676 { .role = "pad_fck", .clk = "pad_clks_ck" },
1677 { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
1678 };
1679
1680 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
1681 .name = "mcbsp2",
1682 .class = &omap44xx_mcbsp_hwmod_class,
1683 .clkdm_name = "abe_clkdm",
1684 .main_clk = "func_mcbsp2_gfclk",
1685 .prcm = {
1686 .omap4 = {
1687 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
1688 .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
1689 .modulemode = MODULEMODE_SWCTRL,
1690 },
1691 },
1692 .opt_clks = mcbsp2_opt_clks,
1693 .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
1694 };
1695
1696 /* mcbsp3 */
1697 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
1698 { .role = "pad_fck", .clk = "pad_clks_ck" },
1699 { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
1700 };
1701
1702 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
1703 .name = "mcbsp3",
1704 .class = &omap44xx_mcbsp_hwmod_class,
1705 .clkdm_name = "abe_clkdm",
1706 .main_clk = "func_mcbsp3_gfclk",
1707 .prcm = {
1708 .omap4 = {
1709 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
1710 .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
1711 .modulemode = MODULEMODE_SWCTRL,
1712 },
1713 },
1714 .opt_clks = mcbsp3_opt_clks,
1715 .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
1716 };
1717
1718 /* mcbsp4 */
1719 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
1720 { .role = "pad_fck", .clk = "pad_clks_ck" },
1721 { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
1722 };
1723
1724 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
1725 .name = "mcbsp4",
1726 .class = &omap44xx_mcbsp_hwmod_class,
1727 .clkdm_name = "l4_per_clkdm",
1728 .main_clk = "per_mcbsp4_gfclk",
1729 .prcm = {
1730 .omap4 = {
1731 .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
1732 .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
1733 .modulemode = MODULEMODE_SWCTRL,
1734 },
1735 },
1736 .opt_clks = mcbsp4_opt_clks,
1737 .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks),
1738 };
1739
1740 /*
1741 * 'mcpdm' class
1742 * multi channel pdm controller (proprietary interface with phoenix power
1743 * ic)
1744 */
1745
1746 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
1747 .rev_offs = 0x0000,
1748 .sysc_offs = 0x0010,
1749 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1750 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1751 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1752 SIDLE_SMART_WKUP),
1753 .sysc_fields = &omap_hwmod_sysc_type2,
1754 };
1755
1756 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
1757 .name = "mcpdm",
1758 .sysc = &omap44xx_mcpdm_sysc,
1759 };
1760
1761 /* mcpdm */
1762 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
1763 .name = "mcpdm",
1764 .class = &omap44xx_mcpdm_hwmod_class,
1765 .clkdm_name = "abe_clkdm",
1766 /*
1767 * It's suspected that the McPDM requires an off-chip main
1768 * functional clock, controlled via I2C. This IP block is
1769 * currently reset very early during boot, before I2C is
1770 * available, so it doesn't seem that we have any choice in
1771 * the kernel other than to avoid resetting it.
1772 *
1773 * Also, McPDM needs to be configured to NO_IDLE mode when it
1774 * is in used otherwise vital clocks will be gated which
1775 * results 'slow motion' audio playback.
1776 */
1777 .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
1778 .main_clk = "pad_clks_ck",
1779 .prcm = {
1780 .omap4 = {
1781 .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
1782 .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
1783 .modulemode = MODULEMODE_SWCTRL,
1784 },
1785 },
1786 };
1787
1788 /*
1789 * 'mcspi' class
1790 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1791 * bus
1792 */
1793
1794 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
1795 .rev_offs = 0x0000,
1796 .sysc_offs = 0x0010,
1797 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1798 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1799 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1800 SIDLE_SMART_WKUP),
1801 .sysc_fields = &omap_hwmod_sysc_type2,
1802 };
1803
1804 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
1805 .name = "mcspi",
1806 .sysc = &omap44xx_mcspi_sysc,
1807 .rev = OMAP4_MCSPI_REV,
1808 };
1809
1810 /* mcspi1 */
1811 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
1812 { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
1813 { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
1814 { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
1815 { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
1816 { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
1817 { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
1818 { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
1819 { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
1820 { .dma_req = -1 }
1821 };
1822
1823 /* mcspi1 dev_attr */
1824 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1825 .num_chipselect = 4,
1826 };
1827
1828 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
1829 .name = "mcspi1",
1830 .class = &omap44xx_mcspi_hwmod_class,
1831 .clkdm_name = "l4_per_clkdm",
1832 .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
1833 .main_clk = "func_48m_fclk",
1834 .prcm = {
1835 .omap4 = {
1836 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1837 .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1838 .modulemode = MODULEMODE_SWCTRL,
1839 },
1840 },
1841 .dev_attr = &mcspi1_dev_attr,
1842 };
1843
1844 /* mcspi2 */
1845 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
1846 { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
1847 { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
1848 { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
1849 { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
1850 { .dma_req = -1 }
1851 };
1852
1853 /* mcspi2 dev_attr */
1854 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1855 .num_chipselect = 2,
1856 };
1857
1858 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
1859 .name = "mcspi2",
1860 .class = &omap44xx_mcspi_hwmod_class,
1861 .clkdm_name = "l4_per_clkdm",
1862 .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
1863 .main_clk = "func_48m_fclk",
1864 .prcm = {
1865 .omap4 = {
1866 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1867 .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1868 .modulemode = MODULEMODE_SWCTRL,
1869 },
1870 },
1871 .dev_attr = &mcspi2_dev_attr,
1872 };
1873
1874 /* mcspi3 */
1875 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
1876 { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
1877 { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
1878 { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
1879 { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
1880 { .dma_req = -1 }
1881 };
1882
1883 /* mcspi3 dev_attr */
1884 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1885 .num_chipselect = 2,
1886 };
1887
1888 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
1889 .name = "mcspi3",
1890 .class = &omap44xx_mcspi_hwmod_class,
1891 .clkdm_name = "l4_per_clkdm",
1892 .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
1893 .main_clk = "func_48m_fclk",
1894 .prcm = {
1895 .omap4 = {
1896 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1897 .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1898 .modulemode = MODULEMODE_SWCTRL,
1899 },
1900 },
1901 .dev_attr = &mcspi3_dev_attr,
1902 };
1903
1904 /* mcspi4 */
1905 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
1906 { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
1907 { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
1908 { .dma_req = -1 }
1909 };
1910
1911 /* mcspi4 dev_attr */
1912 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1913 .num_chipselect = 1,
1914 };
1915
1916 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
1917 .name = "mcspi4",
1918 .class = &omap44xx_mcspi_hwmod_class,
1919 .clkdm_name = "l4_per_clkdm",
1920 .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
1921 .main_clk = "func_48m_fclk",
1922 .prcm = {
1923 .omap4 = {
1924 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1925 .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1926 .modulemode = MODULEMODE_SWCTRL,
1927 },
1928 },
1929 .dev_attr = &mcspi4_dev_attr,
1930 };
1931
1932 /*
1933 * 'mmc' class
1934 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
1935 */
1936
1937 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
1938 .rev_offs = 0x0000,
1939 .sysc_offs = 0x0010,
1940 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1941 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1942 SYSC_HAS_SOFTRESET),
1943 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1944 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1945 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1946 .sysc_fields = &omap_hwmod_sysc_type2,
1947 };
1948
1949 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
1950 .name = "mmc",
1951 .sysc = &omap44xx_mmc_sysc,
1952 };
1953
1954 /* mmc1 */
1955 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
1956 { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
1957 { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
1958 { .dma_req = -1 }
1959 };
1960
1961 /* mmc1 dev_attr */
1962 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1963 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1964 };
1965
1966 static struct omap_hwmod omap44xx_mmc1_hwmod = {
1967 .name = "mmc1",
1968 .class = &omap44xx_mmc_hwmod_class,
1969 .clkdm_name = "l3_init_clkdm",
1970 .sdma_reqs = omap44xx_mmc1_sdma_reqs,
1971 .main_clk = "hsmmc1_fclk",
1972 .prcm = {
1973 .omap4 = {
1974 .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1975 .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1976 .modulemode = MODULEMODE_SWCTRL,
1977 },
1978 },
1979 .dev_attr = &mmc1_dev_attr,
1980 };
1981
1982 /* mmc2 */
1983 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
1984 { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
1985 { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
1986 { .dma_req = -1 }
1987 };
1988
1989 static struct omap_hwmod omap44xx_mmc2_hwmod = {
1990 .name = "mmc2",
1991 .class = &omap44xx_mmc_hwmod_class,
1992 .clkdm_name = "l3_init_clkdm",
1993 .sdma_reqs = omap44xx_mmc2_sdma_reqs,
1994 .main_clk = "hsmmc2_fclk",
1995 .prcm = {
1996 .omap4 = {
1997 .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1998 .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1999 .modulemode = MODULEMODE_SWCTRL,
2000 },
2001 },
2002 };
2003
2004 /* mmc3 */
2005 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2006 { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2007 { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2008 { .dma_req = -1 }
2009 };
2010
2011 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2012 .name = "mmc3",
2013 .class = &omap44xx_mmc_hwmod_class,
2014 .clkdm_name = "l4_per_clkdm",
2015 .sdma_reqs = omap44xx_mmc3_sdma_reqs,
2016 .main_clk = "func_48m_fclk",
2017 .prcm = {
2018 .omap4 = {
2019 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2020 .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2021 .modulemode = MODULEMODE_SWCTRL,
2022 },
2023 },
2024 };
2025
2026 /* mmc4 */
2027 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2028 { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2029 { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2030 { .dma_req = -1 }
2031 };
2032
2033 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2034 .name = "mmc4",
2035 .class = &omap44xx_mmc_hwmod_class,
2036 .clkdm_name = "l4_per_clkdm",
2037 .sdma_reqs = omap44xx_mmc4_sdma_reqs,
2038 .main_clk = "func_48m_fclk",
2039 .prcm = {
2040 .omap4 = {
2041 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2042 .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2043 .modulemode = MODULEMODE_SWCTRL,
2044 },
2045 },
2046 };
2047
2048 /* mmc5 */
2049 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2050 { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2051 { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2052 { .dma_req = -1 }
2053 };
2054
2055 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2056 .name = "mmc5",
2057 .class = &omap44xx_mmc_hwmod_class,
2058 .clkdm_name = "l4_per_clkdm",
2059 .sdma_reqs = omap44xx_mmc5_sdma_reqs,
2060 .main_clk = "func_48m_fclk",
2061 .prcm = {
2062 .omap4 = {
2063 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2064 .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2065 .modulemode = MODULEMODE_SWCTRL,
2066 },
2067 },
2068 };
2069
2070 /*
2071 * 'mmu' class
2072 * The memory management unit performs virtual to physical address translation
2073 * for its requestors.
2074 */
2075
2076 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2077 .rev_offs = 0x000,
2078 .sysc_offs = 0x010,
2079 .syss_offs = 0x014,
2080 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2081 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2082 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2083 .sysc_fields = &omap_hwmod_sysc_type1,
2084 };
2085
2086 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
2087 .name = "mmu",
2088 .sysc = &mmu_sysc,
2089 };
2090
2091 /* mmu ipu */
2092
2093 static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
2094 .nr_tlb_entries = 32,
2095 };
2096
2097 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2098 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2099 { .name = "mmu_cache", .rst_shift = 2 },
2100 };
2101
2102 static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = {
2103 {
2104 .pa_start = 0x55082000,
2105 .pa_end = 0x550820ff,
2106 .flags = ADDR_TYPE_RT,
2107 },
2108 { }
2109 };
2110
2111 /* l3_main_2 -> mmu_ipu */
2112 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
2113 .master = &omap44xx_l3_main_2_hwmod,
2114 .slave = &omap44xx_mmu_ipu_hwmod,
2115 .clk = "l3_div_ck",
2116 .addr = omap44xx_mmu_ipu_addrs,
2117 .user = OCP_USER_MPU | OCP_USER_SDMA,
2118 };
2119
2120 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2121 .name = "mmu_ipu",
2122 .class = &omap44xx_mmu_hwmod_class,
2123 .clkdm_name = "ducati_clkdm",
2124 .rst_lines = omap44xx_mmu_ipu_resets,
2125 .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2126 .main_clk = "ducati_clk_mux_ck",
2127 .prcm = {
2128 .omap4 = {
2129 .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2130 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2131 .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2132 .modulemode = MODULEMODE_HWCTRL,
2133 },
2134 },
2135 .dev_attr = &mmu_ipu_dev_attr,
2136 };
2137
2138 /* mmu dsp */
2139
2140 static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
2141 .nr_tlb_entries = 32,
2142 };
2143
2144 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2145 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2146 { .name = "mmu_cache", .rst_shift = 1 },
2147 };
2148
2149 static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = {
2150 {
2151 .pa_start = 0x4a066000,
2152 .pa_end = 0x4a0660ff,
2153 .flags = ADDR_TYPE_RT,
2154 },
2155 { }
2156 };
2157
2158 /* l4_cfg -> dsp */
2159 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
2160 .master = &omap44xx_l4_cfg_hwmod,
2161 .slave = &omap44xx_mmu_dsp_hwmod,
2162 .clk = "l4_div_ck",
2163 .addr = omap44xx_mmu_dsp_addrs,
2164 .user = OCP_USER_MPU | OCP_USER_SDMA,
2165 };
2166
2167 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2168 .name = "mmu_dsp",
2169 .class = &omap44xx_mmu_hwmod_class,
2170 .clkdm_name = "tesla_clkdm",
2171 .rst_lines = omap44xx_mmu_dsp_resets,
2172 .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2173 .main_clk = "dpll_iva_m4x2_ck",
2174 .prcm = {
2175 .omap4 = {
2176 .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
2177 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
2178 .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
2179 .modulemode = MODULEMODE_HWCTRL,
2180 },
2181 },
2182 .dev_attr = &mmu_dsp_dev_attr,
2183 };
2184
2185 /*
2186 * 'mpu' class
2187 * mpu sub-system
2188 */
2189
2190 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2191 .name = "mpu",
2192 };
2193
2194 /* mpu */
2195 static struct omap_hwmod omap44xx_mpu_hwmod = {
2196 .name = "mpu",
2197 .class = &omap44xx_mpu_hwmod_class,
2198 .clkdm_name = "mpuss_clkdm",
2199 .flags = HWMOD_INIT_NO_IDLE,
2200 .main_clk = "dpll_mpu_m2_ck",
2201 .prcm = {
2202 .omap4 = {
2203 .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2204 .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2205 },
2206 },
2207 };
2208
2209 /*
2210 * 'ocmc_ram' class
2211 * top-level core on-chip ram
2212 */
2213
2214 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2215 .name = "ocmc_ram",
2216 };
2217
2218 /* ocmc_ram */
2219 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2220 .name = "ocmc_ram",
2221 .class = &omap44xx_ocmc_ram_hwmod_class,
2222 .clkdm_name = "l3_2_clkdm",
2223 .prcm = {
2224 .omap4 = {
2225 .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2226 .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2227 },
2228 },
2229 };
2230
2231 /*
2232 * 'ocp2scp' class
2233 * bridge to transform ocp interface protocol to scp (serial control port)
2234 * protocol
2235 */
2236
2237 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2238 .rev_offs = 0x0000,
2239 .sysc_offs = 0x0010,
2240 .syss_offs = 0x0014,
2241 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2242 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2243 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2244 .sysc_fields = &omap_hwmod_sysc_type1,
2245 };
2246
2247 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2248 .name = "ocp2scp",
2249 .sysc = &omap44xx_ocp2scp_sysc,
2250 };
2251
2252 /* ocp2scp_usb_phy */
2253 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2254 .name = "ocp2scp_usb_phy",
2255 .class = &omap44xx_ocp2scp_hwmod_class,
2256 .clkdm_name = "l3_init_clkdm",
2257 /*
2258 * ocp2scp_usb_phy_phy_48m is provided by the OMAP4 PRCM IP
2259 * block as an "optional clock," and normally should never be
2260 * specified as the main_clk for an OMAP IP block. However it
2261 * turns out that this clock is actually the main clock for
2262 * the ocp2scp_usb_phy IP block:
2263 * http://lists.infradead.org/pipermail/linux-arm-kernel/2012-September/119943.html
2264 * So listing ocp2scp_usb_phy_phy_48m as a main_clk here seems
2265 * to be the best workaround.
2266 */
2267 .main_clk = "ocp2scp_usb_phy_phy_48m",
2268 .prcm = {
2269 .omap4 = {
2270 .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2271 .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2272 .modulemode = MODULEMODE_HWCTRL,
2273 },
2274 },
2275 };
2276
2277 /*
2278 * 'prcm' class
2279 * power and reset manager (part of the prcm infrastructure) + clock manager 2
2280 * + clock manager 1 (in always on power domain) + local prm in mpu
2281 */
2282
2283 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2284 .name = "prcm",
2285 };
2286
2287 /* prcm_mpu */
2288 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2289 .name = "prcm_mpu",
2290 .class = &omap44xx_prcm_hwmod_class,
2291 .clkdm_name = "l4_wkup_clkdm",
2292 .flags = HWMOD_NO_IDLEST,
2293 .prcm = {
2294 .omap4 = {
2295 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2296 },
2297 },
2298 };
2299
2300 /* cm_core_aon */
2301 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2302 .name = "cm_core_aon",
2303 .class = &omap44xx_prcm_hwmod_class,
2304 .flags = HWMOD_NO_IDLEST,
2305 .prcm = {
2306 .omap4 = {
2307 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2308 },
2309 },
2310 };
2311
2312 /* cm_core */
2313 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2314 .name = "cm_core",
2315 .class = &omap44xx_prcm_hwmod_class,
2316 .flags = HWMOD_NO_IDLEST,
2317 .prcm = {
2318 .omap4 = {
2319 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2320 },
2321 },
2322 };
2323
2324 /* prm */
2325 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2326 { .name = "rst_global_warm_sw", .rst_shift = 0 },
2327 { .name = "rst_global_cold_sw", .rst_shift = 1 },
2328 };
2329
2330 static struct omap_hwmod omap44xx_prm_hwmod = {
2331 .name = "prm",
2332 .class = &omap44xx_prcm_hwmod_class,
2333 .rst_lines = omap44xx_prm_resets,
2334 .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets),
2335 };
2336
2337 /*
2338 * 'scrm' class
2339 * system clock and reset manager
2340 */
2341
2342 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2343 .name = "scrm",
2344 };
2345
2346 /* scrm */
2347 static struct omap_hwmod omap44xx_scrm_hwmod = {
2348 .name = "scrm",
2349 .class = &omap44xx_scrm_hwmod_class,
2350 .clkdm_name = "l4_wkup_clkdm",
2351 .prcm = {
2352 .omap4 = {
2353 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2354 },
2355 },
2356 };
2357
2358 /*
2359 * 'sl2if' class
2360 * shared level 2 memory interface
2361 */
2362
2363 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2364 .name = "sl2if",
2365 };
2366
2367 /* sl2if */
2368 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2369 .name = "sl2if",
2370 .class = &omap44xx_sl2if_hwmod_class,
2371 .clkdm_name = "ivahd_clkdm",
2372 .prcm = {
2373 .omap4 = {
2374 .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2375 .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2376 .modulemode = MODULEMODE_HWCTRL,
2377 },
2378 },
2379 };
2380
2381 /*
2382 * 'slimbus' class
2383 * bidirectional, multi-drop, multi-channel two-line serial interface between
2384 * the device and external components
2385 */
2386
2387 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2388 .rev_offs = 0x0000,
2389 .sysc_offs = 0x0010,
2390 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2391 SYSC_HAS_SOFTRESET),
2392 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2393 SIDLE_SMART_WKUP),
2394 .sysc_fields = &omap_hwmod_sysc_type2,
2395 };
2396
2397 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2398 .name = "slimbus",
2399 .sysc = &omap44xx_slimbus_sysc,
2400 };
2401
2402 /* slimbus1 */
2403 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2404 { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2405 { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2406 { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2407 { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2408 };
2409
2410 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2411 .name = "slimbus1",
2412 .class = &omap44xx_slimbus_hwmod_class,
2413 .clkdm_name = "abe_clkdm",
2414 .prcm = {
2415 .omap4 = {
2416 .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2417 .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2418 .modulemode = MODULEMODE_SWCTRL,
2419 },
2420 },
2421 .opt_clks = slimbus1_opt_clks,
2422 .opt_clks_cnt = ARRAY_SIZE(slimbus1_opt_clks),
2423 };
2424
2425 /* slimbus2 */
2426 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2427 { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2428 { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2429 { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2430 };
2431
2432 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2433 .name = "slimbus2",
2434 .class = &omap44xx_slimbus_hwmod_class,
2435 .clkdm_name = "l4_per_clkdm",
2436 .prcm = {
2437 .omap4 = {
2438 .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2439 .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2440 .modulemode = MODULEMODE_SWCTRL,
2441 },
2442 },
2443 .opt_clks = slimbus2_opt_clks,
2444 .opt_clks_cnt = ARRAY_SIZE(slimbus2_opt_clks),
2445 };
2446
2447 /*
2448 * 'smartreflex' class
2449 * smartreflex module (monitor silicon performance and outputs a measure of
2450 * performance error)
2451 */
2452
2453 /* The IP is not compliant to type1 / type2 scheme */
2454 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2455 .sidle_shift = 24,
2456 .enwkup_shift = 26,
2457 };
2458
2459 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2460 .sysc_offs = 0x0038,
2461 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2462 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2463 SIDLE_SMART_WKUP),
2464 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
2465 };
2466
2467 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2468 .name = "smartreflex",
2469 .sysc = &omap44xx_smartreflex_sysc,
2470 .rev = 2,
2471 };
2472
2473 /* smartreflex_core */
2474 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2475 .sensor_voltdm_name = "core",
2476 };
2477
2478 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2479 .name = "smartreflex_core",
2480 .class = &omap44xx_smartreflex_hwmod_class,
2481 .clkdm_name = "l4_ao_clkdm",
2482
2483 .main_clk = "smartreflex_core_fck",
2484 .prcm = {
2485 .omap4 = {
2486 .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2487 .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2488 .modulemode = MODULEMODE_SWCTRL,
2489 },
2490 },
2491 .dev_attr = &smartreflex_core_dev_attr,
2492 };
2493
2494 /* smartreflex_iva */
2495 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
2496 .sensor_voltdm_name = "iva",
2497 };
2498
2499 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2500 .name = "smartreflex_iva",
2501 .class = &omap44xx_smartreflex_hwmod_class,
2502 .clkdm_name = "l4_ao_clkdm",
2503 .main_clk = "smartreflex_iva_fck",
2504 .prcm = {
2505 .omap4 = {
2506 .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
2507 .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
2508 .modulemode = MODULEMODE_SWCTRL,
2509 },
2510 },
2511 .dev_attr = &smartreflex_iva_dev_attr,
2512 };
2513
2514 /* smartreflex_mpu */
2515 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2516 .sensor_voltdm_name = "mpu",
2517 };
2518
2519 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
2520 .name = "smartreflex_mpu",
2521 .class = &omap44xx_smartreflex_hwmod_class,
2522 .clkdm_name = "l4_ao_clkdm",
2523 .main_clk = "smartreflex_mpu_fck",
2524 .prcm = {
2525 .omap4 = {
2526 .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
2527 .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
2528 .modulemode = MODULEMODE_SWCTRL,
2529 },
2530 },
2531 .dev_attr = &smartreflex_mpu_dev_attr,
2532 };
2533
2534 /*
2535 * 'spinlock' class
2536 * spinlock provides hardware assistance for synchronizing the processes
2537 * running on multiple processors
2538 */
2539
2540 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
2541 .rev_offs = 0x0000,
2542 .sysc_offs = 0x0010,
2543 .syss_offs = 0x0014,
2544 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2545 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2546 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2547 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2548 .sysc_fields = &omap_hwmod_sysc_type1,
2549 };
2550
2551 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
2552 .name = "spinlock",
2553 .sysc = &omap44xx_spinlock_sysc,
2554 };
2555
2556 /* spinlock */
2557 static struct omap_hwmod omap44xx_spinlock_hwmod = {
2558 .name = "spinlock",
2559 .class = &omap44xx_spinlock_hwmod_class,
2560 .clkdm_name = "l4_cfg_clkdm",
2561 .prcm = {
2562 .omap4 = {
2563 .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
2564 .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
2565 },
2566 },
2567 };
2568
2569 /*
2570 * 'timer' class
2571 * general purpose timer module with accurate 1ms tick
2572 * This class contains several variants: ['timer_1ms', 'timer']
2573 */
2574
2575 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
2576 .rev_offs = 0x0000,
2577 .sysc_offs = 0x0010,
2578 .syss_offs = 0x0014,
2579 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2580 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2581 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2582 SYSS_HAS_RESET_STATUS),
2583 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2584 .clockact = CLOCKACT_TEST_ICLK,
2585 .sysc_fields = &omap_hwmod_sysc_type1,
2586 };
2587
2588 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
2589 .name = "timer",
2590 .sysc = &omap44xx_timer_1ms_sysc,
2591 };
2592
2593 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
2594 .rev_offs = 0x0000,
2595 .sysc_offs = 0x0010,
2596 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2597 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2598 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2599 SIDLE_SMART_WKUP),
2600 .sysc_fields = &omap_hwmod_sysc_type2,
2601 };
2602
2603 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
2604 .name = "timer",
2605 .sysc = &omap44xx_timer_sysc,
2606 };
2607
2608 /* always-on timers dev attribute */
2609 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
2610 .timer_capability = OMAP_TIMER_ALWON,
2611 };
2612
2613 /* pwm timers dev attribute */
2614 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
2615 .timer_capability = OMAP_TIMER_HAS_PWM,
2616 };
2617
2618 /* timers with DSP interrupt dev attribute */
2619 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
2620 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
2621 };
2622
2623 /* pwm timers with DSP interrupt dev attribute */
2624 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
2625 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
2626 };
2627
2628 /* timer1 */
2629 static struct omap_hwmod omap44xx_timer1_hwmod = {
2630 .name = "timer1",
2631 .class = &omap44xx_timer_1ms_hwmod_class,
2632 .clkdm_name = "l4_wkup_clkdm",
2633 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2634 .main_clk = "dmt1_clk_mux",
2635 .prcm = {
2636 .omap4 = {
2637 .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2638 .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
2639 .modulemode = MODULEMODE_SWCTRL,
2640 },
2641 },
2642 .dev_attr = &capability_alwon_dev_attr,
2643 };
2644
2645 /* timer2 */
2646 static struct omap_hwmod omap44xx_timer2_hwmod = {
2647 .name = "timer2",
2648 .class = &omap44xx_timer_1ms_hwmod_class,
2649 .clkdm_name = "l4_per_clkdm",
2650 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2651 .main_clk = "cm2_dm2_mux",
2652 .prcm = {
2653 .omap4 = {
2654 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
2655 .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
2656 .modulemode = MODULEMODE_SWCTRL,
2657 },
2658 },
2659 };
2660
2661 /* timer3 */
2662 static struct omap_hwmod omap44xx_timer3_hwmod = {
2663 .name = "timer3",
2664 .class = &omap44xx_timer_hwmod_class,
2665 .clkdm_name = "l4_per_clkdm",
2666 .main_clk = "cm2_dm3_mux",
2667 .prcm = {
2668 .omap4 = {
2669 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
2670 .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
2671 .modulemode = MODULEMODE_SWCTRL,
2672 },
2673 },
2674 };
2675
2676 /* timer4 */
2677 static struct omap_hwmod omap44xx_timer4_hwmod = {
2678 .name = "timer4",
2679 .class = &omap44xx_timer_hwmod_class,
2680 .clkdm_name = "l4_per_clkdm",
2681 .main_clk = "cm2_dm4_mux",
2682 .prcm = {
2683 .omap4 = {
2684 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
2685 .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
2686 .modulemode = MODULEMODE_SWCTRL,
2687 },
2688 },
2689 };
2690
2691 /* timer5 */
2692 static struct omap_hwmod omap44xx_timer5_hwmod = {
2693 .name = "timer5",
2694 .class = &omap44xx_timer_hwmod_class,
2695 .clkdm_name = "abe_clkdm",
2696 .main_clk = "timer5_sync_mux",
2697 .prcm = {
2698 .omap4 = {
2699 .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
2700 .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
2701 .modulemode = MODULEMODE_SWCTRL,
2702 },
2703 },
2704 .dev_attr = &capability_dsp_dev_attr,
2705 };
2706
2707 /* timer6 */
2708 static struct omap_hwmod omap44xx_timer6_hwmod = {
2709 .name = "timer6",
2710 .class = &omap44xx_timer_hwmod_class,
2711 .clkdm_name = "abe_clkdm",
2712 .main_clk = "timer6_sync_mux",
2713 .prcm = {
2714 .omap4 = {
2715 .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
2716 .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
2717 .modulemode = MODULEMODE_SWCTRL,
2718 },
2719 },
2720 .dev_attr = &capability_dsp_dev_attr,
2721 };
2722
2723 /* timer7 */
2724 static struct omap_hwmod omap44xx_timer7_hwmod = {
2725 .name = "timer7",
2726 .class = &omap44xx_timer_hwmod_class,
2727 .clkdm_name = "abe_clkdm",
2728 .main_clk = "timer7_sync_mux",
2729 .prcm = {
2730 .omap4 = {
2731 .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
2732 .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
2733 .modulemode = MODULEMODE_SWCTRL,
2734 },
2735 },
2736 .dev_attr = &capability_dsp_dev_attr,
2737 };
2738
2739 /* timer8 */
2740 static struct omap_hwmod omap44xx_timer8_hwmod = {
2741 .name = "timer8",
2742 .class = &omap44xx_timer_hwmod_class,
2743 .clkdm_name = "abe_clkdm",
2744 .main_clk = "timer8_sync_mux",
2745 .prcm = {
2746 .omap4 = {
2747 .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
2748 .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
2749 .modulemode = MODULEMODE_SWCTRL,
2750 },
2751 },
2752 .dev_attr = &capability_dsp_pwm_dev_attr,
2753 };
2754
2755 /* timer9 */
2756 static struct omap_hwmod omap44xx_timer9_hwmod = {
2757 .name = "timer9",
2758 .class = &omap44xx_timer_hwmod_class,
2759 .clkdm_name = "l4_per_clkdm",
2760 .main_clk = "cm2_dm9_mux",
2761 .prcm = {
2762 .omap4 = {
2763 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
2764 .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
2765 .modulemode = MODULEMODE_SWCTRL,
2766 },
2767 },
2768 .dev_attr = &capability_pwm_dev_attr,
2769 };
2770
2771 /* timer10 */
2772 static struct omap_hwmod omap44xx_timer10_hwmod = {
2773 .name = "timer10",
2774 .class = &omap44xx_timer_1ms_hwmod_class,
2775 .clkdm_name = "l4_per_clkdm",
2776 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2777 .main_clk = "cm2_dm10_mux",
2778 .prcm = {
2779 .omap4 = {
2780 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
2781 .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
2782 .modulemode = MODULEMODE_SWCTRL,
2783 },
2784 },
2785 .dev_attr = &capability_pwm_dev_attr,
2786 };
2787
2788 /* timer11 */
2789 static struct omap_hwmod omap44xx_timer11_hwmod = {
2790 .name = "timer11",
2791 .class = &omap44xx_timer_hwmod_class,
2792 .clkdm_name = "l4_per_clkdm",
2793 .main_clk = "cm2_dm11_mux",
2794 .prcm = {
2795 .omap4 = {
2796 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
2797 .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
2798 .modulemode = MODULEMODE_SWCTRL,
2799 },
2800 },
2801 .dev_attr = &capability_pwm_dev_attr,
2802 };
2803
2804 /*
2805 * 'uart' class
2806 * universal asynchronous receiver/transmitter (uart)
2807 */
2808
2809 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
2810 .rev_offs = 0x0050,
2811 .sysc_offs = 0x0054,
2812 .syss_offs = 0x0058,
2813 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2814 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2815 SYSS_HAS_RESET_STATUS),
2816 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2817 SIDLE_SMART_WKUP),
2818 .sysc_fields = &omap_hwmod_sysc_type1,
2819 };
2820
2821 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
2822 .name = "uart",
2823 .sysc = &omap44xx_uart_sysc,
2824 };
2825
2826 /* uart1 */
2827 static struct omap_hwmod omap44xx_uart1_hwmod = {
2828 .name = "uart1",
2829 .class = &omap44xx_uart_hwmod_class,
2830 .clkdm_name = "l4_per_clkdm",
2831 .flags = HWMOD_SWSUP_SIDLE_ACT,
2832 .main_clk = "func_48m_fclk",
2833 .prcm = {
2834 .omap4 = {
2835 .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
2836 .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
2837 .modulemode = MODULEMODE_SWCTRL,
2838 },
2839 },
2840 };
2841
2842 /* uart2 */
2843 static struct omap_hwmod omap44xx_uart2_hwmod = {
2844 .name = "uart2",
2845 .class = &omap44xx_uart_hwmod_class,
2846 .clkdm_name = "l4_per_clkdm",
2847 .flags = HWMOD_SWSUP_SIDLE_ACT,
2848 .main_clk = "func_48m_fclk",
2849 .prcm = {
2850 .omap4 = {
2851 .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
2852 .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
2853 .modulemode = MODULEMODE_SWCTRL,
2854 },
2855 },
2856 };
2857
2858 /* uart3 */
2859 static struct omap_hwmod omap44xx_uart3_hwmod = {
2860 .name = "uart3",
2861 .class = &omap44xx_uart_hwmod_class,
2862 .clkdm_name = "l4_per_clkdm",
2863 .flags = DEBUG_OMAP4UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
2864 .main_clk = "func_48m_fclk",
2865 .prcm = {
2866 .omap4 = {
2867 .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
2868 .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
2869 .modulemode = MODULEMODE_SWCTRL,
2870 },
2871 },
2872 };
2873
2874 /* uart4 */
2875 static struct omap_hwmod omap44xx_uart4_hwmod = {
2876 .name = "uart4",
2877 .class = &omap44xx_uart_hwmod_class,
2878 .clkdm_name = "l4_per_clkdm",
2879 .flags = DEBUG_OMAP4UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
2880 .main_clk = "func_48m_fclk",
2881 .prcm = {
2882 .omap4 = {
2883 .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
2884 .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
2885 .modulemode = MODULEMODE_SWCTRL,
2886 },
2887 },
2888 };
2889
2890 /*
2891 * 'usb_host_fs' class
2892 * full-speed usb host controller
2893 */
2894
2895 /* The IP is not compliant to type1 / type2 scheme */
2896 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
2897 .midle_shift = 4,
2898 .sidle_shift = 2,
2899 .srst_shift = 1,
2900 };
2901
2902 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
2903 .rev_offs = 0x0000,
2904 .sysc_offs = 0x0210,
2905 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2906 SYSC_HAS_SOFTRESET),
2907 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2908 SIDLE_SMART_WKUP),
2909 .sysc_fields = &omap_hwmod_sysc_type_usb_host_fs,
2910 };
2911
2912 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
2913 .name = "usb_host_fs",
2914 .sysc = &omap44xx_usb_host_fs_sysc,
2915 };
2916
2917 /* usb_host_fs */
2918 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
2919 .name = "usb_host_fs",
2920 .class = &omap44xx_usb_host_fs_hwmod_class,
2921 .clkdm_name = "l3_init_clkdm",
2922 .main_clk = "usb_host_fs_fck",
2923 .prcm = {
2924 .omap4 = {
2925 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
2926 .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
2927 .modulemode = MODULEMODE_SWCTRL,
2928 },
2929 },
2930 };
2931
2932 /*
2933 * 'usb_host_hs' class
2934 * high-speed multi-port usb host controller
2935 */
2936
2937 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
2938 .rev_offs = 0x0000,
2939 .sysc_offs = 0x0010,
2940 .syss_offs = 0x0014,
2941 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2942 SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS),
2943 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2944 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2945 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2946 .sysc_fields = &omap_hwmod_sysc_type2,
2947 };
2948
2949 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
2950 .name = "usb_host_hs",
2951 .sysc = &omap44xx_usb_host_hs_sysc,
2952 };
2953
2954 /* usb_host_hs */
2955 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
2956 .name = "usb_host_hs",
2957 .class = &omap44xx_usb_host_hs_hwmod_class,
2958 .clkdm_name = "l3_init_clkdm",
2959 .main_clk = "usb_host_hs_fck",
2960 .prcm = {
2961 .omap4 = {
2962 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
2963 .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
2964 .modulemode = MODULEMODE_SWCTRL,
2965 },
2966 },
2967
2968 /*
2969 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
2970 * id: i660
2971 *
2972 * Description:
2973 * In the following configuration :
2974 * - USBHOST module is set to smart-idle mode
2975 * - PRCM asserts idle_req to the USBHOST module ( This typically
2976 * happens when the system is going to a low power mode : all ports
2977 * have been suspended, the master part of the USBHOST module has
2978 * entered the standby state, and SW has cut the functional clocks)
2979 * - an USBHOST interrupt occurs before the module is able to answer
2980 * idle_ack, typically a remote wakeup IRQ.
2981 * Then the USB HOST module will enter a deadlock situation where it
2982 * is no more accessible nor functional.
2983 *
2984 * Workaround:
2985 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
2986 */
2987
2988 /*
2989 * Errata: USB host EHCI may stall when entering smart-standby mode
2990 * Id: i571
2991 *
2992 * Description:
2993 * When the USBHOST module is set to smart-standby mode, and when it is
2994 * ready to enter the standby state (i.e. all ports are suspended and
2995 * all attached devices are in suspend mode), then it can wrongly assert
2996 * the Mstandby signal too early while there are still some residual OCP
2997 * transactions ongoing. If this condition occurs, the internal state
2998 * machine may go to an undefined state and the USB link may be stuck
2999 * upon the next resume.
3000 *
3001 * Workaround:
3002 * Don't use smart standby; use only force standby,
3003 * hence HWMOD_SWSUP_MSTANDBY
3004 */
3005
3006 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3007 };
3008
3009 /*
3010 * 'usb_otg_hs' class
3011 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3012 */
3013
3014 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3015 .rev_offs = 0x0400,
3016 .sysc_offs = 0x0404,
3017 .syss_offs = 0x0408,
3018 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3019 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3020 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3021 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3022 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3023 MSTANDBY_SMART),
3024 .sysc_fields = &omap_hwmod_sysc_type1,
3025 };
3026
3027 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3028 .name = "usb_otg_hs",
3029 .sysc = &omap44xx_usb_otg_hs_sysc,
3030 };
3031
3032 /* usb_otg_hs */
3033 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3034 { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3035 };
3036
3037 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3038 .name = "usb_otg_hs",
3039 .class = &omap44xx_usb_otg_hs_hwmod_class,
3040 .clkdm_name = "l3_init_clkdm",
3041 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3042 .main_clk = "usb_otg_hs_ick",
3043 .prcm = {
3044 .omap4 = {
3045 .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3046 .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3047 .modulemode = MODULEMODE_HWCTRL,
3048 },
3049 },
3050 .opt_clks = usb_otg_hs_opt_clks,
3051 .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
3052 };
3053
3054 /*
3055 * 'usb_tll_hs' class
3056 * usb_tll_hs module is the adapter on the usb_host_hs ports
3057 */
3058
3059 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3060 .rev_offs = 0x0000,
3061 .sysc_offs = 0x0010,
3062 .syss_offs = 0x0014,
3063 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3064 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3065 SYSC_HAS_AUTOIDLE),
3066 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3067 .sysc_fields = &omap_hwmod_sysc_type1,
3068 };
3069
3070 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3071 .name = "usb_tll_hs",
3072 .sysc = &omap44xx_usb_tll_hs_sysc,
3073 };
3074
3075 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3076 .name = "usb_tll_hs",
3077 .class = &omap44xx_usb_tll_hs_hwmod_class,
3078 .clkdm_name = "l3_init_clkdm",
3079 .main_clk = "usb_tll_hs_ick",
3080 .prcm = {
3081 .omap4 = {
3082 .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3083 .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3084 .modulemode = MODULEMODE_HWCTRL,
3085 },
3086 },
3087 };
3088
3089 /*
3090 * 'wd_timer' class
3091 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3092 * overflow condition
3093 */
3094
3095 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3096 .rev_offs = 0x0000,
3097 .sysc_offs = 0x0010,
3098 .syss_offs = 0x0014,
3099 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3100 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3101 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3102 SIDLE_SMART_WKUP),
3103 .sysc_fields = &omap_hwmod_sysc_type1,
3104 };
3105
3106 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3107 .name = "wd_timer",
3108 .sysc = &omap44xx_wd_timer_sysc,
3109 .pre_shutdown = &omap2_wd_timer_disable,
3110 .reset = &omap2_wd_timer_reset,
3111 };
3112
3113 /* wd_timer2 */
3114 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3115 .name = "wd_timer2",
3116 .class = &omap44xx_wd_timer_hwmod_class,
3117 .clkdm_name = "l4_wkup_clkdm",
3118 .main_clk = "sys_32k_ck",
3119 .prcm = {
3120 .omap4 = {
3121 .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3122 .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3123 .modulemode = MODULEMODE_SWCTRL,
3124 },
3125 },
3126 };
3127
3128 /* wd_timer3 */
3129 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3130 .name = "wd_timer3",
3131 .class = &omap44xx_wd_timer_hwmod_class,
3132 .clkdm_name = "abe_clkdm",
3133 .main_clk = "sys_32k_ck",
3134 .prcm = {
3135 .omap4 = {
3136 .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3137 .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3138 .modulemode = MODULEMODE_SWCTRL,
3139 },
3140 },
3141 };
3142
3143
3144 /*
3145 * interfaces
3146 */
3147
3148 /* l3_main_1 -> dmm */
3149 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3150 .master = &omap44xx_l3_main_1_hwmod,
3151 .slave = &omap44xx_dmm_hwmod,
3152 .clk = "l3_div_ck",
3153 .user = OCP_USER_SDMA,
3154 };
3155
3156 /* mpu -> dmm */
3157 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3158 .master = &omap44xx_mpu_hwmod,
3159 .slave = &omap44xx_dmm_hwmod,
3160 .clk = "l3_div_ck",
3161 .user = OCP_USER_MPU,
3162 };
3163
3164 /* iva -> l3_instr */
3165 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3166 .master = &omap44xx_iva_hwmod,
3167 .slave = &omap44xx_l3_instr_hwmod,
3168 .clk = "l3_div_ck",
3169 .user = OCP_USER_MPU | OCP_USER_SDMA,
3170 };
3171
3172 /* l3_main_3 -> l3_instr */
3173 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3174 .master = &omap44xx_l3_main_3_hwmod,
3175 .slave = &omap44xx_l3_instr_hwmod,
3176 .clk = "l3_div_ck",
3177 .user = OCP_USER_MPU | OCP_USER_SDMA,
3178 };
3179
3180 /* ocp_wp_noc -> l3_instr */
3181 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3182 .master = &omap44xx_ocp_wp_noc_hwmod,
3183 .slave = &omap44xx_l3_instr_hwmod,
3184 .clk = "l3_div_ck",
3185 .user = OCP_USER_MPU | OCP_USER_SDMA,
3186 };
3187
3188 /* dsp -> l3_main_1 */
3189 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3190 .master = &omap44xx_dsp_hwmod,
3191 .slave = &omap44xx_l3_main_1_hwmod,
3192 .clk = "l3_div_ck",
3193 .user = OCP_USER_MPU | OCP_USER_SDMA,
3194 };
3195
3196 /* dss -> l3_main_1 */
3197 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3198 .master = &omap44xx_dss_hwmod,
3199 .slave = &omap44xx_l3_main_1_hwmod,
3200 .clk = "l3_div_ck",
3201 .user = OCP_USER_MPU | OCP_USER_SDMA,
3202 };
3203
3204 /* l3_main_2 -> l3_main_1 */
3205 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3206 .master = &omap44xx_l3_main_2_hwmod,
3207 .slave = &omap44xx_l3_main_1_hwmod,
3208 .clk = "l3_div_ck",
3209 .user = OCP_USER_MPU | OCP_USER_SDMA,
3210 };
3211
3212 /* l4_cfg -> l3_main_1 */
3213 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3214 .master = &omap44xx_l4_cfg_hwmod,
3215 .slave = &omap44xx_l3_main_1_hwmod,
3216 .clk = "l4_div_ck",
3217 .user = OCP_USER_MPU | OCP_USER_SDMA,
3218 };
3219
3220 /* mmc1 -> l3_main_1 */
3221 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3222 .master = &omap44xx_mmc1_hwmod,
3223 .slave = &omap44xx_l3_main_1_hwmod,
3224 .clk = "l3_div_ck",
3225 .user = OCP_USER_MPU | OCP_USER_SDMA,
3226 };
3227
3228 /* mmc2 -> l3_main_1 */
3229 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3230 .master = &omap44xx_mmc2_hwmod,
3231 .slave = &omap44xx_l3_main_1_hwmod,
3232 .clk = "l3_div_ck",
3233 .user = OCP_USER_MPU | OCP_USER_SDMA,
3234 };
3235
3236 /* mpu -> l3_main_1 */
3237 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3238 .master = &omap44xx_mpu_hwmod,
3239 .slave = &omap44xx_l3_main_1_hwmod,
3240 .clk = "l3_div_ck",
3241 .user = OCP_USER_MPU,
3242 };
3243
3244 /* debugss -> l3_main_2 */
3245 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
3246 .master = &omap44xx_debugss_hwmod,
3247 .slave = &omap44xx_l3_main_2_hwmod,
3248 .clk = "dbgclk_mux_ck",
3249 .user = OCP_USER_MPU | OCP_USER_SDMA,
3250 };
3251
3252 /* dma_system -> l3_main_2 */
3253 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
3254 .master = &omap44xx_dma_system_hwmod,
3255 .slave = &omap44xx_l3_main_2_hwmod,
3256 .clk = "l3_div_ck",
3257 .user = OCP_USER_MPU | OCP_USER_SDMA,
3258 };
3259
3260 /* fdif -> l3_main_2 */
3261 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3262 .master = &omap44xx_fdif_hwmod,
3263 .slave = &omap44xx_l3_main_2_hwmod,
3264 .clk = "l3_div_ck",
3265 .user = OCP_USER_MPU | OCP_USER_SDMA,
3266 };
3267
3268 /* gpu -> l3_main_2 */
3269 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
3270 .master = &omap44xx_gpu_hwmod,
3271 .slave = &omap44xx_l3_main_2_hwmod,
3272 .clk = "l3_div_ck",
3273 .user = OCP_USER_MPU | OCP_USER_SDMA,
3274 };
3275
3276 /* hsi -> l3_main_2 */
3277 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
3278 .master = &omap44xx_hsi_hwmod,
3279 .slave = &omap44xx_l3_main_2_hwmod,
3280 .clk = "l3_div_ck",
3281 .user = OCP_USER_MPU | OCP_USER_SDMA,
3282 };
3283
3284 /* ipu -> l3_main_2 */
3285 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
3286 .master = &omap44xx_ipu_hwmod,
3287 .slave = &omap44xx_l3_main_2_hwmod,
3288 .clk = "l3_div_ck",
3289 .user = OCP_USER_MPU | OCP_USER_SDMA,
3290 };
3291
3292 /* iss -> l3_main_2 */
3293 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
3294 .master = &omap44xx_iss_hwmod,
3295 .slave = &omap44xx_l3_main_2_hwmod,
3296 .clk = "l3_div_ck",
3297 .user = OCP_USER_MPU | OCP_USER_SDMA,
3298 };
3299
3300 /* iva -> l3_main_2 */
3301 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
3302 .master = &omap44xx_iva_hwmod,
3303 .slave = &omap44xx_l3_main_2_hwmod,
3304 .clk = "l3_div_ck",
3305 .user = OCP_USER_MPU | OCP_USER_SDMA,
3306 };
3307
3308 /* l3_main_1 -> l3_main_2 */
3309 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
3310 .master = &omap44xx_l3_main_1_hwmod,
3311 .slave = &omap44xx_l3_main_2_hwmod,
3312 .clk = "l3_div_ck",
3313 .user = OCP_USER_MPU,
3314 };
3315
3316 /* l4_cfg -> l3_main_2 */
3317 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
3318 .master = &omap44xx_l4_cfg_hwmod,
3319 .slave = &omap44xx_l3_main_2_hwmod,
3320 .clk = "l4_div_ck",
3321 .user = OCP_USER_MPU | OCP_USER_SDMA,
3322 };
3323
3324 /* usb_host_fs -> l3_main_2 */
3325 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
3326 .master = &omap44xx_usb_host_fs_hwmod,
3327 .slave = &omap44xx_l3_main_2_hwmod,
3328 .clk = "l3_div_ck",
3329 .user = OCP_USER_MPU | OCP_USER_SDMA,
3330 };
3331
3332 /* usb_host_hs -> l3_main_2 */
3333 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
3334 .master = &omap44xx_usb_host_hs_hwmod,
3335 .slave = &omap44xx_l3_main_2_hwmod,
3336 .clk = "l3_div_ck",
3337 .user = OCP_USER_MPU | OCP_USER_SDMA,
3338 };
3339
3340 /* usb_otg_hs -> l3_main_2 */
3341 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
3342 .master = &omap44xx_usb_otg_hs_hwmod,
3343 .slave = &omap44xx_l3_main_2_hwmod,
3344 .clk = "l3_div_ck",
3345 .user = OCP_USER_MPU | OCP_USER_SDMA,
3346 };
3347
3348 /* l3_main_1 -> l3_main_3 */
3349 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
3350 .master = &omap44xx_l3_main_1_hwmod,
3351 .slave = &omap44xx_l3_main_3_hwmod,
3352 .clk = "l3_div_ck",
3353 .user = OCP_USER_MPU,
3354 };
3355
3356 /* l3_main_2 -> l3_main_3 */
3357 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
3358 .master = &omap44xx_l3_main_2_hwmod,
3359 .slave = &omap44xx_l3_main_3_hwmod,
3360 .clk = "l3_div_ck",
3361 .user = OCP_USER_MPU | OCP_USER_SDMA,
3362 };
3363
3364 /* l4_cfg -> l3_main_3 */
3365 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
3366 .master = &omap44xx_l4_cfg_hwmod,
3367 .slave = &omap44xx_l3_main_3_hwmod,
3368 .clk = "l4_div_ck",
3369 .user = OCP_USER_MPU | OCP_USER_SDMA,
3370 };
3371
3372 /* aess -> l4_abe */
3373 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
3374 .master = &omap44xx_aess_hwmod,
3375 .slave = &omap44xx_l4_abe_hwmod,
3376 .clk = "ocp_abe_iclk",
3377 .user = OCP_USER_MPU | OCP_USER_SDMA,
3378 };
3379
3380 /* dsp -> l4_abe */
3381 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
3382 .master = &omap44xx_dsp_hwmod,
3383 .slave = &omap44xx_l4_abe_hwmod,
3384 .clk = "ocp_abe_iclk",
3385 .user = OCP_USER_MPU | OCP_USER_SDMA,
3386 };
3387
3388 /* l3_main_1 -> l4_abe */
3389 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
3390 .master = &omap44xx_l3_main_1_hwmod,
3391 .slave = &omap44xx_l4_abe_hwmod,
3392 .clk = "l3_div_ck",
3393 .user = OCP_USER_MPU | OCP_USER_SDMA,
3394 };
3395
3396 /* mpu -> l4_abe */
3397 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
3398 .master = &omap44xx_mpu_hwmod,
3399 .slave = &omap44xx_l4_abe_hwmod,
3400 .clk = "ocp_abe_iclk",
3401 .user = OCP_USER_MPU | OCP_USER_SDMA,
3402 };
3403
3404 /* l3_main_1 -> l4_cfg */
3405 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
3406 .master = &omap44xx_l3_main_1_hwmod,
3407 .slave = &omap44xx_l4_cfg_hwmod,
3408 .clk = "l3_div_ck",
3409 .user = OCP_USER_MPU | OCP_USER_SDMA,
3410 };
3411
3412 /* l3_main_2 -> l4_per */
3413 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
3414 .master = &omap44xx_l3_main_2_hwmod,
3415 .slave = &omap44xx_l4_per_hwmod,
3416 .clk = "l3_div_ck",
3417 .user = OCP_USER_MPU | OCP_USER_SDMA,
3418 };
3419
3420 /* l4_cfg -> l4_wkup */
3421 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
3422 .master = &omap44xx_l4_cfg_hwmod,
3423 .slave = &omap44xx_l4_wkup_hwmod,
3424 .clk = "l4_div_ck",
3425 .user = OCP_USER_MPU | OCP_USER_SDMA,
3426 };
3427
3428 /* mpu -> mpu_private */
3429 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
3430 .master = &omap44xx_mpu_hwmod,
3431 .slave = &omap44xx_mpu_private_hwmod,
3432 .clk = "l3_div_ck",
3433 .user = OCP_USER_MPU | OCP_USER_SDMA,
3434 };
3435
3436 /* l4_cfg -> ocp_wp_noc */
3437 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
3438 .master = &omap44xx_l4_cfg_hwmod,
3439 .slave = &omap44xx_ocp_wp_noc_hwmod,
3440 .clk = "l4_div_ck",
3441 .user = OCP_USER_MPU | OCP_USER_SDMA,
3442 };
3443
3444 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
3445 {
3446 .name = "dmem",
3447 .pa_start = 0x40180000,
3448 .pa_end = 0x4018ffff
3449 },
3450 {
3451 .name = "cmem",
3452 .pa_start = 0x401a0000,
3453 .pa_end = 0x401a1fff
3454 },
3455 {
3456 .name = "smem",
3457 .pa_start = 0x401c0000,
3458 .pa_end = 0x401c5fff
3459 },
3460 {
3461 .name = "pmem",
3462 .pa_start = 0x401e0000,
3463 .pa_end = 0x401e1fff
3464 },
3465 {
3466 .name = "mpu",
3467 .pa_start = 0x401f1000,
3468 .pa_end = 0x401f13ff,
3469 .flags = ADDR_TYPE_RT
3470 },
3471 { }
3472 };
3473
3474 /* l4_abe -> aess */
3475 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
3476 .master = &omap44xx_l4_abe_hwmod,
3477 .slave = &omap44xx_aess_hwmod,
3478 .clk = "ocp_abe_iclk",
3479 .addr = omap44xx_aess_addrs,
3480 .user = OCP_USER_MPU,
3481 };
3482
3483 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
3484 {
3485 .name = "dmem_dma",
3486 .pa_start = 0x49080000,
3487 .pa_end = 0x4908ffff
3488 },
3489 {
3490 .name = "cmem_dma",
3491 .pa_start = 0x490a0000,
3492 .pa_end = 0x490a1fff
3493 },
3494 {
3495 .name = "smem_dma",
3496 .pa_start = 0x490c0000,
3497 .pa_end = 0x490c5fff
3498 },
3499 {
3500 .name = "pmem_dma",
3501 .pa_start = 0x490e0000,
3502 .pa_end = 0x490e1fff
3503 },
3504 {
3505 .name = "dma",
3506 .pa_start = 0x490f1000,
3507 .pa_end = 0x490f13ff,
3508 .flags = ADDR_TYPE_RT
3509 },
3510 { }
3511 };
3512
3513 /* l4_abe -> aess (dma) */
3514 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
3515 .master = &omap44xx_l4_abe_hwmod,
3516 .slave = &omap44xx_aess_hwmod,
3517 .clk = "ocp_abe_iclk",
3518 .addr = omap44xx_aess_dma_addrs,
3519 .user = OCP_USER_SDMA,
3520 };
3521
3522 /* l3_main_2 -> c2c */
3523 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
3524 .master = &omap44xx_l3_main_2_hwmod,
3525 .slave = &omap44xx_c2c_hwmod,
3526 .clk = "l3_div_ck",
3527 .user = OCP_USER_MPU | OCP_USER_SDMA,
3528 };
3529
3530 /* l4_wkup -> counter_32k */
3531 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
3532 .master = &omap44xx_l4_wkup_hwmod,
3533 .slave = &omap44xx_counter_32k_hwmod,
3534 .clk = "l4_wkup_clk_mux_ck",
3535 .user = OCP_USER_MPU | OCP_USER_SDMA,
3536 };
3537
3538 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
3539 {
3540 .pa_start = 0x4a002000,
3541 .pa_end = 0x4a0027ff,
3542 .flags = ADDR_TYPE_RT
3543 },
3544 { }
3545 };
3546
3547 /* l4_cfg -> ctrl_module_core */
3548 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
3549 .master = &omap44xx_l4_cfg_hwmod,
3550 .slave = &omap44xx_ctrl_module_core_hwmod,
3551 .clk = "l4_div_ck",
3552 .addr = omap44xx_ctrl_module_core_addrs,
3553 .user = OCP_USER_MPU | OCP_USER_SDMA,
3554 };
3555
3556 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
3557 {
3558 .pa_start = 0x4a100000,
3559 .pa_end = 0x4a1007ff,
3560 .flags = ADDR_TYPE_RT
3561 },
3562 { }
3563 };
3564
3565 /* l4_cfg -> ctrl_module_pad_core */
3566 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
3567 .master = &omap44xx_l4_cfg_hwmod,
3568 .slave = &omap44xx_ctrl_module_pad_core_hwmod,
3569 .clk = "l4_div_ck",
3570 .addr = omap44xx_ctrl_module_pad_core_addrs,
3571 .user = OCP_USER_MPU | OCP_USER_SDMA,
3572 };
3573
3574 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
3575 {
3576 .pa_start = 0x4a30c000,
3577 .pa_end = 0x4a30c7ff,
3578 .flags = ADDR_TYPE_RT
3579 },
3580 { }
3581 };
3582
3583 /* l4_wkup -> ctrl_module_wkup */
3584 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
3585 .master = &omap44xx_l4_wkup_hwmod,
3586 .slave = &omap44xx_ctrl_module_wkup_hwmod,
3587 .clk = "l4_wkup_clk_mux_ck",
3588 .addr = omap44xx_ctrl_module_wkup_addrs,
3589 .user = OCP_USER_MPU | OCP_USER_SDMA,
3590 };
3591
3592 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
3593 {
3594 .pa_start = 0x4a31e000,
3595 .pa_end = 0x4a31e7ff,
3596 .flags = ADDR_TYPE_RT
3597 },
3598 { }
3599 };
3600
3601 /* l4_wkup -> ctrl_module_pad_wkup */
3602 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
3603 .master = &omap44xx_l4_wkup_hwmod,
3604 .slave = &omap44xx_ctrl_module_pad_wkup_hwmod,
3605 .clk = "l4_wkup_clk_mux_ck",
3606 .addr = omap44xx_ctrl_module_pad_wkup_addrs,
3607 .user = OCP_USER_MPU | OCP_USER_SDMA,
3608 };
3609
3610 /* l3_instr -> debugss */
3611 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
3612 .master = &omap44xx_l3_instr_hwmod,
3613 .slave = &omap44xx_debugss_hwmod,
3614 .clk = "l3_div_ck",
3615 .user = OCP_USER_MPU | OCP_USER_SDMA,
3616 };
3617
3618 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
3619 {
3620 .pa_start = 0x4a056000,
3621 .pa_end = 0x4a056fff,
3622 .flags = ADDR_TYPE_RT
3623 },
3624 { }
3625 };
3626
3627 /* l4_cfg -> dma_system */
3628 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
3629 .master = &omap44xx_l4_cfg_hwmod,
3630 .slave = &omap44xx_dma_system_hwmod,
3631 .clk = "l4_div_ck",
3632 .addr = omap44xx_dma_system_addrs,
3633 .user = OCP_USER_MPU | OCP_USER_SDMA,
3634 };
3635
3636 /* l4_abe -> dmic */
3637 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
3638 .master = &omap44xx_l4_abe_hwmod,
3639 .slave = &omap44xx_dmic_hwmod,
3640 .clk = "ocp_abe_iclk",
3641 .user = OCP_USER_MPU | OCP_USER_SDMA,
3642 };
3643
3644 /* dsp -> iva */
3645 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
3646 .master = &omap44xx_dsp_hwmod,
3647 .slave = &omap44xx_iva_hwmod,
3648 .clk = "dpll_iva_m5x2_ck",
3649 .user = OCP_USER_DSP,
3650 };
3651
3652 /* dsp -> sl2if */
3653 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
3654 .master = &omap44xx_dsp_hwmod,
3655 .slave = &omap44xx_sl2if_hwmod,
3656 .clk = "dpll_iva_m5x2_ck",
3657 .user = OCP_USER_DSP,
3658 };
3659
3660 /* l4_cfg -> dsp */
3661 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
3662 .master = &omap44xx_l4_cfg_hwmod,
3663 .slave = &omap44xx_dsp_hwmod,
3664 .clk = "l4_div_ck",
3665 .user = OCP_USER_MPU | OCP_USER_SDMA,
3666 };
3667
3668 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
3669 {
3670 .pa_start = 0x58000000,
3671 .pa_end = 0x5800007f,
3672 .flags = ADDR_TYPE_RT
3673 },
3674 { }
3675 };
3676
3677 /* l3_main_2 -> dss */
3678 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
3679 .master = &omap44xx_l3_main_2_hwmod,
3680 .slave = &omap44xx_dss_hwmod,
3681 .clk = "l3_div_ck",
3682 .addr = omap44xx_dss_dma_addrs,
3683 .user = OCP_USER_SDMA,
3684 };
3685
3686 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
3687 {
3688 .pa_start = 0x48040000,
3689 .pa_end = 0x4804007f,
3690 .flags = ADDR_TYPE_RT
3691 },
3692 { }
3693 };
3694
3695 /* l4_per -> dss */
3696 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
3697 .master = &omap44xx_l4_per_hwmod,
3698 .slave = &omap44xx_dss_hwmod,
3699 .clk = "l4_div_ck",
3700 .addr = omap44xx_dss_addrs,
3701 .user = OCP_USER_MPU,
3702 };
3703
3704 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
3705 {
3706 .pa_start = 0x58001000,
3707 .pa_end = 0x58001fff,
3708 .flags = ADDR_TYPE_RT
3709 },
3710 { }
3711 };
3712
3713 /* l3_main_2 -> dss_dispc */
3714 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
3715 .master = &omap44xx_l3_main_2_hwmod,
3716 .slave = &omap44xx_dss_dispc_hwmod,
3717 .clk = "l3_div_ck",
3718 .addr = omap44xx_dss_dispc_dma_addrs,
3719 .user = OCP_USER_SDMA,
3720 };
3721
3722 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
3723 {
3724 .pa_start = 0x48041000,
3725 .pa_end = 0x48041fff,
3726 .flags = ADDR_TYPE_RT
3727 },
3728 { }
3729 };
3730
3731 /* l4_per -> dss_dispc */
3732 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
3733 .master = &omap44xx_l4_per_hwmod,
3734 .slave = &omap44xx_dss_dispc_hwmod,
3735 .clk = "l4_div_ck",
3736 .addr = omap44xx_dss_dispc_addrs,
3737 .user = OCP_USER_MPU,
3738 };
3739
3740 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
3741 {
3742 .pa_start = 0x58004000,
3743 .pa_end = 0x580041ff,
3744 .flags = ADDR_TYPE_RT
3745 },
3746 { }
3747 };
3748
3749 /* l3_main_2 -> dss_dsi1 */
3750 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
3751 .master = &omap44xx_l3_main_2_hwmod,
3752 .slave = &omap44xx_dss_dsi1_hwmod,
3753 .clk = "l3_div_ck",
3754 .addr = omap44xx_dss_dsi1_dma_addrs,
3755 .user = OCP_USER_SDMA,
3756 };
3757
3758 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
3759 {
3760 .pa_start = 0x48044000,
3761 .pa_end = 0x480441ff,
3762 .flags = ADDR_TYPE_RT
3763 },
3764 { }
3765 };
3766
3767 /* l4_per -> dss_dsi1 */
3768 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
3769 .master = &omap44xx_l4_per_hwmod,
3770 .slave = &omap44xx_dss_dsi1_hwmod,
3771 .clk = "l4_div_ck",
3772 .addr = omap44xx_dss_dsi1_addrs,
3773 .user = OCP_USER_MPU,
3774 };
3775
3776 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
3777 {
3778 .pa_start = 0x58005000,
3779 .pa_end = 0x580051ff,
3780 .flags = ADDR_TYPE_RT
3781 },
3782 { }
3783 };
3784
3785 /* l3_main_2 -> dss_dsi2 */
3786 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
3787 .master = &omap44xx_l3_main_2_hwmod,
3788 .slave = &omap44xx_dss_dsi2_hwmod,
3789 .clk = "l3_div_ck",
3790 .addr = omap44xx_dss_dsi2_dma_addrs,
3791 .user = OCP_USER_SDMA,
3792 };
3793
3794 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
3795 {
3796 .pa_start = 0x48045000,
3797 .pa_end = 0x480451ff,
3798 .flags = ADDR_TYPE_RT
3799 },
3800 { }
3801 };
3802
3803 /* l4_per -> dss_dsi2 */
3804 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
3805 .master = &omap44xx_l4_per_hwmod,
3806 .slave = &omap44xx_dss_dsi2_hwmod,
3807 .clk = "l4_div_ck",
3808 .addr = omap44xx_dss_dsi2_addrs,
3809 .user = OCP_USER_MPU,
3810 };
3811
3812 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
3813 {
3814 .pa_start = 0x58006000,
3815 .pa_end = 0x58006fff,
3816 .flags = ADDR_TYPE_RT
3817 },
3818 { }
3819 };
3820
3821 /* l3_main_2 -> dss_hdmi */
3822 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
3823 .master = &omap44xx_l3_main_2_hwmod,
3824 .slave = &omap44xx_dss_hdmi_hwmod,
3825 .clk = "l3_div_ck",
3826 .addr = omap44xx_dss_hdmi_dma_addrs,
3827 .user = OCP_USER_SDMA,
3828 };
3829
3830 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
3831 {
3832 .pa_start = 0x48046000,
3833 .pa_end = 0x48046fff,
3834 .flags = ADDR_TYPE_RT
3835 },
3836 { }
3837 };
3838
3839 /* l4_per -> dss_hdmi */
3840 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
3841 .master = &omap44xx_l4_per_hwmod,
3842 .slave = &omap44xx_dss_hdmi_hwmod,
3843 .clk = "l4_div_ck",
3844 .addr = omap44xx_dss_hdmi_addrs,
3845 .user = OCP_USER_MPU,
3846 };
3847
3848 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
3849 {
3850 .pa_start = 0x58002000,
3851 .pa_end = 0x580020ff,
3852 .flags = ADDR_TYPE_RT
3853 },
3854 { }
3855 };
3856
3857 /* l3_main_2 -> dss_rfbi */
3858 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
3859 .master = &omap44xx_l3_main_2_hwmod,
3860 .slave = &omap44xx_dss_rfbi_hwmod,
3861 .clk = "l3_div_ck",
3862 .addr = omap44xx_dss_rfbi_dma_addrs,
3863 .user = OCP_USER_SDMA,
3864 };
3865
3866 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
3867 {
3868 .pa_start = 0x48042000,
3869 .pa_end = 0x480420ff,
3870 .flags = ADDR_TYPE_RT
3871 },
3872 { }
3873 };
3874
3875 /* l4_per -> dss_rfbi */
3876 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
3877 .master = &omap44xx_l4_per_hwmod,
3878 .slave = &omap44xx_dss_rfbi_hwmod,
3879 .clk = "l4_div_ck",
3880 .addr = omap44xx_dss_rfbi_addrs,
3881 .user = OCP_USER_MPU,
3882 };
3883
3884 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
3885 {
3886 .pa_start = 0x58003000,
3887 .pa_end = 0x580030ff,
3888 .flags = ADDR_TYPE_RT
3889 },
3890 { }
3891 };
3892
3893 /* l3_main_2 -> dss_venc */
3894 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
3895 .master = &omap44xx_l3_main_2_hwmod,
3896 .slave = &omap44xx_dss_venc_hwmod,
3897 .clk = "l3_div_ck",
3898 .addr = omap44xx_dss_venc_dma_addrs,
3899 .user = OCP_USER_SDMA,
3900 };
3901
3902 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
3903 {
3904 .pa_start = 0x48043000,
3905 .pa_end = 0x480430ff,
3906 .flags = ADDR_TYPE_RT
3907 },
3908 { }
3909 };
3910
3911 /* l4_per -> dss_venc */
3912 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
3913 .master = &omap44xx_l4_per_hwmod,
3914 .slave = &omap44xx_dss_venc_hwmod,
3915 .clk = "l4_div_ck",
3916 .addr = omap44xx_dss_venc_addrs,
3917 .user = OCP_USER_MPU,
3918 };
3919
3920 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
3921 {
3922 .pa_start = 0x48078000,
3923 .pa_end = 0x48078fff,
3924 .flags = ADDR_TYPE_RT
3925 },
3926 { }
3927 };
3928
3929 /* l4_per -> elm */
3930 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
3931 .master = &omap44xx_l4_per_hwmod,
3932 .slave = &omap44xx_elm_hwmod,
3933 .clk = "l4_div_ck",
3934 .addr = omap44xx_elm_addrs,
3935 .user = OCP_USER_MPU | OCP_USER_SDMA,
3936 };
3937
3938 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
3939 {
3940 .pa_start = 0x4a10a000,
3941 .pa_end = 0x4a10a1ff,
3942 .flags = ADDR_TYPE_RT
3943 },
3944 { }
3945 };
3946
3947 /* l4_cfg -> fdif */
3948 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
3949 .master = &omap44xx_l4_cfg_hwmod,
3950 .slave = &omap44xx_fdif_hwmod,
3951 .clk = "l4_div_ck",
3952 .addr = omap44xx_fdif_addrs,
3953 .user = OCP_USER_MPU | OCP_USER_SDMA,
3954 };
3955
3956 /* l4_wkup -> gpio1 */
3957 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
3958 .master = &omap44xx_l4_wkup_hwmod,
3959 .slave = &omap44xx_gpio1_hwmod,
3960 .clk = "l4_wkup_clk_mux_ck",
3961 .user = OCP_USER_MPU | OCP_USER_SDMA,
3962 };
3963
3964 /* l4_per -> gpio2 */
3965 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
3966 .master = &omap44xx_l4_per_hwmod,
3967 .slave = &omap44xx_gpio2_hwmod,
3968 .clk = "l4_div_ck",
3969 .user = OCP_USER_MPU | OCP_USER_SDMA,
3970 };
3971
3972 /* l4_per -> gpio3 */
3973 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
3974 .master = &omap44xx_l4_per_hwmod,
3975 .slave = &omap44xx_gpio3_hwmod,
3976 .clk = "l4_div_ck",
3977 .user = OCP_USER_MPU | OCP_USER_SDMA,
3978 };
3979
3980 /* l4_per -> gpio4 */
3981 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
3982 .master = &omap44xx_l4_per_hwmod,
3983 .slave = &omap44xx_gpio4_hwmod,
3984 .clk = "l4_div_ck",
3985 .user = OCP_USER_MPU | OCP_USER_SDMA,
3986 };
3987
3988 /* l4_per -> gpio5 */
3989 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
3990 .master = &omap44xx_l4_per_hwmod,
3991 .slave = &omap44xx_gpio5_hwmod,
3992 .clk = "l4_div_ck",
3993 .user = OCP_USER_MPU | OCP_USER_SDMA,
3994 };
3995
3996 /* l4_per -> gpio6 */
3997 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
3998 .master = &omap44xx_l4_per_hwmod,
3999 .slave = &omap44xx_gpio6_hwmod,
4000 .clk = "l4_div_ck",
4001 .user = OCP_USER_MPU | OCP_USER_SDMA,
4002 };
4003
4004 /* l3_main_2 -> gpmc */
4005 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4006 .master = &omap44xx_l3_main_2_hwmod,
4007 .slave = &omap44xx_gpmc_hwmod,
4008 .clk = "l3_div_ck",
4009 .user = OCP_USER_MPU | OCP_USER_SDMA,
4010 };
4011
4012 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4013 {
4014 .pa_start = 0x56000000,
4015 .pa_end = 0x5600ffff,
4016 .flags = ADDR_TYPE_RT
4017 },
4018 { }
4019 };
4020
4021 /* l3_main_2 -> gpu */
4022 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4023 .master = &omap44xx_l3_main_2_hwmod,
4024 .slave = &omap44xx_gpu_hwmod,
4025 .clk = "l3_div_ck",
4026 .addr = omap44xx_gpu_addrs,
4027 .user = OCP_USER_MPU | OCP_USER_SDMA,
4028 };
4029
4030 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4031 {
4032 .pa_start = 0x480b2000,
4033 .pa_end = 0x480b201f,
4034 .flags = ADDR_TYPE_RT
4035 },
4036 { }
4037 };
4038
4039 /* l4_per -> hdq1w */
4040 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4041 .master = &omap44xx_l4_per_hwmod,
4042 .slave = &omap44xx_hdq1w_hwmod,
4043 .clk = "l4_div_ck",
4044 .addr = omap44xx_hdq1w_addrs,
4045 .user = OCP_USER_MPU | OCP_USER_SDMA,
4046 };
4047
4048 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4049 {
4050 .pa_start = 0x4a058000,
4051 .pa_end = 0x4a05bfff,
4052 .flags = ADDR_TYPE_RT
4053 },
4054 { }
4055 };
4056
4057 /* l4_cfg -> hsi */
4058 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4059 .master = &omap44xx_l4_cfg_hwmod,
4060 .slave = &omap44xx_hsi_hwmod,
4061 .clk = "l4_div_ck",
4062 .addr = omap44xx_hsi_addrs,
4063 .user = OCP_USER_MPU | OCP_USER_SDMA,
4064 };
4065
4066 /* l4_per -> i2c1 */
4067 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4068 .master = &omap44xx_l4_per_hwmod,
4069 .slave = &omap44xx_i2c1_hwmod,
4070 .clk = "l4_div_ck",
4071 .user = OCP_USER_MPU | OCP_USER_SDMA,
4072 };
4073
4074 /* l4_per -> i2c2 */
4075 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
4076 .master = &omap44xx_l4_per_hwmod,
4077 .slave = &omap44xx_i2c2_hwmod,
4078 .clk = "l4_div_ck",
4079 .user = OCP_USER_MPU | OCP_USER_SDMA,
4080 };
4081
4082 /* l4_per -> i2c3 */
4083 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
4084 .master = &omap44xx_l4_per_hwmod,
4085 .slave = &omap44xx_i2c3_hwmod,
4086 .clk = "l4_div_ck",
4087 .user = OCP_USER_MPU | OCP_USER_SDMA,
4088 };
4089
4090 /* l4_per -> i2c4 */
4091 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
4092 .master = &omap44xx_l4_per_hwmod,
4093 .slave = &omap44xx_i2c4_hwmod,
4094 .clk = "l4_div_ck",
4095 .user = OCP_USER_MPU | OCP_USER_SDMA,
4096 };
4097
4098 /* l3_main_2 -> ipu */
4099 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
4100 .master = &omap44xx_l3_main_2_hwmod,
4101 .slave = &omap44xx_ipu_hwmod,
4102 .clk = "l3_div_ck",
4103 .user = OCP_USER_MPU | OCP_USER_SDMA,
4104 };
4105
4106 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
4107 {
4108 .pa_start = 0x52000000,
4109 .pa_end = 0x520000ff,
4110 .flags = ADDR_TYPE_RT
4111 },
4112 { }
4113 };
4114
4115 /* l3_main_2 -> iss */
4116 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
4117 .master = &omap44xx_l3_main_2_hwmod,
4118 .slave = &omap44xx_iss_hwmod,
4119 .clk = "l3_div_ck",
4120 .addr = omap44xx_iss_addrs,
4121 .user = OCP_USER_MPU | OCP_USER_SDMA,
4122 };
4123
4124 /* iva -> sl2if */
4125 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
4126 .master = &omap44xx_iva_hwmod,
4127 .slave = &omap44xx_sl2if_hwmod,
4128 .clk = "dpll_iva_m5x2_ck",
4129 .user = OCP_USER_IVA,
4130 };
4131
4132 /* l3_main_2 -> iva */
4133 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
4134 .master = &omap44xx_l3_main_2_hwmod,
4135 .slave = &omap44xx_iva_hwmod,
4136 .clk = "l3_div_ck",
4137 .user = OCP_USER_MPU,
4138 };
4139
4140 /* l4_wkup -> kbd */
4141 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
4142 .master = &omap44xx_l4_wkup_hwmod,
4143 .slave = &omap44xx_kbd_hwmod,
4144 .clk = "l4_wkup_clk_mux_ck",
4145 .user = OCP_USER_MPU | OCP_USER_SDMA,
4146 };
4147
4148 /* l4_cfg -> mailbox */
4149 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
4150 .master = &omap44xx_l4_cfg_hwmod,
4151 .slave = &omap44xx_mailbox_hwmod,
4152 .clk = "l4_div_ck",
4153 .user = OCP_USER_MPU | OCP_USER_SDMA,
4154 };
4155
4156 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
4157 {
4158 .pa_start = 0x40128000,
4159 .pa_end = 0x401283ff,
4160 .flags = ADDR_TYPE_RT
4161 },
4162 { }
4163 };
4164
4165 /* l4_abe -> mcasp */
4166 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
4167 .master = &omap44xx_l4_abe_hwmod,
4168 .slave = &omap44xx_mcasp_hwmod,
4169 .clk = "ocp_abe_iclk",
4170 .addr = omap44xx_mcasp_addrs,
4171 .user = OCP_USER_MPU,
4172 };
4173
4174 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
4175 {
4176 .pa_start = 0x49028000,
4177 .pa_end = 0x490283ff,
4178 .flags = ADDR_TYPE_RT
4179 },
4180 { }
4181 };
4182
4183 /* l4_abe -> mcasp (dma) */
4184 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
4185 .master = &omap44xx_l4_abe_hwmod,
4186 .slave = &omap44xx_mcasp_hwmod,
4187 .clk = "ocp_abe_iclk",
4188 .addr = omap44xx_mcasp_dma_addrs,
4189 .user = OCP_USER_SDMA,
4190 };
4191
4192 /* l4_abe -> mcbsp1 */
4193 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
4194 .master = &omap44xx_l4_abe_hwmod,
4195 .slave = &omap44xx_mcbsp1_hwmod,
4196 .clk = "ocp_abe_iclk",
4197 .user = OCP_USER_MPU | OCP_USER_SDMA,
4198 };
4199
4200 /* l4_abe -> mcbsp2 */
4201 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
4202 .master = &omap44xx_l4_abe_hwmod,
4203 .slave = &omap44xx_mcbsp2_hwmod,
4204 .clk = "ocp_abe_iclk",
4205 .user = OCP_USER_MPU | OCP_USER_SDMA,
4206 };
4207
4208 /* l4_abe -> mcbsp3 */
4209 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
4210 .master = &omap44xx_l4_abe_hwmod,
4211 .slave = &omap44xx_mcbsp3_hwmod,
4212 .clk = "ocp_abe_iclk",
4213 .user = OCP_USER_MPU | OCP_USER_SDMA,
4214 };
4215
4216 /* l4_per -> mcbsp4 */
4217 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
4218 .master = &omap44xx_l4_per_hwmod,
4219 .slave = &omap44xx_mcbsp4_hwmod,
4220 .clk = "l4_div_ck",
4221 .user = OCP_USER_MPU | OCP_USER_SDMA,
4222 };
4223
4224 /* l4_abe -> mcpdm */
4225 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
4226 .master = &omap44xx_l4_abe_hwmod,
4227 .slave = &omap44xx_mcpdm_hwmod,
4228 .clk = "ocp_abe_iclk",
4229 .user = OCP_USER_MPU | OCP_USER_SDMA,
4230 };
4231
4232 /* l4_per -> mcspi1 */
4233 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
4234 .master = &omap44xx_l4_per_hwmod,
4235 .slave = &omap44xx_mcspi1_hwmod,
4236 .clk = "l4_div_ck",
4237 .user = OCP_USER_MPU | OCP_USER_SDMA,
4238 };
4239
4240 /* l4_per -> mcspi2 */
4241 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
4242 .master = &omap44xx_l4_per_hwmod,
4243 .slave = &omap44xx_mcspi2_hwmod,
4244 .clk = "l4_div_ck",
4245 .user = OCP_USER_MPU | OCP_USER_SDMA,
4246 };
4247
4248 /* l4_per -> mcspi3 */
4249 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
4250 .master = &omap44xx_l4_per_hwmod,
4251 .slave = &omap44xx_mcspi3_hwmod,
4252 .clk = "l4_div_ck",
4253 .user = OCP_USER_MPU | OCP_USER_SDMA,
4254 };
4255
4256 /* l4_per -> mcspi4 */
4257 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
4258 .master = &omap44xx_l4_per_hwmod,
4259 .slave = &omap44xx_mcspi4_hwmod,
4260 .clk = "l4_div_ck",
4261 .user = OCP_USER_MPU | OCP_USER_SDMA,
4262 };
4263
4264 /* l4_per -> mmc1 */
4265 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
4266 .master = &omap44xx_l4_per_hwmod,
4267 .slave = &omap44xx_mmc1_hwmod,
4268 .clk = "l4_div_ck",
4269 .user = OCP_USER_MPU | OCP_USER_SDMA,
4270 };
4271
4272 /* l4_per -> mmc2 */
4273 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
4274 .master = &omap44xx_l4_per_hwmod,
4275 .slave = &omap44xx_mmc2_hwmod,
4276 .clk = "l4_div_ck",
4277 .user = OCP_USER_MPU | OCP_USER_SDMA,
4278 };
4279
4280 /* l4_per -> mmc3 */
4281 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
4282 .master = &omap44xx_l4_per_hwmod,
4283 .slave = &omap44xx_mmc3_hwmod,
4284 .clk = "l4_div_ck",
4285 .user = OCP_USER_MPU | OCP_USER_SDMA,
4286 };
4287
4288 /* l4_per -> mmc4 */
4289 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
4290 .master = &omap44xx_l4_per_hwmod,
4291 .slave = &omap44xx_mmc4_hwmod,
4292 .clk = "l4_div_ck",
4293 .user = OCP_USER_MPU | OCP_USER_SDMA,
4294 };
4295
4296 /* l4_per -> mmc5 */
4297 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
4298 .master = &omap44xx_l4_per_hwmod,
4299 .slave = &omap44xx_mmc5_hwmod,
4300 .clk = "l4_div_ck",
4301 .user = OCP_USER_MPU | OCP_USER_SDMA,
4302 };
4303
4304 /* l3_main_2 -> ocmc_ram */
4305 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
4306 .master = &omap44xx_l3_main_2_hwmod,
4307 .slave = &omap44xx_ocmc_ram_hwmod,
4308 .clk = "l3_div_ck",
4309 .user = OCP_USER_MPU | OCP_USER_SDMA,
4310 };
4311
4312 /* l4_cfg -> ocp2scp_usb_phy */
4313 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
4314 .master = &omap44xx_l4_cfg_hwmod,
4315 .slave = &omap44xx_ocp2scp_usb_phy_hwmod,
4316 .clk = "l4_div_ck",
4317 .user = OCP_USER_MPU | OCP_USER_SDMA,
4318 };
4319
4320 /* mpu_private -> prcm_mpu */
4321 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
4322 .master = &omap44xx_mpu_private_hwmod,
4323 .slave = &omap44xx_prcm_mpu_hwmod,
4324 .clk = "l3_div_ck",
4325 .user = OCP_USER_MPU | OCP_USER_SDMA,
4326 };
4327
4328 /* l4_wkup -> cm_core_aon */
4329 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
4330 .master = &omap44xx_l4_wkup_hwmod,
4331 .slave = &omap44xx_cm_core_aon_hwmod,
4332 .clk = "l4_wkup_clk_mux_ck",
4333 .user = OCP_USER_MPU | OCP_USER_SDMA,
4334 };
4335
4336 /* l4_cfg -> cm_core */
4337 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
4338 .master = &omap44xx_l4_cfg_hwmod,
4339 .slave = &omap44xx_cm_core_hwmod,
4340 .clk = "l4_div_ck",
4341 .user = OCP_USER_MPU | OCP_USER_SDMA,
4342 };
4343
4344 /* l4_wkup -> prm */
4345 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
4346 .master = &omap44xx_l4_wkup_hwmod,
4347 .slave = &omap44xx_prm_hwmod,
4348 .clk = "l4_wkup_clk_mux_ck",
4349 .user = OCP_USER_MPU | OCP_USER_SDMA,
4350 };
4351
4352 /* l4_wkup -> scrm */
4353 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
4354 .master = &omap44xx_l4_wkup_hwmod,
4355 .slave = &omap44xx_scrm_hwmod,
4356 .clk = "l4_wkup_clk_mux_ck",
4357 .user = OCP_USER_MPU | OCP_USER_SDMA,
4358 };
4359
4360 /* l3_main_2 -> sl2if */
4361 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
4362 .master = &omap44xx_l3_main_2_hwmod,
4363 .slave = &omap44xx_sl2if_hwmod,
4364 .clk = "l3_div_ck",
4365 .user = OCP_USER_MPU | OCP_USER_SDMA,
4366 };
4367
4368 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
4369 {
4370 .pa_start = 0x4012c000,
4371 .pa_end = 0x4012c3ff,
4372 .flags = ADDR_TYPE_RT
4373 },
4374 { }
4375 };
4376
4377 /* l4_abe -> slimbus1 */
4378 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
4379 .master = &omap44xx_l4_abe_hwmod,
4380 .slave = &omap44xx_slimbus1_hwmod,
4381 .clk = "ocp_abe_iclk",
4382 .addr = omap44xx_slimbus1_addrs,
4383 .user = OCP_USER_MPU,
4384 };
4385
4386 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
4387 {
4388 .pa_start = 0x4902c000,
4389 .pa_end = 0x4902c3ff,
4390 .flags = ADDR_TYPE_RT
4391 },
4392 { }
4393 };
4394
4395 /* l4_abe -> slimbus1 (dma) */
4396 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
4397 .master = &omap44xx_l4_abe_hwmod,
4398 .slave = &omap44xx_slimbus1_hwmod,
4399 .clk = "ocp_abe_iclk",
4400 .addr = omap44xx_slimbus1_dma_addrs,
4401 .user = OCP_USER_SDMA,
4402 };
4403
4404 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
4405 {
4406 .pa_start = 0x48076000,
4407 .pa_end = 0x480763ff,
4408 .flags = ADDR_TYPE_RT
4409 },
4410 { }
4411 };
4412
4413 /* l4_per -> slimbus2 */
4414 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
4415 .master = &omap44xx_l4_per_hwmod,
4416 .slave = &omap44xx_slimbus2_hwmod,
4417 .clk = "l4_div_ck",
4418 .addr = omap44xx_slimbus2_addrs,
4419 .user = OCP_USER_MPU | OCP_USER_SDMA,
4420 };
4421
4422 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
4423 {
4424 .pa_start = 0x4a0dd000,
4425 .pa_end = 0x4a0dd03f,
4426 .flags = ADDR_TYPE_RT
4427 },
4428 { }
4429 };
4430
4431 /* l4_cfg -> smartreflex_core */
4432 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
4433 .master = &omap44xx_l4_cfg_hwmod,
4434 .slave = &omap44xx_smartreflex_core_hwmod,
4435 .clk = "l4_div_ck",
4436 .addr = omap44xx_smartreflex_core_addrs,
4437 .user = OCP_USER_MPU | OCP_USER_SDMA,
4438 };
4439
4440 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
4441 {
4442 .pa_start = 0x4a0db000,
4443 .pa_end = 0x4a0db03f,
4444 .flags = ADDR_TYPE_RT
4445 },
4446 { }
4447 };
4448
4449 /* l4_cfg -> smartreflex_iva */
4450 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
4451 .master = &omap44xx_l4_cfg_hwmod,
4452 .slave = &omap44xx_smartreflex_iva_hwmod,
4453 .clk = "l4_div_ck",
4454 .addr = omap44xx_smartreflex_iva_addrs,
4455 .user = OCP_USER_MPU | OCP_USER_SDMA,
4456 };
4457
4458 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
4459 {
4460 .pa_start = 0x4a0d9000,
4461 .pa_end = 0x4a0d903f,
4462 .flags = ADDR_TYPE_RT
4463 },
4464 { }
4465 };
4466
4467 /* l4_cfg -> smartreflex_mpu */
4468 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
4469 .master = &omap44xx_l4_cfg_hwmod,
4470 .slave = &omap44xx_smartreflex_mpu_hwmod,
4471 .clk = "l4_div_ck",
4472 .addr = omap44xx_smartreflex_mpu_addrs,
4473 .user = OCP_USER_MPU | OCP_USER_SDMA,
4474 };
4475
4476 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
4477 {
4478 .pa_start = 0x4a0f6000,
4479 .pa_end = 0x4a0f6fff,
4480 .flags = ADDR_TYPE_RT
4481 },
4482 { }
4483 };
4484
4485 /* l4_cfg -> spinlock */
4486 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
4487 .master = &omap44xx_l4_cfg_hwmod,
4488 .slave = &omap44xx_spinlock_hwmod,
4489 .clk = "l4_div_ck",
4490 .addr = omap44xx_spinlock_addrs,
4491 .user = OCP_USER_MPU | OCP_USER_SDMA,
4492 };
4493
4494 /* l4_wkup -> timer1 */
4495 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4496 .master = &omap44xx_l4_wkup_hwmod,
4497 .slave = &omap44xx_timer1_hwmod,
4498 .clk = "l4_wkup_clk_mux_ck",
4499 .user = OCP_USER_MPU | OCP_USER_SDMA,
4500 };
4501
4502 /* l4_per -> timer2 */
4503 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4504 .master = &omap44xx_l4_per_hwmod,
4505 .slave = &omap44xx_timer2_hwmod,
4506 .clk = "l4_div_ck",
4507 .user = OCP_USER_MPU | OCP_USER_SDMA,
4508 };
4509
4510 /* l4_per -> timer3 */
4511 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4512 .master = &omap44xx_l4_per_hwmod,
4513 .slave = &omap44xx_timer3_hwmod,
4514 .clk = "l4_div_ck",
4515 .user = OCP_USER_MPU | OCP_USER_SDMA,
4516 };
4517
4518 /* l4_per -> timer4 */
4519 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4520 .master = &omap44xx_l4_per_hwmod,
4521 .slave = &omap44xx_timer4_hwmod,
4522 .clk = "l4_div_ck",
4523 .user = OCP_USER_MPU | OCP_USER_SDMA,
4524 };
4525
4526 /* l4_abe -> timer5 */
4527 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4528 .master = &omap44xx_l4_abe_hwmod,
4529 .slave = &omap44xx_timer5_hwmod,
4530 .clk = "ocp_abe_iclk",
4531 .user = OCP_USER_MPU | OCP_USER_SDMA,
4532 };
4533
4534 /* l4_abe -> timer6 */
4535 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4536 .master = &omap44xx_l4_abe_hwmod,
4537 .slave = &omap44xx_timer6_hwmod,
4538 .clk = "ocp_abe_iclk",
4539 .user = OCP_USER_MPU | OCP_USER_SDMA,
4540 };
4541
4542 /* l4_abe -> timer7 */
4543 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4544 .master = &omap44xx_l4_abe_hwmod,
4545 .slave = &omap44xx_timer7_hwmod,
4546 .clk = "ocp_abe_iclk",
4547 .user = OCP_USER_MPU | OCP_USER_SDMA,
4548 };
4549
4550 /* l4_abe -> timer8 */
4551 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4552 .master = &omap44xx_l4_abe_hwmod,
4553 .slave = &omap44xx_timer8_hwmod,
4554 .clk = "ocp_abe_iclk",
4555 .user = OCP_USER_MPU | OCP_USER_SDMA,
4556 };
4557
4558 /* l4_per -> timer9 */
4559 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4560 .master = &omap44xx_l4_per_hwmod,
4561 .slave = &omap44xx_timer9_hwmod,
4562 .clk = "l4_div_ck",
4563 .user = OCP_USER_MPU | OCP_USER_SDMA,
4564 };
4565
4566 /* l4_per -> timer10 */
4567 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4568 .master = &omap44xx_l4_per_hwmod,
4569 .slave = &omap44xx_timer10_hwmod,
4570 .clk = "l4_div_ck",
4571 .user = OCP_USER_MPU | OCP_USER_SDMA,
4572 };
4573
4574 /* l4_per -> timer11 */
4575 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4576 .master = &omap44xx_l4_per_hwmod,
4577 .slave = &omap44xx_timer11_hwmod,
4578 .clk = "l4_div_ck",
4579 .user = OCP_USER_MPU | OCP_USER_SDMA,
4580 };
4581
4582 /* l4_per -> uart1 */
4583 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4584 .master = &omap44xx_l4_per_hwmod,
4585 .slave = &omap44xx_uart1_hwmod,
4586 .clk = "l4_div_ck",
4587 .user = OCP_USER_MPU | OCP_USER_SDMA,
4588 };
4589
4590 /* l4_per -> uart2 */
4591 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4592 .master = &omap44xx_l4_per_hwmod,
4593 .slave = &omap44xx_uart2_hwmod,
4594 .clk = "l4_div_ck",
4595 .user = OCP_USER_MPU | OCP_USER_SDMA,
4596 };
4597
4598 /* l4_per -> uart3 */
4599 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4600 .master = &omap44xx_l4_per_hwmod,
4601 .slave = &omap44xx_uart3_hwmod,
4602 .clk = "l4_div_ck",
4603 .user = OCP_USER_MPU | OCP_USER_SDMA,
4604 };
4605
4606 /* l4_per -> uart4 */
4607 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
4608 .master = &omap44xx_l4_per_hwmod,
4609 .slave = &omap44xx_uart4_hwmod,
4610 .clk = "l4_div_ck",
4611 .user = OCP_USER_MPU | OCP_USER_SDMA,
4612 };
4613
4614 /* l4_cfg -> usb_host_fs */
4615 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
4616 .master = &omap44xx_l4_cfg_hwmod,
4617 .slave = &omap44xx_usb_host_fs_hwmod,
4618 .clk = "l4_div_ck",
4619 .user = OCP_USER_MPU | OCP_USER_SDMA,
4620 };
4621
4622 /* l4_cfg -> usb_host_hs */
4623 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
4624 .master = &omap44xx_l4_cfg_hwmod,
4625 .slave = &omap44xx_usb_host_hs_hwmod,
4626 .clk = "l4_div_ck",
4627 .user = OCP_USER_MPU | OCP_USER_SDMA,
4628 };
4629
4630 /* l4_cfg -> usb_otg_hs */
4631 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
4632 .master = &omap44xx_l4_cfg_hwmod,
4633 .slave = &omap44xx_usb_otg_hs_hwmod,
4634 .clk = "l4_div_ck",
4635 .user = OCP_USER_MPU | OCP_USER_SDMA,
4636 };
4637
4638 /* l4_cfg -> usb_tll_hs */
4639 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
4640 .master = &omap44xx_l4_cfg_hwmod,
4641 .slave = &omap44xx_usb_tll_hs_hwmod,
4642 .clk = "l4_div_ck",
4643 .user = OCP_USER_MPU | OCP_USER_SDMA,
4644 };
4645
4646 /* l4_wkup -> wd_timer2 */
4647 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
4648 .master = &omap44xx_l4_wkup_hwmod,
4649 .slave = &omap44xx_wd_timer2_hwmod,
4650 .clk = "l4_wkup_clk_mux_ck",
4651 .user = OCP_USER_MPU | OCP_USER_SDMA,
4652 };
4653
4654 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
4655 {
4656 .pa_start = 0x40130000,
4657 .pa_end = 0x4013007f,
4658 .flags = ADDR_TYPE_RT
4659 },
4660 { }
4661 };
4662
4663 /* l4_abe -> wd_timer3 */
4664 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
4665 .master = &omap44xx_l4_abe_hwmod,
4666 .slave = &omap44xx_wd_timer3_hwmod,
4667 .clk = "ocp_abe_iclk",
4668 .addr = omap44xx_wd_timer3_addrs,
4669 .user = OCP_USER_MPU,
4670 };
4671
4672 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
4673 {
4674 .pa_start = 0x49030000,
4675 .pa_end = 0x4903007f,
4676 .flags = ADDR_TYPE_RT
4677 },
4678 { }
4679 };
4680
4681 /* l4_abe -> wd_timer3 (dma) */
4682 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
4683 .master = &omap44xx_l4_abe_hwmod,
4684 .slave = &omap44xx_wd_timer3_hwmod,
4685 .clk = "ocp_abe_iclk",
4686 .addr = omap44xx_wd_timer3_dma_addrs,
4687 .user = OCP_USER_SDMA,
4688 };
4689
4690 /* mpu -> emif1 */
4691 static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
4692 .master = &omap44xx_mpu_hwmod,
4693 .slave = &omap44xx_emif1_hwmod,
4694 .clk = "l3_div_ck",
4695 .user = OCP_USER_MPU | OCP_USER_SDMA,
4696 };
4697
4698 /* mpu -> emif2 */
4699 static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
4700 .master = &omap44xx_mpu_hwmod,
4701 .slave = &omap44xx_emif2_hwmod,
4702 .clk = "l3_div_ck",
4703 .user = OCP_USER_MPU | OCP_USER_SDMA,
4704 };
4705
4706 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
4707 &omap44xx_l3_main_1__dmm,
4708 &omap44xx_mpu__dmm,
4709 &omap44xx_iva__l3_instr,
4710 &omap44xx_l3_main_3__l3_instr,
4711 &omap44xx_ocp_wp_noc__l3_instr,
4712 &omap44xx_dsp__l3_main_1,
4713 &omap44xx_dss__l3_main_1,
4714 &omap44xx_l3_main_2__l3_main_1,
4715 &omap44xx_l4_cfg__l3_main_1,
4716 &omap44xx_mmc1__l3_main_1,
4717 &omap44xx_mmc2__l3_main_1,
4718 &omap44xx_mpu__l3_main_1,
4719 &omap44xx_debugss__l3_main_2,
4720 &omap44xx_dma_system__l3_main_2,
4721 &omap44xx_fdif__l3_main_2,
4722 &omap44xx_gpu__l3_main_2,
4723 &omap44xx_hsi__l3_main_2,
4724 &omap44xx_ipu__l3_main_2,
4725 &omap44xx_iss__l3_main_2,
4726 &omap44xx_iva__l3_main_2,
4727 &omap44xx_l3_main_1__l3_main_2,
4728 &omap44xx_l4_cfg__l3_main_2,
4729 /* &omap44xx_usb_host_fs__l3_main_2, */
4730 &omap44xx_usb_host_hs__l3_main_2,
4731 &omap44xx_usb_otg_hs__l3_main_2,
4732 &omap44xx_l3_main_1__l3_main_3,
4733 &omap44xx_l3_main_2__l3_main_3,
4734 &omap44xx_l4_cfg__l3_main_3,
4735 &omap44xx_aess__l4_abe,
4736 &omap44xx_dsp__l4_abe,
4737 &omap44xx_l3_main_1__l4_abe,
4738 &omap44xx_mpu__l4_abe,
4739 &omap44xx_l3_main_1__l4_cfg,
4740 &omap44xx_l3_main_2__l4_per,
4741 &omap44xx_l4_cfg__l4_wkup,
4742 &omap44xx_mpu__mpu_private,
4743 &omap44xx_l4_cfg__ocp_wp_noc,
4744 &omap44xx_l4_abe__aess,
4745 &omap44xx_l4_abe__aess_dma,
4746 &omap44xx_l3_main_2__c2c,
4747 &omap44xx_l4_wkup__counter_32k,
4748 &omap44xx_l4_cfg__ctrl_module_core,
4749 &omap44xx_l4_cfg__ctrl_module_pad_core,
4750 &omap44xx_l4_wkup__ctrl_module_wkup,
4751 &omap44xx_l4_wkup__ctrl_module_pad_wkup,
4752 &omap44xx_l3_instr__debugss,
4753 &omap44xx_l4_cfg__dma_system,
4754 &omap44xx_l4_abe__dmic,
4755 &omap44xx_dsp__iva,
4756 /* &omap44xx_dsp__sl2if, */
4757 &omap44xx_l4_cfg__dsp,
4758 &omap44xx_l3_main_2__dss,
4759 &omap44xx_l4_per__dss,
4760 &omap44xx_l3_main_2__dss_dispc,
4761 &omap44xx_l4_per__dss_dispc,
4762 &omap44xx_l3_main_2__dss_dsi1,
4763 &omap44xx_l4_per__dss_dsi1,
4764 &omap44xx_l3_main_2__dss_dsi2,
4765 &omap44xx_l4_per__dss_dsi2,
4766 &omap44xx_l3_main_2__dss_hdmi,
4767 &omap44xx_l4_per__dss_hdmi,
4768 &omap44xx_l3_main_2__dss_rfbi,
4769 &omap44xx_l4_per__dss_rfbi,
4770 &omap44xx_l3_main_2__dss_venc,
4771 &omap44xx_l4_per__dss_venc,
4772 &omap44xx_l4_per__elm,
4773 &omap44xx_l4_cfg__fdif,
4774 &omap44xx_l4_wkup__gpio1,
4775 &omap44xx_l4_per__gpio2,
4776 &omap44xx_l4_per__gpio3,
4777 &omap44xx_l4_per__gpio4,
4778 &omap44xx_l4_per__gpio5,
4779 &omap44xx_l4_per__gpio6,
4780 &omap44xx_l3_main_2__gpmc,
4781 &omap44xx_l3_main_2__gpu,
4782 &omap44xx_l4_per__hdq1w,
4783 &omap44xx_l4_cfg__hsi,
4784 &omap44xx_l4_per__i2c1,
4785 &omap44xx_l4_per__i2c2,
4786 &omap44xx_l4_per__i2c3,
4787 &omap44xx_l4_per__i2c4,
4788 &omap44xx_l3_main_2__ipu,
4789 &omap44xx_l3_main_2__iss,
4790 /* &omap44xx_iva__sl2if, */
4791 &omap44xx_l3_main_2__iva,
4792 &omap44xx_l4_wkup__kbd,
4793 &omap44xx_l4_cfg__mailbox,
4794 &omap44xx_l4_abe__mcasp,
4795 &omap44xx_l4_abe__mcasp_dma,
4796 &omap44xx_l4_abe__mcbsp1,
4797 &omap44xx_l4_abe__mcbsp2,
4798 &omap44xx_l4_abe__mcbsp3,
4799 &omap44xx_l4_per__mcbsp4,
4800 &omap44xx_l4_abe__mcpdm,
4801 &omap44xx_l4_per__mcspi1,
4802 &omap44xx_l4_per__mcspi2,
4803 &omap44xx_l4_per__mcspi3,
4804 &omap44xx_l4_per__mcspi4,
4805 &omap44xx_l4_per__mmc1,
4806 &omap44xx_l4_per__mmc2,
4807 &omap44xx_l4_per__mmc3,
4808 &omap44xx_l4_per__mmc4,
4809 &omap44xx_l4_per__mmc5,
4810 &omap44xx_l3_main_2__mmu_ipu,
4811 &omap44xx_l4_cfg__mmu_dsp,
4812 &omap44xx_l3_main_2__ocmc_ram,
4813 &omap44xx_l4_cfg__ocp2scp_usb_phy,
4814 &omap44xx_mpu_private__prcm_mpu,
4815 &omap44xx_l4_wkup__cm_core_aon,
4816 &omap44xx_l4_cfg__cm_core,
4817 &omap44xx_l4_wkup__prm,
4818 &omap44xx_l4_wkup__scrm,
4819 /* &omap44xx_l3_main_2__sl2if, */
4820 &omap44xx_l4_abe__slimbus1,
4821 &omap44xx_l4_abe__slimbus1_dma,
4822 &omap44xx_l4_per__slimbus2,
4823 &omap44xx_l4_cfg__smartreflex_core,
4824 &omap44xx_l4_cfg__smartreflex_iva,
4825 &omap44xx_l4_cfg__smartreflex_mpu,
4826 &omap44xx_l4_cfg__spinlock,
4827 &omap44xx_l4_wkup__timer1,
4828 &omap44xx_l4_per__timer2,
4829 &omap44xx_l4_per__timer3,
4830 &omap44xx_l4_per__timer4,
4831 &omap44xx_l4_abe__timer5,
4832 &omap44xx_l4_abe__timer6,
4833 &omap44xx_l4_abe__timer7,
4834 &omap44xx_l4_abe__timer8,
4835 &omap44xx_l4_per__timer9,
4836 &omap44xx_l4_per__timer10,
4837 &omap44xx_l4_per__timer11,
4838 &omap44xx_l4_per__uart1,
4839 &omap44xx_l4_per__uart2,
4840 &omap44xx_l4_per__uart3,
4841 &omap44xx_l4_per__uart4,
4842 /* &omap44xx_l4_cfg__usb_host_fs, */
4843 &omap44xx_l4_cfg__usb_host_hs,
4844 &omap44xx_l4_cfg__usb_otg_hs,
4845 &omap44xx_l4_cfg__usb_tll_hs,
4846 &omap44xx_l4_wkup__wd_timer2,
4847 &omap44xx_l4_abe__wd_timer3,
4848 &omap44xx_l4_abe__wd_timer3_dma,
4849 &omap44xx_mpu__emif1,
4850 &omap44xx_mpu__emif2,
4851 NULL,
4852 };
4853
4854 int __init omap44xx_hwmod_init(void)
4855 {
4856 omap_hwmod_init();
4857 return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
4858 }
4859
Linux kernel - Deliverables
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