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Merge branch 'cleanup-hwmod' into cleanup
[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_44xx_data.c
1 /*
2 * Hardware modules present on the OMAP44xx chips
3 *
4 * Copyright (C) 2009-2012 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley
8 * Benoit Cousson
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21 #include <linux/io.h>
22
23 #include <plat/omap_hwmod.h>
24 #include <plat/cpu.h>
25 #include <plat/i2c.h>
26 #include <plat/gpio.h>
27 #include <plat/dma.h>
28 #include <plat/mcspi.h>
29 #include <plat/mcbsp.h>
30 #include <plat/mmc.h>
31 #include <plat/dmtimer.h>
32 #include <plat/common.h>
33
34 #include "omap_hwmod_common_data.h"
35
36 #include "smartreflex.h"
37 #include "cm1_44xx.h"
38 #include "cm2_44xx.h"
39 #include "prm44xx.h"
40 #include "prm-regbits-44xx.h"
41 #include "wd_timer.h"
42
43 /* Base offset for all OMAP4 interrupts external to MPUSS */
44 #define OMAP44XX_IRQ_GIC_START 32
45
46 /* Base offset for all OMAP4 dma requests */
47 #define OMAP44XX_DMA_REQ_START 1
48
49 /*
50 * IP blocks
51 */
52
53 /*
54 * 'c2c_target_fw' class
55 * instance(s): c2c_target_fw
56 */
57 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
58 .name = "c2c_target_fw",
59 };
60
61 /* c2c_target_fw */
62 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
63 .name = "c2c_target_fw",
64 .class = &omap44xx_c2c_target_fw_hwmod_class,
65 .clkdm_name = "d2d_clkdm",
66 .prcm = {
67 .omap4 = {
68 .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
69 .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
70 },
71 },
72 };
73
74 /*
75 * 'dmm' class
76 * instance(s): dmm
77 */
78 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
79 .name = "dmm",
80 };
81
82 /* dmm */
83 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
84 { .irq = 113 + OMAP44XX_IRQ_GIC_START },
85 { .irq = -1 }
86 };
87
88 static struct omap_hwmod omap44xx_dmm_hwmod = {
89 .name = "dmm",
90 .class = &omap44xx_dmm_hwmod_class,
91 .clkdm_name = "l3_emif_clkdm",
92 .mpu_irqs = omap44xx_dmm_irqs,
93 .prcm = {
94 .omap4 = {
95 .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
96 .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
97 },
98 },
99 };
100
101 /*
102 * 'emif_fw' class
103 * instance(s): emif_fw
104 */
105 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
106 .name = "emif_fw",
107 };
108
109 /* emif_fw */
110 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
111 .name = "emif_fw",
112 .class = &omap44xx_emif_fw_hwmod_class,
113 .clkdm_name = "l3_emif_clkdm",
114 .prcm = {
115 .omap4 = {
116 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
117 .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
118 },
119 },
120 };
121
122 /*
123 * 'l3' class
124 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
125 */
126 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
127 .name = "l3",
128 };
129
130 /* l3_instr */
131 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
132 .name = "l3_instr",
133 .class = &omap44xx_l3_hwmod_class,
134 .clkdm_name = "l3_instr_clkdm",
135 .prcm = {
136 .omap4 = {
137 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
138 .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
139 .modulemode = MODULEMODE_HWCTRL,
140 },
141 },
142 };
143
144 /* l3_main_1 */
145 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
146 { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
147 { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
148 { .irq = -1 }
149 };
150
151 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
152 .name = "l3_main_1",
153 .class = &omap44xx_l3_hwmod_class,
154 .clkdm_name = "l3_1_clkdm",
155 .mpu_irqs = omap44xx_l3_main_1_irqs,
156 .prcm = {
157 .omap4 = {
158 .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
159 .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
160 },
161 },
162 };
163
164 /* l3_main_2 */
165 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
166 .name = "l3_main_2",
167 .class = &omap44xx_l3_hwmod_class,
168 .clkdm_name = "l3_2_clkdm",
169 .prcm = {
170 .omap4 = {
171 .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
172 .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
173 },
174 },
175 };
176
177 /* l3_main_3 */
178 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
179 .name = "l3_main_3",
180 .class = &omap44xx_l3_hwmod_class,
181 .clkdm_name = "l3_instr_clkdm",
182 .prcm = {
183 .omap4 = {
184 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
185 .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
186 .modulemode = MODULEMODE_HWCTRL,
187 },
188 },
189 };
190
191 /*
192 * 'l4' class
193 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
194 */
195 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
196 .name = "l4",
197 };
198
199 /* l4_abe */
200 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
201 .name = "l4_abe",
202 .class = &omap44xx_l4_hwmod_class,
203 .clkdm_name = "abe_clkdm",
204 .prcm = {
205 .omap4 = {
206 .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
207 },
208 },
209 };
210
211 /* l4_cfg */
212 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
213 .name = "l4_cfg",
214 .class = &omap44xx_l4_hwmod_class,
215 .clkdm_name = "l4_cfg_clkdm",
216 .prcm = {
217 .omap4 = {
218 .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
219 .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
220 },
221 },
222 };
223
224 /* l4_per */
225 static struct omap_hwmod omap44xx_l4_per_hwmod = {
226 .name = "l4_per",
227 .class = &omap44xx_l4_hwmod_class,
228 .clkdm_name = "l4_per_clkdm",
229 .prcm = {
230 .omap4 = {
231 .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
232 .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
233 },
234 },
235 };
236
237 /* l4_wkup */
238 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
239 .name = "l4_wkup",
240 .class = &omap44xx_l4_hwmod_class,
241 .clkdm_name = "l4_wkup_clkdm",
242 .prcm = {
243 .omap4 = {
244 .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
245 .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
246 },
247 },
248 };
249
250 /*
251 * 'mpu_bus' class
252 * instance(s): mpu_private
253 */
254 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
255 .name = "mpu_bus",
256 };
257
258 /* mpu_private */
259 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
260 .name = "mpu_private",
261 .class = &omap44xx_mpu_bus_hwmod_class,
262 .clkdm_name = "mpuss_clkdm",
263 };
264
265 /*
266 * 'ocp_wp_noc' class
267 * instance(s): ocp_wp_noc
268 */
269 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
270 .name = "ocp_wp_noc",
271 };
272
273 /* ocp_wp_noc */
274 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
275 .name = "ocp_wp_noc",
276 .class = &omap44xx_ocp_wp_noc_hwmod_class,
277 .clkdm_name = "l3_instr_clkdm",
278 .prcm = {
279 .omap4 = {
280 .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
281 .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
282 .modulemode = MODULEMODE_HWCTRL,
283 },
284 },
285 };
286
287 /*
288 * Modules omap_hwmod structures
289 *
290 * The following IPs are excluded for the moment because:
291 * - They do not need an explicit SW control using omap_hwmod API.
292 * - They still need to be validated with the driver
293 * properly adapted to omap_hwmod / omap_device
294 *
295 * usim
296 */
297
298 /*
299 * 'aess' class
300 * audio engine sub system
301 */
302
303 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
304 .rev_offs = 0x0000,
305 .sysc_offs = 0x0010,
306 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
307 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
308 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
309 MSTANDBY_SMART_WKUP),
310 .sysc_fields = &omap_hwmod_sysc_type2,
311 };
312
313 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
314 .name = "aess",
315 .sysc = &omap44xx_aess_sysc,
316 };
317
318 /* aess */
319 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
320 { .irq = 99 + OMAP44XX_IRQ_GIC_START },
321 { .irq = -1 }
322 };
323
324 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
325 { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
326 { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
327 { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
328 { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
329 { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
330 { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
331 { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
332 { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
333 { .dma_req = -1 }
334 };
335
336 static struct omap_hwmod omap44xx_aess_hwmod = {
337 .name = "aess",
338 .class = &omap44xx_aess_hwmod_class,
339 .clkdm_name = "abe_clkdm",
340 .mpu_irqs = omap44xx_aess_irqs,
341 .sdma_reqs = omap44xx_aess_sdma_reqs,
342 .main_clk = "aess_fck",
343 .prcm = {
344 .omap4 = {
345 .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
346 .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
347 .modulemode = MODULEMODE_SWCTRL,
348 },
349 },
350 };
351
352 /*
353 * 'c2c' class
354 * chip 2 chip interface used to plug the ape soc (omap) with an external modem
355 * soc
356 */
357
358 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
359 .name = "c2c",
360 };
361
362 /* c2c */
363 static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
364 { .irq = 88 + OMAP44XX_IRQ_GIC_START },
365 { .irq = -1 }
366 };
367
368 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
369 { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
370 { .dma_req = -1 }
371 };
372
373 static struct omap_hwmod omap44xx_c2c_hwmod = {
374 .name = "c2c",
375 .class = &omap44xx_c2c_hwmod_class,
376 .clkdm_name = "d2d_clkdm",
377 .mpu_irqs = omap44xx_c2c_irqs,
378 .sdma_reqs = omap44xx_c2c_sdma_reqs,
379 .prcm = {
380 .omap4 = {
381 .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
382 .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
383 },
384 },
385 };
386
387 /*
388 * 'counter' class
389 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
390 */
391
392 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
393 .rev_offs = 0x0000,
394 .sysc_offs = 0x0004,
395 .sysc_flags = SYSC_HAS_SIDLEMODE,
396 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
397 .sysc_fields = &omap_hwmod_sysc_type1,
398 };
399
400 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
401 .name = "counter",
402 .sysc = &omap44xx_counter_sysc,
403 };
404
405 /* counter_32k */
406 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
407 .name = "counter_32k",
408 .class = &omap44xx_counter_hwmod_class,
409 .clkdm_name = "l4_wkup_clkdm",
410 .flags = HWMOD_SWSUP_SIDLE,
411 .main_clk = "sys_32k_ck",
412 .prcm = {
413 .omap4 = {
414 .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
415 .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
416 },
417 },
418 };
419
420 /*
421 * 'ctrl_module' class
422 * attila core control module + core pad control module + wkup pad control
423 * module + attila wkup control module
424 */
425
426 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
427 .rev_offs = 0x0000,
428 .sysc_offs = 0x0010,
429 .sysc_flags = SYSC_HAS_SIDLEMODE,
430 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
431 SIDLE_SMART_WKUP),
432 .sysc_fields = &omap_hwmod_sysc_type2,
433 };
434
435 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
436 .name = "ctrl_module",
437 .sysc = &omap44xx_ctrl_module_sysc,
438 };
439
440 /* ctrl_module_core */
441 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
442 { .irq = 8 + OMAP44XX_IRQ_GIC_START },
443 { .irq = -1 }
444 };
445
446 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
447 .name = "ctrl_module_core",
448 .class = &omap44xx_ctrl_module_hwmod_class,
449 .clkdm_name = "l4_cfg_clkdm",
450 .mpu_irqs = omap44xx_ctrl_module_core_irqs,
451 };
452
453 /* ctrl_module_pad_core */
454 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
455 .name = "ctrl_module_pad_core",
456 .class = &omap44xx_ctrl_module_hwmod_class,
457 .clkdm_name = "l4_cfg_clkdm",
458 };
459
460 /* ctrl_module_wkup */
461 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
462 .name = "ctrl_module_wkup",
463 .class = &omap44xx_ctrl_module_hwmod_class,
464 .clkdm_name = "l4_wkup_clkdm",
465 };
466
467 /* ctrl_module_pad_wkup */
468 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
469 .name = "ctrl_module_pad_wkup",
470 .class = &omap44xx_ctrl_module_hwmod_class,
471 .clkdm_name = "l4_wkup_clkdm",
472 };
473
474 /*
475 * 'debugss' class
476 * debug and emulation sub system
477 */
478
479 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
480 .name = "debugss",
481 };
482
483 /* debugss */
484 static struct omap_hwmod omap44xx_debugss_hwmod = {
485 .name = "debugss",
486 .class = &omap44xx_debugss_hwmod_class,
487 .clkdm_name = "emu_sys_clkdm",
488 .main_clk = "trace_clk_div_ck",
489 .prcm = {
490 .omap4 = {
491 .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
492 .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
493 },
494 },
495 };
496
497 /*
498 * 'dma' class
499 * dma controller for data exchange between memory to memory (i.e. internal or
500 * external memory) and gp peripherals to memory or memory to gp peripherals
501 */
502
503 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
504 .rev_offs = 0x0000,
505 .sysc_offs = 0x002c,
506 .syss_offs = 0x0028,
507 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
508 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
509 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
510 SYSS_HAS_RESET_STATUS),
511 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
512 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
513 .sysc_fields = &omap_hwmod_sysc_type1,
514 };
515
516 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
517 .name = "dma",
518 .sysc = &omap44xx_dma_sysc,
519 };
520
521 /* dma dev_attr */
522 static struct omap_dma_dev_attr dma_dev_attr = {
523 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
524 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
525 .lch_count = 32,
526 };
527
528 /* dma_system */
529 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
530 { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
531 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
532 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
533 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
534 { .irq = -1 }
535 };
536
537 static struct omap_hwmod omap44xx_dma_system_hwmod = {
538 .name = "dma_system",
539 .class = &omap44xx_dma_hwmod_class,
540 .clkdm_name = "l3_dma_clkdm",
541 .mpu_irqs = omap44xx_dma_system_irqs,
542 .main_clk = "l3_div_ck",
543 .prcm = {
544 .omap4 = {
545 .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
546 .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
547 },
548 },
549 .dev_attr = &dma_dev_attr,
550 };
551
552 /*
553 * 'dmic' class
554 * digital microphone controller
555 */
556
557 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
558 .rev_offs = 0x0000,
559 .sysc_offs = 0x0010,
560 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
561 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
562 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
563 SIDLE_SMART_WKUP),
564 .sysc_fields = &omap_hwmod_sysc_type2,
565 };
566
567 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
568 .name = "dmic",
569 .sysc = &omap44xx_dmic_sysc,
570 };
571
572 /* dmic */
573 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
574 { .irq = 114 + OMAP44XX_IRQ_GIC_START },
575 { .irq = -1 }
576 };
577
578 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
579 { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
580 { .dma_req = -1 }
581 };
582
583 static struct omap_hwmod omap44xx_dmic_hwmod = {
584 .name = "dmic",
585 .class = &omap44xx_dmic_hwmod_class,
586 .clkdm_name = "abe_clkdm",
587 .mpu_irqs = omap44xx_dmic_irqs,
588 .sdma_reqs = omap44xx_dmic_sdma_reqs,
589 .main_clk = "dmic_fck",
590 .prcm = {
591 .omap4 = {
592 .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
593 .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
594 .modulemode = MODULEMODE_SWCTRL,
595 },
596 },
597 };
598
599 /*
600 * 'dsp' class
601 * dsp sub-system
602 */
603
604 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
605 .name = "dsp",
606 };
607
608 /* dsp */
609 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
610 { .irq = 28 + OMAP44XX_IRQ_GIC_START },
611 { .irq = -1 }
612 };
613
614 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
615 { .name = "dsp", .rst_shift = 0 },
616 { .name = "mmu_cache", .rst_shift = 1 },
617 };
618
619 static struct omap_hwmod omap44xx_dsp_hwmod = {
620 .name = "dsp",
621 .class = &omap44xx_dsp_hwmod_class,
622 .clkdm_name = "tesla_clkdm",
623 .mpu_irqs = omap44xx_dsp_irqs,
624 .rst_lines = omap44xx_dsp_resets,
625 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
626 .main_clk = "dsp_fck",
627 .prcm = {
628 .omap4 = {
629 .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
630 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
631 .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
632 .modulemode = MODULEMODE_HWCTRL,
633 },
634 },
635 };
636
637 /*
638 * 'dss' class
639 * display sub-system
640 */
641
642 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
643 .rev_offs = 0x0000,
644 .syss_offs = 0x0014,
645 .sysc_flags = SYSS_HAS_RESET_STATUS,
646 };
647
648 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
649 .name = "dss",
650 .sysc = &omap44xx_dss_sysc,
651 .reset = omap_dss_reset,
652 };
653
654 /* dss */
655 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
656 { .role = "sys_clk", .clk = "dss_sys_clk" },
657 { .role = "tv_clk", .clk = "dss_tv_clk" },
658 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
659 };
660
661 static struct omap_hwmod omap44xx_dss_hwmod = {
662 .name = "dss_core",
663 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
664 .class = &omap44xx_dss_hwmod_class,
665 .clkdm_name = "l3_dss_clkdm",
666 .main_clk = "dss_dss_clk",
667 .prcm = {
668 .omap4 = {
669 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
670 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
671 },
672 },
673 .opt_clks = dss_opt_clks,
674 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
675 };
676
677 /*
678 * 'dispc' class
679 * display controller
680 */
681
682 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
683 .rev_offs = 0x0000,
684 .sysc_offs = 0x0010,
685 .syss_offs = 0x0014,
686 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
687 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
688 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
689 SYSS_HAS_RESET_STATUS),
690 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
691 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
692 .sysc_fields = &omap_hwmod_sysc_type1,
693 };
694
695 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
696 .name = "dispc",
697 .sysc = &omap44xx_dispc_sysc,
698 };
699
700 /* dss_dispc */
701 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
702 { .irq = 25 + OMAP44XX_IRQ_GIC_START },
703 { .irq = -1 }
704 };
705
706 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
707 { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
708 { .dma_req = -1 }
709 };
710
711 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
712 .manager_count = 3,
713 .has_framedonetv_irq = 1
714 };
715
716 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
717 .name = "dss_dispc",
718 .class = &omap44xx_dispc_hwmod_class,
719 .clkdm_name = "l3_dss_clkdm",
720 .mpu_irqs = omap44xx_dss_dispc_irqs,
721 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
722 .main_clk = "dss_dss_clk",
723 .prcm = {
724 .omap4 = {
725 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
726 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
727 },
728 },
729 .dev_attr = &omap44xx_dss_dispc_dev_attr
730 };
731
732 /*
733 * 'dsi' class
734 * display serial interface controller
735 */
736
737 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
738 .rev_offs = 0x0000,
739 .sysc_offs = 0x0010,
740 .syss_offs = 0x0014,
741 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
742 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
743 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
744 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
745 .sysc_fields = &omap_hwmod_sysc_type1,
746 };
747
748 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
749 .name = "dsi",
750 .sysc = &omap44xx_dsi_sysc,
751 };
752
753 /* dss_dsi1 */
754 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
755 { .irq = 53 + OMAP44XX_IRQ_GIC_START },
756 { .irq = -1 }
757 };
758
759 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
760 { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
761 { .dma_req = -1 }
762 };
763
764 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
765 { .role = "sys_clk", .clk = "dss_sys_clk" },
766 };
767
768 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
769 .name = "dss_dsi1",
770 .class = &omap44xx_dsi_hwmod_class,
771 .clkdm_name = "l3_dss_clkdm",
772 .mpu_irqs = omap44xx_dss_dsi1_irqs,
773 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
774 .main_clk = "dss_dss_clk",
775 .prcm = {
776 .omap4 = {
777 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
778 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
779 },
780 },
781 .opt_clks = dss_dsi1_opt_clks,
782 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
783 };
784
785 /* dss_dsi2 */
786 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
787 { .irq = 84 + OMAP44XX_IRQ_GIC_START },
788 { .irq = -1 }
789 };
790
791 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
792 { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
793 { .dma_req = -1 }
794 };
795
796 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
797 { .role = "sys_clk", .clk = "dss_sys_clk" },
798 };
799
800 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
801 .name = "dss_dsi2",
802 .class = &omap44xx_dsi_hwmod_class,
803 .clkdm_name = "l3_dss_clkdm",
804 .mpu_irqs = omap44xx_dss_dsi2_irqs,
805 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
806 .main_clk = "dss_dss_clk",
807 .prcm = {
808 .omap4 = {
809 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
810 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
811 },
812 },
813 .opt_clks = dss_dsi2_opt_clks,
814 .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
815 };
816
817 /*
818 * 'hdmi' class
819 * hdmi controller
820 */
821
822 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
823 .rev_offs = 0x0000,
824 .sysc_offs = 0x0010,
825 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
826 SYSC_HAS_SOFTRESET),
827 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
828 SIDLE_SMART_WKUP),
829 .sysc_fields = &omap_hwmod_sysc_type2,
830 };
831
832 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
833 .name = "hdmi",
834 .sysc = &omap44xx_hdmi_sysc,
835 };
836
837 /* dss_hdmi */
838 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
839 { .irq = 101 + OMAP44XX_IRQ_GIC_START },
840 { .irq = -1 }
841 };
842
843 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
844 { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
845 { .dma_req = -1 }
846 };
847
848 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
849 { .role = "sys_clk", .clk = "dss_sys_clk" },
850 };
851
852 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
853 .name = "dss_hdmi",
854 .class = &omap44xx_hdmi_hwmod_class,
855 .clkdm_name = "l3_dss_clkdm",
856 /*
857 * HDMI audio requires to use no-idle mode. Hence,
858 * set idle mode by software.
859 */
860 .flags = HWMOD_SWSUP_SIDLE,
861 .mpu_irqs = omap44xx_dss_hdmi_irqs,
862 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
863 .main_clk = "dss_48mhz_clk",
864 .prcm = {
865 .omap4 = {
866 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
867 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
868 },
869 },
870 .opt_clks = dss_hdmi_opt_clks,
871 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
872 };
873
874 /*
875 * 'rfbi' class
876 * remote frame buffer interface
877 */
878
879 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
880 .rev_offs = 0x0000,
881 .sysc_offs = 0x0010,
882 .syss_offs = 0x0014,
883 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
884 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
885 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
886 .sysc_fields = &omap_hwmod_sysc_type1,
887 };
888
889 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
890 .name = "rfbi",
891 .sysc = &omap44xx_rfbi_sysc,
892 };
893
894 /* dss_rfbi */
895 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
896 { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
897 { .dma_req = -1 }
898 };
899
900 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
901 { .role = "ick", .clk = "dss_fck" },
902 };
903
904 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
905 .name = "dss_rfbi",
906 .class = &omap44xx_rfbi_hwmod_class,
907 .clkdm_name = "l3_dss_clkdm",
908 .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
909 .main_clk = "dss_dss_clk",
910 .prcm = {
911 .omap4 = {
912 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
913 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
914 },
915 },
916 .opt_clks = dss_rfbi_opt_clks,
917 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
918 };
919
920 /*
921 * 'venc' class
922 * video encoder
923 */
924
925 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
926 .name = "venc",
927 };
928
929 /* dss_venc */
930 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
931 .name = "dss_venc",
932 .class = &omap44xx_venc_hwmod_class,
933 .clkdm_name = "l3_dss_clkdm",
934 .main_clk = "dss_tv_clk",
935 .prcm = {
936 .omap4 = {
937 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
938 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
939 },
940 },
941 };
942
943 /*
944 * 'elm' class
945 * bch error location module
946 */
947
948 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
949 .rev_offs = 0x0000,
950 .sysc_offs = 0x0010,
951 .syss_offs = 0x0014,
952 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
953 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
954 SYSS_HAS_RESET_STATUS),
955 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
956 .sysc_fields = &omap_hwmod_sysc_type1,
957 };
958
959 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
960 .name = "elm",
961 .sysc = &omap44xx_elm_sysc,
962 };
963
964 /* elm */
965 static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
966 { .irq = 4 + OMAP44XX_IRQ_GIC_START },
967 { .irq = -1 }
968 };
969
970 static struct omap_hwmod omap44xx_elm_hwmod = {
971 .name = "elm",
972 .class = &omap44xx_elm_hwmod_class,
973 .clkdm_name = "l4_per_clkdm",
974 .mpu_irqs = omap44xx_elm_irqs,
975 .prcm = {
976 .omap4 = {
977 .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
978 .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
979 },
980 },
981 };
982
983 /*
984 * 'emif' class
985 * external memory interface no1
986 */
987
988 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
989 .rev_offs = 0x0000,
990 };
991
992 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
993 .name = "emif",
994 .sysc = &omap44xx_emif_sysc,
995 };
996
997 /* emif1 */
998 static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
999 { .irq = 110 + OMAP44XX_IRQ_GIC_START },
1000 { .irq = -1 }
1001 };
1002
1003 static struct omap_hwmod omap44xx_emif1_hwmod = {
1004 .name = "emif1",
1005 .class = &omap44xx_emif_hwmod_class,
1006 .clkdm_name = "l3_emif_clkdm",
1007 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1008 .mpu_irqs = omap44xx_emif1_irqs,
1009 .main_clk = "ddrphy_ck",
1010 .prcm = {
1011 .omap4 = {
1012 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
1013 .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
1014 .modulemode = MODULEMODE_HWCTRL,
1015 },
1016 },
1017 };
1018
1019 /* emif2 */
1020 static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
1021 { .irq = 111 + OMAP44XX_IRQ_GIC_START },
1022 { .irq = -1 }
1023 };
1024
1025 static struct omap_hwmod omap44xx_emif2_hwmod = {
1026 .name = "emif2",
1027 .class = &omap44xx_emif_hwmod_class,
1028 .clkdm_name = "l3_emif_clkdm",
1029 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1030 .mpu_irqs = omap44xx_emif2_irqs,
1031 .main_clk = "ddrphy_ck",
1032 .prcm = {
1033 .omap4 = {
1034 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
1035 .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
1036 .modulemode = MODULEMODE_HWCTRL,
1037 },
1038 },
1039 };
1040
1041 /*
1042 * 'fdif' class
1043 * face detection hw accelerator module
1044 */
1045
1046 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1047 .rev_offs = 0x0000,
1048 .sysc_offs = 0x0010,
1049 /*
1050 * FDIF needs 100 OCP clk cycles delay after a softreset before
1051 * accessing sysconfig again.
1052 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1053 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1054 *
1055 * TODO: Indicate errata when available.
1056 */
1057 .srst_udelay = 2,
1058 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1059 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1060 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1061 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1062 .sysc_fields = &omap_hwmod_sysc_type2,
1063 };
1064
1065 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1066 .name = "fdif",
1067 .sysc = &omap44xx_fdif_sysc,
1068 };
1069
1070 /* fdif */
1071 static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1072 { .irq = 69 + OMAP44XX_IRQ_GIC_START },
1073 { .irq = -1 }
1074 };
1075
1076 static struct omap_hwmod omap44xx_fdif_hwmod = {
1077 .name = "fdif",
1078 .class = &omap44xx_fdif_hwmod_class,
1079 .clkdm_name = "iss_clkdm",
1080 .mpu_irqs = omap44xx_fdif_irqs,
1081 .main_clk = "fdif_fck",
1082 .prcm = {
1083 .omap4 = {
1084 .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1085 .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1086 .modulemode = MODULEMODE_SWCTRL,
1087 },
1088 },
1089 };
1090
1091 /*
1092 * 'gpio' class
1093 * general purpose io module
1094 */
1095
1096 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1097 .rev_offs = 0x0000,
1098 .sysc_offs = 0x0010,
1099 .syss_offs = 0x0114,
1100 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1101 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1102 SYSS_HAS_RESET_STATUS),
1103 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1104 SIDLE_SMART_WKUP),
1105 .sysc_fields = &omap_hwmod_sysc_type1,
1106 };
1107
1108 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1109 .name = "gpio",
1110 .sysc = &omap44xx_gpio_sysc,
1111 .rev = 2,
1112 };
1113
1114 /* gpio dev_attr */
1115 static struct omap_gpio_dev_attr gpio_dev_attr = {
1116 .bank_width = 32,
1117 .dbck_flag = true,
1118 };
1119
1120 /* gpio1 */
1121 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1122 { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1123 { .irq = -1 }
1124 };
1125
1126 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1127 { .role = "dbclk", .clk = "gpio1_dbclk" },
1128 };
1129
1130 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1131 .name = "gpio1",
1132 .class = &omap44xx_gpio_hwmod_class,
1133 .clkdm_name = "l4_wkup_clkdm",
1134 .mpu_irqs = omap44xx_gpio1_irqs,
1135 .main_clk = "gpio1_ick",
1136 .prcm = {
1137 .omap4 = {
1138 .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1139 .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1140 .modulemode = MODULEMODE_HWCTRL,
1141 },
1142 },
1143 .opt_clks = gpio1_opt_clks,
1144 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1145 .dev_attr = &gpio_dev_attr,
1146 };
1147
1148 /* gpio2 */
1149 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1150 { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1151 { .irq = -1 }
1152 };
1153
1154 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1155 { .role = "dbclk", .clk = "gpio2_dbclk" },
1156 };
1157
1158 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1159 .name = "gpio2",
1160 .class = &omap44xx_gpio_hwmod_class,
1161 .clkdm_name = "l4_per_clkdm",
1162 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1163 .mpu_irqs = omap44xx_gpio2_irqs,
1164 .main_clk = "gpio2_ick",
1165 .prcm = {
1166 .omap4 = {
1167 .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1168 .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1169 .modulemode = MODULEMODE_HWCTRL,
1170 },
1171 },
1172 .opt_clks = gpio2_opt_clks,
1173 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1174 .dev_attr = &gpio_dev_attr,
1175 };
1176
1177 /* gpio3 */
1178 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1179 { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1180 { .irq = -1 }
1181 };
1182
1183 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1184 { .role = "dbclk", .clk = "gpio3_dbclk" },
1185 };
1186
1187 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1188 .name = "gpio3",
1189 .class = &omap44xx_gpio_hwmod_class,
1190 .clkdm_name = "l4_per_clkdm",
1191 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1192 .mpu_irqs = omap44xx_gpio3_irqs,
1193 .main_clk = "gpio3_ick",
1194 .prcm = {
1195 .omap4 = {
1196 .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1197 .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1198 .modulemode = MODULEMODE_HWCTRL,
1199 },
1200 },
1201 .opt_clks = gpio3_opt_clks,
1202 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1203 .dev_attr = &gpio_dev_attr,
1204 };
1205
1206 /* gpio4 */
1207 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1208 { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1209 { .irq = -1 }
1210 };
1211
1212 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1213 { .role = "dbclk", .clk = "gpio4_dbclk" },
1214 };
1215
1216 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1217 .name = "gpio4",
1218 .class = &omap44xx_gpio_hwmod_class,
1219 .clkdm_name = "l4_per_clkdm",
1220 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1221 .mpu_irqs = omap44xx_gpio4_irqs,
1222 .main_clk = "gpio4_ick",
1223 .prcm = {
1224 .omap4 = {
1225 .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1226 .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1227 .modulemode = MODULEMODE_HWCTRL,
1228 },
1229 },
1230 .opt_clks = gpio4_opt_clks,
1231 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1232 .dev_attr = &gpio_dev_attr,
1233 };
1234
1235 /* gpio5 */
1236 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1237 { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1238 { .irq = -1 }
1239 };
1240
1241 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1242 { .role = "dbclk", .clk = "gpio5_dbclk" },
1243 };
1244
1245 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1246 .name = "gpio5",
1247 .class = &omap44xx_gpio_hwmod_class,
1248 .clkdm_name = "l4_per_clkdm",
1249 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1250 .mpu_irqs = omap44xx_gpio5_irqs,
1251 .main_clk = "gpio5_ick",
1252 .prcm = {
1253 .omap4 = {
1254 .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1255 .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1256 .modulemode = MODULEMODE_HWCTRL,
1257 },
1258 },
1259 .opt_clks = gpio5_opt_clks,
1260 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1261 .dev_attr = &gpio_dev_attr,
1262 };
1263
1264 /* gpio6 */
1265 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1266 { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1267 { .irq = -1 }
1268 };
1269
1270 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1271 { .role = "dbclk", .clk = "gpio6_dbclk" },
1272 };
1273
1274 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1275 .name = "gpio6",
1276 .class = &omap44xx_gpio_hwmod_class,
1277 .clkdm_name = "l4_per_clkdm",
1278 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1279 .mpu_irqs = omap44xx_gpio6_irqs,
1280 .main_clk = "gpio6_ick",
1281 .prcm = {
1282 .omap4 = {
1283 .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1284 .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1285 .modulemode = MODULEMODE_HWCTRL,
1286 },
1287 },
1288 .opt_clks = gpio6_opt_clks,
1289 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1290 .dev_attr = &gpio_dev_attr,
1291 };
1292
1293 /*
1294 * 'gpmc' class
1295 * general purpose memory controller
1296 */
1297
1298 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1299 .rev_offs = 0x0000,
1300 .sysc_offs = 0x0010,
1301 .syss_offs = 0x0014,
1302 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1303 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1304 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1305 .sysc_fields = &omap_hwmod_sysc_type1,
1306 };
1307
1308 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1309 .name = "gpmc",
1310 .sysc = &omap44xx_gpmc_sysc,
1311 };
1312
1313 /* gpmc */
1314 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
1315 { .irq = 20 + OMAP44XX_IRQ_GIC_START },
1316 { .irq = -1 }
1317 };
1318
1319 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
1320 { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
1321 { .dma_req = -1 }
1322 };
1323
1324 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1325 .name = "gpmc",
1326 .class = &omap44xx_gpmc_hwmod_class,
1327 .clkdm_name = "l3_2_clkdm",
1328 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1329 .mpu_irqs = omap44xx_gpmc_irqs,
1330 .sdma_reqs = omap44xx_gpmc_sdma_reqs,
1331 .prcm = {
1332 .omap4 = {
1333 .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1334 .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1335 .modulemode = MODULEMODE_HWCTRL,
1336 },
1337 },
1338 };
1339
1340 /*
1341 * 'gpu' class
1342 * 2d/3d graphics accelerator
1343 */
1344
1345 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1346 .rev_offs = 0x1fc00,
1347 .sysc_offs = 0x1fc10,
1348 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1349 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1350 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1351 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1352 .sysc_fields = &omap_hwmod_sysc_type2,
1353 };
1354
1355 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1356 .name = "gpu",
1357 .sysc = &omap44xx_gpu_sysc,
1358 };
1359
1360 /* gpu */
1361 static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
1362 { .irq = 21 + OMAP44XX_IRQ_GIC_START },
1363 { .irq = -1 }
1364 };
1365
1366 static struct omap_hwmod omap44xx_gpu_hwmod = {
1367 .name = "gpu",
1368 .class = &omap44xx_gpu_hwmod_class,
1369 .clkdm_name = "l3_gfx_clkdm",
1370 .mpu_irqs = omap44xx_gpu_irqs,
1371 .main_clk = "gpu_fck",
1372 .prcm = {
1373 .omap4 = {
1374 .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1375 .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1376 .modulemode = MODULEMODE_SWCTRL,
1377 },
1378 },
1379 };
1380
1381 /*
1382 * 'hdq1w' class
1383 * hdq / 1-wire serial interface controller
1384 */
1385
1386 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1387 .rev_offs = 0x0000,
1388 .sysc_offs = 0x0014,
1389 .syss_offs = 0x0018,
1390 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1391 SYSS_HAS_RESET_STATUS),
1392 .sysc_fields = &omap_hwmod_sysc_type1,
1393 };
1394
1395 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1396 .name = "hdq1w",
1397 .sysc = &omap44xx_hdq1w_sysc,
1398 };
1399
1400 /* hdq1w */
1401 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
1402 { .irq = 58 + OMAP44XX_IRQ_GIC_START },
1403 { .irq = -1 }
1404 };
1405
1406 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1407 .name = "hdq1w",
1408 .class = &omap44xx_hdq1w_hwmod_class,
1409 .clkdm_name = "l4_per_clkdm",
1410 .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */
1411 .mpu_irqs = omap44xx_hdq1w_irqs,
1412 .main_clk = "hdq1w_fck",
1413 .prcm = {
1414 .omap4 = {
1415 .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1416 .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1417 .modulemode = MODULEMODE_SWCTRL,
1418 },
1419 },
1420 };
1421
1422 /*
1423 * 'hsi' class
1424 * mipi high-speed synchronous serial interface (multichannel and full-duplex
1425 * serial if)
1426 */
1427
1428 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1429 .rev_offs = 0x0000,
1430 .sysc_offs = 0x0010,
1431 .syss_offs = 0x0014,
1432 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1433 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1434 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1435 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1436 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1437 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1438 .sysc_fields = &omap_hwmod_sysc_type1,
1439 };
1440
1441 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1442 .name = "hsi",
1443 .sysc = &omap44xx_hsi_sysc,
1444 };
1445
1446 /* hsi */
1447 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
1448 { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
1449 { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
1450 { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
1451 { .irq = -1 }
1452 };
1453
1454 static struct omap_hwmod omap44xx_hsi_hwmod = {
1455 .name = "hsi",
1456 .class = &omap44xx_hsi_hwmod_class,
1457 .clkdm_name = "l3_init_clkdm",
1458 .mpu_irqs = omap44xx_hsi_irqs,
1459 .main_clk = "hsi_fck",
1460 .prcm = {
1461 .omap4 = {
1462 .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1463 .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1464 .modulemode = MODULEMODE_HWCTRL,
1465 },
1466 },
1467 };
1468
1469 /*
1470 * 'i2c' class
1471 * multimaster high-speed i2c controller
1472 */
1473
1474 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1475 .sysc_offs = 0x0010,
1476 .syss_offs = 0x0090,
1477 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1478 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1479 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1480 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1481 SIDLE_SMART_WKUP),
1482 .clockact = CLOCKACT_TEST_ICLK,
1483 .sysc_fields = &omap_hwmod_sysc_type1,
1484 };
1485
1486 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1487 .name = "i2c",
1488 .sysc = &omap44xx_i2c_sysc,
1489 .rev = OMAP_I2C_IP_VERSION_2,
1490 .reset = &omap_i2c_reset,
1491 };
1492
1493 static struct omap_i2c_dev_attr i2c_dev_attr = {
1494 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
1495 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
1496 };
1497
1498 /* i2c1 */
1499 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1500 { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1501 { .irq = -1 }
1502 };
1503
1504 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1505 { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1506 { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1507 { .dma_req = -1 }
1508 };
1509
1510 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1511 .name = "i2c1",
1512 .class = &omap44xx_i2c_hwmod_class,
1513 .clkdm_name = "l4_per_clkdm",
1514 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1515 .mpu_irqs = omap44xx_i2c1_irqs,
1516 .sdma_reqs = omap44xx_i2c1_sdma_reqs,
1517 .main_clk = "i2c1_fck",
1518 .prcm = {
1519 .omap4 = {
1520 .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1521 .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1522 .modulemode = MODULEMODE_SWCTRL,
1523 },
1524 },
1525 .dev_attr = &i2c_dev_attr,
1526 };
1527
1528 /* i2c2 */
1529 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1530 { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1531 { .irq = -1 }
1532 };
1533
1534 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1535 { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1536 { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1537 { .dma_req = -1 }
1538 };
1539
1540 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1541 .name = "i2c2",
1542 .class = &omap44xx_i2c_hwmod_class,
1543 .clkdm_name = "l4_per_clkdm",
1544 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1545 .mpu_irqs = omap44xx_i2c2_irqs,
1546 .sdma_reqs = omap44xx_i2c2_sdma_reqs,
1547 .main_clk = "i2c2_fck",
1548 .prcm = {
1549 .omap4 = {
1550 .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1551 .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1552 .modulemode = MODULEMODE_SWCTRL,
1553 },
1554 },
1555 .dev_attr = &i2c_dev_attr,
1556 };
1557
1558 /* i2c3 */
1559 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1560 { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1561 { .irq = -1 }
1562 };
1563
1564 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1565 { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1566 { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1567 { .dma_req = -1 }
1568 };
1569
1570 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1571 .name = "i2c3",
1572 .class = &omap44xx_i2c_hwmod_class,
1573 .clkdm_name = "l4_per_clkdm",
1574 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1575 .mpu_irqs = omap44xx_i2c3_irqs,
1576 .sdma_reqs = omap44xx_i2c3_sdma_reqs,
1577 .main_clk = "i2c3_fck",
1578 .prcm = {
1579 .omap4 = {
1580 .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1581 .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1582 .modulemode = MODULEMODE_SWCTRL,
1583 },
1584 },
1585 .dev_attr = &i2c_dev_attr,
1586 };
1587
1588 /* i2c4 */
1589 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1590 { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1591 { .irq = -1 }
1592 };
1593
1594 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1595 { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1596 { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1597 { .dma_req = -1 }
1598 };
1599
1600 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1601 .name = "i2c4",
1602 .class = &omap44xx_i2c_hwmod_class,
1603 .clkdm_name = "l4_per_clkdm",
1604 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1605 .mpu_irqs = omap44xx_i2c4_irqs,
1606 .sdma_reqs = omap44xx_i2c4_sdma_reqs,
1607 .main_clk = "i2c4_fck",
1608 .prcm = {
1609 .omap4 = {
1610 .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1611 .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1612 .modulemode = MODULEMODE_SWCTRL,
1613 },
1614 },
1615 .dev_attr = &i2c_dev_attr,
1616 };
1617
1618 /*
1619 * 'ipu' class
1620 * imaging processor unit
1621 */
1622
1623 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1624 .name = "ipu",
1625 };
1626
1627 /* ipu */
1628 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
1629 { .irq = 100 + OMAP44XX_IRQ_GIC_START },
1630 { .irq = -1 }
1631 };
1632
1633 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1634 { .name = "cpu0", .rst_shift = 0 },
1635 { .name = "cpu1", .rst_shift = 1 },
1636 { .name = "mmu_cache", .rst_shift = 2 },
1637 };
1638
1639 static struct omap_hwmod omap44xx_ipu_hwmod = {
1640 .name = "ipu",
1641 .class = &omap44xx_ipu_hwmod_class,
1642 .clkdm_name = "ducati_clkdm",
1643 .mpu_irqs = omap44xx_ipu_irqs,
1644 .rst_lines = omap44xx_ipu_resets,
1645 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
1646 .main_clk = "ipu_fck",
1647 .prcm = {
1648 .omap4 = {
1649 .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1650 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1651 .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1652 .modulemode = MODULEMODE_HWCTRL,
1653 },
1654 },
1655 };
1656
1657 /*
1658 * 'iss' class
1659 * external images sensor pixel data processor
1660 */
1661
1662 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1663 .rev_offs = 0x0000,
1664 .sysc_offs = 0x0010,
1665 /*
1666 * ISS needs 100 OCP clk cycles delay after a softreset before
1667 * accessing sysconfig again.
1668 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1669 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1670 *
1671 * TODO: Indicate errata when available.
1672 */
1673 .srst_udelay = 2,
1674 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1675 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1676 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1677 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1678 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1679 .sysc_fields = &omap_hwmod_sysc_type2,
1680 };
1681
1682 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1683 .name = "iss",
1684 .sysc = &omap44xx_iss_sysc,
1685 };
1686
1687 /* iss */
1688 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
1689 { .irq = 24 + OMAP44XX_IRQ_GIC_START },
1690 { .irq = -1 }
1691 };
1692
1693 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
1694 { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
1695 { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
1696 { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
1697 { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
1698 { .dma_req = -1 }
1699 };
1700
1701 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1702 { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1703 };
1704
1705 static struct omap_hwmod omap44xx_iss_hwmod = {
1706 .name = "iss",
1707 .class = &omap44xx_iss_hwmod_class,
1708 .clkdm_name = "iss_clkdm",
1709 .mpu_irqs = omap44xx_iss_irqs,
1710 .sdma_reqs = omap44xx_iss_sdma_reqs,
1711 .main_clk = "iss_fck",
1712 .prcm = {
1713 .omap4 = {
1714 .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1715 .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1716 .modulemode = MODULEMODE_SWCTRL,
1717 },
1718 },
1719 .opt_clks = iss_opt_clks,
1720 .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
1721 };
1722
1723 /*
1724 * 'iva' class
1725 * multi-standard video encoder/decoder hardware accelerator
1726 */
1727
1728 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1729 .name = "iva",
1730 };
1731
1732 /* iva */
1733 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1734 { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1735 { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1736 { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1737 { .irq = -1 }
1738 };
1739
1740 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1741 { .name = "seq0", .rst_shift = 0 },
1742 { .name = "seq1", .rst_shift = 1 },
1743 { .name = "logic", .rst_shift = 2 },
1744 };
1745
1746 static struct omap_hwmod omap44xx_iva_hwmod = {
1747 .name = "iva",
1748 .class = &omap44xx_iva_hwmod_class,
1749 .clkdm_name = "ivahd_clkdm",
1750 .mpu_irqs = omap44xx_iva_irqs,
1751 .rst_lines = omap44xx_iva_resets,
1752 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
1753 .main_clk = "iva_fck",
1754 .prcm = {
1755 .omap4 = {
1756 .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1757 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1758 .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1759 .modulemode = MODULEMODE_HWCTRL,
1760 },
1761 },
1762 };
1763
1764 /*
1765 * 'kbd' class
1766 * keyboard controller
1767 */
1768
1769 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1770 .rev_offs = 0x0000,
1771 .sysc_offs = 0x0010,
1772 .syss_offs = 0x0014,
1773 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1774 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1775 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1776 SYSS_HAS_RESET_STATUS),
1777 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1778 .sysc_fields = &omap_hwmod_sysc_type1,
1779 };
1780
1781 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1782 .name = "kbd",
1783 .sysc = &omap44xx_kbd_sysc,
1784 };
1785
1786 /* kbd */
1787 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
1788 { .irq = 120 + OMAP44XX_IRQ_GIC_START },
1789 { .irq = -1 }
1790 };
1791
1792 static struct omap_hwmod omap44xx_kbd_hwmod = {
1793 .name = "kbd",
1794 .class = &omap44xx_kbd_hwmod_class,
1795 .clkdm_name = "l4_wkup_clkdm",
1796 .mpu_irqs = omap44xx_kbd_irqs,
1797 .main_clk = "kbd_fck",
1798 .prcm = {
1799 .omap4 = {
1800 .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1801 .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1802 .modulemode = MODULEMODE_SWCTRL,
1803 },
1804 },
1805 };
1806
1807 /*
1808 * 'mailbox' class
1809 * mailbox module allowing communication between the on-chip processors using a
1810 * queued mailbox-interrupt mechanism.
1811 */
1812
1813 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1814 .rev_offs = 0x0000,
1815 .sysc_offs = 0x0010,
1816 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1817 SYSC_HAS_SOFTRESET),
1818 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1819 .sysc_fields = &omap_hwmod_sysc_type2,
1820 };
1821
1822 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1823 .name = "mailbox",
1824 .sysc = &omap44xx_mailbox_sysc,
1825 };
1826
1827 /* mailbox */
1828 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
1829 { .irq = 26 + OMAP44XX_IRQ_GIC_START },
1830 { .irq = -1 }
1831 };
1832
1833 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1834 .name = "mailbox",
1835 .class = &omap44xx_mailbox_hwmod_class,
1836 .clkdm_name = "l4_cfg_clkdm",
1837 .mpu_irqs = omap44xx_mailbox_irqs,
1838 .prcm = {
1839 .omap4 = {
1840 .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1841 .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1842 },
1843 },
1844 };
1845
1846 /*
1847 * 'mcasp' class
1848 * multi-channel audio serial port controller
1849 */
1850
1851 /* The IP is not compliant to type1 / type2 scheme */
1852 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1853 .sidle_shift = 0,
1854 };
1855
1856 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1857 .sysc_offs = 0x0004,
1858 .sysc_flags = SYSC_HAS_SIDLEMODE,
1859 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1860 SIDLE_SMART_WKUP),
1861 .sysc_fields = &omap_hwmod_sysc_type_mcasp,
1862 };
1863
1864 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1865 .name = "mcasp",
1866 .sysc = &omap44xx_mcasp_sysc,
1867 };
1868
1869 /* mcasp */
1870 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
1871 { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
1872 { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
1873 { .irq = -1 }
1874 };
1875
1876 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
1877 { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
1878 { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
1879 { .dma_req = -1 }
1880 };
1881
1882 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1883 .name = "mcasp",
1884 .class = &omap44xx_mcasp_hwmod_class,
1885 .clkdm_name = "abe_clkdm",
1886 .mpu_irqs = omap44xx_mcasp_irqs,
1887 .sdma_reqs = omap44xx_mcasp_sdma_reqs,
1888 .main_clk = "mcasp_fck",
1889 .prcm = {
1890 .omap4 = {
1891 .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1892 .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1893 .modulemode = MODULEMODE_SWCTRL,
1894 },
1895 },
1896 };
1897
1898 /*
1899 * 'mcbsp' class
1900 * multi channel buffered serial port controller
1901 */
1902
1903 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1904 .sysc_offs = 0x008c,
1905 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1906 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1907 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1908 .sysc_fields = &omap_hwmod_sysc_type1,
1909 };
1910
1911 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1912 .name = "mcbsp",
1913 .sysc = &omap44xx_mcbsp_sysc,
1914 .rev = MCBSP_CONFIG_TYPE4,
1915 };
1916
1917 /* mcbsp1 */
1918 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
1919 { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
1920 { .irq = -1 }
1921 };
1922
1923 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
1924 { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
1925 { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
1926 { .dma_req = -1 }
1927 };
1928
1929 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1930 { .role = "pad_fck", .clk = "pad_clks_ck" },
1931 { .role = "prcm_clk", .clk = "mcbsp1_sync_mux_ck" },
1932 };
1933
1934 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1935 .name = "mcbsp1",
1936 .class = &omap44xx_mcbsp_hwmod_class,
1937 .clkdm_name = "abe_clkdm",
1938 .mpu_irqs = omap44xx_mcbsp1_irqs,
1939 .sdma_reqs = omap44xx_mcbsp1_sdma_reqs,
1940 .main_clk = "mcbsp1_fck",
1941 .prcm = {
1942 .omap4 = {
1943 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1944 .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1945 .modulemode = MODULEMODE_SWCTRL,
1946 },
1947 },
1948 .opt_clks = mcbsp1_opt_clks,
1949 .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
1950 };
1951
1952 /* mcbsp2 */
1953 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
1954 { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
1955 { .irq = -1 }
1956 };
1957
1958 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
1959 { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
1960 { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
1961 { .dma_req = -1 }
1962 };
1963
1964 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1965 { .role = "pad_fck", .clk = "pad_clks_ck" },
1966 { .role = "prcm_clk", .clk = "mcbsp2_sync_mux_ck" },
1967 };
1968
1969 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
1970 .name = "mcbsp2",
1971 .class = &omap44xx_mcbsp_hwmod_class,
1972 .clkdm_name = "abe_clkdm",
1973 .mpu_irqs = omap44xx_mcbsp2_irqs,
1974 .sdma_reqs = omap44xx_mcbsp2_sdma_reqs,
1975 .main_clk = "mcbsp2_fck",
1976 .prcm = {
1977 .omap4 = {
1978 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
1979 .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
1980 .modulemode = MODULEMODE_SWCTRL,
1981 },
1982 },
1983 .opt_clks = mcbsp2_opt_clks,
1984 .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
1985 };
1986
1987 /* mcbsp3 */
1988 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
1989 { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
1990 { .irq = -1 }
1991 };
1992
1993 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
1994 { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
1995 { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
1996 { .dma_req = -1 }
1997 };
1998
1999 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
2000 { .role = "pad_fck", .clk = "pad_clks_ck" },
2001 { .role = "prcm_clk", .clk = "mcbsp3_sync_mux_ck" },
2002 };
2003
2004 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2005 .name = "mcbsp3",
2006 .class = &omap44xx_mcbsp_hwmod_class,
2007 .clkdm_name = "abe_clkdm",
2008 .mpu_irqs = omap44xx_mcbsp3_irqs,
2009 .sdma_reqs = omap44xx_mcbsp3_sdma_reqs,
2010 .main_clk = "mcbsp3_fck",
2011 .prcm = {
2012 .omap4 = {
2013 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
2014 .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2015 .modulemode = MODULEMODE_SWCTRL,
2016 },
2017 },
2018 .opt_clks = mcbsp3_opt_clks,
2019 .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
2020 };
2021
2022 /* mcbsp4 */
2023 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2024 { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
2025 { .irq = -1 }
2026 };
2027
2028 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2029 { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2030 { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2031 { .dma_req = -1 }
2032 };
2033
2034 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2035 { .role = "pad_fck", .clk = "pad_clks_ck" },
2036 { .role = "prcm_clk", .clk = "mcbsp4_sync_mux_ck" },
2037 };
2038
2039 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2040 .name = "mcbsp4",
2041 .class = &omap44xx_mcbsp_hwmod_class,
2042 .clkdm_name = "l4_per_clkdm",
2043 .mpu_irqs = omap44xx_mcbsp4_irqs,
2044 .sdma_reqs = omap44xx_mcbsp4_sdma_reqs,
2045 .main_clk = "mcbsp4_fck",
2046 .prcm = {
2047 .omap4 = {
2048 .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
2049 .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
2050 .modulemode = MODULEMODE_SWCTRL,
2051 },
2052 },
2053 .opt_clks = mcbsp4_opt_clks,
2054 .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks),
2055 };
2056
2057 /*
2058 * 'mcpdm' class
2059 * multi channel pdm controller (proprietary interface with phoenix power
2060 * ic)
2061 */
2062
2063 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
2064 .rev_offs = 0x0000,
2065 .sysc_offs = 0x0010,
2066 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2067 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2068 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2069 SIDLE_SMART_WKUP),
2070 .sysc_fields = &omap_hwmod_sysc_type2,
2071 };
2072
2073 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
2074 .name = "mcpdm",
2075 .sysc = &omap44xx_mcpdm_sysc,
2076 };
2077
2078 /* mcpdm */
2079 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
2080 { .irq = 112 + OMAP44XX_IRQ_GIC_START },
2081 { .irq = -1 }
2082 };
2083
2084 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
2085 { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
2086 { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
2087 { .dma_req = -1 }
2088 };
2089
2090 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2091 .name = "mcpdm",
2092 .class = &omap44xx_mcpdm_hwmod_class,
2093 .clkdm_name = "abe_clkdm",
2094 .mpu_irqs = omap44xx_mcpdm_irqs,
2095 .sdma_reqs = omap44xx_mcpdm_sdma_reqs,
2096 .main_clk = "mcpdm_fck",
2097 .prcm = {
2098 .omap4 = {
2099 .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
2100 .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
2101 .modulemode = MODULEMODE_SWCTRL,
2102 },
2103 },
2104 };
2105
2106 /*
2107 * 'mcspi' class
2108 * multichannel serial port interface (mcspi) / master/slave synchronous serial
2109 * bus
2110 */
2111
2112 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
2113 .rev_offs = 0x0000,
2114 .sysc_offs = 0x0010,
2115 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2116 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2117 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2118 SIDLE_SMART_WKUP),
2119 .sysc_fields = &omap_hwmod_sysc_type2,
2120 };
2121
2122 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2123 .name = "mcspi",
2124 .sysc = &omap44xx_mcspi_sysc,
2125 .rev = OMAP4_MCSPI_REV,
2126 };
2127
2128 /* mcspi1 */
2129 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2130 { .irq = 65 + OMAP44XX_IRQ_GIC_START },
2131 { .irq = -1 }
2132 };
2133
2134 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2135 { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2136 { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
2137 { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
2138 { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
2139 { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
2140 { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
2141 { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
2142 { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
2143 { .dma_req = -1 }
2144 };
2145
2146 /* mcspi1 dev_attr */
2147 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2148 .num_chipselect = 4,
2149 };
2150
2151 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2152 .name = "mcspi1",
2153 .class = &omap44xx_mcspi_hwmod_class,
2154 .clkdm_name = "l4_per_clkdm",
2155 .mpu_irqs = omap44xx_mcspi1_irqs,
2156 .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
2157 .main_clk = "mcspi1_fck",
2158 .prcm = {
2159 .omap4 = {
2160 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2161 .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2162 .modulemode = MODULEMODE_SWCTRL,
2163 },
2164 },
2165 .dev_attr = &mcspi1_dev_attr,
2166 };
2167
2168 /* mcspi2 */
2169 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2170 { .irq = 66 + OMAP44XX_IRQ_GIC_START },
2171 { .irq = -1 }
2172 };
2173
2174 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2175 { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2176 { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
2177 { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
2178 { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
2179 { .dma_req = -1 }
2180 };
2181
2182 /* mcspi2 dev_attr */
2183 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2184 .num_chipselect = 2,
2185 };
2186
2187 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2188 .name = "mcspi2",
2189 .class = &omap44xx_mcspi_hwmod_class,
2190 .clkdm_name = "l4_per_clkdm",
2191 .mpu_irqs = omap44xx_mcspi2_irqs,
2192 .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
2193 .main_clk = "mcspi2_fck",
2194 .prcm = {
2195 .omap4 = {
2196 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2197 .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2198 .modulemode = MODULEMODE_SWCTRL,
2199 },
2200 },
2201 .dev_attr = &mcspi2_dev_attr,
2202 };
2203
2204 /* mcspi3 */
2205 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2206 { .irq = 91 + OMAP44XX_IRQ_GIC_START },
2207 { .irq = -1 }
2208 };
2209
2210 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2211 { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2212 { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2213 { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2214 { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2215 { .dma_req = -1 }
2216 };
2217
2218 /* mcspi3 dev_attr */
2219 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2220 .num_chipselect = 2,
2221 };
2222
2223 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2224 .name = "mcspi3",
2225 .class = &omap44xx_mcspi_hwmod_class,
2226 .clkdm_name = "l4_per_clkdm",
2227 .mpu_irqs = omap44xx_mcspi3_irqs,
2228 .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
2229 .main_clk = "mcspi3_fck",
2230 .prcm = {
2231 .omap4 = {
2232 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2233 .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2234 .modulemode = MODULEMODE_SWCTRL,
2235 },
2236 },
2237 .dev_attr = &mcspi3_dev_attr,
2238 };
2239
2240 /* mcspi4 */
2241 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
2242 { .irq = 48 + OMAP44XX_IRQ_GIC_START },
2243 { .irq = -1 }
2244 };
2245
2246 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2247 { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2248 { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
2249 { .dma_req = -1 }
2250 };
2251
2252 /* mcspi4 dev_attr */
2253 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2254 .num_chipselect = 1,
2255 };
2256
2257 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2258 .name = "mcspi4",
2259 .class = &omap44xx_mcspi_hwmod_class,
2260 .clkdm_name = "l4_per_clkdm",
2261 .mpu_irqs = omap44xx_mcspi4_irqs,
2262 .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
2263 .main_clk = "mcspi4_fck",
2264 .prcm = {
2265 .omap4 = {
2266 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2267 .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2268 .modulemode = MODULEMODE_SWCTRL,
2269 },
2270 },
2271 .dev_attr = &mcspi4_dev_attr,
2272 };
2273
2274 /*
2275 * 'mmc' class
2276 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2277 */
2278
2279 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
2280 .rev_offs = 0x0000,
2281 .sysc_offs = 0x0010,
2282 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2283 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2284 SYSC_HAS_SOFTRESET),
2285 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2286 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2287 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2288 .sysc_fields = &omap_hwmod_sysc_type2,
2289 };
2290
2291 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
2292 .name = "mmc",
2293 .sysc = &omap44xx_mmc_sysc,
2294 };
2295
2296 /* mmc1 */
2297 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
2298 { .irq = 83 + OMAP44XX_IRQ_GIC_START },
2299 { .irq = -1 }
2300 };
2301
2302 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
2303 { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
2304 { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
2305 { .dma_req = -1 }
2306 };
2307
2308 /* mmc1 dev_attr */
2309 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2310 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2311 };
2312
2313 static struct omap_hwmod omap44xx_mmc1_hwmod = {
2314 .name = "mmc1",
2315 .class = &omap44xx_mmc_hwmod_class,
2316 .clkdm_name = "l3_init_clkdm",
2317 .mpu_irqs = omap44xx_mmc1_irqs,
2318 .sdma_reqs = omap44xx_mmc1_sdma_reqs,
2319 .main_clk = "mmc1_fck",
2320 .prcm = {
2321 .omap4 = {
2322 .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2323 .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2324 .modulemode = MODULEMODE_SWCTRL,
2325 },
2326 },
2327 .dev_attr = &mmc1_dev_attr,
2328 };
2329
2330 /* mmc2 */
2331 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
2332 { .irq = 86 + OMAP44XX_IRQ_GIC_START },
2333 { .irq = -1 }
2334 };
2335
2336 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
2337 { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
2338 { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
2339 { .dma_req = -1 }
2340 };
2341
2342 static struct omap_hwmod omap44xx_mmc2_hwmod = {
2343 .name = "mmc2",
2344 .class = &omap44xx_mmc_hwmod_class,
2345 .clkdm_name = "l3_init_clkdm",
2346 .mpu_irqs = omap44xx_mmc2_irqs,
2347 .sdma_reqs = omap44xx_mmc2_sdma_reqs,
2348 .main_clk = "mmc2_fck",
2349 .prcm = {
2350 .omap4 = {
2351 .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2352 .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2353 .modulemode = MODULEMODE_SWCTRL,
2354 },
2355 },
2356 };
2357
2358 /* mmc3 */
2359 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
2360 { .irq = 94 + OMAP44XX_IRQ_GIC_START },
2361 { .irq = -1 }
2362 };
2363
2364 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2365 { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2366 { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2367 { .dma_req = -1 }
2368 };
2369
2370 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2371 .name = "mmc3",
2372 .class = &omap44xx_mmc_hwmod_class,
2373 .clkdm_name = "l4_per_clkdm",
2374 .mpu_irqs = omap44xx_mmc3_irqs,
2375 .sdma_reqs = omap44xx_mmc3_sdma_reqs,
2376 .main_clk = "mmc3_fck",
2377 .prcm = {
2378 .omap4 = {
2379 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2380 .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2381 .modulemode = MODULEMODE_SWCTRL,
2382 },
2383 },
2384 };
2385
2386 /* mmc4 */
2387 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
2388 { .irq = 96 + OMAP44XX_IRQ_GIC_START },
2389 { .irq = -1 }
2390 };
2391
2392 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2393 { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2394 { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2395 { .dma_req = -1 }
2396 };
2397
2398 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2399 .name = "mmc4",
2400 .class = &omap44xx_mmc_hwmod_class,
2401 .clkdm_name = "l4_per_clkdm",
2402 .mpu_irqs = omap44xx_mmc4_irqs,
2403 .sdma_reqs = omap44xx_mmc4_sdma_reqs,
2404 .main_clk = "mmc4_fck",
2405 .prcm = {
2406 .omap4 = {
2407 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2408 .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2409 .modulemode = MODULEMODE_SWCTRL,
2410 },
2411 },
2412 };
2413
2414 /* mmc5 */
2415 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
2416 { .irq = 59 + OMAP44XX_IRQ_GIC_START },
2417 { .irq = -1 }
2418 };
2419
2420 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2421 { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2422 { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2423 { .dma_req = -1 }
2424 };
2425
2426 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2427 .name = "mmc5",
2428 .class = &omap44xx_mmc_hwmod_class,
2429 .clkdm_name = "l4_per_clkdm",
2430 .mpu_irqs = omap44xx_mmc5_irqs,
2431 .sdma_reqs = omap44xx_mmc5_sdma_reqs,
2432 .main_clk = "mmc5_fck",
2433 .prcm = {
2434 .omap4 = {
2435 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2436 .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2437 .modulemode = MODULEMODE_SWCTRL,
2438 },
2439 },
2440 };
2441
2442 /*
2443 * 'mpu' class
2444 * mpu sub-system
2445 */
2446
2447 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2448 .name = "mpu",
2449 };
2450
2451 /* mpu */
2452 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
2453 { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
2454 { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
2455 { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
2456 { .irq = -1 }
2457 };
2458
2459 static struct omap_hwmod omap44xx_mpu_hwmod = {
2460 .name = "mpu",
2461 .class = &omap44xx_mpu_hwmod_class,
2462 .clkdm_name = "mpuss_clkdm",
2463 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2464 .mpu_irqs = omap44xx_mpu_irqs,
2465 .main_clk = "dpll_mpu_m2_ck",
2466 .prcm = {
2467 .omap4 = {
2468 .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2469 .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2470 },
2471 },
2472 };
2473
2474 /*
2475 * 'ocmc_ram' class
2476 * top-level core on-chip ram
2477 */
2478
2479 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2480 .name = "ocmc_ram",
2481 };
2482
2483 /* ocmc_ram */
2484 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2485 .name = "ocmc_ram",
2486 .class = &omap44xx_ocmc_ram_hwmod_class,
2487 .clkdm_name = "l3_2_clkdm",
2488 .prcm = {
2489 .omap4 = {
2490 .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2491 .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2492 },
2493 },
2494 };
2495
2496 /*
2497 * 'ocp2scp' class
2498 * bridge to transform ocp interface protocol to scp (serial control port)
2499 * protocol
2500 */
2501
2502 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2503 .name = "ocp2scp",
2504 };
2505
2506 /* ocp2scp_usb_phy */
2507 static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = {
2508 { .role = "phy_48m", .clk = "ocp2scp_usb_phy_phy_48m" },
2509 };
2510
2511 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2512 .name = "ocp2scp_usb_phy",
2513 .class = &omap44xx_ocp2scp_hwmod_class,
2514 .clkdm_name = "l3_init_clkdm",
2515 .prcm = {
2516 .omap4 = {
2517 .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2518 .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2519 .modulemode = MODULEMODE_HWCTRL,
2520 },
2521 },
2522 .opt_clks = ocp2scp_usb_phy_opt_clks,
2523 .opt_clks_cnt = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks),
2524 };
2525
2526 /*
2527 * 'prcm' class
2528 * power and reset manager (part of the prcm infrastructure) + clock manager 2
2529 * + clock manager 1 (in always on power domain) + local prm in mpu
2530 */
2531
2532 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2533 .name = "prcm",
2534 };
2535
2536 /* prcm_mpu */
2537 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2538 .name = "prcm_mpu",
2539 .class = &omap44xx_prcm_hwmod_class,
2540 .clkdm_name = "l4_wkup_clkdm",
2541 };
2542
2543 /* cm_core_aon */
2544 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2545 .name = "cm_core_aon",
2546 .class = &omap44xx_prcm_hwmod_class,
2547 };
2548
2549 /* cm_core */
2550 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2551 .name = "cm_core",
2552 .class = &omap44xx_prcm_hwmod_class,
2553 };
2554
2555 /* prm */
2556 static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
2557 { .irq = 11 + OMAP44XX_IRQ_GIC_START },
2558 { .irq = -1 }
2559 };
2560
2561 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2562 { .name = "rst_global_warm_sw", .rst_shift = 0 },
2563 { .name = "rst_global_cold_sw", .rst_shift = 1 },
2564 };
2565
2566 static struct omap_hwmod omap44xx_prm_hwmod = {
2567 .name = "prm",
2568 .class = &omap44xx_prcm_hwmod_class,
2569 .mpu_irqs = omap44xx_prm_irqs,
2570 .rst_lines = omap44xx_prm_resets,
2571 .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets),
2572 };
2573
2574 /*
2575 * 'scrm' class
2576 * system clock and reset manager
2577 */
2578
2579 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2580 .name = "scrm",
2581 };
2582
2583 /* scrm */
2584 static struct omap_hwmod omap44xx_scrm_hwmod = {
2585 .name = "scrm",
2586 .class = &omap44xx_scrm_hwmod_class,
2587 .clkdm_name = "l4_wkup_clkdm",
2588 };
2589
2590 /*
2591 * 'sl2if' class
2592 * shared level 2 memory interface
2593 */
2594
2595 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2596 .name = "sl2if",
2597 };
2598
2599 /* sl2if */
2600 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2601 .name = "sl2if",
2602 .class = &omap44xx_sl2if_hwmod_class,
2603 .clkdm_name = "ivahd_clkdm",
2604 .prcm = {
2605 .omap4 = {
2606 .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2607 .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2608 .modulemode = MODULEMODE_HWCTRL,
2609 },
2610 },
2611 };
2612
2613 /*
2614 * 'slimbus' class
2615 * bidirectional, multi-drop, multi-channel two-line serial interface between
2616 * the device and external components
2617 */
2618
2619 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2620 .rev_offs = 0x0000,
2621 .sysc_offs = 0x0010,
2622 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2623 SYSC_HAS_SOFTRESET),
2624 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2625 SIDLE_SMART_WKUP),
2626 .sysc_fields = &omap_hwmod_sysc_type2,
2627 };
2628
2629 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2630 .name = "slimbus",
2631 .sysc = &omap44xx_slimbus_sysc,
2632 };
2633
2634 /* slimbus1 */
2635 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
2636 { .irq = 97 + OMAP44XX_IRQ_GIC_START },
2637 { .irq = -1 }
2638 };
2639
2640 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
2641 { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
2642 { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
2643 { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
2644 { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
2645 { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
2646 { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
2647 { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
2648 { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
2649 { .dma_req = -1 }
2650 };
2651
2652 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2653 { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2654 { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2655 { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2656 { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2657 };
2658
2659 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2660 .name = "slimbus1",
2661 .class = &omap44xx_slimbus_hwmod_class,
2662 .clkdm_name = "abe_clkdm",
2663 .mpu_irqs = omap44xx_slimbus1_irqs,
2664 .sdma_reqs = omap44xx_slimbus1_sdma_reqs,
2665 .prcm = {
2666 .omap4 = {
2667 .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2668 .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2669 .modulemode = MODULEMODE_SWCTRL,
2670 },
2671 },
2672 .opt_clks = slimbus1_opt_clks,
2673 .opt_clks_cnt = ARRAY_SIZE(slimbus1_opt_clks),
2674 };
2675
2676 /* slimbus2 */
2677 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
2678 { .irq = 98 + OMAP44XX_IRQ_GIC_START },
2679 { .irq = -1 }
2680 };
2681
2682 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
2683 { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
2684 { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
2685 { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
2686 { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
2687 { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
2688 { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
2689 { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
2690 { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
2691 { .dma_req = -1 }
2692 };
2693
2694 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2695 { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2696 { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2697 { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2698 };
2699
2700 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2701 .name = "slimbus2",
2702 .class = &omap44xx_slimbus_hwmod_class,
2703 .clkdm_name = "l4_per_clkdm",
2704 .mpu_irqs = omap44xx_slimbus2_irqs,
2705 .sdma_reqs = omap44xx_slimbus2_sdma_reqs,
2706 .prcm = {
2707 .omap4 = {
2708 .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2709 .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2710 .modulemode = MODULEMODE_SWCTRL,
2711 },
2712 },
2713 .opt_clks = slimbus2_opt_clks,
2714 .opt_clks_cnt = ARRAY_SIZE(slimbus2_opt_clks),
2715 };
2716
2717 /*
2718 * 'smartreflex' class
2719 * smartreflex module (monitor silicon performance and outputs a measure of
2720 * performance error)
2721 */
2722
2723 /* The IP is not compliant to type1 / type2 scheme */
2724 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2725 .sidle_shift = 24,
2726 .enwkup_shift = 26,
2727 };
2728
2729 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2730 .sysc_offs = 0x0038,
2731 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2732 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2733 SIDLE_SMART_WKUP),
2734 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
2735 };
2736
2737 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2738 .name = "smartreflex",
2739 .sysc = &omap44xx_smartreflex_sysc,
2740 .rev = 2,
2741 };
2742
2743 /* smartreflex_core */
2744 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2745 .sensor_voltdm_name = "core",
2746 };
2747
2748 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
2749 { .irq = 19 + OMAP44XX_IRQ_GIC_START },
2750 { .irq = -1 }
2751 };
2752
2753 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2754 .name = "smartreflex_core",
2755 .class = &omap44xx_smartreflex_hwmod_class,
2756 .clkdm_name = "l4_ao_clkdm",
2757 .mpu_irqs = omap44xx_smartreflex_core_irqs,
2758
2759 .main_clk = "smartreflex_core_fck",
2760 .prcm = {
2761 .omap4 = {
2762 .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2763 .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2764 .modulemode = MODULEMODE_SWCTRL,
2765 },
2766 },
2767 .dev_attr = &smartreflex_core_dev_attr,
2768 };
2769
2770 /* smartreflex_iva */
2771 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
2772 .sensor_voltdm_name = "iva",
2773 };
2774
2775 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
2776 { .irq = 102 + OMAP44XX_IRQ_GIC_START },
2777 { .irq = -1 }
2778 };
2779
2780 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2781 .name = "smartreflex_iva",
2782 .class = &omap44xx_smartreflex_hwmod_class,
2783 .clkdm_name = "l4_ao_clkdm",
2784 .mpu_irqs = omap44xx_smartreflex_iva_irqs,
2785 .main_clk = "smartreflex_iva_fck",
2786 .prcm = {
2787 .omap4 = {
2788 .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
2789 .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
2790 .modulemode = MODULEMODE_SWCTRL,
2791 },
2792 },
2793 .dev_attr = &smartreflex_iva_dev_attr,
2794 };
2795
2796 /* smartreflex_mpu */
2797 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2798 .sensor_voltdm_name = "mpu",
2799 };
2800
2801 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
2802 { .irq = 18 + OMAP44XX_IRQ_GIC_START },
2803 { .irq = -1 }
2804 };
2805
2806 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
2807 .name = "smartreflex_mpu",
2808 .class = &omap44xx_smartreflex_hwmod_class,
2809 .clkdm_name = "l4_ao_clkdm",
2810 .mpu_irqs = omap44xx_smartreflex_mpu_irqs,
2811 .main_clk = "smartreflex_mpu_fck",
2812 .prcm = {
2813 .omap4 = {
2814 .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
2815 .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
2816 .modulemode = MODULEMODE_SWCTRL,
2817 },
2818 },
2819 .dev_attr = &smartreflex_mpu_dev_attr,
2820 };
2821
2822 /*
2823 * 'spinlock' class
2824 * spinlock provides hardware assistance for synchronizing the processes
2825 * running on multiple processors
2826 */
2827
2828 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
2829 .rev_offs = 0x0000,
2830 .sysc_offs = 0x0010,
2831 .syss_offs = 0x0014,
2832 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2833 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2834 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2835 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2836 SIDLE_SMART_WKUP),
2837 .sysc_fields = &omap_hwmod_sysc_type1,
2838 };
2839
2840 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
2841 .name = "spinlock",
2842 .sysc = &omap44xx_spinlock_sysc,
2843 };
2844
2845 /* spinlock */
2846 static struct omap_hwmod omap44xx_spinlock_hwmod = {
2847 .name = "spinlock",
2848 .class = &omap44xx_spinlock_hwmod_class,
2849 .clkdm_name = "l4_cfg_clkdm",
2850 .prcm = {
2851 .omap4 = {
2852 .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
2853 .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
2854 },
2855 },
2856 };
2857
2858 /*
2859 * 'timer' class
2860 * general purpose timer module with accurate 1ms tick
2861 * This class contains several variants: ['timer_1ms', 'timer']
2862 */
2863
2864 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
2865 .rev_offs = 0x0000,
2866 .sysc_offs = 0x0010,
2867 .syss_offs = 0x0014,
2868 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2869 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2870 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2871 SYSS_HAS_RESET_STATUS),
2872 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2873 .sysc_fields = &omap_hwmod_sysc_type1,
2874 };
2875
2876 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
2877 .name = "timer",
2878 .sysc = &omap44xx_timer_1ms_sysc,
2879 };
2880
2881 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
2882 .rev_offs = 0x0000,
2883 .sysc_offs = 0x0010,
2884 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2885 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2886 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2887 SIDLE_SMART_WKUP),
2888 .sysc_fields = &omap_hwmod_sysc_type2,
2889 };
2890
2891 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
2892 .name = "timer",
2893 .sysc = &omap44xx_timer_sysc,
2894 };
2895
2896 /* always-on timers dev attribute */
2897 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
2898 .timer_capability = OMAP_TIMER_ALWON,
2899 };
2900
2901 /* pwm timers dev attribute */
2902 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
2903 .timer_capability = OMAP_TIMER_HAS_PWM,
2904 };
2905
2906 /* timer1 */
2907 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
2908 { .irq = 37 + OMAP44XX_IRQ_GIC_START },
2909 { .irq = -1 }
2910 };
2911
2912 static struct omap_hwmod omap44xx_timer1_hwmod = {
2913 .name = "timer1",
2914 .class = &omap44xx_timer_1ms_hwmod_class,
2915 .clkdm_name = "l4_wkup_clkdm",
2916 .mpu_irqs = omap44xx_timer1_irqs,
2917 .main_clk = "timer1_fck",
2918 .prcm = {
2919 .omap4 = {
2920 .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2921 .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
2922 .modulemode = MODULEMODE_SWCTRL,
2923 },
2924 },
2925 .dev_attr = &capability_alwon_dev_attr,
2926 };
2927
2928 /* timer2 */
2929 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
2930 { .irq = 38 + OMAP44XX_IRQ_GIC_START },
2931 { .irq = -1 }
2932 };
2933
2934 static struct omap_hwmod omap44xx_timer2_hwmod = {
2935 .name = "timer2",
2936 .class = &omap44xx_timer_1ms_hwmod_class,
2937 .clkdm_name = "l4_per_clkdm",
2938 .mpu_irqs = omap44xx_timer2_irqs,
2939 .main_clk = "timer2_fck",
2940 .prcm = {
2941 .omap4 = {
2942 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
2943 .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
2944 .modulemode = MODULEMODE_SWCTRL,
2945 },
2946 },
2947 .dev_attr = &capability_alwon_dev_attr,
2948 };
2949
2950 /* timer3 */
2951 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
2952 { .irq = 39 + OMAP44XX_IRQ_GIC_START },
2953 { .irq = -1 }
2954 };
2955
2956 static struct omap_hwmod omap44xx_timer3_hwmod = {
2957 .name = "timer3",
2958 .class = &omap44xx_timer_hwmod_class,
2959 .clkdm_name = "l4_per_clkdm",
2960 .mpu_irqs = omap44xx_timer3_irqs,
2961 .main_clk = "timer3_fck",
2962 .prcm = {
2963 .omap4 = {
2964 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
2965 .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
2966 .modulemode = MODULEMODE_SWCTRL,
2967 },
2968 },
2969 .dev_attr = &capability_alwon_dev_attr,
2970 };
2971
2972 /* timer4 */
2973 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
2974 { .irq = 40 + OMAP44XX_IRQ_GIC_START },
2975 { .irq = -1 }
2976 };
2977
2978 static struct omap_hwmod omap44xx_timer4_hwmod = {
2979 .name = "timer4",
2980 .class = &omap44xx_timer_hwmod_class,
2981 .clkdm_name = "l4_per_clkdm",
2982 .mpu_irqs = omap44xx_timer4_irqs,
2983 .main_clk = "timer4_fck",
2984 .prcm = {
2985 .omap4 = {
2986 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
2987 .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
2988 .modulemode = MODULEMODE_SWCTRL,
2989 },
2990 },
2991 .dev_attr = &capability_alwon_dev_attr,
2992 };
2993
2994 /* timer5 */
2995 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
2996 { .irq = 41 + OMAP44XX_IRQ_GIC_START },
2997 { .irq = -1 }
2998 };
2999
3000 static struct omap_hwmod omap44xx_timer5_hwmod = {
3001 .name = "timer5",
3002 .class = &omap44xx_timer_hwmod_class,
3003 .clkdm_name = "abe_clkdm",
3004 .mpu_irqs = omap44xx_timer5_irqs,
3005 .main_clk = "timer5_fck",
3006 .prcm = {
3007 .omap4 = {
3008 .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
3009 .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
3010 .modulemode = MODULEMODE_SWCTRL,
3011 },
3012 },
3013 .dev_attr = &capability_alwon_dev_attr,
3014 };
3015
3016 /* timer6 */
3017 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
3018 { .irq = 42 + OMAP44XX_IRQ_GIC_START },
3019 { .irq = -1 }
3020 };
3021
3022 static struct omap_hwmod omap44xx_timer6_hwmod = {
3023 .name = "timer6",
3024 .class = &omap44xx_timer_hwmod_class,
3025 .clkdm_name = "abe_clkdm",
3026 .mpu_irqs = omap44xx_timer6_irqs,
3027
3028 .main_clk = "timer6_fck",
3029 .prcm = {
3030 .omap4 = {
3031 .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
3032 .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
3033 .modulemode = MODULEMODE_SWCTRL,
3034 },
3035 },
3036 .dev_attr = &capability_alwon_dev_attr,
3037 };
3038
3039 /* timer7 */
3040 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
3041 { .irq = 43 + OMAP44XX_IRQ_GIC_START },
3042 { .irq = -1 }
3043 };
3044
3045 static struct omap_hwmod omap44xx_timer7_hwmod = {
3046 .name = "timer7",
3047 .class = &omap44xx_timer_hwmod_class,
3048 .clkdm_name = "abe_clkdm",
3049 .mpu_irqs = omap44xx_timer7_irqs,
3050 .main_clk = "timer7_fck",
3051 .prcm = {
3052 .omap4 = {
3053 .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
3054 .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
3055 .modulemode = MODULEMODE_SWCTRL,
3056 },
3057 },
3058 .dev_attr = &capability_alwon_dev_attr,
3059 };
3060
3061 /* timer8 */
3062 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
3063 { .irq = 44 + OMAP44XX_IRQ_GIC_START },
3064 { .irq = -1 }
3065 };
3066
3067 static struct omap_hwmod omap44xx_timer8_hwmod = {
3068 .name = "timer8",
3069 .class = &omap44xx_timer_hwmod_class,
3070 .clkdm_name = "abe_clkdm",
3071 .mpu_irqs = omap44xx_timer8_irqs,
3072 .main_clk = "timer8_fck",
3073 .prcm = {
3074 .omap4 = {
3075 .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
3076 .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
3077 .modulemode = MODULEMODE_SWCTRL,
3078 },
3079 },
3080 .dev_attr = &capability_pwm_dev_attr,
3081 };
3082
3083 /* timer9 */
3084 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
3085 { .irq = 45 + OMAP44XX_IRQ_GIC_START },
3086 { .irq = -1 }
3087 };
3088
3089 static struct omap_hwmod omap44xx_timer9_hwmod = {
3090 .name = "timer9",
3091 .class = &omap44xx_timer_hwmod_class,
3092 .clkdm_name = "l4_per_clkdm",
3093 .mpu_irqs = omap44xx_timer9_irqs,
3094 .main_clk = "timer9_fck",
3095 .prcm = {
3096 .omap4 = {
3097 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
3098 .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
3099 .modulemode = MODULEMODE_SWCTRL,
3100 },
3101 },
3102 .dev_attr = &capability_pwm_dev_attr,
3103 };
3104
3105 /* timer10 */
3106 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
3107 { .irq = 46 + OMAP44XX_IRQ_GIC_START },
3108 { .irq = -1 }
3109 };
3110
3111 static struct omap_hwmod omap44xx_timer10_hwmod = {
3112 .name = "timer10",
3113 .class = &omap44xx_timer_1ms_hwmod_class,
3114 .clkdm_name = "l4_per_clkdm",
3115 .mpu_irqs = omap44xx_timer10_irqs,
3116 .main_clk = "timer10_fck",
3117 .prcm = {
3118 .omap4 = {
3119 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
3120 .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
3121 .modulemode = MODULEMODE_SWCTRL,
3122 },
3123 },
3124 .dev_attr = &capability_pwm_dev_attr,
3125 };
3126
3127 /* timer11 */
3128 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
3129 { .irq = 47 + OMAP44XX_IRQ_GIC_START },
3130 { .irq = -1 }
3131 };
3132
3133 static struct omap_hwmod omap44xx_timer11_hwmod = {
3134 .name = "timer11",
3135 .class = &omap44xx_timer_hwmod_class,
3136 .clkdm_name = "l4_per_clkdm",
3137 .mpu_irqs = omap44xx_timer11_irqs,
3138 .main_clk = "timer11_fck",
3139 .prcm = {
3140 .omap4 = {
3141 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
3142 .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
3143 .modulemode = MODULEMODE_SWCTRL,
3144 },
3145 },
3146 .dev_attr = &capability_pwm_dev_attr,
3147 };
3148
3149 /*
3150 * 'uart' class
3151 * universal asynchronous receiver/transmitter (uart)
3152 */
3153
3154 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
3155 .rev_offs = 0x0050,
3156 .sysc_offs = 0x0054,
3157 .syss_offs = 0x0058,
3158 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3159 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3160 SYSS_HAS_RESET_STATUS),
3161 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3162 SIDLE_SMART_WKUP),
3163 .sysc_fields = &omap_hwmod_sysc_type1,
3164 };
3165
3166 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
3167 .name = "uart",
3168 .sysc = &omap44xx_uart_sysc,
3169 };
3170
3171 /* uart1 */
3172 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
3173 { .irq = 72 + OMAP44XX_IRQ_GIC_START },
3174 { .irq = -1 }
3175 };
3176
3177 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
3178 { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
3179 { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
3180 { .dma_req = -1 }
3181 };
3182
3183 static struct omap_hwmod omap44xx_uart1_hwmod = {
3184 .name = "uart1",
3185 .class = &omap44xx_uart_hwmod_class,
3186 .clkdm_name = "l4_per_clkdm",
3187 .mpu_irqs = omap44xx_uart1_irqs,
3188 .sdma_reqs = omap44xx_uart1_sdma_reqs,
3189 .main_clk = "uart1_fck",
3190 .prcm = {
3191 .omap4 = {
3192 .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
3193 .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
3194 .modulemode = MODULEMODE_SWCTRL,
3195 },
3196 },
3197 };
3198
3199 /* uart2 */
3200 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
3201 { .irq = 73 + OMAP44XX_IRQ_GIC_START },
3202 { .irq = -1 }
3203 };
3204
3205 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
3206 { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
3207 { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
3208 { .dma_req = -1 }
3209 };
3210
3211 static struct omap_hwmod omap44xx_uart2_hwmod = {
3212 .name = "uart2",
3213 .class = &omap44xx_uart_hwmod_class,
3214 .clkdm_name = "l4_per_clkdm",
3215 .mpu_irqs = omap44xx_uart2_irqs,
3216 .sdma_reqs = omap44xx_uart2_sdma_reqs,
3217 .main_clk = "uart2_fck",
3218 .prcm = {
3219 .omap4 = {
3220 .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
3221 .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
3222 .modulemode = MODULEMODE_SWCTRL,
3223 },
3224 },
3225 };
3226
3227 /* uart3 */
3228 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
3229 { .irq = 74 + OMAP44XX_IRQ_GIC_START },
3230 { .irq = -1 }
3231 };
3232
3233 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
3234 { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
3235 { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
3236 { .dma_req = -1 }
3237 };
3238
3239 static struct omap_hwmod omap44xx_uart3_hwmod = {
3240 .name = "uart3",
3241 .class = &omap44xx_uart_hwmod_class,
3242 .clkdm_name = "l4_per_clkdm",
3243 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3244 .mpu_irqs = omap44xx_uart3_irqs,
3245 .sdma_reqs = omap44xx_uart3_sdma_reqs,
3246 .main_clk = "uart3_fck",
3247 .prcm = {
3248 .omap4 = {
3249 .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
3250 .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
3251 .modulemode = MODULEMODE_SWCTRL,
3252 },
3253 },
3254 };
3255
3256 /* uart4 */
3257 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
3258 { .irq = 70 + OMAP44XX_IRQ_GIC_START },
3259 { .irq = -1 }
3260 };
3261
3262 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
3263 { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
3264 { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
3265 { .dma_req = -1 }
3266 };
3267
3268 static struct omap_hwmod omap44xx_uart4_hwmod = {
3269 .name = "uart4",
3270 .class = &omap44xx_uart_hwmod_class,
3271 .clkdm_name = "l4_per_clkdm",
3272 .mpu_irqs = omap44xx_uart4_irqs,
3273 .sdma_reqs = omap44xx_uart4_sdma_reqs,
3274 .main_clk = "uart4_fck",
3275 .prcm = {
3276 .omap4 = {
3277 .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
3278 .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
3279 .modulemode = MODULEMODE_SWCTRL,
3280 },
3281 },
3282 };
3283
3284 /*
3285 * 'usb_host_fs' class
3286 * full-speed usb host controller
3287 */
3288
3289 /* The IP is not compliant to type1 / type2 scheme */
3290 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
3291 .midle_shift = 4,
3292 .sidle_shift = 2,
3293 .srst_shift = 1,
3294 };
3295
3296 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
3297 .rev_offs = 0x0000,
3298 .sysc_offs = 0x0210,
3299 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3300 SYSC_HAS_SOFTRESET),
3301 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3302 SIDLE_SMART_WKUP),
3303 .sysc_fields = &omap_hwmod_sysc_type_usb_host_fs,
3304 };
3305
3306 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
3307 .name = "usb_host_fs",
3308 .sysc = &omap44xx_usb_host_fs_sysc,
3309 };
3310
3311 /* usb_host_fs */
3312 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
3313 { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
3314 { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
3315 { .irq = -1 }
3316 };
3317
3318 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
3319 .name = "usb_host_fs",
3320 .class = &omap44xx_usb_host_fs_hwmod_class,
3321 .clkdm_name = "l3_init_clkdm",
3322 .mpu_irqs = omap44xx_usb_host_fs_irqs,
3323 .main_clk = "usb_host_fs_fck",
3324 .prcm = {
3325 .omap4 = {
3326 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
3327 .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
3328 .modulemode = MODULEMODE_SWCTRL,
3329 },
3330 },
3331 };
3332
3333 /*
3334 * 'usb_host_hs' class
3335 * high-speed multi-port usb host controller
3336 */
3337
3338 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
3339 .rev_offs = 0x0000,
3340 .sysc_offs = 0x0010,
3341 .syss_offs = 0x0014,
3342 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3343 SYSC_HAS_SOFTRESET),
3344 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3345 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3346 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3347 .sysc_fields = &omap_hwmod_sysc_type2,
3348 };
3349
3350 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
3351 .name = "usb_host_hs",
3352 .sysc = &omap44xx_usb_host_hs_sysc,
3353 };
3354
3355 /* usb_host_hs */
3356 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
3357 { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
3358 { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
3359 { .irq = -1 }
3360 };
3361
3362 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
3363 .name = "usb_host_hs",
3364 .class = &omap44xx_usb_host_hs_hwmod_class,
3365 .clkdm_name = "l3_init_clkdm",
3366 .main_clk = "usb_host_hs_fck",
3367 .prcm = {
3368 .omap4 = {
3369 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
3370 .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
3371 .modulemode = MODULEMODE_SWCTRL,
3372 },
3373 },
3374 .mpu_irqs = omap44xx_usb_host_hs_irqs,
3375
3376 /*
3377 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3378 * id: i660
3379 *
3380 * Description:
3381 * In the following configuration :
3382 * - USBHOST module is set to smart-idle mode
3383 * - PRCM asserts idle_req to the USBHOST module ( This typically
3384 * happens when the system is going to a low power mode : all ports
3385 * have been suspended, the master part of the USBHOST module has
3386 * entered the standby state, and SW has cut the functional clocks)
3387 * - an USBHOST interrupt occurs before the module is able to answer
3388 * idle_ack, typically a remote wakeup IRQ.
3389 * Then the USB HOST module will enter a deadlock situation where it
3390 * is no more accessible nor functional.
3391 *
3392 * Workaround:
3393 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3394 */
3395
3396 /*
3397 * Errata: USB host EHCI may stall when entering smart-standby mode
3398 * Id: i571
3399 *
3400 * Description:
3401 * When the USBHOST module is set to smart-standby mode, and when it is
3402 * ready to enter the standby state (i.e. all ports are suspended and
3403 * all attached devices are in suspend mode), then it can wrongly assert
3404 * the Mstandby signal too early while there are still some residual OCP
3405 * transactions ongoing. If this condition occurs, the internal state
3406 * machine may go to an undefined state and the USB link may be stuck
3407 * upon the next resume.
3408 *
3409 * Workaround:
3410 * Don't use smart standby; use only force standby,
3411 * hence HWMOD_SWSUP_MSTANDBY
3412 */
3413
3414 /*
3415 * During system boot; If the hwmod framework resets the module
3416 * the module will have smart idle settings; which can lead to deadlock
3417 * (above Errata Id:i660); so, dont reset the module during boot;
3418 * Use HWMOD_INIT_NO_RESET.
3419 */
3420
3421 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3422 HWMOD_INIT_NO_RESET,
3423 };
3424
3425 /*
3426 * 'usb_otg_hs' class
3427 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3428 */
3429
3430 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3431 .rev_offs = 0x0400,
3432 .sysc_offs = 0x0404,
3433 .syss_offs = 0x0408,
3434 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3435 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3436 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3437 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3438 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3439 MSTANDBY_SMART),
3440 .sysc_fields = &omap_hwmod_sysc_type1,
3441 };
3442
3443 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3444 .name = "usb_otg_hs",
3445 .sysc = &omap44xx_usb_otg_hs_sysc,
3446 };
3447
3448 /* usb_otg_hs */
3449 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
3450 { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
3451 { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
3452 { .irq = -1 }
3453 };
3454
3455 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3456 { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3457 };
3458
3459 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3460 .name = "usb_otg_hs",
3461 .class = &omap44xx_usb_otg_hs_hwmod_class,
3462 .clkdm_name = "l3_init_clkdm",
3463 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3464 .mpu_irqs = omap44xx_usb_otg_hs_irqs,
3465 .main_clk = "usb_otg_hs_ick",
3466 .prcm = {
3467 .omap4 = {
3468 .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3469 .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3470 .modulemode = MODULEMODE_HWCTRL,
3471 },
3472 },
3473 .opt_clks = usb_otg_hs_opt_clks,
3474 .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
3475 };
3476
3477 /*
3478 * 'usb_tll_hs' class
3479 * usb_tll_hs module is the adapter on the usb_host_hs ports
3480 */
3481
3482 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3483 .rev_offs = 0x0000,
3484 .sysc_offs = 0x0010,
3485 .syss_offs = 0x0014,
3486 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3487 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3488 SYSC_HAS_AUTOIDLE),
3489 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3490 .sysc_fields = &omap_hwmod_sysc_type1,
3491 };
3492
3493 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3494 .name = "usb_tll_hs",
3495 .sysc = &omap44xx_usb_tll_hs_sysc,
3496 };
3497
3498 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
3499 { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
3500 { .irq = -1 }
3501 };
3502
3503 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3504 .name = "usb_tll_hs",
3505 .class = &omap44xx_usb_tll_hs_hwmod_class,
3506 .clkdm_name = "l3_init_clkdm",
3507 .mpu_irqs = omap44xx_usb_tll_hs_irqs,
3508 .main_clk = "usb_tll_hs_ick",
3509 .prcm = {
3510 .omap4 = {
3511 .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3512 .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3513 .modulemode = MODULEMODE_HWCTRL,
3514 },
3515 },
3516 };
3517
3518 /*
3519 * 'wd_timer' class
3520 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3521 * overflow condition
3522 */
3523
3524 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3525 .rev_offs = 0x0000,
3526 .sysc_offs = 0x0010,
3527 .syss_offs = 0x0014,
3528 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3529 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3530 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3531 SIDLE_SMART_WKUP),
3532 .sysc_fields = &omap_hwmod_sysc_type1,
3533 };
3534
3535 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3536 .name = "wd_timer",
3537 .sysc = &omap44xx_wd_timer_sysc,
3538 .pre_shutdown = &omap2_wd_timer_disable,
3539 .reset = &omap2_wd_timer_reset,
3540 };
3541
3542 /* wd_timer2 */
3543 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
3544 { .irq = 80 + OMAP44XX_IRQ_GIC_START },
3545 { .irq = -1 }
3546 };
3547
3548 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3549 .name = "wd_timer2",
3550 .class = &omap44xx_wd_timer_hwmod_class,
3551 .clkdm_name = "l4_wkup_clkdm",
3552 .mpu_irqs = omap44xx_wd_timer2_irqs,
3553 .main_clk = "wd_timer2_fck",
3554 .prcm = {
3555 .omap4 = {
3556 .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3557 .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3558 .modulemode = MODULEMODE_SWCTRL,
3559 },
3560 },
3561 };
3562
3563 /* wd_timer3 */
3564 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
3565 { .irq = 36 + OMAP44XX_IRQ_GIC_START },
3566 { .irq = -1 }
3567 };
3568
3569 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3570 .name = "wd_timer3",
3571 .class = &omap44xx_wd_timer_hwmod_class,
3572 .clkdm_name = "abe_clkdm",
3573 .mpu_irqs = omap44xx_wd_timer3_irqs,
3574 .main_clk = "wd_timer3_fck",
3575 .prcm = {
3576 .omap4 = {
3577 .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3578 .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3579 .modulemode = MODULEMODE_SWCTRL,
3580 },
3581 },
3582 };
3583
3584
3585 /*
3586 * interfaces
3587 */
3588
3589 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
3590 {
3591 .pa_start = 0x4a204000,
3592 .pa_end = 0x4a2040ff,
3593 .flags = ADDR_TYPE_RT
3594 },
3595 { }
3596 };
3597
3598 /* c2c -> c2c_target_fw */
3599 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
3600 .master = &omap44xx_c2c_hwmod,
3601 .slave = &omap44xx_c2c_target_fw_hwmod,
3602 .clk = "div_core_ck",
3603 .addr = omap44xx_c2c_target_fw_addrs,
3604 .user = OCP_USER_MPU,
3605 };
3606
3607 /* l4_cfg -> c2c_target_fw */
3608 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
3609 .master = &omap44xx_l4_cfg_hwmod,
3610 .slave = &omap44xx_c2c_target_fw_hwmod,
3611 .clk = "l4_div_ck",
3612 .user = OCP_USER_MPU | OCP_USER_SDMA,
3613 };
3614
3615 /* l3_main_1 -> dmm */
3616 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3617 .master = &omap44xx_l3_main_1_hwmod,
3618 .slave = &omap44xx_dmm_hwmod,
3619 .clk = "l3_div_ck",
3620 .user = OCP_USER_SDMA,
3621 };
3622
3623 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
3624 {
3625 .pa_start = 0x4e000000,
3626 .pa_end = 0x4e0007ff,
3627 .flags = ADDR_TYPE_RT
3628 },
3629 { }
3630 };
3631
3632 /* mpu -> dmm */
3633 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3634 .master = &omap44xx_mpu_hwmod,
3635 .slave = &omap44xx_dmm_hwmod,
3636 .clk = "l3_div_ck",
3637 .addr = omap44xx_dmm_addrs,
3638 .user = OCP_USER_MPU,
3639 };
3640
3641 /* c2c -> emif_fw */
3642 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
3643 .master = &omap44xx_c2c_hwmod,
3644 .slave = &omap44xx_emif_fw_hwmod,
3645 .clk = "div_core_ck",
3646 .user = OCP_USER_MPU | OCP_USER_SDMA,
3647 };
3648
3649 /* dmm -> emif_fw */
3650 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
3651 .master = &omap44xx_dmm_hwmod,
3652 .slave = &omap44xx_emif_fw_hwmod,
3653 .clk = "l3_div_ck",
3654 .user = OCP_USER_MPU | OCP_USER_SDMA,
3655 };
3656
3657 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
3658 {
3659 .pa_start = 0x4a20c000,
3660 .pa_end = 0x4a20c0ff,
3661 .flags = ADDR_TYPE_RT
3662 },
3663 { }
3664 };
3665
3666 /* l4_cfg -> emif_fw */
3667 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
3668 .master = &omap44xx_l4_cfg_hwmod,
3669 .slave = &omap44xx_emif_fw_hwmod,
3670 .clk = "l4_div_ck",
3671 .addr = omap44xx_emif_fw_addrs,
3672 .user = OCP_USER_MPU,
3673 };
3674
3675 /* iva -> l3_instr */
3676 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3677 .master = &omap44xx_iva_hwmod,
3678 .slave = &omap44xx_l3_instr_hwmod,
3679 .clk = "l3_div_ck",
3680 .user = OCP_USER_MPU | OCP_USER_SDMA,
3681 };
3682
3683 /* l3_main_3 -> l3_instr */
3684 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3685 .master = &omap44xx_l3_main_3_hwmod,
3686 .slave = &omap44xx_l3_instr_hwmod,
3687 .clk = "l3_div_ck",
3688 .user = OCP_USER_MPU | OCP_USER_SDMA,
3689 };
3690
3691 /* ocp_wp_noc -> l3_instr */
3692 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3693 .master = &omap44xx_ocp_wp_noc_hwmod,
3694 .slave = &omap44xx_l3_instr_hwmod,
3695 .clk = "l3_div_ck",
3696 .user = OCP_USER_MPU | OCP_USER_SDMA,
3697 };
3698
3699 /* dsp -> l3_main_1 */
3700 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3701 .master = &omap44xx_dsp_hwmod,
3702 .slave = &omap44xx_l3_main_1_hwmod,
3703 .clk = "l3_div_ck",
3704 .user = OCP_USER_MPU | OCP_USER_SDMA,
3705 };
3706
3707 /* dss -> l3_main_1 */
3708 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3709 .master = &omap44xx_dss_hwmod,
3710 .slave = &omap44xx_l3_main_1_hwmod,
3711 .clk = "l3_div_ck",
3712 .user = OCP_USER_MPU | OCP_USER_SDMA,
3713 };
3714
3715 /* l3_main_2 -> l3_main_1 */
3716 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3717 .master = &omap44xx_l3_main_2_hwmod,
3718 .slave = &omap44xx_l3_main_1_hwmod,
3719 .clk = "l3_div_ck",
3720 .user = OCP_USER_MPU | OCP_USER_SDMA,
3721 };
3722
3723 /* l4_cfg -> l3_main_1 */
3724 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3725 .master = &omap44xx_l4_cfg_hwmod,
3726 .slave = &omap44xx_l3_main_1_hwmod,
3727 .clk = "l4_div_ck",
3728 .user = OCP_USER_MPU | OCP_USER_SDMA,
3729 };
3730
3731 /* mmc1 -> l3_main_1 */
3732 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3733 .master = &omap44xx_mmc1_hwmod,
3734 .slave = &omap44xx_l3_main_1_hwmod,
3735 .clk = "l3_div_ck",
3736 .user = OCP_USER_MPU | OCP_USER_SDMA,
3737 };
3738
3739 /* mmc2 -> l3_main_1 */
3740 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3741 .master = &omap44xx_mmc2_hwmod,
3742 .slave = &omap44xx_l3_main_1_hwmod,
3743 .clk = "l3_div_ck",
3744 .user = OCP_USER_MPU | OCP_USER_SDMA,
3745 };
3746
3747 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
3748 {
3749 .pa_start = 0x44000000,
3750 .pa_end = 0x44000fff,
3751 .flags = ADDR_TYPE_RT
3752 },
3753 { }
3754 };
3755
3756 /* mpu -> l3_main_1 */
3757 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3758 .master = &omap44xx_mpu_hwmod,
3759 .slave = &omap44xx_l3_main_1_hwmod,
3760 .clk = "l3_div_ck",
3761 .addr = omap44xx_l3_main_1_addrs,
3762 .user = OCP_USER_MPU,
3763 };
3764
3765 /* c2c_target_fw -> l3_main_2 */
3766 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
3767 .master = &omap44xx_c2c_target_fw_hwmod,
3768 .slave = &omap44xx_l3_main_2_hwmod,
3769 .clk = "l3_div_ck",
3770 .user = OCP_USER_MPU | OCP_USER_SDMA,
3771 };
3772
3773 /* debugss -> l3_main_2 */
3774 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
3775 .master = &omap44xx_debugss_hwmod,
3776 .slave = &omap44xx_l3_main_2_hwmod,
3777 .clk = "dbgclk_mux_ck",
3778 .user = OCP_USER_MPU | OCP_USER_SDMA,
3779 };
3780
3781 /* dma_system -> l3_main_2 */
3782 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
3783 .master = &omap44xx_dma_system_hwmod,
3784 .slave = &omap44xx_l3_main_2_hwmod,
3785 .clk = "l3_div_ck",
3786 .user = OCP_USER_MPU | OCP_USER_SDMA,
3787 };
3788
3789 /* fdif -> l3_main_2 */
3790 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3791 .master = &omap44xx_fdif_hwmod,
3792 .slave = &omap44xx_l3_main_2_hwmod,
3793 .clk = "l3_div_ck",
3794 .user = OCP_USER_MPU | OCP_USER_SDMA,
3795 };
3796
3797 /* gpu -> l3_main_2 */
3798 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
3799 .master = &omap44xx_gpu_hwmod,
3800 .slave = &omap44xx_l3_main_2_hwmod,
3801 .clk = "l3_div_ck",
3802 .user = OCP_USER_MPU | OCP_USER_SDMA,
3803 };
3804
3805 /* hsi -> l3_main_2 */
3806 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
3807 .master = &omap44xx_hsi_hwmod,
3808 .slave = &omap44xx_l3_main_2_hwmod,
3809 .clk = "l3_div_ck",
3810 .user = OCP_USER_MPU | OCP_USER_SDMA,
3811 };
3812
3813 /* ipu -> l3_main_2 */
3814 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
3815 .master = &omap44xx_ipu_hwmod,
3816 .slave = &omap44xx_l3_main_2_hwmod,
3817 .clk = "l3_div_ck",
3818 .user = OCP_USER_MPU | OCP_USER_SDMA,
3819 };
3820
3821 /* iss -> l3_main_2 */
3822 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
3823 .master = &omap44xx_iss_hwmod,
3824 .slave = &omap44xx_l3_main_2_hwmod,
3825 .clk = "l3_div_ck",
3826 .user = OCP_USER_MPU | OCP_USER_SDMA,
3827 };
3828
3829 /* iva -> l3_main_2 */
3830 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
3831 .master = &omap44xx_iva_hwmod,
3832 .slave = &omap44xx_l3_main_2_hwmod,
3833 .clk = "l3_div_ck",
3834 .user = OCP_USER_MPU | OCP_USER_SDMA,
3835 };
3836
3837 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
3838 {
3839 .pa_start = 0x44800000,
3840 .pa_end = 0x44801fff,
3841 .flags = ADDR_TYPE_RT
3842 },
3843 { }
3844 };
3845
3846 /* l3_main_1 -> l3_main_2 */
3847 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
3848 .master = &omap44xx_l3_main_1_hwmod,
3849 .slave = &omap44xx_l3_main_2_hwmod,
3850 .clk = "l3_div_ck",
3851 .addr = omap44xx_l3_main_2_addrs,
3852 .user = OCP_USER_MPU,
3853 };
3854
3855 /* l4_cfg -> l3_main_2 */
3856 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
3857 .master = &omap44xx_l4_cfg_hwmod,
3858 .slave = &omap44xx_l3_main_2_hwmod,
3859 .clk = "l4_div_ck",
3860 .user = OCP_USER_MPU | OCP_USER_SDMA,
3861 };
3862
3863 /* usb_host_fs -> l3_main_2 */
3864 static struct omap_hwmod_ocp_if omap44xx_usb_host_fs__l3_main_2 = {
3865 .master = &omap44xx_usb_host_fs_hwmod,
3866 .slave = &omap44xx_l3_main_2_hwmod,
3867 .clk = "l3_div_ck",
3868 .user = OCP_USER_MPU | OCP_USER_SDMA,
3869 };
3870
3871 /* usb_host_hs -> l3_main_2 */
3872 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
3873 .master = &omap44xx_usb_host_hs_hwmod,
3874 .slave = &omap44xx_l3_main_2_hwmod,
3875 .clk = "l3_div_ck",
3876 .user = OCP_USER_MPU | OCP_USER_SDMA,
3877 };
3878
3879 /* usb_otg_hs -> l3_main_2 */
3880 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
3881 .master = &omap44xx_usb_otg_hs_hwmod,
3882 .slave = &omap44xx_l3_main_2_hwmod,
3883 .clk = "l3_div_ck",
3884 .user = OCP_USER_MPU | OCP_USER_SDMA,
3885 };
3886
3887 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
3888 {
3889 .pa_start = 0x45000000,
3890 .pa_end = 0x45000fff,
3891 .flags = ADDR_TYPE_RT
3892 },
3893 { }
3894 };
3895
3896 /* l3_main_1 -> l3_main_3 */
3897 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
3898 .master = &omap44xx_l3_main_1_hwmod,
3899 .slave = &omap44xx_l3_main_3_hwmod,
3900 .clk = "l3_div_ck",
3901 .addr = omap44xx_l3_main_3_addrs,
3902 .user = OCP_USER_MPU,
3903 };
3904
3905 /* l3_main_2 -> l3_main_3 */
3906 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
3907 .master = &omap44xx_l3_main_2_hwmod,
3908 .slave = &omap44xx_l3_main_3_hwmod,
3909 .clk = "l3_div_ck",
3910 .user = OCP_USER_MPU | OCP_USER_SDMA,
3911 };
3912
3913 /* l4_cfg -> l3_main_3 */
3914 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
3915 .master = &omap44xx_l4_cfg_hwmod,
3916 .slave = &omap44xx_l3_main_3_hwmod,
3917 .clk = "l4_div_ck",
3918 .user = OCP_USER_MPU | OCP_USER_SDMA,
3919 };
3920
3921 /* aess -> l4_abe */
3922 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
3923 .master = &omap44xx_aess_hwmod,
3924 .slave = &omap44xx_l4_abe_hwmod,
3925 .clk = "ocp_abe_iclk",
3926 .user = OCP_USER_MPU | OCP_USER_SDMA,
3927 };
3928
3929 /* dsp -> l4_abe */
3930 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
3931 .master = &omap44xx_dsp_hwmod,
3932 .slave = &omap44xx_l4_abe_hwmod,
3933 .clk = "ocp_abe_iclk",
3934 .user = OCP_USER_MPU | OCP_USER_SDMA,
3935 };
3936
3937 /* l3_main_1 -> l4_abe */
3938 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
3939 .master = &omap44xx_l3_main_1_hwmod,
3940 .slave = &omap44xx_l4_abe_hwmod,
3941 .clk = "l3_div_ck",
3942 .user = OCP_USER_MPU | OCP_USER_SDMA,
3943 };
3944
3945 /* mpu -> l4_abe */
3946 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
3947 .master = &omap44xx_mpu_hwmod,
3948 .slave = &omap44xx_l4_abe_hwmod,
3949 .clk = "ocp_abe_iclk",
3950 .user = OCP_USER_MPU | OCP_USER_SDMA,
3951 };
3952
3953 /* l3_main_1 -> l4_cfg */
3954 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
3955 .master = &omap44xx_l3_main_1_hwmod,
3956 .slave = &omap44xx_l4_cfg_hwmod,
3957 .clk = "l3_div_ck",
3958 .user = OCP_USER_MPU | OCP_USER_SDMA,
3959 };
3960
3961 /* l3_main_2 -> l4_per */
3962 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
3963 .master = &omap44xx_l3_main_2_hwmod,
3964 .slave = &omap44xx_l4_per_hwmod,
3965 .clk = "l3_div_ck",
3966 .user = OCP_USER_MPU | OCP_USER_SDMA,
3967 };
3968
3969 /* l4_cfg -> l4_wkup */
3970 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
3971 .master = &omap44xx_l4_cfg_hwmod,
3972 .slave = &omap44xx_l4_wkup_hwmod,
3973 .clk = "l4_div_ck",
3974 .user = OCP_USER_MPU | OCP_USER_SDMA,
3975 };
3976
3977 /* mpu -> mpu_private */
3978 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
3979 .master = &omap44xx_mpu_hwmod,
3980 .slave = &omap44xx_mpu_private_hwmod,
3981 .clk = "l3_div_ck",
3982 .user = OCP_USER_MPU | OCP_USER_SDMA,
3983 };
3984
3985 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
3986 {
3987 .pa_start = 0x4a102000,
3988 .pa_end = 0x4a10207f,
3989 .flags = ADDR_TYPE_RT
3990 },
3991 { }
3992 };
3993
3994 /* l4_cfg -> ocp_wp_noc */
3995 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
3996 .master = &omap44xx_l4_cfg_hwmod,
3997 .slave = &omap44xx_ocp_wp_noc_hwmod,
3998 .clk = "l4_div_ck",
3999 .addr = omap44xx_ocp_wp_noc_addrs,
4000 .user = OCP_USER_MPU | OCP_USER_SDMA,
4001 };
4002
4003 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
4004 {
4005 .pa_start = 0x401f1000,
4006 .pa_end = 0x401f13ff,
4007 .flags = ADDR_TYPE_RT
4008 },
4009 { }
4010 };
4011
4012 /* l4_abe -> aess */
4013 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
4014 .master = &omap44xx_l4_abe_hwmod,
4015 .slave = &omap44xx_aess_hwmod,
4016 .clk = "ocp_abe_iclk",
4017 .addr = omap44xx_aess_addrs,
4018 .user = OCP_USER_MPU,
4019 };
4020
4021 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
4022 {
4023 .pa_start = 0x490f1000,
4024 .pa_end = 0x490f13ff,
4025 .flags = ADDR_TYPE_RT
4026 },
4027 { }
4028 };
4029
4030 /* l4_abe -> aess (dma) */
4031 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
4032 .master = &omap44xx_l4_abe_hwmod,
4033 .slave = &omap44xx_aess_hwmod,
4034 .clk = "ocp_abe_iclk",
4035 .addr = omap44xx_aess_dma_addrs,
4036 .user = OCP_USER_SDMA,
4037 };
4038
4039 /* l3_main_2 -> c2c */
4040 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
4041 .master = &omap44xx_l3_main_2_hwmod,
4042 .slave = &omap44xx_c2c_hwmod,
4043 .clk = "l3_div_ck",
4044 .user = OCP_USER_MPU | OCP_USER_SDMA,
4045 };
4046
4047 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
4048 {
4049 .pa_start = 0x4a304000,
4050 .pa_end = 0x4a30401f,
4051 .flags = ADDR_TYPE_RT
4052 },
4053 { }
4054 };
4055
4056 /* l4_wkup -> counter_32k */
4057 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
4058 .master = &omap44xx_l4_wkup_hwmod,
4059 .slave = &omap44xx_counter_32k_hwmod,
4060 .clk = "l4_wkup_clk_mux_ck",
4061 .addr = omap44xx_counter_32k_addrs,
4062 .user = OCP_USER_MPU | OCP_USER_SDMA,
4063 };
4064
4065 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
4066 {
4067 .pa_start = 0x4a002000,
4068 .pa_end = 0x4a0027ff,
4069 .flags = ADDR_TYPE_RT
4070 },
4071 { }
4072 };
4073
4074 /* l4_cfg -> ctrl_module_core */
4075 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
4076 .master = &omap44xx_l4_cfg_hwmod,
4077 .slave = &omap44xx_ctrl_module_core_hwmod,
4078 .clk = "l4_div_ck",
4079 .addr = omap44xx_ctrl_module_core_addrs,
4080 .user = OCP_USER_MPU | OCP_USER_SDMA,
4081 };
4082
4083 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
4084 {
4085 .pa_start = 0x4a100000,
4086 .pa_end = 0x4a1007ff,
4087 .flags = ADDR_TYPE_RT
4088 },
4089 { }
4090 };
4091
4092 /* l4_cfg -> ctrl_module_pad_core */
4093 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
4094 .master = &omap44xx_l4_cfg_hwmod,
4095 .slave = &omap44xx_ctrl_module_pad_core_hwmod,
4096 .clk = "l4_div_ck",
4097 .addr = omap44xx_ctrl_module_pad_core_addrs,
4098 .user = OCP_USER_MPU | OCP_USER_SDMA,
4099 };
4100
4101 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
4102 {
4103 .pa_start = 0x4a30c000,
4104 .pa_end = 0x4a30c7ff,
4105 .flags = ADDR_TYPE_RT
4106 },
4107 { }
4108 };
4109
4110 /* l4_wkup -> ctrl_module_wkup */
4111 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
4112 .master = &omap44xx_l4_wkup_hwmod,
4113 .slave = &omap44xx_ctrl_module_wkup_hwmod,
4114 .clk = "l4_wkup_clk_mux_ck",
4115 .addr = omap44xx_ctrl_module_wkup_addrs,
4116 .user = OCP_USER_MPU | OCP_USER_SDMA,
4117 };
4118
4119 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
4120 {
4121 .pa_start = 0x4a31e000,
4122 .pa_end = 0x4a31e7ff,
4123 .flags = ADDR_TYPE_RT
4124 },
4125 { }
4126 };
4127
4128 /* l4_wkup -> ctrl_module_pad_wkup */
4129 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
4130 .master = &omap44xx_l4_wkup_hwmod,
4131 .slave = &omap44xx_ctrl_module_pad_wkup_hwmod,
4132 .clk = "l4_wkup_clk_mux_ck",
4133 .addr = omap44xx_ctrl_module_pad_wkup_addrs,
4134 .user = OCP_USER_MPU | OCP_USER_SDMA,
4135 };
4136
4137 static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
4138 {
4139 .pa_start = 0x54160000,
4140 .pa_end = 0x54167fff,
4141 .flags = ADDR_TYPE_RT
4142 },
4143 { }
4144 };
4145
4146 /* l3_instr -> debugss */
4147 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
4148 .master = &omap44xx_l3_instr_hwmod,
4149 .slave = &omap44xx_debugss_hwmod,
4150 .clk = "l3_div_ck",
4151 .addr = omap44xx_debugss_addrs,
4152 .user = OCP_USER_MPU | OCP_USER_SDMA,
4153 };
4154
4155 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
4156 {
4157 .pa_start = 0x4a056000,
4158 .pa_end = 0x4a056fff,
4159 .flags = ADDR_TYPE_RT
4160 },
4161 { }
4162 };
4163
4164 /* l4_cfg -> dma_system */
4165 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
4166 .master = &omap44xx_l4_cfg_hwmod,
4167 .slave = &omap44xx_dma_system_hwmod,
4168 .clk = "l4_div_ck",
4169 .addr = omap44xx_dma_system_addrs,
4170 .user = OCP_USER_MPU | OCP_USER_SDMA,
4171 };
4172
4173 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
4174 {
4175 .name = "mpu",
4176 .pa_start = 0x4012e000,
4177 .pa_end = 0x4012e07f,
4178 .flags = ADDR_TYPE_RT
4179 },
4180 { }
4181 };
4182
4183 /* l4_abe -> dmic */
4184 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
4185 .master = &omap44xx_l4_abe_hwmod,
4186 .slave = &omap44xx_dmic_hwmod,
4187 .clk = "ocp_abe_iclk",
4188 .addr = omap44xx_dmic_addrs,
4189 .user = OCP_USER_MPU,
4190 };
4191
4192 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
4193 {
4194 .name = "dma",
4195 .pa_start = 0x4902e000,
4196 .pa_end = 0x4902e07f,
4197 .flags = ADDR_TYPE_RT
4198 },
4199 { }
4200 };
4201
4202 /* l4_abe -> dmic (dma) */
4203 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
4204 .master = &omap44xx_l4_abe_hwmod,
4205 .slave = &omap44xx_dmic_hwmod,
4206 .clk = "ocp_abe_iclk",
4207 .addr = omap44xx_dmic_dma_addrs,
4208 .user = OCP_USER_SDMA,
4209 };
4210
4211 /* dsp -> iva */
4212 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
4213 .master = &omap44xx_dsp_hwmod,
4214 .slave = &omap44xx_iva_hwmod,
4215 .clk = "dpll_iva_m5x2_ck",
4216 .user = OCP_USER_DSP,
4217 };
4218
4219 /* dsp -> sl2if */
4220 static struct omap_hwmod_ocp_if omap44xx_dsp__sl2if = {
4221 .master = &omap44xx_dsp_hwmod,
4222 .slave = &omap44xx_sl2if_hwmod,
4223 .clk = "dpll_iva_m5x2_ck",
4224 .user = OCP_USER_DSP,
4225 };
4226
4227 /* l4_cfg -> dsp */
4228 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
4229 .master = &omap44xx_l4_cfg_hwmod,
4230 .slave = &omap44xx_dsp_hwmod,
4231 .clk = "l4_div_ck",
4232 .user = OCP_USER_MPU | OCP_USER_SDMA,
4233 };
4234
4235 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
4236 {
4237 .pa_start = 0x58000000,
4238 .pa_end = 0x5800007f,
4239 .flags = ADDR_TYPE_RT
4240 },
4241 { }
4242 };
4243
4244 /* l3_main_2 -> dss */
4245 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
4246 .master = &omap44xx_l3_main_2_hwmod,
4247 .slave = &omap44xx_dss_hwmod,
4248 .clk = "dss_fck",
4249 .addr = omap44xx_dss_dma_addrs,
4250 .user = OCP_USER_SDMA,
4251 };
4252
4253 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
4254 {
4255 .pa_start = 0x48040000,
4256 .pa_end = 0x4804007f,
4257 .flags = ADDR_TYPE_RT
4258 },
4259 { }
4260 };
4261
4262 /* l4_per -> dss */
4263 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
4264 .master = &omap44xx_l4_per_hwmod,
4265 .slave = &omap44xx_dss_hwmod,
4266 .clk = "l4_div_ck",
4267 .addr = omap44xx_dss_addrs,
4268 .user = OCP_USER_MPU,
4269 };
4270
4271 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
4272 {
4273 .pa_start = 0x58001000,
4274 .pa_end = 0x58001fff,
4275 .flags = ADDR_TYPE_RT
4276 },
4277 { }
4278 };
4279
4280 /* l3_main_2 -> dss_dispc */
4281 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
4282 .master = &omap44xx_l3_main_2_hwmod,
4283 .slave = &omap44xx_dss_dispc_hwmod,
4284 .clk = "dss_fck",
4285 .addr = omap44xx_dss_dispc_dma_addrs,
4286 .user = OCP_USER_SDMA,
4287 };
4288
4289 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
4290 {
4291 .pa_start = 0x48041000,
4292 .pa_end = 0x48041fff,
4293 .flags = ADDR_TYPE_RT
4294 },
4295 { }
4296 };
4297
4298 /* l4_per -> dss_dispc */
4299 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
4300 .master = &omap44xx_l4_per_hwmod,
4301 .slave = &omap44xx_dss_dispc_hwmod,
4302 .clk = "l4_div_ck",
4303 .addr = omap44xx_dss_dispc_addrs,
4304 .user = OCP_USER_MPU,
4305 };
4306
4307 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
4308 {
4309 .pa_start = 0x58004000,
4310 .pa_end = 0x580041ff,
4311 .flags = ADDR_TYPE_RT
4312 },
4313 { }
4314 };
4315
4316 /* l3_main_2 -> dss_dsi1 */
4317 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
4318 .master = &omap44xx_l3_main_2_hwmod,
4319 .slave = &omap44xx_dss_dsi1_hwmod,
4320 .clk = "dss_fck",
4321 .addr = omap44xx_dss_dsi1_dma_addrs,
4322 .user = OCP_USER_SDMA,
4323 };
4324
4325 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
4326 {
4327 .pa_start = 0x48044000,
4328 .pa_end = 0x480441ff,
4329 .flags = ADDR_TYPE_RT
4330 },
4331 { }
4332 };
4333
4334 /* l4_per -> dss_dsi1 */
4335 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
4336 .master = &omap44xx_l4_per_hwmod,
4337 .slave = &omap44xx_dss_dsi1_hwmod,
4338 .clk = "l4_div_ck",
4339 .addr = omap44xx_dss_dsi1_addrs,
4340 .user = OCP_USER_MPU,
4341 };
4342
4343 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
4344 {
4345 .pa_start = 0x58005000,
4346 .pa_end = 0x580051ff,
4347 .flags = ADDR_TYPE_RT
4348 },
4349 { }
4350 };
4351
4352 /* l3_main_2 -> dss_dsi2 */
4353 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
4354 .master = &omap44xx_l3_main_2_hwmod,
4355 .slave = &omap44xx_dss_dsi2_hwmod,
4356 .clk = "dss_fck",
4357 .addr = omap44xx_dss_dsi2_dma_addrs,
4358 .user = OCP_USER_SDMA,
4359 };
4360
4361 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
4362 {
4363 .pa_start = 0x48045000,
4364 .pa_end = 0x480451ff,
4365 .flags = ADDR_TYPE_RT
4366 },
4367 { }
4368 };
4369
4370 /* l4_per -> dss_dsi2 */
4371 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
4372 .master = &omap44xx_l4_per_hwmod,
4373 .slave = &omap44xx_dss_dsi2_hwmod,
4374 .clk = "l4_div_ck",
4375 .addr = omap44xx_dss_dsi2_addrs,
4376 .user = OCP_USER_MPU,
4377 };
4378
4379 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
4380 {
4381 .pa_start = 0x58006000,
4382 .pa_end = 0x58006fff,
4383 .flags = ADDR_TYPE_RT
4384 },
4385 { }
4386 };
4387
4388 /* l3_main_2 -> dss_hdmi */
4389 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
4390 .master = &omap44xx_l3_main_2_hwmod,
4391 .slave = &omap44xx_dss_hdmi_hwmod,
4392 .clk = "dss_fck",
4393 .addr = omap44xx_dss_hdmi_dma_addrs,
4394 .user = OCP_USER_SDMA,
4395 };
4396
4397 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
4398 {
4399 .pa_start = 0x48046000,
4400 .pa_end = 0x48046fff,
4401 .flags = ADDR_TYPE_RT
4402 },
4403 { }
4404 };
4405
4406 /* l4_per -> dss_hdmi */
4407 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
4408 .master = &omap44xx_l4_per_hwmod,
4409 .slave = &omap44xx_dss_hdmi_hwmod,
4410 .clk = "l4_div_ck",
4411 .addr = omap44xx_dss_hdmi_addrs,
4412 .user = OCP_USER_MPU,
4413 };
4414
4415 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
4416 {
4417 .pa_start = 0x58002000,
4418 .pa_end = 0x580020ff,
4419 .flags = ADDR_TYPE_RT
4420 },
4421 { }
4422 };
4423
4424 /* l3_main_2 -> dss_rfbi */
4425 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
4426 .master = &omap44xx_l3_main_2_hwmod,
4427 .slave = &omap44xx_dss_rfbi_hwmod,
4428 .clk = "dss_fck",
4429 .addr = omap44xx_dss_rfbi_dma_addrs,
4430 .user = OCP_USER_SDMA,
4431 };
4432
4433 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
4434 {
4435 .pa_start = 0x48042000,
4436 .pa_end = 0x480420ff,
4437 .flags = ADDR_TYPE_RT
4438 },
4439 { }
4440 };
4441
4442 /* l4_per -> dss_rfbi */
4443 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
4444 .master = &omap44xx_l4_per_hwmod,
4445 .slave = &omap44xx_dss_rfbi_hwmod,
4446 .clk = "l4_div_ck",
4447 .addr = omap44xx_dss_rfbi_addrs,
4448 .user = OCP_USER_MPU,
4449 };
4450
4451 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
4452 {
4453 .pa_start = 0x58003000,
4454 .pa_end = 0x580030ff,
4455 .flags = ADDR_TYPE_RT
4456 },
4457 { }
4458 };
4459
4460 /* l3_main_2 -> dss_venc */
4461 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
4462 .master = &omap44xx_l3_main_2_hwmod,
4463 .slave = &omap44xx_dss_venc_hwmod,
4464 .clk = "dss_fck",
4465 .addr = omap44xx_dss_venc_dma_addrs,
4466 .user = OCP_USER_SDMA,
4467 };
4468
4469 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
4470 {
4471 .pa_start = 0x48043000,
4472 .pa_end = 0x480430ff,
4473 .flags = ADDR_TYPE_RT
4474 },
4475 { }
4476 };
4477
4478 /* l4_per -> dss_venc */
4479 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
4480 .master = &omap44xx_l4_per_hwmod,
4481 .slave = &omap44xx_dss_venc_hwmod,
4482 .clk = "l4_div_ck",
4483 .addr = omap44xx_dss_venc_addrs,
4484 .user = OCP_USER_MPU,
4485 };
4486
4487 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
4488 {
4489 .pa_start = 0x48078000,
4490 .pa_end = 0x48078fff,
4491 .flags = ADDR_TYPE_RT
4492 },
4493 { }
4494 };
4495
4496 /* l4_per -> elm */
4497 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
4498 .master = &omap44xx_l4_per_hwmod,
4499 .slave = &omap44xx_elm_hwmod,
4500 .clk = "l4_div_ck",
4501 .addr = omap44xx_elm_addrs,
4502 .user = OCP_USER_MPU | OCP_USER_SDMA,
4503 };
4504
4505 static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
4506 {
4507 .pa_start = 0x4c000000,
4508 .pa_end = 0x4c0000ff,
4509 .flags = ADDR_TYPE_RT
4510 },
4511 { }
4512 };
4513
4514 /* emif_fw -> emif1 */
4515 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
4516 .master = &omap44xx_emif_fw_hwmod,
4517 .slave = &omap44xx_emif1_hwmod,
4518 .clk = "l3_div_ck",
4519 .addr = omap44xx_emif1_addrs,
4520 .user = OCP_USER_MPU | OCP_USER_SDMA,
4521 };
4522
4523 static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
4524 {
4525 .pa_start = 0x4d000000,
4526 .pa_end = 0x4d0000ff,
4527 .flags = ADDR_TYPE_RT
4528 },
4529 { }
4530 };
4531
4532 /* emif_fw -> emif2 */
4533 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
4534 .master = &omap44xx_emif_fw_hwmod,
4535 .slave = &omap44xx_emif2_hwmod,
4536 .clk = "l3_div_ck",
4537 .addr = omap44xx_emif2_addrs,
4538 .user = OCP_USER_MPU | OCP_USER_SDMA,
4539 };
4540
4541 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
4542 {
4543 .pa_start = 0x4a10a000,
4544 .pa_end = 0x4a10a1ff,
4545 .flags = ADDR_TYPE_RT
4546 },
4547 { }
4548 };
4549
4550 /* l4_cfg -> fdif */
4551 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
4552 .master = &omap44xx_l4_cfg_hwmod,
4553 .slave = &omap44xx_fdif_hwmod,
4554 .clk = "l4_div_ck",
4555 .addr = omap44xx_fdif_addrs,
4556 .user = OCP_USER_MPU | OCP_USER_SDMA,
4557 };
4558
4559 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
4560 {
4561 .pa_start = 0x4a310000,
4562 .pa_end = 0x4a3101ff,
4563 .flags = ADDR_TYPE_RT
4564 },
4565 { }
4566 };
4567
4568 /* l4_wkup -> gpio1 */
4569 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
4570 .master = &omap44xx_l4_wkup_hwmod,
4571 .slave = &omap44xx_gpio1_hwmod,
4572 .clk = "l4_wkup_clk_mux_ck",
4573 .addr = omap44xx_gpio1_addrs,
4574 .user = OCP_USER_MPU | OCP_USER_SDMA,
4575 };
4576
4577 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
4578 {
4579 .pa_start = 0x48055000,
4580 .pa_end = 0x480551ff,
4581 .flags = ADDR_TYPE_RT
4582 },
4583 { }
4584 };
4585
4586 /* l4_per -> gpio2 */
4587 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
4588 .master = &omap44xx_l4_per_hwmod,
4589 .slave = &omap44xx_gpio2_hwmod,
4590 .clk = "l4_div_ck",
4591 .addr = omap44xx_gpio2_addrs,
4592 .user = OCP_USER_MPU | OCP_USER_SDMA,
4593 };
4594
4595 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
4596 {
4597 .pa_start = 0x48057000,
4598 .pa_end = 0x480571ff,
4599 .flags = ADDR_TYPE_RT
4600 },
4601 { }
4602 };
4603
4604 /* l4_per -> gpio3 */
4605 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
4606 .master = &omap44xx_l4_per_hwmod,
4607 .slave = &omap44xx_gpio3_hwmod,
4608 .clk = "l4_div_ck",
4609 .addr = omap44xx_gpio3_addrs,
4610 .user = OCP_USER_MPU | OCP_USER_SDMA,
4611 };
4612
4613 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
4614 {
4615 .pa_start = 0x48059000,
4616 .pa_end = 0x480591ff,
4617 .flags = ADDR_TYPE_RT
4618 },
4619 { }
4620 };
4621
4622 /* l4_per -> gpio4 */
4623 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
4624 .master = &omap44xx_l4_per_hwmod,
4625 .slave = &omap44xx_gpio4_hwmod,
4626 .clk = "l4_div_ck",
4627 .addr = omap44xx_gpio4_addrs,
4628 .user = OCP_USER_MPU | OCP_USER_SDMA,
4629 };
4630
4631 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
4632 {
4633 .pa_start = 0x4805b000,
4634 .pa_end = 0x4805b1ff,
4635 .flags = ADDR_TYPE_RT
4636 },
4637 { }
4638 };
4639
4640 /* l4_per -> gpio5 */
4641 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
4642 .master = &omap44xx_l4_per_hwmod,
4643 .slave = &omap44xx_gpio5_hwmod,
4644 .clk = "l4_div_ck",
4645 .addr = omap44xx_gpio5_addrs,
4646 .user = OCP_USER_MPU | OCP_USER_SDMA,
4647 };
4648
4649 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
4650 {
4651 .pa_start = 0x4805d000,
4652 .pa_end = 0x4805d1ff,
4653 .flags = ADDR_TYPE_RT
4654 },
4655 { }
4656 };
4657
4658 /* l4_per -> gpio6 */
4659 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4660 .master = &omap44xx_l4_per_hwmod,
4661 .slave = &omap44xx_gpio6_hwmod,
4662 .clk = "l4_div_ck",
4663 .addr = omap44xx_gpio6_addrs,
4664 .user = OCP_USER_MPU | OCP_USER_SDMA,
4665 };
4666
4667 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
4668 {
4669 .pa_start = 0x50000000,
4670 .pa_end = 0x500003ff,
4671 .flags = ADDR_TYPE_RT
4672 },
4673 { }
4674 };
4675
4676 /* l3_main_2 -> gpmc */
4677 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4678 .master = &omap44xx_l3_main_2_hwmod,
4679 .slave = &omap44xx_gpmc_hwmod,
4680 .clk = "l3_div_ck",
4681 .addr = omap44xx_gpmc_addrs,
4682 .user = OCP_USER_MPU | OCP_USER_SDMA,
4683 };
4684
4685 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4686 {
4687 .pa_start = 0x56000000,
4688 .pa_end = 0x5600ffff,
4689 .flags = ADDR_TYPE_RT
4690 },
4691 { }
4692 };
4693
4694 /* l3_main_2 -> gpu */
4695 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4696 .master = &omap44xx_l3_main_2_hwmod,
4697 .slave = &omap44xx_gpu_hwmod,
4698 .clk = "l3_div_ck",
4699 .addr = omap44xx_gpu_addrs,
4700 .user = OCP_USER_MPU | OCP_USER_SDMA,
4701 };
4702
4703 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4704 {
4705 .pa_start = 0x480b2000,
4706 .pa_end = 0x480b201f,
4707 .flags = ADDR_TYPE_RT
4708 },
4709 { }
4710 };
4711
4712 /* l4_per -> hdq1w */
4713 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4714 .master = &omap44xx_l4_per_hwmod,
4715 .slave = &omap44xx_hdq1w_hwmod,
4716 .clk = "l4_div_ck",
4717 .addr = omap44xx_hdq1w_addrs,
4718 .user = OCP_USER_MPU | OCP_USER_SDMA,
4719 };
4720
4721 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4722 {
4723 .pa_start = 0x4a058000,
4724 .pa_end = 0x4a05bfff,
4725 .flags = ADDR_TYPE_RT
4726 },
4727 { }
4728 };
4729
4730 /* l4_cfg -> hsi */
4731 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4732 .master = &omap44xx_l4_cfg_hwmod,
4733 .slave = &omap44xx_hsi_hwmod,
4734 .clk = "l4_div_ck",
4735 .addr = omap44xx_hsi_addrs,
4736 .user = OCP_USER_MPU | OCP_USER_SDMA,
4737 };
4738
4739 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
4740 {
4741 .pa_start = 0x48070000,
4742 .pa_end = 0x480700ff,
4743 .flags = ADDR_TYPE_RT
4744 },
4745 { }
4746 };
4747
4748 /* l4_per -> i2c1 */
4749 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4750 .master = &omap44xx_l4_per_hwmod,
4751 .slave = &omap44xx_i2c1_hwmod,
4752 .clk = "l4_div_ck",
4753 .addr = omap44xx_i2c1_addrs,
4754 .user = OCP_USER_MPU | OCP_USER_SDMA,
4755 };
4756
4757 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
4758 {
4759 .pa_start = 0x48072000,
4760 .pa_end = 0x480720ff,
4761 .flags = ADDR_TYPE_RT
4762 },
4763 { }
4764 };
4765
4766 /* l4_per -> i2c2 */
4767 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
4768 .master = &omap44xx_l4_per_hwmod,
4769 .slave = &omap44xx_i2c2_hwmod,
4770 .clk = "l4_div_ck",
4771 .addr = omap44xx_i2c2_addrs,
4772 .user = OCP_USER_MPU | OCP_USER_SDMA,
4773 };
4774
4775 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
4776 {
4777 .pa_start = 0x48060000,
4778 .pa_end = 0x480600ff,
4779 .flags = ADDR_TYPE_RT
4780 },
4781 { }
4782 };
4783
4784 /* l4_per -> i2c3 */
4785 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
4786 .master = &omap44xx_l4_per_hwmod,
4787 .slave = &omap44xx_i2c3_hwmod,
4788 .clk = "l4_div_ck",
4789 .addr = omap44xx_i2c3_addrs,
4790 .user = OCP_USER_MPU | OCP_USER_SDMA,
4791 };
4792
4793 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
4794 {
4795 .pa_start = 0x48350000,
4796 .pa_end = 0x483500ff,
4797 .flags = ADDR_TYPE_RT
4798 },
4799 { }
4800 };
4801
4802 /* l4_per -> i2c4 */
4803 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
4804 .master = &omap44xx_l4_per_hwmod,
4805 .slave = &omap44xx_i2c4_hwmod,
4806 .clk = "l4_div_ck",
4807 .addr = omap44xx_i2c4_addrs,
4808 .user = OCP_USER_MPU | OCP_USER_SDMA,
4809 };
4810
4811 /* l3_main_2 -> ipu */
4812 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
4813 .master = &omap44xx_l3_main_2_hwmod,
4814 .slave = &omap44xx_ipu_hwmod,
4815 .clk = "l3_div_ck",
4816 .user = OCP_USER_MPU | OCP_USER_SDMA,
4817 };
4818
4819 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
4820 {
4821 .pa_start = 0x52000000,
4822 .pa_end = 0x520000ff,
4823 .flags = ADDR_TYPE_RT
4824 },
4825 { }
4826 };
4827
4828 /* l3_main_2 -> iss */
4829 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
4830 .master = &omap44xx_l3_main_2_hwmod,
4831 .slave = &omap44xx_iss_hwmod,
4832 .clk = "l3_div_ck",
4833 .addr = omap44xx_iss_addrs,
4834 .user = OCP_USER_MPU | OCP_USER_SDMA,
4835 };
4836
4837 /* iva -> sl2if */
4838 static struct omap_hwmod_ocp_if omap44xx_iva__sl2if = {
4839 .master = &omap44xx_iva_hwmod,
4840 .slave = &omap44xx_sl2if_hwmod,
4841 .clk = "dpll_iva_m5x2_ck",
4842 .user = OCP_USER_IVA,
4843 };
4844
4845 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
4846 {
4847 .pa_start = 0x5a000000,
4848 .pa_end = 0x5a07ffff,
4849 .flags = ADDR_TYPE_RT
4850 },
4851 { }
4852 };
4853
4854 /* l3_main_2 -> iva */
4855 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
4856 .master = &omap44xx_l3_main_2_hwmod,
4857 .slave = &omap44xx_iva_hwmod,
4858 .clk = "l3_div_ck",
4859 .addr = omap44xx_iva_addrs,
4860 .user = OCP_USER_MPU,
4861 };
4862
4863 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
4864 {
4865 .pa_start = 0x4a31c000,
4866 .pa_end = 0x4a31c07f,
4867 .flags = ADDR_TYPE_RT
4868 },
4869 { }
4870 };
4871
4872 /* l4_wkup -> kbd */
4873 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
4874 .master = &omap44xx_l4_wkup_hwmod,
4875 .slave = &omap44xx_kbd_hwmod,
4876 .clk = "l4_wkup_clk_mux_ck",
4877 .addr = omap44xx_kbd_addrs,
4878 .user = OCP_USER_MPU | OCP_USER_SDMA,
4879 };
4880
4881 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
4882 {
4883 .pa_start = 0x4a0f4000,
4884 .pa_end = 0x4a0f41ff,
4885 .flags = ADDR_TYPE_RT
4886 },
4887 { }
4888 };
4889
4890 /* l4_cfg -> mailbox */
4891 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
4892 .master = &omap44xx_l4_cfg_hwmod,
4893 .slave = &omap44xx_mailbox_hwmod,
4894 .clk = "l4_div_ck",
4895 .addr = omap44xx_mailbox_addrs,
4896 .user = OCP_USER_MPU | OCP_USER_SDMA,
4897 };
4898
4899 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
4900 {
4901 .pa_start = 0x40128000,
4902 .pa_end = 0x401283ff,
4903 .flags = ADDR_TYPE_RT
4904 },
4905 { }
4906 };
4907
4908 /* l4_abe -> mcasp */
4909 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
4910 .master = &omap44xx_l4_abe_hwmod,
4911 .slave = &omap44xx_mcasp_hwmod,
4912 .clk = "ocp_abe_iclk",
4913 .addr = omap44xx_mcasp_addrs,
4914 .user = OCP_USER_MPU,
4915 };
4916
4917 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
4918 {
4919 .pa_start = 0x49028000,
4920 .pa_end = 0x490283ff,
4921 .flags = ADDR_TYPE_RT
4922 },
4923 { }
4924 };
4925
4926 /* l4_abe -> mcasp (dma) */
4927 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
4928 .master = &omap44xx_l4_abe_hwmod,
4929 .slave = &omap44xx_mcasp_hwmod,
4930 .clk = "ocp_abe_iclk",
4931 .addr = omap44xx_mcasp_dma_addrs,
4932 .user = OCP_USER_SDMA,
4933 };
4934
4935 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
4936 {
4937 .name = "mpu",
4938 .pa_start = 0x40122000,
4939 .pa_end = 0x401220ff,
4940 .flags = ADDR_TYPE_RT
4941 },
4942 { }
4943 };
4944
4945 /* l4_abe -> mcbsp1 */
4946 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
4947 .master = &omap44xx_l4_abe_hwmod,
4948 .slave = &omap44xx_mcbsp1_hwmod,
4949 .clk = "ocp_abe_iclk",
4950 .addr = omap44xx_mcbsp1_addrs,
4951 .user = OCP_USER_MPU,
4952 };
4953
4954 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
4955 {
4956 .name = "dma",
4957 .pa_start = 0x49022000,
4958 .pa_end = 0x490220ff,
4959 .flags = ADDR_TYPE_RT
4960 },
4961 { }
4962 };
4963
4964 /* l4_abe -> mcbsp1 (dma) */
4965 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
4966 .master = &omap44xx_l4_abe_hwmod,
4967 .slave = &omap44xx_mcbsp1_hwmod,
4968 .clk = "ocp_abe_iclk",
4969 .addr = omap44xx_mcbsp1_dma_addrs,
4970 .user = OCP_USER_SDMA,
4971 };
4972
4973 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
4974 {
4975 .name = "mpu",
4976 .pa_start = 0x40124000,
4977 .pa_end = 0x401240ff,
4978 .flags = ADDR_TYPE_RT
4979 },
4980 { }
4981 };
4982
4983 /* l4_abe -> mcbsp2 */
4984 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
4985 .master = &omap44xx_l4_abe_hwmod,
4986 .slave = &omap44xx_mcbsp2_hwmod,
4987 .clk = "ocp_abe_iclk",
4988 .addr = omap44xx_mcbsp2_addrs,
4989 .user = OCP_USER_MPU,
4990 };
4991
4992 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
4993 {
4994 .name = "dma",
4995 .pa_start = 0x49024000,
4996 .pa_end = 0x490240ff,
4997 .flags = ADDR_TYPE_RT
4998 },
4999 { }
5000 };
5001
5002 /* l4_abe -> mcbsp2 (dma) */
5003 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
5004 .master = &omap44xx_l4_abe_hwmod,
5005 .slave = &omap44xx_mcbsp2_hwmod,
5006 .clk = "ocp_abe_iclk",
5007 .addr = omap44xx_mcbsp2_dma_addrs,
5008 .user = OCP_USER_SDMA,
5009 };
5010
5011 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
5012 {
5013 .name = "mpu",
5014 .pa_start = 0x40126000,
5015 .pa_end = 0x401260ff,
5016 .flags = ADDR_TYPE_RT
5017 },
5018 { }
5019 };
5020
5021 /* l4_abe -> mcbsp3 */
5022 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
5023 .master = &omap44xx_l4_abe_hwmod,
5024 .slave = &omap44xx_mcbsp3_hwmod,
5025 .clk = "ocp_abe_iclk",
5026 .addr = omap44xx_mcbsp3_addrs,
5027 .user = OCP_USER_MPU,
5028 };
5029
5030 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
5031 {
5032 .name = "dma",
5033 .pa_start = 0x49026000,
5034 .pa_end = 0x490260ff,
5035 .flags = ADDR_TYPE_RT
5036 },
5037 { }
5038 };
5039
5040 /* l4_abe -> mcbsp3 (dma) */
5041 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
5042 .master = &omap44xx_l4_abe_hwmod,
5043 .slave = &omap44xx_mcbsp3_hwmod,
5044 .clk = "ocp_abe_iclk",
5045 .addr = omap44xx_mcbsp3_dma_addrs,
5046 .user = OCP_USER_SDMA,
5047 };
5048
5049 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
5050 {
5051 .pa_start = 0x48096000,
5052 .pa_end = 0x480960ff,
5053 .flags = ADDR_TYPE_RT
5054 },
5055 { }
5056 };
5057
5058 /* l4_per -> mcbsp4 */
5059 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
5060 .master = &omap44xx_l4_per_hwmod,
5061 .slave = &omap44xx_mcbsp4_hwmod,
5062 .clk = "l4_div_ck",
5063 .addr = omap44xx_mcbsp4_addrs,
5064 .user = OCP_USER_MPU | OCP_USER_SDMA,
5065 };
5066
5067 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
5068 {
5069 .pa_start = 0x40132000,
5070 .pa_end = 0x4013207f,
5071 .flags = ADDR_TYPE_RT
5072 },
5073 { }
5074 };
5075
5076 /* l4_abe -> mcpdm */
5077 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
5078 .master = &omap44xx_l4_abe_hwmod,
5079 .slave = &omap44xx_mcpdm_hwmod,
5080 .clk = "ocp_abe_iclk",
5081 .addr = omap44xx_mcpdm_addrs,
5082 .user = OCP_USER_MPU,
5083 };
5084
5085 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
5086 {
5087 .pa_start = 0x49032000,
5088 .pa_end = 0x4903207f,
5089 .flags = ADDR_TYPE_RT
5090 },
5091 { }
5092 };
5093
5094 /* l4_abe -> mcpdm (dma) */
5095 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
5096 .master = &omap44xx_l4_abe_hwmod,
5097 .slave = &omap44xx_mcpdm_hwmod,
5098 .clk = "ocp_abe_iclk",
5099 .addr = omap44xx_mcpdm_dma_addrs,
5100 .user = OCP_USER_SDMA,
5101 };
5102
5103 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
5104 {
5105 .pa_start = 0x48098000,
5106 .pa_end = 0x480981ff,
5107 .flags = ADDR_TYPE_RT
5108 },
5109 { }
5110 };
5111
5112 /* l4_per -> mcspi1 */
5113 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
5114 .master = &omap44xx_l4_per_hwmod,
5115 .slave = &omap44xx_mcspi1_hwmod,
5116 .clk = "l4_div_ck",
5117 .addr = omap44xx_mcspi1_addrs,
5118 .user = OCP_USER_MPU | OCP_USER_SDMA,
5119 };
5120
5121 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
5122 {
5123 .pa_start = 0x4809a000,
5124 .pa_end = 0x4809a1ff,
5125 .flags = ADDR_TYPE_RT
5126 },
5127 { }
5128 };
5129
5130 /* l4_per -> mcspi2 */
5131 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
5132 .master = &omap44xx_l4_per_hwmod,
5133 .slave = &omap44xx_mcspi2_hwmod,
5134 .clk = "l4_div_ck",
5135 .addr = omap44xx_mcspi2_addrs,
5136 .user = OCP_USER_MPU | OCP_USER_SDMA,
5137 };
5138
5139 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
5140 {
5141 .pa_start = 0x480b8000,
5142 .pa_end = 0x480b81ff,
5143 .flags = ADDR_TYPE_RT
5144 },
5145 { }
5146 };
5147
5148 /* l4_per -> mcspi3 */
5149 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
5150 .master = &omap44xx_l4_per_hwmod,
5151 .slave = &omap44xx_mcspi3_hwmod,
5152 .clk = "l4_div_ck",
5153 .addr = omap44xx_mcspi3_addrs,
5154 .user = OCP_USER_MPU | OCP_USER_SDMA,
5155 };
5156
5157 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
5158 {
5159 .pa_start = 0x480ba000,
5160 .pa_end = 0x480ba1ff,
5161 .flags = ADDR_TYPE_RT
5162 },
5163 { }
5164 };
5165
5166 /* l4_per -> mcspi4 */
5167 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
5168 .master = &omap44xx_l4_per_hwmod,
5169 .slave = &omap44xx_mcspi4_hwmod,
5170 .clk = "l4_div_ck",
5171 .addr = omap44xx_mcspi4_addrs,
5172 .user = OCP_USER_MPU | OCP_USER_SDMA,
5173 };
5174
5175 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
5176 {
5177 .pa_start = 0x4809c000,
5178 .pa_end = 0x4809c3ff,
5179 .flags = ADDR_TYPE_RT
5180 },
5181 { }
5182 };
5183
5184 /* l4_per -> mmc1 */
5185 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
5186 .master = &omap44xx_l4_per_hwmod,
5187 .slave = &omap44xx_mmc1_hwmod,
5188 .clk = "l4_div_ck",
5189 .addr = omap44xx_mmc1_addrs,
5190 .user = OCP_USER_MPU | OCP_USER_SDMA,
5191 };
5192
5193 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
5194 {
5195 .pa_start = 0x480b4000,
5196 .pa_end = 0x480b43ff,
5197 .flags = ADDR_TYPE_RT
5198 },
5199 { }
5200 };
5201
5202 /* l4_per -> mmc2 */
5203 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
5204 .master = &omap44xx_l4_per_hwmod,
5205 .slave = &omap44xx_mmc2_hwmod,
5206 .clk = "l4_div_ck",
5207 .addr = omap44xx_mmc2_addrs,
5208 .user = OCP_USER_MPU | OCP_USER_SDMA,
5209 };
5210
5211 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
5212 {
5213 .pa_start = 0x480ad000,
5214 .pa_end = 0x480ad3ff,
5215 .flags = ADDR_TYPE_RT
5216 },
5217 { }
5218 };
5219
5220 /* l4_per -> mmc3 */
5221 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
5222 .master = &omap44xx_l4_per_hwmod,
5223 .slave = &omap44xx_mmc3_hwmod,
5224 .clk = "l4_div_ck",
5225 .addr = omap44xx_mmc3_addrs,
5226 .user = OCP_USER_MPU | OCP_USER_SDMA,
5227 };
5228
5229 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
5230 {
5231 .pa_start = 0x480d1000,
5232 .pa_end = 0x480d13ff,
5233 .flags = ADDR_TYPE_RT
5234 },
5235 { }
5236 };
5237
5238 /* l4_per -> mmc4 */
5239 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
5240 .master = &omap44xx_l4_per_hwmod,
5241 .slave = &omap44xx_mmc4_hwmod,
5242 .clk = "l4_div_ck",
5243 .addr = omap44xx_mmc4_addrs,
5244 .user = OCP_USER_MPU | OCP_USER_SDMA,
5245 };
5246
5247 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
5248 {
5249 .pa_start = 0x480d5000,
5250 .pa_end = 0x480d53ff,
5251 .flags = ADDR_TYPE_RT
5252 },
5253 { }
5254 };
5255
5256 /* l4_per -> mmc5 */
5257 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
5258 .master = &omap44xx_l4_per_hwmod,
5259 .slave = &omap44xx_mmc5_hwmod,
5260 .clk = "l4_div_ck",
5261 .addr = omap44xx_mmc5_addrs,
5262 .user = OCP_USER_MPU | OCP_USER_SDMA,
5263 };
5264
5265 /* l3_main_2 -> ocmc_ram */
5266 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
5267 .master = &omap44xx_l3_main_2_hwmod,
5268 .slave = &omap44xx_ocmc_ram_hwmod,
5269 .clk = "l3_div_ck",
5270 .user = OCP_USER_MPU | OCP_USER_SDMA,
5271 };
5272
5273 /* l4_cfg -> ocp2scp_usb_phy */
5274 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
5275 .master = &omap44xx_l4_cfg_hwmod,
5276 .slave = &omap44xx_ocp2scp_usb_phy_hwmod,
5277 .clk = "l4_div_ck",
5278 .user = OCP_USER_MPU | OCP_USER_SDMA,
5279 };
5280
5281 static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
5282 {
5283 .pa_start = 0x48243000,
5284 .pa_end = 0x48243fff,
5285 .flags = ADDR_TYPE_RT
5286 },
5287 { }
5288 };
5289
5290 /* mpu_private -> prcm_mpu */
5291 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
5292 .master = &omap44xx_mpu_private_hwmod,
5293 .slave = &omap44xx_prcm_mpu_hwmod,
5294 .clk = "l3_div_ck",
5295 .addr = omap44xx_prcm_mpu_addrs,
5296 .user = OCP_USER_MPU | OCP_USER_SDMA,
5297 };
5298
5299 static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
5300 {
5301 .pa_start = 0x4a004000,
5302 .pa_end = 0x4a004fff,
5303 .flags = ADDR_TYPE_RT
5304 },
5305 { }
5306 };
5307
5308 /* l4_wkup -> cm_core_aon */
5309 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
5310 .master = &omap44xx_l4_wkup_hwmod,
5311 .slave = &omap44xx_cm_core_aon_hwmod,
5312 .clk = "l4_wkup_clk_mux_ck",
5313 .addr = omap44xx_cm_core_aon_addrs,
5314 .user = OCP_USER_MPU | OCP_USER_SDMA,
5315 };
5316
5317 static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
5318 {
5319 .pa_start = 0x4a008000,
5320 .pa_end = 0x4a009fff,
5321 .flags = ADDR_TYPE_RT
5322 },
5323 { }
5324 };
5325
5326 /* l4_cfg -> cm_core */
5327 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
5328 .master = &omap44xx_l4_cfg_hwmod,
5329 .slave = &omap44xx_cm_core_hwmod,
5330 .clk = "l4_div_ck",
5331 .addr = omap44xx_cm_core_addrs,
5332 .user = OCP_USER_MPU | OCP_USER_SDMA,
5333 };
5334
5335 static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
5336 {
5337 .pa_start = 0x4a306000,
5338 .pa_end = 0x4a307fff,
5339 .flags = ADDR_TYPE_RT
5340 },
5341 { }
5342 };
5343
5344 /* l4_wkup -> prm */
5345 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
5346 .master = &omap44xx_l4_wkup_hwmod,
5347 .slave = &omap44xx_prm_hwmod,
5348 .clk = "l4_wkup_clk_mux_ck",
5349 .addr = omap44xx_prm_addrs,
5350 .user = OCP_USER_MPU | OCP_USER_SDMA,
5351 };
5352
5353 static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
5354 {
5355 .pa_start = 0x4a30a000,
5356 .pa_end = 0x4a30a7ff,
5357 .flags = ADDR_TYPE_RT
5358 },
5359 { }
5360 };
5361
5362 /* l4_wkup -> scrm */
5363 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
5364 .master = &omap44xx_l4_wkup_hwmod,
5365 .slave = &omap44xx_scrm_hwmod,
5366 .clk = "l4_wkup_clk_mux_ck",
5367 .addr = omap44xx_scrm_addrs,
5368 .user = OCP_USER_MPU | OCP_USER_SDMA,
5369 };
5370
5371 /* l3_main_2 -> sl2if */
5372 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sl2if = {
5373 .master = &omap44xx_l3_main_2_hwmod,
5374 .slave = &omap44xx_sl2if_hwmod,
5375 .clk = "l3_div_ck",
5376 .user = OCP_USER_MPU | OCP_USER_SDMA,
5377 };
5378
5379 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
5380 {
5381 .pa_start = 0x4012c000,
5382 .pa_end = 0x4012c3ff,
5383 .flags = ADDR_TYPE_RT
5384 },
5385 { }
5386 };
5387
5388 /* l4_abe -> slimbus1 */
5389 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
5390 .master = &omap44xx_l4_abe_hwmod,
5391 .slave = &omap44xx_slimbus1_hwmod,
5392 .clk = "ocp_abe_iclk",
5393 .addr = omap44xx_slimbus1_addrs,
5394 .user = OCP_USER_MPU,
5395 };
5396
5397 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
5398 {
5399 .pa_start = 0x4902c000,
5400 .pa_end = 0x4902c3ff,
5401 .flags = ADDR_TYPE_RT
5402 },
5403 { }
5404 };
5405
5406 /* l4_abe -> slimbus1 (dma) */
5407 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
5408 .master = &omap44xx_l4_abe_hwmod,
5409 .slave = &omap44xx_slimbus1_hwmod,
5410 .clk = "ocp_abe_iclk",
5411 .addr = omap44xx_slimbus1_dma_addrs,
5412 .user = OCP_USER_SDMA,
5413 };
5414
5415 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
5416 {
5417 .pa_start = 0x48076000,
5418 .pa_end = 0x480763ff,
5419 .flags = ADDR_TYPE_RT
5420 },
5421 { }
5422 };
5423
5424 /* l4_per -> slimbus2 */
5425 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
5426 .master = &omap44xx_l4_per_hwmod,
5427 .slave = &omap44xx_slimbus2_hwmod,
5428 .clk = "l4_div_ck",
5429 .addr = omap44xx_slimbus2_addrs,
5430 .user = OCP_USER_MPU | OCP_USER_SDMA,
5431 };
5432
5433 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
5434 {
5435 .pa_start = 0x4a0dd000,
5436 .pa_end = 0x4a0dd03f,
5437 .flags = ADDR_TYPE_RT
5438 },
5439 { }
5440 };
5441
5442 /* l4_cfg -> smartreflex_core */
5443 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
5444 .master = &omap44xx_l4_cfg_hwmod,
5445 .slave = &omap44xx_smartreflex_core_hwmod,
5446 .clk = "l4_div_ck",
5447 .addr = omap44xx_smartreflex_core_addrs,
5448 .user = OCP_USER_MPU | OCP_USER_SDMA,
5449 };
5450
5451 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
5452 {
5453 .pa_start = 0x4a0db000,
5454 .pa_end = 0x4a0db03f,
5455 .flags = ADDR_TYPE_RT
5456 },
5457 { }
5458 };
5459
5460 /* l4_cfg -> smartreflex_iva */
5461 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
5462 .master = &omap44xx_l4_cfg_hwmod,
5463 .slave = &omap44xx_smartreflex_iva_hwmod,
5464 .clk = "l4_div_ck",
5465 .addr = omap44xx_smartreflex_iva_addrs,
5466 .user = OCP_USER_MPU | OCP_USER_SDMA,
5467 };
5468
5469 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
5470 {
5471 .pa_start = 0x4a0d9000,
5472 .pa_end = 0x4a0d903f,
5473 .flags = ADDR_TYPE_RT
5474 },
5475 { }
5476 };
5477
5478 /* l4_cfg -> smartreflex_mpu */
5479 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
5480 .master = &omap44xx_l4_cfg_hwmod,
5481 .slave = &omap44xx_smartreflex_mpu_hwmod,
5482 .clk = "l4_div_ck",
5483 .addr = omap44xx_smartreflex_mpu_addrs,
5484 .user = OCP_USER_MPU | OCP_USER_SDMA,
5485 };
5486
5487 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
5488 {
5489 .pa_start = 0x4a0f6000,
5490 .pa_end = 0x4a0f6fff,
5491 .flags = ADDR_TYPE_RT
5492 },
5493 { }
5494 };
5495
5496 /* l4_cfg -> spinlock */
5497 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
5498 .master = &omap44xx_l4_cfg_hwmod,
5499 .slave = &omap44xx_spinlock_hwmod,
5500 .clk = "l4_div_ck",
5501 .addr = omap44xx_spinlock_addrs,
5502 .user = OCP_USER_MPU | OCP_USER_SDMA,
5503 };
5504
5505 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
5506 {
5507 .pa_start = 0x4a318000,
5508 .pa_end = 0x4a31807f,
5509 .flags = ADDR_TYPE_RT
5510 },
5511 { }
5512 };
5513
5514 /* l4_wkup -> timer1 */
5515 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
5516 .master = &omap44xx_l4_wkup_hwmod,
5517 .slave = &omap44xx_timer1_hwmod,
5518 .clk = "l4_wkup_clk_mux_ck",
5519 .addr = omap44xx_timer1_addrs,
5520 .user = OCP_USER_MPU | OCP_USER_SDMA,
5521 };
5522
5523 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
5524 {
5525 .pa_start = 0x48032000,
5526 .pa_end = 0x4803207f,
5527 .flags = ADDR_TYPE_RT
5528 },
5529 { }
5530 };
5531
5532 /* l4_per -> timer2 */
5533 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
5534 .master = &omap44xx_l4_per_hwmod,
5535 .slave = &omap44xx_timer2_hwmod,
5536 .clk = "l4_div_ck",
5537 .addr = omap44xx_timer2_addrs,
5538 .user = OCP_USER_MPU | OCP_USER_SDMA,
5539 };
5540
5541 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
5542 {
5543 .pa_start = 0x48034000,
5544 .pa_end = 0x4803407f,
5545 .flags = ADDR_TYPE_RT
5546 },
5547 { }
5548 };
5549
5550 /* l4_per -> timer3 */
5551 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
5552 .master = &omap44xx_l4_per_hwmod,
5553 .slave = &omap44xx_timer3_hwmod,
5554 .clk = "l4_div_ck",
5555 .addr = omap44xx_timer3_addrs,
5556 .user = OCP_USER_MPU | OCP_USER_SDMA,
5557 };
5558
5559 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
5560 {
5561 .pa_start = 0x48036000,
5562 .pa_end = 0x4803607f,
5563 .flags = ADDR_TYPE_RT
5564 },
5565 { }
5566 };
5567
5568 /* l4_per -> timer4 */
5569 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
5570 .master = &omap44xx_l4_per_hwmod,
5571 .slave = &omap44xx_timer4_hwmod,
5572 .clk = "l4_div_ck",
5573 .addr = omap44xx_timer4_addrs,
5574 .user = OCP_USER_MPU | OCP_USER_SDMA,
5575 };
5576
5577 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
5578 {
5579 .pa_start = 0x40138000,
5580 .pa_end = 0x4013807f,
5581 .flags = ADDR_TYPE_RT
5582 },
5583 { }
5584 };
5585
5586 /* l4_abe -> timer5 */
5587 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
5588 .master = &omap44xx_l4_abe_hwmod,
5589 .slave = &omap44xx_timer5_hwmod,
5590 .clk = "ocp_abe_iclk",
5591 .addr = omap44xx_timer5_addrs,
5592 .user = OCP_USER_MPU,
5593 };
5594
5595 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
5596 {
5597 .pa_start = 0x49038000,
5598 .pa_end = 0x4903807f,
5599 .flags = ADDR_TYPE_RT
5600 },
5601 { }
5602 };
5603
5604 /* l4_abe -> timer5 (dma) */
5605 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
5606 .master = &omap44xx_l4_abe_hwmod,
5607 .slave = &omap44xx_timer5_hwmod,
5608 .clk = "ocp_abe_iclk",
5609 .addr = omap44xx_timer5_dma_addrs,
5610 .user = OCP_USER_SDMA,
5611 };
5612
5613 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
5614 {
5615 .pa_start = 0x4013a000,
5616 .pa_end = 0x4013a07f,
5617 .flags = ADDR_TYPE_RT
5618 },
5619 { }
5620 };
5621
5622 /* l4_abe -> timer6 */
5623 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
5624 .master = &omap44xx_l4_abe_hwmod,
5625 .slave = &omap44xx_timer6_hwmod,
5626 .clk = "ocp_abe_iclk",
5627 .addr = omap44xx_timer6_addrs,
5628 .user = OCP_USER_MPU,
5629 };
5630
5631 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
5632 {
5633 .pa_start = 0x4903a000,
5634 .pa_end = 0x4903a07f,
5635 .flags = ADDR_TYPE_RT
5636 },
5637 { }
5638 };
5639
5640 /* l4_abe -> timer6 (dma) */
5641 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
5642 .master = &omap44xx_l4_abe_hwmod,
5643 .slave = &omap44xx_timer6_hwmod,
5644 .clk = "ocp_abe_iclk",
5645 .addr = omap44xx_timer6_dma_addrs,
5646 .user = OCP_USER_SDMA,
5647 };
5648
5649 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
5650 {
5651 .pa_start = 0x4013c000,
5652 .pa_end = 0x4013c07f,
5653 .flags = ADDR_TYPE_RT
5654 },
5655 { }
5656 };
5657
5658 /* l4_abe -> timer7 */
5659 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
5660 .master = &omap44xx_l4_abe_hwmod,
5661 .slave = &omap44xx_timer7_hwmod,
5662 .clk = "ocp_abe_iclk",
5663 .addr = omap44xx_timer7_addrs,
5664 .user = OCP_USER_MPU,
5665 };
5666
5667 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
5668 {
5669 .pa_start = 0x4903c000,
5670 .pa_end = 0x4903c07f,
5671 .flags = ADDR_TYPE_RT
5672 },
5673 { }
5674 };
5675
5676 /* l4_abe -> timer7 (dma) */
5677 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
5678 .master = &omap44xx_l4_abe_hwmod,
5679 .slave = &omap44xx_timer7_hwmod,
5680 .clk = "ocp_abe_iclk",
5681 .addr = omap44xx_timer7_dma_addrs,
5682 .user = OCP_USER_SDMA,
5683 };
5684
5685 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
5686 {
5687 .pa_start = 0x4013e000,
5688 .pa_end = 0x4013e07f,
5689 .flags = ADDR_TYPE_RT
5690 },
5691 { }
5692 };
5693
5694 /* l4_abe -> timer8 */
5695 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
5696 .master = &omap44xx_l4_abe_hwmod,
5697 .slave = &omap44xx_timer8_hwmod,
5698 .clk = "ocp_abe_iclk",
5699 .addr = omap44xx_timer8_addrs,
5700 .user = OCP_USER_MPU,
5701 };
5702
5703 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
5704 {
5705 .pa_start = 0x4903e000,
5706 .pa_end = 0x4903e07f,
5707 .flags = ADDR_TYPE_RT
5708 },
5709 { }
5710 };
5711
5712 /* l4_abe -> timer8 (dma) */
5713 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
5714 .master = &omap44xx_l4_abe_hwmod,
5715 .slave = &omap44xx_timer8_hwmod,
5716 .clk = "ocp_abe_iclk",
5717 .addr = omap44xx_timer8_dma_addrs,
5718 .user = OCP_USER_SDMA,
5719 };
5720
5721 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
5722 {
5723 .pa_start = 0x4803e000,
5724 .pa_end = 0x4803e07f,
5725 .flags = ADDR_TYPE_RT
5726 },
5727 { }
5728 };
5729
5730 /* l4_per -> timer9 */
5731 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
5732 .master = &omap44xx_l4_per_hwmod,
5733 .slave = &omap44xx_timer9_hwmod,
5734 .clk = "l4_div_ck",
5735 .addr = omap44xx_timer9_addrs,
5736 .user = OCP_USER_MPU | OCP_USER_SDMA,
5737 };
5738
5739 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
5740 {
5741 .pa_start = 0x48086000,
5742 .pa_end = 0x4808607f,
5743 .flags = ADDR_TYPE_RT
5744 },
5745 { }
5746 };
5747
5748 /* l4_per -> timer10 */
5749 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
5750 .master = &omap44xx_l4_per_hwmod,
5751 .slave = &omap44xx_timer10_hwmod,
5752 .clk = "l4_div_ck",
5753 .addr = omap44xx_timer10_addrs,
5754 .user = OCP_USER_MPU | OCP_USER_SDMA,
5755 };
5756
5757 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
5758 {
5759 .pa_start = 0x48088000,
5760 .pa_end = 0x4808807f,
5761 .flags = ADDR_TYPE_RT
5762 },
5763 { }
5764 };
5765
5766 /* l4_per -> timer11 */
5767 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
5768 .master = &omap44xx_l4_per_hwmod,
5769 .slave = &omap44xx_timer11_hwmod,
5770 .clk = "l4_div_ck",
5771 .addr = omap44xx_timer11_addrs,
5772 .user = OCP_USER_MPU | OCP_USER_SDMA,
5773 };
5774
5775 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
5776 {
5777 .pa_start = 0x4806a000,
5778 .pa_end = 0x4806a0ff,
5779 .flags = ADDR_TYPE_RT
5780 },
5781 { }
5782 };
5783
5784 /* l4_per -> uart1 */
5785 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
5786 .master = &omap44xx_l4_per_hwmod,
5787 .slave = &omap44xx_uart1_hwmod,
5788 .clk = "l4_div_ck",
5789 .addr = omap44xx_uart1_addrs,
5790 .user = OCP_USER_MPU | OCP_USER_SDMA,
5791 };
5792
5793 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
5794 {
5795 .pa_start = 0x4806c000,
5796 .pa_end = 0x4806c0ff,
5797 .flags = ADDR_TYPE_RT
5798 },
5799 { }
5800 };
5801
5802 /* l4_per -> uart2 */
5803 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
5804 .master = &omap44xx_l4_per_hwmod,
5805 .slave = &omap44xx_uart2_hwmod,
5806 .clk = "l4_div_ck",
5807 .addr = omap44xx_uart2_addrs,
5808 .user = OCP_USER_MPU | OCP_USER_SDMA,
5809 };
5810
5811 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
5812 {
5813 .pa_start = 0x48020000,
5814 .pa_end = 0x480200ff,
5815 .flags = ADDR_TYPE_RT
5816 },
5817 { }
5818 };
5819
5820 /* l4_per -> uart3 */
5821 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
5822 .master = &omap44xx_l4_per_hwmod,
5823 .slave = &omap44xx_uart3_hwmod,
5824 .clk = "l4_div_ck",
5825 .addr = omap44xx_uart3_addrs,
5826 .user = OCP_USER_MPU | OCP_USER_SDMA,
5827 };
5828
5829 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
5830 {
5831 .pa_start = 0x4806e000,
5832 .pa_end = 0x4806e0ff,
5833 .flags = ADDR_TYPE_RT
5834 },
5835 { }
5836 };
5837
5838 /* l4_per -> uart4 */
5839 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
5840 .master = &omap44xx_l4_per_hwmod,
5841 .slave = &omap44xx_uart4_hwmod,
5842 .clk = "l4_div_ck",
5843 .addr = omap44xx_uart4_addrs,
5844 .user = OCP_USER_MPU | OCP_USER_SDMA,
5845 };
5846
5847 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
5848 {
5849 .pa_start = 0x4a0a9000,
5850 .pa_end = 0x4a0a93ff,
5851 .flags = ADDR_TYPE_RT
5852 },
5853 { }
5854 };
5855
5856 /* l4_cfg -> usb_host_fs */
5857 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_fs = {
5858 .master = &omap44xx_l4_cfg_hwmod,
5859 .slave = &omap44xx_usb_host_fs_hwmod,
5860 .clk = "l4_div_ck",
5861 .addr = omap44xx_usb_host_fs_addrs,
5862 .user = OCP_USER_MPU | OCP_USER_SDMA,
5863 };
5864
5865 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
5866 {
5867 .name = "uhh",
5868 .pa_start = 0x4a064000,
5869 .pa_end = 0x4a0647ff,
5870 .flags = ADDR_TYPE_RT
5871 },
5872 {
5873 .name = "ohci",
5874 .pa_start = 0x4a064800,
5875 .pa_end = 0x4a064bff,
5876 },
5877 {
5878 .name = "ehci",
5879 .pa_start = 0x4a064c00,
5880 .pa_end = 0x4a064fff,
5881 },
5882 {}
5883 };
5884
5885 /* l4_cfg -> usb_host_hs */
5886 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
5887 .master = &omap44xx_l4_cfg_hwmod,
5888 .slave = &omap44xx_usb_host_hs_hwmod,
5889 .clk = "l4_div_ck",
5890 .addr = omap44xx_usb_host_hs_addrs,
5891 .user = OCP_USER_MPU | OCP_USER_SDMA,
5892 };
5893
5894 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
5895 {
5896 .pa_start = 0x4a0ab000,
5897 .pa_end = 0x4a0ab003,
5898 .flags = ADDR_TYPE_RT
5899 },
5900 { }
5901 };
5902
5903 /* l4_cfg -> usb_otg_hs */
5904 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
5905 .master = &omap44xx_l4_cfg_hwmod,
5906 .slave = &omap44xx_usb_otg_hs_hwmod,
5907 .clk = "l4_div_ck",
5908 .addr = omap44xx_usb_otg_hs_addrs,
5909 .user = OCP_USER_MPU | OCP_USER_SDMA,
5910 };
5911
5912 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
5913 {
5914 .name = "tll",
5915 .pa_start = 0x4a062000,
5916 .pa_end = 0x4a063fff,
5917 .flags = ADDR_TYPE_RT
5918 },
5919 {}
5920 };
5921
5922 /* l4_cfg -> usb_tll_hs */
5923 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
5924 .master = &omap44xx_l4_cfg_hwmod,
5925 .slave = &omap44xx_usb_tll_hs_hwmod,
5926 .clk = "l4_div_ck",
5927 .addr = omap44xx_usb_tll_hs_addrs,
5928 .user = OCP_USER_MPU | OCP_USER_SDMA,
5929 };
5930
5931 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
5932 {
5933 .pa_start = 0x4a314000,
5934 .pa_end = 0x4a31407f,
5935 .flags = ADDR_TYPE_RT
5936 },
5937 { }
5938 };
5939
5940 /* l4_wkup -> wd_timer2 */
5941 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
5942 .master = &omap44xx_l4_wkup_hwmod,
5943 .slave = &omap44xx_wd_timer2_hwmod,
5944 .clk = "l4_wkup_clk_mux_ck",
5945 .addr = omap44xx_wd_timer2_addrs,
5946 .user = OCP_USER_MPU | OCP_USER_SDMA,
5947 };
5948
5949 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
5950 {
5951 .pa_start = 0x40130000,
5952 .pa_end = 0x4013007f,
5953 .flags = ADDR_TYPE_RT
5954 },
5955 { }
5956 };
5957
5958 /* l4_abe -> wd_timer3 */
5959 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
5960 .master = &omap44xx_l4_abe_hwmod,
5961 .slave = &omap44xx_wd_timer3_hwmod,
5962 .clk = "ocp_abe_iclk",
5963 .addr = omap44xx_wd_timer3_addrs,
5964 .user = OCP_USER_MPU,
5965 };
5966
5967 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
5968 {
5969 .pa_start = 0x49030000,
5970 .pa_end = 0x4903007f,
5971 .flags = ADDR_TYPE_RT
5972 },
5973 { }
5974 };
5975
5976 /* l4_abe -> wd_timer3 (dma) */
5977 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5978 .master = &omap44xx_l4_abe_hwmod,
5979 .slave = &omap44xx_wd_timer3_hwmod,
5980 .clk = "ocp_abe_iclk",
5981 .addr = omap44xx_wd_timer3_dma_addrs,
5982 .user = OCP_USER_SDMA,
5983 };
5984
5985 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
5986 &omap44xx_c2c__c2c_target_fw,
5987 &omap44xx_l4_cfg__c2c_target_fw,
5988 &omap44xx_l3_main_1__dmm,
5989 &omap44xx_mpu__dmm,
5990 &omap44xx_c2c__emif_fw,
5991 &omap44xx_dmm__emif_fw,
5992 &omap44xx_l4_cfg__emif_fw,
5993 &omap44xx_iva__l3_instr,
5994 &omap44xx_l3_main_3__l3_instr,
5995 &omap44xx_ocp_wp_noc__l3_instr,
5996 &omap44xx_dsp__l3_main_1,
5997 &omap44xx_dss__l3_main_1,
5998 &omap44xx_l3_main_2__l3_main_1,
5999 &omap44xx_l4_cfg__l3_main_1,
6000 &omap44xx_mmc1__l3_main_1,
6001 &omap44xx_mmc2__l3_main_1,
6002 &omap44xx_mpu__l3_main_1,
6003 &omap44xx_c2c_target_fw__l3_main_2,
6004 &omap44xx_debugss__l3_main_2,
6005 &omap44xx_dma_system__l3_main_2,
6006 &omap44xx_fdif__l3_main_2,
6007 &omap44xx_gpu__l3_main_2,
6008 &omap44xx_hsi__l3_main_2,
6009 &omap44xx_ipu__l3_main_2,
6010 &omap44xx_iss__l3_main_2,
6011 &omap44xx_iva__l3_main_2,
6012 &omap44xx_l3_main_1__l3_main_2,
6013 &omap44xx_l4_cfg__l3_main_2,
6014 &omap44xx_usb_host_fs__l3_main_2,
6015 &omap44xx_usb_host_hs__l3_main_2,
6016 &omap44xx_usb_otg_hs__l3_main_2,
6017 &omap44xx_l3_main_1__l3_main_3,
6018 &omap44xx_l3_main_2__l3_main_3,
6019 &omap44xx_l4_cfg__l3_main_3,
6020 &omap44xx_aess__l4_abe,
6021 &omap44xx_dsp__l4_abe,
6022 &omap44xx_l3_main_1__l4_abe,
6023 &omap44xx_mpu__l4_abe,
6024 &omap44xx_l3_main_1__l4_cfg,
6025 &omap44xx_l3_main_2__l4_per,
6026 &omap44xx_l4_cfg__l4_wkup,
6027 &omap44xx_mpu__mpu_private,
6028 &omap44xx_l4_cfg__ocp_wp_noc,
6029 &omap44xx_l4_abe__aess,
6030 &omap44xx_l4_abe__aess_dma,
6031 &omap44xx_l3_main_2__c2c,
6032 &omap44xx_l4_wkup__counter_32k,
6033 &omap44xx_l4_cfg__ctrl_module_core,
6034 &omap44xx_l4_cfg__ctrl_module_pad_core,
6035 &omap44xx_l4_wkup__ctrl_module_wkup,
6036 &omap44xx_l4_wkup__ctrl_module_pad_wkup,
6037 &omap44xx_l3_instr__debugss,
6038 &omap44xx_l4_cfg__dma_system,
6039 &omap44xx_l4_abe__dmic,
6040 &omap44xx_l4_abe__dmic_dma,
6041 &omap44xx_dsp__iva,
6042 &omap44xx_dsp__sl2if,
6043 &omap44xx_l4_cfg__dsp,
6044 &omap44xx_l3_main_2__dss,
6045 &omap44xx_l4_per__dss,
6046 &omap44xx_l3_main_2__dss_dispc,
6047 &omap44xx_l4_per__dss_dispc,
6048 &omap44xx_l3_main_2__dss_dsi1,
6049 &omap44xx_l4_per__dss_dsi1,
6050 &omap44xx_l3_main_2__dss_dsi2,
6051 &omap44xx_l4_per__dss_dsi2,
6052 &omap44xx_l3_main_2__dss_hdmi,
6053 &omap44xx_l4_per__dss_hdmi,
6054 &omap44xx_l3_main_2__dss_rfbi,
6055 &omap44xx_l4_per__dss_rfbi,
6056 &omap44xx_l3_main_2__dss_venc,
6057 &omap44xx_l4_per__dss_venc,
6058 &omap44xx_l4_per__elm,
6059 &omap44xx_emif_fw__emif1,
6060 &omap44xx_emif_fw__emif2,
6061 &omap44xx_l4_cfg__fdif,
6062 &omap44xx_l4_wkup__gpio1,
6063 &omap44xx_l4_per__gpio2,
6064 &omap44xx_l4_per__gpio3,
6065 &omap44xx_l4_per__gpio4,
6066 &omap44xx_l4_per__gpio5,
6067 &omap44xx_l4_per__gpio6,
6068 &omap44xx_l3_main_2__gpmc,
6069 &omap44xx_l3_main_2__gpu,
6070 &omap44xx_l4_per__hdq1w,
6071 &omap44xx_l4_cfg__hsi,
6072 &omap44xx_l4_per__i2c1,
6073 &omap44xx_l4_per__i2c2,
6074 &omap44xx_l4_per__i2c3,
6075 &omap44xx_l4_per__i2c4,
6076 &omap44xx_l3_main_2__ipu,
6077 &omap44xx_l3_main_2__iss,
6078 &omap44xx_iva__sl2if,
6079 &omap44xx_l3_main_2__iva,
6080 &omap44xx_l4_wkup__kbd,
6081 &omap44xx_l4_cfg__mailbox,
6082 &omap44xx_l4_abe__mcasp,
6083 &omap44xx_l4_abe__mcasp_dma,
6084 &omap44xx_l4_abe__mcbsp1,
6085 &omap44xx_l4_abe__mcbsp1_dma,
6086 &omap44xx_l4_abe__mcbsp2,
6087 &omap44xx_l4_abe__mcbsp2_dma,
6088 &omap44xx_l4_abe__mcbsp3,
6089 &omap44xx_l4_abe__mcbsp3_dma,
6090 &omap44xx_l4_per__mcbsp4,
6091 &omap44xx_l4_abe__mcpdm,
6092 &omap44xx_l4_abe__mcpdm_dma,
6093 &omap44xx_l4_per__mcspi1,
6094 &omap44xx_l4_per__mcspi2,
6095 &omap44xx_l4_per__mcspi3,
6096 &omap44xx_l4_per__mcspi4,
6097 &omap44xx_l4_per__mmc1,
6098 &omap44xx_l4_per__mmc2,
6099 &omap44xx_l4_per__mmc3,
6100 &omap44xx_l4_per__mmc4,
6101 &omap44xx_l4_per__mmc5,
6102 &omap44xx_l3_main_2__ocmc_ram,
6103 &omap44xx_l4_cfg__ocp2scp_usb_phy,
6104 &omap44xx_mpu_private__prcm_mpu,
6105 &omap44xx_l4_wkup__cm_core_aon,
6106 &omap44xx_l4_cfg__cm_core,
6107 &omap44xx_l4_wkup__prm,
6108 &omap44xx_l4_wkup__scrm,
6109 &omap44xx_l3_main_2__sl2if,
6110 &omap44xx_l4_abe__slimbus1,
6111 &omap44xx_l4_abe__slimbus1_dma,
6112 &omap44xx_l4_per__slimbus2,
6113 &omap44xx_l4_cfg__smartreflex_core,
6114 &omap44xx_l4_cfg__smartreflex_iva,
6115 &omap44xx_l4_cfg__smartreflex_mpu,
6116 &omap44xx_l4_cfg__spinlock,
6117 &omap44xx_l4_wkup__timer1,
6118 &omap44xx_l4_per__timer2,
6119 &omap44xx_l4_per__timer3,
6120 &omap44xx_l4_per__timer4,
6121 &omap44xx_l4_abe__timer5,
6122 &omap44xx_l4_abe__timer5_dma,
6123 &omap44xx_l4_abe__timer6,
6124 &omap44xx_l4_abe__timer6_dma,
6125 &omap44xx_l4_abe__timer7,
6126 &omap44xx_l4_abe__timer7_dma,
6127 &omap44xx_l4_abe__timer8,
6128 &omap44xx_l4_abe__timer8_dma,
6129 &omap44xx_l4_per__timer9,
6130 &omap44xx_l4_per__timer10,
6131 &omap44xx_l4_per__timer11,
6132 &omap44xx_l4_per__uart1,
6133 &omap44xx_l4_per__uart2,
6134 &omap44xx_l4_per__uart3,
6135 &omap44xx_l4_per__uart4,
6136 &omap44xx_l4_cfg__usb_host_fs,
6137 &omap44xx_l4_cfg__usb_host_hs,
6138 &omap44xx_l4_cfg__usb_otg_hs,
6139 &omap44xx_l4_cfg__usb_tll_hs,
6140 &omap44xx_l4_wkup__wd_timer2,
6141 &omap44xx_l4_abe__wd_timer3,
6142 &omap44xx_l4_abe__wd_timer3_dma,
6143 NULL,
6144 };
6145
6146 int __init omap44xx_hwmod_init(void)
6147 {
6148 omap_hwmod_init();
6149 return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
6150 }
6151
Linux kernel - Deliverables
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