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Merge tag 'drm-for-v4.8' of git://people.freedesktop.org/~airlied/linux
[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_44xx_data.c
1 /*
2 * Hardware modules present on the OMAP44xx chips
3 *
4 * Copyright (C) 2009-2012 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley
8 * Benoit Cousson
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 * Note that this file is currently not in sync with autogeneration scripts.
16 * The above note to be removed, once it is synced up.
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21 */
22
23 #include <linux/io.h>
24 #include <linux/platform_data/gpio-omap.h>
25 #include <linux/platform_data/hsmmc-omap.h>
26 #include <linux/power/smartreflex.h>
27 #include <linux/i2c-omap.h>
28
29 #include <linux/omap-dma.h>
30
31 #include <linux/platform_data/spi-omap2-mcspi.h>
32 #include <linux/platform_data/asoc-ti-mcbsp.h>
33 #include <plat/dmtimer.h>
34
35 #include "omap_hwmod.h"
36 #include "omap_hwmod_common_data.h"
37 #include "cm1_44xx.h"
38 #include "cm2_44xx.h"
39 #include "prm44xx.h"
40 #include "prm-regbits-44xx.h"
41 #include "i2c.h"
42 #include "wd_timer.h"
43
44 /* Base offset for all OMAP4 interrupts external to MPUSS */
45 #define OMAP44XX_IRQ_GIC_START 32
46
47 /* Base offset for all OMAP4 dma requests */
48 #define OMAP44XX_DMA_REQ_START 1
49
50 /*
51 * IP blocks
52 */
53
54 /*
55 * 'dmm' class
56 * instance(s): dmm
57 */
58 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
59 .name = "dmm",
60 };
61
62 /* dmm */
63 static struct omap_hwmod omap44xx_dmm_hwmod = {
64 .name = "dmm",
65 .class = &omap44xx_dmm_hwmod_class,
66 .clkdm_name = "l3_emif_clkdm",
67 .prcm = {
68 .omap4 = {
69 .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
70 .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
71 },
72 },
73 };
74
75 /*
76 * 'l3' class
77 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
78 */
79 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
80 .name = "l3",
81 };
82
83 /* l3_instr */
84 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
85 .name = "l3_instr",
86 .class = &omap44xx_l3_hwmod_class,
87 .clkdm_name = "l3_instr_clkdm",
88 .prcm = {
89 .omap4 = {
90 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
91 .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
92 .modulemode = MODULEMODE_HWCTRL,
93 },
94 },
95 };
96
97 /* l3_main_1 */
98 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
99 .name = "l3_main_1",
100 .class = &omap44xx_l3_hwmod_class,
101 .clkdm_name = "l3_1_clkdm",
102 .prcm = {
103 .omap4 = {
104 .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
105 .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
106 },
107 },
108 };
109
110 /* l3_main_2 */
111 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
112 .name = "l3_main_2",
113 .class = &omap44xx_l3_hwmod_class,
114 .clkdm_name = "l3_2_clkdm",
115 .prcm = {
116 .omap4 = {
117 .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
118 .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
119 },
120 },
121 };
122
123 /* l3_main_3 */
124 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
125 .name = "l3_main_3",
126 .class = &omap44xx_l3_hwmod_class,
127 .clkdm_name = "l3_instr_clkdm",
128 .prcm = {
129 .omap4 = {
130 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
131 .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
132 .modulemode = MODULEMODE_HWCTRL,
133 },
134 },
135 };
136
137 /*
138 * 'l4' class
139 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
140 */
141 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
142 .name = "l4",
143 };
144
145 /* l4_abe */
146 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
147 .name = "l4_abe",
148 .class = &omap44xx_l4_hwmod_class,
149 .clkdm_name = "abe_clkdm",
150 .prcm = {
151 .omap4 = {
152 .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
153 .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
154 .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
155 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
156 },
157 },
158 };
159
160 /* l4_cfg */
161 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
162 .name = "l4_cfg",
163 .class = &omap44xx_l4_hwmod_class,
164 .clkdm_name = "l4_cfg_clkdm",
165 .prcm = {
166 .omap4 = {
167 .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
168 .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
169 },
170 },
171 };
172
173 /* l4_per */
174 static struct omap_hwmod omap44xx_l4_per_hwmod = {
175 .name = "l4_per",
176 .class = &omap44xx_l4_hwmod_class,
177 .clkdm_name = "l4_per_clkdm",
178 .prcm = {
179 .omap4 = {
180 .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
181 .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
182 },
183 },
184 };
185
186 /* l4_wkup */
187 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
188 .name = "l4_wkup",
189 .class = &omap44xx_l4_hwmod_class,
190 .clkdm_name = "l4_wkup_clkdm",
191 .prcm = {
192 .omap4 = {
193 .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
194 .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
195 },
196 },
197 };
198
199 /*
200 * 'mpu_bus' class
201 * instance(s): mpu_private
202 */
203 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
204 .name = "mpu_bus",
205 };
206
207 /* mpu_private */
208 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
209 .name = "mpu_private",
210 .class = &omap44xx_mpu_bus_hwmod_class,
211 .clkdm_name = "mpuss_clkdm",
212 .prcm = {
213 .omap4 = {
214 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
215 },
216 },
217 };
218
219 /*
220 * 'ocp_wp_noc' class
221 * instance(s): ocp_wp_noc
222 */
223 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
224 .name = "ocp_wp_noc",
225 };
226
227 /* ocp_wp_noc */
228 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
229 .name = "ocp_wp_noc",
230 .class = &omap44xx_ocp_wp_noc_hwmod_class,
231 .clkdm_name = "l3_instr_clkdm",
232 .prcm = {
233 .omap4 = {
234 .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
235 .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
236 .modulemode = MODULEMODE_HWCTRL,
237 },
238 },
239 };
240
241 /*
242 * Modules omap_hwmod structures
243 *
244 * The following IPs are excluded for the moment because:
245 * - They do not need an explicit SW control using omap_hwmod API.
246 * - They still need to be validated with the driver
247 * properly adapted to omap_hwmod / omap_device
248 *
249 * usim
250 */
251
252 /*
253 * 'aess' class
254 * audio engine sub system
255 */
256
257 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
258 .rev_offs = 0x0000,
259 .sysc_offs = 0x0010,
260 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
261 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
262 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
263 MSTANDBY_SMART_WKUP),
264 .sysc_fields = &omap_hwmod_sysc_type2,
265 };
266
267 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
268 .name = "aess",
269 .sysc = &omap44xx_aess_sysc,
270 .enable_preprogram = omap_hwmod_aess_preprogram,
271 };
272
273 /* aess */
274 static struct omap_hwmod omap44xx_aess_hwmod = {
275 .name = "aess",
276 .class = &omap44xx_aess_hwmod_class,
277 .clkdm_name = "abe_clkdm",
278 .main_clk = "aess_fclk",
279 .prcm = {
280 .omap4 = {
281 .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
282 .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
283 .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
284 .modulemode = MODULEMODE_SWCTRL,
285 },
286 },
287 };
288
289 /*
290 * 'c2c' class
291 * chip 2 chip interface used to plug the ape soc (omap) with an external modem
292 * soc
293 */
294
295 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
296 .name = "c2c",
297 };
298
299 /* c2c */
300 static struct omap_hwmod omap44xx_c2c_hwmod = {
301 .name = "c2c",
302 .class = &omap44xx_c2c_hwmod_class,
303 .clkdm_name = "d2d_clkdm",
304 .prcm = {
305 .omap4 = {
306 .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
307 .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
308 },
309 },
310 };
311
312 /*
313 * 'counter' class
314 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
315 */
316
317 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
318 .rev_offs = 0x0000,
319 .sysc_offs = 0x0004,
320 .sysc_flags = SYSC_HAS_SIDLEMODE,
321 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
322 .sysc_fields = &omap_hwmod_sysc_type1,
323 };
324
325 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
326 .name = "counter",
327 .sysc = &omap44xx_counter_sysc,
328 };
329
330 /* counter_32k */
331 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
332 .name = "counter_32k",
333 .class = &omap44xx_counter_hwmod_class,
334 .clkdm_name = "l4_wkup_clkdm",
335 .flags = HWMOD_SWSUP_SIDLE,
336 .main_clk = "sys_32k_ck",
337 .prcm = {
338 .omap4 = {
339 .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
340 .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
341 },
342 },
343 };
344
345 /*
346 * 'ctrl_module' class
347 * attila core control module + core pad control module + wkup pad control
348 * module + attila wkup control module
349 */
350
351 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
352 .rev_offs = 0x0000,
353 .sysc_offs = 0x0010,
354 .sysc_flags = SYSC_HAS_SIDLEMODE,
355 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
356 SIDLE_SMART_WKUP),
357 .sysc_fields = &omap_hwmod_sysc_type2,
358 };
359
360 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
361 .name = "ctrl_module",
362 .sysc = &omap44xx_ctrl_module_sysc,
363 };
364
365 /* ctrl_module_core */
366 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
367 .name = "ctrl_module_core",
368 .class = &omap44xx_ctrl_module_hwmod_class,
369 .clkdm_name = "l4_cfg_clkdm",
370 .prcm = {
371 .omap4 = {
372 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
373 },
374 },
375 };
376
377 /* ctrl_module_pad_core */
378 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
379 .name = "ctrl_module_pad_core",
380 .class = &omap44xx_ctrl_module_hwmod_class,
381 .clkdm_name = "l4_cfg_clkdm",
382 .prcm = {
383 .omap4 = {
384 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
385 },
386 },
387 };
388
389 /* ctrl_module_wkup */
390 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
391 .name = "ctrl_module_wkup",
392 .class = &omap44xx_ctrl_module_hwmod_class,
393 .clkdm_name = "l4_wkup_clkdm",
394 .prcm = {
395 .omap4 = {
396 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
397 },
398 },
399 };
400
401 /* ctrl_module_pad_wkup */
402 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
403 .name = "ctrl_module_pad_wkup",
404 .class = &omap44xx_ctrl_module_hwmod_class,
405 .clkdm_name = "l4_wkup_clkdm",
406 .prcm = {
407 .omap4 = {
408 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
409 },
410 },
411 };
412
413 /*
414 * 'debugss' class
415 * debug and emulation sub system
416 */
417
418 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
419 .name = "debugss",
420 };
421
422 /* debugss */
423 static struct omap_hwmod omap44xx_debugss_hwmod = {
424 .name = "debugss",
425 .class = &omap44xx_debugss_hwmod_class,
426 .clkdm_name = "emu_sys_clkdm",
427 .main_clk = "trace_clk_div_ck",
428 .prcm = {
429 .omap4 = {
430 .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
431 .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
432 },
433 },
434 };
435
436 /*
437 * 'dma' class
438 * dma controller for data exchange between memory to memory (i.e. internal or
439 * external memory) and gp peripherals to memory or memory to gp peripherals
440 */
441
442 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
443 .rev_offs = 0x0000,
444 .sysc_offs = 0x002c,
445 .syss_offs = 0x0028,
446 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
447 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
448 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
449 SYSS_HAS_RESET_STATUS),
450 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
451 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
452 .sysc_fields = &omap_hwmod_sysc_type1,
453 };
454
455 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
456 .name = "dma",
457 .sysc = &omap44xx_dma_sysc,
458 };
459
460 /* dma dev_attr */
461 static struct omap_dma_dev_attr dma_dev_attr = {
462 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
463 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
464 .lch_count = 32,
465 };
466
467 /* dma_system */
468 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
469 { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
470 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
471 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
472 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
473 { .irq = -1 }
474 };
475
476 static struct omap_hwmod omap44xx_dma_system_hwmod = {
477 .name = "dma_system",
478 .class = &omap44xx_dma_hwmod_class,
479 .clkdm_name = "l3_dma_clkdm",
480 .mpu_irqs = omap44xx_dma_system_irqs,
481 .xlate_irq = omap4_xlate_irq,
482 .main_clk = "l3_div_ck",
483 .prcm = {
484 .omap4 = {
485 .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
486 .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
487 },
488 },
489 .dev_attr = &dma_dev_attr,
490 };
491
492 /*
493 * 'dmic' class
494 * digital microphone controller
495 */
496
497 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
498 .rev_offs = 0x0000,
499 .sysc_offs = 0x0010,
500 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
501 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
502 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
503 SIDLE_SMART_WKUP),
504 .sysc_fields = &omap_hwmod_sysc_type2,
505 };
506
507 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
508 .name = "dmic",
509 .sysc = &omap44xx_dmic_sysc,
510 };
511
512 /* dmic */
513 static struct omap_hwmod omap44xx_dmic_hwmod = {
514 .name = "dmic",
515 .class = &omap44xx_dmic_hwmod_class,
516 .clkdm_name = "abe_clkdm",
517 .main_clk = "func_dmic_abe_gfclk",
518 .prcm = {
519 .omap4 = {
520 .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
521 .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
522 .modulemode = MODULEMODE_SWCTRL,
523 },
524 },
525 };
526
527 /*
528 * 'dsp' class
529 * dsp sub-system
530 */
531
532 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
533 .name = "dsp",
534 };
535
536 /* dsp */
537 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
538 { .name = "dsp", .rst_shift = 0 },
539 };
540
541 static struct omap_hwmod omap44xx_dsp_hwmod = {
542 .name = "dsp",
543 .class = &omap44xx_dsp_hwmod_class,
544 .clkdm_name = "tesla_clkdm",
545 .rst_lines = omap44xx_dsp_resets,
546 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
547 .main_clk = "dpll_iva_m4x2_ck",
548 .prcm = {
549 .omap4 = {
550 .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
551 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
552 .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
553 .modulemode = MODULEMODE_HWCTRL,
554 },
555 },
556 };
557
558 /*
559 * 'dss' class
560 * display sub-system
561 */
562
563 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
564 .rev_offs = 0x0000,
565 .syss_offs = 0x0014,
566 .sysc_flags = SYSS_HAS_RESET_STATUS,
567 };
568
569 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
570 .name = "dss",
571 .sysc = &omap44xx_dss_sysc,
572 .reset = omap_dss_reset,
573 };
574
575 /* dss */
576 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
577 { .role = "sys_clk", .clk = "dss_sys_clk" },
578 { .role = "tv_clk", .clk = "dss_tv_clk" },
579 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
580 };
581
582 static struct omap_hwmod omap44xx_dss_hwmod = {
583 .name = "dss_core",
584 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
585 .class = &omap44xx_dss_hwmod_class,
586 .clkdm_name = "l3_dss_clkdm",
587 .main_clk = "dss_dss_clk",
588 .prcm = {
589 .omap4 = {
590 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
591 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
592 .modulemode = MODULEMODE_SWCTRL,
593 },
594 },
595 .opt_clks = dss_opt_clks,
596 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
597 };
598
599 /*
600 * 'dispc' class
601 * display controller
602 */
603
604 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
605 .rev_offs = 0x0000,
606 .sysc_offs = 0x0010,
607 .syss_offs = 0x0014,
608 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
609 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
610 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
611 SYSS_HAS_RESET_STATUS),
612 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
613 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
614 .sysc_fields = &omap_hwmod_sysc_type1,
615 };
616
617 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
618 .name = "dispc",
619 .sysc = &omap44xx_dispc_sysc,
620 };
621
622 /* dss_dispc */
623 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
624 { .irq = 25 + OMAP44XX_IRQ_GIC_START },
625 { .irq = -1 }
626 };
627
628 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
629 { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
630 { .dma_req = -1 }
631 };
632
633 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
634 .manager_count = 3,
635 .has_framedonetv_irq = 1
636 };
637
638 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
639 .name = "dss_dispc",
640 .class = &omap44xx_dispc_hwmod_class,
641 .clkdm_name = "l3_dss_clkdm",
642 .mpu_irqs = omap44xx_dss_dispc_irqs,
643 .xlate_irq = omap4_xlate_irq,
644 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
645 .main_clk = "dss_dss_clk",
646 .prcm = {
647 .omap4 = {
648 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
649 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
650 },
651 },
652 .dev_attr = &omap44xx_dss_dispc_dev_attr,
653 .parent_hwmod = &omap44xx_dss_hwmod,
654 };
655
656 /*
657 * 'dsi' class
658 * display serial interface controller
659 */
660
661 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
662 .rev_offs = 0x0000,
663 .sysc_offs = 0x0010,
664 .syss_offs = 0x0014,
665 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
666 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
667 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
668 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
669 .sysc_fields = &omap_hwmod_sysc_type1,
670 };
671
672 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
673 .name = "dsi",
674 .sysc = &omap44xx_dsi_sysc,
675 };
676
677 /* dss_dsi1 */
678 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
679 { .irq = 53 + OMAP44XX_IRQ_GIC_START },
680 { .irq = -1 }
681 };
682
683 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
684 { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
685 { .dma_req = -1 }
686 };
687
688 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
689 { .role = "sys_clk", .clk = "dss_sys_clk" },
690 };
691
692 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
693 .name = "dss_dsi1",
694 .class = &omap44xx_dsi_hwmod_class,
695 .clkdm_name = "l3_dss_clkdm",
696 .mpu_irqs = omap44xx_dss_dsi1_irqs,
697 .xlate_irq = omap4_xlate_irq,
698 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
699 .main_clk = "dss_dss_clk",
700 .prcm = {
701 .omap4 = {
702 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
703 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
704 },
705 },
706 .opt_clks = dss_dsi1_opt_clks,
707 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
708 .parent_hwmod = &omap44xx_dss_hwmod,
709 };
710
711 /* dss_dsi2 */
712 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
713 { .irq = 84 + OMAP44XX_IRQ_GIC_START },
714 { .irq = -1 }
715 };
716
717 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
718 { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
719 { .dma_req = -1 }
720 };
721
722 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
723 { .role = "sys_clk", .clk = "dss_sys_clk" },
724 };
725
726 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
727 .name = "dss_dsi2",
728 .class = &omap44xx_dsi_hwmod_class,
729 .clkdm_name = "l3_dss_clkdm",
730 .mpu_irqs = omap44xx_dss_dsi2_irqs,
731 .xlate_irq = omap4_xlate_irq,
732 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
733 .main_clk = "dss_dss_clk",
734 .prcm = {
735 .omap4 = {
736 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
737 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
738 },
739 },
740 .opt_clks = dss_dsi2_opt_clks,
741 .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
742 .parent_hwmod = &omap44xx_dss_hwmod,
743 };
744
745 /*
746 * 'hdmi' class
747 * hdmi controller
748 */
749
750 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
751 .rev_offs = 0x0000,
752 .sysc_offs = 0x0010,
753 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
754 SYSC_HAS_SOFTRESET),
755 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
756 SIDLE_SMART_WKUP),
757 .sysc_fields = &omap_hwmod_sysc_type2,
758 };
759
760 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
761 .name = "hdmi",
762 .sysc = &omap44xx_hdmi_sysc,
763 };
764
765 /* dss_hdmi */
766 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
767 { .irq = 101 + OMAP44XX_IRQ_GIC_START },
768 { .irq = -1 }
769 };
770
771 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
772 { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
773 { .dma_req = -1 }
774 };
775
776 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
777 { .role = "sys_clk", .clk = "dss_sys_clk" },
778 };
779
780 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
781 .name = "dss_hdmi",
782 .class = &omap44xx_hdmi_hwmod_class,
783 .clkdm_name = "l3_dss_clkdm",
784 /*
785 * HDMI audio requires to use no-idle mode. Hence,
786 * set idle mode by software.
787 */
788 .flags = HWMOD_SWSUP_SIDLE,
789 .mpu_irqs = omap44xx_dss_hdmi_irqs,
790 .xlate_irq = omap4_xlate_irq,
791 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
792 .main_clk = "dss_48mhz_clk",
793 .prcm = {
794 .omap4 = {
795 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
796 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
797 },
798 },
799 .opt_clks = dss_hdmi_opt_clks,
800 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
801 .parent_hwmod = &omap44xx_dss_hwmod,
802 };
803
804 /*
805 * 'rfbi' class
806 * remote frame buffer interface
807 */
808
809 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
810 .rev_offs = 0x0000,
811 .sysc_offs = 0x0010,
812 .syss_offs = 0x0014,
813 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
814 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
815 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
816 .sysc_fields = &omap_hwmod_sysc_type1,
817 };
818
819 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
820 .name = "rfbi",
821 .sysc = &omap44xx_rfbi_sysc,
822 };
823
824 /* dss_rfbi */
825 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
826 { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
827 { .dma_req = -1 }
828 };
829
830 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
831 { .role = "ick", .clk = "l3_div_ck" },
832 };
833
834 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
835 .name = "dss_rfbi",
836 .class = &omap44xx_rfbi_hwmod_class,
837 .clkdm_name = "l3_dss_clkdm",
838 .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
839 .main_clk = "dss_dss_clk",
840 .prcm = {
841 .omap4 = {
842 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
843 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
844 },
845 },
846 .opt_clks = dss_rfbi_opt_clks,
847 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
848 .parent_hwmod = &omap44xx_dss_hwmod,
849 };
850
851 /*
852 * 'venc' class
853 * video encoder
854 */
855
856 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
857 .name = "venc",
858 };
859
860 /* dss_venc */
861 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
862 .name = "dss_venc",
863 .class = &omap44xx_venc_hwmod_class,
864 .clkdm_name = "l3_dss_clkdm",
865 .main_clk = "dss_tv_clk",
866 .prcm = {
867 .omap4 = {
868 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
869 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
870 },
871 },
872 .parent_hwmod = &omap44xx_dss_hwmod,
873 };
874
875 /*
876 * 'elm' class
877 * bch error location module
878 */
879
880 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
881 .rev_offs = 0x0000,
882 .sysc_offs = 0x0010,
883 .syss_offs = 0x0014,
884 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
885 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
886 SYSS_HAS_RESET_STATUS),
887 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
888 .sysc_fields = &omap_hwmod_sysc_type1,
889 };
890
891 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
892 .name = "elm",
893 .sysc = &omap44xx_elm_sysc,
894 };
895
896 /* elm */
897 static struct omap_hwmod omap44xx_elm_hwmod = {
898 .name = "elm",
899 .class = &omap44xx_elm_hwmod_class,
900 .clkdm_name = "l4_per_clkdm",
901 .prcm = {
902 .omap4 = {
903 .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
904 .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
905 },
906 },
907 };
908
909 /*
910 * 'emif' class
911 * external memory interface no1
912 */
913
914 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
915 .rev_offs = 0x0000,
916 };
917
918 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
919 .name = "emif",
920 .sysc = &omap44xx_emif_sysc,
921 };
922
923 /* emif1 */
924 static struct omap_hwmod omap44xx_emif1_hwmod = {
925 .name = "emif1",
926 .class = &omap44xx_emif_hwmod_class,
927 .clkdm_name = "l3_emif_clkdm",
928 .flags = HWMOD_INIT_NO_IDLE,
929 .main_clk = "ddrphy_ck",
930 .prcm = {
931 .omap4 = {
932 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
933 .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
934 .modulemode = MODULEMODE_HWCTRL,
935 },
936 },
937 };
938
939 /* emif2 */
940 static struct omap_hwmod omap44xx_emif2_hwmod = {
941 .name = "emif2",
942 .class = &omap44xx_emif_hwmod_class,
943 .clkdm_name = "l3_emif_clkdm",
944 .flags = HWMOD_INIT_NO_IDLE,
945 .main_clk = "ddrphy_ck",
946 .prcm = {
947 .omap4 = {
948 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
949 .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
950 .modulemode = MODULEMODE_HWCTRL,
951 },
952 },
953 };
954
955 /*
956 * 'fdif' class
957 * face detection hw accelerator module
958 */
959
960 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
961 .rev_offs = 0x0000,
962 .sysc_offs = 0x0010,
963 /*
964 * FDIF needs 100 OCP clk cycles delay after a softreset before
965 * accessing sysconfig again.
966 * The lowest frequency at the moment for L3 bus is 100 MHz, so
967 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
968 *
969 * TODO: Indicate errata when available.
970 */
971 .srst_udelay = 2,
972 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
973 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
974 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
975 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
976 .sysc_fields = &omap_hwmod_sysc_type2,
977 };
978
979 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
980 .name = "fdif",
981 .sysc = &omap44xx_fdif_sysc,
982 };
983
984 /* fdif */
985 static struct omap_hwmod omap44xx_fdif_hwmod = {
986 .name = "fdif",
987 .class = &omap44xx_fdif_hwmod_class,
988 .clkdm_name = "iss_clkdm",
989 .main_clk = "fdif_fck",
990 .prcm = {
991 .omap4 = {
992 .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
993 .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
994 .modulemode = MODULEMODE_SWCTRL,
995 },
996 },
997 };
998
999 /*
1000 * 'gpio' class
1001 * general purpose io module
1002 */
1003
1004 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1005 .rev_offs = 0x0000,
1006 .sysc_offs = 0x0010,
1007 .syss_offs = 0x0114,
1008 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1009 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1010 SYSS_HAS_RESET_STATUS),
1011 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1012 SIDLE_SMART_WKUP),
1013 .sysc_fields = &omap_hwmod_sysc_type1,
1014 };
1015
1016 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1017 .name = "gpio",
1018 .sysc = &omap44xx_gpio_sysc,
1019 .rev = 2,
1020 };
1021
1022 /* gpio dev_attr */
1023 static struct omap_gpio_dev_attr gpio_dev_attr = {
1024 .bank_width = 32,
1025 .dbck_flag = true,
1026 };
1027
1028 /* gpio1 */
1029 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1030 { .role = "dbclk", .clk = "gpio1_dbclk" },
1031 };
1032
1033 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1034 .name = "gpio1",
1035 .class = &omap44xx_gpio_hwmod_class,
1036 .clkdm_name = "l4_wkup_clkdm",
1037 .main_clk = "l4_wkup_clk_mux_ck",
1038 .prcm = {
1039 .omap4 = {
1040 .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1041 .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1042 .modulemode = MODULEMODE_HWCTRL,
1043 },
1044 },
1045 .opt_clks = gpio1_opt_clks,
1046 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1047 .dev_attr = &gpio_dev_attr,
1048 };
1049
1050 /* gpio2 */
1051 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1052 { .role = "dbclk", .clk = "gpio2_dbclk" },
1053 };
1054
1055 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1056 .name = "gpio2",
1057 .class = &omap44xx_gpio_hwmod_class,
1058 .clkdm_name = "l4_per_clkdm",
1059 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1060 .main_clk = "l4_div_ck",
1061 .prcm = {
1062 .omap4 = {
1063 .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1064 .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1065 .modulemode = MODULEMODE_HWCTRL,
1066 },
1067 },
1068 .opt_clks = gpio2_opt_clks,
1069 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1070 .dev_attr = &gpio_dev_attr,
1071 };
1072
1073 /* gpio3 */
1074 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1075 { .role = "dbclk", .clk = "gpio3_dbclk" },
1076 };
1077
1078 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1079 .name = "gpio3",
1080 .class = &omap44xx_gpio_hwmod_class,
1081 .clkdm_name = "l4_per_clkdm",
1082 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1083 .main_clk = "l4_div_ck",
1084 .prcm = {
1085 .omap4 = {
1086 .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1087 .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1088 .modulemode = MODULEMODE_HWCTRL,
1089 },
1090 },
1091 .opt_clks = gpio3_opt_clks,
1092 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1093 .dev_attr = &gpio_dev_attr,
1094 };
1095
1096 /* gpio4 */
1097 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1098 { .role = "dbclk", .clk = "gpio4_dbclk" },
1099 };
1100
1101 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1102 .name = "gpio4",
1103 .class = &omap44xx_gpio_hwmod_class,
1104 .clkdm_name = "l4_per_clkdm",
1105 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1106 .main_clk = "l4_div_ck",
1107 .prcm = {
1108 .omap4 = {
1109 .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1110 .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1111 .modulemode = MODULEMODE_HWCTRL,
1112 },
1113 },
1114 .opt_clks = gpio4_opt_clks,
1115 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1116 .dev_attr = &gpio_dev_attr,
1117 };
1118
1119 /* gpio5 */
1120 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1121 { .role = "dbclk", .clk = "gpio5_dbclk" },
1122 };
1123
1124 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1125 .name = "gpio5",
1126 .class = &omap44xx_gpio_hwmod_class,
1127 .clkdm_name = "l4_per_clkdm",
1128 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1129 .main_clk = "l4_div_ck",
1130 .prcm = {
1131 .omap4 = {
1132 .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1133 .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1134 .modulemode = MODULEMODE_HWCTRL,
1135 },
1136 },
1137 .opt_clks = gpio5_opt_clks,
1138 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1139 .dev_attr = &gpio_dev_attr,
1140 };
1141
1142 /* gpio6 */
1143 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1144 { .role = "dbclk", .clk = "gpio6_dbclk" },
1145 };
1146
1147 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1148 .name = "gpio6",
1149 .class = &omap44xx_gpio_hwmod_class,
1150 .clkdm_name = "l4_per_clkdm",
1151 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1152 .main_clk = "l4_div_ck",
1153 .prcm = {
1154 .omap4 = {
1155 .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1156 .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1157 .modulemode = MODULEMODE_HWCTRL,
1158 },
1159 },
1160 .opt_clks = gpio6_opt_clks,
1161 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1162 .dev_attr = &gpio_dev_attr,
1163 };
1164
1165 /*
1166 * 'gpmc' class
1167 * general purpose memory controller
1168 */
1169
1170 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1171 .rev_offs = 0x0000,
1172 .sysc_offs = 0x0010,
1173 .syss_offs = 0x0014,
1174 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1175 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1176 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1177 .sysc_fields = &omap_hwmod_sysc_type1,
1178 };
1179
1180 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1181 .name = "gpmc",
1182 .sysc = &omap44xx_gpmc_sysc,
1183 };
1184
1185 /* gpmc */
1186 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1187 .name = "gpmc",
1188 .class = &omap44xx_gpmc_hwmod_class,
1189 .clkdm_name = "l3_2_clkdm",
1190 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
1191 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
1192 .prcm = {
1193 .omap4 = {
1194 .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1195 .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1196 .modulemode = MODULEMODE_HWCTRL,
1197 },
1198 },
1199 };
1200
1201 /*
1202 * 'gpu' class
1203 * 2d/3d graphics accelerator
1204 */
1205
1206 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1207 .rev_offs = 0x1fc00,
1208 .sysc_offs = 0x1fc10,
1209 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1210 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1211 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1212 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1213 .sysc_fields = &omap_hwmod_sysc_type2,
1214 };
1215
1216 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1217 .name = "gpu",
1218 .sysc = &omap44xx_gpu_sysc,
1219 };
1220
1221 /* gpu */
1222 static struct omap_hwmod omap44xx_gpu_hwmod = {
1223 .name = "gpu",
1224 .class = &omap44xx_gpu_hwmod_class,
1225 .clkdm_name = "l3_gfx_clkdm",
1226 .main_clk = "sgx_clk_mux",
1227 .prcm = {
1228 .omap4 = {
1229 .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1230 .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1231 .modulemode = MODULEMODE_SWCTRL,
1232 },
1233 },
1234 };
1235
1236 /*
1237 * 'hdq1w' class
1238 * hdq / 1-wire serial interface controller
1239 */
1240
1241 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1242 .rev_offs = 0x0000,
1243 .sysc_offs = 0x0014,
1244 .syss_offs = 0x0018,
1245 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1246 SYSS_HAS_RESET_STATUS),
1247 .sysc_fields = &omap_hwmod_sysc_type1,
1248 };
1249
1250 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1251 .name = "hdq1w",
1252 .sysc = &omap44xx_hdq1w_sysc,
1253 };
1254
1255 /* hdq1w */
1256 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1257 .name = "hdq1w",
1258 .class = &omap44xx_hdq1w_hwmod_class,
1259 .clkdm_name = "l4_per_clkdm",
1260 .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */
1261 .main_clk = "func_12m_fclk",
1262 .prcm = {
1263 .omap4 = {
1264 .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1265 .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1266 .modulemode = MODULEMODE_SWCTRL,
1267 },
1268 },
1269 };
1270
1271 /*
1272 * 'hsi' class
1273 * mipi high-speed synchronous serial interface (multichannel and full-duplex
1274 * serial if)
1275 */
1276
1277 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1278 .rev_offs = 0x0000,
1279 .sysc_offs = 0x0010,
1280 .syss_offs = 0x0014,
1281 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1282 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1283 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1284 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1285 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1286 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1287 .sysc_fields = &omap_hwmod_sysc_type1,
1288 };
1289
1290 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1291 .name = "hsi",
1292 .sysc = &omap44xx_hsi_sysc,
1293 };
1294
1295 /* hsi */
1296 static struct omap_hwmod omap44xx_hsi_hwmod = {
1297 .name = "hsi",
1298 .class = &omap44xx_hsi_hwmod_class,
1299 .clkdm_name = "l3_init_clkdm",
1300 .main_clk = "hsi_fck",
1301 .prcm = {
1302 .omap4 = {
1303 .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1304 .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1305 .modulemode = MODULEMODE_HWCTRL,
1306 },
1307 },
1308 };
1309
1310 /*
1311 * 'i2c' class
1312 * multimaster high-speed i2c controller
1313 */
1314
1315 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1316 .sysc_offs = 0x0010,
1317 .syss_offs = 0x0090,
1318 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1319 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1320 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1321 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1322 SIDLE_SMART_WKUP),
1323 .clockact = CLOCKACT_TEST_ICLK,
1324 .sysc_fields = &omap_hwmod_sysc_type1,
1325 };
1326
1327 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1328 .name = "i2c",
1329 .sysc = &omap44xx_i2c_sysc,
1330 .rev = OMAP_I2C_IP_VERSION_2,
1331 .reset = &omap_i2c_reset,
1332 };
1333
1334 static struct omap_i2c_dev_attr i2c_dev_attr = {
1335 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1336 };
1337
1338 /* i2c1 */
1339 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1340 .name = "i2c1",
1341 .class = &omap44xx_i2c_hwmod_class,
1342 .clkdm_name = "l4_per_clkdm",
1343 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1344 .main_clk = "func_96m_fclk",
1345 .prcm = {
1346 .omap4 = {
1347 .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1348 .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1349 .modulemode = MODULEMODE_SWCTRL,
1350 },
1351 },
1352 .dev_attr = &i2c_dev_attr,
1353 };
1354
1355 /* i2c2 */
1356 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1357 .name = "i2c2",
1358 .class = &omap44xx_i2c_hwmod_class,
1359 .clkdm_name = "l4_per_clkdm",
1360 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1361 .main_clk = "func_96m_fclk",
1362 .prcm = {
1363 .omap4 = {
1364 .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1365 .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1366 .modulemode = MODULEMODE_SWCTRL,
1367 },
1368 },
1369 .dev_attr = &i2c_dev_attr,
1370 };
1371
1372 /* i2c3 */
1373 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1374 .name = "i2c3",
1375 .class = &omap44xx_i2c_hwmod_class,
1376 .clkdm_name = "l4_per_clkdm",
1377 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1378 .main_clk = "func_96m_fclk",
1379 .prcm = {
1380 .omap4 = {
1381 .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1382 .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1383 .modulemode = MODULEMODE_SWCTRL,
1384 },
1385 },
1386 .dev_attr = &i2c_dev_attr,
1387 };
1388
1389 /* i2c4 */
1390 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1391 .name = "i2c4",
1392 .class = &omap44xx_i2c_hwmod_class,
1393 .clkdm_name = "l4_per_clkdm",
1394 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1395 .main_clk = "func_96m_fclk",
1396 .prcm = {
1397 .omap4 = {
1398 .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1399 .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1400 .modulemode = MODULEMODE_SWCTRL,
1401 },
1402 },
1403 .dev_attr = &i2c_dev_attr,
1404 };
1405
1406 /*
1407 * 'ipu' class
1408 * imaging processor unit
1409 */
1410
1411 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1412 .name = "ipu",
1413 };
1414
1415 /* ipu */
1416 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1417 { .name = "cpu0", .rst_shift = 0 },
1418 { .name = "cpu1", .rst_shift = 1 },
1419 };
1420
1421 static struct omap_hwmod omap44xx_ipu_hwmod = {
1422 .name = "ipu",
1423 .class = &omap44xx_ipu_hwmod_class,
1424 .clkdm_name = "ducati_clkdm",
1425 .rst_lines = omap44xx_ipu_resets,
1426 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
1427 .main_clk = "ducati_clk_mux_ck",
1428 .prcm = {
1429 .omap4 = {
1430 .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1431 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1432 .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1433 .modulemode = MODULEMODE_HWCTRL,
1434 },
1435 },
1436 };
1437
1438 /*
1439 * 'iss' class
1440 * external images sensor pixel data processor
1441 */
1442
1443 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1444 .rev_offs = 0x0000,
1445 .sysc_offs = 0x0010,
1446 /*
1447 * ISS needs 100 OCP clk cycles delay after a softreset before
1448 * accessing sysconfig again.
1449 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1450 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1451 *
1452 * TODO: Indicate errata when available.
1453 */
1454 .srst_udelay = 2,
1455 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1456 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1457 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1458 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1459 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1460 .sysc_fields = &omap_hwmod_sysc_type2,
1461 };
1462
1463 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1464 .name = "iss",
1465 .sysc = &omap44xx_iss_sysc,
1466 };
1467
1468 /* iss */
1469 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1470 { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1471 };
1472
1473 static struct omap_hwmod omap44xx_iss_hwmod = {
1474 .name = "iss",
1475 .class = &omap44xx_iss_hwmod_class,
1476 .clkdm_name = "iss_clkdm",
1477 .main_clk = "ducati_clk_mux_ck",
1478 .prcm = {
1479 .omap4 = {
1480 .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1481 .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1482 .modulemode = MODULEMODE_SWCTRL,
1483 },
1484 },
1485 .opt_clks = iss_opt_clks,
1486 .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
1487 };
1488
1489 /*
1490 * 'iva' class
1491 * multi-standard video encoder/decoder hardware accelerator
1492 */
1493
1494 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1495 .name = "iva",
1496 };
1497
1498 /* iva */
1499 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1500 { .name = "seq0", .rst_shift = 0 },
1501 { .name = "seq1", .rst_shift = 1 },
1502 { .name = "logic", .rst_shift = 2 },
1503 };
1504
1505 static struct omap_hwmod omap44xx_iva_hwmod = {
1506 .name = "iva",
1507 .class = &omap44xx_iva_hwmod_class,
1508 .clkdm_name = "ivahd_clkdm",
1509 .rst_lines = omap44xx_iva_resets,
1510 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
1511 .main_clk = "dpll_iva_m5x2_ck",
1512 .prcm = {
1513 .omap4 = {
1514 .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1515 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1516 .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1517 .modulemode = MODULEMODE_HWCTRL,
1518 },
1519 },
1520 };
1521
1522 /*
1523 * 'kbd' class
1524 * keyboard controller
1525 */
1526
1527 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1528 .rev_offs = 0x0000,
1529 .sysc_offs = 0x0010,
1530 .syss_offs = 0x0014,
1531 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1532 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1533 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1534 SYSS_HAS_RESET_STATUS),
1535 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1536 .sysc_fields = &omap_hwmod_sysc_type1,
1537 };
1538
1539 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1540 .name = "kbd",
1541 .sysc = &omap44xx_kbd_sysc,
1542 };
1543
1544 /* kbd */
1545 static struct omap_hwmod omap44xx_kbd_hwmod = {
1546 .name = "kbd",
1547 .class = &omap44xx_kbd_hwmod_class,
1548 .clkdm_name = "l4_wkup_clkdm",
1549 .main_clk = "sys_32k_ck",
1550 .prcm = {
1551 .omap4 = {
1552 .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1553 .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1554 .modulemode = MODULEMODE_SWCTRL,
1555 },
1556 },
1557 };
1558
1559 /*
1560 * 'mailbox' class
1561 * mailbox module allowing communication between the on-chip processors using a
1562 * queued mailbox-interrupt mechanism.
1563 */
1564
1565 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1566 .rev_offs = 0x0000,
1567 .sysc_offs = 0x0010,
1568 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1569 SYSC_HAS_SOFTRESET),
1570 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1571 .sysc_fields = &omap_hwmod_sysc_type2,
1572 };
1573
1574 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1575 .name = "mailbox",
1576 .sysc = &omap44xx_mailbox_sysc,
1577 };
1578
1579 /* mailbox */
1580 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1581 .name = "mailbox",
1582 .class = &omap44xx_mailbox_hwmod_class,
1583 .clkdm_name = "l4_cfg_clkdm",
1584 .prcm = {
1585 .omap4 = {
1586 .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1587 .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1588 },
1589 },
1590 };
1591
1592 /*
1593 * 'mcasp' class
1594 * multi-channel audio serial port controller
1595 */
1596
1597 /* The IP is not compliant to type1 / type2 scheme */
1598 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1599 .sidle_shift = 0,
1600 };
1601
1602 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1603 .sysc_offs = 0x0004,
1604 .sysc_flags = SYSC_HAS_SIDLEMODE,
1605 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1606 SIDLE_SMART_WKUP),
1607 .sysc_fields = &omap_hwmod_sysc_type_mcasp,
1608 };
1609
1610 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1611 .name = "mcasp",
1612 .sysc = &omap44xx_mcasp_sysc,
1613 };
1614
1615 /* mcasp */
1616 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1617 .name = "mcasp",
1618 .class = &omap44xx_mcasp_hwmod_class,
1619 .clkdm_name = "abe_clkdm",
1620 .main_clk = "func_mcasp_abe_gfclk",
1621 .prcm = {
1622 .omap4 = {
1623 .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1624 .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1625 .modulemode = MODULEMODE_SWCTRL,
1626 },
1627 },
1628 };
1629
1630 /*
1631 * 'mcbsp' class
1632 * multi channel buffered serial port controller
1633 */
1634
1635 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1636 .sysc_offs = 0x008c,
1637 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1638 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1639 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1640 .sysc_fields = &omap_hwmod_sysc_type1,
1641 };
1642
1643 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1644 .name = "mcbsp",
1645 .sysc = &omap44xx_mcbsp_sysc,
1646 .rev = MCBSP_CONFIG_TYPE4,
1647 };
1648
1649 /* mcbsp1 */
1650 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1651 { .role = "pad_fck", .clk = "pad_clks_ck" },
1652 { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1653 };
1654
1655 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1656 .name = "mcbsp1",
1657 .class = &omap44xx_mcbsp_hwmod_class,
1658 .clkdm_name = "abe_clkdm",
1659 .main_clk = "func_mcbsp1_gfclk",
1660 .prcm = {
1661 .omap4 = {
1662 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1663 .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1664 .modulemode = MODULEMODE_SWCTRL,
1665 },
1666 },
1667 .opt_clks = mcbsp1_opt_clks,
1668 .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
1669 };
1670
1671 /* mcbsp2 */
1672 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1673 { .role = "pad_fck", .clk = "pad_clks_ck" },
1674 { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
1675 };
1676
1677 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
1678 .name = "mcbsp2",
1679 .class = &omap44xx_mcbsp_hwmod_class,
1680 .clkdm_name = "abe_clkdm",
1681 .main_clk = "func_mcbsp2_gfclk",
1682 .prcm = {
1683 .omap4 = {
1684 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
1685 .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
1686 .modulemode = MODULEMODE_SWCTRL,
1687 },
1688 },
1689 .opt_clks = mcbsp2_opt_clks,
1690 .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
1691 };
1692
1693 /* mcbsp3 */
1694 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
1695 { .role = "pad_fck", .clk = "pad_clks_ck" },
1696 { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
1697 };
1698
1699 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
1700 .name = "mcbsp3",
1701 .class = &omap44xx_mcbsp_hwmod_class,
1702 .clkdm_name = "abe_clkdm",
1703 .main_clk = "func_mcbsp3_gfclk",
1704 .prcm = {
1705 .omap4 = {
1706 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
1707 .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
1708 .modulemode = MODULEMODE_SWCTRL,
1709 },
1710 },
1711 .opt_clks = mcbsp3_opt_clks,
1712 .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
1713 };
1714
1715 /* mcbsp4 */
1716 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
1717 { .role = "pad_fck", .clk = "pad_clks_ck" },
1718 { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
1719 };
1720
1721 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
1722 .name = "mcbsp4",
1723 .class = &omap44xx_mcbsp_hwmod_class,
1724 .clkdm_name = "l4_per_clkdm",
1725 .main_clk = "per_mcbsp4_gfclk",
1726 .prcm = {
1727 .omap4 = {
1728 .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
1729 .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
1730 .modulemode = MODULEMODE_SWCTRL,
1731 },
1732 },
1733 .opt_clks = mcbsp4_opt_clks,
1734 .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks),
1735 };
1736
1737 /*
1738 * 'mcpdm' class
1739 * multi channel pdm controller (proprietary interface with phoenix power
1740 * ic)
1741 */
1742
1743 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
1744 .rev_offs = 0x0000,
1745 .sysc_offs = 0x0010,
1746 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1747 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1748 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1749 SIDLE_SMART_WKUP),
1750 .sysc_fields = &omap_hwmod_sysc_type2,
1751 };
1752
1753 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
1754 .name = "mcpdm",
1755 .sysc = &omap44xx_mcpdm_sysc,
1756 };
1757
1758 /* mcpdm */
1759 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
1760 .name = "mcpdm",
1761 .class = &omap44xx_mcpdm_hwmod_class,
1762 .clkdm_name = "abe_clkdm",
1763 /*
1764 * It's suspected that the McPDM requires an off-chip main
1765 * functional clock, controlled via I2C. This IP block is
1766 * currently reset very early during boot, before I2C is
1767 * available, so it doesn't seem that we have any choice in
1768 * the kernel other than to avoid resetting it.
1769 *
1770 * Also, McPDM needs to be configured to NO_IDLE mode when it
1771 * is in used otherwise vital clocks will be gated which
1772 * results 'slow motion' audio playback.
1773 */
1774 .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
1775 .main_clk = "pad_clks_ck",
1776 .prcm = {
1777 .omap4 = {
1778 .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
1779 .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
1780 .modulemode = MODULEMODE_SWCTRL,
1781 },
1782 },
1783 };
1784
1785 /*
1786 * 'mcspi' class
1787 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1788 * bus
1789 */
1790
1791 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
1792 .rev_offs = 0x0000,
1793 .sysc_offs = 0x0010,
1794 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1795 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1796 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1797 SIDLE_SMART_WKUP),
1798 .sysc_fields = &omap_hwmod_sysc_type2,
1799 };
1800
1801 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
1802 .name = "mcspi",
1803 .sysc = &omap44xx_mcspi_sysc,
1804 .rev = OMAP4_MCSPI_REV,
1805 };
1806
1807 /* mcspi1 */
1808 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
1809 { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
1810 { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
1811 { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
1812 { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
1813 { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
1814 { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
1815 { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
1816 { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
1817 { .dma_req = -1 }
1818 };
1819
1820 /* mcspi1 dev_attr */
1821 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1822 .num_chipselect = 4,
1823 };
1824
1825 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
1826 .name = "mcspi1",
1827 .class = &omap44xx_mcspi_hwmod_class,
1828 .clkdm_name = "l4_per_clkdm",
1829 .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
1830 .main_clk = "func_48m_fclk",
1831 .prcm = {
1832 .omap4 = {
1833 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1834 .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1835 .modulemode = MODULEMODE_SWCTRL,
1836 },
1837 },
1838 .dev_attr = &mcspi1_dev_attr,
1839 };
1840
1841 /* mcspi2 */
1842 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
1843 { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
1844 { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
1845 { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
1846 { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
1847 { .dma_req = -1 }
1848 };
1849
1850 /* mcspi2 dev_attr */
1851 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1852 .num_chipselect = 2,
1853 };
1854
1855 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
1856 .name = "mcspi2",
1857 .class = &omap44xx_mcspi_hwmod_class,
1858 .clkdm_name = "l4_per_clkdm",
1859 .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
1860 .main_clk = "func_48m_fclk",
1861 .prcm = {
1862 .omap4 = {
1863 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1864 .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1865 .modulemode = MODULEMODE_SWCTRL,
1866 },
1867 },
1868 .dev_attr = &mcspi2_dev_attr,
1869 };
1870
1871 /* mcspi3 */
1872 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
1873 { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
1874 { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
1875 { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
1876 { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
1877 { .dma_req = -1 }
1878 };
1879
1880 /* mcspi3 dev_attr */
1881 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1882 .num_chipselect = 2,
1883 };
1884
1885 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
1886 .name = "mcspi3",
1887 .class = &omap44xx_mcspi_hwmod_class,
1888 .clkdm_name = "l4_per_clkdm",
1889 .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
1890 .main_clk = "func_48m_fclk",
1891 .prcm = {
1892 .omap4 = {
1893 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1894 .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1895 .modulemode = MODULEMODE_SWCTRL,
1896 },
1897 },
1898 .dev_attr = &mcspi3_dev_attr,
1899 };
1900
1901 /* mcspi4 */
1902 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
1903 { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
1904 { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
1905 { .dma_req = -1 }
1906 };
1907
1908 /* mcspi4 dev_attr */
1909 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1910 .num_chipselect = 1,
1911 };
1912
1913 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
1914 .name = "mcspi4",
1915 .class = &omap44xx_mcspi_hwmod_class,
1916 .clkdm_name = "l4_per_clkdm",
1917 .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
1918 .main_clk = "func_48m_fclk",
1919 .prcm = {
1920 .omap4 = {
1921 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1922 .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1923 .modulemode = MODULEMODE_SWCTRL,
1924 },
1925 },
1926 .dev_attr = &mcspi4_dev_attr,
1927 };
1928
1929 /*
1930 * 'mmc' class
1931 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
1932 */
1933
1934 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
1935 .rev_offs = 0x0000,
1936 .sysc_offs = 0x0010,
1937 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1938 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1939 SYSC_HAS_SOFTRESET),
1940 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1941 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1942 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1943 .sysc_fields = &omap_hwmod_sysc_type2,
1944 };
1945
1946 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
1947 .name = "mmc",
1948 .sysc = &omap44xx_mmc_sysc,
1949 };
1950
1951 /* mmc1 */
1952 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
1953 { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
1954 { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
1955 { .dma_req = -1 }
1956 };
1957
1958 /* mmc1 dev_attr */
1959 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1960 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1961 };
1962
1963 static struct omap_hwmod omap44xx_mmc1_hwmod = {
1964 .name = "mmc1",
1965 .class = &omap44xx_mmc_hwmod_class,
1966 .clkdm_name = "l3_init_clkdm",
1967 .sdma_reqs = omap44xx_mmc1_sdma_reqs,
1968 .main_clk = "hsmmc1_fclk",
1969 .prcm = {
1970 .omap4 = {
1971 .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1972 .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1973 .modulemode = MODULEMODE_SWCTRL,
1974 },
1975 },
1976 .dev_attr = &mmc1_dev_attr,
1977 };
1978
1979 /* mmc2 */
1980 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
1981 { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
1982 { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
1983 { .dma_req = -1 }
1984 };
1985
1986 static struct omap_hwmod omap44xx_mmc2_hwmod = {
1987 .name = "mmc2",
1988 .class = &omap44xx_mmc_hwmod_class,
1989 .clkdm_name = "l3_init_clkdm",
1990 .sdma_reqs = omap44xx_mmc2_sdma_reqs,
1991 .main_clk = "hsmmc2_fclk",
1992 .prcm = {
1993 .omap4 = {
1994 .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1995 .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1996 .modulemode = MODULEMODE_SWCTRL,
1997 },
1998 },
1999 };
2000
2001 /* mmc3 */
2002 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2003 { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2004 { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2005 { .dma_req = -1 }
2006 };
2007
2008 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2009 .name = "mmc3",
2010 .class = &omap44xx_mmc_hwmod_class,
2011 .clkdm_name = "l4_per_clkdm",
2012 .sdma_reqs = omap44xx_mmc3_sdma_reqs,
2013 .main_clk = "func_48m_fclk",
2014 .prcm = {
2015 .omap4 = {
2016 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2017 .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2018 .modulemode = MODULEMODE_SWCTRL,
2019 },
2020 },
2021 };
2022
2023 /* mmc4 */
2024 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2025 { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2026 { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2027 { .dma_req = -1 }
2028 };
2029
2030 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2031 .name = "mmc4",
2032 .class = &omap44xx_mmc_hwmod_class,
2033 .clkdm_name = "l4_per_clkdm",
2034 .sdma_reqs = omap44xx_mmc4_sdma_reqs,
2035 .main_clk = "func_48m_fclk",
2036 .prcm = {
2037 .omap4 = {
2038 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2039 .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2040 .modulemode = MODULEMODE_SWCTRL,
2041 },
2042 },
2043 };
2044
2045 /* mmc5 */
2046 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2047 { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2048 { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2049 { .dma_req = -1 }
2050 };
2051
2052 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2053 .name = "mmc5",
2054 .class = &omap44xx_mmc_hwmod_class,
2055 .clkdm_name = "l4_per_clkdm",
2056 .sdma_reqs = omap44xx_mmc5_sdma_reqs,
2057 .main_clk = "func_48m_fclk",
2058 .prcm = {
2059 .omap4 = {
2060 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2061 .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2062 .modulemode = MODULEMODE_SWCTRL,
2063 },
2064 },
2065 };
2066
2067 /*
2068 * 'mmu' class
2069 * The memory management unit performs virtual to physical address translation
2070 * for its requestors.
2071 */
2072
2073 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2074 .rev_offs = 0x000,
2075 .sysc_offs = 0x010,
2076 .syss_offs = 0x014,
2077 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2078 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2079 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2080 .sysc_fields = &omap_hwmod_sysc_type1,
2081 };
2082
2083 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
2084 .name = "mmu",
2085 .sysc = &mmu_sysc,
2086 };
2087
2088 /* mmu ipu */
2089
2090 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2091 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2092 { .name = "mmu_cache", .rst_shift = 2 },
2093 };
2094
2095 /* l3_main_2 -> mmu_ipu */
2096 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
2097 .master = &omap44xx_l3_main_2_hwmod,
2098 .slave = &omap44xx_mmu_ipu_hwmod,
2099 .clk = "l3_div_ck",
2100 .user = OCP_USER_MPU | OCP_USER_SDMA,
2101 };
2102
2103 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2104 .name = "mmu_ipu",
2105 .class = &omap44xx_mmu_hwmod_class,
2106 .clkdm_name = "ducati_clkdm",
2107 .rst_lines = omap44xx_mmu_ipu_resets,
2108 .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2109 .main_clk = "ducati_clk_mux_ck",
2110 .prcm = {
2111 .omap4 = {
2112 .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2113 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2114 .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2115 .modulemode = MODULEMODE_HWCTRL,
2116 },
2117 },
2118 };
2119
2120 /* mmu dsp */
2121
2122 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2123 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2124 { .name = "mmu_cache", .rst_shift = 1 },
2125 };
2126
2127 /* l4_cfg -> dsp */
2128 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
2129 .master = &omap44xx_l4_cfg_hwmod,
2130 .slave = &omap44xx_mmu_dsp_hwmod,
2131 .clk = "l4_div_ck",
2132 .user = OCP_USER_MPU | OCP_USER_SDMA,
2133 };
2134
2135 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2136 .name = "mmu_dsp",
2137 .class = &omap44xx_mmu_hwmod_class,
2138 .clkdm_name = "tesla_clkdm",
2139 .rst_lines = omap44xx_mmu_dsp_resets,
2140 .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2141 .main_clk = "dpll_iva_m4x2_ck",
2142 .prcm = {
2143 .omap4 = {
2144 .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
2145 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
2146 .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
2147 .modulemode = MODULEMODE_HWCTRL,
2148 },
2149 },
2150 };
2151
2152 /*
2153 * 'mpu' class
2154 * mpu sub-system
2155 */
2156
2157 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2158 .name = "mpu",
2159 };
2160
2161 /* mpu */
2162 static struct omap_hwmod omap44xx_mpu_hwmod = {
2163 .name = "mpu",
2164 .class = &omap44xx_mpu_hwmod_class,
2165 .clkdm_name = "mpuss_clkdm",
2166 .flags = HWMOD_INIT_NO_IDLE,
2167 .main_clk = "dpll_mpu_m2_ck",
2168 .prcm = {
2169 .omap4 = {
2170 .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2171 .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2172 },
2173 },
2174 };
2175
2176 /*
2177 * 'ocmc_ram' class
2178 * top-level core on-chip ram
2179 */
2180
2181 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2182 .name = "ocmc_ram",
2183 };
2184
2185 /* ocmc_ram */
2186 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2187 .name = "ocmc_ram",
2188 .class = &omap44xx_ocmc_ram_hwmod_class,
2189 .clkdm_name = "l3_2_clkdm",
2190 .prcm = {
2191 .omap4 = {
2192 .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2193 .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2194 },
2195 },
2196 };
2197
2198 /*
2199 * 'ocp2scp' class
2200 * bridge to transform ocp interface protocol to scp (serial control port)
2201 * protocol
2202 */
2203
2204 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2205 .rev_offs = 0x0000,
2206 .sysc_offs = 0x0010,
2207 .syss_offs = 0x0014,
2208 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2209 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2210 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2211 .sysc_fields = &omap_hwmod_sysc_type1,
2212 };
2213
2214 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2215 .name = "ocp2scp",
2216 .sysc = &omap44xx_ocp2scp_sysc,
2217 };
2218
2219 /* ocp2scp_usb_phy */
2220 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2221 .name = "ocp2scp_usb_phy",
2222 .class = &omap44xx_ocp2scp_hwmod_class,
2223 .clkdm_name = "l3_init_clkdm",
2224 /*
2225 * ocp2scp_usb_phy_phy_48m is provided by the OMAP4 PRCM IP
2226 * block as an "optional clock," and normally should never be
2227 * specified as the main_clk for an OMAP IP block. However it
2228 * turns out that this clock is actually the main clock for
2229 * the ocp2scp_usb_phy IP block:
2230 * http://lists.infradead.org/pipermail/linux-arm-kernel/2012-September/119943.html
2231 * So listing ocp2scp_usb_phy_phy_48m as a main_clk here seems
2232 * to be the best workaround.
2233 */
2234 .main_clk = "ocp2scp_usb_phy_phy_48m",
2235 .prcm = {
2236 .omap4 = {
2237 .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2238 .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2239 .modulemode = MODULEMODE_HWCTRL,
2240 },
2241 },
2242 };
2243
2244 /*
2245 * 'prcm' class
2246 * power and reset manager (part of the prcm infrastructure) + clock manager 2
2247 * + clock manager 1 (in always on power domain) + local prm in mpu
2248 */
2249
2250 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2251 .name = "prcm",
2252 };
2253
2254 /* prcm_mpu */
2255 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2256 .name = "prcm_mpu",
2257 .class = &omap44xx_prcm_hwmod_class,
2258 .clkdm_name = "l4_wkup_clkdm",
2259 .flags = HWMOD_NO_IDLEST,
2260 .prcm = {
2261 .omap4 = {
2262 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2263 },
2264 },
2265 };
2266
2267 /* cm_core_aon */
2268 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2269 .name = "cm_core_aon",
2270 .class = &omap44xx_prcm_hwmod_class,
2271 .flags = HWMOD_NO_IDLEST,
2272 .prcm = {
2273 .omap4 = {
2274 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2275 },
2276 },
2277 };
2278
2279 /* cm_core */
2280 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2281 .name = "cm_core",
2282 .class = &omap44xx_prcm_hwmod_class,
2283 .flags = HWMOD_NO_IDLEST,
2284 .prcm = {
2285 .omap4 = {
2286 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2287 },
2288 },
2289 };
2290
2291 /* prm */
2292 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2293 { .name = "rst_global_warm_sw", .rst_shift = 0 },
2294 { .name = "rst_global_cold_sw", .rst_shift = 1 },
2295 };
2296
2297 static struct omap_hwmod omap44xx_prm_hwmod = {
2298 .name = "prm",
2299 .class = &omap44xx_prcm_hwmod_class,
2300 .rst_lines = omap44xx_prm_resets,
2301 .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets),
2302 };
2303
2304 /*
2305 * 'scrm' class
2306 * system clock and reset manager
2307 */
2308
2309 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2310 .name = "scrm",
2311 };
2312
2313 /* scrm */
2314 static struct omap_hwmod omap44xx_scrm_hwmod = {
2315 .name = "scrm",
2316 .class = &omap44xx_scrm_hwmod_class,
2317 .clkdm_name = "l4_wkup_clkdm",
2318 .prcm = {
2319 .omap4 = {
2320 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2321 },
2322 },
2323 };
2324
2325 /*
2326 * 'sl2if' class
2327 * shared level 2 memory interface
2328 */
2329
2330 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2331 .name = "sl2if",
2332 };
2333
2334 /* sl2if */
2335 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2336 .name = "sl2if",
2337 .class = &omap44xx_sl2if_hwmod_class,
2338 .clkdm_name = "ivahd_clkdm",
2339 .prcm = {
2340 .omap4 = {
2341 .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2342 .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2343 .modulemode = MODULEMODE_HWCTRL,
2344 },
2345 },
2346 };
2347
2348 /*
2349 * 'slimbus' class
2350 * bidirectional, multi-drop, multi-channel two-line serial interface between
2351 * the device and external components
2352 */
2353
2354 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2355 .rev_offs = 0x0000,
2356 .sysc_offs = 0x0010,
2357 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2358 SYSC_HAS_SOFTRESET),
2359 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2360 SIDLE_SMART_WKUP),
2361 .sysc_fields = &omap_hwmod_sysc_type2,
2362 };
2363
2364 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2365 .name = "slimbus",
2366 .sysc = &omap44xx_slimbus_sysc,
2367 };
2368
2369 /* slimbus1 */
2370 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2371 { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2372 { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2373 { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2374 { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2375 };
2376
2377 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2378 .name = "slimbus1",
2379 .class = &omap44xx_slimbus_hwmod_class,
2380 .clkdm_name = "abe_clkdm",
2381 .prcm = {
2382 .omap4 = {
2383 .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2384 .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2385 .modulemode = MODULEMODE_SWCTRL,
2386 },
2387 },
2388 .opt_clks = slimbus1_opt_clks,
2389 .opt_clks_cnt = ARRAY_SIZE(slimbus1_opt_clks),
2390 };
2391
2392 /* slimbus2 */
2393 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2394 { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2395 { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2396 { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2397 };
2398
2399 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2400 .name = "slimbus2",
2401 .class = &omap44xx_slimbus_hwmod_class,
2402 .clkdm_name = "l4_per_clkdm",
2403 .prcm = {
2404 .omap4 = {
2405 .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2406 .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2407 .modulemode = MODULEMODE_SWCTRL,
2408 },
2409 },
2410 .opt_clks = slimbus2_opt_clks,
2411 .opt_clks_cnt = ARRAY_SIZE(slimbus2_opt_clks),
2412 };
2413
2414 /*
2415 * 'smartreflex' class
2416 * smartreflex module (monitor silicon performance and outputs a measure of
2417 * performance error)
2418 */
2419
2420 /* The IP is not compliant to type1 / type2 scheme */
2421 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2422 .sidle_shift = 24,
2423 .enwkup_shift = 26,
2424 };
2425
2426 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2427 .sysc_offs = 0x0038,
2428 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2429 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2430 SIDLE_SMART_WKUP),
2431 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
2432 };
2433
2434 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2435 .name = "smartreflex",
2436 .sysc = &omap44xx_smartreflex_sysc,
2437 .rev = 2,
2438 };
2439
2440 /* smartreflex_core */
2441 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2442 .sensor_voltdm_name = "core",
2443 };
2444
2445 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2446 .name = "smartreflex_core",
2447 .class = &omap44xx_smartreflex_hwmod_class,
2448 .clkdm_name = "l4_ao_clkdm",
2449
2450 .main_clk = "smartreflex_core_fck",
2451 .prcm = {
2452 .omap4 = {
2453 .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2454 .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2455 .modulemode = MODULEMODE_SWCTRL,
2456 },
2457 },
2458 .dev_attr = &smartreflex_core_dev_attr,
2459 };
2460
2461 /* smartreflex_iva */
2462 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
2463 .sensor_voltdm_name = "iva",
2464 };
2465
2466 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2467 .name = "smartreflex_iva",
2468 .class = &omap44xx_smartreflex_hwmod_class,
2469 .clkdm_name = "l4_ao_clkdm",
2470 .main_clk = "smartreflex_iva_fck",
2471 .prcm = {
2472 .omap4 = {
2473 .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
2474 .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
2475 .modulemode = MODULEMODE_SWCTRL,
2476 },
2477 },
2478 .dev_attr = &smartreflex_iva_dev_attr,
2479 };
2480
2481 /* smartreflex_mpu */
2482 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2483 .sensor_voltdm_name = "mpu",
2484 };
2485
2486 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
2487 .name = "smartreflex_mpu",
2488 .class = &omap44xx_smartreflex_hwmod_class,
2489 .clkdm_name = "l4_ao_clkdm",
2490 .main_clk = "smartreflex_mpu_fck",
2491 .prcm = {
2492 .omap4 = {
2493 .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
2494 .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
2495 .modulemode = MODULEMODE_SWCTRL,
2496 },
2497 },
2498 .dev_attr = &smartreflex_mpu_dev_attr,
2499 };
2500
2501 /*
2502 * 'spinlock' class
2503 * spinlock provides hardware assistance for synchronizing the processes
2504 * running on multiple processors
2505 */
2506
2507 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
2508 .rev_offs = 0x0000,
2509 .sysc_offs = 0x0010,
2510 .syss_offs = 0x0014,
2511 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2512 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2513 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2514 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2515 .sysc_fields = &omap_hwmod_sysc_type1,
2516 };
2517
2518 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
2519 .name = "spinlock",
2520 .sysc = &omap44xx_spinlock_sysc,
2521 };
2522
2523 /* spinlock */
2524 static struct omap_hwmod omap44xx_spinlock_hwmod = {
2525 .name = "spinlock",
2526 .class = &omap44xx_spinlock_hwmod_class,
2527 .clkdm_name = "l4_cfg_clkdm",
2528 .prcm = {
2529 .omap4 = {
2530 .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
2531 .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
2532 },
2533 },
2534 };
2535
2536 /*
2537 * 'timer' class
2538 * general purpose timer module with accurate 1ms tick
2539 * This class contains several variants: ['timer_1ms', 'timer']
2540 */
2541
2542 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
2543 .rev_offs = 0x0000,
2544 .sysc_offs = 0x0010,
2545 .syss_offs = 0x0014,
2546 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2547 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2548 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2549 SYSS_HAS_RESET_STATUS),
2550 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2551 .clockact = CLOCKACT_TEST_ICLK,
2552 .sysc_fields = &omap_hwmod_sysc_type1,
2553 };
2554
2555 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
2556 .name = "timer",
2557 .sysc = &omap44xx_timer_1ms_sysc,
2558 };
2559
2560 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
2561 .rev_offs = 0x0000,
2562 .sysc_offs = 0x0010,
2563 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2564 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2565 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2566 SIDLE_SMART_WKUP),
2567 .sysc_fields = &omap_hwmod_sysc_type2,
2568 };
2569
2570 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
2571 .name = "timer",
2572 .sysc = &omap44xx_timer_sysc,
2573 };
2574
2575 /* always-on timers dev attribute */
2576 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
2577 .timer_capability = OMAP_TIMER_ALWON,
2578 };
2579
2580 /* pwm timers dev attribute */
2581 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
2582 .timer_capability = OMAP_TIMER_HAS_PWM,
2583 };
2584
2585 /* timers with DSP interrupt dev attribute */
2586 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
2587 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
2588 };
2589
2590 /* pwm timers with DSP interrupt dev attribute */
2591 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
2592 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
2593 };
2594
2595 /* timer1 */
2596 static struct omap_hwmod omap44xx_timer1_hwmod = {
2597 .name = "timer1",
2598 .class = &omap44xx_timer_1ms_hwmod_class,
2599 .clkdm_name = "l4_wkup_clkdm",
2600 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2601 .main_clk = "dmt1_clk_mux",
2602 .prcm = {
2603 .omap4 = {
2604 .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2605 .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
2606 .modulemode = MODULEMODE_SWCTRL,
2607 },
2608 },
2609 .dev_attr = &capability_alwon_dev_attr,
2610 };
2611
2612 /* timer2 */
2613 static struct omap_hwmod omap44xx_timer2_hwmod = {
2614 .name = "timer2",
2615 .class = &omap44xx_timer_1ms_hwmod_class,
2616 .clkdm_name = "l4_per_clkdm",
2617 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2618 .main_clk = "cm2_dm2_mux",
2619 .prcm = {
2620 .omap4 = {
2621 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
2622 .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
2623 .modulemode = MODULEMODE_SWCTRL,
2624 },
2625 },
2626 };
2627
2628 /* timer3 */
2629 static struct omap_hwmod omap44xx_timer3_hwmod = {
2630 .name = "timer3",
2631 .class = &omap44xx_timer_hwmod_class,
2632 .clkdm_name = "l4_per_clkdm",
2633 .main_clk = "cm2_dm3_mux",
2634 .prcm = {
2635 .omap4 = {
2636 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
2637 .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
2638 .modulemode = MODULEMODE_SWCTRL,
2639 },
2640 },
2641 };
2642
2643 /* timer4 */
2644 static struct omap_hwmod omap44xx_timer4_hwmod = {
2645 .name = "timer4",
2646 .class = &omap44xx_timer_hwmod_class,
2647 .clkdm_name = "l4_per_clkdm",
2648 .main_clk = "cm2_dm4_mux",
2649 .prcm = {
2650 .omap4 = {
2651 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
2652 .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
2653 .modulemode = MODULEMODE_SWCTRL,
2654 },
2655 },
2656 };
2657
2658 /* timer5 */
2659 static struct omap_hwmod omap44xx_timer5_hwmod = {
2660 .name = "timer5",
2661 .class = &omap44xx_timer_hwmod_class,
2662 .clkdm_name = "abe_clkdm",
2663 .main_clk = "timer5_sync_mux",
2664 .prcm = {
2665 .omap4 = {
2666 .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
2667 .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
2668 .modulemode = MODULEMODE_SWCTRL,
2669 },
2670 },
2671 .dev_attr = &capability_dsp_dev_attr,
2672 };
2673
2674 /* timer6 */
2675 static struct omap_hwmod omap44xx_timer6_hwmod = {
2676 .name = "timer6",
2677 .class = &omap44xx_timer_hwmod_class,
2678 .clkdm_name = "abe_clkdm",
2679 .main_clk = "timer6_sync_mux",
2680 .prcm = {
2681 .omap4 = {
2682 .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
2683 .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
2684 .modulemode = MODULEMODE_SWCTRL,
2685 },
2686 },
2687 .dev_attr = &capability_dsp_dev_attr,
2688 };
2689
2690 /* timer7 */
2691 static struct omap_hwmod omap44xx_timer7_hwmod = {
2692 .name = "timer7",
2693 .class = &omap44xx_timer_hwmod_class,
2694 .clkdm_name = "abe_clkdm",
2695 .main_clk = "timer7_sync_mux",
2696 .prcm = {
2697 .omap4 = {
2698 .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
2699 .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
2700 .modulemode = MODULEMODE_SWCTRL,
2701 },
2702 },
2703 .dev_attr = &capability_dsp_dev_attr,
2704 };
2705
2706 /* timer8 */
2707 static struct omap_hwmod omap44xx_timer8_hwmod = {
2708 .name = "timer8",
2709 .class = &omap44xx_timer_hwmod_class,
2710 .clkdm_name = "abe_clkdm",
2711 .main_clk = "timer8_sync_mux",
2712 .prcm = {
2713 .omap4 = {
2714 .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
2715 .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
2716 .modulemode = MODULEMODE_SWCTRL,
2717 },
2718 },
2719 .dev_attr = &capability_dsp_pwm_dev_attr,
2720 };
2721
2722 /* timer9 */
2723 static struct omap_hwmod omap44xx_timer9_hwmod = {
2724 .name = "timer9",
2725 .class = &omap44xx_timer_hwmod_class,
2726 .clkdm_name = "l4_per_clkdm",
2727 .main_clk = "cm2_dm9_mux",
2728 .prcm = {
2729 .omap4 = {
2730 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
2731 .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
2732 .modulemode = MODULEMODE_SWCTRL,
2733 },
2734 },
2735 .dev_attr = &capability_pwm_dev_attr,
2736 };
2737
2738 /* timer10 */
2739 static struct omap_hwmod omap44xx_timer10_hwmod = {
2740 .name = "timer10",
2741 .class = &omap44xx_timer_1ms_hwmod_class,
2742 .clkdm_name = "l4_per_clkdm",
2743 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2744 .main_clk = "cm2_dm10_mux",
2745 .prcm = {
2746 .omap4 = {
2747 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
2748 .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
2749 .modulemode = MODULEMODE_SWCTRL,
2750 },
2751 },
2752 .dev_attr = &capability_pwm_dev_attr,
2753 };
2754
2755 /* timer11 */
2756 static struct omap_hwmod omap44xx_timer11_hwmod = {
2757 .name = "timer11",
2758 .class = &omap44xx_timer_hwmod_class,
2759 .clkdm_name = "l4_per_clkdm",
2760 .main_clk = "cm2_dm11_mux",
2761 .prcm = {
2762 .omap4 = {
2763 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
2764 .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
2765 .modulemode = MODULEMODE_SWCTRL,
2766 },
2767 },
2768 .dev_attr = &capability_pwm_dev_attr,
2769 };
2770
2771 /*
2772 * 'uart' class
2773 * universal asynchronous receiver/transmitter (uart)
2774 */
2775
2776 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
2777 .rev_offs = 0x0050,
2778 .sysc_offs = 0x0054,
2779 .syss_offs = 0x0058,
2780 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2781 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2782 SYSS_HAS_RESET_STATUS),
2783 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2784 SIDLE_SMART_WKUP),
2785 .sysc_fields = &omap_hwmod_sysc_type1,
2786 };
2787
2788 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
2789 .name = "uart",
2790 .sysc = &omap44xx_uart_sysc,
2791 };
2792
2793 /* uart1 */
2794 static struct omap_hwmod omap44xx_uart1_hwmod = {
2795 .name = "uart1",
2796 .class = &omap44xx_uart_hwmod_class,
2797 .clkdm_name = "l4_per_clkdm",
2798 .flags = HWMOD_SWSUP_SIDLE_ACT,
2799 .main_clk = "func_48m_fclk",
2800 .prcm = {
2801 .omap4 = {
2802 .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
2803 .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
2804 .modulemode = MODULEMODE_SWCTRL,
2805 },
2806 },
2807 };
2808
2809 /* uart2 */
2810 static struct omap_hwmod omap44xx_uart2_hwmod = {
2811 .name = "uart2",
2812 .class = &omap44xx_uart_hwmod_class,
2813 .clkdm_name = "l4_per_clkdm",
2814 .flags = HWMOD_SWSUP_SIDLE_ACT,
2815 .main_clk = "func_48m_fclk",
2816 .prcm = {
2817 .omap4 = {
2818 .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
2819 .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
2820 .modulemode = MODULEMODE_SWCTRL,
2821 },
2822 },
2823 };
2824
2825 /* uart3 */
2826 static struct omap_hwmod omap44xx_uart3_hwmod = {
2827 .name = "uart3",
2828 .class = &omap44xx_uart_hwmod_class,
2829 .clkdm_name = "l4_per_clkdm",
2830 .flags = DEBUG_OMAP4UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
2831 .main_clk = "func_48m_fclk",
2832 .prcm = {
2833 .omap4 = {
2834 .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
2835 .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
2836 .modulemode = MODULEMODE_SWCTRL,
2837 },
2838 },
2839 };
2840
2841 /* uart4 */
2842 static struct omap_hwmod omap44xx_uart4_hwmod = {
2843 .name = "uart4",
2844 .class = &omap44xx_uart_hwmod_class,
2845 .clkdm_name = "l4_per_clkdm",
2846 .flags = DEBUG_OMAP4UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
2847 .main_clk = "func_48m_fclk",
2848 .prcm = {
2849 .omap4 = {
2850 .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
2851 .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
2852 .modulemode = MODULEMODE_SWCTRL,
2853 },
2854 },
2855 };
2856
2857 /*
2858 * 'usb_host_fs' class
2859 * full-speed usb host controller
2860 */
2861
2862 /* The IP is not compliant to type1 / type2 scheme */
2863 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
2864 .midle_shift = 4,
2865 .sidle_shift = 2,
2866 .srst_shift = 1,
2867 };
2868
2869 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
2870 .rev_offs = 0x0000,
2871 .sysc_offs = 0x0210,
2872 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2873 SYSC_HAS_SOFTRESET),
2874 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2875 SIDLE_SMART_WKUP),
2876 .sysc_fields = &omap_hwmod_sysc_type_usb_host_fs,
2877 };
2878
2879 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
2880 .name = "usb_host_fs",
2881 .sysc = &omap44xx_usb_host_fs_sysc,
2882 };
2883
2884 /* usb_host_fs */
2885 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
2886 .name = "usb_host_fs",
2887 .class = &omap44xx_usb_host_fs_hwmod_class,
2888 .clkdm_name = "l3_init_clkdm",
2889 .main_clk = "usb_host_fs_fck",
2890 .prcm = {
2891 .omap4 = {
2892 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
2893 .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
2894 .modulemode = MODULEMODE_SWCTRL,
2895 },
2896 },
2897 };
2898
2899 /*
2900 * 'usb_host_hs' class
2901 * high-speed multi-port usb host controller
2902 */
2903
2904 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
2905 .rev_offs = 0x0000,
2906 .sysc_offs = 0x0010,
2907 .syss_offs = 0x0014,
2908 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2909 SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS),
2910 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2911 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2912 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2913 .sysc_fields = &omap_hwmod_sysc_type2,
2914 };
2915
2916 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
2917 .name = "usb_host_hs",
2918 .sysc = &omap44xx_usb_host_hs_sysc,
2919 };
2920
2921 /* usb_host_hs */
2922 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
2923 .name = "usb_host_hs",
2924 .class = &omap44xx_usb_host_hs_hwmod_class,
2925 .clkdm_name = "l3_init_clkdm",
2926 .main_clk = "usb_host_hs_fck",
2927 .prcm = {
2928 .omap4 = {
2929 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
2930 .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
2931 .modulemode = MODULEMODE_SWCTRL,
2932 },
2933 },
2934
2935 /*
2936 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
2937 * id: i660
2938 *
2939 * Description:
2940 * In the following configuration :
2941 * - USBHOST module is set to smart-idle mode
2942 * - PRCM asserts idle_req to the USBHOST module ( This typically
2943 * happens when the system is going to a low power mode : all ports
2944 * have been suspended, the master part of the USBHOST module has
2945 * entered the standby state, and SW has cut the functional clocks)
2946 * - an USBHOST interrupt occurs before the module is able to answer
2947 * idle_ack, typically a remote wakeup IRQ.
2948 * Then the USB HOST module will enter a deadlock situation where it
2949 * is no more accessible nor functional.
2950 *
2951 * Workaround:
2952 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
2953 */
2954
2955 /*
2956 * Errata: USB host EHCI may stall when entering smart-standby mode
2957 * Id: i571
2958 *
2959 * Description:
2960 * When the USBHOST module is set to smart-standby mode, and when it is
2961 * ready to enter the standby state (i.e. all ports are suspended and
2962 * all attached devices are in suspend mode), then it can wrongly assert
2963 * the Mstandby signal too early while there are still some residual OCP
2964 * transactions ongoing. If this condition occurs, the internal state
2965 * machine may go to an undefined state and the USB link may be stuck
2966 * upon the next resume.
2967 *
2968 * Workaround:
2969 * Don't use smart standby; use only force standby,
2970 * hence HWMOD_SWSUP_MSTANDBY
2971 */
2972
2973 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2974 };
2975
2976 /*
2977 * 'usb_otg_hs' class
2978 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
2979 */
2980
2981 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
2982 .rev_offs = 0x0400,
2983 .sysc_offs = 0x0404,
2984 .syss_offs = 0x0408,
2985 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2986 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2987 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2988 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2989 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2990 MSTANDBY_SMART),
2991 .sysc_fields = &omap_hwmod_sysc_type1,
2992 };
2993
2994 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
2995 .name = "usb_otg_hs",
2996 .sysc = &omap44xx_usb_otg_hs_sysc,
2997 };
2998
2999 /* usb_otg_hs */
3000 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3001 { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3002 };
3003
3004 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3005 .name = "usb_otg_hs",
3006 .class = &omap44xx_usb_otg_hs_hwmod_class,
3007 .clkdm_name = "l3_init_clkdm",
3008 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3009 .main_clk = "usb_otg_hs_ick",
3010 .prcm = {
3011 .omap4 = {
3012 .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3013 .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3014 .modulemode = MODULEMODE_HWCTRL,
3015 },
3016 },
3017 .opt_clks = usb_otg_hs_opt_clks,
3018 .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
3019 };
3020
3021 /*
3022 * 'usb_tll_hs' class
3023 * usb_tll_hs module is the adapter on the usb_host_hs ports
3024 */
3025
3026 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3027 .rev_offs = 0x0000,
3028 .sysc_offs = 0x0010,
3029 .syss_offs = 0x0014,
3030 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3031 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3032 SYSC_HAS_AUTOIDLE),
3033 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3034 .sysc_fields = &omap_hwmod_sysc_type1,
3035 };
3036
3037 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3038 .name = "usb_tll_hs",
3039 .sysc = &omap44xx_usb_tll_hs_sysc,
3040 };
3041
3042 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3043 .name = "usb_tll_hs",
3044 .class = &omap44xx_usb_tll_hs_hwmod_class,
3045 .clkdm_name = "l3_init_clkdm",
3046 .main_clk = "usb_tll_hs_ick",
3047 .prcm = {
3048 .omap4 = {
3049 .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3050 .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3051 .modulemode = MODULEMODE_HWCTRL,
3052 },
3053 },
3054 };
3055
3056 /*
3057 * 'wd_timer' class
3058 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3059 * overflow condition
3060 */
3061
3062 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3063 .rev_offs = 0x0000,
3064 .sysc_offs = 0x0010,
3065 .syss_offs = 0x0014,
3066 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3067 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3068 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3069 SIDLE_SMART_WKUP),
3070 .sysc_fields = &omap_hwmod_sysc_type1,
3071 };
3072
3073 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3074 .name = "wd_timer",
3075 .sysc = &omap44xx_wd_timer_sysc,
3076 .pre_shutdown = &omap2_wd_timer_disable,
3077 .reset = &omap2_wd_timer_reset,
3078 };
3079
3080 /* wd_timer2 */
3081 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3082 .name = "wd_timer2",
3083 .class = &omap44xx_wd_timer_hwmod_class,
3084 .clkdm_name = "l4_wkup_clkdm",
3085 .main_clk = "sys_32k_ck",
3086 .prcm = {
3087 .omap4 = {
3088 .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3089 .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3090 .modulemode = MODULEMODE_SWCTRL,
3091 },
3092 },
3093 };
3094
3095 /* wd_timer3 */
3096 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3097 .name = "wd_timer3",
3098 .class = &omap44xx_wd_timer_hwmod_class,
3099 .clkdm_name = "abe_clkdm",
3100 .main_clk = "sys_32k_ck",
3101 .prcm = {
3102 .omap4 = {
3103 .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3104 .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3105 .modulemode = MODULEMODE_SWCTRL,
3106 },
3107 },
3108 };
3109
3110
3111 /*
3112 * interfaces
3113 */
3114
3115 /* l3_main_1 -> dmm */
3116 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3117 .master = &omap44xx_l3_main_1_hwmod,
3118 .slave = &omap44xx_dmm_hwmod,
3119 .clk = "l3_div_ck",
3120 .user = OCP_USER_SDMA,
3121 };
3122
3123 /* mpu -> dmm */
3124 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3125 .master = &omap44xx_mpu_hwmod,
3126 .slave = &omap44xx_dmm_hwmod,
3127 .clk = "l3_div_ck",
3128 .user = OCP_USER_MPU,
3129 };
3130
3131 /* iva -> l3_instr */
3132 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3133 .master = &omap44xx_iva_hwmod,
3134 .slave = &omap44xx_l3_instr_hwmod,
3135 .clk = "l3_div_ck",
3136 .user = OCP_USER_MPU | OCP_USER_SDMA,
3137 };
3138
3139 /* l3_main_3 -> l3_instr */
3140 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3141 .master = &omap44xx_l3_main_3_hwmod,
3142 .slave = &omap44xx_l3_instr_hwmod,
3143 .clk = "l3_div_ck",
3144 .user = OCP_USER_MPU | OCP_USER_SDMA,
3145 };
3146
3147 /* ocp_wp_noc -> l3_instr */
3148 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3149 .master = &omap44xx_ocp_wp_noc_hwmod,
3150 .slave = &omap44xx_l3_instr_hwmod,
3151 .clk = "l3_div_ck",
3152 .user = OCP_USER_MPU | OCP_USER_SDMA,
3153 };
3154
3155 /* dsp -> l3_main_1 */
3156 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3157 .master = &omap44xx_dsp_hwmod,
3158 .slave = &omap44xx_l3_main_1_hwmod,
3159 .clk = "l3_div_ck",
3160 .user = OCP_USER_MPU | OCP_USER_SDMA,
3161 };
3162
3163 /* dss -> l3_main_1 */
3164 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3165 .master = &omap44xx_dss_hwmod,
3166 .slave = &omap44xx_l3_main_1_hwmod,
3167 .clk = "l3_div_ck",
3168 .user = OCP_USER_MPU | OCP_USER_SDMA,
3169 };
3170
3171 /* l3_main_2 -> l3_main_1 */
3172 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3173 .master = &omap44xx_l3_main_2_hwmod,
3174 .slave = &omap44xx_l3_main_1_hwmod,
3175 .clk = "l3_div_ck",
3176 .user = OCP_USER_MPU | OCP_USER_SDMA,
3177 };
3178
3179 /* l4_cfg -> l3_main_1 */
3180 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3181 .master = &omap44xx_l4_cfg_hwmod,
3182 .slave = &omap44xx_l3_main_1_hwmod,
3183 .clk = "l4_div_ck",
3184 .user = OCP_USER_MPU | OCP_USER_SDMA,
3185 };
3186
3187 /* mmc1 -> l3_main_1 */
3188 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3189 .master = &omap44xx_mmc1_hwmod,
3190 .slave = &omap44xx_l3_main_1_hwmod,
3191 .clk = "l3_div_ck",
3192 .user = OCP_USER_MPU | OCP_USER_SDMA,
3193 };
3194
3195 /* mmc2 -> l3_main_1 */
3196 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3197 .master = &omap44xx_mmc2_hwmod,
3198 .slave = &omap44xx_l3_main_1_hwmod,
3199 .clk = "l3_div_ck",
3200 .user = OCP_USER_MPU | OCP_USER_SDMA,
3201 };
3202
3203 /* mpu -> l3_main_1 */
3204 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3205 .master = &omap44xx_mpu_hwmod,
3206 .slave = &omap44xx_l3_main_1_hwmod,
3207 .clk = "l3_div_ck",
3208 .user = OCP_USER_MPU,
3209 };
3210
3211 /* debugss -> l3_main_2 */
3212 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
3213 .master = &omap44xx_debugss_hwmod,
3214 .slave = &omap44xx_l3_main_2_hwmod,
3215 .clk = "dbgclk_mux_ck",
3216 .user = OCP_USER_MPU | OCP_USER_SDMA,
3217 };
3218
3219 /* dma_system -> l3_main_2 */
3220 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
3221 .master = &omap44xx_dma_system_hwmod,
3222 .slave = &omap44xx_l3_main_2_hwmod,
3223 .clk = "l3_div_ck",
3224 .user = OCP_USER_MPU | OCP_USER_SDMA,
3225 };
3226
3227 /* fdif -> l3_main_2 */
3228 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3229 .master = &omap44xx_fdif_hwmod,
3230 .slave = &omap44xx_l3_main_2_hwmod,
3231 .clk = "l3_div_ck",
3232 .user = OCP_USER_MPU | OCP_USER_SDMA,
3233 };
3234
3235 /* gpu -> l3_main_2 */
3236 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
3237 .master = &omap44xx_gpu_hwmod,
3238 .slave = &omap44xx_l3_main_2_hwmod,
3239 .clk = "l3_div_ck",
3240 .user = OCP_USER_MPU | OCP_USER_SDMA,
3241 };
3242
3243 /* hsi -> l3_main_2 */
3244 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
3245 .master = &omap44xx_hsi_hwmod,
3246 .slave = &omap44xx_l3_main_2_hwmod,
3247 .clk = "l3_div_ck",
3248 .user = OCP_USER_MPU | OCP_USER_SDMA,
3249 };
3250
3251 /* ipu -> l3_main_2 */
3252 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
3253 .master = &omap44xx_ipu_hwmod,
3254 .slave = &omap44xx_l3_main_2_hwmod,
3255 .clk = "l3_div_ck",
3256 .user = OCP_USER_MPU | OCP_USER_SDMA,
3257 };
3258
3259 /* iss -> l3_main_2 */
3260 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
3261 .master = &omap44xx_iss_hwmod,
3262 .slave = &omap44xx_l3_main_2_hwmod,
3263 .clk = "l3_div_ck",
3264 .user = OCP_USER_MPU | OCP_USER_SDMA,
3265 };
3266
3267 /* iva -> l3_main_2 */
3268 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
3269 .master = &omap44xx_iva_hwmod,
3270 .slave = &omap44xx_l3_main_2_hwmod,
3271 .clk = "l3_div_ck",
3272 .user = OCP_USER_MPU | OCP_USER_SDMA,
3273 };
3274
3275 /* l3_main_1 -> l3_main_2 */
3276 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
3277 .master = &omap44xx_l3_main_1_hwmod,
3278 .slave = &omap44xx_l3_main_2_hwmod,
3279 .clk = "l3_div_ck",
3280 .user = OCP_USER_MPU,
3281 };
3282
3283 /* l4_cfg -> l3_main_2 */
3284 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
3285 .master = &omap44xx_l4_cfg_hwmod,
3286 .slave = &omap44xx_l3_main_2_hwmod,
3287 .clk = "l4_div_ck",
3288 .user = OCP_USER_MPU | OCP_USER_SDMA,
3289 };
3290
3291 /* usb_host_fs -> l3_main_2 */
3292 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
3293 .master = &omap44xx_usb_host_fs_hwmod,
3294 .slave = &omap44xx_l3_main_2_hwmod,
3295 .clk = "l3_div_ck",
3296 .user = OCP_USER_MPU | OCP_USER_SDMA,
3297 };
3298
3299 /* usb_host_hs -> l3_main_2 */
3300 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
3301 .master = &omap44xx_usb_host_hs_hwmod,
3302 .slave = &omap44xx_l3_main_2_hwmod,
3303 .clk = "l3_div_ck",
3304 .user = OCP_USER_MPU | OCP_USER_SDMA,
3305 };
3306
3307 /* usb_otg_hs -> l3_main_2 */
3308 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
3309 .master = &omap44xx_usb_otg_hs_hwmod,
3310 .slave = &omap44xx_l3_main_2_hwmod,
3311 .clk = "l3_div_ck",
3312 .user = OCP_USER_MPU | OCP_USER_SDMA,
3313 };
3314
3315 /* l3_main_1 -> l3_main_3 */
3316 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
3317 .master = &omap44xx_l3_main_1_hwmod,
3318 .slave = &omap44xx_l3_main_3_hwmod,
3319 .clk = "l3_div_ck",
3320 .user = OCP_USER_MPU,
3321 };
3322
3323 /* l3_main_2 -> l3_main_3 */
3324 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
3325 .master = &omap44xx_l3_main_2_hwmod,
3326 .slave = &omap44xx_l3_main_3_hwmod,
3327 .clk = "l3_div_ck",
3328 .user = OCP_USER_MPU | OCP_USER_SDMA,
3329 };
3330
3331 /* l4_cfg -> l3_main_3 */
3332 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
3333 .master = &omap44xx_l4_cfg_hwmod,
3334 .slave = &omap44xx_l3_main_3_hwmod,
3335 .clk = "l4_div_ck",
3336 .user = OCP_USER_MPU | OCP_USER_SDMA,
3337 };
3338
3339 /* aess -> l4_abe */
3340 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
3341 .master = &omap44xx_aess_hwmod,
3342 .slave = &omap44xx_l4_abe_hwmod,
3343 .clk = "ocp_abe_iclk",
3344 .user = OCP_USER_MPU | OCP_USER_SDMA,
3345 };
3346
3347 /* dsp -> l4_abe */
3348 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
3349 .master = &omap44xx_dsp_hwmod,
3350 .slave = &omap44xx_l4_abe_hwmod,
3351 .clk = "ocp_abe_iclk",
3352 .user = OCP_USER_MPU | OCP_USER_SDMA,
3353 };
3354
3355 /* l3_main_1 -> l4_abe */
3356 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
3357 .master = &omap44xx_l3_main_1_hwmod,
3358 .slave = &omap44xx_l4_abe_hwmod,
3359 .clk = "l3_div_ck",
3360 .user = OCP_USER_MPU | OCP_USER_SDMA,
3361 };
3362
3363 /* mpu -> l4_abe */
3364 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
3365 .master = &omap44xx_mpu_hwmod,
3366 .slave = &omap44xx_l4_abe_hwmod,
3367 .clk = "ocp_abe_iclk",
3368 .user = OCP_USER_MPU | OCP_USER_SDMA,
3369 };
3370
3371 /* l3_main_1 -> l4_cfg */
3372 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
3373 .master = &omap44xx_l3_main_1_hwmod,
3374 .slave = &omap44xx_l4_cfg_hwmod,
3375 .clk = "l3_div_ck",
3376 .user = OCP_USER_MPU | OCP_USER_SDMA,
3377 };
3378
3379 /* l3_main_2 -> l4_per */
3380 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
3381 .master = &omap44xx_l3_main_2_hwmod,
3382 .slave = &omap44xx_l4_per_hwmod,
3383 .clk = "l3_div_ck",
3384 .user = OCP_USER_MPU | OCP_USER_SDMA,
3385 };
3386
3387 /* l4_cfg -> l4_wkup */
3388 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
3389 .master = &omap44xx_l4_cfg_hwmod,
3390 .slave = &omap44xx_l4_wkup_hwmod,
3391 .clk = "l4_div_ck",
3392 .user = OCP_USER_MPU | OCP_USER_SDMA,
3393 };
3394
3395 /* mpu -> mpu_private */
3396 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
3397 .master = &omap44xx_mpu_hwmod,
3398 .slave = &omap44xx_mpu_private_hwmod,
3399 .clk = "l3_div_ck",
3400 .user = OCP_USER_MPU | OCP_USER_SDMA,
3401 };
3402
3403 /* l4_cfg -> ocp_wp_noc */
3404 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
3405 .master = &omap44xx_l4_cfg_hwmod,
3406 .slave = &omap44xx_ocp_wp_noc_hwmod,
3407 .clk = "l4_div_ck",
3408 .user = OCP_USER_MPU | OCP_USER_SDMA,
3409 };
3410
3411 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
3412 {
3413 .name = "dmem",
3414 .pa_start = 0x40180000,
3415 .pa_end = 0x4018ffff
3416 },
3417 {
3418 .name = "cmem",
3419 .pa_start = 0x401a0000,
3420 .pa_end = 0x401a1fff
3421 },
3422 {
3423 .name = "smem",
3424 .pa_start = 0x401c0000,
3425 .pa_end = 0x401c5fff
3426 },
3427 {
3428 .name = "pmem",
3429 .pa_start = 0x401e0000,
3430 .pa_end = 0x401e1fff
3431 },
3432 {
3433 .name = "mpu",
3434 .pa_start = 0x401f1000,
3435 .pa_end = 0x401f13ff,
3436 .flags = ADDR_TYPE_RT
3437 },
3438 { }
3439 };
3440
3441 /* l4_abe -> aess */
3442 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
3443 .master = &omap44xx_l4_abe_hwmod,
3444 .slave = &omap44xx_aess_hwmod,
3445 .clk = "ocp_abe_iclk",
3446 .addr = omap44xx_aess_addrs,
3447 .user = OCP_USER_MPU,
3448 };
3449
3450 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
3451 {
3452 .name = "dmem_dma",
3453 .pa_start = 0x49080000,
3454 .pa_end = 0x4908ffff
3455 },
3456 {
3457 .name = "cmem_dma",
3458 .pa_start = 0x490a0000,
3459 .pa_end = 0x490a1fff
3460 },
3461 {
3462 .name = "smem_dma",
3463 .pa_start = 0x490c0000,
3464 .pa_end = 0x490c5fff
3465 },
3466 {
3467 .name = "pmem_dma",
3468 .pa_start = 0x490e0000,
3469 .pa_end = 0x490e1fff
3470 },
3471 {
3472 .name = "dma",
3473 .pa_start = 0x490f1000,
3474 .pa_end = 0x490f13ff,
3475 .flags = ADDR_TYPE_RT
3476 },
3477 { }
3478 };
3479
3480 /* l4_abe -> aess (dma) */
3481 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
3482 .master = &omap44xx_l4_abe_hwmod,
3483 .slave = &omap44xx_aess_hwmod,
3484 .clk = "ocp_abe_iclk",
3485 .addr = omap44xx_aess_dma_addrs,
3486 .user = OCP_USER_SDMA,
3487 };
3488
3489 /* l3_main_2 -> c2c */
3490 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
3491 .master = &omap44xx_l3_main_2_hwmod,
3492 .slave = &omap44xx_c2c_hwmod,
3493 .clk = "l3_div_ck",
3494 .user = OCP_USER_MPU | OCP_USER_SDMA,
3495 };
3496
3497 /* l4_wkup -> counter_32k */
3498 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
3499 .master = &omap44xx_l4_wkup_hwmod,
3500 .slave = &omap44xx_counter_32k_hwmod,
3501 .clk = "l4_wkup_clk_mux_ck",
3502 .user = OCP_USER_MPU | OCP_USER_SDMA,
3503 };
3504
3505 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
3506 {
3507 .pa_start = 0x4a002000,
3508 .pa_end = 0x4a0027ff,
3509 .flags = ADDR_TYPE_RT
3510 },
3511 { }
3512 };
3513
3514 /* l4_cfg -> ctrl_module_core */
3515 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
3516 .master = &omap44xx_l4_cfg_hwmod,
3517 .slave = &omap44xx_ctrl_module_core_hwmod,
3518 .clk = "l4_div_ck",
3519 .addr = omap44xx_ctrl_module_core_addrs,
3520 .user = OCP_USER_MPU | OCP_USER_SDMA,
3521 };
3522
3523 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
3524 {
3525 .pa_start = 0x4a100000,
3526 .pa_end = 0x4a1007ff,
3527 .flags = ADDR_TYPE_RT
3528 },
3529 { }
3530 };
3531
3532 /* l4_cfg -> ctrl_module_pad_core */
3533 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
3534 .master = &omap44xx_l4_cfg_hwmod,
3535 .slave = &omap44xx_ctrl_module_pad_core_hwmod,
3536 .clk = "l4_div_ck",
3537 .addr = omap44xx_ctrl_module_pad_core_addrs,
3538 .user = OCP_USER_MPU | OCP_USER_SDMA,
3539 };
3540
3541 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
3542 {
3543 .pa_start = 0x4a30c000,
3544 .pa_end = 0x4a30c7ff,
3545 .flags = ADDR_TYPE_RT
3546 },
3547 { }
3548 };
3549
3550 /* l4_wkup -> ctrl_module_wkup */
3551 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
3552 .master = &omap44xx_l4_wkup_hwmod,
3553 .slave = &omap44xx_ctrl_module_wkup_hwmod,
3554 .clk = "l4_wkup_clk_mux_ck",
3555 .addr = omap44xx_ctrl_module_wkup_addrs,
3556 .user = OCP_USER_MPU | OCP_USER_SDMA,
3557 };
3558
3559 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
3560 {
3561 .pa_start = 0x4a31e000,
3562 .pa_end = 0x4a31e7ff,
3563 .flags = ADDR_TYPE_RT
3564 },
3565 { }
3566 };
3567
3568 /* l4_wkup -> ctrl_module_pad_wkup */
3569 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
3570 .master = &omap44xx_l4_wkup_hwmod,
3571 .slave = &omap44xx_ctrl_module_pad_wkup_hwmod,
3572 .clk = "l4_wkup_clk_mux_ck",
3573 .addr = omap44xx_ctrl_module_pad_wkup_addrs,
3574 .user = OCP_USER_MPU | OCP_USER_SDMA,
3575 };
3576
3577 /* l3_instr -> debugss */
3578 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
3579 .master = &omap44xx_l3_instr_hwmod,
3580 .slave = &omap44xx_debugss_hwmod,
3581 .clk = "l3_div_ck",
3582 .user = OCP_USER_MPU | OCP_USER_SDMA,
3583 };
3584
3585 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
3586 {
3587 .pa_start = 0x4a056000,
3588 .pa_end = 0x4a056fff,
3589 .flags = ADDR_TYPE_RT
3590 },
3591 { }
3592 };
3593
3594 /* l4_cfg -> dma_system */
3595 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
3596 .master = &omap44xx_l4_cfg_hwmod,
3597 .slave = &omap44xx_dma_system_hwmod,
3598 .clk = "l4_div_ck",
3599 .addr = omap44xx_dma_system_addrs,
3600 .user = OCP_USER_MPU | OCP_USER_SDMA,
3601 };
3602
3603 /* l4_abe -> dmic */
3604 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
3605 .master = &omap44xx_l4_abe_hwmod,
3606 .slave = &omap44xx_dmic_hwmod,
3607 .clk = "ocp_abe_iclk",
3608 .user = OCP_USER_MPU | OCP_USER_SDMA,
3609 };
3610
3611 /* dsp -> iva */
3612 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
3613 .master = &omap44xx_dsp_hwmod,
3614 .slave = &omap44xx_iva_hwmod,
3615 .clk = "dpll_iva_m5x2_ck",
3616 .user = OCP_USER_DSP,
3617 };
3618
3619 /* dsp -> sl2if */
3620 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
3621 .master = &omap44xx_dsp_hwmod,
3622 .slave = &omap44xx_sl2if_hwmod,
3623 .clk = "dpll_iva_m5x2_ck",
3624 .user = OCP_USER_DSP,
3625 };
3626
3627 /* l4_cfg -> dsp */
3628 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
3629 .master = &omap44xx_l4_cfg_hwmod,
3630 .slave = &omap44xx_dsp_hwmod,
3631 .clk = "l4_div_ck",
3632 .user = OCP_USER_MPU | OCP_USER_SDMA,
3633 };
3634
3635 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
3636 {
3637 .pa_start = 0x58000000,
3638 .pa_end = 0x5800007f,
3639 .flags = ADDR_TYPE_RT
3640 },
3641 { }
3642 };
3643
3644 /* l3_main_2 -> dss */
3645 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
3646 .master = &omap44xx_l3_main_2_hwmod,
3647 .slave = &omap44xx_dss_hwmod,
3648 .clk = "l3_div_ck",
3649 .addr = omap44xx_dss_dma_addrs,
3650 .user = OCP_USER_SDMA,
3651 };
3652
3653 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
3654 {
3655 .pa_start = 0x48040000,
3656 .pa_end = 0x4804007f,
3657 .flags = ADDR_TYPE_RT
3658 },
3659 { }
3660 };
3661
3662 /* l4_per -> dss */
3663 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
3664 .master = &omap44xx_l4_per_hwmod,
3665 .slave = &omap44xx_dss_hwmod,
3666 .clk = "l4_div_ck",
3667 .addr = omap44xx_dss_addrs,
3668 .user = OCP_USER_MPU,
3669 };
3670
3671 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
3672 {
3673 .pa_start = 0x58001000,
3674 .pa_end = 0x58001fff,
3675 .flags = ADDR_TYPE_RT
3676 },
3677 { }
3678 };
3679
3680 /* l3_main_2 -> dss_dispc */
3681 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
3682 .master = &omap44xx_l3_main_2_hwmod,
3683 .slave = &omap44xx_dss_dispc_hwmod,
3684 .clk = "l3_div_ck",
3685 .addr = omap44xx_dss_dispc_dma_addrs,
3686 .user = OCP_USER_SDMA,
3687 };
3688
3689 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
3690 {
3691 .pa_start = 0x48041000,
3692 .pa_end = 0x48041fff,
3693 .flags = ADDR_TYPE_RT
3694 },
3695 { }
3696 };
3697
3698 /* l4_per -> dss_dispc */
3699 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
3700 .master = &omap44xx_l4_per_hwmod,
3701 .slave = &omap44xx_dss_dispc_hwmod,
3702 .clk = "l4_div_ck",
3703 .addr = omap44xx_dss_dispc_addrs,
3704 .user = OCP_USER_MPU,
3705 };
3706
3707 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
3708 {
3709 .pa_start = 0x58004000,
3710 .pa_end = 0x580041ff,
3711 .flags = ADDR_TYPE_RT
3712 },
3713 { }
3714 };
3715
3716 /* l3_main_2 -> dss_dsi1 */
3717 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
3718 .master = &omap44xx_l3_main_2_hwmod,
3719 .slave = &omap44xx_dss_dsi1_hwmod,
3720 .clk = "l3_div_ck",
3721 .addr = omap44xx_dss_dsi1_dma_addrs,
3722 .user = OCP_USER_SDMA,
3723 };
3724
3725 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
3726 {
3727 .pa_start = 0x48044000,
3728 .pa_end = 0x480441ff,
3729 .flags = ADDR_TYPE_RT
3730 },
3731 { }
3732 };
3733
3734 /* l4_per -> dss_dsi1 */
3735 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
3736 .master = &omap44xx_l4_per_hwmod,
3737 .slave = &omap44xx_dss_dsi1_hwmod,
3738 .clk = "l4_div_ck",
3739 .addr = omap44xx_dss_dsi1_addrs,
3740 .user = OCP_USER_MPU,
3741 };
3742
3743 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
3744 {
3745 .pa_start = 0x58005000,
3746 .pa_end = 0x580051ff,
3747 .flags = ADDR_TYPE_RT
3748 },
3749 { }
3750 };
3751
3752 /* l3_main_2 -> dss_dsi2 */
3753 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
3754 .master = &omap44xx_l3_main_2_hwmod,
3755 .slave = &omap44xx_dss_dsi2_hwmod,
3756 .clk = "l3_div_ck",
3757 .addr = omap44xx_dss_dsi2_dma_addrs,
3758 .user = OCP_USER_SDMA,
3759 };
3760
3761 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
3762 {
3763 .pa_start = 0x48045000,
3764 .pa_end = 0x480451ff,
3765 .flags = ADDR_TYPE_RT
3766 },
3767 { }
3768 };
3769
3770 /* l4_per -> dss_dsi2 */
3771 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
3772 .master = &omap44xx_l4_per_hwmod,
3773 .slave = &omap44xx_dss_dsi2_hwmod,
3774 .clk = "l4_div_ck",
3775 .addr = omap44xx_dss_dsi2_addrs,
3776 .user = OCP_USER_MPU,
3777 };
3778
3779 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
3780 {
3781 .pa_start = 0x58006000,
3782 .pa_end = 0x58006fff,
3783 .flags = ADDR_TYPE_RT
3784 },
3785 { }
3786 };
3787
3788 /* l3_main_2 -> dss_hdmi */
3789 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
3790 .master = &omap44xx_l3_main_2_hwmod,
3791 .slave = &omap44xx_dss_hdmi_hwmod,
3792 .clk = "l3_div_ck",
3793 .addr = omap44xx_dss_hdmi_dma_addrs,
3794 .user = OCP_USER_SDMA,
3795 };
3796
3797 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
3798 {
3799 .pa_start = 0x48046000,
3800 .pa_end = 0x48046fff,
3801 .flags = ADDR_TYPE_RT
3802 },
3803 { }
3804 };
3805
3806 /* l4_per -> dss_hdmi */
3807 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
3808 .master = &omap44xx_l4_per_hwmod,
3809 .slave = &omap44xx_dss_hdmi_hwmod,
3810 .clk = "l4_div_ck",
3811 .addr = omap44xx_dss_hdmi_addrs,
3812 .user = OCP_USER_MPU,
3813 };
3814
3815 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
3816 {
3817 .pa_start = 0x58002000,
3818 .pa_end = 0x580020ff,
3819 .flags = ADDR_TYPE_RT
3820 },
3821 { }
3822 };
3823
3824 /* l3_main_2 -> dss_rfbi */
3825 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
3826 .master = &omap44xx_l3_main_2_hwmod,
3827 .slave = &omap44xx_dss_rfbi_hwmod,
3828 .clk = "l3_div_ck",
3829 .addr = omap44xx_dss_rfbi_dma_addrs,
3830 .user = OCP_USER_SDMA,
3831 };
3832
3833 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
3834 {
3835 .pa_start = 0x48042000,
3836 .pa_end = 0x480420ff,
3837 .flags = ADDR_TYPE_RT
3838 },
3839 { }
3840 };
3841
3842 /* l4_per -> dss_rfbi */
3843 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
3844 .master = &omap44xx_l4_per_hwmod,
3845 .slave = &omap44xx_dss_rfbi_hwmod,
3846 .clk = "l4_div_ck",
3847 .addr = omap44xx_dss_rfbi_addrs,
3848 .user = OCP_USER_MPU,
3849 };
3850
3851 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
3852 {
3853 .pa_start = 0x58003000,
3854 .pa_end = 0x580030ff,
3855 .flags = ADDR_TYPE_RT
3856 },
3857 { }
3858 };
3859
3860 /* l3_main_2 -> dss_venc */
3861 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
3862 .master = &omap44xx_l3_main_2_hwmod,
3863 .slave = &omap44xx_dss_venc_hwmod,
3864 .clk = "l3_div_ck",
3865 .addr = omap44xx_dss_venc_dma_addrs,
3866 .user = OCP_USER_SDMA,
3867 };
3868
3869 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
3870 {
3871 .pa_start = 0x48043000,
3872 .pa_end = 0x480430ff,
3873 .flags = ADDR_TYPE_RT
3874 },
3875 { }
3876 };
3877
3878 /* l4_per -> dss_venc */
3879 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
3880 .master = &omap44xx_l4_per_hwmod,
3881 .slave = &omap44xx_dss_venc_hwmod,
3882 .clk = "l4_div_ck",
3883 .addr = omap44xx_dss_venc_addrs,
3884 .user = OCP_USER_MPU,
3885 };
3886
3887 /* l4_per -> elm */
3888 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
3889 .master = &omap44xx_l4_per_hwmod,
3890 .slave = &omap44xx_elm_hwmod,
3891 .clk = "l4_div_ck",
3892 .user = OCP_USER_MPU | OCP_USER_SDMA,
3893 };
3894
3895 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
3896 {
3897 .pa_start = 0x4a10a000,
3898 .pa_end = 0x4a10a1ff,
3899 .flags = ADDR_TYPE_RT
3900 },
3901 { }
3902 };
3903
3904 /* l4_cfg -> fdif */
3905 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
3906 .master = &omap44xx_l4_cfg_hwmod,
3907 .slave = &omap44xx_fdif_hwmod,
3908 .clk = "l4_div_ck",
3909 .addr = omap44xx_fdif_addrs,
3910 .user = OCP_USER_MPU | OCP_USER_SDMA,
3911 };
3912
3913 /* l4_wkup -> gpio1 */
3914 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
3915 .master = &omap44xx_l4_wkup_hwmod,
3916 .slave = &omap44xx_gpio1_hwmod,
3917 .clk = "l4_wkup_clk_mux_ck",
3918 .user = OCP_USER_MPU | OCP_USER_SDMA,
3919 };
3920
3921 /* l4_per -> gpio2 */
3922 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
3923 .master = &omap44xx_l4_per_hwmod,
3924 .slave = &omap44xx_gpio2_hwmod,
3925 .clk = "l4_div_ck",
3926 .user = OCP_USER_MPU | OCP_USER_SDMA,
3927 };
3928
3929 /* l4_per -> gpio3 */
3930 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
3931 .master = &omap44xx_l4_per_hwmod,
3932 .slave = &omap44xx_gpio3_hwmod,
3933 .clk = "l4_div_ck",
3934 .user = OCP_USER_MPU | OCP_USER_SDMA,
3935 };
3936
3937 /* l4_per -> gpio4 */
3938 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
3939 .master = &omap44xx_l4_per_hwmod,
3940 .slave = &omap44xx_gpio4_hwmod,
3941 .clk = "l4_div_ck",
3942 .user = OCP_USER_MPU | OCP_USER_SDMA,
3943 };
3944
3945 /* l4_per -> gpio5 */
3946 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
3947 .master = &omap44xx_l4_per_hwmod,
3948 .slave = &omap44xx_gpio5_hwmod,
3949 .clk = "l4_div_ck",
3950 .user = OCP_USER_MPU | OCP_USER_SDMA,
3951 };
3952
3953 /* l4_per -> gpio6 */
3954 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
3955 .master = &omap44xx_l4_per_hwmod,
3956 .slave = &omap44xx_gpio6_hwmod,
3957 .clk = "l4_div_ck",
3958 .user = OCP_USER_MPU | OCP_USER_SDMA,
3959 };
3960
3961 /* l3_main_2 -> gpmc */
3962 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
3963 .master = &omap44xx_l3_main_2_hwmod,
3964 .slave = &omap44xx_gpmc_hwmod,
3965 .clk = "l3_div_ck",
3966 .user = OCP_USER_MPU | OCP_USER_SDMA,
3967 };
3968
3969 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
3970 {
3971 .pa_start = 0x56000000,
3972 .pa_end = 0x5600ffff,
3973 .flags = ADDR_TYPE_RT
3974 },
3975 { }
3976 };
3977
3978 /* l3_main_2 -> gpu */
3979 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
3980 .master = &omap44xx_l3_main_2_hwmod,
3981 .slave = &omap44xx_gpu_hwmod,
3982 .clk = "l3_div_ck",
3983 .addr = omap44xx_gpu_addrs,
3984 .user = OCP_USER_MPU | OCP_USER_SDMA,
3985 };
3986
3987 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
3988 {
3989 .pa_start = 0x480b2000,
3990 .pa_end = 0x480b201f,
3991 .flags = ADDR_TYPE_RT
3992 },
3993 { }
3994 };
3995
3996 /* l4_per -> hdq1w */
3997 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
3998 .master = &omap44xx_l4_per_hwmod,
3999 .slave = &omap44xx_hdq1w_hwmod,
4000 .clk = "l4_div_ck",
4001 .addr = omap44xx_hdq1w_addrs,
4002 .user = OCP_USER_MPU | OCP_USER_SDMA,
4003 };
4004
4005 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4006 {
4007 .pa_start = 0x4a058000,
4008 .pa_end = 0x4a05bfff,
4009 .flags = ADDR_TYPE_RT
4010 },
4011 { }
4012 };
4013
4014 /* l4_cfg -> hsi */
4015 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4016 .master = &omap44xx_l4_cfg_hwmod,
4017 .slave = &omap44xx_hsi_hwmod,
4018 .clk = "l4_div_ck",
4019 .addr = omap44xx_hsi_addrs,
4020 .user = OCP_USER_MPU | OCP_USER_SDMA,
4021 };
4022
4023 /* l4_per -> i2c1 */
4024 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4025 .master = &omap44xx_l4_per_hwmod,
4026 .slave = &omap44xx_i2c1_hwmod,
4027 .clk = "l4_div_ck",
4028 .user = OCP_USER_MPU | OCP_USER_SDMA,
4029 };
4030
4031 /* l4_per -> i2c2 */
4032 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
4033 .master = &omap44xx_l4_per_hwmod,
4034 .slave = &omap44xx_i2c2_hwmod,
4035 .clk = "l4_div_ck",
4036 .user = OCP_USER_MPU | OCP_USER_SDMA,
4037 };
4038
4039 /* l4_per -> i2c3 */
4040 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
4041 .master = &omap44xx_l4_per_hwmod,
4042 .slave = &omap44xx_i2c3_hwmod,
4043 .clk = "l4_div_ck",
4044 .user = OCP_USER_MPU | OCP_USER_SDMA,
4045 };
4046
4047 /* l4_per -> i2c4 */
4048 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
4049 .master = &omap44xx_l4_per_hwmod,
4050 .slave = &omap44xx_i2c4_hwmod,
4051 .clk = "l4_div_ck",
4052 .user = OCP_USER_MPU | OCP_USER_SDMA,
4053 };
4054
4055 /* l3_main_2 -> ipu */
4056 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
4057 .master = &omap44xx_l3_main_2_hwmod,
4058 .slave = &omap44xx_ipu_hwmod,
4059 .clk = "l3_div_ck",
4060 .user = OCP_USER_MPU | OCP_USER_SDMA,
4061 };
4062
4063 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
4064 {
4065 .pa_start = 0x52000000,
4066 .pa_end = 0x520000ff,
4067 .flags = ADDR_TYPE_RT
4068 },
4069 { }
4070 };
4071
4072 /* l3_main_2 -> iss */
4073 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
4074 .master = &omap44xx_l3_main_2_hwmod,
4075 .slave = &omap44xx_iss_hwmod,
4076 .clk = "l3_div_ck",
4077 .addr = omap44xx_iss_addrs,
4078 .user = OCP_USER_MPU | OCP_USER_SDMA,
4079 };
4080
4081 /* iva -> sl2if */
4082 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
4083 .master = &omap44xx_iva_hwmod,
4084 .slave = &omap44xx_sl2if_hwmod,
4085 .clk = "dpll_iva_m5x2_ck",
4086 .user = OCP_USER_IVA,
4087 };
4088
4089 /* l3_main_2 -> iva */
4090 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
4091 .master = &omap44xx_l3_main_2_hwmod,
4092 .slave = &omap44xx_iva_hwmod,
4093 .clk = "l3_div_ck",
4094 .user = OCP_USER_MPU,
4095 };
4096
4097 /* l4_wkup -> kbd */
4098 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
4099 .master = &omap44xx_l4_wkup_hwmod,
4100 .slave = &omap44xx_kbd_hwmod,
4101 .clk = "l4_wkup_clk_mux_ck",
4102 .user = OCP_USER_MPU | OCP_USER_SDMA,
4103 };
4104
4105 /* l4_cfg -> mailbox */
4106 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
4107 .master = &omap44xx_l4_cfg_hwmod,
4108 .slave = &omap44xx_mailbox_hwmod,
4109 .clk = "l4_div_ck",
4110 .user = OCP_USER_MPU | OCP_USER_SDMA,
4111 };
4112
4113 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
4114 {
4115 .pa_start = 0x40128000,
4116 .pa_end = 0x401283ff,
4117 .flags = ADDR_TYPE_RT
4118 },
4119 { }
4120 };
4121
4122 /* l4_abe -> mcasp */
4123 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
4124 .master = &omap44xx_l4_abe_hwmod,
4125 .slave = &omap44xx_mcasp_hwmod,
4126 .clk = "ocp_abe_iclk",
4127 .addr = omap44xx_mcasp_addrs,
4128 .user = OCP_USER_MPU,
4129 };
4130
4131 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
4132 {
4133 .pa_start = 0x49028000,
4134 .pa_end = 0x490283ff,
4135 .flags = ADDR_TYPE_RT
4136 },
4137 { }
4138 };
4139
4140 /* l4_abe -> mcasp (dma) */
4141 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
4142 .master = &omap44xx_l4_abe_hwmod,
4143 .slave = &omap44xx_mcasp_hwmod,
4144 .clk = "ocp_abe_iclk",
4145 .addr = omap44xx_mcasp_dma_addrs,
4146 .user = OCP_USER_SDMA,
4147 };
4148
4149 /* l4_abe -> mcbsp1 */
4150 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
4151 .master = &omap44xx_l4_abe_hwmod,
4152 .slave = &omap44xx_mcbsp1_hwmod,
4153 .clk = "ocp_abe_iclk",
4154 .user = OCP_USER_MPU | OCP_USER_SDMA,
4155 };
4156
4157 /* l4_abe -> mcbsp2 */
4158 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
4159 .master = &omap44xx_l4_abe_hwmod,
4160 .slave = &omap44xx_mcbsp2_hwmod,
4161 .clk = "ocp_abe_iclk",
4162 .user = OCP_USER_MPU | OCP_USER_SDMA,
4163 };
4164
4165 /* l4_abe -> mcbsp3 */
4166 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
4167 .master = &omap44xx_l4_abe_hwmod,
4168 .slave = &omap44xx_mcbsp3_hwmod,
4169 .clk = "ocp_abe_iclk",
4170 .user = OCP_USER_MPU | OCP_USER_SDMA,
4171 };
4172
4173 /* l4_per -> mcbsp4 */
4174 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
4175 .master = &omap44xx_l4_per_hwmod,
4176 .slave = &omap44xx_mcbsp4_hwmod,
4177 .clk = "l4_div_ck",
4178 .user = OCP_USER_MPU | OCP_USER_SDMA,
4179 };
4180
4181 /* l4_abe -> mcpdm */
4182 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
4183 .master = &omap44xx_l4_abe_hwmod,
4184 .slave = &omap44xx_mcpdm_hwmod,
4185 .clk = "ocp_abe_iclk",
4186 .user = OCP_USER_MPU | OCP_USER_SDMA,
4187 };
4188
4189 /* l4_per -> mcspi1 */
4190 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
4191 .master = &omap44xx_l4_per_hwmod,
4192 .slave = &omap44xx_mcspi1_hwmod,
4193 .clk = "l4_div_ck",
4194 .user = OCP_USER_MPU | OCP_USER_SDMA,
4195 };
4196
4197 /* l4_per -> mcspi2 */
4198 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
4199 .master = &omap44xx_l4_per_hwmod,
4200 .slave = &omap44xx_mcspi2_hwmod,
4201 .clk = "l4_div_ck",
4202 .user = OCP_USER_MPU | OCP_USER_SDMA,
4203 };
4204
4205 /* l4_per -> mcspi3 */
4206 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
4207 .master = &omap44xx_l4_per_hwmod,
4208 .slave = &omap44xx_mcspi3_hwmod,
4209 .clk = "l4_div_ck",
4210 .user = OCP_USER_MPU | OCP_USER_SDMA,
4211 };
4212
4213 /* l4_per -> mcspi4 */
4214 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
4215 .master = &omap44xx_l4_per_hwmod,
4216 .slave = &omap44xx_mcspi4_hwmod,
4217 .clk = "l4_div_ck",
4218 .user = OCP_USER_MPU | OCP_USER_SDMA,
4219 };
4220
4221 /* l4_per -> mmc1 */
4222 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
4223 .master = &omap44xx_l4_per_hwmod,
4224 .slave = &omap44xx_mmc1_hwmod,
4225 .clk = "l4_div_ck",
4226 .user = OCP_USER_MPU | OCP_USER_SDMA,
4227 };
4228
4229 /* l4_per -> mmc2 */
4230 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
4231 .master = &omap44xx_l4_per_hwmod,
4232 .slave = &omap44xx_mmc2_hwmod,
4233 .clk = "l4_div_ck",
4234 .user = OCP_USER_MPU | OCP_USER_SDMA,
4235 };
4236
4237 /* l4_per -> mmc3 */
4238 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
4239 .master = &omap44xx_l4_per_hwmod,
4240 .slave = &omap44xx_mmc3_hwmod,
4241 .clk = "l4_div_ck",
4242 .user = OCP_USER_MPU | OCP_USER_SDMA,
4243 };
4244
4245 /* l4_per -> mmc4 */
4246 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
4247 .master = &omap44xx_l4_per_hwmod,
4248 .slave = &omap44xx_mmc4_hwmod,
4249 .clk = "l4_div_ck",
4250 .user = OCP_USER_MPU | OCP_USER_SDMA,
4251 };
4252
4253 /* l4_per -> mmc5 */
4254 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
4255 .master = &omap44xx_l4_per_hwmod,
4256 .slave = &omap44xx_mmc5_hwmod,
4257 .clk = "l4_div_ck",
4258 .user = OCP_USER_MPU | OCP_USER_SDMA,
4259 };
4260
4261 /* l3_main_2 -> ocmc_ram */
4262 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
4263 .master = &omap44xx_l3_main_2_hwmod,
4264 .slave = &omap44xx_ocmc_ram_hwmod,
4265 .clk = "l3_div_ck",
4266 .user = OCP_USER_MPU | OCP_USER_SDMA,
4267 };
4268
4269 /* l4_cfg -> ocp2scp_usb_phy */
4270 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
4271 .master = &omap44xx_l4_cfg_hwmod,
4272 .slave = &omap44xx_ocp2scp_usb_phy_hwmod,
4273 .clk = "l4_div_ck",
4274 .user = OCP_USER_MPU | OCP_USER_SDMA,
4275 };
4276
4277 /* mpu_private -> prcm_mpu */
4278 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
4279 .master = &omap44xx_mpu_private_hwmod,
4280 .slave = &omap44xx_prcm_mpu_hwmod,
4281 .clk = "l3_div_ck",
4282 .user = OCP_USER_MPU | OCP_USER_SDMA,
4283 };
4284
4285 /* l4_wkup -> cm_core_aon */
4286 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
4287 .master = &omap44xx_l4_wkup_hwmod,
4288 .slave = &omap44xx_cm_core_aon_hwmod,
4289 .clk = "l4_wkup_clk_mux_ck",
4290 .user = OCP_USER_MPU | OCP_USER_SDMA,
4291 };
4292
4293 /* l4_cfg -> cm_core */
4294 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
4295 .master = &omap44xx_l4_cfg_hwmod,
4296 .slave = &omap44xx_cm_core_hwmod,
4297 .clk = "l4_div_ck",
4298 .user = OCP_USER_MPU | OCP_USER_SDMA,
4299 };
4300
4301 /* l4_wkup -> prm */
4302 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
4303 .master = &omap44xx_l4_wkup_hwmod,
4304 .slave = &omap44xx_prm_hwmod,
4305 .clk = "l4_wkup_clk_mux_ck",
4306 .user = OCP_USER_MPU | OCP_USER_SDMA,
4307 };
4308
4309 /* l4_wkup -> scrm */
4310 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
4311 .master = &omap44xx_l4_wkup_hwmod,
4312 .slave = &omap44xx_scrm_hwmod,
4313 .clk = "l4_wkup_clk_mux_ck",
4314 .user = OCP_USER_MPU | OCP_USER_SDMA,
4315 };
4316
4317 /* l3_main_2 -> sl2if */
4318 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
4319 .master = &omap44xx_l3_main_2_hwmod,
4320 .slave = &omap44xx_sl2if_hwmod,
4321 .clk = "l3_div_ck",
4322 .user = OCP_USER_MPU | OCP_USER_SDMA,
4323 };
4324
4325 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
4326 {
4327 .pa_start = 0x4012c000,
4328 .pa_end = 0x4012c3ff,
4329 .flags = ADDR_TYPE_RT
4330 },
4331 { }
4332 };
4333
4334 /* l4_abe -> slimbus1 */
4335 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
4336 .master = &omap44xx_l4_abe_hwmod,
4337 .slave = &omap44xx_slimbus1_hwmod,
4338 .clk = "ocp_abe_iclk",
4339 .addr = omap44xx_slimbus1_addrs,
4340 .user = OCP_USER_MPU,
4341 };
4342
4343 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
4344 {
4345 .pa_start = 0x4902c000,
4346 .pa_end = 0x4902c3ff,
4347 .flags = ADDR_TYPE_RT
4348 },
4349 { }
4350 };
4351
4352 /* l4_abe -> slimbus1 (dma) */
4353 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
4354 .master = &omap44xx_l4_abe_hwmod,
4355 .slave = &omap44xx_slimbus1_hwmod,
4356 .clk = "ocp_abe_iclk",
4357 .addr = omap44xx_slimbus1_dma_addrs,
4358 .user = OCP_USER_SDMA,
4359 };
4360
4361 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
4362 {
4363 .pa_start = 0x48076000,
4364 .pa_end = 0x480763ff,
4365 .flags = ADDR_TYPE_RT
4366 },
4367 { }
4368 };
4369
4370 /* l4_per -> slimbus2 */
4371 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
4372 .master = &omap44xx_l4_per_hwmod,
4373 .slave = &omap44xx_slimbus2_hwmod,
4374 .clk = "l4_div_ck",
4375 .addr = omap44xx_slimbus2_addrs,
4376 .user = OCP_USER_MPU | OCP_USER_SDMA,
4377 };
4378
4379 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
4380 {
4381 .pa_start = 0x4a0dd000,
4382 .pa_end = 0x4a0dd03f,
4383 .flags = ADDR_TYPE_RT
4384 },
4385 { }
4386 };
4387
4388 /* l4_cfg -> smartreflex_core */
4389 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
4390 .master = &omap44xx_l4_cfg_hwmod,
4391 .slave = &omap44xx_smartreflex_core_hwmod,
4392 .clk = "l4_div_ck",
4393 .addr = omap44xx_smartreflex_core_addrs,
4394 .user = OCP_USER_MPU | OCP_USER_SDMA,
4395 };
4396
4397 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
4398 {
4399 .pa_start = 0x4a0db000,
4400 .pa_end = 0x4a0db03f,
4401 .flags = ADDR_TYPE_RT
4402 },
4403 { }
4404 };
4405
4406 /* l4_cfg -> smartreflex_iva */
4407 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
4408 .master = &omap44xx_l4_cfg_hwmod,
4409 .slave = &omap44xx_smartreflex_iva_hwmod,
4410 .clk = "l4_div_ck",
4411 .addr = omap44xx_smartreflex_iva_addrs,
4412 .user = OCP_USER_MPU | OCP_USER_SDMA,
4413 };
4414
4415 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
4416 {
4417 .pa_start = 0x4a0d9000,
4418 .pa_end = 0x4a0d903f,
4419 .flags = ADDR_TYPE_RT
4420 },
4421 { }
4422 };
4423
4424 /* l4_cfg -> smartreflex_mpu */
4425 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
4426 .master = &omap44xx_l4_cfg_hwmod,
4427 .slave = &omap44xx_smartreflex_mpu_hwmod,
4428 .clk = "l4_div_ck",
4429 .addr = omap44xx_smartreflex_mpu_addrs,
4430 .user = OCP_USER_MPU | OCP_USER_SDMA,
4431 };
4432
4433 /* l4_cfg -> spinlock */
4434 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
4435 .master = &omap44xx_l4_cfg_hwmod,
4436 .slave = &omap44xx_spinlock_hwmod,
4437 .clk = "l4_div_ck",
4438 .user = OCP_USER_MPU | OCP_USER_SDMA,
4439 };
4440
4441 /* l4_wkup -> timer1 */
4442 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4443 .master = &omap44xx_l4_wkup_hwmod,
4444 .slave = &omap44xx_timer1_hwmod,
4445 .clk = "l4_wkup_clk_mux_ck",
4446 .user = OCP_USER_MPU | OCP_USER_SDMA,
4447 };
4448
4449 /* l4_per -> timer2 */
4450 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4451 .master = &omap44xx_l4_per_hwmod,
4452 .slave = &omap44xx_timer2_hwmod,
4453 .clk = "l4_div_ck",
4454 .user = OCP_USER_MPU | OCP_USER_SDMA,
4455 };
4456
4457 /* l4_per -> timer3 */
4458 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4459 .master = &omap44xx_l4_per_hwmod,
4460 .slave = &omap44xx_timer3_hwmod,
4461 .clk = "l4_div_ck",
4462 .user = OCP_USER_MPU | OCP_USER_SDMA,
4463 };
4464
4465 /* l4_per -> timer4 */
4466 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4467 .master = &omap44xx_l4_per_hwmod,
4468 .slave = &omap44xx_timer4_hwmod,
4469 .clk = "l4_div_ck",
4470 .user = OCP_USER_MPU | OCP_USER_SDMA,
4471 };
4472
4473 /* l4_abe -> timer5 */
4474 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4475 .master = &omap44xx_l4_abe_hwmod,
4476 .slave = &omap44xx_timer5_hwmod,
4477 .clk = "ocp_abe_iclk",
4478 .user = OCP_USER_MPU | OCP_USER_SDMA,
4479 };
4480
4481 /* l4_abe -> timer6 */
4482 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4483 .master = &omap44xx_l4_abe_hwmod,
4484 .slave = &omap44xx_timer6_hwmod,
4485 .clk = "ocp_abe_iclk",
4486 .user = OCP_USER_MPU | OCP_USER_SDMA,
4487 };
4488
4489 /* l4_abe -> timer7 */
4490 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4491 .master = &omap44xx_l4_abe_hwmod,
4492 .slave = &omap44xx_timer7_hwmod,
4493 .clk = "ocp_abe_iclk",
4494 .user = OCP_USER_MPU | OCP_USER_SDMA,
4495 };
4496
4497 /* l4_abe -> timer8 */
4498 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4499 .master = &omap44xx_l4_abe_hwmod,
4500 .slave = &omap44xx_timer8_hwmod,
4501 .clk = "ocp_abe_iclk",
4502 .user = OCP_USER_MPU | OCP_USER_SDMA,
4503 };
4504
4505 /* l4_per -> timer9 */
4506 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4507 .master = &omap44xx_l4_per_hwmod,
4508 .slave = &omap44xx_timer9_hwmod,
4509 .clk = "l4_div_ck",
4510 .user = OCP_USER_MPU | OCP_USER_SDMA,
4511 };
4512
4513 /* l4_per -> timer10 */
4514 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4515 .master = &omap44xx_l4_per_hwmod,
4516 .slave = &omap44xx_timer10_hwmod,
4517 .clk = "l4_div_ck",
4518 .user = OCP_USER_MPU | OCP_USER_SDMA,
4519 };
4520
4521 /* l4_per -> timer11 */
4522 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4523 .master = &omap44xx_l4_per_hwmod,
4524 .slave = &omap44xx_timer11_hwmod,
4525 .clk = "l4_div_ck",
4526 .user = OCP_USER_MPU | OCP_USER_SDMA,
4527 };
4528
4529 /* l4_per -> uart1 */
4530 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4531 .master = &omap44xx_l4_per_hwmod,
4532 .slave = &omap44xx_uart1_hwmod,
4533 .clk = "l4_div_ck",
4534 .user = OCP_USER_MPU | OCP_USER_SDMA,
4535 };
4536
4537 /* l4_per -> uart2 */
4538 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4539 .master = &omap44xx_l4_per_hwmod,
4540 .slave = &omap44xx_uart2_hwmod,
4541 .clk = "l4_div_ck",
4542 .user = OCP_USER_MPU | OCP_USER_SDMA,
4543 };
4544
4545 /* l4_per -> uart3 */
4546 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4547 .master = &omap44xx_l4_per_hwmod,
4548 .slave = &omap44xx_uart3_hwmod,
4549 .clk = "l4_div_ck",
4550 .user = OCP_USER_MPU | OCP_USER_SDMA,
4551 };
4552
4553 /* l4_per -> uart4 */
4554 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
4555 .master = &omap44xx_l4_per_hwmod,
4556 .slave = &omap44xx_uart4_hwmod,
4557 .clk = "l4_div_ck",
4558 .user = OCP_USER_MPU | OCP_USER_SDMA,
4559 };
4560
4561 /* l4_cfg -> usb_host_fs */
4562 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
4563 .master = &omap44xx_l4_cfg_hwmod,
4564 .slave = &omap44xx_usb_host_fs_hwmod,
4565 .clk = "l4_div_ck",
4566 .user = OCP_USER_MPU | OCP_USER_SDMA,
4567 };
4568
4569 /* l4_cfg -> usb_host_hs */
4570 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
4571 .master = &omap44xx_l4_cfg_hwmod,
4572 .slave = &omap44xx_usb_host_hs_hwmod,
4573 .clk = "l4_div_ck",
4574 .user = OCP_USER_MPU | OCP_USER_SDMA,
4575 };
4576
4577 /* l4_cfg -> usb_otg_hs */
4578 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
4579 .master = &omap44xx_l4_cfg_hwmod,
4580 .slave = &omap44xx_usb_otg_hs_hwmod,
4581 .clk = "l4_div_ck",
4582 .user = OCP_USER_MPU | OCP_USER_SDMA,
4583 };
4584
4585 /* l4_cfg -> usb_tll_hs */
4586 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
4587 .master = &omap44xx_l4_cfg_hwmod,
4588 .slave = &omap44xx_usb_tll_hs_hwmod,
4589 .clk = "l4_div_ck",
4590 .user = OCP_USER_MPU | OCP_USER_SDMA,
4591 };
4592
4593 /* l4_wkup -> wd_timer2 */
4594 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
4595 .master = &omap44xx_l4_wkup_hwmod,
4596 .slave = &omap44xx_wd_timer2_hwmod,
4597 .clk = "l4_wkup_clk_mux_ck",
4598 .user = OCP_USER_MPU | OCP_USER_SDMA,
4599 };
4600
4601 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
4602 {
4603 .pa_start = 0x40130000,
4604 .pa_end = 0x4013007f,
4605 .flags = ADDR_TYPE_RT
4606 },
4607 { }
4608 };
4609
4610 /* l4_abe -> wd_timer3 */
4611 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
4612 .master = &omap44xx_l4_abe_hwmod,
4613 .slave = &omap44xx_wd_timer3_hwmod,
4614 .clk = "ocp_abe_iclk",
4615 .addr = omap44xx_wd_timer3_addrs,
4616 .user = OCP_USER_MPU,
4617 };
4618
4619 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
4620 {
4621 .pa_start = 0x49030000,
4622 .pa_end = 0x4903007f,
4623 .flags = ADDR_TYPE_RT
4624 },
4625 { }
4626 };
4627
4628 /* l4_abe -> wd_timer3 (dma) */
4629 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
4630 .master = &omap44xx_l4_abe_hwmod,
4631 .slave = &omap44xx_wd_timer3_hwmod,
4632 .clk = "ocp_abe_iclk",
4633 .addr = omap44xx_wd_timer3_dma_addrs,
4634 .user = OCP_USER_SDMA,
4635 };
4636
4637 /* mpu -> emif1 */
4638 static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
4639 .master = &omap44xx_mpu_hwmod,
4640 .slave = &omap44xx_emif1_hwmod,
4641 .clk = "l3_div_ck",
4642 .user = OCP_USER_MPU | OCP_USER_SDMA,
4643 };
4644
4645 /* mpu -> emif2 */
4646 static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
4647 .master = &omap44xx_mpu_hwmod,
4648 .slave = &omap44xx_emif2_hwmod,
4649 .clk = "l3_div_ck",
4650 .user = OCP_USER_MPU | OCP_USER_SDMA,
4651 };
4652
4653 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
4654 &omap44xx_l3_main_1__dmm,
4655 &omap44xx_mpu__dmm,
4656 &omap44xx_iva__l3_instr,
4657 &omap44xx_l3_main_3__l3_instr,
4658 &omap44xx_ocp_wp_noc__l3_instr,
4659 &omap44xx_dsp__l3_main_1,
4660 &omap44xx_dss__l3_main_1,
4661 &omap44xx_l3_main_2__l3_main_1,
4662 &omap44xx_l4_cfg__l3_main_1,
4663 &omap44xx_mmc1__l3_main_1,
4664 &omap44xx_mmc2__l3_main_1,
4665 &omap44xx_mpu__l3_main_1,
4666 &omap44xx_debugss__l3_main_2,
4667 &omap44xx_dma_system__l3_main_2,
4668 &omap44xx_fdif__l3_main_2,
4669 &omap44xx_gpu__l3_main_2,
4670 &omap44xx_hsi__l3_main_2,
4671 &omap44xx_ipu__l3_main_2,
4672 &omap44xx_iss__l3_main_2,
4673 &omap44xx_iva__l3_main_2,
4674 &omap44xx_l3_main_1__l3_main_2,
4675 &omap44xx_l4_cfg__l3_main_2,
4676 /* &omap44xx_usb_host_fs__l3_main_2, */
4677 &omap44xx_usb_host_hs__l3_main_2,
4678 &omap44xx_usb_otg_hs__l3_main_2,
4679 &omap44xx_l3_main_1__l3_main_3,
4680 &omap44xx_l3_main_2__l3_main_3,
4681 &omap44xx_l4_cfg__l3_main_3,
4682 &omap44xx_aess__l4_abe,
4683 &omap44xx_dsp__l4_abe,
4684 &omap44xx_l3_main_1__l4_abe,
4685 &omap44xx_mpu__l4_abe,
4686 &omap44xx_l3_main_1__l4_cfg,
4687 &omap44xx_l3_main_2__l4_per,
4688 &omap44xx_l4_cfg__l4_wkup,
4689 &omap44xx_mpu__mpu_private,
4690 &omap44xx_l4_cfg__ocp_wp_noc,
4691 &omap44xx_l4_abe__aess,
4692 &omap44xx_l4_abe__aess_dma,
4693 &omap44xx_l3_main_2__c2c,
4694 &omap44xx_l4_wkup__counter_32k,
4695 &omap44xx_l4_cfg__ctrl_module_core,
4696 &omap44xx_l4_cfg__ctrl_module_pad_core,
4697 &omap44xx_l4_wkup__ctrl_module_wkup,
4698 &omap44xx_l4_wkup__ctrl_module_pad_wkup,
4699 &omap44xx_l3_instr__debugss,
4700 &omap44xx_l4_cfg__dma_system,
4701 &omap44xx_l4_abe__dmic,
4702 &omap44xx_dsp__iva,
4703 /* &omap44xx_dsp__sl2if, */
4704 &omap44xx_l4_cfg__dsp,
4705 &omap44xx_l3_main_2__dss,
4706 &omap44xx_l4_per__dss,
4707 &omap44xx_l3_main_2__dss_dispc,
4708 &omap44xx_l4_per__dss_dispc,
4709 &omap44xx_l3_main_2__dss_dsi1,
4710 &omap44xx_l4_per__dss_dsi1,
4711 &omap44xx_l3_main_2__dss_dsi2,
4712 &omap44xx_l4_per__dss_dsi2,
4713 &omap44xx_l3_main_2__dss_hdmi,
4714 &omap44xx_l4_per__dss_hdmi,
4715 &omap44xx_l3_main_2__dss_rfbi,
4716 &omap44xx_l4_per__dss_rfbi,
4717 &omap44xx_l3_main_2__dss_venc,
4718 &omap44xx_l4_per__dss_venc,
4719 &omap44xx_l4_per__elm,
4720 &omap44xx_l4_cfg__fdif,
4721 &omap44xx_l4_wkup__gpio1,
4722 &omap44xx_l4_per__gpio2,
4723 &omap44xx_l4_per__gpio3,
4724 &omap44xx_l4_per__gpio4,
4725 &omap44xx_l4_per__gpio5,
4726 &omap44xx_l4_per__gpio6,
4727 &omap44xx_l3_main_2__gpmc,
4728 &omap44xx_l3_main_2__gpu,
4729 &omap44xx_l4_per__hdq1w,
4730 &omap44xx_l4_cfg__hsi,
4731 &omap44xx_l4_per__i2c1,
4732 &omap44xx_l4_per__i2c2,
4733 &omap44xx_l4_per__i2c3,
4734 &omap44xx_l4_per__i2c4,
4735 &omap44xx_l3_main_2__ipu,
4736 &omap44xx_l3_main_2__iss,
4737 /* &omap44xx_iva__sl2if, */
4738 &omap44xx_l3_main_2__iva,
4739 &omap44xx_l4_wkup__kbd,
4740 &omap44xx_l4_cfg__mailbox,
4741 &omap44xx_l4_abe__mcasp,
4742 &omap44xx_l4_abe__mcasp_dma,
4743 &omap44xx_l4_abe__mcbsp1,
4744 &omap44xx_l4_abe__mcbsp2,
4745 &omap44xx_l4_abe__mcbsp3,
4746 &omap44xx_l4_per__mcbsp4,
4747 &omap44xx_l4_abe__mcpdm,
4748 &omap44xx_l4_per__mcspi1,
4749 &omap44xx_l4_per__mcspi2,
4750 &omap44xx_l4_per__mcspi3,
4751 &omap44xx_l4_per__mcspi4,
4752 &omap44xx_l4_per__mmc1,
4753 &omap44xx_l4_per__mmc2,
4754 &omap44xx_l4_per__mmc3,
4755 &omap44xx_l4_per__mmc4,
4756 &omap44xx_l4_per__mmc5,
4757 &omap44xx_l3_main_2__mmu_ipu,
4758 &omap44xx_l4_cfg__mmu_dsp,
4759 &omap44xx_l3_main_2__ocmc_ram,
4760 &omap44xx_l4_cfg__ocp2scp_usb_phy,
4761 &omap44xx_mpu_private__prcm_mpu,
4762 &omap44xx_l4_wkup__cm_core_aon,
4763 &omap44xx_l4_cfg__cm_core,
4764 &omap44xx_l4_wkup__prm,
4765 &omap44xx_l4_wkup__scrm,
4766 /* &omap44xx_l3_main_2__sl2if, */
4767 &omap44xx_l4_abe__slimbus1,
4768 &omap44xx_l4_abe__slimbus1_dma,
4769 &omap44xx_l4_per__slimbus2,
4770 &omap44xx_l4_cfg__smartreflex_core,
4771 &omap44xx_l4_cfg__smartreflex_iva,
4772 &omap44xx_l4_cfg__smartreflex_mpu,
4773 &omap44xx_l4_cfg__spinlock,
4774 &omap44xx_l4_wkup__timer1,
4775 &omap44xx_l4_per__timer2,
4776 &omap44xx_l4_per__timer3,
4777 &omap44xx_l4_per__timer4,
4778 &omap44xx_l4_abe__timer5,
4779 &omap44xx_l4_abe__timer6,
4780 &omap44xx_l4_abe__timer7,
4781 &omap44xx_l4_abe__timer8,
4782 &omap44xx_l4_per__timer9,
4783 &omap44xx_l4_per__timer10,
4784 &omap44xx_l4_per__timer11,
4785 &omap44xx_l4_per__uart1,
4786 &omap44xx_l4_per__uart2,
4787 &omap44xx_l4_per__uart3,
4788 &omap44xx_l4_per__uart4,
4789 /* &omap44xx_l4_cfg__usb_host_fs, */
4790 &omap44xx_l4_cfg__usb_host_hs,
4791 &omap44xx_l4_cfg__usb_otg_hs,
4792 &omap44xx_l4_cfg__usb_tll_hs,
4793 &omap44xx_l4_wkup__wd_timer2,
4794 &omap44xx_l4_abe__wd_timer3,
4795 &omap44xx_l4_abe__wd_timer3_dma,
4796 &omap44xx_mpu__emif1,
4797 &omap44xx_mpu__emif2,
4798 NULL,
4799 };
4800
4801 int __init omap44xx_hwmod_init(void)
4802 {
4803 omap_hwmod_init();
4804 return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
4805 }
4806
Linux kernel - Deliverables
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