2 * Hardware modules present on the OMAP44xx chips
4 * Copyright (C) 2009-2012 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
23 #include <plat/omap_hwmod.h>
26 #include <plat/gpio.h>
28 #include <plat/mcspi.h>
29 #include <plat/mcbsp.h>
31 #include <plat/dmtimer.h>
32 #include <plat/common.h>
34 #include "omap_hwmod_common_data.h"
36 #include "smartreflex.h"
40 #include "prm-regbits-44xx.h"
43 /* Base offset for all OMAP4 interrupts external to MPUSS */
44 #define OMAP44XX_IRQ_GIC_START 32
46 /* Base offset for all OMAP4 dma requests */
47 #define OMAP44XX_DMA_REQ_START 1
54 * 'c2c_target_fw' class
55 * instance(s): c2c_target_fw
57 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class
= {
58 .name
= "c2c_target_fw",
62 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod
= {
63 .name
= "c2c_target_fw",
64 .class = &omap44xx_c2c_target_fw_hwmod_class
,
65 .clkdm_name
= "d2d_clkdm",
68 .clkctrl_offs
= OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET
,
69 .context_offs
= OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET
,
78 static struct omap_hwmod_class omap44xx_dmm_hwmod_class
= {
83 static struct omap_hwmod_irq_info omap44xx_dmm_irqs
[] = {
84 { .irq
= 113 + OMAP44XX_IRQ_GIC_START
},
88 static struct omap_hwmod omap44xx_dmm_hwmod
= {
90 .class = &omap44xx_dmm_hwmod_class
,
91 .clkdm_name
= "l3_emif_clkdm",
92 .mpu_irqs
= omap44xx_dmm_irqs
,
95 .clkctrl_offs
= OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET
,
96 .context_offs
= OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET
,
103 * instance(s): emif_fw
105 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class
= {
110 static struct omap_hwmod omap44xx_emif_fw_hwmod
= {
112 .class = &omap44xx_emif_fw_hwmod_class
,
113 .clkdm_name
= "l3_emif_clkdm",
116 .clkctrl_offs
= OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET
,
117 .context_offs
= OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET
,
124 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
126 static struct omap_hwmod_class omap44xx_l3_hwmod_class
= {
131 static struct omap_hwmod omap44xx_l3_instr_hwmod
= {
133 .class = &omap44xx_l3_hwmod_class
,
134 .clkdm_name
= "l3_instr_clkdm",
137 .clkctrl_offs
= OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET
,
138 .context_offs
= OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET
,
139 .modulemode
= MODULEMODE_HWCTRL
,
145 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs
[] = {
146 { .name
= "dbg_err", .irq
= 9 + OMAP44XX_IRQ_GIC_START
},
147 { .name
= "app_err", .irq
= 10 + OMAP44XX_IRQ_GIC_START
},
151 static struct omap_hwmod omap44xx_l3_main_1_hwmod
= {
153 .class = &omap44xx_l3_hwmod_class
,
154 .clkdm_name
= "l3_1_clkdm",
155 .mpu_irqs
= omap44xx_l3_main_1_irqs
,
158 .clkctrl_offs
= OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET
,
159 .context_offs
= OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET
,
165 static struct omap_hwmod omap44xx_l3_main_2_hwmod
= {
167 .class = &omap44xx_l3_hwmod_class
,
168 .clkdm_name
= "l3_2_clkdm",
171 .clkctrl_offs
= OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET
,
172 .context_offs
= OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET
,
178 static struct omap_hwmod omap44xx_l3_main_3_hwmod
= {
180 .class = &omap44xx_l3_hwmod_class
,
181 .clkdm_name
= "l3_instr_clkdm",
184 .clkctrl_offs
= OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET
,
185 .context_offs
= OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET
,
186 .modulemode
= MODULEMODE_HWCTRL
,
193 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
195 static struct omap_hwmod_class omap44xx_l4_hwmod_class
= {
200 static struct omap_hwmod omap44xx_l4_abe_hwmod
= {
202 .class = &omap44xx_l4_hwmod_class
,
203 .clkdm_name
= "abe_clkdm",
206 .clkctrl_offs
= OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET
,
212 static struct omap_hwmod omap44xx_l4_cfg_hwmod
= {
214 .class = &omap44xx_l4_hwmod_class
,
215 .clkdm_name
= "l4_cfg_clkdm",
218 .clkctrl_offs
= OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET
,
219 .context_offs
= OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET
,
225 static struct omap_hwmod omap44xx_l4_per_hwmod
= {
227 .class = &omap44xx_l4_hwmod_class
,
228 .clkdm_name
= "l4_per_clkdm",
231 .clkctrl_offs
= OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET
,
232 .context_offs
= OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET
,
238 static struct omap_hwmod omap44xx_l4_wkup_hwmod
= {
240 .class = &omap44xx_l4_hwmod_class
,
241 .clkdm_name
= "l4_wkup_clkdm",
244 .clkctrl_offs
= OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET
,
245 .context_offs
= OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET
,
252 * instance(s): mpu_private
254 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class
= {
259 static struct omap_hwmod omap44xx_mpu_private_hwmod
= {
260 .name
= "mpu_private",
261 .class = &omap44xx_mpu_bus_hwmod_class
,
262 .clkdm_name
= "mpuss_clkdm",
267 * instance(s): ocp_wp_noc
269 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class
= {
270 .name
= "ocp_wp_noc",
274 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod
= {
275 .name
= "ocp_wp_noc",
276 .class = &omap44xx_ocp_wp_noc_hwmod_class
,
277 .clkdm_name
= "l3_instr_clkdm",
280 .clkctrl_offs
= OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET
,
281 .context_offs
= OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET
,
282 .modulemode
= MODULEMODE_HWCTRL
,
288 * Modules omap_hwmod structures
290 * The following IPs are excluded for the moment because:
291 * - They do not need an explicit SW control using omap_hwmod API.
292 * - They still need to be validated with the driver
293 * properly adapted to omap_hwmod / omap_device
300 * audio engine sub system
303 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc
= {
306 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
),
307 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
308 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
|
309 MSTANDBY_SMART_WKUP
),
310 .sysc_fields
= &omap_hwmod_sysc_type2
,
313 static struct omap_hwmod_class omap44xx_aess_hwmod_class
= {
315 .sysc
= &omap44xx_aess_sysc
,
319 static struct omap_hwmod_irq_info omap44xx_aess_irqs
[] = {
320 { .irq
= 99 + OMAP44XX_IRQ_GIC_START
},
324 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs
[] = {
325 { .name
= "fifo0", .dma_req
= 100 + OMAP44XX_DMA_REQ_START
},
326 { .name
= "fifo1", .dma_req
= 101 + OMAP44XX_DMA_REQ_START
},
327 { .name
= "fifo2", .dma_req
= 102 + OMAP44XX_DMA_REQ_START
},
328 { .name
= "fifo3", .dma_req
= 103 + OMAP44XX_DMA_REQ_START
},
329 { .name
= "fifo4", .dma_req
= 104 + OMAP44XX_DMA_REQ_START
},
330 { .name
= "fifo5", .dma_req
= 105 + OMAP44XX_DMA_REQ_START
},
331 { .name
= "fifo6", .dma_req
= 106 + OMAP44XX_DMA_REQ_START
},
332 { .name
= "fifo7", .dma_req
= 107 + OMAP44XX_DMA_REQ_START
},
336 static struct omap_hwmod omap44xx_aess_hwmod
= {
338 .class = &omap44xx_aess_hwmod_class
,
339 .clkdm_name
= "abe_clkdm",
340 .mpu_irqs
= omap44xx_aess_irqs
,
341 .sdma_reqs
= omap44xx_aess_sdma_reqs
,
342 .main_clk
= "aess_fck",
345 .clkctrl_offs
= OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET
,
346 .context_offs
= OMAP4_RM_ABE_AESS_CONTEXT_OFFSET
,
347 .modulemode
= MODULEMODE_SWCTRL
,
354 * chip 2 chip interface used to plug the ape soc (omap) with an external modem
358 static struct omap_hwmod_class omap44xx_c2c_hwmod_class
= {
363 static struct omap_hwmod_irq_info omap44xx_c2c_irqs
[] = {
364 { .irq
= 88 + OMAP44XX_IRQ_GIC_START
},
368 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs
[] = {
369 { .dma_req
= 68 + OMAP44XX_DMA_REQ_START
},
373 static struct omap_hwmod omap44xx_c2c_hwmod
= {
375 .class = &omap44xx_c2c_hwmod_class
,
376 .clkdm_name
= "d2d_clkdm",
377 .mpu_irqs
= omap44xx_c2c_irqs
,
378 .sdma_reqs
= omap44xx_c2c_sdma_reqs
,
381 .clkctrl_offs
= OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET
,
382 .context_offs
= OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET
,
389 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
392 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc
= {
395 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
396 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
398 .sysc_fields
= &omap_hwmod_sysc_type1
,
401 static struct omap_hwmod_class omap44xx_counter_hwmod_class
= {
403 .sysc
= &omap44xx_counter_sysc
,
407 static struct omap_hwmod omap44xx_counter_32k_hwmod
= {
408 .name
= "counter_32k",
409 .class = &omap44xx_counter_hwmod_class
,
410 .clkdm_name
= "l4_wkup_clkdm",
411 .flags
= HWMOD_SWSUP_SIDLE
,
412 .main_clk
= "sys_32k_ck",
415 .clkctrl_offs
= OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET
,
416 .context_offs
= OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET
,
422 * 'ctrl_module' class
423 * attila core control module + core pad control module + wkup pad control
424 * module + attila wkup control module
427 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc
= {
430 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
431 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
433 .sysc_fields
= &omap_hwmod_sysc_type2
,
436 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class
= {
437 .name
= "ctrl_module",
438 .sysc
= &omap44xx_ctrl_module_sysc
,
441 /* ctrl_module_core */
442 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs
[] = {
443 { .irq
= 8 + OMAP44XX_IRQ_GIC_START
},
447 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod
= {
448 .name
= "ctrl_module_core",
449 .class = &omap44xx_ctrl_module_hwmod_class
,
450 .clkdm_name
= "l4_cfg_clkdm",
451 .mpu_irqs
= omap44xx_ctrl_module_core_irqs
,
454 /* ctrl_module_pad_core */
455 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod
= {
456 .name
= "ctrl_module_pad_core",
457 .class = &omap44xx_ctrl_module_hwmod_class
,
458 .clkdm_name
= "l4_cfg_clkdm",
461 /* ctrl_module_wkup */
462 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod
= {
463 .name
= "ctrl_module_wkup",
464 .class = &omap44xx_ctrl_module_hwmod_class
,
465 .clkdm_name
= "l4_wkup_clkdm",
468 /* ctrl_module_pad_wkup */
469 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod
= {
470 .name
= "ctrl_module_pad_wkup",
471 .class = &omap44xx_ctrl_module_hwmod_class
,
472 .clkdm_name
= "l4_wkup_clkdm",
477 * debug and emulation sub system
480 static struct omap_hwmod_class omap44xx_debugss_hwmod_class
= {
485 static struct omap_hwmod omap44xx_debugss_hwmod
= {
487 .class = &omap44xx_debugss_hwmod_class
,
488 .clkdm_name
= "emu_sys_clkdm",
489 .main_clk
= "trace_clk_div_ck",
492 .clkctrl_offs
= OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET
,
493 .context_offs
= OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET
,
500 * dma controller for data exchange between memory to memory (i.e. internal or
501 * external memory) and gp peripherals to memory or memory to gp peripherals
504 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc
= {
508 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
509 SYSC_HAS_EMUFREE
| SYSC_HAS_MIDLEMODE
|
510 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
511 SYSS_HAS_RESET_STATUS
),
512 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
513 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
514 .sysc_fields
= &omap_hwmod_sysc_type1
,
517 static struct omap_hwmod_class omap44xx_dma_hwmod_class
= {
519 .sysc
= &omap44xx_dma_sysc
,
523 static struct omap_dma_dev_attr dma_dev_attr
= {
524 .dev_caps
= RESERVE_CHANNEL
| DMA_LINKED_LCH
| GLOBAL_PRIORITY
|
525 IS_CSSA_32
| IS_CDSA_32
| IS_RW_PRIORITY
,
530 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs
[] = {
531 { .name
= "0", .irq
= 12 + OMAP44XX_IRQ_GIC_START
},
532 { .name
= "1", .irq
= 13 + OMAP44XX_IRQ_GIC_START
},
533 { .name
= "2", .irq
= 14 + OMAP44XX_IRQ_GIC_START
},
534 { .name
= "3", .irq
= 15 + OMAP44XX_IRQ_GIC_START
},
538 static struct omap_hwmod omap44xx_dma_system_hwmod
= {
539 .name
= "dma_system",
540 .class = &omap44xx_dma_hwmod_class
,
541 .clkdm_name
= "l3_dma_clkdm",
542 .mpu_irqs
= omap44xx_dma_system_irqs
,
543 .main_clk
= "l3_div_ck",
546 .clkctrl_offs
= OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET
,
547 .context_offs
= OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET
,
550 .dev_attr
= &dma_dev_attr
,
555 * digital microphone controller
558 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc
= {
561 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
562 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
563 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
565 .sysc_fields
= &omap_hwmod_sysc_type2
,
568 static struct omap_hwmod_class omap44xx_dmic_hwmod_class
= {
570 .sysc
= &omap44xx_dmic_sysc
,
574 static struct omap_hwmod_irq_info omap44xx_dmic_irqs
[] = {
575 { .irq
= 114 + OMAP44XX_IRQ_GIC_START
},
579 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs
[] = {
580 { .dma_req
= 66 + OMAP44XX_DMA_REQ_START
},
584 static struct omap_hwmod omap44xx_dmic_hwmod
= {
586 .class = &omap44xx_dmic_hwmod_class
,
587 .clkdm_name
= "abe_clkdm",
588 .mpu_irqs
= omap44xx_dmic_irqs
,
589 .sdma_reqs
= omap44xx_dmic_sdma_reqs
,
590 .main_clk
= "dmic_fck",
593 .clkctrl_offs
= OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET
,
594 .context_offs
= OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET
,
595 .modulemode
= MODULEMODE_SWCTRL
,
605 static struct omap_hwmod_class omap44xx_dsp_hwmod_class
= {
610 static struct omap_hwmod_irq_info omap44xx_dsp_irqs
[] = {
611 { .irq
= 28 + OMAP44XX_IRQ_GIC_START
},
615 static struct omap_hwmod_rst_info omap44xx_dsp_resets
[] = {
616 { .name
= "dsp", .rst_shift
= 0 },
617 { .name
= "mmu_cache", .rst_shift
= 1 },
620 static struct omap_hwmod omap44xx_dsp_hwmod
= {
622 .class = &omap44xx_dsp_hwmod_class
,
623 .clkdm_name
= "tesla_clkdm",
624 .mpu_irqs
= omap44xx_dsp_irqs
,
625 .rst_lines
= omap44xx_dsp_resets
,
626 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_dsp_resets
),
627 .main_clk
= "dsp_fck",
630 .clkctrl_offs
= OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET
,
631 .rstctrl_offs
= OMAP4_RM_TESLA_RSTCTRL_OFFSET
,
632 .context_offs
= OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET
,
633 .modulemode
= MODULEMODE_HWCTRL
,
643 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc
= {
646 .sysc_flags
= SYSS_HAS_RESET_STATUS
,
649 static struct omap_hwmod_class omap44xx_dss_hwmod_class
= {
651 .sysc
= &omap44xx_dss_sysc
,
652 .reset
= omap_dss_reset
,
656 static struct omap_hwmod_opt_clk dss_opt_clks
[] = {
657 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
658 { .role
= "tv_clk", .clk
= "dss_tv_clk" },
659 { .role
= "hdmi_clk", .clk
= "dss_48mhz_clk" },
662 static struct omap_hwmod omap44xx_dss_hwmod
= {
664 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
665 .class = &omap44xx_dss_hwmod_class
,
666 .clkdm_name
= "l3_dss_clkdm",
667 .main_clk
= "dss_dss_clk",
670 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
671 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
674 .opt_clks
= dss_opt_clks
,
675 .opt_clks_cnt
= ARRAY_SIZE(dss_opt_clks
),
683 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc
= {
687 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
688 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_MIDLEMODE
|
689 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
690 SYSS_HAS_RESET_STATUS
),
691 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
692 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
693 .sysc_fields
= &omap_hwmod_sysc_type1
,
696 static struct omap_hwmod_class omap44xx_dispc_hwmod_class
= {
698 .sysc
= &omap44xx_dispc_sysc
,
702 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs
[] = {
703 { .irq
= 25 + OMAP44XX_IRQ_GIC_START
},
707 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs
[] = {
708 { .dma_req
= 5 + OMAP44XX_DMA_REQ_START
},
712 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr
= {
714 .has_framedonetv_irq
= 1
717 static struct omap_hwmod omap44xx_dss_dispc_hwmod
= {
719 .class = &omap44xx_dispc_hwmod_class
,
720 .clkdm_name
= "l3_dss_clkdm",
721 .mpu_irqs
= omap44xx_dss_dispc_irqs
,
722 .sdma_reqs
= omap44xx_dss_dispc_sdma_reqs
,
723 .main_clk
= "dss_dss_clk",
726 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
727 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
730 .dev_attr
= &omap44xx_dss_dispc_dev_attr
735 * display serial interface controller
738 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc
= {
742 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
743 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
744 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
745 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
746 .sysc_fields
= &omap_hwmod_sysc_type1
,
749 static struct omap_hwmod_class omap44xx_dsi_hwmod_class
= {
751 .sysc
= &omap44xx_dsi_sysc
,
755 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs
[] = {
756 { .irq
= 53 + OMAP44XX_IRQ_GIC_START
},
760 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs
[] = {
761 { .dma_req
= 74 + OMAP44XX_DMA_REQ_START
},
765 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks
[] = {
766 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
769 static struct omap_hwmod omap44xx_dss_dsi1_hwmod
= {
771 .class = &omap44xx_dsi_hwmod_class
,
772 .clkdm_name
= "l3_dss_clkdm",
773 .mpu_irqs
= omap44xx_dss_dsi1_irqs
,
774 .sdma_reqs
= omap44xx_dss_dsi1_sdma_reqs
,
775 .main_clk
= "dss_dss_clk",
778 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
779 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
782 .opt_clks
= dss_dsi1_opt_clks
,
783 .opt_clks_cnt
= ARRAY_SIZE(dss_dsi1_opt_clks
),
787 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs
[] = {
788 { .irq
= 84 + OMAP44XX_IRQ_GIC_START
},
792 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs
[] = {
793 { .dma_req
= 83 + OMAP44XX_DMA_REQ_START
},
797 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks
[] = {
798 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
801 static struct omap_hwmod omap44xx_dss_dsi2_hwmod
= {
803 .class = &omap44xx_dsi_hwmod_class
,
804 .clkdm_name
= "l3_dss_clkdm",
805 .mpu_irqs
= omap44xx_dss_dsi2_irqs
,
806 .sdma_reqs
= omap44xx_dss_dsi2_sdma_reqs
,
807 .main_clk
= "dss_dss_clk",
810 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
811 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
814 .opt_clks
= dss_dsi2_opt_clks
,
815 .opt_clks_cnt
= ARRAY_SIZE(dss_dsi2_opt_clks
),
823 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc
= {
826 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
828 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
830 .sysc_fields
= &omap_hwmod_sysc_type2
,
833 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class
= {
835 .sysc
= &omap44xx_hdmi_sysc
,
839 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs
[] = {
840 { .irq
= 101 + OMAP44XX_IRQ_GIC_START
},
844 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs
[] = {
845 { .dma_req
= 75 + OMAP44XX_DMA_REQ_START
},
849 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks
[] = {
850 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
853 static struct omap_hwmod omap44xx_dss_hdmi_hwmod
= {
855 .class = &omap44xx_hdmi_hwmod_class
,
856 .clkdm_name
= "l3_dss_clkdm",
857 .mpu_irqs
= omap44xx_dss_hdmi_irqs
,
858 .sdma_reqs
= omap44xx_dss_hdmi_sdma_reqs
,
859 .main_clk
= "dss_48mhz_clk",
862 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
863 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
866 .opt_clks
= dss_hdmi_opt_clks
,
867 .opt_clks_cnt
= ARRAY_SIZE(dss_hdmi_opt_clks
),
872 * remote frame buffer interface
875 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc
= {
879 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SIDLEMODE
|
880 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
881 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
882 .sysc_fields
= &omap_hwmod_sysc_type1
,
885 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class
= {
887 .sysc
= &omap44xx_rfbi_sysc
,
891 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs
[] = {
892 { .dma_req
= 13 + OMAP44XX_DMA_REQ_START
},
896 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks
[] = {
897 { .role
= "ick", .clk
= "dss_fck" },
900 static struct omap_hwmod omap44xx_dss_rfbi_hwmod
= {
902 .class = &omap44xx_rfbi_hwmod_class
,
903 .clkdm_name
= "l3_dss_clkdm",
904 .sdma_reqs
= omap44xx_dss_rfbi_sdma_reqs
,
905 .main_clk
= "dss_dss_clk",
908 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
909 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
912 .opt_clks
= dss_rfbi_opt_clks
,
913 .opt_clks_cnt
= ARRAY_SIZE(dss_rfbi_opt_clks
),
921 static struct omap_hwmod_class omap44xx_venc_hwmod_class
= {
926 static struct omap_hwmod omap44xx_dss_venc_hwmod
= {
928 .class = &omap44xx_venc_hwmod_class
,
929 .clkdm_name
= "l3_dss_clkdm",
930 .main_clk
= "dss_tv_clk",
933 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
934 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
941 * bch error location module
944 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc
= {
948 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
949 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
950 SYSS_HAS_RESET_STATUS
),
951 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
952 .sysc_fields
= &omap_hwmod_sysc_type1
,
955 static struct omap_hwmod_class omap44xx_elm_hwmod_class
= {
957 .sysc
= &omap44xx_elm_sysc
,
961 static struct omap_hwmod_irq_info omap44xx_elm_irqs
[] = {
962 { .irq
= 4 + OMAP44XX_IRQ_GIC_START
},
966 static struct omap_hwmod omap44xx_elm_hwmod
= {
968 .class = &omap44xx_elm_hwmod_class
,
969 .clkdm_name
= "l4_per_clkdm",
970 .mpu_irqs
= omap44xx_elm_irqs
,
973 .clkctrl_offs
= OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET
,
974 .context_offs
= OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET
,
981 * external memory interface no1
984 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc
= {
988 static struct omap_hwmod_class omap44xx_emif_hwmod_class
= {
990 .sysc
= &omap44xx_emif_sysc
,
994 static struct omap_hwmod_irq_info omap44xx_emif1_irqs
[] = {
995 { .irq
= 110 + OMAP44XX_IRQ_GIC_START
},
999 static struct omap_hwmod omap44xx_emif1_hwmod
= {
1001 .class = &omap44xx_emif_hwmod_class
,
1002 .clkdm_name
= "l3_emif_clkdm",
1003 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
1004 .mpu_irqs
= omap44xx_emif1_irqs
,
1005 .main_clk
= "ddrphy_ck",
1008 .clkctrl_offs
= OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET
,
1009 .context_offs
= OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET
,
1010 .modulemode
= MODULEMODE_HWCTRL
,
1016 static struct omap_hwmod_irq_info omap44xx_emif2_irqs
[] = {
1017 { .irq
= 111 + OMAP44XX_IRQ_GIC_START
},
1021 static struct omap_hwmod omap44xx_emif2_hwmod
= {
1023 .class = &omap44xx_emif_hwmod_class
,
1024 .clkdm_name
= "l3_emif_clkdm",
1025 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
1026 .mpu_irqs
= omap44xx_emif2_irqs
,
1027 .main_clk
= "ddrphy_ck",
1030 .clkctrl_offs
= OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET
,
1031 .context_offs
= OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET
,
1032 .modulemode
= MODULEMODE_HWCTRL
,
1039 * face detection hw accelerator module
1042 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc
= {
1044 .sysc_offs
= 0x0010,
1046 * FDIF needs 100 OCP clk cycles delay after a softreset before
1047 * accessing sysconfig again.
1048 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1049 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1051 * TODO: Indicate errata when available.
1054 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_RESET_STATUS
|
1055 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1056 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1057 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
1058 .sysc_fields
= &omap_hwmod_sysc_type2
,
1061 static struct omap_hwmod_class omap44xx_fdif_hwmod_class
= {
1063 .sysc
= &omap44xx_fdif_sysc
,
1067 static struct omap_hwmod_irq_info omap44xx_fdif_irqs
[] = {
1068 { .irq
= 69 + OMAP44XX_IRQ_GIC_START
},
1072 static struct omap_hwmod omap44xx_fdif_hwmod
= {
1074 .class = &omap44xx_fdif_hwmod_class
,
1075 .clkdm_name
= "iss_clkdm",
1076 .mpu_irqs
= omap44xx_fdif_irqs
,
1077 .main_clk
= "fdif_fck",
1080 .clkctrl_offs
= OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET
,
1081 .context_offs
= OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET
,
1082 .modulemode
= MODULEMODE_SWCTRL
,
1089 * general purpose io module
1092 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc
= {
1094 .sysc_offs
= 0x0010,
1095 .syss_offs
= 0x0114,
1096 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
1097 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
1098 SYSS_HAS_RESET_STATUS
),
1099 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1101 .sysc_fields
= &omap_hwmod_sysc_type1
,
1104 static struct omap_hwmod_class omap44xx_gpio_hwmod_class
= {
1106 .sysc
= &omap44xx_gpio_sysc
,
1111 static struct omap_gpio_dev_attr gpio_dev_attr
= {
1117 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs
[] = {
1118 { .irq
= 29 + OMAP44XX_IRQ_GIC_START
},
1122 static struct omap_hwmod_opt_clk gpio1_opt_clks
[] = {
1123 { .role
= "dbclk", .clk
= "gpio1_dbclk" },
1126 static struct omap_hwmod omap44xx_gpio1_hwmod
= {
1128 .class = &omap44xx_gpio_hwmod_class
,
1129 .clkdm_name
= "l4_wkup_clkdm",
1130 .mpu_irqs
= omap44xx_gpio1_irqs
,
1131 .main_clk
= "gpio1_ick",
1134 .clkctrl_offs
= OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET
,
1135 .context_offs
= OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET
,
1136 .modulemode
= MODULEMODE_HWCTRL
,
1139 .opt_clks
= gpio1_opt_clks
,
1140 .opt_clks_cnt
= ARRAY_SIZE(gpio1_opt_clks
),
1141 .dev_attr
= &gpio_dev_attr
,
1145 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs
[] = {
1146 { .irq
= 30 + OMAP44XX_IRQ_GIC_START
},
1150 static struct omap_hwmod_opt_clk gpio2_opt_clks
[] = {
1151 { .role
= "dbclk", .clk
= "gpio2_dbclk" },
1154 static struct omap_hwmod omap44xx_gpio2_hwmod
= {
1156 .class = &omap44xx_gpio_hwmod_class
,
1157 .clkdm_name
= "l4_per_clkdm",
1158 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1159 .mpu_irqs
= omap44xx_gpio2_irqs
,
1160 .main_clk
= "gpio2_ick",
1163 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET
,
1164 .context_offs
= OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET
,
1165 .modulemode
= MODULEMODE_HWCTRL
,
1168 .opt_clks
= gpio2_opt_clks
,
1169 .opt_clks_cnt
= ARRAY_SIZE(gpio2_opt_clks
),
1170 .dev_attr
= &gpio_dev_attr
,
1174 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs
[] = {
1175 { .irq
= 31 + OMAP44XX_IRQ_GIC_START
},
1179 static struct omap_hwmod_opt_clk gpio3_opt_clks
[] = {
1180 { .role
= "dbclk", .clk
= "gpio3_dbclk" },
1183 static struct omap_hwmod omap44xx_gpio3_hwmod
= {
1185 .class = &omap44xx_gpio_hwmod_class
,
1186 .clkdm_name
= "l4_per_clkdm",
1187 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1188 .mpu_irqs
= omap44xx_gpio3_irqs
,
1189 .main_clk
= "gpio3_ick",
1192 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET
,
1193 .context_offs
= OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET
,
1194 .modulemode
= MODULEMODE_HWCTRL
,
1197 .opt_clks
= gpio3_opt_clks
,
1198 .opt_clks_cnt
= ARRAY_SIZE(gpio3_opt_clks
),
1199 .dev_attr
= &gpio_dev_attr
,
1203 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs
[] = {
1204 { .irq
= 32 + OMAP44XX_IRQ_GIC_START
},
1208 static struct omap_hwmod_opt_clk gpio4_opt_clks
[] = {
1209 { .role
= "dbclk", .clk
= "gpio4_dbclk" },
1212 static struct omap_hwmod omap44xx_gpio4_hwmod
= {
1214 .class = &omap44xx_gpio_hwmod_class
,
1215 .clkdm_name
= "l4_per_clkdm",
1216 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1217 .mpu_irqs
= omap44xx_gpio4_irqs
,
1218 .main_clk
= "gpio4_ick",
1221 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET
,
1222 .context_offs
= OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET
,
1223 .modulemode
= MODULEMODE_HWCTRL
,
1226 .opt_clks
= gpio4_opt_clks
,
1227 .opt_clks_cnt
= ARRAY_SIZE(gpio4_opt_clks
),
1228 .dev_attr
= &gpio_dev_attr
,
1232 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs
[] = {
1233 { .irq
= 33 + OMAP44XX_IRQ_GIC_START
},
1237 static struct omap_hwmod_opt_clk gpio5_opt_clks
[] = {
1238 { .role
= "dbclk", .clk
= "gpio5_dbclk" },
1241 static struct omap_hwmod omap44xx_gpio5_hwmod
= {
1243 .class = &omap44xx_gpio_hwmod_class
,
1244 .clkdm_name
= "l4_per_clkdm",
1245 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1246 .mpu_irqs
= omap44xx_gpio5_irqs
,
1247 .main_clk
= "gpio5_ick",
1250 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET
,
1251 .context_offs
= OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET
,
1252 .modulemode
= MODULEMODE_HWCTRL
,
1255 .opt_clks
= gpio5_opt_clks
,
1256 .opt_clks_cnt
= ARRAY_SIZE(gpio5_opt_clks
),
1257 .dev_attr
= &gpio_dev_attr
,
1261 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs
[] = {
1262 { .irq
= 34 + OMAP44XX_IRQ_GIC_START
},
1266 static struct omap_hwmod_opt_clk gpio6_opt_clks
[] = {
1267 { .role
= "dbclk", .clk
= "gpio6_dbclk" },
1270 static struct omap_hwmod omap44xx_gpio6_hwmod
= {
1272 .class = &omap44xx_gpio_hwmod_class
,
1273 .clkdm_name
= "l4_per_clkdm",
1274 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1275 .mpu_irqs
= omap44xx_gpio6_irqs
,
1276 .main_clk
= "gpio6_ick",
1279 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET
,
1280 .context_offs
= OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET
,
1281 .modulemode
= MODULEMODE_HWCTRL
,
1284 .opt_clks
= gpio6_opt_clks
,
1285 .opt_clks_cnt
= ARRAY_SIZE(gpio6_opt_clks
),
1286 .dev_attr
= &gpio_dev_attr
,
1291 * general purpose memory controller
1294 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc
= {
1296 .sysc_offs
= 0x0010,
1297 .syss_offs
= 0x0014,
1298 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SIDLEMODE
|
1299 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1300 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1301 .sysc_fields
= &omap_hwmod_sysc_type1
,
1304 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class
= {
1306 .sysc
= &omap44xx_gpmc_sysc
,
1310 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs
[] = {
1311 { .irq
= 20 + OMAP44XX_IRQ_GIC_START
},
1315 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs
[] = {
1316 { .dma_req
= 3 + OMAP44XX_DMA_REQ_START
},
1320 static struct omap_hwmod omap44xx_gpmc_hwmod
= {
1322 .class = &omap44xx_gpmc_hwmod_class
,
1323 .clkdm_name
= "l3_2_clkdm",
1324 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
1325 .mpu_irqs
= omap44xx_gpmc_irqs
,
1326 .sdma_reqs
= omap44xx_gpmc_sdma_reqs
,
1329 .clkctrl_offs
= OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET
,
1330 .context_offs
= OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET
,
1331 .modulemode
= MODULEMODE_HWCTRL
,
1338 * 2d/3d graphics accelerator
1341 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc
= {
1342 .rev_offs
= 0x1fc00,
1343 .sysc_offs
= 0x1fc10,
1344 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
),
1345 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1346 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1347 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1348 .sysc_fields
= &omap_hwmod_sysc_type2
,
1351 static struct omap_hwmod_class omap44xx_gpu_hwmod_class
= {
1353 .sysc
= &omap44xx_gpu_sysc
,
1357 static struct omap_hwmod_irq_info omap44xx_gpu_irqs
[] = {
1358 { .irq
= 21 + OMAP44XX_IRQ_GIC_START
},
1362 static struct omap_hwmod omap44xx_gpu_hwmod
= {
1364 .class = &omap44xx_gpu_hwmod_class
,
1365 .clkdm_name
= "l3_gfx_clkdm",
1366 .mpu_irqs
= omap44xx_gpu_irqs
,
1367 .main_clk
= "gpu_fck",
1370 .clkctrl_offs
= OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET
,
1371 .context_offs
= OMAP4_RM_GFX_GFX_CONTEXT_OFFSET
,
1372 .modulemode
= MODULEMODE_SWCTRL
,
1379 * hdq / 1-wire serial interface controller
1382 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc
= {
1384 .sysc_offs
= 0x0014,
1385 .syss_offs
= 0x0018,
1386 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SOFTRESET
|
1387 SYSS_HAS_RESET_STATUS
),
1388 .sysc_fields
= &omap_hwmod_sysc_type1
,
1391 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class
= {
1393 .sysc
= &omap44xx_hdq1w_sysc
,
1397 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs
[] = {
1398 { .irq
= 58 + OMAP44XX_IRQ_GIC_START
},
1402 static struct omap_hwmod omap44xx_hdq1w_hwmod
= {
1404 .class = &omap44xx_hdq1w_hwmod_class
,
1405 .clkdm_name
= "l4_per_clkdm",
1406 .flags
= HWMOD_INIT_NO_RESET
, /* XXX temporary */
1407 .mpu_irqs
= omap44xx_hdq1w_irqs
,
1408 .main_clk
= "hdq1w_fck",
1411 .clkctrl_offs
= OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET
,
1412 .context_offs
= OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET
,
1413 .modulemode
= MODULEMODE_SWCTRL
,
1420 * mipi high-speed synchronous serial interface (multichannel and full-duplex
1424 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc
= {
1426 .sysc_offs
= 0x0010,
1427 .syss_offs
= 0x0014,
1428 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_EMUFREE
|
1429 SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
|
1430 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1431 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1432 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1433 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1434 .sysc_fields
= &omap_hwmod_sysc_type1
,
1437 static struct omap_hwmod_class omap44xx_hsi_hwmod_class
= {
1439 .sysc
= &omap44xx_hsi_sysc
,
1443 static struct omap_hwmod_irq_info omap44xx_hsi_irqs
[] = {
1444 { .name
= "mpu_p1", .irq
= 67 + OMAP44XX_IRQ_GIC_START
},
1445 { .name
= "mpu_p2", .irq
= 68 + OMAP44XX_IRQ_GIC_START
},
1446 { .name
= "mpu_dma", .irq
= 71 + OMAP44XX_IRQ_GIC_START
},
1450 static struct omap_hwmod omap44xx_hsi_hwmod
= {
1452 .class = &omap44xx_hsi_hwmod_class
,
1453 .clkdm_name
= "l3_init_clkdm",
1454 .mpu_irqs
= omap44xx_hsi_irqs
,
1455 .main_clk
= "hsi_fck",
1458 .clkctrl_offs
= OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET
,
1459 .context_offs
= OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET
,
1460 .modulemode
= MODULEMODE_HWCTRL
,
1467 * multimaster high-speed i2c controller
1470 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc
= {
1471 .sysc_offs
= 0x0010,
1472 .syss_offs
= 0x0090,
1473 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
1474 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
1475 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1476 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1478 .clockact
= CLOCKACT_TEST_ICLK
,
1479 .sysc_fields
= &omap_hwmod_sysc_type1
,
1482 static struct omap_hwmod_class omap44xx_i2c_hwmod_class
= {
1484 .sysc
= &omap44xx_i2c_sysc
,
1485 .rev
= OMAP_I2C_IP_VERSION_2
,
1486 .reset
= &omap_i2c_reset
,
1489 static struct omap_i2c_dev_attr i2c_dev_attr
= {
1490 .flags
= OMAP_I2C_FLAG_BUS_SHIFT_NONE
|
1491 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE
,
1495 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs
[] = {
1496 { .irq
= 56 + OMAP44XX_IRQ_GIC_START
},
1500 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs
[] = {
1501 { .name
= "tx", .dma_req
= 26 + OMAP44XX_DMA_REQ_START
},
1502 { .name
= "rx", .dma_req
= 27 + OMAP44XX_DMA_REQ_START
},
1506 static struct omap_hwmod omap44xx_i2c1_hwmod
= {
1508 .class = &omap44xx_i2c_hwmod_class
,
1509 .clkdm_name
= "l4_per_clkdm",
1510 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1511 .mpu_irqs
= omap44xx_i2c1_irqs
,
1512 .sdma_reqs
= omap44xx_i2c1_sdma_reqs
,
1513 .main_clk
= "i2c1_fck",
1516 .clkctrl_offs
= OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET
,
1517 .context_offs
= OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET
,
1518 .modulemode
= MODULEMODE_SWCTRL
,
1521 .dev_attr
= &i2c_dev_attr
,
1525 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs
[] = {
1526 { .irq
= 57 + OMAP44XX_IRQ_GIC_START
},
1530 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs
[] = {
1531 { .name
= "tx", .dma_req
= 28 + OMAP44XX_DMA_REQ_START
},
1532 { .name
= "rx", .dma_req
= 29 + OMAP44XX_DMA_REQ_START
},
1536 static struct omap_hwmod omap44xx_i2c2_hwmod
= {
1538 .class = &omap44xx_i2c_hwmod_class
,
1539 .clkdm_name
= "l4_per_clkdm",
1540 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1541 .mpu_irqs
= omap44xx_i2c2_irqs
,
1542 .sdma_reqs
= omap44xx_i2c2_sdma_reqs
,
1543 .main_clk
= "i2c2_fck",
1546 .clkctrl_offs
= OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET
,
1547 .context_offs
= OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET
,
1548 .modulemode
= MODULEMODE_SWCTRL
,
1551 .dev_attr
= &i2c_dev_attr
,
1555 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs
[] = {
1556 { .irq
= 61 + OMAP44XX_IRQ_GIC_START
},
1560 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs
[] = {
1561 { .name
= "tx", .dma_req
= 24 + OMAP44XX_DMA_REQ_START
},
1562 { .name
= "rx", .dma_req
= 25 + OMAP44XX_DMA_REQ_START
},
1566 static struct omap_hwmod omap44xx_i2c3_hwmod
= {
1568 .class = &omap44xx_i2c_hwmod_class
,
1569 .clkdm_name
= "l4_per_clkdm",
1570 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1571 .mpu_irqs
= omap44xx_i2c3_irqs
,
1572 .sdma_reqs
= omap44xx_i2c3_sdma_reqs
,
1573 .main_clk
= "i2c3_fck",
1576 .clkctrl_offs
= OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET
,
1577 .context_offs
= OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET
,
1578 .modulemode
= MODULEMODE_SWCTRL
,
1581 .dev_attr
= &i2c_dev_attr
,
1585 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs
[] = {
1586 { .irq
= 62 + OMAP44XX_IRQ_GIC_START
},
1590 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs
[] = {
1591 { .name
= "tx", .dma_req
= 123 + OMAP44XX_DMA_REQ_START
},
1592 { .name
= "rx", .dma_req
= 124 + OMAP44XX_DMA_REQ_START
},
1596 static struct omap_hwmod omap44xx_i2c4_hwmod
= {
1598 .class = &omap44xx_i2c_hwmod_class
,
1599 .clkdm_name
= "l4_per_clkdm",
1600 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1601 .mpu_irqs
= omap44xx_i2c4_irqs
,
1602 .sdma_reqs
= omap44xx_i2c4_sdma_reqs
,
1603 .main_clk
= "i2c4_fck",
1606 .clkctrl_offs
= OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET
,
1607 .context_offs
= OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET
,
1608 .modulemode
= MODULEMODE_SWCTRL
,
1611 .dev_attr
= &i2c_dev_attr
,
1616 * imaging processor unit
1619 static struct omap_hwmod_class omap44xx_ipu_hwmod_class
= {
1624 static struct omap_hwmod_irq_info omap44xx_ipu_irqs
[] = {
1625 { .irq
= 100 + OMAP44XX_IRQ_GIC_START
},
1629 static struct omap_hwmod_rst_info omap44xx_ipu_resets
[] = {
1630 { .name
= "cpu0", .rst_shift
= 0 },
1631 { .name
= "cpu1", .rst_shift
= 1 },
1632 { .name
= "mmu_cache", .rst_shift
= 2 },
1635 static struct omap_hwmod omap44xx_ipu_hwmod
= {
1637 .class = &omap44xx_ipu_hwmod_class
,
1638 .clkdm_name
= "ducati_clkdm",
1639 .mpu_irqs
= omap44xx_ipu_irqs
,
1640 .rst_lines
= omap44xx_ipu_resets
,
1641 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_ipu_resets
),
1642 .main_clk
= "ipu_fck",
1645 .clkctrl_offs
= OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET
,
1646 .rstctrl_offs
= OMAP4_RM_DUCATI_RSTCTRL_OFFSET
,
1647 .context_offs
= OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET
,
1648 .modulemode
= MODULEMODE_HWCTRL
,
1655 * external images sensor pixel data processor
1658 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc
= {
1660 .sysc_offs
= 0x0010,
1662 * ISS needs 100 OCP clk cycles delay after a softreset before
1663 * accessing sysconfig again.
1664 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1665 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1667 * TODO: Indicate errata when available.
1670 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_RESET_STATUS
|
1671 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1672 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1673 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1674 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1675 .sysc_fields
= &omap_hwmod_sysc_type2
,
1678 static struct omap_hwmod_class omap44xx_iss_hwmod_class
= {
1680 .sysc
= &omap44xx_iss_sysc
,
1684 static struct omap_hwmod_irq_info omap44xx_iss_irqs
[] = {
1685 { .irq
= 24 + OMAP44XX_IRQ_GIC_START
},
1689 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs
[] = {
1690 { .name
= "1", .dma_req
= 8 + OMAP44XX_DMA_REQ_START
},
1691 { .name
= "2", .dma_req
= 9 + OMAP44XX_DMA_REQ_START
},
1692 { .name
= "3", .dma_req
= 11 + OMAP44XX_DMA_REQ_START
},
1693 { .name
= "4", .dma_req
= 12 + OMAP44XX_DMA_REQ_START
},
1697 static struct omap_hwmod_opt_clk iss_opt_clks
[] = {
1698 { .role
= "ctrlclk", .clk
= "iss_ctrlclk" },
1701 static struct omap_hwmod omap44xx_iss_hwmod
= {
1703 .class = &omap44xx_iss_hwmod_class
,
1704 .clkdm_name
= "iss_clkdm",
1705 .mpu_irqs
= omap44xx_iss_irqs
,
1706 .sdma_reqs
= omap44xx_iss_sdma_reqs
,
1707 .main_clk
= "iss_fck",
1710 .clkctrl_offs
= OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET
,
1711 .context_offs
= OMAP4_RM_CAM_ISS_CONTEXT_OFFSET
,
1712 .modulemode
= MODULEMODE_SWCTRL
,
1715 .opt_clks
= iss_opt_clks
,
1716 .opt_clks_cnt
= ARRAY_SIZE(iss_opt_clks
),
1721 * multi-standard video encoder/decoder hardware accelerator
1724 static struct omap_hwmod_class omap44xx_iva_hwmod_class
= {
1729 static struct omap_hwmod_irq_info omap44xx_iva_irqs
[] = {
1730 { .name
= "sync_1", .irq
= 103 + OMAP44XX_IRQ_GIC_START
},
1731 { .name
= "sync_0", .irq
= 104 + OMAP44XX_IRQ_GIC_START
},
1732 { .name
= "mailbox_0", .irq
= 107 + OMAP44XX_IRQ_GIC_START
},
1736 static struct omap_hwmod_rst_info omap44xx_iva_resets
[] = {
1737 { .name
= "seq0", .rst_shift
= 0 },
1738 { .name
= "seq1", .rst_shift
= 1 },
1739 { .name
= "logic", .rst_shift
= 2 },
1742 static struct omap_hwmod omap44xx_iva_hwmod
= {
1744 .class = &omap44xx_iva_hwmod_class
,
1745 .clkdm_name
= "ivahd_clkdm",
1746 .mpu_irqs
= omap44xx_iva_irqs
,
1747 .rst_lines
= omap44xx_iva_resets
,
1748 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_iva_resets
),
1749 .main_clk
= "iva_fck",
1752 .clkctrl_offs
= OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET
,
1753 .rstctrl_offs
= OMAP4_RM_IVAHD_RSTCTRL_OFFSET
,
1754 .context_offs
= OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET
,
1755 .modulemode
= MODULEMODE_HWCTRL
,
1762 * keyboard controller
1765 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc
= {
1767 .sysc_offs
= 0x0010,
1768 .syss_offs
= 0x0014,
1769 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
1770 SYSC_HAS_EMUFREE
| SYSC_HAS_ENAWAKEUP
|
1771 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
1772 SYSS_HAS_RESET_STATUS
),
1773 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1774 .sysc_fields
= &omap_hwmod_sysc_type1
,
1777 static struct omap_hwmod_class omap44xx_kbd_hwmod_class
= {
1779 .sysc
= &omap44xx_kbd_sysc
,
1783 static struct omap_hwmod_irq_info omap44xx_kbd_irqs
[] = {
1784 { .irq
= 120 + OMAP44XX_IRQ_GIC_START
},
1788 static struct omap_hwmod omap44xx_kbd_hwmod
= {
1790 .class = &omap44xx_kbd_hwmod_class
,
1791 .clkdm_name
= "l4_wkup_clkdm",
1792 .mpu_irqs
= omap44xx_kbd_irqs
,
1793 .main_clk
= "kbd_fck",
1796 .clkctrl_offs
= OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET
,
1797 .context_offs
= OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET
,
1798 .modulemode
= MODULEMODE_SWCTRL
,
1805 * mailbox module allowing communication between the on-chip processors using a
1806 * queued mailbox-interrupt mechanism.
1809 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc
= {
1811 .sysc_offs
= 0x0010,
1812 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
1813 SYSC_HAS_SOFTRESET
),
1814 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1815 .sysc_fields
= &omap_hwmod_sysc_type2
,
1818 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class
= {
1820 .sysc
= &omap44xx_mailbox_sysc
,
1824 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs
[] = {
1825 { .irq
= 26 + OMAP44XX_IRQ_GIC_START
},
1829 static struct omap_hwmod omap44xx_mailbox_hwmod
= {
1831 .class = &omap44xx_mailbox_hwmod_class
,
1832 .clkdm_name
= "l4_cfg_clkdm",
1833 .mpu_irqs
= omap44xx_mailbox_irqs
,
1836 .clkctrl_offs
= OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET
,
1837 .context_offs
= OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET
,
1844 * multi-channel audio serial port controller
1847 /* The IP is not compliant to type1 / type2 scheme */
1848 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp
= {
1852 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc
= {
1853 .sysc_offs
= 0x0004,
1854 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
1855 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1857 .sysc_fields
= &omap_hwmod_sysc_type_mcasp
,
1860 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class
= {
1862 .sysc
= &omap44xx_mcasp_sysc
,
1866 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs
[] = {
1867 { .name
= "arevt", .irq
= 108 + OMAP44XX_IRQ_GIC_START
},
1868 { .name
= "axevt", .irq
= 109 + OMAP44XX_IRQ_GIC_START
},
1872 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs
[] = {
1873 { .name
= "axevt", .dma_req
= 7 + OMAP44XX_DMA_REQ_START
},
1874 { .name
= "arevt", .dma_req
= 10 + OMAP44XX_DMA_REQ_START
},
1878 static struct omap_hwmod omap44xx_mcasp_hwmod
= {
1880 .class = &omap44xx_mcasp_hwmod_class
,
1881 .clkdm_name
= "abe_clkdm",
1882 .mpu_irqs
= omap44xx_mcasp_irqs
,
1883 .sdma_reqs
= omap44xx_mcasp_sdma_reqs
,
1884 .main_clk
= "mcasp_fck",
1887 .clkctrl_offs
= OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET
,
1888 .context_offs
= OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET
,
1889 .modulemode
= MODULEMODE_SWCTRL
,
1896 * multi channel buffered serial port controller
1899 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc
= {
1900 .sysc_offs
= 0x008c,
1901 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_ENAWAKEUP
|
1902 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1903 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1904 .sysc_fields
= &omap_hwmod_sysc_type1
,
1907 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class
= {
1909 .sysc
= &omap44xx_mcbsp_sysc
,
1910 .rev
= MCBSP_CONFIG_TYPE4
,
1914 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs
[] = {
1915 { .name
= "common", .irq
= 17 + OMAP44XX_IRQ_GIC_START
},
1919 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs
[] = {
1920 { .name
= "tx", .dma_req
= 32 + OMAP44XX_DMA_REQ_START
},
1921 { .name
= "rx", .dma_req
= 33 + OMAP44XX_DMA_REQ_START
},
1925 static struct omap_hwmod_opt_clk mcbsp1_opt_clks
[] = {
1926 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
1927 { .role
= "prcm_clk", .clk
= "mcbsp1_sync_mux_ck" },
1930 static struct omap_hwmod omap44xx_mcbsp1_hwmod
= {
1932 .class = &omap44xx_mcbsp_hwmod_class
,
1933 .clkdm_name
= "abe_clkdm",
1934 .mpu_irqs
= omap44xx_mcbsp1_irqs
,
1935 .sdma_reqs
= omap44xx_mcbsp1_sdma_reqs
,
1936 .main_clk
= "mcbsp1_fck",
1939 .clkctrl_offs
= OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET
,
1940 .context_offs
= OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET
,
1941 .modulemode
= MODULEMODE_SWCTRL
,
1944 .opt_clks
= mcbsp1_opt_clks
,
1945 .opt_clks_cnt
= ARRAY_SIZE(mcbsp1_opt_clks
),
1949 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs
[] = {
1950 { .name
= "common", .irq
= 22 + OMAP44XX_IRQ_GIC_START
},
1954 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs
[] = {
1955 { .name
= "tx", .dma_req
= 16 + OMAP44XX_DMA_REQ_START
},
1956 { .name
= "rx", .dma_req
= 17 + OMAP44XX_DMA_REQ_START
},
1960 static struct omap_hwmod_opt_clk mcbsp2_opt_clks
[] = {
1961 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
1962 { .role
= "prcm_clk", .clk
= "mcbsp2_sync_mux_ck" },
1965 static struct omap_hwmod omap44xx_mcbsp2_hwmod
= {
1967 .class = &omap44xx_mcbsp_hwmod_class
,
1968 .clkdm_name
= "abe_clkdm",
1969 .mpu_irqs
= omap44xx_mcbsp2_irqs
,
1970 .sdma_reqs
= omap44xx_mcbsp2_sdma_reqs
,
1971 .main_clk
= "mcbsp2_fck",
1974 .clkctrl_offs
= OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET
,
1975 .context_offs
= OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET
,
1976 .modulemode
= MODULEMODE_SWCTRL
,
1979 .opt_clks
= mcbsp2_opt_clks
,
1980 .opt_clks_cnt
= ARRAY_SIZE(mcbsp2_opt_clks
),
1984 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs
[] = {
1985 { .name
= "common", .irq
= 23 + OMAP44XX_IRQ_GIC_START
},
1989 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs
[] = {
1990 { .name
= "tx", .dma_req
= 18 + OMAP44XX_DMA_REQ_START
},
1991 { .name
= "rx", .dma_req
= 19 + OMAP44XX_DMA_REQ_START
},
1995 static struct omap_hwmod_opt_clk mcbsp3_opt_clks
[] = {
1996 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
1997 { .role
= "prcm_clk", .clk
= "mcbsp3_sync_mux_ck" },
2000 static struct omap_hwmod omap44xx_mcbsp3_hwmod
= {
2002 .class = &omap44xx_mcbsp_hwmod_class
,
2003 .clkdm_name
= "abe_clkdm",
2004 .mpu_irqs
= omap44xx_mcbsp3_irqs
,
2005 .sdma_reqs
= omap44xx_mcbsp3_sdma_reqs
,
2006 .main_clk
= "mcbsp3_fck",
2009 .clkctrl_offs
= OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET
,
2010 .context_offs
= OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET
,
2011 .modulemode
= MODULEMODE_SWCTRL
,
2014 .opt_clks
= mcbsp3_opt_clks
,
2015 .opt_clks_cnt
= ARRAY_SIZE(mcbsp3_opt_clks
),
2019 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs
[] = {
2020 { .name
= "common", .irq
= 16 + OMAP44XX_IRQ_GIC_START
},
2024 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs
[] = {
2025 { .name
= "tx", .dma_req
= 30 + OMAP44XX_DMA_REQ_START
},
2026 { .name
= "rx", .dma_req
= 31 + OMAP44XX_DMA_REQ_START
},
2030 static struct omap_hwmod_opt_clk mcbsp4_opt_clks
[] = {
2031 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
2032 { .role
= "prcm_clk", .clk
= "mcbsp4_sync_mux_ck" },
2035 static struct omap_hwmod omap44xx_mcbsp4_hwmod
= {
2037 .class = &omap44xx_mcbsp_hwmod_class
,
2038 .clkdm_name
= "l4_per_clkdm",
2039 .mpu_irqs
= omap44xx_mcbsp4_irqs
,
2040 .sdma_reqs
= omap44xx_mcbsp4_sdma_reqs
,
2041 .main_clk
= "mcbsp4_fck",
2044 .clkctrl_offs
= OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET
,
2045 .context_offs
= OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET
,
2046 .modulemode
= MODULEMODE_SWCTRL
,
2049 .opt_clks
= mcbsp4_opt_clks
,
2050 .opt_clks_cnt
= ARRAY_SIZE(mcbsp4_opt_clks
),
2055 * multi channel pdm controller (proprietary interface with phoenix power
2059 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc
= {
2061 .sysc_offs
= 0x0010,
2062 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
2063 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
2064 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2066 .sysc_fields
= &omap_hwmod_sysc_type2
,
2069 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class
= {
2071 .sysc
= &omap44xx_mcpdm_sysc
,
2075 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs
[] = {
2076 { .irq
= 112 + OMAP44XX_IRQ_GIC_START
},
2080 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs
[] = {
2081 { .name
= "up_link", .dma_req
= 64 + OMAP44XX_DMA_REQ_START
},
2082 { .name
= "dn_link", .dma_req
= 65 + OMAP44XX_DMA_REQ_START
},
2086 static struct omap_hwmod omap44xx_mcpdm_hwmod
= {
2088 .class = &omap44xx_mcpdm_hwmod_class
,
2089 .clkdm_name
= "abe_clkdm",
2090 .mpu_irqs
= omap44xx_mcpdm_irqs
,
2091 .sdma_reqs
= omap44xx_mcpdm_sdma_reqs
,
2092 .main_clk
= "mcpdm_fck",
2095 .clkctrl_offs
= OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET
,
2096 .context_offs
= OMAP4_RM_ABE_PDM_CONTEXT_OFFSET
,
2097 .modulemode
= MODULEMODE_SWCTRL
,
2104 * multichannel serial port interface (mcspi) / master/slave synchronous serial
2108 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc
= {
2110 .sysc_offs
= 0x0010,
2111 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
2112 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
2113 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2115 .sysc_fields
= &omap_hwmod_sysc_type2
,
2118 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class
= {
2120 .sysc
= &omap44xx_mcspi_sysc
,
2121 .rev
= OMAP4_MCSPI_REV
,
2125 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs
[] = {
2126 { .irq
= 65 + OMAP44XX_IRQ_GIC_START
},
2130 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs
[] = {
2131 { .name
= "tx0", .dma_req
= 34 + OMAP44XX_DMA_REQ_START
},
2132 { .name
= "rx0", .dma_req
= 35 + OMAP44XX_DMA_REQ_START
},
2133 { .name
= "tx1", .dma_req
= 36 + OMAP44XX_DMA_REQ_START
},
2134 { .name
= "rx1", .dma_req
= 37 + OMAP44XX_DMA_REQ_START
},
2135 { .name
= "tx2", .dma_req
= 38 + OMAP44XX_DMA_REQ_START
},
2136 { .name
= "rx2", .dma_req
= 39 + OMAP44XX_DMA_REQ_START
},
2137 { .name
= "tx3", .dma_req
= 40 + OMAP44XX_DMA_REQ_START
},
2138 { .name
= "rx3", .dma_req
= 41 + OMAP44XX_DMA_REQ_START
},
2142 /* mcspi1 dev_attr */
2143 static struct omap2_mcspi_dev_attr mcspi1_dev_attr
= {
2144 .num_chipselect
= 4,
2147 static struct omap_hwmod omap44xx_mcspi1_hwmod
= {
2149 .class = &omap44xx_mcspi_hwmod_class
,
2150 .clkdm_name
= "l4_per_clkdm",
2151 .mpu_irqs
= omap44xx_mcspi1_irqs
,
2152 .sdma_reqs
= omap44xx_mcspi1_sdma_reqs
,
2153 .main_clk
= "mcspi1_fck",
2156 .clkctrl_offs
= OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET
,
2157 .context_offs
= OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET
,
2158 .modulemode
= MODULEMODE_SWCTRL
,
2161 .dev_attr
= &mcspi1_dev_attr
,
2165 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs
[] = {
2166 { .irq
= 66 + OMAP44XX_IRQ_GIC_START
},
2170 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs
[] = {
2171 { .name
= "tx0", .dma_req
= 42 + OMAP44XX_DMA_REQ_START
},
2172 { .name
= "rx0", .dma_req
= 43 + OMAP44XX_DMA_REQ_START
},
2173 { .name
= "tx1", .dma_req
= 44 + OMAP44XX_DMA_REQ_START
},
2174 { .name
= "rx1", .dma_req
= 45 + OMAP44XX_DMA_REQ_START
},
2178 /* mcspi2 dev_attr */
2179 static struct omap2_mcspi_dev_attr mcspi2_dev_attr
= {
2180 .num_chipselect
= 2,
2183 static struct omap_hwmod omap44xx_mcspi2_hwmod
= {
2185 .class = &omap44xx_mcspi_hwmod_class
,
2186 .clkdm_name
= "l4_per_clkdm",
2187 .mpu_irqs
= omap44xx_mcspi2_irqs
,
2188 .sdma_reqs
= omap44xx_mcspi2_sdma_reqs
,
2189 .main_clk
= "mcspi2_fck",
2192 .clkctrl_offs
= OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET
,
2193 .context_offs
= OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET
,
2194 .modulemode
= MODULEMODE_SWCTRL
,
2197 .dev_attr
= &mcspi2_dev_attr
,
2201 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs
[] = {
2202 { .irq
= 91 + OMAP44XX_IRQ_GIC_START
},
2206 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs
[] = {
2207 { .name
= "tx0", .dma_req
= 14 + OMAP44XX_DMA_REQ_START
},
2208 { .name
= "rx0", .dma_req
= 15 + OMAP44XX_DMA_REQ_START
},
2209 { .name
= "tx1", .dma_req
= 22 + OMAP44XX_DMA_REQ_START
},
2210 { .name
= "rx1", .dma_req
= 23 + OMAP44XX_DMA_REQ_START
},
2214 /* mcspi3 dev_attr */
2215 static struct omap2_mcspi_dev_attr mcspi3_dev_attr
= {
2216 .num_chipselect
= 2,
2219 static struct omap_hwmod omap44xx_mcspi3_hwmod
= {
2221 .class = &omap44xx_mcspi_hwmod_class
,
2222 .clkdm_name
= "l4_per_clkdm",
2223 .mpu_irqs
= omap44xx_mcspi3_irqs
,
2224 .sdma_reqs
= omap44xx_mcspi3_sdma_reqs
,
2225 .main_clk
= "mcspi3_fck",
2228 .clkctrl_offs
= OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET
,
2229 .context_offs
= OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET
,
2230 .modulemode
= MODULEMODE_SWCTRL
,
2233 .dev_attr
= &mcspi3_dev_attr
,
2237 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs
[] = {
2238 { .irq
= 48 + OMAP44XX_IRQ_GIC_START
},
2242 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs
[] = {
2243 { .name
= "tx0", .dma_req
= 69 + OMAP44XX_DMA_REQ_START
},
2244 { .name
= "rx0", .dma_req
= 70 + OMAP44XX_DMA_REQ_START
},
2248 /* mcspi4 dev_attr */
2249 static struct omap2_mcspi_dev_attr mcspi4_dev_attr
= {
2250 .num_chipselect
= 1,
2253 static struct omap_hwmod omap44xx_mcspi4_hwmod
= {
2255 .class = &omap44xx_mcspi_hwmod_class
,
2256 .clkdm_name
= "l4_per_clkdm",
2257 .mpu_irqs
= omap44xx_mcspi4_irqs
,
2258 .sdma_reqs
= omap44xx_mcspi4_sdma_reqs
,
2259 .main_clk
= "mcspi4_fck",
2262 .clkctrl_offs
= OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET
,
2263 .context_offs
= OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET
,
2264 .modulemode
= MODULEMODE_SWCTRL
,
2267 .dev_attr
= &mcspi4_dev_attr
,
2272 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2275 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc
= {
2277 .sysc_offs
= 0x0010,
2278 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_MIDLEMODE
|
2279 SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
2280 SYSC_HAS_SOFTRESET
),
2281 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2282 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
2283 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
2284 .sysc_fields
= &omap_hwmod_sysc_type2
,
2287 static struct omap_hwmod_class omap44xx_mmc_hwmod_class
= {
2289 .sysc
= &omap44xx_mmc_sysc
,
2293 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs
[] = {
2294 { .irq
= 83 + OMAP44XX_IRQ_GIC_START
},
2298 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs
[] = {
2299 { .name
= "tx", .dma_req
= 60 + OMAP44XX_DMA_REQ_START
},
2300 { .name
= "rx", .dma_req
= 61 + OMAP44XX_DMA_REQ_START
},
2305 static struct omap_mmc_dev_attr mmc1_dev_attr
= {
2306 .flags
= OMAP_HSMMC_SUPPORTS_DUAL_VOLT
,
2309 static struct omap_hwmod omap44xx_mmc1_hwmod
= {
2311 .class = &omap44xx_mmc_hwmod_class
,
2312 .clkdm_name
= "l3_init_clkdm",
2313 .mpu_irqs
= omap44xx_mmc1_irqs
,
2314 .sdma_reqs
= omap44xx_mmc1_sdma_reqs
,
2315 .main_clk
= "mmc1_fck",
2318 .clkctrl_offs
= OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET
,
2319 .context_offs
= OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET
,
2320 .modulemode
= MODULEMODE_SWCTRL
,
2323 .dev_attr
= &mmc1_dev_attr
,
2327 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs
[] = {
2328 { .irq
= 86 + OMAP44XX_IRQ_GIC_START
},
2332 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs
[] = {
2333 { .name
= "tx", .dma_req
= 46 + OMAP44XX_DMA_REQ_START
},
2334 { .name
= "rx", .dma_req
= 47 + OMAP44XX_DMA_REQ_START
},
2338 static struct omap_hwmod omap44xx_mmc2_hwmod
= {
2340 .class = &omap44xx_mmc_hwmod_class
,
2341 .clkdm_name
= "l3_init_clkdm",
2342 .mpu_irqs
= omap44xx_mmc2_irqs
,
2343 .sdma_reqs
= omap44xx_mmc2_sdma_reqs
,
2344 .main_clk
= "mmc2_fck",
2347 .clkctrl_offs
= OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET
,
2348 .context_offs
= OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET
,
2349 .modulemode
= MODULEMODE_SWCTRL
,
2355 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs
[] = {
2356 { .irq
= 94 + OMAP44XX_IRQ_GIC_START
},
2360 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs
[] = {
2361 { .name
= "tx", .dma_req
= 76 + OMAP44XX_DMA_REQ_START
},
2362 { .name
= "rx", .dma_req
= 77 + OMAP44XX_DMA_REQ_START
},
2366 static struct omap_hwmod omap44xx_mmc3_hwmod
= {
2368 .class = &omap44xx_mmc_hwmod_class
,
2369 .clkdm_name
= "l4_per_clkdm",
2370 .mpu_irqs
= omap44xx_mmc3_irqs
,
2371 .sdma_reqs
= omap44xx_mmc3_sdma_reqs
,
2372 .main_clk
= "mmc3_fck",
2375 .clkctrl_offs
= OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET
,
2376 .context_offs
= OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET
,
2377 .modulemode
= MODULEMODE_SWCTRL
,
2383 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs
[] = {
2384 { .irq
= 96 + OMAP44XX_IRQ_GIC_START
},
2388 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs
[] = {
2389 { .name
= "tx", .dma_req
= 56 + OMAP44XX_DMA_REQ_START
},
2390 { .name
= "rx", .dma_req
= 57 + OMAP44XX_DMA_REQ_START
},
2394 static struct omap_hwmod omap44xx_mmc4_hwmod
= {
2396 .class = &omap44xx_mmc_hwmod_class
,
2397 .clkdm_name
= "l4_per_clkdm",
2398 .mpu_irqs
= omap44xx_mmc4_irqs
,
2399 .sdma_reqs
= omap44xx_mmc4_sdma_reqs
,
2400 .main_clk
= "mmc4_fck",
2403 .clkctrl_offs
= OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET
,
2404 .context_offs
= OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET
,
2405 .modulemode
= MODULEMODE_SWCTRL
,
2411 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs
[] = {
2412 { .irq
= 59 + OMAP44XX_IRQ_GIC_START
},
2416 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs
[] = {
2417 { .name
= "tx", .dma_req
= 58 + OMAP44XX_DMA_REQ_START
},
2418 { .name
= "rx", .dma_req
= 59 + OMAP44XX_DMA_REQ_START
},
2422 static struct omap_hwmod omap44xx_mmc5_hwmod
= {
2424 .class = &omap44xx_mmc_hwmod_class
,
2425 .clkdm_name
= "l4_per_clkdm",
2426 .mpu_irqs
= omap44xx_mmc5_irqs
,
2427 .sdma_reqs
= omap44xx_mmc5_sdma_reqs
,
2428 .main_clk
= "mmc5_fck",
2431 .clkctrl_offs
= OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET
,
2432 .context_offs
= OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET
,
2433 .modulemode
= MODULEMODE_SWCTRL
,
2443 static struct omap_hwmod_class omap44xx_mpu_hwmod_class
= {
2448 static struct omap_hwmod_irq_info omap44xx_mpu_irqs
[] = {
2449 { .name
= "pl310", .irq
= 0 + OMAP44XX_IRQ_GIC_START
},
2450 { .name
= "cti0", .irq
= 1 + OMAP44XX_IRQ_GIC_START
},
2451 { .name
= "cti1", .irq
= 2 + OMAP44XX_IRQ_GIC_START
},
2455 static struct omap_hwmod omap44xx_mpu_hwmod
= {
2457 .class = &omap44xx_mpu_hwmod_class
,
2458 .clkdm_name
= "mpuss_clkdm",
2459 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
2460 .mpu_irqs
= omap44xx_mpu_irqs
,
2461 .main_clk
= "dpll_mpu_m2_ck",
2464 .clkctrl_offs
= OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET
,
2465 .context_offs
= OMAP4_RM_MPU_MPU_CONTEXT_OFFSET
,
2472 * top-level core on-chip ram
2475 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class
= {
2480 static struct omap_hwmod omap44xx_ocmc_ram_hwmod
= {
2482 .class = &omap44xx_ocmc_ram_hwmod_class
,
2483 .clkdm_name
= "l3_2_clkdm",
2486 .clkctrl_offs
= OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET
,
2487 .context_offs
= OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET
,
2494 * bridge to transform ocp interface protocol to scp (serial control port)
2498 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class
= {
2502 /* ocp2scp_usb_phy */
2503 static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks
[] = {
2504 { .role
= "phy_48m", .clk
= "ocp2scp_usb_phy_phy_48m" },
2507 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod
= {
2508 .name
= "ocp2scp_usb_phy",
2509 .class = &omap44xx_ocp2scp_hwmod_class
,
2510 .clkdm_name
= "l3_init_clkdm",
2513 .clkctrl_offs
= OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET
,
2514 .context_offs
= OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET
,
2515 .modulemode
= MODULEMODE_HWCTRL
,
2518 .opt_clks
= ocp2scp_usb_phy_opt_clks
,
2519 .opt_clks_cnt
= ARRAY_SIZE(ocp2scp_usb_phy_opt_clks
),
2524 * power and reset manager (part of the prcm infrastructure) + clock manager 2
2525 * + clock manager 1 (in always on power domain) + local prm in mpu
2528 static struct omap_hwmod_class omap44xx_prcm_hwmod_class
= {
2533 static struct omap_hwmod omap44xx_prcm_mpu_hwmod
= {
2535 .class = &omap44xx_prcm_hwmod_class
,
2536 .clkdm_name
= "l4_wkup_clkdm",
2540 static struct omap_hwmod omap44xx_cm_core_aon_hwmod
= {
2541 .name
= "cm_core_aon",
2542 .class = &omap44xx_prcm_hwmod_class
,
2543 .clkdm_name
= "cm_clkdm",
2547 static struct omap_hwmod omap44xx_cm_core_hwmod
= {
2549 .class = &omap44xx_prcm_hwmod_class
,
2550 .clkdm_name
= "cm_clkdm",
2554 static struct omap_hwmod_irq_info omap44xx_prm_irqs
[] = {
2555 { .irq
= 11 + OMAP44XX_IRQ_GIC_START
},
2559 static struct omap_hwmod_rst_info omap44xx_prm_resets
[] = {
2560 { .name
= "rst_global_warm_sw", .rst_shift
= 0 },
2561 { .name
= "rst_global_cold_sw", .rst_shift
= 1 },
2564 static struct omap_hwmod omap44xx_prm_hwmod
= {
2566 .class = &omap44xx_prcm_hwmod_class
,
2567 .clkdm_name
= "prm_clkdm",
2568 .mpu_irqs
= omap44xx_prm_irqs
,
2569 .rst_lines
= omap44xx_prm_resets
,
2570 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_prm_resets
),
2575 * system clock and reset manager
2578 static struct omap_hwmod_class omap44xx_scrm_hwmod_class
= {
2583 static struct omap_hwmod omap44xx_scrm_hwmod
= {
2585 .class = &omap44xx_scrm_hwmod_class
,
2586 .clkdm_name
= "l4_wkup_clkdm",
2591 * shared level 2 memory interface
2594 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class
= {
2599 static struct omap_hwmod omap44xx_sl2if_hwmod
= {
2601 .class = &omap44xx_sl2if_hwmod_class
,
2602 .clkdm_name
= "ivahd_clkdm",
2605 .clkctrl_offs
= OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET
,
2606 .context_offs
= OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET
,
2607 .modulemode
= MODULEMODE_HWCTRL
,
2614 * bidirectional, multi-drop, multi-channel two-line serial interface between
2615 * the device and external components
2618 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc
= {
2620 .sysc_offs
= 0x0010,
2621 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
2622 SYSC_HAS_SOFTRESET
),
2623 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2625 .sysc_fields
= &omap_hwmod_sysc_type2
,
2628 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class
= {
2630 .sysc
= &omap44xx_slimbus_sysc
,
2634 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs
[] = {
2635 { .irq
= 97 + OMAP44XX_IRQ_GIC_START
},
2639 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs
[] = {
2640 { .name
= "tx0", .dma_req
= 84 + OMAP44XX_DMA_REQ_START
},
2641 { .name
= "tx1", .dma_req
= 85 + OMAP44XX_DMA_REQ_START
},
2642 { .name
= "tx2", .dma_req
= 86 + OMAP44XX_DMA_REQ_START
},
2643 { .name
= "tx3", .dma_req
= 87 + OMAP44XX_DMA_REQ_START
},
2644 { .name
= "rx0", .dma_req
= 88 + OMAP44XX_DMA_REQ_START
},
2645 { .name
= "rx1", .dma_req
= 89 + OMAP44XX_DMA_REQ_START
},
2646 { .name
= "rx2", .dma_req
= 90 + OMAP44XX_DMA_REQ_START
},
2647 { .name
= "rx3", .dma_req
= 91 + OMAP44XX_DMA_REQ_START
},
2651 static struct omap_hwmod_opt_clk slimbus1_opt_clks
[] = {
2652 { .role
= "fclk_1", .clk
= "slimbus1_fclk_1" },
2653 { .role
= "fclk_0", .clk
= "slimbus1_fclk_0" },
2654 { .role
= "fclk_2", .clk
= "slimbus1_fclk_2" },
2655 { .role
= "slimbus_clk", .clk
= "slimbus1_slimbus_clk" },
2658 static struct omap_hwmod omap44xx_slimbus1_hwmod
= {
2660 .class = &omap44xx_slimbus_hwmod_class
,
2661 .clkdm_name
= "abe_clkdm",
2662 .mpu_irqs
= omap44xx_slimbus1_irqs
,
2663 .sdma_reqs
= omap44xx_slimbus1_sdma_reqs
,
2666 .clkctrl_offs
= OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET
,
2667 .context_offs
= OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET
,
2668 .modulemode
= MODULEMODE_SWCTRL
,
2671 .opt_clks
= slimbus1_opt_clks
,
2672 .opt_clks_cnt
= ARRAY_SIZE(slimbus1_opt_clks
),
2676 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs
[] = {
2677 { .irq
= 98 + OMAP44XX_IRQ_GIC_START
},
2681 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs
[] = {
2682 { .name
= "tx0", .dma_req
= 92 + OMAP44XX_DMA_REQ_START
},
2683 { .name
= "tx1", .dma_req
= 93 + OMAP44XX_DMA_REQ_START
},
2684 { .name
= "tx2", .dma_req
= 94 + OMAP44XX_DMA_REQ_START
},
2685 { .name
= "tx3", .dma_req
= 95 + OMAP44XX_DMA_REQ_START
},
2686 { .name
= "rx0", .dma_req
= 96 + OMAP44XX_DMA_REQ_START
},
2687 { .name
= "rx1", .dma_req
= 97 + OMAP44XX_DMA_REQ_START
},
2688 { .name
= "rx2", .dma_req
= 98 + OMAP44XX_DMA_REQ_START
},
2689 { .name
= "rx3", .dma_req
= 99 + OMAP44XX_DMA_REQ_START
},
2693 static struct omap_hwmod_opt_clk slimbus2_opt_clks
[] = {
2694 { .role
= "fclk_1", .clk
= "slimbus2_fclk_1" },
2695 { .role
= "fclk_0", .clk
= "slimbus2_fclk_0" },
2696 { .role
= "slimbus_clk", .clk
= "slimbus2_slimbus_clk" },
2699 static struct omap_hwmod omap44xx_slimbus2_hwmod
= {
2701 .class = &omap44xx_slimbus_hwmod_class
,
2702 .clkdm_name
= "l4_per_clkdm",
2703 .mpu_irqs
= omap44xx_slimbus2_irqs
,
2704 .sdma_reqs
= omap44xx_slimbus2_sdma_reqs
,
2707 .clkctrl_offs
= OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET
,
2708 .context_offs
= OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET
,
2709 .modulemode
= MODULEMODE_SWCTRL
,
2712 .opt_clks
= slimbus2_opt_clks
,
2713 .opt_clks_cnt
= ARRAY_SIZE(slimbus2_opt_clks
),
2717 * 'smartreflex' class
2718 * smartreflex module (monitor silicon performance and outputs a measure of
2719 * performance error)
2722 /* The IP is not compliant to type1 / type2 scheme */
2723 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex
= {
2728 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc
= {
2729 .sysc_offs
= 0x0038,
2730 .sysc_flags
= (SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
),
2731 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2733 .sysc_fields
= &omap_hwmod_sysc_type_smartreflex
,
2736 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class
= {
2737 .name
= "smartreflex",
2738 .sysc
= &omap44xx_smartreflex_sysc
,
2742 /* smartreflex_core */
2743 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr
= {
2744 .sensor_voltdm_name
= "core",
2747 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs
[] = {
2748 { .irq
= 19 + OMAP44XX_IRQ_GIC_START
},
2752 static struct omap_hwmod omap44xx_smartreflex_core_hwmod
= {
2753 .name
= "smartreflex_core",
2754 .class = &omap44xx_smartreflex_hwmod_class
,
2755 .clkdm_name
= "l4_ao_clkdm",
2756 .mpu_irqs
= omap44xx_smartreflex_core_irqs
,
2758 .main_clk
= "smartreflex_core_fck",
2761 .clkctrl_offs
= OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET
,
2762 .context_offs
= OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET
,
2763 .modulemode
= MODULEMODE_SWCTRL
,
2766 .dev_attr
= &smartreflex_core_dev_attr
,
2769 /* smartreflex_iva */
2770 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr
= {
2771 .sensor_voltdm_name
= "iva",
2774 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs
[] = {
2775 { .irq
= 102 + OMAP44XX_IRQ_GIC_START
},
2779 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod
= {
2780 .name
= "smartreflex_iva",
2781 .class = &omap44xx_smartreflex_hwmod_class
,
2782 .clkdm_name
= "l4_ao_clkdm",
2783 .mpu_irqs
= omap44xx_smartreflex_iva_irqs
,
2784 .main_clk
= "smartreflex_iva_fck",
2787 .clkctrl_offs
= OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET
,
2788 .context_offs
= OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET
,
2789 .modulemode
= MODULEMODE_SWCTRL
,
2792 .dev_attr
= &smartreflex_iva_dev_attr
,
2795 /* smartreflex_mpu */
2796 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr
= {
2797 .sensor_voltdm_name
= "mpu",
2800 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs
[] = {
2801 { .irq
= 18 + OMAP44XX_IRQ_GIC_START
},
2805 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod
= {
2806 .name
= "smartreflex_mpu",
2807 .class = &omap44xx_smartreflex_hwmod_class
,
2808 .clkdm_name
= "l4_ao_clkdm",
2809 .mpu_irqs
= omap44xx_smartreflex_mpu_irqs
,
2810 .main_clk
= "smartreflex_mpu_fck",
2813 .clkctrl_offs
= OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET
,
2814 .context_offs
= OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET
,
2815 .modulemode
= MODULEMODE_SWCTRL
,
2818 .dev_attr
= &smartreflex_mpu_dev_attr
,
2823 * spinlock provides hardware assistance for synchronizing the processes
2824 * running on multiple processors
2827 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc
= {
2829 .sysc_offs
= 0x0010,
2830 .syss_offs
= 0x0014,
2831 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
2832 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
2833 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
2834 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2836 .sysc_fields
= &omap_hwmod_sysc_type1
,
2839 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class
= {
2841 .sysc
= &omap44xx_spinlock_sysc
,
2845 static struct omap_hwmod omap44xx_spinlock_hwmod
= {
2847 .class = &omap44xx_spinlock_hwmod_class
,
2848 .clkdm_name
= "l4_cfg_clkdm",
2851 .clkctrl_offs
= OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET
,
2852 .context_offs
= OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET
,
2859 * general purpose timer module with accurate 1ms tick
2860 * This class contains several variants: ['timer_1ms', 'timer']
2863 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc
= {
2865 .sysc_offs
= 0x0010,
2866 .syss_offs
= 0x0014,
2867 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
2868 SYSC_HAS_EMUFREE
| SYSC_HAS_ENAWAKEUP
|
2869 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
2870 SYSS_HAS_RESET_STATUS
),
2871 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
2872 .sysc_fields
= &omap_hwmod_sysc_type1
,
2875 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class
= {
2877 .sysc
= &omap44xx_timer_1ms_sysc
,
2880 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc
= {
2882 .sysc_offs
= 0x0010,
2883 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
2884 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
2885 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2887 .sysc_fields
= &omap_hwmod_sysc_type2
,
2890 static struct omap_hwmod_class omap44xx_timer_hwmod_class
= {
2892 .sysc
= &omap44xx_timer_sysc
,
2895 /* always-on timers dev attribute */
2896 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr
= {
2897 .timer_capability
= OMAP_TIMER_ALWON
,
2900 /* pwm timers dev attribute */
2901 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr
= {
2902 .timer_capability
= OMAP_TIMER_HAS_PWM
,
2906 static struct omap_hwmod_irq_info omap44xx_timer1_irqs
[] = {
2907 { .irq
= 37 + OMAP44XX_IRQ_GIC_START
},
2911 static struct omap_hwmod omap44xx_timer1_hwmod
= {
2913 .class = &omap44xx_timer_1ms_hwmod_class
,
2914 .clkdm_name
= "l4_wkup_clkdm",
2915 .mpu_irqs
= omap44xx_timer1_irqs
,
2916 .main_clk
= "timer1_fck",
2919 .clkctrl_offs
= OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET
,
2920 .context_offs
= OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET
,
2921 .modulemode
= MODULEMODE_SWCTRL
,
2924 .dev_attr
= &capability_alwon_dev_attr
,
2928 static struct omap_hwmod_irq_info omap44xx_timer2_irqs
[] = {
2929 { .irq
= 38 + OMAP44XX_IRQ_GIC_START
},
2933 static struct omap_hwmod omap44xx_timer2_hwmod
= {
2935 .class = &omap44xx_timer_1ms_hwmod_class
,
2936 .clkdm_name
= "l4_per_clkdm",
2937 .mpu_irqs
= omap44xx_timer2_irqs
,
2938 .main_clk
= "timer2_fck",
2941 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET
,
2942 .context_offs
= OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET
,
2943 .modulemode
= MODULEMODE_SWCTRL
,
2946 .dev_attr
= &capability_alwon_dev_attr
,
2950 static struct omap_hwmod_irq_info omap44xx_timer3_irqs
[] = {
2951 { .irq
= 39 + OMAP44XX_IRQ_GIC_START
},
2955 static struct omap_hwmod omap44xx_timer3_hwmod
= {
2957 .class = &omap44xx_timer_hwmod_class
,
2958 .clkdm_name
= "l4_per_clkdm",
2959 .mpu_irqs
= omap44xx_timer3_irqs
,
2960 .main_clk
= "timer3_fck",
2963 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET
,
2964 .context_offs
= OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET
,
2965 .modulemode
= MODULEMODE_SWCTRL
,
2968 .dev_attr
= &capability_alwon_dev_attr
,
2972 static struct omap_hwmod_irq_info omap44xx_timer4_irqs
[] = {
2973 { .irq
= 40 + OMAP44XX_IRQ_GIC_START
},
2977 static struct omap_hwmod omap44xx_timer4_hwmod
= {
2979 .class = &omap44xx_timer_hwmod_class
,
2980 .clkdm_name
= "l4_per_clkdm",
2981 .mpu_irqs
= omap44xx_timer4_irqs
,
2982 .main_clk
= "timer4_fck",
2985 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET
,
2986 .context_offs
= OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET
,
2987 .modulemode
= MODULEMODE_SWCTRL
,
2990 .dev_attr
= &capability_alwon_dev_attr
,
2994 static struct omap_hwmod_irq_info omap44xx_timer5_irqs
[] = {
2995 { .irq
= 41 + OMAP44XX_IRQ_GIC_START
},
2999 static struct omap_hwmod omap44xx_timer5_hwmod
= {
3001 .class = &omap44xx_timer_hwmod_class
,
3002 .clkdm_name
= "abe_clkdm",
3003 .mpu_irqs
= omap44xx_timer5_irqs
,
3004 .main_clk
= "timer5_fck",
3007 .clkctrl_offs
= OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET
,
3008 .context_offs
= OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET
,
3009 .modulemode
= MODULEMODE_SWCTRL
,
3012 .dev_attr
= &capability_alwon_dev_attr
,
3016 static struct omap_hwmod_irq_info omap44xx_timer6_irqs
[] = {
3017 { .irq
= 42 + OMAP44XX_IRQ_GIC_START
},
3021 static struct omap_hwmod omap44xx_timer6_hwmod
= {
3023 .class = &omap44xx_timer_hwmod_class
,
3024 .clkdm_name
= "abe_clkdm",
3025 .mpu_irqs
= omap44xx_timer6_irqs
,
3027 .main_clk
= "timer6_fck",
3030 .clkctrl_offs
= OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET
,
3031 .context_offs
= OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET
,
3032 .modulemode
= MODULEMODE_SWCTRL
,
3035 .dev_attr
= &capability_alwon_dev_attr
,
3039 static struct omap_hwmod_irq_info omap44xx_timer7_irqs
[] = {
3040 { .irq
= 43 + OMAP44XX_IRQ_GIC_START
},
3044 static struct omap_hwmod omap44xx_timer7_hwmod
= {
3046 .class = &omap44xx_timer_hwmod_class
,
3047 .clkdm_name
= "abe_clkdm",
3048 .mpu_irqs
= omap44xx_timer7_irqs
,
3049 .main_clk
= "timer7_fck",
3052 .clkctrl_offs
= OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET
,
3053 .context_offs
= OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET
,
3054 .modulemode
= MODULEMODE_SWCTRL
,
3057 .dev_attr
= &capability_alwon_dev_attr
,
3061 static struct omap_hwmod_irq_info omap44xx_timer8_irqs
[] = {
3062 { .irq
= 44 + OMAP44XX_IRQ_GIC_START
},
3066 static struct omap_hwmod omap44xx_timer8_hwmod
= {
3068 .class = &omap44xx_timer_hwmod_class
,
3069 .clkdm_name
= "abe_clkdm",
3070 .mpu_irqs
= omap44xx_timer8_irqs
,
3071 .main_clk
= "timer8_fck",
3074 .clkctrl_offs
= OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET
,
3075 .context_offs
= OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET
,
3076 .modulemode
= MODULEMODE_SWCTRL
,
3079 .dev_attr
= &capability_pwm_dev_attr
,
3083 static struct omap_hwmod_irq_info omap44xx_timer9_irqs
[] = {
3084 { .irq
= 45 + OMAP44XX_IRQ_GIC_START
},
3088 static struct omap_hwmod omap44xx_timer9_hwmod
= {
3090 .class = &omap44xx_timer_hwmod_class
,
3091 .clkdm_name
= "l4_per_clkdm",
3092 .mpu_irqs
= omap44xx_timer9_irqs
,
3093 .main_clk
= "timer9_fck",
3096 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET
,
3097 .context_offs
= OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET
,
3098 .modulemode
= MODULEMODE_SWCTRL
,
3101 .dev_attr
= &capability_pwm_dev_attr
,
3105 static struct omap_hwmod_irq_info omap44xx_timer10_irqs
[] = {
3106 { .irq
= 46 + OMAP44XX_IRQ_GIC_START
},
3110 static struct omap_hwmod omap44xx_timer10_hwmod
= {
3112 .class = &omap44xx_timer_1ms_hwmod_class
,
3113 .clkdm_name
= "l4_per_clkdm",
3114 .mpu_irqs
= omap44xx_timer10_irqs
,
3115 .main_clk
= "timer10_fck",
3118 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET
,
3119 .context_offs
= OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET
,
3120 .modulemode
= MODULEMODE_SWCTRL
,
3123 .dev_attr
= &capability_pwm_dev_attr
,
3127 static struct omap_hwmod_irq_info omap44xx_timer11_irqs
[] = {
3128 { .irq
= 47 + OMAP44XX_IRQ_GIC_START
},
3132 static struct omap_hwmod omap44xx_timer11_hwmod
= {
3134 .class = &omap44xx_timer_hwmod_class
,
3135 .clkdm_name
= "l4_per_clkdm",
3136 .mpu_irqs
= omap44xx_timer11_irqs
,
3137 .main_clk
= "timer11_fck",
3140 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET
,
3141 .context_offs
= OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET
,
3142 .modulemode
= MODULEMODE_SWCTRL
,
3145 .dev_attr
= &capability_pwm_dev_attr
,
3150 * universal asynchronous receiver/transmitter (uart)
3153 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc
= {
3155 .sysc_offs
= 0x0054,
3156 .syss_offs
= 0x0058,
3157 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
3158 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
3159 SYSS_HAS_RESET_STATUS
),
3160 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3162 .sysc_fields
= &omap_hwmod_sysc_type1
,
3165 static struct omap_hwmod_class omap44xx_uart_hwmod_class
= {
3167 .sysc
= &omap44xx_uart_sysc
,
3171 static struct omap_hwmod_irq_info omap44xx_uart1_irqs
[] = {
3172 { .irq
= 72 + OMAP44XX_IRQ_GIC_START
},
3176 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs
[] = {
3177 { .name
= "tx", .dma_req
= 48 + OMAP44XX_DMA_REQ_START
},
3178 { .name
= "rx", .dma_req
= 49 + OMAP44XX_DMA_REQ_START
},
3182 static struct omap_hwmod omap44xx_uart1_hwmod
= {
3184 .class = &omap44xx_uart_hwmod_class
,
3185 .clkdm_name
= "l4_per_clkdm",
3186 .mpu_irqs
= omap44xx_uart1_irqs
,
3187 .sdma_reqs
= omap44xx_uart1_sdma_reqs
,
3188 .main_clk
= "uart1_fck",
3191 .clkctrl_offs
= OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET
,
3192 .context_offs
= OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET
,
3193 .modulemode
= MODULEMODE_SWCTRL
,
3199 static struct omap_hwmod_irq_info omap44xx_uart2_irqs
[] = {
3200 { .irq
= 73 + OMAP44XX_IRQ_GIC_START
},
3204 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs
[] = {
3205 { .name
= "tx", .dma_req
= 50 + OMAP44XX_DMA_REQ_START
},
3206 { .name
= "rx", .dma_req
= 51 + OMAP44XX_DMA_REQ_START
},
3210 static struct omap_hwmod omap44xx_uart2_hwmod
= {
3212 .class = &omap44xx_uart_hwmod_class
,
3213 .clkdm_name
= "l4_per_clkdm",
3214 .mpu_irqs
= omap44xx_uart2_irqs
,
3215 .sdma_reqs
= omap44xx_uart2_sdma_reqs
,
3216 .main_clk
= "uart2_fck",
3219 .clkctrl_offs
= OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET
,
3220 .context_offs
= OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET
,
3221 .modulemode
= MODULEMODE_SWCTRL
,
3227 static struct omap_hwmod_irq_info omap44xx_uart3_irqs
[] = {
3228 { .irq
= 74 + OMAP44XX_IRQ_GIC_START
},
3232 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs
[] = {
3233 { .name
= "tx", .dma_req
= 52 + OMAP44XX_DMA_REQ_START
},
3234 { .name
= "rx", .dma_req
= 53 + OMAP44XX_DMA_REQ_START
},
3238 static struct omap_hwmod omap44xx_uart3_hwmod
= {
3240 .class = &omap44xx_uart_hwmod_class
,
3241 .clkdm_name
= "l4_per_clkdm",
3242 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
3243 .mpu_irqs
= omap44xx_uart3_irqs
,
3244 .sdma_reqs
= omap44xx_uart3_sdma_reqs
,
3245 .main_clk
= "uart3_fck",
3248 .clkctrl_offs
= OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET
,
3249 .context_offs
= OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET
,
3250 .modulemode
= MODULEMODE_SWCTRL
,
3256 static struct omap_hwmod_irq_info omap44xx_uart4_irqs
[] = {
3257 { .irq
= 70 + OMAP44XX_IRQ_GIC_START
},
3261 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs
[] = {
3262 { .name
= "tx", .dma_req
= 54 + OMAP44XX_DMA_REQ_START
},
3263 { .name
= "rx", .dma_req
= 55 + OMAP44XX_DMA_REQ_START
},
3267 static struct omap_hwmod omap44xx_uart4_hwmod
= {
3269 .class = &omap44xx_uart_hwmod_class
,
3270 .clkdm_name
= "l4_per_clkdm",
3271 .mpu_irqs
= omap44xx_uart4_irqs
,
3272 .sdma_reqs
= omap44xx_uart4_sdma_reqs
,
3273 .main_clk
= "uart4_fck",
3276 .clkctrl_offs
= OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET
,
3277 .context_offs
= OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET
,
3278 .modulemode
= MODULEMODE_SWCTRL
,
3284 * 'usb_host_fs' class
3285 * full-speed usb host controller
3288 /* The IP is not compliant to type1 / type2 scheme */
3289 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs
= {
3295 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc
= {
3297 .sysc_offs
= 0x0210,
3298 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
|
3299 SYSC_HAS_SOFTRESET
),
3300 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3302 .sysc_fields
= &omap_hwmod_sysc_type_usb_host_fs
,
3305 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class
= {
3306 .name
= "usb_host_fs",
3307 .sysc
= &omap44xx_usb_host_fs_sysc
,
3311 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs
[] = {
3312 { .name
= "std", .irq
= 89 + OMAP44XX_IRQ_GIC_START
},
3313 { .name
= "smi", .irq
= 90 + OMAP44XX_IRQ_GIC_START
},
3317 static struct omap_hwmod omap44xx_usb_host_fs_hwmod
= {
3318 .name
= "usb_host_fs",
3319 .class = &omap44xx_usb_host_fs_hwmod_class
,
3320 .clkdm_name
= "l3_init_clkdm",
3321 .mpu_irqs
= omap44xx_usb_host_fs_irqs
,
3322 .main_clk
= "usb_host_fs_fck",
3325 .clkctrl_offs
= OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET
,
3326 .context_offs
= OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET
,
3327 .modulemode
= MODULEMODE_SWCTRL
,
3333 * 'usb_host_hs' class
3334 * high-speed multi-port usb host controller
3337 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc
= {
3339 .sysc_offs
= 0x0010,
3340 .syss_offs
= 0x0014,
3341 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
|
3342 SYSC_HAS_SOFTRESET
),
3343 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3344 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
3345 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
3346 .sysc_fields
= &omap_hwmod_sysc_type2
,
3349 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class
= {
3350 .name
= "usb_host_hs",
3351 .sysc
= &omap44xx_usb_host_hs_sysc
,
3355 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs
[] = {
3356 { .name
= "ohci-irq", .irq
= 76 + OMAP44XX_IRQ_GIC_START
},
3357 { .name
= "ehci-irq", .irq
= 77 + OMAP44XX_IRQ_GIC_START
},
3361 static struct omap_hwmod omap44xx_usb_host_hs_hwmod
= {
3362 .name
= "usb_host_hs",
3363 .class = &omap44xx_usb_host_hs_hwmod_class
,
3364 .clkdm_name
= "l3_init_clkdm",
3365 .main_clk
= "usb_host_hs_fck",
3368 .clkctrl_offs
= OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET
,
3369 .context_offs
= OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET
,
3370 .modulemode
= MODULEMODE_SWCTRL
,
3373 .mpu_irqs
= omap44xx_usb_host_hs_irqs
,
3376 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3380 * In the following configuration :
3381 * - USBHOST module is set to smart-idle mode
3382 * - PRCM asserts idle_req to the USBHOST module ( This typically
3383 * happens when the system is going to a low power mode : all ports
3384 * have been suspended, the master part of the USBHOST module has
3385 * entered the standby state, and SW has cut the functional clocks)
3386 * - an USBHOST interrupt occurs before the module is able to answer
3387 * idle_ack, typically a remote wakeup IRQ.
3388 * Then the USB HOST module will enter a deadlock situation where it
3389 * is no more accessible nor functional.
3392 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3396 * Errata: USB host EHCI may stall when entering smart-standby mode
3400 * When the USBHOST module is set to smart-standby mode, and when it is
3401 * ready to enter the standby state (i.e. all ports are suspended and
3402 * all attached devices are in suspend mode), then it can wrongly assert
3403 * the Mstandby signal too early while there are still some residual OCP
3404 * transactions ongoing. If this condition occurs, the internal state
3405 * machine may go to an undefined state and the USB link may be stuck
3406 * upon the next resume.
3409 * Don't use smart standby; use only force standby,
3410 * hence HWMOD_SWSUP_MSTANDBY
3414 * During system boot; If the hwmod framework resets the module
3415 * the module will have smart idle settings; which can lead to deadlock
3416 * (above Errata Id:i660); so, dont reset the module during boot;
3417 * Use HWMOD_INIT_NO_RESET.
3420 .flags
= HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
|
3421 HWMOD_INIT_NO_RESET
,
3425 * 'usb_otg_hs' class
3426 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3429 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc
= {
3431 .sysc_offs
= 0x0404,
3432 .syss_offs
= 0x0408,
3433 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
3434 SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
|
3435 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
3436 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3437 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
3439 .sysc_fields
= &omap_hwmod_sysc_type1
,
3442 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class
= {
3443 .name
= "usb_otg_hs",
3444 .sysc
= &omap44xx_usb_otg_hs_sysc
,
3448 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs
[] = {
3449 { .name
= "mc", .irq
= 92 + OMAP44XX_IRQ_GIC_START
},
3450 { .name
= "dma", .irq
= 93 + OMAP44XX_IRQ_GIC_START
},
3454 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks
[] = {
3455 { .role
= "xclk", .clk
= "usb_otg_hs_xclk" },
3458 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod
= {
3459 .name
= "usb_otg_hs",
3460 .class = &omap44xx_usb_otg_hs_hwmod_class
,
3461 .clkdm_name
= "l3_init_clkdm",
3462 .flags
= HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
,
3463 .mpu_irqs
= omap44xx_usb_otg_hs_irqs
,
3464 .main_clk
= "usb_otg_hs_ick",
3467 .clkctrl_offs
= OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET
,
3468 .context_offs
= OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET
,
3469 .modulemode
= MODULEMODE_HWCTRL
,
3472 .opt_clks
= usb_otg_hs_opt_clks
,
3473 .opt_clks_cnt
= ARRAY_SIZE(usb_otg_hs_opt_clks
),
3477 * 'usb_tll_hs' class
3478 * usb_tll_hs module is the adapter on the usb_host_hs ports
3481 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc
= {
3483 .sysc_offs
= 0x0010,
3484 .syss_offs
= 0x0014,
3485 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
3486 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
3488 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
3489 .sysc_fields
= &omap_hwmod_sysc_type1
,
3492 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class
= {
3493 .name
= "usb_tll_hs",
3494 .sysc
= &omap44xx_usb_tll_hs_sysc
,
3497 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs
[] = {
3498 { .name
= "tll-irq", .irq
= 78 + OMAP44XX_IRQ_GIC_START
},
3502 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod
= {
3503 .name
= "usb_tll_hs",
3504 .class = &omap44xx_usb_tll_hs_hwmod_class
,
3505 .clkdm_name
= "l3_init_clkdm",
3506 .mpu_irqs
= omap44xx_usb_tll_hs_irqs
,
3507 .main_clk
= "usb_tll_hs_ick",
3510 .clkctrl_offs
= OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET
,
3511 .context_offs
= OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET
,
3512 .modulemode
= MODULEMODE_HWCTRL
,
3519 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3520 * overflow condition
3523 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc
= {
3525 .sysc_offs
= 0x0010,
3526 .syss_offs
= 0x0014,
3527 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_SIDLEMODE
|
3528 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
3529 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3531 .sysc_fields
= &omap_hwmod_sysc_type1
,
3534 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class
= {
3536 .sysc
= &omap44xx_wd_timer_sysc
,
3537 .pre_shutdown
= &omap2_wd_timer_disable
,
3538 .reset
= &omap2_wd_timer_reset
,
3542 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs
[] = {
3543 { .irq
= 80 + OMAP44XX_IRQ_GIC_START
},
3547 static struct omap_hwmod omap44xx_wd_timer2_hwmod
= {
3548 .name
= "wd_timer2",
3549 .class = &omap44xx_wd_timer_hwmod_class
,
3550 .clkdm_name
= "l4_wkup_clkdm",
3551 .mpu_irqs
= omap44xx_wd_timer2_irqs
,
3552 .main_clk
= "wd_timer2_fck",
3555 .clkctrl_offs
= OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET
,
3556 .context_offs
= OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET
,
3557 .modulemode
= MODULEMODE_SWCTRL
,
3563 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs
[] = {
3564 { .irq
= 36 + OMAP44XX_IRQ_GIC_START
},
3568 static struct omap_hwmod omap44xx_wd_timer3_hwmod
= {
3569 .name
= "wd_timer3",
3570 .class = &omap44xx_wd_timer_hwmod_class
,
3571 .clkdm_name
= "abe_clkdm",
3572 .mpu_irqs
= omap44xx_wd_timer3_irqs
,
3573 .main_clk
= "wd_timer3_fck",
3576 .clkctrl_offs
= OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET
,
3577 .context_offs
= OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET
,
3578 .modulemode
= MODULEMODE_SWCTRL
,
3588 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs
[] = {
3590 .pa_start
= 0x4a204000,
3591 .pa_end
= 0x4a2040ff,
3592 .flags
= ADDR_TYPE_RT
3597 /* c2c -> c2c_target_fw */
3598 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw
= {
3599 .master
= &omap44xx_c2c_hwmod
,
3600 .slave
= &omap44xx_c2c_target_fw_hwmod
,
3601 .clk
= "div_core_ck",
3602 .addr
= omap44xx_c2c_target_fw_addrs
,
3603 .user
= OCP_USER_MPU
,
3606 /* l4_cfg -> c2c_target_fw */
3607 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw
= {
3608 .master
= &omap44xx_l4_cfg_hwmod
,
3609 .slave
= &omap44xx_c2c_target_fw_hwmod
,
3611 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3614 /* l3_main_1 -> dmm */
3615 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm
= {
3616 .master
= &omap44xx_l3_main_1_hwmod
,
3617 .slave
= &omap44xx_dmm_hwmod
,
3619 .user
= OCP_USER_SDMA
,
3622 static struct omap_hwmod_addr_space omap44xx_dmm_addrs
[] = {
3624 .pa_start
= 0x4e000000,
3625 .pa_end
= 0x4e0007ff,
3626 .flags
= ADDR_TYPE_RT
3632 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm
= {
3633 .master
= &omap44xx_mpu_hwmod
,
3634 .slave
= &omap44xx_dmm_hwmod
,
3636 .addr
= omap44xx_dmm_addrs
,
3637 .user
= OCP_USER_MPU
,
3640 /* c2c -> emif_fw */
3641 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw
= {
3642 .master
= &omap44xx_c2c_hwmod
,
3643 .slave
= &omap44xx_emif_fw_hwmod
,
3644 .clk
= "div_core_ck",
3645 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3648 /* dmm -> emif_fw */
3649 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw
= {
3650 .master
= &omap44xx_dmm_hwmod
,
3651 .slave
= &omap44xx_emif_fw_hwmod
,
3653 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3656 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs
[] = {
3658 .pa_start
= 0x4a20c000,
3659 .pa_end
= 0x4a20c0ff,
3660 .flags
= ADDR_TYPE_RT
3665 /* l4_cfg -> emif_fw */
3666 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw
= {
3667 .master
= &omap44xx_l4_cfg_hwmod
,
3668 .slave
= &omap44xx_emif_fw_hwmod
,
3670 .addr
= omap44xx_emif_fw_addrs
,
3671 .user
= OCP_USER_MPU
,
3674 /* iva -> l3_instr */
3675 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr
= {
3676 .master
= &omap44xx_iva_hwmod
,
3677 .slave
= &omap44xx_l3_instr_hwmod
,
3679 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3682 /* l3_main_3 -> l3_instr */
3683 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr
= {
3684 .master
= &omap44xx_l3_main_3_hwmod
,
3685 .slave
= &omap44xx_l3_instr_hwmod
,
3687 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3690 /* ocp_wp_noc -> l3_instr */
3691 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr
= {
3692 .master
= &omap44xx_ocp_wp_noc_hwmod
,
3693 .slave
= &omap44xx_l3_instr_hwmod
,
3695 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3698 /* dsp -> l3_main_1 */
3699 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1
= {
3700 .master
= &omap44xx_dsp_hwmod
,
3701 .slave
= &omap44xx_l3_main_1_hwmod
,
3703 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3706 /* dss -> l3_main_1 */
3707 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1
= {
3708 .master
= &omap44xx_dss_hwmod
,
3709 .slave
= &omap44xx_l3_main_1_hwmod
,
3711 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3714 /* l3_main_2 -> l3_main_1 */
3715 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1
= {
3716 .master
= &omap44xx_l3_main_2_hwmod
,
3717 .slave
= &omap44xx_l3_main_1_hwmod
,
3719 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3722 /* l4_cfg -> l3_main_1 */
3723 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1
= {
3724 .master
= &omap44xx_l4_cfg_hwmod
,
3725 .slave
= &omap44xx_l3_main_1_hwmod
,
3727 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3730 /* mmc1 -> l3_main_1 */
3731 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1
= {
3732 .master
= &omap44xx_mmc1_hwmod
,
3733 .slave
= &omap44xx_l3_main_1_hwmod
,
3735 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3738 /* mmc2 -> l3_main_1 */
3739 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1
= {
3740 .master
= &omap44xx_mmc2_hwmod
,
3741 .slave
= &omap44xx_l3_main_1_hwmod
,
3743 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3746 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs
[] = {
3748 .pa_start
= 0x44000000,
3749 .pa_end
= 0x44000fff,
3750 .flags
= ADDR_TYPE_RT
3755 /* mpu -> l3_main_1 */
3756 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1
= {
3757 .master
= &omap44xx_mpu_hwmod
,
3758 .slave
= &omap44xx_l3_main_1_hwmod
,
3760 .addr
= omap44xx_l3_main_1_addrs
,
3761 .user
= OCP_USER_MPU
,
3764 /* c2c_target_fw -> l3_main_2 */
3765 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2
= {
3766 .master
= &omap44xx_c2c_target_fw_hwmod
,
3767 .slave
= &omap44xx_l3_main_2_hwmod
,
3769 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3772 /* debugss -> l3_main_2 */
3773 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2
= {
3774 .master
= &omap44xx_debugss_hwmod
,
3775 .slave
= &omap44xx_l3_main_2_hwmod
,
3776 .clk
= "dbgclk_mux_ck",
3777 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3780 /* dma_system -> l3_main_2 */
3781 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2
= {
3782 .master
= &omap44xx_dma_system_hwmod
,
3783 .slave
= &omap44xx_l3_main_2_hwmod
,
3785 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3788 /* fdif -> l3_main_2 */
3789 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2
= {
3790 .master
= &omap44xx_fdif_hwmod
,
3791 .slave
= &omap44xx_l3_main_2_hwmod
,
3793 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3796 /* gpu -> l3_main_2 */
3797 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2
= {
3798 .master
= &omap44xx_gpu_hwmod
,
3799 .slave
= &omap44xx_l3_main_2_hwmod
,
3801 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3804 /* hsi -> l3_main_2 */
3805 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2
= {
3806 .master
= &omap44xx_hsi_hwmod
,
3807 .slave
= &omap44xx_l3_main_2_hwmod
,
3809 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3812 /* ipu -> l3_main_2 */
3813 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2
= {
3814 .master
= &omap44xx_ipu_hwmod
,
3815 .slave
= &omap44xx_l3_main_2_hwmod
,
3817 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3820 /* iss -> l3_main_2 */
3821 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2
= {
3822 .master
= &omap44xx_iss_hwmod
,
3823 .slave
= &omap44xx_l3_main_2_hwmod
,
3825 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3828 /* iva -> l3_main_2 */
3829 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2
= {
3830 .master
= &omap44xx_iva_hwmod
,
3831 .slave
= &omap44xx_l3_main_2_hwmod
,
3833 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3836 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs
[] = {
3838 .pa_start
= 0x44800000,
3839 .pa_end
= 0x44801fff,
3840 .flags
= ADDR_TYPE_RT
3845 /* l3_main_1 -> l3_main_2 */
3846 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2
= {
3847 .master
= &omap44xx_l3_main_1_hwmod
,
3848 .slave
= &omap44xx_l3_main_2_hwmod
,
3850 .addr
= omap44xx_l3_main_2_addrs
,
3851 .user
= OCP_USER_MPU
,
3854 /* l4_cfg -> l3_main_2 */
3855 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2
= {
3856 .master
= &omap44xx_l4_cfg_hwmod
,
3857 .slave
= &omap44xx_l3_main_2_hwmod
,
3859 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3862 /* usb_host_fs -> l3_main_2 */
3863 static struct omap_hwmod_ocp_if omap44xx_usb_host_fs__l3_main_2
= {
3864 .master
= &omap44xx_usb_host_fs_hwmod
,
3865 .slave
= &omap44xx_l3_main_2_hwmod
,
3867 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3870 /* usb_host_hs -> l3_main_2 */
3871 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2
= {
3872 .master
= &omap44xx_usb_host_hs_hwmod
,
3873 .slave
= &omap44xx_l3_main_2_hwmod
,
3875 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3878 /* usb_otg_hs -> l3_main_2 */
3879 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2
= {
3880 .master
= &omap44xx_usb_otg_hs_hwmod
,
3881 .slave
= &omap44xx_l3_main_2_hwmod
,
3883 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3886 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs
[] = {
3888 .pa_start
= 0x45000000,
3889 .pa_end
= 0x45000fff,
3890 .flags
= ADDR_TYPE_RT
3895 /* l3_main_1 -> l3_main_3 */
3896 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3
= {
3897 .master
= &omap44xx_l3_main_1_hwmod
,
3898 .slave
= &omap44xx_l3_main_3_hwmod
,
3900 .addr
= omap44xx_l3_main_3_addrs
,
3901 .user
= OCP_USER_MPU
,
3904 /* l3_main_2 -> l3_main_3 */
3905 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3
= {
3906 .master
= &omap44xx_l3_main_2_hwmod
,
3907 .slave
= &omap44xx_l3_main_3_hwmod
,
3909 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3912 /* l4_cfg -> l3_main_3 */
3913 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3
= {
3914 .master
= &omap44xx_l4_cfg_hwmod
,
3915 .slave
= &omap44xx_l3_main_3_hwmod
,
3917 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3920 /* aess -> l4_abe */
3921 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe
= {
3922 .master
= &omap44xx_aess_hwmod
,
3923 .slave
= &omap44xx_l4_abe_hwmod
,
3924 .clk
= "ocp_abe_iclk",
3925 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3929 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe
= {
3930 .master
= &omap44xx_dsp_hwmod
,
3931 .slave
= &omap44xx_l4_abe_hwmod
,
3932 .clk
= "ocp_abe_iclk",
3933 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3936 /* l3_main_1 -> l4_abe */
3937 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe
= {
3938 .master
= &omap44xx_l3_main_1_hwmod
,
3939 .slave
= &omap44xx_l4_abe_hwmod
,
3941 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3945 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe
= {
3946 .master
= &omap44xx_mpu_hwmod
,
3947 .slave
= &omap44xx_l4_abe_hwmod
,
3948 .clk
= "ocp_abe_iclk",
3949 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3952 /* l3_main_1 -> l4_cfg */
3953 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg
= {
3954 .master
= &omap44xx_l3_main_1_hwmod
,
3955 .slave
= &omap44xx_l4_cfg_hwmod
,
3957 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3960 /* l3_main_2 -> l4_per */
3961 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per
= {
3962 .master
= &omap44xx_l3_main_2_hwmod
,
3963 .slave
= &omap44xx_l4_per_hwmod
,
3965 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3968 /* l4_cfg -> l4_wkup */
3969 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup
= {
3970 .master
= &omap44xx_l4_cfg_hwmod
,
3971 .slave
= &omap44xx_l4_wkup_hwmod
,
3973 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3976 /* mpu -> mpu_private */
3977 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private
= {
3978 .master
= &omap44xx_mpu_hwmod
,
3979 .slave
= &omap44xx_mpu_private_hwmod
,
3981 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3984 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs
[] = {
3986 .pa_start
= 0x4a102000,
3987 .pa_end
= 0x4a10207f,
3988 .flags
= ADDR_TYPE_RT
3993 /* l4_cfg -> ocp_wp_noc */
3994 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc
= {
3995 .master
= &omap44xx_l4_cfg_hwmod
,
3996 .slave
= &omap44xx_ocp_wp_noc_hwmod
,
3998 .addr
= omap44xx_ocp_wp_noc_addrs
,
3999 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4002 static struct omap_hwmod_addr_space omap44xx_aess_addrs
[] = {
4004 .pa_start
= 0x401f1000,
4005 .pa_end
= 0x401f13ff,
4006 .flags
= ADDR_TYPE_RT
4011 /* l4_abe -> aess */
4012 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess
= {
4013 .master
= &omap44xx_l4_abe_hwmod
,
4014 .slave
= &omap44xx_aess_hwmod
,
4015 .clk
= "ocp_abe_iclk",
4016 .addr
= omap44xx_aess_addrs
,
4017 .user
= OCP_USER_MPU
,
4020 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs
[] = {
4022 .pa_start
= 0x490f1000,
4023 .pa_end
= 0x490f13ff,
4024 .flags
= ADDR_TYPE_RT
4029 /* l4_abe -> aess (dma) */
4030 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma
= {
4031 .master
= &omap44xx_l4_abe_hwmod
,
4032 .slave
= &omap44xx_aess_hwmod
,
4033 .clk
= "ocp_abe_iclk",
4034 .addr
= omap44xx_aess_dma_addrs
,
4035 .user
= OCP_USER_SDMA
,
4038 /* l3_main_2 -> c2c */
4039 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c
= {
4040 .master
= &omap44xx_l3_main_2_hwmod
,
4041 .slave
= &omap44xx_c2c_hwmod
,
4043 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4046 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs
[] = {
4048 .pa_start
= 0x4a304000,
4049 .pa_end
= 0x4a30401f,
4050 .flags
= ADDR_TYPE_RT
4055 /* l4_wkup -> counter_32k */
4056 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k
= {
4057 .master
= &omap44xx_l4_wkup_hwmod
,
4058 .slave
= &omap44xx_counter_32k_hwmod
,
4059 .clk
= "l4_wkup_clk_mux_ck",
4060 .addr
= omap44xx_counter_32k_addrs
,
4061 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4064 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs
[] = {
4066 .pa_start
= 0x4a002000,
4067 .pa_end
= 0x4a0027ff,
4068 .flags
= ADDR_TYPE_RT
4073 /* l4_cfg -> ctrl_module_core */
4074 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core
= {
4075 .master
= &omap44xx_l4_cfg_hwmod
,
4076 .slave
= &omap44xx_ctrl_module_core_hwmod
,
4078 .addr
= omap44xx_ctrl_module_core_addrs
,
4079 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4082 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs
[] = {
4084 .pa_start
= 0x4a100000,
4085 .pa_end
= 0x4a1007ff,
4086 .flags
= ADDR_TYPE_RT
4091 /* l4_cfg -> ctrl_module_pad_core */
4092 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core
= {
4093 .master
= &omap44xx_l4_cfg_hwmod
,
4094 .slave
= &omap44xx_ctrl_module_pad_core_hwmod
,
4096 .addr
= omap44xx_ctrl_module_pad_core_addrs
,
4097 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4100 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs
[] = {
4102 .pa_start
= 0x4a30c000,
4103 .pa_end
= 0x4a30c7ff,
4104 .flags
= ADDR_TYPE_RT
4109 /* l4_wkup -> ctrl_module_wkup */
4110 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup
= {
4111 .master
= &omap44xx_l4_wkup_hwmod
,
4112 .slave
= &omap44xx_ctrl_module_wkup_hwmod
,
4113 .clk
= "l4_wkup_clk_mux_ck",
4114 .addr
= omap44xx_ctrl_module_wkup_addrs
,
4115 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4118 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs
[] = {
4120 .pa_start
= 0x4a31e000,
4121 .pa_end
= 0x4a31e7ff,
4122 .flags
= ADDR_TYPE_RT
4127 /* l4_wkup -> ctrl_module_pad_wkup */
4128 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup
= {
4129 .master
= &omap44xx_l4_wkup_hwmod
,
4130 .slave
= &omap44xx_ctrl_module_pad_wkup_hwmod
,
4131 .clk
= "l4_wkup_clk_mux_ck",
4132 .addr
= omap44xx_ctrl_module_pad_wkup_addrs
,
4133 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4136 static struct omap_hwmod_addr_space omap44xx_debugss_addrs
[] = {
4138 .pa_start
= 0x54160000,
4139 .pa_end
= 0x54167fff,
4140 .flags
= ADDR_TYPE_RT
4145 /* l3_instr -> debugss */
4146 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss
= {
4147 .master
= &omap44xx_l3_instr_hwmod
,
4148 .slave
= &omap44xx_debugss_hwmod
,
4150 .addr
= omap44xx_debugss_addrs
,
4151 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4154 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs
[] = {
4156 .pa_start
= 0x4a056000,
4157 .pa_end
= 0x4a056fff,
4158 .flags
= ADDR_TYPE_RT
4163 /* l4_cfg -> dma_system */
4164 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system
= {
4165 .master
= &omap44xx_l4_cfg_hwmod
,
4166 .slave
= &omap44xx_dma_system_hwmod
,
4168 .addr
= omap44xx_dma_system_addrs
,
4169 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4172 static struct omap_hwmod_addr_space omap44xx_dmic_addrs
[] = {
4175 .pa_start
= 0x4012e000,
4176 .pa_end
= 0x4012e07f,
4177 .flags
= ADDR_TYPE_RT
4182 /* l4_abe -> dmic */
4183 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic
= {
4184 .master
= &omap44xx_l4_abe_hwmod
,
4185 .slave
= &omap44xx_dmic_hwmod
,
4186 .clk
= "ocp_abe_iclk",
4187 .addr
= omap44xx_dmic_addrs
,
4188 .user
= OCP_USER_MPU
,
4191 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs
[] = {
4194 .pa_start
= 0x4902e000,
4195 .pa_end
= 0x4902e07f,
4196 .flags
= ADDR_TYPE_RT
4201 /* l4_abe -> dmic (dma) */
4202 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma
= {
4203 .master
= &omap44xx_l4_abe_hwmod
,
4204 .slave
= &omap44xx_dmic_hwmod
,
4205 .clk
= "ocp_abe_iclk",
4206 .addr
= omap44xx_dmic_dma_addrs
,
4207 .user
= OCP_USER_SDMA
,
4211 static struct omap_hwmod_ocp_if omap44xx_dsp__iva
= {
4212 .master
= &omap44xx_dsp_hwmod
,
4213 .slave
= &omap44xx_iva_hwmod
,
4214 .clk
= "dpll_iva_m5x2_ck",
4215 .user
= OCP_USER_DSP
,
4219 static struct omap_hwmod_ocp_if omap44xx_dsp__sl2if
= {
4220 .master
= &omap44xx_dsp_hwmod
,
4221 .slave
= &omap44xx_sl2if_hwmod
,
4222 .clk
= "dpll_iva_m5x2_ck",
4223 .user
= OCP_USER_DSP
,
4227 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp
= {
4228 .master
= &omap44xx_l4_cfg_hwmod
,
4229 .slave
= &omap44xx_dsp_hwmod
,
4231 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4234 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs
[] = {
4236 .pa_start
= 0x58000000,
4237 .pa_end
= 0x5800007f,
4238 .flags
= ADDR_TYPE_RT
4243 /* l3_main_2 -> dss */
4244 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss
= {
4245 .master
= &omap44xx_l3_main_2_hwmod
,
4246 .slave
= &omap44xx_dss_hwmod
,
4248 .addr
= omap44xx_dss_dma_addrs
,
4249 .user
= OCP_USER_SDMA
,
4252 static struct omap_hwmod_addr_space omap44xx_dss_addrs
[] = {
4254 .pa_start
= 0x48040000,
4255 .pa_end
= 0x4804007f,
4256 .flags
= ADDR_TYPE_RT
4262 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss
= {
4263 .master
= &omap44xx_l4_per_hwmod
,
4264 .slave
= &omap44xx_dss_hwmod
,
4266 .addr
= omap44xx_dss_addrs
,
4267 .user
= OCP_USER_MPU
,
4270 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs
[] = {
4272 .pa_start
= 0x58001000,
4273 .pa_end
= 0x58001fff,
4274 .flags
= ADDR_TYPE_RT
4279 /* l3_main_2 -> dss_dispc */
4280 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc
= {
4281 .master
= &omap44xx_l3_main_2_hwmod
,
4282 .slave
= &omap44xx_dss_dispc_hwmod
,
4284 .addr
= omap44xx_dss_dispc_dma_addrs
,
4285 .user
= OCP_USER_SDMA
,
4288 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs
[] = {
4290 .pa_start
= 0x48041000,
4291 .pa_end
= 0x48041fff,
4292 .flags
= ADDR_TYPE_RT
4297 /* l4_per -> dss_dispc */
4298 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc
= {
4299 .master
= &omap44xx_l4_per_hwmod
,
4300 .slave
= &omap44xx_dss_dispc_hwmod
,
4302 .addr
= omap44xx_dss_dispc_addrs
,
4303 .user
= OCP_USER_MPU
,
4306 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs
[] = {
4308 .pa_start
= 0x58004000,
4309 .pa_end
= 0x580041ff,
4310 .flags
= ADDR_TYPE_RT
4315 /* l3_main_2 -> dss_dsi1 */
4316 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1
= {
4317 .master
= &omap44xx_l3_main_2_hwmod
,
4318 .slave
= &omap44xx_dss_dsi1_hwmod
,
4320 .addr
= omap44xx_dss_dsi1_dma_addrs
,
4321 .user
= OCP_USER_SDMA
,
4324 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs
[] = {
4326 .pa_start
= 0x48044000,
4327 .pa_end
= 0x480441ff,
4328 .flags
= ADDR_TYPE_RT
4333 /* l4_per -> dss_dsi1 */
4334 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1
= {
4335 .master
= &omap44xx_l4_per_hwmod
,
4336 .slave
= &omap44xx_dss_dsi1_hwmod
,
4338 .addr
= omap44xx_dss_dsi1_addrs
,
4339 .user
= OCP_USER_MPU
,
4342 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs
[] = {
4344 .pa_start
= 0x58005000,
4345 .pa_end
= 0x580051ff,
4346 .flags
= ADDR_TYPE_RT
4351 /* l3_main_2 -> dss_dsi2 */
4352 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2
= {
4353 .master
= &omap44xx_l3_main_2_hwmod
,
4354 .slave
= &omap44xx_dss_dsi2_hwmod
,
4356 .addr
= omap44xx_dss_dsi2_dma_addrs
,
4357 .user
= OCP_USER_SDMA
,
4360 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs
[] = {
4362 .pa_start
= 0x48045000,
4363 .pa_end
= 0x480451ff,
4364 .flags
= ADDR_TYPE_RT
4369 /* l4_per -> dss_dsi2 */
4370 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2
= {
4371 .master
= &omap44xx_l4_per_hwmod
,
4372 .slave
= &omap44xx_dss_dsi2_hwmod
,
4374 .addr
= omap44xx_dss_dsi2_addrs
,
4375 .user
= OCP_USER_MPU
,
4378 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs
[] = {
4380 .pa_start
= 0x58006000,
4381 .pa_end
= 0x58006fff,
4382 .flags
= ADDR_TYPE_RT
4387 /* l3_main_2 -> dss_hdmi */
4388 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi
= {
4389 .master
= &omap44xx_l3_main_2_hwmod
,
4390 .slave
= &omap44xx_dss_hdmi_hwmod
,
4392 .addr
= omap44xx_dss_hdmi_dma_addrs
,
4393 .user
= OCP_USER_SDMA
,
4396 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs
[] = {
4398 .pa_start
= 0x48046000,
4399 .pa_end
= 0x48046fff,
4400 .flags
= ADDR_TYPE_RT
4405 /* l4_per -> dss_hdmi */
4406 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi
= {
4407 .master
= &omap44xx_l4_per_hwmod
,
4408 .slave
= &omap44xx_dss_hdmi_hwmod
,
4410 .addr
= omap44xx_dss_hdmi_addrs
,
4411 .user
= OCP_USER_MPU
,
4414 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs
[] = {
4416 .pa_start
= 0x58002000,
4417 .pa_end
= 0x580020ff,
4418 .flags
= ADDR_TYPE_RT
4423 /* l3_main_2 -> dss_rfbi */
4424 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi
= {
4425 .master
= &omap44xx_l3_main_2_hwmod
,
4426 .slave
= &omap44xx_dss_rfbi_hwmod
,
4428 .addr
= omap44xx_dss_rfbi_dma_addrs
,
4429 .user
= OCP_USER_SDMA
,
4432 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs
[] = {
4434 .pa_start
= 0x48042000,
4435 .pa_end
= 0x480420ff,
4436 .flags
= ADDR_TYPE_RT
4441 /* l4_per -> dss_rfbi */
4442 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi
= {
4443 .master
= &omap44xx_l4_per_hwmod
,
4444 .slave
= &omap44xx_dss_rfbi_hwmod
,
4446 .addr
= omap44xx_dss_rfbi_addrs
,
4447 .user
= OCP_USER_MPU
,
4450 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs
[] = {
4452 .pa_start
= 0x58003000,
4453 .pa_end
= 0x580030ff,
4454 .flags
= ADDR_TYPE_RT
4459 /* l3_main_2 -> dss_venc */
4460 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc
= {
4461 .master
= &omap44xx_l3_main_2_hwmod
,
4462 .slave
= &omap44xx_dss_venc_hwmod
,
4464 .addr
= omap44xx_dss_venc_dma_addrs
,
4465 .user
= OCP_USER_SDMA
,
4468 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs
[] = {
4470 .pa_start
= 0x48043000,
4471 .pa_end
= 0x480430ff,
4472 .flags
= ADDR_TYPE_RT
4477 /* l4_per -> dss_venc */
4478 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc
= {
4479 .master
= &omap44xx_l4_per_hwmod
,
4480 .slave
= &omap44xx_dss_venc_hwmod
,
4482 .addr
= omap44xx_dss_venc_addrs
,
4483 .user
= OCP_USER_MPU
,
4486 static struct omap_hwmod_addr_space omap44xx_elm_addrs
[] = {
4488 .pa_start
= 0x48078000,
4489 .pa_end
= 0x48078fff,
4490 .flags
= ADDR_TYPE_RT
4496 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm
= {
4497 .master
= &omap44xx_l4_per_hwmod
,
4498 .slave
= &omap44xx_elm_hwmod
,
4500 .addr
= omap44xx_elm_addrs
,
4501 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4504 static struct omap_hwmod_addr_space omap44xx_emif1_addrs
[] = {
4506 .pa_start
= 0x4c000000,
4507 .pa_end
= 0x4c0000ff,
4508 .flags
= ADDR_TYPE_RT
4513 /* emif_fw -> emif1 */
4514 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1
= {
4515 .master
= &omap44xx_emif_fw_hwmod
,
4516 .slave
= &omap44xx_emif1_hwmod
,
4518 .addr
= omap44xx_emif1_addrs
,
4519 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4522 static struct omap_hwmod_addr_space omap44xx_emif2_addrs
[] = {
4524 .pa_start
= 0x4d000000,
4525 .pa_end
= 0x4d0000ff,
4526 .flags
= ADDR_TYPE_RT
4531 /* emif_fw -> emif2 */
4532 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2
= {
4533 .master
= &omap44xx_emif_fw_hwmod
,
4534 .slave
= &omap44xx_emif2_hwmod
,
4536 .addr
= omap44xx_emif2_addrs
,
4537 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4540 static struct omap_hwmod_addr_space omap44xx_fdif_addrs
[] = {
4542 .pa_start
= 0x4a10a000,
4543 .pa_end
= 0x4a10a1ff,
4544 .flags
= ADDR_TYPE_RT
4549 /* l4_cfg -> fdif */
4550 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif
= {
4551 .master
= &omap44xx_l4_cfg_hwmod
,
4552 .slave
= &omap44xx_fdif_hwmod
,
4554 .addr
= omap44xx_fdif_addrs
,
4555 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4558 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs
[] = {
4560 .pa_start
= 0x4a310000,
4561 .pa_end
= 0x4a3101ff,
4562 .flags
= ADDR_TYPE_RT
4567 /* l4_wkup -> gpio1 */
4568 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1
= {
4569 .master
= &omap44xx_l4_wkup_hwmod
,
4570 .slave
= &omap44xx_gpio1_hwmod
,
4571 .clk
= "l4_wkup_clk_mux_ck",
4572 .addr
= omap44xx_gpio1_addrs
,
4573 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4576 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs
[] = {
4578 .pa_start
= 0x48055000,
4579 .pa_end
= 0x480551ff,
4580 .flags
= ADDR_TYPE_RT
4585 /* l4_per -> gpio2 */
4586 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2
= {
4587 .master
= &omap44xx_l4_per_hwmod
,
4588 .slave
= &omap44xx_gpio2_hwmod
,
4590 .addr
= omap44xx_gpio2_addrs
,
4591 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4594 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs
[] = {
4596 .pa_start
= 0x48057000,
4597 .pa_end
= 0x480571ff,
4598 .flags
= ADDR_TYPE_RT
4603 /* l4_per -> gpio3 */
4604 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3
= {
4605 .master
= &omap44xx_l4_per_hwmod
,
4606 .slave
= &omap44xx_gpio3_hwmod
,
4608 .addr
= omap44xx_gpio3_addrs
,
4609 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4612 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs
[] = {
4614 .pa_start
= 0x48059000,
4615 .pa_end
= 0x480591ff,
4616 .flags
= ADDR_TYPE_RT
4621 /* l4_per -> gpio4 */
4622 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4
= {
4623 .master
= &omap44xx_l4_per_hwmod
,
4624 .slave
= &omap44xx_gpio4_hwmod
,
4626 .addr
= omap44xx_gpio4_addrs
,
4627 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4630 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs
[] = {
4632 .pa_start
= 0x4805b000,
4633 .pa_end
= 0x4805b1ff,
4634 .flags
= ADDR_TYPE_RT
4639 /* l4_per -> gpio5 */
4640 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5
= {
4641 .master
= &omap44xx_l4_per_hwmod
,
4642 .slave
= &omap44xx_gpio5_hwmod
,
4644 .addr
= omap44xx_gpio5_addrs
,
4645 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4648 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs
[] = {
4650 .pa_start
= 0x4805d000,
4651 .pa_end
= 0x4805d1ff,
4652 .flags
= ADDR_TYPE_RT
4657 /* l4_per -> gpio6 */
4658 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6
= {
4659 .master
= &omap44xx_l4_per_hwmod
,
4660 .slave
= &omap44xx_gpio6_hwmod
,
4662 .addr
= omap44xx_gpio6_addrs
,
4663 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4666 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs
[] = {
4668 .pa_start
= 0x50000000,
4669 .pa_end
= 0x500003ff,
4670 .flags
= ADDR_TYPE_RT
4675 /* l3_main_2 -> gpmc */
4676 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc
= {
4677 .master
= &omap44xx_l3_main_2_hwmod
,
4678 .slave
= &omap44xx_gpmc_hwmod
,
4680 .addr
= omap44xx_gpmc_addrs
,
4681 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4684 static struct omap_hwmod_addr_space omap44xx_gpu_addrs
[] = {
4686 .pa_start
= 0x56000000,
4687 .pa_end
= 0x5600ffff,
4688 .flags
= ADDR_TYPE_RT
4693 /* l3_main_2 -> gpu */
4694 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu
= {
4695 .master
= &omap44xx_l3_main_2_hwmod
,
4696 .slave
= &omap44xx_gpu_hwmod
,
4698 .addr
= omap44xx_gpu_addrs
,
4699 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4702 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs
[] = {
4704 .pa_start
= 0x480b2000,
4705 .pa_end
= 0x480b201f,
4706 .flags
= ADDR_TYPE_RT
4711 /* l4_per -> hdq1w */
4712 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w
= {
4713 .master
= &omap44xx_l4_per_hwmod
,
4714 .slave
= &omap44xx_hdq1w_hwmod
,
4716 .addr
= omap44xx_hdq1w_addrs
,
4717 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4720 static struct omap_hwmod_addr_space omap44xx_hsi_addrs
[] = {
4722 .pa_start
= 0x4a058000,
4723 .pa_end
= 0x4a05bfff,
4724 .flags
= ADDR_TYPE_RT
4730 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi
= {
4731 .master
= &omap44xx_l4_cfg_hwmod
,
4732 .slave
= &omap44xx_hsi_hwmod
,
4734 .addr
= omap44xx_hsi_addrs
,
4735 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4738 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs
[] = {
4740 .pa_start
= 0x48070000,
4741 .pa_end
= 0x480700ff,
4742 .flags
= ADDR_TYPE_RT
4747 /* l4_per -> i2c1 */
4748 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1
= {
4749 .master
= &omap44xx_l4_per_hwmod
,
4750 .slave
= &omap44xx_i2c1_hwmod
,
4752 .addr
= omap44xx_i2c1_addrs
,
4753 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4756 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs
[] = {
4758 .pa_start
= 0x48072000,
4759 .pa_end
= 0x480720ff,
4760 .flags
= ADDR_TYPE_RT
4765 /* l4_per -> i2c2 */
4766 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2
= {
4767 .master
= &omap44xx_l4_per_hwmod
,
4768 .slave
= &omap44xx_i2c2_hwmod
,
4770 .addr
= omap44xx_i2c2_addrs
,
4771 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4774 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs
[] = {
4776 .pa_start
= 0x48060000,
4777 .pa_end
= 0x480600ff,
4778 .flags
= ADDR_TYPE_RT
4783 /* l4_per -> i2c3 */
4784 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3
= {
4785 .master
= &omap44xx_l4_per_hwmod
,
4786 .slave
= &omap44xx_i2c3_hwmod
,
4788 .addr
= omap44xx_i2c3_addrs
,
4789 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4792 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs
[] = {
4794 .pa_start
= 0x48350000,
4795 .pa_end
= 0x483500ff,
4796 .flags
= ADDR_TYPE_RT
4801 /* l4_per -> i2c4 */
4802 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4
= {
4803 .master
= &omap44xx_l4_per_hwmod
,
4804 .slave
= &omap44xx_i2c4_hwmod
,
4806 .addr
= omap44xx_i2c4_addrs
,
4807 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4810 /* l3_main_2 -> ipu */
4811 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu
= {
4812 .master
= &omap44xx_l3_main_2_hwmod
,
4813 .slave
= &omap44xx_ipu_hwmod
,
4815 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4818 static struct omap_hwmod_addr_space omap44xx_iss_addrs
[] = {
4820 .pa_start
= 0x52000000,
4821 .pa_end
= 0x520000ff,
4822 .flags
= ADDR_TYPE_RT
4827 /* l3_main_2 -> iss */
4828 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss
= {
4829 .master
= &omap44xx_l3_main_2_hwmod
,
4830 .slave
= &omap44xx_iss_hwmod
,
4832 .addr
= omap44xx_iss_addrs
,
4833 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4837 static struct omap_hwmod_ocp_if omap44xx_iva__sl2if
= {
4838 .master
= &omap44xx_iva_hwmod
,
4839 .slave
= &omap44xx_sl2if_hwmod
,
4840 .clk
= "dpll_iva_m5x2_ck",
4841 .user
= OCP_USER_IVA
,
4844 static struct omap_hwmod_addr_space omap44xx_iva_addrs
[] = {
4846 .pa_start
= 0x5a000000,
4847 .pa_end
= 0x5a07ffff,
4848 .flags
= ADDR_TYPE_RT
4853 /* l3_main_2 -> iva */
4854 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva
= {
4855 .master
= &omap44xx_l3_main_2_hwmod
,
4856 .slave
= &omap44xx_iva_hwmod
,
4858 .addr
= omap44xx_iva_addrs
,
4859 .user
= OCP_USER_MPU
,
4862 static struct omap_hwmod_addr_space omap44xx_kbd_addrs
[] = {
4864 .pa_start
= 0x4a31c000,
4865 .pa_end
= 0x4a31c07f,
4866 .flags
= ADDR_TYPE_RT
4871 /* l4_wkup -> kbd */
4872 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd
= {
4873 .master
= &omap44xx_l4_wkup_hwmod
,
4874 .slave
= &omap44xx_kbd_hwmod
,
4875 .clk
= "l4_wkup_clk_mux_ck",
4876 .addr
= omap44xx_kbd_addrs
,
4877 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4880 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs
[] = {
4882 .pa_start
= 0x4a0f4000,
4883 .pa_end
= 0x4a0f41ff,
4884 .flags
= ADDR_TYPE_RT
4889 /* l4_cfg -> mailbox */
4890 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox
= {
4891 .master
= &omap44xx_l4_cfg_hwmod
,
4892 .slave
= &omap44xx_mailbox_hwmod
,
4894 .addr
= omap44xx_mailbox_addrs
,
4895 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4898 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs
[] = {
4900 .pa_start
= 0x40128000,
4901 .pa_end
= 0x401283ff,
4902 .flags
= ADDR_TYPE_RT
4907 /* l4_abe -> mcasp */
4908 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp
= {
4909 .master
= &omap44xx_l4_abe_hwmod
,
4910 .slave
= &omap44xx_mcasp_hwmod
,
4911 .clk
= "ocp_abe_iclk",
4912 .addr
= omap44xx_mcasp_addrs
,
4913 .user
= OCP_USER_MPU
,
4916 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs
[] = {
4918 .pa_start
= 0x49028000,
4919 .pa_end
= 0x490283ff,
4920 .flags
= ADDR_TYPE_RT
4925 /* l4_abe -> mcasp (dma) */
4926 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma
= {
4927 .master
= &omap44xx_l4_abe_hwmod
,
4928 .slave
= &omap44xx_mcasp_hwmod
,
4929 .clk
= "ocp_abe_iclk",
4930 .addr
= omap44xx_mcasp_dma_addrs
,
4931 .user
= OCP_USER_SDMA
,
4934 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs
[] = {
4937 .pa_start
= 0x40122000,
4938 .pa_end
= 0x401220ff,
4939 .flags
= ADDR_TYPE_RT
4944 /* l4_abe -> mcbsp1 */
4945 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1
= {
4946 .master
= &omap44xx_l4_abe_hwmod
,
4947 .slave
= &omap44xx_mcbsp1_hwmod
,
4948 .clk
= "ocp_abe_iclk",
4949 .addr
= omap44xx_mcbsp1_addrs
,
4950 .user
= OCP_USER_MPU
,
4953 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs
[] = {
4956 .pa_start
= 0x49022000,
4957 .pa_end
= 0x490220ff,
4958 .flags
= ADDR_TYPE_RT
4963 /* l4_abe -> mcbsp1 (dma) */
4964 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma
= {
4965 .master
= &omap44xx_l4_abe_hwmod
,
4966 .slave
= &omap44xx_mcbsp1_hwmod
,
4967 .clk
= "ocp_abe_iclk",
4968 .addr
= omap44xx_mcbsp1_dma_addrs
,
4969 .user
= OCP_USER_SDMA
,
4972 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs
[] = {
4975 .pa_start
= 0x40124000,
4976 .pa_end
= 0x401240ff,
4977 .flags
= ADDR_TYPE_RT
4982 /* l4_abe -> mcbsp2 */
4983 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2
= {
4984 .master
= &omap44xx_l4_abe_hwmod
,
4985 .slave
= &omap44xx_mcbsp2_hwmod
,
4986 .clk
= "ocp_abe_iclk",
4987 .addr
= omap44xx_mcbsp2_addrs
,
4988 .user
= OCP_USER_MPU
,
4991 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs
[] = {
4994 .pa_start
= 0x49024000,
4995 .pa_end
= 0x490240ff,
4996 .flags
= ADDR_TYPE_RT
5001 /* l4_abe -> mcbsp2 (dma) */
5002 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma
= {
5003 .master
= &omap44xx_l4_abe_hwmod
,
5004 .slave
= &omap44xx_mcbsp2_hwmod
,
5005 .clk
= "ocp_abe_iclk",
5006 .addr
= omap44xx_mcbsp2_dma_addrs
,
5007 .user
= OCP_USER_SDMA
,
5010 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs
[] = {
5013 .pa_start
= 0x40126000,
5014 .pa_end
= 0x401260ff,
5015 .flags
= ADDR_TYPE_RT
5020 /* l4_abe -> mcbsp3 */
5021 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3
= {
5022 .master
= &omap44xx_l4_abe_hwmod
,
5023 .slave
= &omap44xx_mcbsp3_hwmod
,
5024 .clk
= "ocp_abe_iclk",
5025 .addr
= omap44xx_mcbsp3_addrs
,
5026 .user
= OCP_USER_MPU
,
5029 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs
[] = {
5032 .pa_start
= 0x49026000,
5033 .pa_end
= 0x490260ff,
5034 .flags
= ADDR_TYPE_RT
5039 /* l4_abe -> mcbsp3 (dma) */
5040 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma
= {
5041 .master
= &omap44xx_l4_abe_hwmod
,
5042 .slave
= &omap44xx_mcbsp3_hwmod
,
5043 .clk
= "ocp_abe_iclk",
5044 .addr
= omap44xx_mcbsp3_dma_addrs
,
5045 .user
= OCP_USER_SDMA
,
5048 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs
[] = {
5050 .pa_start
= 0x48096000,
5051 .pa_end
= 0x480960ff,
5052 .flags
= ADDR_TYPE_RT
5057 /* l4_per -> mcbsp4 */
5058 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4
= {
5059 .master
= &omap44xx_l4_per_hwmod
,
5060 .slave
= &omap44xx_mcbsp4_hwmod
,
5062 .addr
= omap44xx_mcbsp4_addrs
,
5063 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5066 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs
[] = {
5068 .pa_start
= 0x40132000,
5069 .pa_end
= 0x4013207f,
5070 .flags
= ADDR_TYPE_RT
5075 /* l4_abe -> mcpdm */
5076 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm
= {
5077 .master
= &omap44xx_l4_abe_hwmod
,
5078 .slave
= &omap44xx_mcpdm_hwmod
,
5079 .clk
= "ocp_abe_iclk",
5080 .addr
= omap44xx_mcpdm_addrs
,
5081 .user
= OCP_USER_MPU
,
5084 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs
[] = {
5086 .pa_start
= 0x49032000,
5087 .pa_end
= 0x4903207f,
5088 .flags
= ADDR_TYPE_RT
5093 /* l4_abe -> mcpdm (dma) */
5094 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma
= {
5095 .master
= &omap44xx_l4_abe_hwmod
,
5096 .slave
= &omap44xx_mcpdm_hwmod
,
5097 .clk
= "ocp_abe_iclk",
5098 .addr
= omap44xx_mcpdm_dma_addrs
,
5099 .user
= OCP_USER_SDMA
,
5102 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs
[] = {
5104 .pa_start
= 0x48098000,
5105 .pa_end
= 0x480981ff,
5106 .flags
= ADDR_TYPE_RT
5111 /* l4_per -> mcspi1 */
5112 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1
= {
5113 .master
= &omap44xx_l4_per_hwmod
,
5114 .slave
= &omap44xx_mcspi1_hwmod
,
5116 .addr
= omap44xx_mcspi1_addrs
,
5117 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5120 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs
[] = {
5122 .pa_start
= 0x4809a000,
5123 .pa_end
= 0x4809a1ff,
5124 .flags
= ADDR_TYPE_RT
5129 /* l4_per -> mcspi2 */
5130 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2
= {
5131 .master
= &omap44xx_l4_per_hwmod
,
5132 .slave
= &omap44xx_mcspi2_hwmod
,
5134 .addr
= omap44xx_mcspi2_addrs
,
5135 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5138 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs
[] = {
5140 .pa_start
= 0x480b8000,
5141 .pa_end
= 0x480b81ff,
5142 .flags
= ADDR_TYPE_RT
5147 /* l4_per -> mcspi3 */
5148 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3
= {
5149 .master
= &omap44xx_l4_per_hwmod
,
5150 .slave
= &omap44xx_mcspi3_hwmod
,
5152 .addr
= omap44xx_mcspi3_addrs
,
5153 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5156 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs
[] = {
5158 .pa_start
= 0x480ba000,
5159 .pa_end
= 0x480ba1ff,
5160 .flags
= ADDR_TYPE_RT
5165 /* l4_per -> mcspi4 */
5166 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4
= {
5167 .master
= &omap44xx_l4_per_hwmod
,
5168 .slave
= &omap44xx_mcspi4_hwmod
,
5170 .addr
= omap44xx_mcspi4_addrs
,
5171 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5174 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs
[] = {
5176 .pa_start
= 0x4809c000,
5177 .pa_end
= 0x4809c3ff,
5178 .flags
= ADDR_TYPE_RT
5183 /* l4_per -> mmc1 */
5184 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1
= {
5185 .master
= &omap44xx_l4_per_hwmod
,
5186 .slave
= &omap44xx_mmc1_hwmod
,
5188 .addr
= omap44xx_mmc1_addrs
,
5189 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5192 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs
[] = {
5194 .pa_start
= 0x480b4000,
5195 .pa_end
= 0x480b43ff,
5196 .flags
= ADDR_TYPE_RT
5201 /* l4_per -> mmc2 */
5202 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2
= {
5203 .master
= &omap44xx_l4_per_hwmod
,
5204 .slave
= &omap44xx_mmc2_hwmod
,
5206 .addr
= omap44xx_mmc2_addrs
,
5207 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5210 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs
[] = {
5212 .pa_start
= 0x480ad000,
5213 .pa_end
= 0x480ad3ff,
5214 .flags
= ADDR_TYPE_RT
5219 /* l4_per -> mmc3 */
5220 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3
= {
5221 .master
= &omap44xx_l4_per_hwmod
,
5222 .slave
= &omap44xx_mmc3_hwmod
,
5224 .addr
= omap44xx_mmc3_addrs
,
5225 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5228 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs
[] = {
5230 .pa_start
= 0x480d1000,
5231 .pa_end
= 0x480d13ff,
5232 .flags
= ADDR_TYPE_RT
5237 /* l4_per -> mmc4 */
5238 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4
= {
5239 .master
= &omap44xx_l4_per_hwmod
,
5240 .slave
= &omap44xx_mmc4_hwmod
,
5242 .addr
= omap44xx_mmc4_addrs
,
5243 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5246 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs
[] = {
5248 .pa_start
= 0x480d5000,
5249 .pa_end
= 0x480d53ff,
5250 .flags
= ADDR_TYPE_RT
5255 /* l4_per -> mmc5 */
5256 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5
= {
5257 .master
= &omap44xx_l4_per_hwmod
,
5258 .slave
= &omap44xx_mmc5_hwmod
,
5260 .addr
= omap44xx_mmc5_addrs
,
5261 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5264 /* l3_main_2 -> ocmc_ram */
5265 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram
= {
5266 .master
= &omap44xx_l3_main_2_hwmod
,
5267 .slave
= &omap44xx_ocmc_ram_hwmod
,
5269 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5272 /* l4_cfg -> ocp2scp_usb_phy */
5273 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy
= {
5274 .master
= &omap44xx_l4_cfg_hwmod
,
5275 .slave
= &omap44xx_ocp2scp_usb_phy_hwmod
,
5277 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5280 static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs
[] = {
5282 .pa_start
= 0x48243000,
5283 .pa_end
= 0x48243fff,
5284 .flags
= ADDR_TYPE_RT
5289 /* mpu_private -> prcm_mpu */
5290 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu
= {
5291 .master
= &omap44xx_mpu_private_hwmod
,
5292 .slave
= &omap44xx_prcm_mpu_hwmod
,
5294 .addr
= omap44xx_prcm_mpu_addrs
,
5295 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5298 static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs
[] = {
5300 .pa_start
= 0x4a004000,
5301 .pa_end
= 0x4a004fff,
5302 .flags
= ADDR_TYPE_RT
5307 /* l4_wkup -> cm_core_aon */
5308 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon
= {
5309 .master
= &omap44xx_l4_wkup_hwmod
,
5310 .slave
= &omap44xx_cm_core_aon_hwmod
,
5311 .clk
= "l4_wkup_clk_mux_ck",
5312 .addr
= omap44xx_cm_core_aon_addrs
,
5313 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5316 static struct omap_hwmod_addr_space omap44xx_cm_core_addrs
[] = {
5318 .pa_start
= 0x4a008000,
5319 .pa_end
= 0x4a009fff,
5320 .flags
= ADDR_TYPE_RT
5325 /* l4_cfg -> cm_core */
5326 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core
= {
5327 .master
= &omap44xx_l4_cfg_hwmod
,
5328 .slave
= &omap44xx_cm_core_hwmod
,
5330 .addr
= omap44xx_cm_core_addrs
,
5331 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5334 static struct omap_hwmod_addr_space omap44xx_prm_addrs
[] = {
5336 .pa_start
= 0x4a306000,
5337 .pa_end
= 0x4a307fff,
5338 .flags
= ADDR_TYPE_RT
5343 /* l4_wkup -> prm */
5344 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm
= {
5345 .master
= &omap44xx_l4_wkup_hwmod
,
5346 .slave
= &omap44xx_prm_hwmod
,
5347 .clk
= "l4_wkup_clk_mux_ck",
5348 .addr
= omap44xx_prm_addrs
,
5349 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5352 static struct omap_hwmod_addr_space omap44xx_scrm_addrs
[] = {
5354 .pa_start
= 0x4a30a000,
5355 .pa_end
= 0x4a30a7ff,
5356 .flags
= ADDR_TYPE_RT
5361 /* l4_wkup -> scrm */
5362 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm
= {
5363 .master
= &omap44xx_l4_wkup_hwmod
,
5364 .slave
= &omap44xx_scrm_hwmod
,
5365 .clk
= "l4_wkup_clk_mux_ck",
5366 .addr
= omap44xx_scrm_addrs
,
5367 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5370 /* l3_main_2 -> sl2if */
5371 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sl2if
= {
5372 .master
= &omap44xx_l3_main_2_hwmod
,
5373 .slave
= &omap44xx_sl2if_hwmod
,
5375 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5378 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs
[] = {
5380 .pa_start
= 0x4012c000,
5381 .pa_end
= 0x4012c3ff,
5382 .flags
= ADDR_TYPE_RT
5387 /* l4_abe -> slimbus1 */
5388 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1
= {
5389 .master
= &omap44xx_l4_abe_hwmod
,
5390 .slave
= &omap44xx_slimbus1_hwmod
,
5391 .clk
= "ocp_abe_iclk",
5392 .addr
= omap44xx_slimbus1_addrs
,
5393 .user
= OCP_USER_MPU
,
5396 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs
[] = {
5398 .pa_start
= 0x4902c000,
5399 .pa_end
= 0x4902c3ff,
5400 .flags
= ADDR_TYPE_RT
5405 /* l4_abe -> slimbus1 (dma) */
5406 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma
= {
5407 .master
= &omap44xx_l4_abe_hwmod
,
5408 .slave
= &omap44xx_slimbus1_hwmod
,
5409 .clk
= "ocp_abe_iclk",
5410 .addr
= omap44xx_slimbus1_dma_addrs
,
5411 .user
= OCP_USER_SDMA
,
5414 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs
[] = {
5416 .pa_start
= 0x48076000,
5417 .pa_end
= 0x480763ff,
5418 .flags
= ADDR_TYPE_RT
5423 /* l4_per -> slimbus2 */
5424 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2
= {
5425 .master
= &omap44xx_l4_per_hwmod
,
5426 .slave
= &omap44xx_slimbus2_hwmod
,
5428 .addr
= omap44xx_slimbus2_addrs
,
5429 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5432 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs
[] = {
5434 .pa_start
= 0x4a0dd000,
5435 .pa_end
= 0x4a0dd03f,
5436 .flags
= ADDR_TYPE_RT
5441 /* l4_cfg -> smartreflex_core */
5442 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core
= {
5443 .master
= &omap44xx_l4_cfg_hwmod
,
5444 .slave
= &omap44xx_smartreflex_core_hwmod
,
5446 .addr
= omap44xx_smartreflex_core_addrs
,
5447 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5450 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs
[] = {
5452 .pa_start
= 0x4a0db000,
5453 .pa_end
= 0x4a0db03f,
5454 .flags
= ADDR_TYPE_RT
5459 /* l4_cfg -> smartreflex_iva */
5460 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva
= {
5461 .master
= &omap44xx_l4_cfg_hwmod
,
5462 .slave
= &omap44xx_smartreflex_iva_hwmod
,
5464 .addr
= omap44xx_smartreflex_iva_addrs
,
5465 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5468 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs
[] = {
5470 .pa_start
= 0x4a0d9000,
5471 .pa_end
= 0x4a0d903f,
5472 .flags
= ADDR_TYPE_RT
5477 /* l4_cfg -> smartreflex_mpu */
5478 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu
= {
5479 .master
= &omap44xx_l4_cfg_hwmod
,
5480 .slave
= &omap44xx_smartreflex_mpu_hwmod
,
5482 .addr
= omap44xx_smartreflex_mpu_addrs
,
5483 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5486 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs
[] = {
5488 .pa_start
= 0x4a0f6000,
5489 .pa_end
= 0x4a0f6fff,
5490 .flags
= ADDR_TYPE_RT
5495 /* l4_cfg -> spinlock */
5496 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock
= {
5497 .master
= &omap44xx_l4_cfg_hwmod
,
5498 .slave
= &omap44xx_spinlock_hwmod
,
5500 .addr
= omap44xx_spinlock_addrs
,
5501 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5504 static struct omap_hwmod_addr_space omap44xx_timer1_addrs
[] = {
5506 .pa_start
= 0x4a318000,
5507 .pa_end
= 0x4a31807f,
5508 .flags
= ADDR_TYPE_RT
5513 /* l4_wkup -> timer1 */
5514 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1
= {
5515 .master
= &omap44xx_l4_wkup_hwmod
,
5516 .slave
= &omap44xx_timer1_hwmod
,
5517 .clk
= "l4_wkup_clk_mux_ck",
5518 .addr
= omap44xx_timer1_addrs
,
5519 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5522 static struct omap_hwmod_addr_space omap44xx_timer2_addrs
[] = {
5524 .pa_start
= 0x48032000,
5525 .pa_end
= 0x4803207f,
5526 .flags
= ADDR_TYPE_RT
5531 /* l4_per -> timer2 */
5532 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2
= {
5533 .master
= &omap44xx_l4_per_hwmod
,
5534 .slave
= &omap44xx_timer2_hwmod
,
5536 .addr
= omap44xx_timer2_addrs
,
5537 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5540 static struct omap_hwmod_addr_space omap44xx_timer3_addrs
[] = {
5542 .pa_start
= 0x48034000,
5543 .pa_end
= 0x4803407f,
5544 .flags
= ADDR_TYPE_RT
5549 /* l4_per -> timer3 */
5550 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3
= {
5551 .master
= &omap44xx_l4_per_hwmod
,
5552 .slave
= &omap44xx_timer3_hwmod
,
5554 .addr
= omap44xx_timer3_addrs
,
5555 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5558 static struct omap_hwmod_addr_space omap44xx_timer4_addrs
[] = {
5560 .pa_start
= 0x48036000,
5561 .pa_end
= 0x4803607f,
5562 .flags
= ADDR_TYPE_RT
5567 /* l4_per -> timer4 */
5568 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4
= {
5569 .master
= &omap44xx_l4_per_hwmod
,
5570 .slave
= &omap44xx_timer4_hwmod
,
5572 .addr
= omap44xx_timer4_addrs
,
5573 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5576 static struct omap_hwmod_addr_space omap44xx_timer5_addrs
[] = {
5578 .pa_start
= 0x40138000,
5579 .pa_end
= 0x4013807f,
5580 .flags
= ADDR_TYPE_RT
5585 /* l4_abe -> timer5 */
5586 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5
= {
5587 .master
= &omap44xx_l4_abe_hwmod
,
5588 .slave
= &omap44xx_timer5_hwmod
,
5589 .clk
= "ocp_abe_iclk",
5590 .addr
= omap44xx_timer5_addrs
,
5591 .user
= OCP_USER_MPU
,
5594 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs
[] = {
5596 .pa_start
= 0x49038000,
5597 .pa_end
= 0x4903807f,
5598 .flags
= ADDR_TYPE_RT
5603 /* l4_abe -> timer5 (dma) */
5604 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma
= {
5605 .master
= &omap44xx_l4_abe_hwmod
,
5606 .slave
= &omap44xx_timer5_hwmod
,
5607 .clk
= "ocp_abe_iclk",
5608 .addr
= omap44xx_timer5_dma_addrs
,
5609 .user
= OCP_USER_SDMA
,
5612 static struct omap_hwmod_addr_space omap44xx_timer6_addrs
[] = {
5614 .pa_start
= 0x4013a000,
5615 .pa_end
= 0x4013a07f,
5616 .flags
= ADDR_TYPE_RT
5621 /* l4_abe -> timer6 */
5622 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6
= {
5623 .master
= &omap44xx_l4_abe_hwmod
,
5624 .slave
= &omap44xx_timer6_hwmod
,
5625 .clk
= "ocp_abe_iclk",
5626 .addr
= omap44xx_timer6_addrs
,
5627 .user
= OCP_USER_MPU
,
5630 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs
[] = {
5632 .pa_start
= 0x4903a000,
5633 .pa_end
= 0x4903a07f,
5634 .flags
= ADDR_TYPE_RT
5639 /* l4_abe -> timer6 (dma) */
5640 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma
= {
5641 .master
= &omap44xx_l4_abe_hwmod
,
5642 .slave
= &omap44xx_timer6_hwmod
,
5643 .clk
= "ocp_abe_iclk",
5644 .addr
= omap44xx_timer6_dma_addrs
,
5645 .user
= OCP_USER_SDMA
,
5648 static struct omap_hwmod_addr_space omap44xx_timer7_addrs
[] = {
5650 .pa_start
= 0x4013c000,
5651 .pa_end
= 0x4013c07f,
5652 .flags
= ADDR_TYPE_RT
5657 /* l4_abe -> timer7 */
5658 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7
= {
5659 .master
= &omap44xx_l4_abe_hwmod
,
5660 .slave
= &omap44xx_timer7_hwmod
,
5661 .clk
= "ocp_abe_iclk",
5662 .addr
= omap44xx_timer7_addrs
,
5663 .user
= OCP_USER_MPU
,
5666 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs
[] = {
5668 .pa_start
= 0x4903c000,
5669 .pa_end
= 0x4903c07f,
5670 .flags
= ADDR_TYPE_RT
5675 /* l4_abe -> timer7 (dma) */
5676 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma
= {
5677 .master
= &omap44xx_l4_abe_hwmod
,
5678 .slave
= &omap44xx_timer7_hwmod
,
5679 .clk
= "ocp_abe_iclk",
5680 .addr
= omap44xx_timer7_dma_addrs
,
5681 .user
= OCP_USER_SDMA
,
5684 static struct omap_hwmod_addr_space omap44xx_timer8_addrs
[] = {
5686 .pa_start
= 0x4013e000,
5687 .pa_end
= 0x4013e07f,
5688 .flags
= ADDR_TYPE_RT
5693 /* l4_abe -> timer8 */
5694 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8
= {
5695 .master
= &omap44xx_l4_abe_hwmod
,
5696 .slave
= &omap44xx_timer8_hwmod
,
5697 .clk
= "ocp_abe_iclk",
5698 .addr
= omap44xx_timer8_addrs
,
5699 .user
= OCP_USER_MPU
,
5702 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs
[] = {
5704 .pa_start
= 0x4903e000,
5705 .pa_end
= 0x4903e07f,
5706 .flags
= ADDR_TYPE_RT
5711 /* l4_abe -> timer8 (dma) */
5712 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma
= {
5713 .master
= &omap44xx_l4_abe_hwmod
,
5714 .slave
= &omap44xx_timer8_hwmod
,
5715 .clk
= "ocp_abe_iclk",
5716 .addr
= omap44xx_timer8_dma_addrs
,
5717 .user
= OCP_USER_SDMA
,
5720 static struct omap_hwmod_addr_space omap44xx_timer9_addrs
[] = {
5722 .pa_start
= 0x4803e000,
5723 .pa_end
= 0x4803e07f,
5724 .flags
= ADDR_TYPE_RT
5729 /* l4_per -> timer9 */
5730 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9
= {
5731 .master
= &omap44xx_l4_per_hwmod
,
5732 .slave
= &omap44xx_timer9_hwmod
,
5734 .addr
= omap44xx_timer9_addrs
,
5735 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5738 static struct omap_hwmod_addr_space omap44xx_timer10_addrs
[] = {
5740 .pa_start
= 0x48086000,
5741 .pa_end
= 0x4808607f,
5742 .flags
= ADDR_TYPE_RT
5747 /* l4_per -> timer10 */
5748 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10
= {
5749 .master
= &omap44xx_l4_per_hwmod
,
5750 .slave
= &omap44xx_timer10_hwmod
,
5752 .addr
= omap44xx_timer10_addrs
,
5753 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5756 static struct omap_hwmod_addr_space omap44xx_timer11_addrs
[] = {
5758 .pa_start
= 0x48088000,
5759 .pa_end
= 0x4808807f,
5760 .flags
= ADDR_TYPE_RT
5765 /* l4_per -> timer11 */
5766 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11
= {
5767 .master
= &omap44xx_l4_per_hwmod
,
5768 .slave
= &omap44xx_timer11_hwmod
,
5770 .addr
= omap44xx_timer11_addrs
,
5771 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5774 static struct omap_hwmod_addr_space omap44xx_uart1_addrs
[] = {
5776 .pa_start
= 0x4806a000,
5777 .pa_end
= 0x4806a0ff,
5778 .flags
= ADDR_TYPE_RT
5783 /* l4_per -> uart1 */
5784 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1
= {
5785 .master
= &omap44xx_l4_per_hwmod
,
5786 .slave
= &omap44xx_uart1_hwmod
,
5788 .addr
= omap44xx_uart1_addrs
,
5789 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5792 static struct omap_hwmod_addr_space omap44xx_uart2_addrs
[] = {
5794 .pa_start
= 0x4806c000,
5795 .pa_end
= 0x4806c0ff,
5796 .flags
= ADDR_TYPE_RT
5801 /* l4_per -> uart2 */
5802 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2
= {
5803 .master
= &omap44xx_l4_per_hwmod
,
5804 .slave
= &omap44xx_uart2_hwmod
,
5806 .addr
= omap44xx_uart2_addrs
,
5807 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5810 static struct omap_hwmod_addr_space omap44xx_uart3_addrs
[] = {
5812 .pa_start
= 0x48020000,
5813 .pa_end
= 0x480200ff,
5814 .flags
= ADDR_TYPE_RT
5819 /* l4_per -> uart3 */
5820 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3
= {
5821 .master
= &omap44xx_l4_per_hwmod
,
5822 .slave
= &omap44xx_uart3_hwmod
,
5824 .addr
= omap44xx_uart3_addrs
,
5825 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5828 static struct omap_hwmod_addr_space omap44xx_uart4_addrs
[] = {
5830 .pa_start
= 0x4806e000,
5831 .pa_end
= 0x4806e0ff,
5832 .flags
= ADDR_TYPE_RT
5837 /* l4_per -> uart4 */
5838 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4
= {
5839 .master
= &omap44xx_l4_per_hwmod
,
5840 .slave
= &omap44xx_uart4_hwmod
,
5842 .addr
= omap44xx_uart4_addrs
,
5843 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5846 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs
[] = {
5848 .pa_start
= 0x4a0a9000,
5849 .pa_end
= 0x4a0a93ff,
5850 .flags
= ADDR_TYPE_RT
5855 /* l4_cfg -> usb_host_fs */
5856 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_fs
= {
5857 .master
= &omap44xx_l4_cfg_hwmod
,
5858 .slave
= &omap44xx_usb_host_fs_hwmod
,
5860 .addr
= omap44xx_usb_host_fs_addrs
,
5861 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5864 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs
[] = {
5867 .pa_start
= 0x4a064000,
5868 .pa_end
= 0x4a0647ff,
5869 .flags
= ADDR_TYPE_RT
5873 .pa_start
= 0x4a064800,
5874 .pa_end
= 0x4a064bff,
5878 .pa_start
= 0x4a064c00,
5879 .pa_end
= 0x4a064fff,
5884 /* l4_cfg -> usb_host_hs */
5885 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs
= {
5886 .master
= &omap44xx_l4_cfg_hwmod
,
5887 .slave
= &omap44xx_usb_host_hs_hwmod
,
5889 .addr
= omap44xx_usb_host_hs_addrs
,
5890 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5893 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs
[] = {
5895 .pa_start
= 0x4a0ab000,
5896 .pa_end
= 0x4a0ab003,
5897 .flags
= ADDR_TYPE_RT
5902 /* l4_cfg -> usb_otg_hs */
5903 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs
= {
5904 .master
= &omap44xx_l4_cfg_hwmod
,
5905 .slave
= &omap44xx_usb_otg_hs_hwmod
,
5907 .addr
= omap44xx_usb_otg_hs_addrs
,
5908 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5911 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs
[] = {
5914 .pa_start
= 0x4a062000,
5915 .pa_end
= 0x4a063fff,
5916 .flags
= ADDR_TYPE_RT
5921 /* l4_cfg -> usb_tll_hs */
5922 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs
= {
5923 .master
= &omap44xx_l4_cfg_hwmod
,
5924 .slave
= &omap44xx_usb_tll_hs_hwmod
,
5926 .addr
= omap44xx_usb_tll_hs_addrs
,
5927 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5930 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs
[] = {
5932 .pa_start
= 0x4a314000,
5933 .pa_end
= 0x4a31407f,
5934 .flags
= ADDR_TYPE_RT
5939 /* l4_wkup -> wd_timer2 */
5940 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2
= {
5941 .master
= &omap44xx_l4_wkup_hwmod
,
5942 .slave
= &omap44xx_wd_timer2_hwmod
,
5943 .clk
= "l4_wkup_clk_mux_ck",
5944 .addr
= omap44xx_wd_timer2_addrs
,
5945 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5948 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs
[] = {
5950 .pa_start
= 0x40130000,
5951 .pa_end
= 0x4013007f,
5952 .flags
= ADDR_TYPE_RT
5957 /* l4_abe -> wd_timer3 */
5958 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3
= {
5959 .master
= &omap44xx_l4_abe_hwmod
,
5960 .slave
= &omap44xx_wd_timer3_hwmod
,
5961 .clk
= "ocp_abe_iclk",
5962 .addr
= omap44xx_wd_timer3_addrs
,
5963 .user
= OCP_USER_MPU
,
5966 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs
[] = {
5968 .pa_start
= 0x49030000,
5969 .pa_end
= 0x4903007f,
5970 .flags
= ADDR_TYPE_RT
5975 /* l4_abe -> wd_timer3 (dma) */
5976 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma
= {
5977 .master
= &omap44xx_l4_abe_hwmod
,
5978 .slave
= &omap44xx_wd_timer3_hwmod
,
5979 .clk
= "ocp_abe_iclk",
5980 .addr
= omap44xx_wd_timer3_dma_addrs
,
5981 .user
= OCP_USER_SDMA
,
5984 static struct omap_hwmod_ocp_if
*omap44xx_hwmod_ocp_ifs
[] __initdata
= {
5985 &omap44xx_c2c__c2c_target_fw
,
5986 &omap44xx_l4_cfg__c2c_target_fw
,
5987 &omap44xx_l3_main_1__dmm
,
5989 &omap44xx_c2c__emif_fw
,
5990 &omap44xx_dmm__emif_fw
,
5991 &omap44xx_l4_cfg__emif_fw
,
5992 &omap44xx_iva__l3_instr
,
5993 &omap44xx_l3_main_3__l3_instr
,
5994 &omap44xx_ocp_wp_noc__l3_instr
,
5995 &omap44xx_dsp__l3_main_1
,
5996 &omap44xx_dss__l3_main_1
,
5997 &omap44xx_l3_main_2__l3_main_1
,
5998 &omap44xx_l4_cfg__l3_main_1
,
5999 &omap44xx_mmc1__l3_main_1
,
6000 &omap44xx_mmc2__l3_main_1
,
6001 &omap44xx_mpu__l3_main_1
,
6002 &omap44xx_c2c_target_fw__l3_main_2
,
6003 &omap44xx_debugss__l3_main_2
,
6004 &omap44xx_dma_system__l3_main_2
,
6005 &omap44xx_fdif__l3_main_2
,
6006 &omap44xx_gpu__l3_main_2
,
6007 &omap44xx_hsi__l3_main_2
,
6008 &omap44xx_ipu__l3_main_2
,
6009 &omap44xx_iss__l3_main_2
,
6010 &omap44xx_iva__l3_main_2
,
6011 &omap44xx_l3_main_1__l3_main_2
,
6012 &omap44xx_l4_cfg__l3_main_2
,
6013 &omap44xx_usb_host_fs__l3_main_2
,
6014 &omap44xx_usb_host_hs__l3_main_2
,
6015 &omap44xx_usb_otg_hs__l3_main_2
,
6016 &omap44xx_l3_main_1__l3_main_3
,
6017 &omap44xx_l3_main_2__l3_main_3
,
6018 &omap44xx_l4_cfg__l3_main_3
,
6019 &omap44xx_aess__l4_abe
,
6020 &omap44xx_dsp__l4_abe
,
6021 &omap44xx_l3_main_1__l4_abe
,
6022 &omap44xx_mpu__l4_abe
,
6023 &omap44xx_l3_main_1__l4_cfg
,
6024 &omap44xx_l3_main_2__l4_per
,
6025 &omap44xx_l4_cfg__l4_wkup
,
6026 &omap44xx_mpu__mpu_private
,
6027 &omap44xx_l4_cfg__ocp_wp_noc
,
6028 &omap44xx_l4_abe__aess
,
6029 &omap44xx_l4_abe__aess_dma
,
6030 &omap44xx_l3_main_2__c2c
,
6031 &omap44xx_l4_wkup__counter_32k
,
6032 &omap44xx_l4_cfg__ctrl_module_core
,
6033 &omap44xx_l4_cfg__ctrl_module_pad_core
,
6034 &omap44xx_l4_wkup__ctrl_module_wkup
,
6035 &omap44xx_l4_wkup__ctrl_module_pad_wkup
,
6036 &omap44xx_l3_instr__debugss
,
6037 &omap44xx_l4_cfg__dma_system
,
6038 &omap44xx_l4_abe__dmic
,
6039 &omap44xx_l4_abe__dmic_dma
,
6041 &omap44xx_dsp__sl2if
,
6042 &omap44xx_l4_cfg__dsp
,
6043 &omap44xx_l3_main_2__dss
,
6044 &omap44xx_l4_per__dss
,
6045 &omap44xx_l3_main_2__dss_dispc
,
6046 &omap44xx_l4_per__dss_dispc
,
6047 &omap44xx_l3_main_2__dss_dsi1
,
6048 &omap44xx_l4_per__dss_dsi1
,
6049 &omap44xx_l3_main_2__dss_dsi2
,
6050 &omap44xx_l4_per__dss_dsi2
,
6051 &omap44xx_l3_main_2__dss_hdmi
,
6052 &omap44xx_l4_per__dss_hdmi
,
6053 &omap44xx_l3_main_2__dss_rfbi
,
6054 &omap44xx_l4_per__dss_rfbi
,
6055 &omap44xx_l3_main_2__dss_venc
,
6056 &omap44xx_l4_per__dss_venc
,
6057 &omap44xx_l4_per__elm
,
6058 &omap44xx_emif_fw__emif1
,
6059 &omap44xx_emif_fw__emif2
,
6060 &omap44xx_l4_cfg__fdif
,
6061 &omap44xx_l4_wkup__gpio1
,
6062 &omap44xx_l4_per__gpio2
,
6063 &omap44xx_l4_per__gpio3
,
6064 &omap44xx_l4_per__gpio4
,
6065 &omap44xx_l4_per__gpio5
,
6066 &omap44xx_l4_per__gpio6
,
6067 &omap44xx_l3_main_2__gpmc
,
6068 &omap44xx_l3_main_2__gpu
,
6069 &omap44xx_l4_per__hdq1w
,
6070 &omap44xx_l4_cfg__hsi
,
6071 &omap44xx_l4_per__i2c1
,
6072 &omap44xx_l4_per__i2c2
,
6073 &omap44xx_l4_per__i2c3
,
6074 &omap44xx_l4_per__i2c4
,
6075 &omap44xx_l3_main_2__ipu
,
6076 &omap44xx_l3_main_2__iss
,
6077 &omap44xx_iva__sl2if
,
6078 &omap44xx_l3_main_2__iva
,
6079 &omap44xx_l4_wkup__kbd
,
6080 &omap44xx_l4_cfg__mailbox
,
6081 &omap44xx_l4_abe__mcasp
,
6082 &omap44xx_l4_abe__mcasp_dma
,
6083 &omap44xx_l4_abe__mcbsp1
,
6084 &omap44xx_l4_abe__mcbsp1_dma
,
6085 &omap44xx_l4_abe__mcbsp2
,
6086 &omap44xx_l4_abe__mcbsp2_dma
,
6087 &omap44xx_l4_abe__mcbsp3
,
6088 &omap44xx_l4_abe__mcbsp3_dma
,
6089 &omap44xx_l4_per__mcbsp4
,
6090 &omap44xx_l4_abe__mcpdm
,
6091 &omap44xx_l4_abe__mcpdm_dma
,
6092 &omap44xx_l4_per__mcspi1
,
6093 &omap44xx_l4_per__mcspi2
,
6094 &omap44xx_l4_per__mcspi3
,
6095 &omap44xx_l4_per__mcspi4
,
6096 &omap44xx_l4_per__mmc1
,
6097 &omap44xx_l4_per__mmc2
,
6098 &omap44xx_l4_per__mmc3
,
6099 &omap44xx_l4_per__mmc4
,
6100 &omap44xx_l4_per__mmc5
,
6101 &omap44xx_l3_main_2__ocmc_ram
,
6102 &omap44xx_l4_cfg__ocp2scp_usb_phy
,
6103 &omap44xx_mpu_private__prcm_mpu
,
6104 &omap44xx_l4_wkup__cm_core_aon
,
6105 &omap44xx_l4_cfg__cm_core
,
6106 &omap44xx_l4_wkup__prm
,
6107 &omap44xx_l4_wkup__scrm
,
6108 &omap44xx_l3_main_2__sl2if
,
6109 &omap44xx_l4_abe__slimbus1
,
6110 &omap44xx_l4_abe__slimbus1_dma
,
6111 &omap44xx_l4_per__slimbus2
,
6112 &omap44xx_l4_cfg__smartreflex_core
,
6113 &omap44xx_l4_cfg__smartreflex_iva
,
6114 &omap44xx_l4_cfg__smartreflex_mpu
,
6115 &omap44xx_l4_cfg__spinlock
,
6116 &omap44xx_l4_wkup__timer1
,
6117 &omap44xx_l4_per__timer2
,
6118 &omap44xx_l4_per__timer3
,
6119 &omap44xx_l4_per__timer4
,
6120 &omap44xx_l4_abe__timer5
,
6121 &omap44xx_l4_abe__timer5_dma
,
6122 &omap44xx_l4_abe__timer6
,
6123 &omap44xx_l4_abe__timer6_dma
,
6124 &omap44xx_l4_abe__timer7
,
6125 &omap44xx_l4_abe__timer7_dma
,
6126 &omap44xx_l4_abe__timer8
,
6127 &omap44xx_l4_abe__timer8_dma
,
6128 &omap44xx_l4_per__timer9
,
6129 &omap44xx_l4_per__timer10
,
6130 &omap44xx_l4_per__timer11
,
6131 &omap44xx_l4_per__uart1
,
6132 &omap44xx_l4_per__uart2
,
6133 &omap44xx_l4_per__uart3
,
6134 &omap44xx_l4_per__uart4
,
6135 &omap44xx_l4_cfg__usb_host_fs
,
6136 &omap44xx_l4_cfg__usb_host_hs
,
6137 &omap44xx_l4_cfg__usb_otg_hs
,
6138 &omap44xx_l4_cfg__usb_tll_hs
,
6139 &omap44xx_l4_wkup__wd_timer2
,
6140 &omap44xx_l4_abe__wd_timer3
,
6141 &omap44xx_l4_abe__wd_timer3_dma
,
6145 int __init
omap44xx_hwmod_init(void)
6147 return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs
);