2 * Hardware modules present on the OMAP44xx chips
4 * Copyright (C) 2009-2012 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
22 #include <linux/platform_data/gpio-omap.h>
23 #include <linux/power/smartreflex.h>
24 #include <linux/platform_data/omap_ocp2scp.h>
25 #include <linux/i2c-omap.h>
27 #include <linux/omap-dma.h>
29 #include <linux/platform_data/spi-omap2-mcspi.h>
30 #include <linux/platform_data/asoc-ti-mcbsp.h>
31 #include <linux/platform_data/iommu-omap.h>
32 #include <plat/dmtimer.h>
34 #include "omap_hwmod.h"
35 #include "omap_hwmod_common_data.h"
39 #include "prm-regbits-44xx.h"
44 /* Base offset for all OMAP4 interrupts external to MPUSS */
45 #define OMAP44XX_IRQ_GIC_START 32
47 /* Base offset for all OMAP4 dma requests */
48 #define OMAP44XX_DMA_REQ_START 1
55 * 'c2c_target_fw' class
56 * instance(s): c2c_target_fw
58 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class
= {
59 .name
= "c2c_target_fw",
63 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod
= {
64 .name
= "c2c_target_fw",
65 .class = &omap44xx_c2c_target_fw_hwmod_class
,
66 .clkdm_name
= "d2d_clkdm",
69 .clkctrl_offs
= OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET
,
70 .context_offs
= OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET
,
79 static struct omap_hwmod_class omap44xx_dmm_hwmod_class
= {
84 static struct omap_hwmod_irq_info omap44xx_dmm_irqs
[] = {
85 { .irq
= 113 + OMAP44XX_IRQ_GIC_START
},
89 static struct omap_hwmod omap44xx_dmm_hwmod
= {
91 .class = &omap44xx_dmm_hwmod_class
,
92 .clkdm_name
= "l3_emif_clkdm",
93 .mpu_irqs
= omap44xx_dmm_irqs
,
96 .clkctrl_offs
= OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET
,
97 .context_offs
= OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET
,
104 * instance(s): emif_fw
106 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class
= {
111 static struct omap_hwmod omap44xx_emif_fw_hwmod
= {
113 .class = &omap44xx_emif_fw_hwmod_class
,
114 .clkdm_name
= "l3_emif_clkdm",
117 .clkctrl_offs
= OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET
,
118 .context_offs
= OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET
,
125 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
127 static struct omap_hwmod_class omap44xx_l3_hwmod_class
= {
132 static struct omap_hwmod omap44xx_l3_instr_hwmod
= {
134 .class = &omap44xx_l3_hwmod_class
,
135 .clkdm_name
= "l3_instr_clkdm",
138 .clkctrl_offs
= OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET
,
139 .context_offs
= OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET
,
140 .modulemode
= MODULEMODE_HWCTRL
,
146 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs
[] = {
147 { .name
= "dbg_err", .irq
= 9 + OMAP44XX_IRQ_GIC_START
},
148 { .name
= "app_err", .irq
= 10 + OMAP44XX_IRQ_GIC_START
},
152 static struct omap_hwmod omap44xx_l3_main_1_hwmod
= {
154 .class = &omap44xx_l3_hwmod_class
,
155 .clkdm_name
= "l3_1_clkdm",
156 .mpu_irqs
= omap44xx_l3_main_1_irqs
,
159 .clkctrl_offs
= OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET
,
160 .context_offs
= OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET
,
166 static struct omap_hwmod omap44xx_l3_main_2_hwmod
= {
168 .class = &omap44xx_l3_hwmod_class
,
169 .clkdm_name
= "l3_2_clkdm",
172 .clkctrl_offs
= OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET
,
173 .context_offs
= OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET
,
179 static struct omap_hwmod omap44xx_l3_main_3_hwmod
= {
181 .class = &omap44xx_l3_hwmod_class
,
182 .clkdm_name
= "l3_instr_clkdm",
185 .clkctrl_offs
= OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET
,
186 .context_offs
= OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET
,
187 .modulemode
= MODULEMODE_HWCTRL
,
194 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
196 static struct omap_hwmod_class omap44xx_l4_hwmod_class
= {
201 static struct omap_hwmod omap44xx_l4_abe_hwmod
= {
203 .class = &omap44xx_l4_hwmod_class
,
204 .clkdm_name
= "abe_clkdm",
207 .clkctrl_offs
= OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET
,
208 .context_offs
= OMAP4_RM_ABE_AESS_CONTEXT_OFFSET
,
209 .lostcontext_mask
= OMAP4430_LOSTMEM_AESSMEM_MASK
,
210 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
216 static struct omap_hwmod omap44xx_l4_cfg_hwmod
= {
218 .class = &omap44xx_l4_hwmod_class
,
219 .clkdm_name
= "l4_cfg_clkdm",
222 .clkctrl_offs
= OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET
,
223 .context_offs
= OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET
,
229 static struct omap_hwmod omap44xx_l4_per_hwmod
= {
231 .class = &omap44xx_l4_hwmod_class
,
232 .clkdm_name
= "l4_per_clkdm",
235 .clkctrl_offs
= OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET
,
236 .context_offs
= OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET
,
242 static struct omap_hwmod omap44xx_l4_wkup_hwmod
= {
244 .class = &omap44xx_l4_hwmod_class
,
245 .clkdm_name
= "l4_wkup_clkdm",
248 .clkctrl_offs
= OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET
,
249 .context_offs
= OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET
,
256 * instance(s): mpu_private
258 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class
= {
263 static struct omap_hwmod omap44xx_mpu_private_hwmod
= {
264 .name
= "mpu_private",
265 .class = &omap44xx_mpu_bus_hwmod_class
,
266 .clkdm_name
= "mpuss_clkdm",
269 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
276 * instance(s): ocp_wp_noc
278 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class
= {
279 .name
= "ocp_wp_noc",
283 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod
= {
284 .name
= "ocp_wp_noc",
285 .class = &omap44xx_ocp_wp_noc_hwmod_class
,
286 .clkdm_name
= "l3_instr_clkdm",
289 .clkctrl_offs
= OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET
,
290 .context_offs
= OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET
,
291 .modulemode
= MODULEMODE_HWCTRL
,
297 * Modules omap_hwmod structures
299 * The following IPs are excluded for the moment because:
300 * - They do not need an explicit SW control using omap_hwmod API.
301 * - They still need to be validated with the driver
302 * properly adapted to omap_hwmod / omap_device
309 * audio engine sub system
312 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc
= {
315 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
),
316 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
317 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
|
318 MSTANDBY_SMART_WKUP
),
319 .sysc_fields
= &omap_hwmod_sysc_type2
,
322 static struct omap_hwmod_class omap44xx_aess_hwmod_class
= {
324 .sysc
= &omap44xx_aess_sysc
,
325 .enable_preprogram
= omap_hwmod_aess_preprogram
,
329 static struct omap_hwmod_irq_info omap44xx_aess_irqs
[] = {
330 { .irq
= 99 + OMAP44XX_IRQ_GIC_START
},
334 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs
[] = {
335 { .name
= "fifo0", .dma_req
= 100 + OMAP44XX_DMA_REQ_START
},
336 { .name
= "fifo1", .dma_req
= 101 + OMAP44XX_DMA_REQ_START
},
337 { .name
= "fifo2", .dma_req
= 102 + OMAP44XX_DMA_REQ_START
},
338 { .name
= "fifo3", .dma_req
= 103 + OMAP44XX_DMA_REQ_START
},
339 { .name
= "fifo4", .dma_req
= 104 + OMAP44XX_DMA_REQ_START
},
340 { .name
= "fifo5", .dma_req
= 105 + OMAP44XX_DMA_REQ_START
},
341 { .name
= "fifo6", .dma_req
= 106 + OMAP44XX_DMA_REQ_START
},
342 { .name
= "fifo7", .dma_req
= 107 + OMAP44XX_DMA_REQ_START
},
346 static struct omap_hwmod omap44xx_aess_hwmod
= {
348 .class = &omap44xx_aess_hwmod_class
,
349 .clkdm_name
= "abe_clkdm",
350 .mpu_irqs
= omap44xx_aess_irqs
,
351 .sdma_reqs
= omap44xx_aess_sdma_reqs
,
352 .main_clk
= "aess_fclk",
355 .clkctrl_offs
= OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET
,
356 .context_offs
= OMAP4_RM_ABE_AESS_CONTEXT_OFFSET
,
357 .lostcontext_mask
= OMAP4430_LOSTCONTEXT_DFF_MASK
,
358 .modulemode
= MODULEMODE_SWCTRL
,
365 * chip 2 chip interface used to plug the ape soc (omap) with an external modem
369 static struct omap_hwmod_class omap44xx_c2c_hwmod_class
= {
374 static struct omap_hwmod_irq_info omap44xx_c2c_irqs
[] = {
375 { .irq
= 88 + OMAP44XX_IRQ_GIC_START
},
379 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs
[] = {
380 { .dma_req
= 68 + OMAP44XX_DMA_REQ_START
},
384 static struct omap_hwmod omap44xx_c2c_hwmod
= {
386 .class = &omap44xx_c2c_hwmod_class
,
387 .clkdm_name
= "d2d_clkdm",
388 .mpu_irqs
= omap44xx_c2c_irqs
,
389 .sdma_reqs
= omap44xx_c2c_sdma_reqs
,
392 .clkctrl_offs
= OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET
,
393 .context_offs
= OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET
,
400 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
403 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc
= {
406 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
407 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
),
408 .sysc_fields
= &omap_hwmod_sysc_type1
,
411 static struct omap_hwmod_class omap44xx_counter_hwmod_class
= {
413 .sysc
= &omap44xx_counter_sysc
,
417 static struct omap_hwmod omap44xx_counter_32k_hwmod
= {
418 .name
= "counter_32k",
419 .class = &omap44xx_counter_hwmod_class
,
420 .clkdm_name
= "l4_wkup_clkdm",
421 .flags
= HWMOD_SWSUP_SIDLE
,
422 .main_clk
= "sys_32k_ck",
425 .clkctrl_offs
= OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET
,
426 .context_offs
= OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET
,
432 * 'ctrl_module' class
433 * attila core control module + core pad control module + wkup pad control
434 * module + attila wkup control module
437 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc
= {
440 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
441 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
443 .sysc_fields
= &omap_hwmod_sysc_type2
,
446 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class
= {
447 .name
= "ctrl_module",
448 .sysc
= &omap44xx_ctrl_module_sysc
,
451 /* ctrl_module_core */
452 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs
[] = {
453 { .irq
= 8 + OMAP44XX_IRQ_GIC_START
},
457 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod
= {
458 .name
= "ctrl_module_core",
459 .class = &omap44xx_ctrl_module_hwmod_class
,
460 .clkdm_name
= "l4_cfg_clkdm",
461 .mpu_irqs
= omap44xx_ctrl_module_core_irqs
,
464 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
469 /* ctrl_module_pad_core */
470 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod
= {
471 .name
= "ctrl_module_pad_core",
472 .class = &omap44xx_ctrl_module_hwmod_class
,
473 .clkdm_name
= "l4_cfg_clkdm",
476 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
481 /* ctrl_module_wkup */
482 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod
= {
483 .name
= "ctrl_module_wkup",
484 .class = &omap44xx_ctrl_module_hwmod_class
,
485 .clkdm_name
= "l4_wkup_clkdm",
488 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
493 /* ctrl_module_pad_wkup */
494 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod
= {
495 .name
= "ctrl_module_pad_wkup",
496 .class = &omap44xx_ctrl_module_hwmod_class
,
497 .clkdm_name
= "l4_wkup_clkdm",
500 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
507 * debug and emulation sub system
510 static struct omap_hwmod_class omap44xx_debugss_hwmod_class
= {
515 static struct omap_hwmod omap44xx_debugss_hwmod
= {
517 .class = &omap44xx_debugss_hwmod_class
,
518 .clkdm_name
= "emu_sys_clkdm",
519 .main_clk
= "trace_clk_div_ck",
522 .clkctrl_offs
= OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET
,
523 .context_offs
= OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET
,
530 * dma controller for data exchange between memory to memory (i.e. internal or
531 * external memory) and gp peripherals to memory or memory to gp peripherals
534 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc
= {
538 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
539 SYSC_HAS_EMUFREE
| SYSC_HAS_MIDLEMODE
|
540 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
541 SYSS_HAS_RESET_STATUS
),
542 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
543 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
544 .sysc_fields
= &omap_hwmod_sysc_type1
,
547 static struct omap_hwmod_class omap44xx_dma_hwmod_class
= {
549 .sysc
= &omap44xx_dma_sysc
,
553 static struct omap_dma_dev_attr dma_dev_attr
= {
554 .dev_caps
= RESERVE_CHANNEL
| DMA_LINKED_LCH
| GLOBAL_PRIORITY
|
555 IS_CSSA_32
| IS_CDSA_32
| IS_RW_PRIORITY
,
560 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs
[] = {
561 { .name
= "0", .irq
= 12 + OMAP44XX_IRQ_GIC_START
},
562 { .name
= "1", .irq
= 13 + OMAP44XX_IRQ_GIC_START
},
563 { .name
= "2", .irq
= 14 + OMAP44XX_IRQ_GIC_START
},
564 { .name
= "3", .irq
= 15 + OMAP44XX_IRQ_GIC_START
},
568 static struct omap_hwmod omap44xx_dma_system_hwmod
= {
569 .name
= "dma_system",
570 .class = &omap44xx_dma_hwmod_class
,
571 .clkdm_name
= "l3_dma_clkdm",
572 .mpu_irqs
= omap44xx_dma_system_irqs
,
573 .main_clk
= "l3_div_ck",
576 .clkctrl_offs
= OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET
,
577 .context_offs
= OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET
,
580 .dev_attr
= &dma_dev_attr
,
585 * digital microphone controller
588 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc
= {
591 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
592 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
593 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
595 .sysc_fields
= &omap_hwmod_sysc_type2
,
598 static struct omap_hwmod_class omap44xx_dmic_hwmod_class
= {
600 .sysc
= &omap44xx_dmic_sysc
,
604 static struct omap_hwmod_irq_info omap44xx_dmic_irqs
[] = {
605 { .irq
= 114 + OMAP44XX_IRQ_GIC_START
},
609 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs
[] = {
610 { .dma_req
= 66 + OMAP44XX_DMA_REQ_START
},
614 static struct omap_hwmod omap44xx_dmic_hwmod
= {
616 .class = &omap44xx_dmic_hwmod_class
,
617 .clkdm_name
= "abe_clkdm",
618 .mpu_irqs
= omap44xx_dmic_irqs
,
619 .sdma_reqs
= omap44xx_dmic_sdma_reqs
,
620 .main_clk
= "func_dmic_abe_gfclk",
623 .clkctrl_offs
= OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET
,
624 .context_offs
= OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET
,
625 .modulemode
= MODULEMODE_SWCTRL
,
635 static struct omap_hwmod_class omap44xx_dsp_hwmod_class
= {
640 static struct omap_hwmod_irq_info omap44xx_dsp_irqs
[] = {
641 { .irq
= 28 + OMAP44XX_IRQ_GIC_START
},
645 static struct omap_hwmod_rst_info omap44xx_dsp_resets
[] = {
646 { .name
= "dsp", .rst_shift
= 0 },
649 static struct omap_hwmod omap44xx_dsp_hwmod
= {
651 .class = &omap44xx_dsp_hwmod_class
,
652 .clkdm_name
= "tesla_clkdm",
653 .mpu_irqs
= omap44xx_dsp_irqs
,
654 .rst_lines
= omap44xx_dsp_resets
,
655 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_dsp_resets
),
656 .main_clk
= "dpll_iva_m4x2_ck",
659 .clkctrl_offs
= OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET
,
660 .rstctrl_offs
= OMAP4_RM_TESLA_RSTCTRL_OFFSET
,
661 .context_offs
= OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET
,
662 .modulemode
= MODULEMODE_HWCTRL
,
672 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc
= {
675 .sysc_flags
= SYSS_HAS_RESET_STATUS
,
678 static struct omap_hwmod_class omap44xx_dss_hwmod_class
= {
680 .sysc
= &omap44xx_dss_sysc
,
681 .reset
= omap_dss_reset
,
685 static struct omap_hwmod_opt_clk dss_opt_clks
[] = {
686 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
687 { .role
= "tv_clk", .clk
= "dss_tv_clk" },
688 { .role
= "hdmi_clk", .clk
= "dss_48mhz_clk" },
691 static struct omap_hwmod omap44xx_dss_hwmod
= {
693 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
694 .class = &omap44xx_dss_hwmod_class
,
695 .clkdm_name
= "l3_dss_clkdm",
696 .main_clk
= "dss_dss_clk",
699 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
700 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
703 .opt_clks
= dss_opt_clks
,
704 .opt_clks_cnt
= ARRAY_SIZE(dss_opt_clks
),
712 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc
= {
716 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
717 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_MIDLEMODE
|
718 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
719 SYSS_HAS_RESET_STATUS
),
720 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
721 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
722 .sysc_fields
= &omap_hwmod_sysc_type1
,
725 static struct omap_hwmod_class omap44xx_dispc_hwmod_class
= {
727 .sysc
= &omap44xx_dispc_sysc
,
731 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs
[] = {
732 { .irq
= 25 + OMAP44XX_IRQ_GIC_START
},
736 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs
[] = {
737 { .dma_req
= 5 + OMAP44XX_DMA_REQ_START
},
741 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr
= {
743 .has_framedonetv_irq
= 1
746 static struct omap_hwmod omap44xx_dss_dispc_hwmod
= {
748 .class = &omap44xx_dispc_hwmod_class
,
749 .clkdm_name
= "l3_dss_clkdm",
750 .mpu_irqs
= omap44xx_dss_dispc_irqs
,
751 .sdma_reqs
= omap44xx_dss_dispc_sdma_reqs
,
752 .main_clk
= "dss_dss_clk",
755 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
756 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
759 .dev_attr
= &omap44xx_dss_dispc_dev_attr
764 * display serial interface controller
767 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc
= {
771 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
772 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
773 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
774 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
775 .sysc_fields
= &omap_hwmod_sysc_type1
,
778 static struct omap_hwmod_class omap44xx_dsi_hwmod_class
= {
780 .sysc
= &omap44xx_dsi_sysc
,
784 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs
[] = {
785 { .irq
= 53 + OMAP44XX_IRQ_GIC_START
},
789 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs
[] = {
790 { .dma_req
= 74 + OMAP44XX_DMA_REQ_START
},
794 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks
[] = {
795 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
798 static struct omap_hwmod omap44xx_dss_dsi1_hwmod
= {
800 .class = &omap44xx_dsi_hwmod_class
,
801 .clkdm_name
= "l3_dss_clkdm",
802 .mpu_irqs
= omap44xx_dss_dsi1_irqs
,
803 .sdma_reqs
= omap44xx_dss_dsi1_sdma_reqs
,
804 .main_clk
= "dss_dss_clk",
807 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
808 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
811 .opt_clks
= dss_dsi1_opt_clks
,
812 .opt_clks_cnt
= ARRAY_SIZE(dss_dsi1_opt_clks
),
816 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs
[] = {
817 { .irq
= 84 + OMAP44XX_IRQ_GIC_START
},
821 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs
[] = {
822 { .dma_req
= 83 + OMAP44XX_DMA_REQ_START
},
826 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks
[] = {
827 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
830 static struct omap_hwmod omap44xx_dss_dsi2_hwmod
= {
832 .class = &omap44xx_dsi_hwmod_class
,
833 .clkdm_name
= "l3_dss_clkdm",
834 .mpu_irqs
= omap44xx_dss_dsi2_irqs
,
835 .sdma_reqs
= omap44xx_dss_dsi2_sdma_reqs
,
836 .main_clk
= "dss_dss_clk",
839 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
840 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
843 .opt_clks
= dss_dsi2_opt_clks
,
844 .opt_clks_cnt
= ARRAY_SIZE(dss_dsi2_opt_clks
),
852 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc
= {
855 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
857 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
859 .sysc_fields
= &omap_hwmod_sysc_type2
,
862 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class
= {
864 .sysc
= &omap44xx_hdmi_sysc
,
868 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs
[] = {
869 { .irq
= 101 + OMAP44XX_IRQ_GIC_START
},
873 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs
[] = {
874 { .dma_req
= 75 + OMAP44XX_DMA_REQ_START
},
878 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks
[] = {
879 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
882 static struct omap_hwmod omap44xx_dss_hdmi_hwmod
= {
884 .class = &omap44xx_hdmi_hwmod_class
,
885 .clkdm_name
= "l3_dss_clkdm",
887 * HDMI audio requires to use no-idle mode. Hence,
888 * set idle mode by software.
890 .flags
= HWMOD_SWSUP_SIDLE
,
891 .mpu_irqs
= omap44xx_dss_hdmi_irqs
,
892 .sdma_reqs
= omap44xx_dss_hdmi_sdma_reqs
,
893 .main_clk
= "dss_48mhz_clk",
896 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
897 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
900 .opt_clks
= dss_hdmi_opt_clks
,
901 .opt_clks_cnt
= ARRAY_SIZE(dss_hdmi_opt_clks
),
906 * remote frame buffer interface
909 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc
= {
913 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SIDLEMODE
|
914 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
915 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
916 .sysc_fields
= &omap_hwmod_sysc_type1
,
919 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class
= {
921 .sysc
= &omap44xx_rfbi_sysc
,
925 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs
[] = {
926 { .dma_req
= 13 + OMAP44XX_DMA_REQ_START
},
930 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks
[] = {
931 { .role
= "ick", .clk
= "dss_fck" },
934 static struct omap_hwmod omap44xx_dss_rfbi_hwmod
= {
936 .class = &omap44xx_rfbi_hwmod_class
,
937 .clkdm_name
= "l3_dss_clkdm",
938 .sdma_reqs
= omap44xx_dss_rfbi_sdma_reqs
,
939 .main_clk
= "dss_dss_clk",
942 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
943 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
946 .opt_clks
= dss_rfbi_opt_clks
,
947 .opt_clks_cnt
= ARRAY_SIZE(dss_rfbi_opt_clks
),
955 static struct omap_hwmod_class omap44xx_venc_hwmod_class
= {
960 static struct omap_hwmod omap44xx_dss_venc_hwmod
= {
962 .class = &omap44xx_venc_hwmod_class
,
963 .clkdm_name
= "l3_dss_clkdm",
964 .main_clk
= "dss_tv_clk",
967 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
968 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
975 * bch error location module
978 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc
= {
982 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
983 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
984 SYSS_HAS_RESET_STATUS
),
985 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
986 .sysc_fields
= &omap_hwmod_sysc_type1
,
989 static struct omap_hwmod_class omap44xx_elm_hwmod_class
= {
991 .sysc
= &omap44xx_elm_sysc
,
995 static struct omap_hwmod_irq_info omap44xx_elm_irqs
[] = {
996 { .irq
= 4 + OMAP44XX_IRQ_GIC_START
},
1000 static struct omap_hwmod omap44xx_elm_hwmod
= {
1002 .class = &omap44xx_elm_hwmod_class
,
1003 .clkdm_name
= "l4_per_clkdm",
1004 .mpu_irqs
= omap44xx_elm_irqs
,
1007 .clkctrl_offs
= OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET
,
1008 .context_offs
= OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET
,
1015 * external memory interface no1
1018 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc
= {
1022 static struct omap_hwmod_class omap44xx_emif_hwmod_class
= {
1024 .sysc
= &omap44xx_emif_sysc
,
1028 static struct omap_hwmod_irq_info omap44xx_emif1_irqs
[] = {
1029 { .irq
= 110 + OMAP44XX_IRQ_GIC_START
},
1033 static struct omap_hwmod omap44xx_emif1_hwmod
= {
1035 .class = &omap44xx_emif_hwmod_class
,
1036 .clkdm_name
= "l3_emif_clkdm",
1037 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
1038 .mpu_irqs
= omap44xx_emif1_irqs
,
1039 .main_clk
= "ddrphy_ck",
1042 .clkctrl_offs
= OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET
,
1043 .context_offs
= OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET
,
1044 .modulemode
= MODULEMODE_HWCTRL
,
1050 static struct omap_hwmod_irq_info omap44xx_emif2_irqs
[] = {
1051 { .irq
= 111 + OMAP44XX_IRQ_GIC_START
},
1055 static struct omap_hwmod omap44xx_emif2_hwmod
= {
1057 .class = &omap44xx_emif_hwmod_class
,
1058 .clkdm_name
= "l3_emif_clkdm",
1059 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
1060 .mpu_irqs
= omap44xx_emif2_irqs
,
1061 .main_clk
= "ddrphy_ck",
1064 .clkctrl_offs
= OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET
,
1065 .context_offs
= OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET
,
1066 .modulemode
= MODULEMODE_HWCTRL
,
1073 * face detection hw accelerator module
1076 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc
= {
1078 .sysc_offs
= 0x0010,
1080 * FDIF needs 100 OCP clk cycles delay after a softreset before
1081 * accessing sysconfig again.
1082 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1083 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1085 * TODO: Indicate errata when available.
1088 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_RESET_STATUS
|
1089 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1090 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1091 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
1092 .sysc_fields
= &omap_hwmod_sysc_type2
,
1095 static struct omap_hwmod_class omap44xx_fdif_hwmod_class
= {
1097 .sysc
= &omap44xx_fdif_sysc
,
1101 static struct omap_hwmod_irq_info omap44xx_fdif_irqs
[] = {
1102 { .irq
= 69 + OMAP44XX_IRQ_GIC_START
},
1106 static struct omap_hwmod omap44xx_fdif_hwmod
= {
1108 .class = &omap44xx_fdif_hwmod_class
,
1109 .clkdm_name
= "iss_clkdm",
1110 .mpu_irqs
= omap44xx_fdif_irqs
,
1111 .main_clk
= "fdif_fck",
1114 .clkctrl_offs
= OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET
,
1115 .context_offs
= OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET
,
1116 .modulemode
= MODULEMODE_SWCTRL
,
1123 * general purpose io module
1126 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc
= {
1128 .sysc_offs
= 0x0010,
1129 .syss_offs
= 0x0114,
1130 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
1131 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
1132 SYSS_HAS_RESET_STATUS
),
1133 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1135 .sysc_fields
= &omap_hwmod_sysc_type1
,
1138 static struct omap_hwmod_class omap44xx_gpio_hwmod_class
= {
1140 .sysc
= &omap44xx_gpio_sysc
,
1145 static struct omap_gpio_dev_attr gpio_dev_attr
= {
1151 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs
[] = {
1152 { .irq
= 29 + OMAP44XX_IRQ_GIC_START
},
1156 static struct omap_hwmod_opt_clk gpio1_opt_clks
[] = {
1157 { .role
= "dbclk", .clk
= "gpio1_dbclk" },
1160 static struct omap_hwmod omap44xx_gpio1_hwmod
= {
1162 .class = &omap44xx_gpio_hwmod_class
,
1163 .clkdm_name
= "l4_wkup_clkdm",
1164 .mpu_irqs
= omap44xx_gpio1_irqs
,
1165 .main_clk
= "l4_wkup_clk_mux_ck",
1168 .clkctrl_offs
= OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET
,
1169 .context_offs
= OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET
,
1170 .modulemode
= MODULEMODE_HWCTRL
,
1173 .opt_clks
= gpio1_opt_clks
,
1174 .opt_clks_cnt
= ARRAY_SIZE(gpio1_opt_clks
),
1175 .dev_attr
= &gpio_dev_attr
,
1179 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs
[] = {
1180 { .irq
= 30 + OMAP44XX_IRQ_GIC_START
},
1184 static struct omap_hwmod_opt_clk gpio2_opt_clks
[] = {
1185 { .role
= "dbclk", .clk
= "gpio2_dbclk" },
1188 static struct omap_hwmod omap44xx_gpio2_hwmod
= {
1190 .class = &omap44xx_gpio_hwmod_class
,
1191 .clkdm_name
= "l4_per_clkdm",
1192 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1193 .mpu_irqs
= omap44xx_gpio2_irqs
,
1194 .main_clk
= "l4_div_ck",
1197 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET
,
1198 .context_offs
= OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET
,
1199 .modulemode
= MODULEMODE_HWCTRL
,
1202 .opt_clks
= gpio2_opt_clks
,
1203 .opt_clks_cnt
= ARRAY_SIZE(gpio2_opt_clks
),
1204 .dev_attr
= &gpio_dev_attr
,
1208 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs
[] = {
1209 { .irq
= 31 + OMAP44XX_IRQ_GIC_START
},
1213 static struct omap_hwmod_opt_clk gpio3_opt_clks
[] = {
1214 { .role
= "dbclk", .clk
= "gpio3_dbclk" },
1217 static struct omap_hwmod omap44xx_gpio3_hwmod
= {
1219 .class = &omap44xx_gpio_hwmod_class
,
1220 .clkdm_name
= "l4_per_clkdm",
1221 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1222 .mpu_irqs
= omap44xx_gpio3_irqs
,
1223 .main_clk
= "l4_div_ck",
1226 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET
,
1227 .context_offs
= OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET
,
1228 .modulemode
= MODULEMODE_HWCTRL
,
1231 .opt_clks
= gpio3_opt_clks
,
1232 .opt_clks_cnt
= ARRAY_SIZE(gpio3_opt_clks
),
1233 .dev_attr
= &gpio_dev_attr
,
1237 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs
[] = {
1238 { .irq
= 32 + OMAP44XX_IRQ_GIC_START
},
1242 static struct omap_hwmod_opt_clk gpio4_opt_clks
[] = {
1243 { .role
= "dbclk", .clk
= "gpio4_dbclk" },
1246 static struct omap_hwmod omap44xx_gpio4_hwmod
= {
1248 .class = &omap44xx_gpio_hwmod_class
,
1249 .clkdm_name
= "l4_per_clkdm",
1250 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1251 .mpu_irqs
= omap44xx_gpio4_irqs
,
1252 .main_clk
= "l4_div_ck",
1255 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET
,
1256 .context_offs
= OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET
,
1257 .modulemode
= MODULEMODE_HWCTRL
,
1260 .opt_clks
= gpio4_opt_clks
,
1261 .opt_clks_cnt
= ARRAY_SIZE(gpio4_opt_clks
),
1262 .dev_attr
= &gpio_dev_attr
,
1266 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs
[] = {
1267 { .irq
= 33 + OMAP44XX_IRQ_GIC_START
},
1271 static struct omap_hwmod_opt_clk gpio5_opt_clks
[] = {
1272 { .role
= "dbclk", .clk
= "gpio5_dbclk" },
1275 static struct omap_hwmod omap44xx_gpio5_hwmod
= {
1277 .class = &omap44xx_gpio_hwmod_class
,
1278 .clkdm_name
= "l4_per_clkdm",
1279 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1280 .mpu_irqs
= omap44xx_gpio5_irqs
,
1281 .main_clk
= "l4_div_ck",
1284 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET
,
1285 .context_offs
= OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET
,
1286 .modulemode
= MODULEMODE_HWCTRL
,
1289 .opt_clks
= gpio5_opt_clks
,
1290 .opt_clks_cnt
= ARRAY_SIZE(gpio5_opt_clks
),
1291 .dev_attr
= &gpio_dev_attr
,
1295 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs
[] = {
1296 { .irq
= 34 + OMAP44XX_IRQ_GIC_START
},
1300 static struct omap_hwmod_opt_clk gpio6_opt_clks
[] = {
1301 { .role
= "dbclk", .clk
= "gpio6_dbclk" },
1304 static struct omap_hwmod omap44xx_gpio6_hwmod
= {
1306 .class = &omap44xx_gpio_hwmod_class
,
1307 .clkdm_name
= "l4_per_clkdm",
1308 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1309 .mpu_irqs
= omap44xx_gpio6_irqs
,
1310 .main_clk
= "l4_div_ck",
1313 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET
,
1314 .context_offs
= OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET
,
1315 .modulemode
= MODULEMODE_HWCTRL
,
1318 .opt_clks
= gpio6_opt_clks
,
1319 .opt_clks_cnt
= ARRAY_SIZE(gpio6_opt_clks
),
1320 .dev_attr
= &gpio_dev_attr
,
1325 * general purpose memory controller
1328 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc
= {
1330 .sysc_offs
= 0x0010,
1331 .syss_offs
= 0x0014,
1332 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SIDLEMODE
|
1333 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1334 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1335 .sysc_fields
= &omap_hwmod_sysc_type1
,
1338 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class
= {
1340 .sysc
= &omap44xx_gpmc_sysc
,
1344 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs
[] = {
1345 { .irq
= 20 + OMAP44XX_IRQ_GIC_START
},
1349 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs
[] = {
1350 { .dma_req
= 3 + OMAP44XX_DMA_REQ_START
},
1354 static struct omap_hwmod omap44xx_gpmc_hwmod
= {
1356 .class = &omap44xx_gpmc_hwmod_class
,
1357 .clkdm_name
= "l3_2_clkdm",
1359 * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
1360 * block. It is not being added due to any known bugs with
1361 * resetting the GPMC IP block, but rather because any timings
1362 * set by the bootloader are not being correctly programmed by
1363 * the kernel from the board file or DT data.
1364 * HWMOD_INIT_NO_RESET should be removed ASAP.
1366 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
1367 .mpu_irqs
= omap44xx_gpmc_irqs
,
1368 .sdma_reqs
= omap44xx_gpmc_sdma_reqs
,
1371 .clkctrl_offs
= OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET
,
1372 .context_offs
= OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET
,
1373 .modulemode
= MODULEMODE_HWCTRL
,
1380 * 2d/3d graphics accelerator
1383 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc
= {
1384 .rev_offs
= 0x1fc00,
1385 .sysc_offs
= 0x1fc10,
1386 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
),
1387 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1388 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1389 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1390 .sysc_fields
= &omap_hwmod_sysc_type2
,
1393 static struct omap_hwmod_class omap44xx_gpu_hwmod_class
= {
1395 .sysc
= &omap44xx_gpu_sysc
,
1399 static struct omap_hwmod_irq_info omap44xx_gpu_irqs
[] = {
1400 { .irq
= 21 + OMAP44XX_IRQ_GIC_START
},
1404 static struct omap_hwmod omap44xx_gpu_hwmod
= {
1406 .class = &omap44xx_gpu_hwmod_class
,
1407 .clkdm_name
= "l3_gfx_clkdm",
1408 .mpu_irqs
= omap44xx_gpu_irqs
,
1409 .main_clk
= "sgx_clk_mux",
1412 .clkctrl_offs
= OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET
,
1413 .context_offs
= OMAP4_RM_GFX_GFX_CONTEXT_OFFSET
,
1414 .modulemode
= MODULEMODE_SWCTRL
,
1421 * hdq / 1-wire serial interface controller
1424 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc
= {
1426 .sysc_offs
= 0x0014,
1427 .syss_offs
= 0x0018,
1428 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SOFTRESET
|
1429 SYSS_HAS_RESET_STATUS
),
1430 .sysc_fields
= &omap_hwmod_sysc_type1
,
1433 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class
= {
1435 .sysc
= &omap44xx_hdq1w_sysc
,
1439 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs
[] = {
1440 { .irq
= 58 + OMAP44XX_IRQ_GIC_START
},
1444 static struct omap_hwmod omap44xx_hdq1w_hwmod
= {
1446 .class = &omap44xx_hdq1w_hwmod_class
,
1447 .clkdm_name
= "l4_per_clkdm",
1448 .flags
= HWMOD_INIT_NO_RESET
, /* XXX temporary */
1449 .mpu_irqs
= omap44xx_hdq1w_irqs
,
1450 .main_clk
= "func_12m_fclk",
1453 .clkctrl_offs
= OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET
,
1454 .context_offs
= OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET
,
1455 .modulemode
= MODULEMODE_SWCTRL
,
1462 * mipi high-speed synchronous serial interface (multichannel and full-duplex
1466 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc
= {
1468 .sysc_offs
= 0x0010,
1469 .syss_offs
= 0x0014,
1470 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_EMUFREE
|
1471 SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
|
1472 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1473 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1474 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1475 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1476 .sysc_fields
= &omap_hwmod_sysc_type1
,
1479 static struct omap_hwmod_class omap44xx_hsi_hwmod_class
= {
1481 .sysc
= &omap44xx_hsi_sysc
,
1485 static struct omap_hwmod_irq_info omap44xx_hsi_irqs
[] = {
1486 { .name
= "mpu_p1", .irq
= 67 + OMAP44XX_IRQ_GIC_START
},
1487 { .name
= "mpu_p2", .irq
= 68 + OMAP44XX_IRQ_GIC_START
},
1488 { .name
= "mpu_dma", .irq
= 71 + OMAP44XX_IRQ_GIC_START
},
1492 static struct omap_hwmod omap44xx_hsi_hwmod
= {
1494 .class = &omap44xx_hsi_hwmod_class
,
1495 .clkdm_name
= "l3_init_clkdm",
1496 .mpu_irqs
= omap44xx_hsi_irqs
,
1497 .main_clk
= "hsi_fck",
1500 .clkctrl_offs
= OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET
,
1501 .context_offs
= OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET
,
1502 .modulemode
= MODULEMODE_HWCTRL
,
1509 * multimaster high-speed i2c controller
1512 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc
= {
1513 .sysc_offs
= 0x0010,
1514 .syss_offs
= 0x0090,
1515 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
1516 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
1517 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1518 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1520 .clockact
= CLOCKACT_TEST_ICLK
,
1521 .sysc_fields
= &omap_hwmod_sysc_type1
,
1524 static struct omap_hwmod_class omap44xx_i2c_hwmod_class
= {
1526 .sysc
= &omap44xx_i2c_sysc
,
1527 .rev
= OMAP_I2C_IP_VERSION_2
,
1528 .reset
= &omap_i2c_reset
,
1531 static struct omap_i2c_dev_attr i2c_dev_attr
= {
1532 .flags
= OMAP_I2C_FLAG_BUS_SHIFT_NONE
,
1536 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs
[] = {
1537 { .irq
= 56 + OMAP44XX_IRQ_GIC_START
},
1541 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs
[] = {
1542 { .name
= "tx", .dma_req
= 26 + OMAP44XX_DMA_REQ_START
},
1543 { .name
= "rx", .dma_req
= 27 + OMAP44XX_DMA_REQ_START
},
1547 static struct omap_hwmod omap44xx_i2c1_hwmod
= {
1549 .class = &omap44xx_i2c_hwmod_class
,
1550 .clkdm_name
= "l4_per_clkdm",
1551 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1552 .mpu_irqs
= omap44xx_i2c1_irqs
,
1553 .sdma_reqs
= omap44xx_i2c1_sdma_reqs
,
1554 .main_clk
= "func_96m_fclk",
1557 .clkctrl_offs
= OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET
,
1558 .context_offs
= OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET
,
1559 .modulemode
= MODULEMODE_SWCTRL
,
1562 .dev_attr
= &i2c_dev_attr
,
1566 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs
[] = {
1567 { .irq
= 57 + OMAP44XX_IRQ_GIC_START
},
1571 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs
[] = {
1572 { .name
= "tx", .dma_req
= 28 + OMAP44XX_DMA_REQ_START
},
1573 { .name
= "rx", .dma_req
= 29 + OMAP44XX_DMA_REQ_START
},
1577 static struct omap_hwmod omap44xx_i2c2_hwmod
= {
1579 .class = &omap44xx_i2c_hwmod_class
,
1580 .clkdm_name
= "l4_per_clkdm",
1581 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1582 .mpu_irqs
= omap44xx_i2c2_irqs
,
1583 .sdma_reqs
= omap44xx_i2c2_sdma_reqs
,
1584 .main_clk
= "func_96m_fclk",
1587 .clkctrl_offs
= OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET
,
1588 .context_offs
= OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET
,
1589 .modulemode
= MODULEMODE_SWCTRL
,
1592 .dev_attr
= &i2c_dev_attr
,
1596 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs
[] = {
1597 { .irq
= 61 + OMAP44XX_IRQ_GIC_START
},
1601 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs
[] = {
1602 { .name
= "tx", .dma_req
= 24 + OMAP44XX_DMA_REQ_START
},
1603 { .name
= "rx", .dma_req
= 25 + OMAP44XX_DMA_REQ_START
},
1607 static struct omap_hwmod omap44xx_i2c3_hwmod
= {
1609 .class = &omap44xx_i2c_hwmod_class
,
1610 .clkdm_name
= "l4_per_clkdm",
1611 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1612 .mpu_irqs
= omap44xx_i2c3_irqs
,
1613 .sdma_reqs
= omap44xx_i2c3_sdma_reqs
,
1614 .main_clk
= "func_96m_fclk",
1617 .clkctrl_offs
= OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET
,
1618 .context_offs
= OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET
,
1619 .modulemode
= MODULEMODE_SWCTRL
,
1622 .dev_attr
= &i2c_dev_attr
,
1626 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs
[] = {
1627 { .irq
= 62 + OMAP44XX_IRQ_GIC_START
},
1631 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs
[] = {
1632 { .name
= "tx", .dma_req
= 123 + OMAP44XX_DMA_REQ_START
},
1633 { .name
= "rx", .dma_req
= 124 + OMAP44XX_DMA_REQ_START
},
1637 static struct omap_hwmod omap44xx_i2c4_hwmod
= {
1639 .class = &omap44xx_i2c_hwmod_class
,
1640 .clkdm_name
= "l4_per_clkdm",
1641 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1642 .mpu_irqs
= omap44xx_i2c4_irqs
,
1643 .sdma_reqs
= omap44xx_i2c4_sdma_reqs
,
1644 .main_clk
= "func_96m_fclk",
1647 .clkctrl_offs
= OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET
,
1648 .context_offs
= OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET
,
1649 .modulemode
= MODULEMODE_SWCTRL
,
1652 .dev_attr
= &i2c_dev_attr
,
1657 * imaging processor unit
1660 static struct omap_hwmod_class omap44xx_ipu_hwmod_class
= {
1665 static struct omap_hwmod_irq_info omap44xx_ipu_irqs
[] = {
1666 { .irq
= 100 + OMAP44XX_IRQ_GIC_START
},
1670 static struct omap_hwmod_rst_info omap44xx_ipu_resets
[] = {
1671 { .name
= "cpu0", .rst_shift
= 0 },
1672 { .name
= "cpu1", .rst_shift
= 1 },
1675 static struct omap_hwmod omap44xx_ipu_hwmod
= {
1677 .class = &omap44xx_ipu_hwmod_class
,
1678 .clkdm_name
= "ducati_clkdm",
1679 .mpu_irqs
= omap44xx_ipu_irqs
,
1680 .rst_lines
= omap44xx_ipu_resets
,
1681 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_ipu_resets
),
1682 .main_clk
= "ducati_clk_mux_ck",
1685 .clkctrl_offs
= OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET
,
1686 .rstctrl_offs
= OMAP4_RM_DUCATI_RSTCTRL_OFFSET
,
1687 .context_offs
= OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET
,
1688 .modulemode
= MODULEMODE_HWCTRL
,
1695 * external images sensor pixel data processor
1698 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc
= {
1700 .sysc_offs
= 0x0010,
1702 * ISS needs 100 OCP clk cycles delay after a softreset before
1703 * accessing sysconfig again.
1704 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1705 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1707 * TODO: Indicate errata when available.
1710 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_RESET_STATUS
|
1711 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1712 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1713 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1714 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1715 .sysc_fields
= &omap_hwmod_sysc_type2
,
1718 static struct omap_hwmod_class omap44xx_iss_hwmod_class
= {
1720 .sysc
= &omap44xx_iss_sysc
,
1724 static struct omap_hwmod_irq_info omap44xx_iss_irqs
[] = {
1725 { .irq
= 24 + OMAP44XX_IRQ_GIC_START
},
1729 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs
[] = {
1730 { .name
= "1", .dma_req
= 8 + OMAP44XX_DMA_REQ_START
},
1731 { .name
= "2", .dma_req
= 9 + OMAP44XX_DMA_REQ_START
},
1732 { .name
= "3", .dma_req
= 11 + OMAP44XX_DMA_REQ_START
},
1733 { .name
= "4", .dma_req
= 12 + OMAP44XX_DMA_REQ_START
},
1737 static struct omap_hwmod_opt_clk iss_opt_clks
[] = {
1738 { .role
= "ctrlclk", .clk
= "iss_ctrlclk" },
1741 static struct omap_hwmod omap44xx_iss_hwmod
= {
1743 .class = &omap44xx_iss_hwmod_class
,
1744 .clkdm_name
= "iss_clkdm",
1745 .mpu_irqs
= omap44xx_iss_irqs
,
1746 .sdma_reqs
= omap44xx_iss_sdma_reqs
,
1747 .main_clk
= "ducati_clk_mux_ck",
1750 .clkctrl_offs
= OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET
,
1751 .context_offs
= OMAP4_RM_CAM_ISS_CONTEXT_OFFSET
,
1752 .modulemode
= MODULEMODE_SWCTRL
,
1755 .opt_clks
= iss_opt_clks
,
1756 .opt_clks_cnt
= ARRAY_SIZE(iss_opt_clks
),
1761 * multi-standard video encoder/decoder hardware accelerator
1764 static struct omap_hwmod_class omap44xx_iva_hwmod_class
= {
1769 static struct omap_hwmod_irq_info omap44xx_iva_irqs
[] = {
1770 { .name
= "sync_1", .irq
= 103 + OMAP44XX_IRQ_GIC_START
},
1771 { .name
= "sync_0", .irq
= 104 + OMAP44XX_IRQ_GIC_START
},
1772 { .name
= "mailbox_0", .irq
= 107 + OMAP44XX_IRQ_GIC_START
},
1776 static struct omap_hwmod_rst_info omap44xx_iva_resets
[] = {
1777 { .name
= "seq0", .rst_shift
= 0 },
1778 { .name
= "seq1", .rst_shift
= 1 },
1779 { .name
= "logic", .rst_shift
= 2 },
1782 static struct omap_hwmod omap44xx_iva_hwmod
= {
1784 .class = &omap44xx_iva_hwmod_class
,
1785 .clkdm_name
= "ivahd_clkdm",
1786 .mpu_irqs
= omap44xx_iva_irqs
,
1787 .rst_lines
= omap44xx_iva_resets
,
1788 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_iva_resets
),
1789 .main_clk
= "dpll_iva_m5x2_ck",
1792 .clkctrl_offs
= OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET
,
1793 .rstctrl_offs
= OMAP4_RM_IVAHD_RSTCTRL_OFFSET
,
1794 .context_offs
= OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET
,
1795 .modulemode
= MODULEMODE_HWCTRL
,
1802 * keyboard controller
1805 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc
= {
1807 .sysc_offs
= 0x0010,
1808 .syss_offs
= 0x0014,
1809 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
1810 SYSC_HAS_EMUFREE
| SYSC_HAS_ENAWAKEUP
|
1811 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
1812 SYSS_HAS_RESET_STATUS
),
1813 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1814 .sysc_fields
= &omap_hwmod_sysc_type1
,
1817 static struct omap_hwmod_class omap44xx_kbd_hwmod_class
= {
1819 .sysc
= &omap44xx_kbd_sysc
,
1823 static struct omap_hwmod_irq_info omap44xx_kbd_irqs
[] = {
1824 { .irq
= 120 + OMAP44XX_IRQ_GIC_START
},
1828 static struct omap_hwmod omap44xx_kbd_hwmod
= {
1830 .class = &omap44xx_kbd_hwmod_class
,
1831 .clkdm_name
= "l4_wkup_clkdm",
1832 .mpu_irqs
= omap44xx_kbd_irqs
,
1833 .main_clk
= "sys_32k_ck",
1836 .clkctrl_offs
= OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET
,
1837 .context_offs
= OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET
,
1838 .modulemode
= MODULEMODE_SWCTRL
,
1845 * mailbox module allowing communication between the on-chip processors using a
1846 * queued mailbox-interrupt mechanism.
1849 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc
= {
1851 .sysc_offs
= 0x0010,
1852 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
1853 SYSC_HAS_SOFTRESET
),
1854 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1855 .sysc_fields
= &omap_hwmod_sysc_type2
,
1858 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class
= {
1860 .sysc
= &omap44xx_mailbox_sysc
,
1864 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs
[] = {
1865 { .irq
= 26 + OMAP44XX_IRQ_GIC_START
},
1869 static struct omap_hwmod omap44xx_mailbox_hwmod
= {
1871 .class = &omap44xx_mailbox_hwmod_class
,
1872 .clkdm_name
= "l4_cfg_clkdm",
1873 .mpu_irqs
= omap44xx_mailbox_irqs
,
1876 .clkctrl_offs
= OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET
,
1877 .context_offs
= OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET
,
1884 * multi-channel audio serial port controller
1887 /* The IP is not compliant to type1 / type2 scheme */
1888 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp
= {
1892 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc
= {
1893 .sysc_offs
= 0x0004,
1894 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
1895 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1897 .sysc_fields
= &omap_hwmod_sysc_type_mcasp
,
1900 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class
= {
1902 .sysc
= &omap44xx_mcasp_sysc
,
1906 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs
[] = {
1907 { .name
= "arevt", .irq
= 108 + OMAP44XX_IRQ_GIC_START
},
1908 { .name
= "axevt", .irq
= 109 + OMAP44XX_IRQ_GIC_START
},
1912 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs
[] = {
1913 { .name
= "axevt", .dma_req
= 7 + OMAP44XX_DMA_REQ_START
},
1914 { .name
= "arevt", .dma_req
= 10 + OMAP44XX_DMA_REQ_START
},
1918 static struct omap_hwmod omap44xx_mcasp_hwmod
= {
1920 .class = &omap44xx_mcasp_hwmod_class
,
1921 .clkdm_name
= "abe_clkdm",
1922 .mpu_irqs
= omap44xx_mcasp_irqs
,
1923 .sdma_reqs
= omap44xx_mcasp_sdma_reqs
,
1924 .main_clk
= "func_mcasp_abe_gfclk",
1927 .clkctrl_offs
= OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET
,
1928 .context_offs
= OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET
,
1929 .modulemode
= MODULEMODE_SWCTRL
,
1936 * multi channel buffered serial port controller
1939 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc
= {
1940 .sysc_offs
= 0x008c,
1941 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_ENAWAKEUP
|
1942 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1943 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1944 .sysc_fields
= &omap_hwmod_sysc_type1
,
1947 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class
= {
1949 .sysc
= &omap44xx_mcbsp_sysc
,
1950 .rev
= MCBSP_CONFIG_TYPE4
,
1954 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs
[] = {
1955 { .name
= "common", .irq
= 17 + OMAP44XX_IRQ_GIC_START
},
1959 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs
[] = {
1960 { .name
= "tx", .dma_req
= 32 + OMAP44XX_DMA_REQ_START
},
1961 { .name
= "rx", .dma_req
= 33 + OMAP44XX_DMA_REQ_START
},
1965 static struct omap_hwmod_opt_clk mcbsp1_opt_clks
[] = {
1966 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
1967 { .role
= "prcm_fck", .clk
= "mcbsp1_sync_mux_ck" },
1970 static struct omap_hwmod omap44xx_mcbsp1_hwmod
= {
1972 .class = &omap44xx_mcbsp_hwmod_class
,
1973 .clkdm_name
= "abe_clkdm",
1974 .mpu_irqs
= omap44xx_mcbsp1_irqs
,
1975 .sdma_reqs
= omap44xx_mcbsp1_sdma_reqs
,
1976 .main_clk
= "func_mcbsp1_gfclk",
1979 .clkctrl_offs
= OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET
,
1980 .context_offs
= OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET
,
1981 .modulemode
= MODULEMODE_SWCTRL
,
1984 .opt_clks
= mcbsp1_opt_clks
,
1985 .opt_clks_cnt
= ARRAY_SIZE(mcbsp1_opt_clks
),
1989 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs
[] = {
1990 { .name
= "common", .irq
= 22 + OMAP44XX_IRQ_GIC_START
},
1994 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs
[] = {
1995 { .name
= "tx", .dma_req
= 16 + OMAP44XX_DMA_REQ_START
},
1996 { .name
= "rx", .dma_req
= 17 + OMAP44XX_DMA_REQ_START
},
2000 static struct omap_hwmod_opt_clk mcbsp2_opt_clks
[] = {
2001 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
2002 { .role
= "prcm_fck", .clk
= "mcbsp2_sync_mux_ck" },
2005 static struct omap_hwmod omap44xx_mcbsp2_hwmod
= {
2007 .class = &omap44xx_mcbsp_hwmod_class
,
2008 .clkdm_name
= "abe_clkdm",
2009 .mpu_irqs
= omap44xx_mcbsp2_irqs
,
2010 .sdma_reqs
= omap44xx_mcbsp2_sdma_reqs
,
2011 .main_clk
= "func_mcbsp2_gfclk",
2014 .clkctrl_offs
= OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET
,
2015 .context_offs
= OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET
,
2016 .modulemode
= MODULEMODE_SWCTRL
,
2019 .opt_clks
= mcbsp2_opt_clks
,
2020 .opt_clks_cnt
= ARRAY_SIZE(mcbsp2_opt_clks
),
2024 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs
[] = {
2025 { .name
= "common", .irq
= 23 + OMAP44XX_IRQ_GIC_START
},
2029 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs
[] = {
2030 { .name
= "tx", .dma_req
= 18 + OMAP44XX_DMA_REQ_START
},
2031 { .name
= "rx", .dma_req
= 19 + OMAP44XX_DMA_REQ_START
},
2035 static struct omap_hwmod_opt_clk mcbsp3_opt_clks
[] = {
2036 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
2037 { .role
= "prcm_fck", .clk
= "mcbsp3_sync_mux_ck" },
2040 static struct omap_hwmod omap44xx_mcbsp3_hwmod
= {
2042 .class = &omap44xx_mcbsp_hwmod_class
,
2043 .clkdm_name
= "abe_clkdm",
2044 .mpu_irqs
= omap44xx_mcbsp3_irqs
,
2045 .sdma_reqs
= omap44xx_mcbsp3_sdma_reqs
,
2046 .main_clk
= "func_mcbsp3_gfclk",
2049 .clkctrl_offs
= OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET
,
2050 .context_offs
= OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET
,
2051 .modulemode
= MODULEMODE_SWCTRL
,
2054 .opt_clks
= mcbsp3_opt_clks
,
2055 .opt_clks_cnt
= ARRAY_SIZE(mcbsp3_opt_clks
),
2059 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs
[] = {
2060 { .name
= "common", .irq
= 16 + OMAP44XX_IRQ_GIC_START
},
2064 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs
[] = {
2065 { .name
= "tx", .dma_req
= 30 + OMAP44XX_DMA_REQ_START
},
2066 { .name
= "rx", .dma_req
= 31 + OMAP44XX_DMA_REQ_START
},
2070 static struct omap_hwmod_opt_clk mcbsp4_opt_clks
[] = {
2071 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
2072 { .role
= "prcm_fck", .clk
= "mcbsp4_sync_mux_ck" },
2075 static struct omap_hwmod omap44xx_mcbsp4_hwmod
= {
2077 .class = &omap44xx_mcbsp_hwmod_class
,
2078 .clkdm_name
= "l4_per_clkdm",
2079 .mpu_irqs
= omap44xx_mcbsp4_irqs
,
2080 .sdma_reqs
= omap44xx_mcbsp4_sdma_reqs
,
2081 .main_clk
= "per_mcbsp4_gfclk",
2084 .clkctrl_offs
= OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET
,
2085 .context_offs
= OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET
,
2086 .modulemode
= MODULEMODE_SWCTRL
,
2089 .opt_clks
= mcbsp4_opt_clks
,
2090 .opt_clks_cnt
= ARRAY_SIZE(mcbsp4_opt_clks
),
2095 * multi channel pdm controller (proprietary interface with phoenix power
2099 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc
= {
2101 .sysc_offs
= 0x0010,
2102 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
2103 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
2104 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2106 .sysc_fields
= &omap_hwmod_sysc_type2
,
2109 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class
= {
2111 .sysc
= &omap44xx_mcpdm_sysc
,
2115 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs
[] = {
2116 { .irq
= 112 + OMAP44XX_IRQ_GIC_START
},
2120 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs
[] = {
2121 { .name
= "up_link", .dma_req
= 64 + OMAP44XX_DMA_REQ_START
},
2122 { .name
= "dn_link", .dma_req
= 65 + OMAP44XX_DMA_REQ_START
},
2126 static struct omap_hwmod omap44xx_mcpdm_hwmod
= {
2128 .class = &omap44xx_mcpdm_hwmod_class
,
2129 .clkdm_name
= "abe_clkdm",
2131 * It's suspected that the McPDM requires an off-chip main
2132 * functional clock, controlled via I2C. This IP block is
2133 * currently reset very early during boot, before I2C is
2134 * available, so it doesn't seem that we have any choice in
2135 * the kernel other than to avoid resetting it.
2137 * Also, McPDM needs to be configured to NO_IDLE mode when it
2138 * is in used otherwise vital clocks will be gated which
2139 * results 'slow motion' audio playback.
2141 .flags
= HWMOD_EXT_OPT_MAIN_CLK
| HWMOD_SWSUP_SIDLE
,
2142 .mpu_irqs
= omap44xx_mcpdm_irqs
,
2143 .sdma_reqs
= omap44xx_mcpdm_sdma_reqs
,
2144 .main_clk
= "pad_clks_ck",
2147 .clkctrl_offs
= OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET
,
2148 .context_offs
= OMAP4_RM_ABE_PDM_CONTEXT_OFFSET
,
2149 .modulemode
= MODULEMODE_SWCTRL
,
2156 * multichannel serial port interface (mcspi) / master/slave synchronous serial
2160 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc
= {
2162 .sysc_offs
= 0x0010,
2163 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
2164 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
2165 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2167 .sysc_fields
= &omap_hwmod_sysc_type2
,
2170 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class
= {
2172 .sysc
= &omap44xx_mcspi_sysc
,
2173 .rev
= OMAP4_MCSPI_REV
,
2177 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs
[] = {
2178 { .irq
= 65 + OMAP44XX_IRQ_GIC_START
},
2182 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs
[] = {
2183 { .name
= "tx0", .dma_req
= 34 + OMAP44XX_DMA_REQ_START
},
2184 { .name
= "rx0", .dma_req
= 35 + OMAP44XX_DMA_REQ_START
},
2185 { .name
= "tx1", .dma_req
= 36 + OMAP44XX_DMA_REQ_START
},
2186 { .name
= "rx1", .dma_req
= 37 + OMAP44XX_DMA_REQ_START
},
2187 { .name
= "tx2", .dma_req
= 38 + OMAP44XX_DMA_REQ_START
},
2188 { .name
= "rx2", .dma_req
= 39 + OMAP44XX_DMA_REQ_START
},
2189 { .name
= "tx3", .dma_req
= 40 + OMAP44XX_DMA_REQ_START
},
2190 { .name
= "rx3", .dma_req
= 41 + OMAP44XX_DMA_REQ_START
},
2194 /* mcspi1 dev_attr */
2195 static struct omap2_mcspi_dev_attr mcspi1_dev_attr
= {
2196 .num_chipselect
= 4,
2199 static struct omap_hwmod omap44xx_mcspi1_hwmod
= {
2201 .class = &omap44xx_mcspi_hwmod_class
,
2202 .clkdm_name
= "l4_per_clkdm",
2203 .mpu_irqs
= omap44xx_mcspi1_irqs
,
2204 .sdma_reqs
= omap44xx_mcspi1_sdma_reqs
,
2205 .main_clk
= "func_48m_fclk",
2208 .clkctrl_offs
= OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET
,
2209 .context_offs
= OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET
,
2210 .modulemode
= MODULEMODE_SWCTRL
,
2213 .dev_attr
= &mcspi1_dev_attr
,
2217 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs
[] = {
2218 { .irq
= 66 + OMAP44XX_IRQ_GIC_START
},
2222 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs
[] = {
2223 { .name
= "tx0", .dma_req
= 42 + OMAP44XX_DMA_REQ_START
},
2224 { .name
= "rx0", .dma_req
= 43 + OMAP44XX_DMA_REQ_START
},
2225 { .name
= "tx1", .dma_req
= 44 + OMAP44XX_DMA_REQ_START
},
2226 { .name
= "rx1", .dma_req
= 45 + OMAP44XX_DMA_REQ_START
},
2230 /* mcspi2 dev_attr */
2231 static struct omap2_mcspi_dev_attr mcspi2_dev_attr
= {
2232 .num_chipselect
= 2,
2235 static struct omap_hwmod omap44xx_mcspi2_hwmod
= {
2237 .class = &omap44xx_mcspi_hwmod_class
,
2238 .clkdm_name
= "l4_per_clkdm",
2239 .mpu_irqs
= omap44xx_mcspi2_irqs
,
2240 .sdma_reqs
= omap44xx_mcspi2_sdma_reqs
,
2241 .main_clk
= "func_48m_fclk",
2244 .clkctrl_offs
= OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET
,
2245 .context_offs
= OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET
,
2246 .modulemode
= MODULEMODE_SWCTRL
,
2249 .dev_attr
= &mcspi2_dev_attr
,
2253 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs
[] = {
2254 { .irq
= 91 + OMAP44XX_IRQ_GIC_START
},
2258 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs
[] = {
2259 { .name
= "tx0", .dma_req
= 14 + OMAP44XX_DMA_REQ_START
},
2260 { .name
= "rx0", .dma_req
= 15 + OMAP44XX_DMA_REQ_START
},
2261 { .name
= "tx1", .dma_req
= 22 + OMAP44XX_DMA_REQ_START
},
2262 { .name
= "rx1", .dma_req
= 23 + OMAP44XX_DMA_REQ_START
},
2266 /* mcspi3 dev_attr */
2267 static struct omap2_mcspi_dev_attr mcspi3_dev_attr
= {
2268 .num_chipselect
= 2,
2271 static struct omap_hwmod omap44xx_mcspi3_hwmod
= {
2273 .class = &omap44xx_mcspi_hwmod_class
,
2274 .clkdm_name
= "l4_per_clkdm",
2275 .mpu_irqs
= omap44xx_mcspi3_irqs
,
2276 .sdma_reqs
= omap44xx_mcspi3_sdma_reqs
,
2277 .main_clk
= "func_48m_fclk",
2280 .clkctrl_offs
= OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET
,
2281 .context_offs
= OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET
,
2282 .modulemode
= MODULEMODE_SWCTRL
,
2285 .dev_attr
= &mcspi3_dev_attr
,
2289 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs
[] = {
2290 { .irq
= 48 + OMAP44XX_IRQ_GIC_START
},
2294 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs
[] = {
2295 { .name
= "tx0", .dma_req
= 69 + OMAP44XX_DMA_REQ_START
},
2296 { .name
= "rx0", .dma_req
= 70 + OMAP44XX_DMA_REQ_START
},
2300 /* mcspi4 dev_attr */
2301 static struct omap2_mcspi_dev_attr mcspi4_dev_attr
= {
2302 .num_chipselect
= 1,
2305 static struct omap_hwmod omap44xx_mcspi4_hwmod
= {
2307 .class = &omap44xx_mcspi_hwmod_class
,
2308 .clkdm_name
= "l4_per_clkdm",
2309 .mpu_irqs
= omap44xx_mcspi4_irqs
,
2310 .sdma_reqs
= omap44xx_mcspi4_sdma_reqs
,
2311 .main_clk
= "func_48m_fclk",
2314 .clkctrl_offs
= OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET
,
2315 .context_offs
= OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET
,
2316 .modulemode
= MODULEMODE_SWCTRL
,
2319 .dev_attr
= &mcspi4_dev_attr
,
2324 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2327 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc
= {
2329 .sysc_offs
= 0x0010,
2330 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_MIDLEMODE
|
2331 SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
2332 SYSC_HAS_SOFTRESET
),
2333 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2334 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
2335 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
2336 .sysc_fields
= &omap_hwmod_sysc_type2
,
2339 static struct omap_hwmod_class omap44xx_mmc_hwmod_class
= {
2341 .sysc
= &omap44xx_mmc_sysc
,
2345 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs
[] = {
2346 { .irq
= 83 + OMAP44XX_IRQ_GIC_START
},
2350 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs
[] = {
2351 { .name
= "tx", .dma_req
= 60 + OMAP44XX_DMA_REQ_START
},
2352 { .name
= "rx", .dma_req
= 61 + OMAP44XX_DMA_REQ_START
},
2357 static struct omap_mmc_dev_attr mmc1_dev_attr
= {
2358 .flags
= OMAP_HSMMC_SUPPORTS_DUAL_VOLT
,
2361 static struct omap_hwmod omap44xx_mmc1_hwmod
= {
2363 .class = &omap44xx_mmc_hwmod_class
,
2364 .clkdm_name
= "l3_init_clkdm",
2365 .mpu_irqs
= omap44xx_mmc1_irqs
,
2366 .sdma_reqs
= omap44xx_mmc1_sdma_reqs
,
2367 .main_clk
= "hsmmc1_fclk",
2370 .clkctrl_offs
= OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET
,
2371 .context_offs
= OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET
,
2372 .modulemode
= MODULEMODE_SWCTRL
,
2375 .dev_attr
= &mmc1_dev_attr
,
2379 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs
[] = {
2380 { .irq
= 86 + OMAP44XX_IRQ_GIC_START
},
2384 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs
[] = {
2385 { .name
= "tx", .dma_req
= 46 + OMAP44XX_DMA_REQ_START
},
2386 { .name
= "rx", .dma_req
= 47 + OMAP44XX_DMA_REQ_START
},
2390 static struct omap_hwmod omap44xx_mmc2_hwmod
= {
2392 .class = &omap44xx_mmc_hwmod_class
,
2393 .clkdm_name
= "l3_init_clkdm",
2394 .mpu_irqs
= omap44xx_mmc2_irqs
,
2395 .sdma_reqs
= omap44xx_mmc2_sdma_reqs
,
2396 .main_clk
= "hsmmc2_fclk",
2399 .clkctrl_offs
= OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET
,
2400 .context_offs
= OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET
,
2401 .modulemode
= MODULEMODE_SWCTRL
,
2407 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs
[] = {
2408 { .irq
= 94 + OMAP44XX_IRQ_GIC_START
},
2412 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs
[] = {
2413 { .name
= "tx", .dma_req
= 76 + OMAP44XX_DMA_REQ_START
},
2414 { .name
= "rx", .dma_req
= 77 + OMAP44XX_DMA_REQ_START
},
2418 static struct omap_hwmod omap44xx_mmc3_hwmod
= {
2420 .class = &omap44xx_mmc_hwmod_class
,
2421 .clkdm_name
= "l4_per_clkdm",
2422 .mpu_irqs
= omap44xx_mmc3_irqs
,
2423 .sdma_reqs
= omap44xx_mmc3_sdma_reqs
,
2424 .main_clk
= "func_48m_fclk",
2427 .clkctrl_offs
= OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET
,
2428 .context_offs
= OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET
,
2429 .modulemode
= MODULEMODE_SWCTRL
,
2435 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs
[] = {
2436 { .irq
= 96 + OMAP44XX_IRQ_GIC_START
},
2440 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs
[] = {
2441 { .name
= "tx", .dma_req
= 56 + OMAP44XX_DMA_REQ_START
},
2442 { .name
= "rx", .dma_req
= 57 + OMAP44XX_DMA_REQ_START
},
2446 static struct omap_hwmod omap44xx_mmc4_hwmod
= {
2448 .class = &omap44xx_mmc_hwmod_class
,
2449 .clkdm_name
= "l4_per_clkdm",
2450 .mpu_irqs
= omap44xx_mmc4_irqs
,
2451 .sdma_reqs
= omap44xx_mmc4_sdma_reqs
,
2452 .main_clk
= "func_48m_fclk",
2455 .clkctrl_offs
= OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET
,
2456 .context_offs
= OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET
,
2457 .modulemode
= MODULEMODE_SWCTRL
,
2463 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs
[] = {
2464 { .irq
= 59 + OMAP44XX_IRQ_GIC_START
},
2468 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs
[] = {
2469 { .name
= "tx", .dma_req
= 58 + OMAP44XX_DMA_REQ_START
},
2470 { .name
= "rx", .dma_req
= 59 + OMAP44XX_DMA_REQ_START
},
2474 static struct omap_hwmod omap44xx_mmc5_hwmod
= {
2476 .class = &omap44xx_mmc_hwmod_class
,
2477 .clkdm_name
= "l4_per_clkdm",
2478 .mpu_irqs
= omap44xx_mmc5_irqs
,
2479 .sdma_reqs
= omap44xx_mmc5_sdma_reqs
,
2480 .main_clk
= "func_48m_fclk",
2483 .clkctrl_offs
= OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET
,
2484 .context_offs
= OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET
,
2485 .modulemode
= MODULEMODE_SWCTRL
,
2492 * The memory management unit performs virtual to physical address translation
2493 * for its requestors.
2496 static struct omap_hwmod_class_sysconfig mmu_sysc
= {
2500 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
2501 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
),
2502 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
2503 .sysc_fields
= &omap_hwmod_sysc_type1
,
2506 static struct omap_hwmod_class omap44xx_mmu_hwmod_class
= {
2513 static struct omap_mmu_dev_attr mmu_ipu_dev_attr
= {
2515 .da_end
= 0xfffff000,
2516 .nr_tlb_entries
= 32,
2519 static struct omap_hwmod omap44xx_mmu_ipu_hwmod
;
2520 static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs
[] = {
2521 { .irq
= 100 + OMAP44XX_IRQ_GIC_START
, },
2525 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets
[] = {
2526 { .name
= "mmu_cache", .rst_shift
= 2 },
2529 static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs
[] = {
2531 .pa_start
= 0x55082000,
2532 .pa_end
= 0x550820ff,
2533 .flags
= ADDR_TYPE_RT
,
2538 /* l3_main_2 -> mmu_ipu */
2539 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu
= {
2540 .master
= &omap44xx_l3_main_2_hwmod
,
2541 .slave
= &omap44xx_mmu_ipu_hwmod
,
2543 .addr
= omap44xx_mmu_ipu_addrs
,
2544 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2547 static struct omap_hwmod omap44xx_mmu_ipu_hwmod
= {
2549 .class = &omap44xx_mmu_hwmod_class
,
2550 .clkdm_name
= "ducati_clkdm",
2551 .mpu_irqs
= omap44xx_mmu_ipu_irqs
,
2552 .rst_lines
= omap44xx_mmu_ipu_resets
,
2553 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_mmu_ipu_resets
),
2554 .main_clk
= "ducati_clk_mux_ck",
2557 .clkctrl_offs
= OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET
,
2558 .rstctrl_offs
= OMAP4_RM_DUCATI_RSTCTRL_OFFSET
,
2559 .context_offs
= OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET
,
2560 .modulemode
= MODULEMODE_HWCTRL
,
2563 .dev_attr
= &mmu_ipu_dev_attr
,
2568 static struct omap_mmu_dev_attr mmu_dsp_dev_attr
= {
2570 .da_end
= 0xfffff000,
2571 .nr_tlb_entries
= 32,
2574 static struct omap_hwmod omap44xx_mmu_dsp_hwmod
;
2575 static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs
[] = {
2576 { .irq
= 28 + OMAP44XX_IRQ_GIC_START
},
2580 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets
[] = {
2581 { .name
= "mmu_cache", .rst_shift
= 1 },
2584 static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs
[] = {
2586 .pa_start
= 0x4a066000,
2587 .pa_end
= 0x4a0660ff,
2588 .flags
= ADDR_TYPE_RT
,
2594 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp
= {
2595 .master
= &omap44xx_l4_cfg_hwmod
,
2596 .slave
= &omap44xx_mmu_dsp_hwmod
,
2598 .addr
= omap44xx_mmu_dsp_addrs
,
2599 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2602 static struct omap_hwmod omap44xx_mmu_dsp_hwmod
= {
2604 .class = &omap44xx_mmu_hwmod_class
,
2605 .clkdm_name
= "tesla_clkdm",
2606 .mpu_irqs
= omap44xx_mmu_dsp_irqs
,
2607 .rst_lines
= omap44xx_mmu_dsp_resets
,
2608 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_mmu_dsp_resets
),
2609 .main_clk
= "dpll_iva_m4x2_ck",
2612 .clkctrl_offs
= OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET
,
2613 .rstctrl_offs
= OMAP4_RM_TESLA_RSTCTRL_OFFSET
,
2614 .context_offs
= OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET
,
2615 .modulemode
= MODULEMODE_HWCTRL
,
2618 .dev_attr
= &mmu_dsp_dev_attr
,
2626 static struct omap_hwmod_class omap44xx_mpu_hwmod_class
= {
2631 static struct omap_hwmod_irq_info omap44xx_mpu_irqs
[] = {
2632 { .name
= "pmu0", .irq
= 54 + OMAP44XX_IRQ_GIC_START
},
2633 { .name
= "pmu1", .irq
= 55 + OMAP44XX_IRQ_GIC_START
},
2634 { .name
= "pl310", .irq
= 0 + OMAP44XX_IRQ_GIC_START
},
2635 { .name
= "cti0", .irq
= 1 + OMAP44XX_IRQ_GIC_START
},
2636 { .name
= "cti1", .irq
= 2 + OMAP44XX_IRQ_GIC_START
},
2640 static struct omap_hwmod omap44xx_mpu_hwmod
= {
2642 .class = &omap44xx_mpu_hwmod_class
,
2643 .clkdm_name
= "mpuss_clkdm",
2644 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
2645 .mpu_irqs
= omap44xx_mpu_irqs
,
2646 .main_clk
= "dpll_mpu_m2_ck",
2649 .clkctrl_offs
= OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET
,
2650 .context_offs
= OMAP4_RM_MPU_MPU_CONTEXT_OFFSET
,
2657 * top-level core on-chip ram
2660 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class
= {
2665 static struct omap_hwmod omap44xx_ocmc_ram_hwmod
= {
2667 .class = &omap44xx_ocmc_ram_hwmod_class
,
2668 .clkdm_name
= "l3_2_clkdm",
2671 .clkctrl_offs
= OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET
,
2672 .context_offs
= OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET
,
2679 * bridge to transform ocp interface protocol to scp (serial control port)
2683 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc
= {
2685 .sysc_offs
= 0x0010,
2686 .syss_offs
= 0x0014,
2687 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SIDLEMODE
|
2688 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
2689 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
2690 .sysc_fields
= &omap_hwmod_sysc_type1
,
2693 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class
= {
2695 .sysc
= &omap44xx_ocp2scp_sysc
,
2698 /* ocp2scp dev_attr */
2699 static struct resource omap44xx_usb_phy_and_pll_addrs
[] = {
2702 .start
= 0x4a0ad080,
2704 .flags
= IORESOURCE_MEM
,
2709 static struct omap_ocp2scp_dev ocp2scp_dev_attr
[] = {
2711 .drv_name
= "omap-usb2",
2712 .res
= omap44xx_usb_phy_and_pll_addrs
,
2717 static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks
[] = {
2718 { .role
= "48mhz", .clk
= "ocp2scp_usb_phy_phy_48m" },
2721 /* ocp2scp_usb_phy */
2722 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod
= {
2723 .name
= "ocp2scp_usb_phy",
2724 .class = &omap44xx_ocp2scp_hwmod_class
,
2725 .clkdm_name
= "l3_init_clkdm",
2726 .main_clk
= "func_48m_fclk",
2729 .clkctrl_offs
= OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET
,
2730 .context_offs
= OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET
,
2731 .modulemode
= MODULEMODE_HWCTRL
,
2734 .dev_attr
= ocp2scp_dev_attr
,
2735 .opt_clks
= ocp2scp_usb_phy_opt_clks
,
2736 .opt_clks_cnt
= ARRAY_SIZE(ocp2scp_usb_phy_opt_clks
),
2741 * power and reset manager (part of the prcm infrastructure) + clock manager 2
2742 * + clock manager 1 (in always on power domain) + local prm in mpu
2745 static struct omap_hwmod_class omap44xx_prcm_hwmod_class
= {
2750 static struct omap_hwmod omap44xx_prcm_mpu_hwmod
= {
2752 .class = &omap44xx_prcm_hwmod_class
,
2753 .clkdm_name
= "l4_wkup_clkdm",
2754 .flags
= HWMOD_NO_IDLEST
,
2757 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
2763 static struct omap_hwmod omap44xx_cm_core_aon_hwmod
= {
2764 .name
= "cm_core_aon",
2765 .class = &omap44xx_prcm_hwmod_class
,
2766 .flags
= HWMOD_NO_IDLEST
,
2769 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
2775 static struct omap_hwmod omap44xx_cm_core_hwmod
= {
2777 .class = &omap44xx_prcm_hwmod_class
,
2778 .flags
= HWMOD_NO_IDLEST
,
2781 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
2787 static struct omap_hwmod_irq_info omap44xx_prm_irqs
[] = {
2788 { .irq
= 11 + OMAP44XX_IRQ_GIC_START
},
2792 static struct omap_hwmod_rst_info omap44xx_prm_resets
[] = {
2793 { .name
= "rst_global_warm_sw", .rst_shift
= 0 },
2794 { .name
= "rst_global_cold_sw", .rst_shift
= 1 },
2797 static struct omap_hwmod omap44xx_prm_hwmod
= {
2799 .class = &omap44xx_prcm_hwmod_class
,
2800 .mpu_irqs
= omap44xx_prm_irqs
,
2801 .rst_lines
= omap44xx_prm_resets
,
2802 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_prm_resets
),
2807 * system clock and reset manager
2810 static struct omap_hwmod_class omap44xx_scrm_hwmod_class
= {
2815 static struct omap_hwmod omap44xx_scrm_hwmod
= {
2817 .class = &omap44xx_scrm_hwmod_class
,
2818 .clkdm_name
= "l4_wkup_clkdm",
2821 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
2828 * shared level 2 memory interface
2831 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class
= {
2836 static struct omap_hwmod omap44xx_sl2if_hwmod
= {
2838 .class = &omap44xx_sl2if_hwmod_class
,
2839 .clkdm_name
= "ivahd_clkdm",
2842 .clkctrl_offs
= OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET
,
2843 .context_offs
= OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET
,
2844 .modulemode
= MODULEMODE_HWCTRL
,
2851 * bidirectional, multi-drop, multi-channel two-line serial interface between
2852 * the device and external components
2855 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc
= {
2857 .sysc_offs
= 0x0010,
2858 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
2859 SYSC_HAS_SOFTRESET
),
2860 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2862 .sysc_fields
= &omap_hwmod_sysc_type2
,
2865 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class
= {
2867 .sysc
= &omap44xx_slimbus_sysc
,
2871 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs
[] = {
2872 { .irq
= 97 + OMAP44XX_IRQ_GIC_START
},
2876 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs
[] = {
2877 { .name
= "tx0", .dma_req
= 84 + OMAP44XX_DMA_REQ_START
},
2878 { .name
= "tx1", .dma_req
= 85 + OMAP44XX_DMA_REQ_START
},
2879 { .name
= "tx2", .dma_req
= 86 + OMAP44XX_DMA_REQ_START
},
2880 { .name
= "tx3", .dma_req
= 87 + OMAP44XX_DMA_REQ_START
},
2881 { .name
= "rx0", .dma_req
= 88 + OMAP44XX_DMA_REQ_START
},
2882 { .name
= "rx1", .dma_req
= 89 + OMAP44XX_DMA_REQ_START
},
2883 { .name
= "rx2", .dma_req
= 90 + OMAP44XX_DMA_REQ_START
},
2884 { .name
= "rx3", .dma_req
= 91 + OMAP44XX_DMA_REQ_START
},
2888 static struct omap_hwmod_opt_clk slimbus1_opt_clks
[] = {
2889 { .role
= "fclk_1", .clk
= "slimbus1_fclk_1" },
2890 { .role
= "fclk_0", .clk
= "slimbus1_fclk_0" },
2891 { .role
= "fclk_2", .clk
= "slimbus1_fclk_2" },
2892 { .role
= "slimbus_clk", .clk
= "slimbus1_slimbus_clk" },
2895 static struct omap_hwmod omap44xx_slimbus1_hwmod
= {
2897 .class = &omap44xx_slimbus_hwmod_class
,
2898 .clkdm_name
= "abe_clkdm",
2899 .mpu_irqs
= omap44xx_slimbus1_irqs
,
2900 .sdma_reqs
= omap44xx_slimbus1_sdma_reqs
,
2903 .clkctrl_offs
= OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET
,
2904 .context_offs
= OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET
,
2905 .modulemode
= MODULEMODE_SWCTRL
,
2908 .opt_clks
= slimbus1_opt_clks
,
2909 .opt_clks_cnt
= ARRAY_SIZE(slimbus1_opt_clks
),
2913 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs
[] = {
2914 { .irq
= 98 + OMAP44XX_IRQ_GIC_START
},
2918 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs
[] = {
2919 { .name
= "tx0", .dma_req
= 92 + OMAP44XX_DMA_REQ_START
},
2920 { .name
= "tx1", .dma_req
= 93 + OMAP44XX_DMA_REQ_START
},
2921 { .name
= "tx2", .dma_req
= 94 + OMAP44XX_DMA_REQ_START
},
2922 { .name
= "tx3", .dma_req
= 95 + OMAP44XX_DMA_REQ_START
},
2923 { .name
= "rx0", .dma_req
= 96 + OMAP44XX_DMA_REQ_START
},
2924 { .name
= "rx1", .dma_req
= 97 + OMAP44XX_DMA_REQ_START
},
2925 { .name
= "rx2", .dma_req
= 98 + OMAP44XX_DMA_REQ_START
},
2926 { .name
= "rx3", .dma_req
= 99 + OMAP44XX_DMA_REQ_START
},
2930 static struct omap_hwmod_opt_clk slimbus2_opt_clks
[] = {
2931 { .role
= "fclk_1", .clk
= "slimbus2_fclk_1" },
2932 { .role
= "fclk_0", .clk
= "slimbus2_fclk_0" },
2933 { .role
= "slimbus_clk", .clk
= "slimbus2_slimbus_clk" },
2936 static struct omap_hwmod omap44xx_slimbus2_hwmod
= {
2938 .class = &omap44xx_slimbus_hwmod_class
,
2939 .clkdm_name
= "l4_per_clkdm",
2940 .mpu_irqs
= omap44xx_slimbus2_irqs
,
2941 .sdma_reqs
= omap44xx_slimbus2_sdma_reqs
,
2944 .clkctrl_offs
= OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET
,
2945 .context_offs
= OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET
,
2946 .modulemode
= MODULEMODE_SWCTRL
,
2949 .opt_clks
= slimbus2_opt_clks
,
2950 .opt_clks_cnt
= ARRAY_SIZE(slimbus2_opt_clks
),
2954 * 'smartreflex' class
2955 * smartreflex module (monitor silicon performance and outputs a measure of
2956 * performance error)
2959 /* The IP is not compliant to type1 / type2 scheme */
2960 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex
= {
2965 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc
= {
2966 .sysc_offs
= 0x0038,
2967 .sysc_flags
= (SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
),
2968 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2970 .sysc_fields
= &omap_hwmod_sysc_type_smartreflex
,
2973 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class
= {
2974 .name
= "smartreflex",
2975 .sysc
= &omap44xx_smartreflex_sysc
,
2979 /* smartreflex_core */
2980 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr
= {
2981 .sensor_voltdm_name
= "core",
2984 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs
[] = {
2985 { .irq
= 19 + OMAP44XX_IRQ_GIC_START
},
2989 static struct omap_hwmod omap44xx_smartreflex_core_hwmod
= {
2990 .name
= "smartreflex_core",
2991 .class = &omap44xx_smartreflex_hwmod_class
,
2992 .clkdm_name
= "l4_ao_clkdm",
2993 .mpu_irqs
= omap44xx_smartreflex_core_irqs
,
2995 .main_clk
= "smartreflex_core_fck",
2998 .clkctrl_offs
= OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET
,
2999 .context_offs
= OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET
,
3000 .modulemode
= MODULEMODE_SWCTRL
,
3003 .dev_attr
= &smartreflex_core_dev_attr
,
3006 /* smartreflex_iva */
3007 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr
= {
3008 .sensor_voltdm_name
= "iva",
3011 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs
[] = {
3012 { .irq
= 102 + OMAP44XX_IRQ_GIC_START
},
3016 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod
= {
3017 .name
= "smartreflex_iva",
3018 .class = &omap44xx_smartreflex_hwmod_class
,
3019 .clkdm_name
= "l4_ao_clkdm",
3020 .mpu_irqs
= omap44xx_smartreflex_iva_irqs
,
3021 .main_clk
= "smartreflex_iva_fck",
3024 .clkctrl_offs
= OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET
,
3025 .context_offs
= OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET
,
3026 .modulemode
= MODULEMODE_SWCTRL
,
3029 .dev_attr
= &smartreflex_iva_dev_attr
,
3032 /* smartreflex_mpu */
3033 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr
= {
3034 .sensor_voltdm_name
= "mpu",
3037 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs
[] = {
3038 { .irq
= 18 + OMAP44XX_IRQ_GIC_START
},
3042 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod
= {
3043 .name
= "smartreflex_mpu",
3044 .class = &omap44xx_smartreflex_hwmod_class
,
3045 .clkdm_name
= "l4_ao_clkdm",
3046 .mpu_irqs
= omap44xx_smartreflex_mpu_irqs
,
3047 .main_clk
= "smartreflex_mpu_fck",
3050 .clkctrl_offs
= OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET
,
3051 .context_offs
= OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET
,
3052 .modulemode
= MODULEMODE_SWCTRL
,
3055 .dev_attr
= &smartreflex_mpu_dev_attr
,
3060 * spinlock provides hardware assistance for synchronizing the processes
3061 * running on multiple processors
3064 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc
= {
3066 .sysc_offs
= 0x0010,
3067 .syss_offs
= 0x0014,
3068 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
3069 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
3070 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
3071 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3073 .sysc_fields
= &omap_hwmod_sysc_type1
,
3076 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class
= {
3078 .sysc
= &omap44xx_spinlock_sysc
,
3082 static struct omap_hwmod omap44xx_spinlock_hwmod
= {
3084 .class = &omap44xx_spinlock_hwmod_class
,
3085 .clkdm_name
= "l4_cfg_clkdm",
3088 .clkctrl_offs
= OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET
,
3089 .context_offs
= OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET
,
3096 * general purpose timer module with accurate 1ms tick
3097 * This class contains several variants: ['timer_1ms', 'timer']
3100 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc
= {
3102 .sysc_offs
= 0x0010,
3103 .syss_offs
= 0x0014,
3104 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
3105 SYSC_HAS_EMUFREE
| SYSC_HAS_ENAWAKEUP
|
3106 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
3107 SYSS_HAS_RESET_STATUS
),
3108 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
3109 .clockact
= CLOCKACT_TEST_ICLK
,
3110 .sysc_fields
= &omap_hwmod_sysc_type1
,
3113 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class
= {
3115 .sysc
= &omap44xx_timer_1ms_sysc
,
3118 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc
= {
3120 .sysc_offs
= 0x0010,
3121 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
3122 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
3123 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3125 .sysc_fields
= &omap_hwmod_sysc_type2
,
3128 static struct omap_hwmod_class omap44xx_timer_hwmod_class
= {
3130 .sysc
= &omap44xx_timer_sysc
,
3133 /* always-on timers dev attribute */
3134 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr
= {
3135 .timer_capability
= OMAP_TIMER_ALWON
,
3138 /* pwm timers dev attribute */
3139 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr
= {
3140 .timer_capability
= OMAP_TIMER_HAS_PWM
,
3143 /* timers with DSP interrupt dev attribute */
3144 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr
= {
3145 .timer_capability
= OMAP_TIMER_HAS_DSP_IRQ
,
3148 /* pwm timers with DSP interrupt dev attribute */
3149 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr
= {
3150 .timer_capability
= OMAP_TIMER_HAS_DSP_IRQ
| OMAP_TIMER_HAS_PWM
,
3154 static struct omap_hwmod_irq_info omap44xx_timer1_irqs
[] = {
3155 { .irq
= 37 + OMAP44XX_IRQ_GIC_START
},
3159 static struct omap_hwmod omap44xx_timer1_hwmod
= {
3161 .class = &omap44xx_timer_1ms_hwmod_class
,
3162 .clkdm_name
= "l4_wkup_clkdm",
3163 .flags
= HWMOD_SET_DEFAULT_CLOCKACT
,
3164 .mpu_irqs
= omap44xx_timer1_irqs
,
3165 .main_clk
= "dmt1_clk_mux",
3168 .clkctrl_offs
= OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET
,
3169 .context_offs
= OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET
,
3170 .modulemode
= MODULEMODE_SWCTRL
,
3173 .dev_attr
= &capability_alwon_dev_attr
,
3177 static struct omap_hwmod_irq_info omap44xx_timer2_irqs
[] = {
3178 { .irq
= 38 + OMAP44XX_IRQ_GIC_START
},
3182 static struct omap_hwmod omap44xx_timer2_hwmod
= {
3184 .class = &omap44xx_timer_1ms_hwmod_class
,
3185 .clkdm_name
= "l4_per_clkdm",
3186 .flags
= HWMOD_SET_DEFAULT_CLOCKACT
,
3187 .mpu_irqs
= omap44xx_timer2_irqs
,
3188 .main_clk
= "cm2_dm2_mux",
3191 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET
,
3192 .context_offs
= OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET
,
3193 .modulemode
= MODULEMODE_SWCTRL
,
3199 static struct omap_hwmod_irq_info omap44xx_timer3_irqs
[] = {
3200 { .irq
= 39 + OMAP44XX_IRQ_GIC_START
},
3204 static struct omap_hwmod omap44xx_timer3_hwmod
= {
3206 .class = &omap44xx_timer_hwmod_class
,
3207 .clkdm_name
= "l4_per_clkdm",
3208 .mpu_irqs
= omap44xx_timer3_irqs
,
3209 .main_clk
= "cm2_dm3_mux",
3212 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET
,
3213 .context_offs
= OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET
,
3214 .modulemode
= MODULEMODE_SWCTRL
,
3220 static struct omap_hwmod_irq_info omap44xx_timer4_irqs
[] = {
3221 { .irq
= 40 + OMAP44XX_IRQ_GIC_START
},
3225 static struct omap_hwmod omap44xx_timer4_hwmod
= {
3227 .class = &omap44xx_timer_hwmod_class
,
3228 .clkdm_name
= "l4_per_clkdm",
3229 .mpu_irqs
= omap44xx_timer4_irqs
,
3230 .main_clk
= "cm2_dm4_mux",
3233 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET
,
3234 .context_offs
= OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET
,
3235 .modulemode
= MODULEMODE_SWCTRL
,
3241 static struct omap_hwmod_irq_info omap44xx_timer5_irqs
[] = {
3242 { .irq
= 41 + OMAP44XX_IRQ_GIC_START
},
3246 static struct omap_hwmod omap44xx_timer5_hwmod
= {
3248 .class = &omap44xx_timer_hwmod_class
,
3249 .clkdm_name
= "abe_clkdm",
3250 .mpu_irqs
= omap44xx_timer5_irqs
,
3251 .main_clk
= "timer5_sync_mux",
3254 .clkctrl_offs
= OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET
,
3255 .context_offs
= OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET
,
3256 .modulemode
= MODULEMODE_SWCTRL
,
3259 .dev_attr
= &capability_dsp_dev_attr
,
3263 static struct omap_hwmod_irq_info omap44xx_timer6_irqs
[] = {
3264 { .irq
= 42 + OMAP44XX_IRQ_GIC_START
},
3268 static struct omap_hwmod omap44xx_timer6_hwmod
= {
3270 .class = &omap44xx_timer_hwmod_class
,
3271 .clkdm_name
= "abe_clkdm",
3272 .mpu_irqs
= omap44xx_timer6_irqs
,
3273 .main_clk
= "timer6_sync_mux",
3276 .clkctrl_offs
= OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET
,
3277 .context_offs
= OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET
,
3278 .modulemode
= MODULEMODE_SWCTRL
,
3281 .dev_attr
= &capability_dsp_dev_attr
,
3285 static struct omap_hwmod_irq_info omap44xx_timer7_irqs
[] = {
3286 { .irq
= 43 + OMAP44XX_IRQ_GIC_START
},
3290 static struct omap_hwmod omap44xx_timer7_hwmod
= {
3292 .class = &omap44xx_timer_hwmod_class
,
3293 .clkdm_name
= "abe_clkdm",
3294 .mpu_irqs
= omap44xx_timer7_irqs
,
3295 .main_clk
= "timer7_sync_mux",
3298 .clkctrl_offs
= OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET
,
3299 .context_offs
= OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET
,
3300 .modulemode
= MODULEMODE_SWCTRL
,
3303 .dev_attr
= &capability_dsp_dev_attr
,
3307 static struct omap_hwmod_irq_info omap44xx_timer8_irqs
[] = {
3308 { .irq
= 44 + OMAP44XX_IRQ_GIC_START
},
3312 static struct omap_hwmod omap44xx_timer8_hwmod
= {
3314 .class = &omap44xx_timer_hwmod_class
,
3315 .clkdm_name
= "abe_clkdm",
3316 .mpu_irqs
= omap44xx_timer8_irqs
,
3317 .main_clk
= "timer8_sync_mux",
3320 .clkctrl_offs
= OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET
,
3321 .context_offs
= OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET
,
3322 .modulemode
= MODULEMODE_SWCTRL
,
3325 .dev_attr
= &capability_dsp_pwm_dev_attr
,
3329 static struct omap_hwmod_irq_info omap44xx_timer9_irqs
[] = {
3330 { .irq
= 45 + OMAP44XX_IRQ_GIC_START
},
3334 static struct omap_hwmod omap44xx_timer9_hwmod
= {
3336 .class = &omap44xx_timer_hwmod_class
,
3337 .clkdm_name
= "l4_per_clkdm",
3338 .mpu_irqs
= omap44xx_timer9_irqs
,
3339 .main_clk
= "cm2_dm9_mux",
3342 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET
,
3343 .context_offs
= OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET
,
3344 .modulemode
= MODULEMODE_SWCTRL
,
3347 .dev_attr
= &capability_pwm_dev_attr
,
3351 static struct omap_hwmod_irq_info omap44xx_timer10_irqs
[] = {
3352 { .irq
= 46 + OMAP44XX_IRQ_GIC_START
},
3356 static struct omap_hwmod omap44xx_timer10_hwmod
= {
3358 .class = &omap44xx_timer_1ms_hwmod_class
,
3359 .clkdm_name
= "l4_per_clkdm",
3360 .flags
= HWMOD_SET_DEFAULT_CLOCKACT
,
3361 .mpu_irqs
= omap44xx_timer10_irqs
,
3362 .main_clk
= "cm2_dm10_mux",
3365 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET
,
3366 .context_offs
= OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET
,
3367 .modulemode
= MODULEMODE_SWCTRL
,
3370 .dev_attr
= &capability_pwm_dev_attr
,
3374 static struct omap_hwmod_irq_info omap44xx_timer11_irqs
[] = {
3375 { .irq
= 47 + OMAP44XX_IRQ_GIC_START
},
3379 static struct omap_hwmod omap44xx_timer11_hwmod
= {
3381 .class = &omap44xx_timer_hwmod_class
,
3382 .clkdm_name
= "l4_per_clkdm",
3383 .mpu_irqs
= omap44xx_timer11_irqs
,
3384 .main_clk
= "cm2_dm11_mux",
3387 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET
,
3388 .context_offs
= OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET
,
3389 .modulemode
= MODULEMODE_SWCTRL
,
3392 .dev_attr
= &capability_pwm_dev_attr
,
3397 * universal asynchronous receiver/transmitter (uart)
3400 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc
= {
3402 .sysc_offs
= 0x0054,
3403 .syss_offs
= 0x0058,
3404 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
3405 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
3406 SYSS_HAS_RESET_STATUS
),
3407 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3409 .sysc_fields
= &omap_hwmod_sysc_type1
,
3412 static struct omap_hwmod_class omap44xx_uart_hwmod_class
= {
3414 .sysc
= &omap44xx_uart_sysc
,
3418 static struct omap_hwmod_irq_info omap44xx_uart1_irqs
[] = {
3419 { .irq
= 72 + OMAP44XX_IRQ_GIC_START
},
3423 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs
[] = {
3424 { .name
= "tx", .dma_req
= 48 + OMAP44XX_DMA_REQ_START
},
3425 { .name
= "rx", .dma_req
= 49 + OMAP44XX_DMA_REQ_START
},
3429 static struct omap_hwmod omap44xx_uart1_hwmod
= {
3431 .class = &omap44xx_uart_hwmod_class
,
3432 .clkdm_name
= "l4_per_clkdm",
3433 .mpu_irqs
= omap44xx_uart1_irqs
,
3434 .sdma_reqs
= omap44xx_uart1_sdma_reqs
,
3435 .main_clk
= "func_48m_fclk",
3438 .clkctrl_offs
= OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET
,
3439 .context_offs
= OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET
,
3440 .modulemode
= MODULEMODE_SWCTRL
,
3446 static struct omap_hwmod_irq_info omap44xx_uart2_irqs
[] = {
3447 { .irq
= 73 + OMAP44XX_IRQ_GIC_START
},
3451 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs
[] = {
3452 { .name
= "tx", .dma_req
= 50 + OMAP44XX_DMA_REQ_START
},
3453 { .name
= "rx", .dma_req
= 51 + OMAP44XX_DMA_REQ_START
},
3457 static struct omap_hwmod omap44xx_uart2_hwmod
= {
3459 .class = &omap44xx_uart_hwmod_class
,
3460 .clkdm_name
= "l4_per_clkdm",
3461 .mpu_irqs
= omap44xx_uart2_irqs
,
3462 .sdma_reqs
= omap44xx_uart2_sdma_reqs
,
3463 .main_clk
= "func_48m_fclk",
3466 .clkctrl_offs
= OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET
,
3467 .context_offs
= OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET
,
3468 .modulemode
= MODULEMODE_SWCTRL
,
3474 static struct omap_hwmod_irq_info omap44xx_uart3_irqs
[] = {
3475 { .irq
= 74 + OMAP44XX_IRQ_GIC_START
},
3479 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs
[] = {
3480 { .name
= "tx", .dma_req
= 52 + OMAP44XX_DMA_REQ_START
},
3481 { .name
= "rx", .dma_req
= 53 + OMAP44XX_DMA_REQ_START
},
3485 static struct omap_hwmod omap44xx_uart3_hwmod
= {
3487 .class = &omap44xx_uart_hwmod_class
,
3488 .clkdm_name
= "l4_per_clkdm",
3489 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
3490 .mpu_irqs
= omap44xx_uart3_irqs
,
3491 .sdma_reqs
= omap44xx_uart3_sdma_reqs
,
3492 .main_clk
= "func_48m_fclk",
3495 .clkctrl_offs
= OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET
,
3496 .context_offs
= OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET
,
3497 .modulemode
= MODULEMODE_SWCTRL
,
3503 static struct omap_hwmod_irq_info omap44xx_uart4_irqs
[] = {
3504 { .irq
= 70 + OMAP44XX_IRQ_GIC_START
},
3508 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs
[] = {
3509 { .name
= "tx", .dma_req
= 54 + OMAP44XX_DMA_REQ_START
},
3510 { .name
= "rx", .dma_req
= 55 + OMAP44XX_DMA_REQ_START
},
3514 static struct omap_hwmod omap44xx_uart4_hwmod
= {
3516 .class = &omap44xx_uart_hwmod_class
,
3517 .clkdm_name
= "l4_per_clkdm",
3518 .mpu_irqs
= omap44xx_uart4_irqs
,
3519 .sdma_reqs
= omap44xx_uart4_sdma_reqs
,
3520 .main_clk
= "func_48m_fclk",
3523 .clkctrl_offs
= OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET
,
3524 .context_offs
= OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET
,
3525 .modulemode
= MODULEMODE_SWCTRL
,
3531 * 'usb_host_fs' class
3532 * full-speed usb host controller
3535 /* The IP is not compliant to type1 / type2 scheme */
3536 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs
= {
3542 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc
= {
3544 .sysc_offs
= 0x0210,
3545 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
|
3546 SYSC_HAS_SOFTRESET
),
3547 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3549 .sysc_fields
= &omap_hwmod_sysc_type_usb_host_fs
,
3552 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class
= {
3553 .name
= "usb_host_fs",
3554 .sysc
= &omap44xx_usb_host_fs_sysc
,
3558 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs
[] = {
3559 { .name
= "std", .irq
= 89 + OMAP44XX_IRQ_GIC_START
},
3560 { .name
= "smi", .irq
= 90 + OMAP44XX_IRQ_GIC_START
},
3564 static struct omap_hwmod omap44xx_usb_host_fs_hwmod
= {
3565 .name
= "usb_host_fs",
3566 .class = &omap44xx_usb_host_fs_hwmod_class
,
3567 .clkdm_name
= "l3_init_clkdm",
3568 .mpu_irqs
= omap44xx_usb_host_fs_irqs
,
3569 .main_clk
= "usb_host_fs_fck",
3572 .clkctrl_offs
= OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET
,
3573 .context_offs
= OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET
,
3574 .modulemode
= MODULEMODE_SWCTRL
,
3580 * 'usb_host_hs' class
3581 * high-speed multi-port usb host controller
3584 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc
= {
3586 .sysc_offs
= 0x0010,
3587 .syss_offs
= 0x0014,
3588 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
|
3589 SYSC_HAS_SOFTRESET
),
3590 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3591 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
3592 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
3593 .sysc_fields
= &omap_hwmod_sysc_type2
,
3596 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class
= {
3597 .name
= "usb_host_hs",
3598 .sysc
= &omap44xx_usb_host_hs_sysc
,
3602 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs
[] = {
3603 { .name
= "ohci-irq", .irq
= 76 + OMAP44XX_IRQ_GIC_START
},
3604 { .name
= "ehci-irq", .irq
= 77 + OMAP44XX_IRQ_GIC_START
},
3608 static struct omap_hwmod omap44xx_usb_host_hs_hwmod
= {
3609 .name
= "usb_host_hs",
3610 .class = &omap44xx_usb_host_hs_hwmod_class
,
3611 .clkdm_name
= "l3_init_clkdm",
3612 .main_clk
= "usb_host_hs_fck",
3615 .clkctrl_offs
= OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET
,
3616 .context_offs
= OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET
,
3617 .modulemode
= MODULEMODE_SWCTRL
,
3620 .mpu_irqs
= omap44xx_usb_host_hs_irqs
,
3623 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3627 * In the following configuration :
3628 * - USBHOST module is set to smart-idle mode
3629 * - PRCM asserts idle_req to the USBHOST module ( This typically
3630 * happens when the system is going to a low power mode : all ports
3631 * have been suspended, the master part of the USBHOST module has
3632 * entered the standby state, and SW has cut the functional clocks)
3633 * - an USBHOST interrupt occurs before the module is able to answer
3634 * idle_ack, typically a remote wakeup IRQ.
3635 * Then the USB HOST module will enter a deadlock situation where it
3636 * is no more accessible nor functional.
3639 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3643 * Errata: USB host EHCI may stall when entering smart-standby mode
3647 * When the USBHOST module is set to smart-standby mode, and when it is
3648 * ready to enter the standby state (i.e. all ports are suspended and
3649 * all attached devices are in suspend mode), then it can wrongly assert
3650 * the Mstandby signal too early while there are still some residual OCP
3651 * transactions ongoing. If this condition occurs, the internal state
3652 * machine may go to an undefined state and the USB link may be stuck
3653 * upon the next resume.
3656 * Don't use smart standby; use only force standby,
3657 * hence HWMOD_SWSUP_MSTANDBY
3661 * During system boot; If the hwmod framework resets the module
3662 * the module will have smart idle settings; which can lead to deadlock
3663 * (above Errata Id:i660); so, dont reset the module during boot;
3664 * Use HWMOD_INIT_NO_RESET.
3667 .flags
= HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
|
3668 HWMOD_INIT_NO_RESET
,
3672 * 'usb_otg_hs' class
3673 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3676 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc
= {
3678 .sysc_offs
= 0x0404,
3679 .syss_offs
= 0x0408,
3680 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
3681 SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
|
3682 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
3683 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3684 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
3686 .sysc_fields
= &omap_hwmod_sysc_type1
,
3689 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class
= {
3690 .name
= "usb_otg_hs",
3691 .sysc
= &omap44xx_usb_otg_hs_sysc
,
3695 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs
[] = {
3696 { .name
= "mc", .irq
= 92 + OMAP44XX_IRQ_GIC_START
},
3697 { .name
= "dma", .irq
= 93 + OMAP44XX_IRQ_GIC_START
},
3701 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks
[] = {
3702 { .role
= "xclk", .clk
= "usb_otg_hs_xclk" },
3705 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod
= {
3706 .name
= "usb_otg_hs",
3707 .class = &omap44xx_usb_otg_hs_hwmod_class
,
3708 .clkdm_name
= "l3_init_clkdm",
3709 .flags
= HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
,
3710 .mpu_irqs
= omap44xx_usb_otg_hs_irqs
,
3711 .main_clk
= "usb_otg_hs_ick",
3714 .clkctrl_offs
= OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET
,
3715 .context_offs
= OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET
,
3716 .modulemode
= MODULEMODE_HWCTRL
,
3719 .opt_clks
= usb_otg_hs_opt_clks
,
3720 .opt_clks_cnt
= ARRAY_SIZE(usb_otg_hs_opt_clks
),
3724 * 'usb_tll_hs' class
3725 * usb_tll_hs module is the adapter on the usb_host_hs ports
3728 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc
= {
3730 .sysc_offs
= 0x0010,
3731 .syss_offs
= 0x0014,
3732 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
3733 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
3735 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
3736 .sysc_fields
= &omap_hwmod_sysc_type1
,
3739 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class
= {
3740 .name
= "usb_tll_hs",
3741 .sysc
= &omap44xx_usb_tll_hs_sysc
,
3744 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs
[] = {
3745 { .name
= "tll-irq", .irq
= 78 + OMAP44XX_IRQ_GIC_START
},
3749 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod
= {
3750 .name
= "usb_tll_hs",
3751 .class = &omap44xx_usb_tll_hs_hwmod_class
,
3752 .clkdm_name
= "l3_init_clkdm",
3753 .mpu_irqs
= omap44xx_usb_tll_hs_irqs
,
3754 .main_clk
= "usb_tll_hs_ick",
3757 .clkctrl_offs
= OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET
,
3758 .context_offs
= OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET
,
3759 .modulemode
= MODULEMODE_HWCTRL
,
3766 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3767 * overflow condition
3770 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc
= {
3772 .sysc_offs
= 0x0010,
3773 .syss_offs
= 0x0014,
3774 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_SIDLEMODE
|
3775 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
3776 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3778 .sysc_fields
= &omap_hwmod_sysc_type1
,
3781 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class
= {
3783 .sysc
= &omap44xx_wd_timer_sysc
,
3784 .pre_shutdown
= &omap2_wd_timer_disable
,
3785 .reset
= &omap2_wd_timer_reset
,
3789 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs
[] = {
3790 { .irq
= 80 + OMAP44XX_IRQ_GIC_START
},
3794 static struct omap_hwmod omap44xx_wd_timer2_hwmod
= {
3795 .name
= "wd_timer2",
3796 .class = &omap44xx_wd_timer_hwmod_class
,
3797 .clkdm_name
= "l4_wkup_clkdm",
3798 .mpu_irqs
= omap44xx_wd_timer2_irqs
,
3799 .main_clk
= "sys_32k_ck",
3802 .clkctrl_offs
= OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET
,
3803 .context_offs
= OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET
,
3804 .modulemode
= MODULEMODE_SWCTRL
,
3810 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs
[] = {
3811 { .irq
= 36 + OMAP44XX_IRQ_GIC_START
},
3815 static struct omap_hwmod omap44xx_wd_timer3_hwmod
= {
3816 .name
= "wd_timer3",
3817 .class = &omap44xx_wd_timer_hwmod_class
,
3818 .clkdm_name
= "abe_clkdm",
3819 .mpu_irqs
= omap44xx_wd_timer3_irqs
,
3820 .main_clk
= "sys_32k_ck",
3823 .clkctrl_offs
= OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET
,
3824 .context_offs
= OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET
,
3825 .modulemode
= MODULEMODE_SWCTRL
,
3835 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs
[] = {
3837 .pa_start
= 0x4a204000,
3838 .pa_end
= 0x4a2040ff,
3839 .flags
= ADDR_TYPE_RT
3844 /* c2c -> c2c_target_fw */
3845 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw
= {
3846 .master
= &omap44xx_c2c_hwmod
,
3847 .slave
= &omap44xx_c2c_target_fw_hwmod
,
3848 .clk
= "div_core_ck",
3849 .addr
= omap44xx_c2c_target_fw_addrs
,
3850 .user
= OCP_USER_MPU
,
3853 /* l4_cfg -> c2c_target_fw */
3854 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw
= {
3855 .master
= &omap44xx_l4_cfg_hwmod
,
3856 .slave
= &omap44xx_c2c_target_fw_hwmod
,
3858 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3861 /* l3_main_1 -> dmm */
3862 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm
= {
3863 .master
= &omap44xx_l3_main_1_hwmod
,
3864 .slave
= &omap44xx_dmm_hwmod
,
3866 .user
= OCP_USER_SDMA
,
3869 static struct omap_hwmod_addr_space omap44xx_dmm_addrs
[] = {
3871 .pa_start
= 0x4e000000,
3872 .pa_end
= 0x4e0007ff,
3873 .flags
= ADDR_TYPE_RT
3879 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm
= {
3880 .master
= &omap44xx_mpu_hwmod
,
3881 .slave
= &omap44xx_dmm_hwmod
,
3883 .addr
= omap44xx_dmm_addrs
,
3884 .user
= OCP_USER_MPU
,
3887 /* c2c -> emif_fw */
3888 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw
= {
3889 .master
= &omap44xx_c2c_hwmod
,
3890 .slave
= &omap44xx_emif_fw_hwmod
,
3891 .clk
= "div_core_ck",
3892 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3895 /* dmm -> emif_fw */
3896 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw
= {
3897 .master
= &omap44xx_dmm_hwmod
,
3898 .slave
= &omap44xx_emif_fw_hwmod
,
3900 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3903 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs
[] = {
3905 .pa_start
= 0x4a20c000,
3906 .pa_end
= 0x4a20c0ff,
3907 .flags
= ADDR_TYPE_RT
3912 /* l4_cfg -> emif_fw */
3913 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw
= {
3914 .master
= &omap44xx_l4_cfg_hwmod
,
3915 .slave
= &omap44xx_emif_fw_hwmod
,
3917 .addr
= omap44xx_emif_fw_addrs
,
3918 .user
= OCP_USER_MPU
,
3921 /* iva -> l3_instr */
3922 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr
= {
3923 .master
= &omap44xx_iva_hwmod
,
3924 .slave
= &omap44xx_l3_instr_hwmod
,
3926 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3929 /* l3_main_3 -> l3_instr */
3930 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr
= {
3931 .master
= &omap44xx_l3_main_3_hwmod
,
3932 .slave
= &omap44xx_l3_instr_hwmod
,
3934 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3937 /* ocp_wp_noc -> l3_instr */
3938 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr
= {
3939 .master
= &omap44xx_ocp_wp_noc_hwmod
,
3940 .slave
= &omap44xx_l3_instr_hwmod
,
3942 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3945 /* dsp -> l3_main_1 */
3946 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1
= {
3947 .master
= &omap44xx_dsp_hwmod
,
3948 .slave
= &omap44xx_l3_main_1_hwmod
,
3950 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3953 /* dss -> l3_main_1 */
3954 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1
= {
3955 .master
= &omap44xx_dss_hwmod
,
3956 .slave
= &omap44xx_l3_main_1_hwmod
,
3958 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3961 /* l3_main_2 -> l3_main_1 */
3962 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1
= {
3963 .master
= &omap44xx_l3_main_2_hwmod
,
3964 .slave
= &omap44xx_l3_main_1_hwmod
,
3966 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3969 /* l4_cfg -> l3_main_1 */
3970 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1
= {
3971 .master
= &omap44xx_l4_cfg_hwmod
,
3972 .slave
= &omap44xx_l3_main_1_hwmod
,
3974 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3977 /* mmc1 -> l3_main_1 */
3978 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1
= {
3979 .master
= &omap44xx_mmc1_hwmod
,
3980 .slave
= &omap44xx_l3_main_1_hwmod
,
3982 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3985 /* mmc2 -> l3_main_1 */
3986 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1
= {
3987 .master
= &omap44xx_mmc2_hwmod
,
3988 .slave
= &omap44xx_l3_main_1_hwmod
,
3990 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3993 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs
[] = {
3995 .pa_start
= 0x44000000,
3996 .pa_end
= 0x44000fff,
3997 .flags
= ADDR_TYPE_RT
4002 /* mpu -> l3_main_1 */
4003 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1
= {
4004 .master
= &omap44xx_mpu_hwmod
,
4005 .slave
= &omap44xx_l3_main_1_hwmod
,
4007 .addr
= omap44xx_l3_main_1_addrs
,
4008 .user
= OCP_USER_MPU
,
4011 /* c2c_target_fw -> l3_main_2 */
4012 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2
= {
4013 .master
= &omap44xx_c2c_target_fw_hwmod
,
4014 .slave
= &omap44xx_l3_main_2_hwmod
,
4016 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4019 /* debugss -> l3_main_2 */
4020 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2
= {
4021 .master
= &omap44xx_debugss_hwmod
,
4022 .slave
= &omap44xx_l3_main_2_hwmod
,
4023 .clk
= "dbgclk_mux_ck",
4024 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4027 /* dma_system -> l3_main_2 */
4028 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2
= {
4029 .master
= &omap44xx_dma_system_hwmod
,
4030 .slave
= &omap44xx_l3_main_2_hwmod
,
4032 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4035 /* fdif -> l3_main_2 */
4036 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2
= {
4037 .master
= &omap44xx_fdif_hwmod
,
4038 .slave
= &omap44xx_l3_main_2_hwmod
,
4040 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4043 /* gpu -> l3_main_2 */
4044 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2
= {
4045 .master
= &omap44xx_gpu_hwmod
,
4046 .slave
= &omap44xx_l3_main_2_hwmod
,
4048 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4051 /* hsi -> l3_main_2 */
4052 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2
= {
4053 .master
= &omap44xx_hsi_hwmod
,
4054 .slave
= &omap44xx_l3_main_2_hwmod
,
4056 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4059 /* ipu -> l3_main_2 */
4060 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2
= {
4061 .master
= &omap44xx_ipu_hwmod
,
4062 .slave
= &omap44xx_l3_main_2_hwmod
,
4064 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4067 /* iss -> l3_main_2 */
4068 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2
= {
4069 .master
= &omap44xx_iss_hwmod
,
4070 .slave
= &omap44xx_l3_main_2_hwmod
,
4072 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4075 /* iva -> l3_main_2 */
4076 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2
= {
4077 .master
= &omap44xx_iva_hwmod
,
4078 .slave
= &omap44xx_l3_main_2_hwmod
,
4080 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4083 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs
[] = {
4085 .pa_start
= 0x44800000,
4086 .pa_end
= 0x44801fff,
4087 .flags
= ADDR_TYPE_RT
4092 /* l3_main_1 -> l3_main_2 */
4093 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2
= {
4094 .master
= &omap44xx_l3_main_1_hwmod
,
4095 .slave
= &omap44xx_l3_main_2_hwmod
,
4097 .addr
= omap44xx_l3_main_2_addrs
,
4098 .user
= OCP_USER_MPU
,
4101 /* l4_cfg -> l3_main_2 */
4102 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2
= {
4103 .master
= &omap44xx_l4_cfg_hwmod
,
4104 .slave
= &omap44xx_l3_main_2_hwmod
,
4106 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4109 /* usb_host_fs -> l3_main_2 */
4110 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2
= {
4111 .master
= &omap44xx_usb_host_fs_hwmod
,
4112 .slave
= &omap44xx_l3_main_2_hwmod
,
4114 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4117 /* usb_host_hs -> l3_main_2 */
4118 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2
= {
4119 .master
= &omap44xx_usb_host_hs_hwmod
,
4120 .slave
= &omap44xx_l3_main_2_hwmod
,
4122 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4125 /* usb_otg_hs -> l3_main_2 */
4126 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2
= {
4127 .master
= &omap44xx_usb_otg_hs_hwmod
,
4128 .slave
= &omap44xx_l3_main_2_hwmod
,
4130 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4133 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs
[] = {
4135 .pa_start
= 0x45000000,
4136 .pa_end
= 0x45000fff,
4137 .flags
= ADDR_TYPE_RT
4142 /* l3_main_1 -> l3_main_3 */
4143 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3
= {
4144 .master
= &omap44xx_l3_main_1_hwmod
,
4145 .slave
= &omap44xx_l3_main_3_hwmod
,
4147 .addr
= omap44xx_l3_main_3_addrs
,
4148 .user
= OCP_USER_MPU
,
4151 /* l3_main_2 -> l3_main_3 */
4152 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3
= {
4153 .master
= &omap44xx_l3_main_2_hwmod
,
4154 .slave
= &omap44xx_l3_main_3_hwmod
,
4156 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4159 /* l4_cfg -> l3_main_3 */
4160 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3
= {
4161 .master
= &omap44xx_l4_cfg_hwmod
,
4162 .slave
= &omap44xx_l3_main_3_hwmod
,
4164 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4167 /* aess -> l4_abe */
4168 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe
= {
4169 .master
= &omap44xx_aess_hwmod
,
4170 .slave
= &omap44xx_l4_abe_hwmod
,
4171 .clk
= "ocp_abe_iclk",
4172 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4176 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe
= {
4177 .master
= &omap44xx_dsp_hwmod
,
4178 .slave
= &omap44xx_l4_abe_hwmod
,
4179 .clk
= "ocp_abe_iclk",
4180 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4183 /* l3_main_1 -> l4_abe */
4184 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe
= {
4185 .master
= &omap44xx_l3_main_1_hwmod
,
4186 .slave
= &omap44xx_l4_abe_hwmod
,
4188 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4192 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe
= {
4193 .master
= &omap44xx_mpu_hwmod
,
4194 .slave
= &omap44xx_l4_abe_hwmod
,
4195 .clk
= "ocp_abe_iclk",
4196 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4199 /* l3_main_1 -> l4_cfg */
4200 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg
= {
4201 .master
= &omap44xx_l3_main_1_hwmod
,
4202 .slave
= &omap44xx_l4_cfg_hwmod
,
4204 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4207 /* l3_main_2 -> l4_per */
4208 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per
= {
4209 .master
= &omap44xx_l3_main_2_hwmod
,
4210 .slave
= &omap44xx_l4_per_hwmod
,
4212 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4215 /* l4_cfg -> l4_wkup */
4216 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup
= {
4217 .master
= &omap44xx_l4_cfg_hwmod
,
4218 .slave
= &omap44xx_l4_wkup_hwmod
,
4220 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4223 /* mpu -> mpu_private */
4224 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private
= {
4225 .master
= &omap44xx_mpu_hwmod
,
4226 .slave
= &omap44xx_mpu_private_hwmod
,
4228 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4231 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs
[] = {
4233 .pa_start
= 0x4a102000,
4234 .pa_end
= 0x4a10207f,
4235 .flags
= ADDR_TYPE_RT
4240 /* l4_cfg -> ocp_wp_noc */
4241 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc
= {
4242 .master
= &omap44xx_l4_cfg_hwmod
,
4243 .slave
= &omap44xx_ocp_wp_noc_hwmod
,
4245 .addr
= omap44xx_ocp_wp_noc_addrs
,
4246 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4249 static struct omap_hwmod_addr_space omap44xx_aess_addrs
[] = {
4252 .pa_start
= 0x40180000,
4253 .pa_end
= 0x4018ffff
4257 .pa_start
= 0x401a0000,
4258 .pa_end
= 0x401a1fff
4262 .pa_start
= 0x401c0000,
4263 .pa_end
= 0x401c5fff
4267 .pa_start
= 0x401e0000,
4268 .pa_end
= 0x401e1fff
4272 .pa_start
= 0x401f1000,
4273 .pa_end
= 0x401f13ff,
4274 .flags
= ADDR_TYPE_RT
4279 /* l4_abe -> aess */
4280 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess
= {
4281 .master
= &omap44xx_l4_abe_hwmod
,
4282 .slave
= &omap44xx_aess_hwmod
,
4283 .clk
= "ocp_abe_iclk",
4284 .addr
= omap44xx_aess_addrs
,
4285 .user
= OCP_USER_MPU
,
4288 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs
[] = {
4291 .pa_start
= 0x49080000,
4292 .pa_end
= 0x4908ffff
4296 .pa_start
= 0x490a0000,
4297 .pa_end
= 0x490a1fff
4301 .pa_start
= 0x490c0000,
4302 .pa_end
= 0x490c5fff
4306 .pa_start
= 0x490e0000,
4307 .pa_end
= 0x490e1fff
4311 .pa_start
= 0x490f1000,
4312 .pa_end
= 0x490f13ff,
4313 .flags
= ADDR_TYPE_RT
4318 /* l4_abe -> aess (dma) */
4319 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma
= {
4320 .master
= &omap44xx_l4_abe_hwmod
,
4321 .slave
= &omap44xx_aess_hwmod
,
4322 .clk
= "ocp_abe_iclk",
4323 .addr
= omap44xx_aess_dma_addrs
,
4324 .user
= OCP_USER_SDMA
,
4327 /* l3_main_2 -> c2c */
4328 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c
= {
4329 .master
= &omap44xx_l3_main_2_hwmod
,
4330 .slave
= &omap44xx_c2c_hwmod
,
4332 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4335 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs
[] = {
4337 .pa_start
= 0x4a304000,
4338 .pa_end
= 0x4a30401f,
4339 .flags
= ADDR_TYPE_RT
4344 /* l4_wkup -> counter_32k */
4345 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k
= {
4346 .master
= &omap44xx_l4_wkup_hwmod
,
4347 .slave
= &omap44xx_counter_32k_hwmod
,
4348 .clk
= "l4_wkup_clk_mux_ck",
4349 .addr
= omap44xx_counter_32k_addrs
,
4350 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4353 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs
[] = {
4355 .pa_start
= 0x4a002000,
4356 .pa_end
= 0x4a0027ff,
4357 .flags
= ADDR_TYPE_RT
4362 /* l4_cfg -> ctrl_module_core */
4363 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core
= {
4364 .master
= &omap44xx_l4_cfg_hwmod
,
4365 .slave
= &omap44xx_ctrl_module_core_hwmod
,
4367 .addr
= omap44xx_ctrl_module_core_addrs
,
4368 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4371 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs
[] = {
4373 .pa_start
= 0x4a100000,
4374 .pa_end
= 0x4a1007ff,
4375 .flags
= ADDR_TYPE_RT
4380 /* l4_cfg -> ctrl_module_pad_core */
4381 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core
= {
4382 .master
= &omap44xx_l4_cfg_hwmod
,
4383 .slave
= &omap44xx_ctrl_module_pad_core_hwmod
,
4385 .addr
= omap44xx_ctrl_module_pad_core_addrs
,
4386 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4389 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs
[] = {
4391 .pa_start
= 0x4a30c000,
4392 .pa_end
= 0x4a30c7ff,
4393 .flags
= ADDR_TYPE_RT
4398 /* l4_wkup -> ctrl_module_wkup */
4399 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup
= {
4400 .master
= &omap44xx_l4_wkup_hwmod
,
4401 .slave
= &omap44xx_ctrl_module_wkup_hwmod
,
4402 .clk
= "l4_wkup_clk_mux_ck",
4403 .addr
= omap44xx_ctrl_module_wkup_addrs
,
4404 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4407 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs
[] = {
4409 .pa_start
= 0x4a31e000,
4410 .pa_end
= 0x4a31e7ff,
4411 .flags
= ADDR_TYPE_RT
4416 /* l4_wkup -> ctrl_module_pad_wkup */
4417 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup
= {
4418 .master
= &omap44xx_l4_wkup_hwmod
,
4419 .slave
= &omap44xx_ctrl_module_pad_wkup_hwmod
,
4420 .clk
= "l4_wkup_clk_mux_ck",
4421 .addr
= omap44xx_ctrl_module_pad_wkup_addrs
,
4422 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4425 static struct omap_hwmod_addr_space omap44xx_debugss_addrs
[] = {
4427 .pa_start
= 0x54160000,
4428 .pa_end
= 0x54167fff,
4429 .flags
= ADDR_TYPE_RT
4434 /* l3_instr -> debugss */
4435 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss
= {
4436 .master
= &omap44xx_l3_instr_hwmod
,
4437 .slave
= &omap44xx_debugss_hwmod
,
4439 .addr
= omap44xx_debugss_addrs
,
4440 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4443 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs
[] = {
4445 .pa_start
= 0x4a056000,
4446 .pa_end
= 0x4a056fff,
4447 .flags
= ADDR_TYPE_RT
4452 /* l4_cfg -> dma_system */
4453 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system
= {
4454 .master
= &omap44xx_l4_cfg_hwmod
,
4455 .slave
= &omap44xx_dma_system_hwmod
,
4457 .addr
= omap44xx_dma_system_addrs
,
4458 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4461 static struct omap_hwmod_addr_space omap44xx_dmic_addrs
[] = {
4464 .pa_start
= 0x4012e000,
4465 .pa_end
= 0x4012e07f,
4466 .flags
= ADDR_TYPE_RT
4471 /* l4_abe -> dmic */
4472 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic
= {
4473 .master
= &omap44xx_l4_abe_hwmod
,
4474 .slave
= &omap44xx_dmic_hwmod
,
4475 .clk
= "ocp_abe_iclk",
4476 .addr
= omap44xx_dmic_addrs
,
4477 .user
= OCP_USER_MPU
,
4480 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs
[] = {
4483 .pa_start
= 0x4902e000,
4484 .pa_end
= 0x4902e07f,
4485 .flags
= ADDR_TYPE_RT
4490 /* l4_abe -> dmic (dma) */
4491 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma
= {
4492 .master
= &omap44xx_l4_abe_hwmod
,
4493 .slave
= &omap44xx_dmic_hwmod
,
4494 .clk
= "ocp_abe_iclk",
4495 .addr
= omap44xx_dmic_dma_addrs
,
4496 .user
= OCP_USER_SDMA
,
4500 static struct omap_hwmod_ocp_if omap44xx_dsp__iva
= {
4501 .master
= &omap44xx_dsp_hwmod
,
4502 .slave
= &omap44xx_iva_hwmod
,
4503 .clk
= "dpll_iva_m5x2_ck",
4504 .user
= OCP_USER_DSP
,
4508 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if
= {
4509 .master
= &omap44xx_dsp_hwmod
,
4510 .slave
= &omap44xx_sl2if_hwmod
,
4511 .clk
= "dpll_iva_m5x2_ck",
4512 .user
= OCP_USER_DSP
,
4516 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp
= {
4517 .master
= &omap44xx_l4_cfg_hwmod
,
4518 .slave
= &omap44xx_dsp_hwmod
,
4520 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4523 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs
[] = {
4525 .pa_start
= 0x58000000,
4526 .pa_end
= 0x5800007f,
4527 .flags
= ADDR_TYPE_RT
4532 /* l3_main_2 -> dss */
4533 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss
= {
4534 .master
= &omap44xx_l3_main_2_hwmod
,
4535 .slave
= &omap44xx_dss_hwmod
,
4537 .addr
= omap44xx_dss_dma_addrs
,
4538 .user
= OCP_USER_SDMA
,
4541 static struct omap_hwmod_addr_space omap44xx_dss_addrs
[] = {
4543 .pa_start
= 0x48040000,
4544 .pa_end
= 0x4804007f,
4545 .flags
= ADDR_TYPE_RT
4551 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss
= {
4552 .master
= &omap44xx_l4_per_hwmod
,
4553 .slave
= &omap44xx_dss_hwmod
,
4555 .addr
= omap44xx_dss_addrs
,
4556 .user
= OCP_USER_MPU
,
4559 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs
[] = {
4561 .pa_start
= 0x58001000,
4562 .pa_end
= 0x58001fff,
4563 .flags
= ADDR_TYPE_RT
4568 /* l3_main_2 -> dss_dispc */
4569 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc
= {
4570 .master
= &omap44xx_l3_main_2_hwmod
,
4571 .slave
= &omap44xx_dss_dispc_hwmod
,
4573 .addr
= omap44xx_dss_dispc_dma_addrs
,
4574 .user
= OCP_USER_SDMA
,
4577 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs
[] = {
4579 .pa_start
= 0x48041000,
4580 .pa_end
= 0x48041fff,
4581 .flags
= ADDR_TYPE_RT
4586 /* l4_per -> dss_dispc */
4587 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc
= {
4588 .master
= &omap44xx_l4_per_hwmod
,
4589 .slave
= &omap44xx_dss_dispc_hwmod
,
4591 .addr
= omap44xx_dss_dispc_addrs
,
4592 .user
= OCP_USER_MPU
,
4595 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs
[] = {
4597 .pa_start
= 0x58004000,
4598 .pa_end
= 0x580041ff,
4599 .flags
= ADDR_TYPE_RT
4604 /* l3_main_2 -> dss_dsi1 */
4605 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1
= {
4606 .master
= &omap44xx_l3_main_2_hwmod
,
4607 .slave
= &omap44xx_dss_dsi1_hwmod
,
4609 .addr
= omap44xx_dss_dsi1_dma_addrs
,
4610 .user
= OCP_USER_SDMA
,
4613 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs
[] = {
4615 .pa_start
= 0x48044000,
4616 .pa_end
= 0x480441ff,
4617 .flags
= ADDR_TYPE_RT
4622 /* l4_per -> dss_dsi1 */
4623 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1
= {
4624 .master
= &omap44xx_l4_per_hwmod
,
4625 .slave
= &omap44xx_dss_dsi1_hwmod
,
4627 .addr
= omap44xx_dss_dsi1_addrs
,
4628 .user
= OCP_USER_MPU
,
4631 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs
[] = {
4633 .pa_start
= 0x58005000,
4634 .pa_end
= 0x580051ff,
4635 .flags
= ADDR_TYPE_RT
4640 /* l3_main_2 -> dss_dsi2 */
4641 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2
= {
4642 .master
= &omap44xx_l3_main_2_hwmod
,
4643 .slave
= &omap44xx_dss_dsi2_hwmod
,
4645 .addr
= omap44xx_dss_dsi2_dma_addrs
,
4646 .user
= OCP_USER_SDMA
,
4649 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs
[] = {
4651 .pa_start
= 0x48045000,
4652 .pa_end
= 0x480451ff,
4653 .flags
= ADDR_TYPE_RT
4658 /* l4_per -> dss_dsi2 */
4659 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2
= {
4660 .master
= &omap44xx_l4_per_hwmod
,
4661 .slave
= &omap44xx_dss_dsi2_hwmod
,
4663 .addr
= omap44xx_dss_dsi2_addrs
,
4664 .user
= OCP_USER_MPU
,
4667 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs
[] = {
4669 .pa_start
= 0x58006000,
4670 .pa_end
= 0x58006fff,
4671 .flags
= ADDR_TYPE_RT
4676 /* l3_main_2 -> dss_hdmi */
4677 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi
= {
4678 .master
= &omap44xx_l3_main_2_hwmod
,
4679 .slave
= &omap44xx_dss_hdmi_hwmod
,
4681 .addr
= omap44xx_dss_hdmi_dma_addrs
,
4682 .user
= OCP_USER_SDMA
,
4685 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs
[] = {
4687 .pa_start
= 0x48046000,
4688 .pa_end
= 0x48046fff,
4689 .flags
= ADDR_TYPE_RT
4694 /* l4_per -> dss_hdmi */
4695 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi
= {
4696 .master
= &omap44xx_l4_per_hwmod
,
4697 .slave
= &omap44xx_dss_hdmi_hwmod
,
4699 .addr
= omap44xx_dss_hdmi_addrs
,
4700 .user
= OCP_USER_MPU
,
4703 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs
[] = {
4705 .pa_start
= 0x58002000,
4706 .pa_end
= 0x580020ff,
4707 .flags
= ADDR_TYPE_RT
4712 /* l3_main_2 -> dss_rfbi */
4713 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi
= {
4714 .master
= &omap44xx_l3_main_2_hwmod
,
4715 .slave
= &omap44xx_dss_rfbi_hwmod
,
4717 .addr
= omap44xx_dss_rfbi_dma_addrs
,
4718 .user
= OCP_USER_SDMA
,
4721 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs
[] = {
4723 .pa_start
= 0x48042000,
4724 .pa_end
= 0x480420ff,
4725 .flags
= ADDR_TYPE_RT
4730 /* l4_per -> dss_rfbi */
4731 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi
= {
4732 .master
= &omap44xx_l4_per_hwmod
,
4733 .slave
= &omap44xx_dss_rfbi_hwmod
,
4735 .addr
= omap44xx_dss_rfbi_addrs
,
4736 .user
= OCP_USER_MPU
,
4739 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs
[] = {
4741 .pa_start
= 0x58003000,
4742 .pa_end
= 0x580030ff,
4743 .flags
= ADDR_TYPE_RT
4748 /* l3_main_2 -> dss_venc */
4749 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc
= {
4750 .master
= &omap44xx_l3_main_2_hwmod
,
4751 .slave
= &omap44xx_dss_venc_hwmod
,
4753 .addr
= omap44xx_dss_venc_dma_addrs
,
4754 .user
= OCP_USER_SDMA
,
4757 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs
[] = {
4759 .pa_start
= 0x48043000,
4760 .pa_end
= 0x480430ff,
4761 .flags
= ADDR_TYPE_RT
4766 /* l4_per -> dss_venc */
4767 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc
= {
4768 .master
= &omap44xx_l4_per_hwmod
,
4769 .slave
= &omap44xx_dss_venc_hwmod
,
4771 .addr
= omap44xx_dss_venc_addrs
,
4772 .user
= OCP_USER_MPU
,
4775 static struct omap_hwmod_addr_space omap44xx_elm_addrs
[] = {
4777 .pa_start
= 0x48078000,
4778 .pa_end
= 0x48078fff,
4779 .flags
= ADDR_TYPE_RT
4785 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm
= {
4786 .master
= &omap44xx_l4_per_hwmod
,
4787 .slave
= &omap44xx_elm_hwmod
,
4789 .addr
= omap44xx_elm_addrs
,
4790 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4793 static struct omap_hwmod_addr_space omap44xx_emif1_addrs
[] = {
4795 .pa_start
= 0x4c000000,
4796 .pa_end
= 0x4c0000ff,
4797 .flags
= ADDR_TYPE_RT
4802 /* emif_fw -> emif1 */
4803 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1
= {
4804 .master
= &omap44xx_emif_fw_hwmod
,
4805 .slave
= &omap44xx_emif1_hwmod
,
4807 .addr
= omap44xx_emif1_addrs
,
4808 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4811 static struct omap_hwmod_addr_space omap44xx_emif2_addrs
[] = {
4813 .pa_start
= 0x4d000000,
4814 .pa_end
= 0x4d0000ff,
4815 .flags
= ADDR_TYPE_RT
4820 /* emif_fw -> emif2 */
4821 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2
= {
4822 .master
= &omap44xx_emif_fw_hwmod
,
4823 .slave
= &omap44xx_emif2_hwmod
,
4825 .addr
= omap44xx_emif2_addrs
,
4826 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4829 static struct omap_hwmod_addr_space omap44xx_fdif_addrs
[] = {
4831 .pa_start
= 0x4a10a000,
4832 .pa_end
= 0x4a10a1ff,
4833 .flags
= ADDR_TYPE_RT
4838 /* l4_cfg -> fdif */
4839 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif
= {
4840 .master
= &omap44xx_l4_cfg_hwmod
,
4841 .slave
= &omap44xx_fdif_hwmod
,
4843 .addr
= omap44xx_fdif_addrs
,
4844 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4847 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs
[] = {
4849 .pa_start
= 0x4a310000,
4850 .pa_end
= 0x4a3101ff,
4851 .flags
= ADDR_TYPE_RT
4856 /* l4_wkup -> gpio1 */
4857 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1
= {
4858 .master
= &omap44xx_l4_wkup_hwmod
,
4859 .slave
= &omap44xx_gpio1_hwmod
,
4860 .clk
= "l4_wkup_clk_mux_ck",
4861 .addr
= omap44xx_gpio1_addrs
,
4862 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4865 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs
[] = {
4867 .pa_start
= 0x48055000,
4868 .pa_end
= 0x480551ff,
4869 .flags
= ADDR_TYPE_RT
4874 /* l4_per -> gpio2 */
4875 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2
= {
4876 .master
= &omap44xx_l4_per_hwmod
,
4877 .slave
= &omap44xx_gpio2_hwmod
,
4879 .addr
= omap44xx_gpio2_addrs
,
4880 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4883 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs
[] = {
4885 .pa_start
= 0x48057000,
4886 .pa_end
= 0x480571ff,
4887 .flags
= ADDR_TYPE_RT
4892 /* l4_per -> gpio3 */
4893 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3
= {
4894 .master
= &omap44xx_l4_per_hwmod
,
4895 .slave
= &omap44xx_gpio3_hwmod
,
4897 .addr
= omap44xx_gpio3_addrs
,
4898 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4901 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs
[] = {
4903 .pa_start
= 0x48059000,
4904 .pa_end
= 0x480591ff,
4905 .flags
= ADDR_TYPE_RT
4910 /* l4_per -> gpio4 */
4911 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4
= {
4912 .master
= &omap44xx_l4_per_hwmod
,
4913 .slave
= &omap44xx_gpio4_hwmod
,
4915 .addr
= omap44xx_gpio4_addrs
,
4916 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4919 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs
[] = {
4921 .pa_start
= 0x4805b000,
4922 .pa_end
= 0x4805b1ff,
4923 .flags
= ADDR_TYPE_RT
4928 /* l4_per -> gpio5 */
4929 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5
= {
4930 .master
= &omap44xx_l4_per_hwmod
,
4931 .slave
= &omap44xx_gpio5_hwmod
,
4933 .addr
= omap44xx_gpio5_addrs
,
4934 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4937 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs
[] = {
4939 .pa_start
= 0x4805d000,
4940 .pa_end
= 0x4805d1ff,
4941 .flags
= ADDR_TYPE_RT
4946 /* l4_per -> gpio6 */
4947 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6
= {
4948 .master
= &omap44xx_l4_per_hwmod
,
4949 .slave
= &omap44xx_gpio6_hwmod
,
4951 .addr
= omap44xx_gpio6_addrs
,
4952 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4955 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs
[] = {
4957 .pa_start
= 0x50000000,
4958 .pa_end
= 0x500003ff,
4959 .flags
= ADDR_TYPE_RT
4964 /* l3_main_2 -> gpmc */
4965 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc
= {
4966 .master
= &omap44xx_l3_main_2_hwmod
,
4967 .slave
= &omap44xx_gpmc_hwmod
,
4969 .addr
= omap44xx_gpmc_addrs
,
4970 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4973 static struct omap_hwmod_addr_space omap44xx_gpu_addrs
[] = {
4975 .pa_start
= 0x56000000,
4976 .pa_end
= 0x5600ffff,
4977 .flags
= ADDR_TYPE_RT
4982 /* l3_main_2 -> gpu */
4983 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu
= {
4984 .master
= &omap44xx_l3_main_2_hwmod
,
4985 .slave
= &omap44xx_gpu_hwmod
,
4987 .addr
= omap44xx_gpu_addrs
,
4988 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4991 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs
[] = {
4993 .pa_start
= 0x480b2000,
4994 .pa_end
= 0x480b201f,
4995 .flags
= ADDR_TYPE_RT
5000 /* l4_per -> hdq1w */
5001 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w
= {
5002 .master
= &omap44xx_l4_per_hwmod
,
5003 .slave
= &omap44xx_hdq1w_hwmod
,
5005 .addr
= omap44xx_hdq1w_addrs
,
5006 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5009 static struct omap_hwmod_addr_space omap44xx_hsi_addrs
[] = {
5011 .pa_start
= 0x4a058000,
5012 .pa_end
= 0x4a05bfff,
5013 .flags
= ADDR_TYPE_RT
5019 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi
= {
5020 .master
= &omap44xx_l4_cfg_hwmod
,
5021 .slave
= &omap44xx_hsi_hwmod
,
5023 .addr
= omap44xx_hsi_addrs
,
5024 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5027 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs
[] = {
5029 .pa_start
= 0x48070000,
5030 .pa_end
= 0x480700ff,
5031 .flags
= ADDR_TYPE_RT
5036 /* l4_per -> i2c1 */
5037 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1
= {
5038 .master
= &omap44xx_l4_per_hwmod
,
5039 .slave
= &omap44xx_i2c1_hwmod
,
5041 .addr
= omap44xx_i2c1_addrs
,
5042 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5045 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs
[] = {
5047 .pa_start
= 0x48072000,
5048 .pa_end
= 0x480720ff,
5049 .flags
= ADDR_TYPE_RT
5054 /* l4_per -> i2c2 */
5055 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2
= {
5056 .master
= &omap44xx_l4_per_hwmod
,
5057 .slave
= &omap44xx_i2c2_hwmod
,
5059 .addr
= omap44xx_i2c2_addrs
,
5060 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5063 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs
[] = {
5065 .pa_start
= 0x48060000,
5066 .pa_end
= 0x480600ff,
5067 .flags
= ADDR_TYPE_RT
5072 /* l4_per -> i2c3 */
5073 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3
= {
5074 .master
= &omap44xx_l4_per_hwmod
,
5075 .slave
= &omap44xx_i2c3_hwmod
,
5077 .addr
= omap44xx_i2c3_addrs
,
5078 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5081 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs
[] = {
5083 .pa_start
= 0x48350000,
5084 .pa_end
= 0x483500ff,
5085 .flags
= ADDR_TYPE_RT
5090 /* l4_per -> i2c4 */
5091 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4
= {
5092 .master
= &omap44xx_l4_per_hwmod
,
5093 .slave
= &omap44xx_i2c4_hwmod
,
5095 .addr
= omap44xx_i2c4_addrs
,
5096 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5099 /* l3_main_2 -> ipu */
5100 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu
= {
5101 .master
= &omap44xx_l3_main_2_hwmod
,
5102 .slave
= &omap44xx_ipu_hwmod
,
5104 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5107 static struct omap_hwmod_addr_space omap44xx_iss_addrs
[] = {
5109 .pa_start
= 0x52000000,
5110 .pa_end
= 0x520000ff,
5111 .flags
= ADDR_TYPE_RT
5116 /* l3_main_2 -> iss */
5117 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss
= {
5118 .master
= &omap44xx_l3_main_2_hwmod
,
5119 .slave
= &omap44xx_iss_hwmod
,
5121 .addr
= omap44xx_iss_addrs
,
5122 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5126 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if
= {
5127 .master
= &omap44xx_iva_hwmod
,
5128 .slave
= &omap44xx_sl2if_hwmod
,
5129 .clk
= "dpll_iva_m5x2_ck",
5130 .user
= OCP_USER_IVA
,
5133 static struct omap_hwmod_addr_space omap44xx_iva_addrs
[] = {
5135 .pa_start
= 0x5a000000,
5136 .pa_end
= 0x5a07ffff,
5137 .flags
= ADDR_TYPE_RT
5142 /* l3_main_2 -> iva */
5143 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva
= {
5144 .master
= &omap44xx_l3_main_2_hwmod
,
5145 .slave
= &omap44xx_iva_hwmod
,
5147 .addr
= omap44xx_iva_addrs
,
5148 .user
= OCP_USER_MPU
,
5151 static struct omap_hwmod_addr_space omap44xx_kbd_addrs
[] = {
5153 .pa_start
= 0x4a31c000,
5154 .pa_end
= 0x4a31c07f,
5155 .flags
= ADDR_TYPE_RT
5160 /* l4_wkup -> kbd */
5161 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd
= {
5162 .master
= &omap44xx_l4_wkup_hwmod
,
5163 .slave
= &omap44xx_kbd_hwmod
,
5164 .clk
= "l4_wkup_clk_mux_ck",
5165 .addr
= omap44xx_kbd_addrs
,
5166 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5169 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs
[] = {
5171 .pa_start
= 0x4a0f4000,
5172 .pa_end
= 0x4a0f41ff,
5173 .flags
= ADDR_TYPE_RT
5178 /* l4_cfg -> mailbox */
5179 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox
= {
5180 .master
= &omap44xx_l4_cfg_hwmod
,
5181 .slave
= &omap44xx_mailbox_hwmod
,
5183 .addr
= omap44xx_mailbox_addrs
,
5184 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5187 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs
[] = {
5189 .pa_start
= 0x40128000,
5190 .pa_end
= 0x401283ff,
5191 .flags
= ADDR_TYPE_RT
5196 /* l4_abe -> mcasp */
5197 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp
= {
5198 .master
= &omap44xx_l4_abe_hwmod
,
5199 .slave
= &omap44xx_mcasp_hwmod
,
5200 .clk
= "ocp_abe_iclk",
5201 .addr
= omap44xx_mcasp_addrs
,
5202 .user
= OCP_USER_MPU
,
5205 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs
[] = {
5207 .pa_start
= 0x49028000,
5208 .pa_end
= 0x490283ff,
5209 .flags
= ADDR_TYPE_RT
5214 /* l4_abe -> mcasp (dma) */
5215 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma
= {
5216 .master
= &omap44xx_l4_abe_hwmod
,
5217 .slave
= &omap44xx_mcasp_hwmod
,
5218 .clk
= "ocp_abe_iclk",
5219 .addr
= omap44xx_mcasp_dma_addrs
,
5220 .user
= OCP_USER_SDMA
,
5223 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs
[] = {
5226 .pa_start
= 0x40122000,
5227 .pa_end
= 0x401220ff,
5228 .flags
= ADDR_TYPE_RT
5233 /* l4_abe -> mcbsp1 */
5234 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1
= {
5235 .master
= &omap44xx_l4_abe_hwmod
,
5236 .slave
= &omap44xx_mcbsp1_hwmod
,
5237 .clk
= "ocp_abe_iclk",
5238 .addr
= omap44xx_mcbsp1_addrs
,
5239 .user
= OCP_USER_MPU
,
5242 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs
[] = {
5245 .pa_start
= 0x49022000,
5246 .pa_end
= 0x490220ff,
5247 .flags
= ADDR_TYPE_RT
5252 /* l4_abe -> mcbsp1 (dma) */
5253 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma
= {
5254 .master
= &omap44xx_l4_abe_hwmod
,
5255 .slave
= &omap44xx_mcbsp1_hwmod
,
5256 .clk
= "ocp_abe_iclk",
5257 .addr
= omap44xx_mcbsp1_dma_addrs
,
5258 .user
= OCP_USER_SDMA
,
5261 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs
[] = {
5264 .pa_start
= 0x40124000,
5265 .pa_end
= 0x401240ff,
5266 .flags
= ADDR_TYPE_RT
5271 /* l4_abe -> mcbsp2 */
5272 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2
= {
5273 .master
= &omap44xx_l4_abe_hwmod
,
5274 .slave
= &omap44xx_mcbsp2_hwmod
,
5275 .clk
= "ocp_abe_iclk",
5276 .addr
= omap44xx_mcbsp2_addrs
,
5277 .user
= OCP_USER_MPU
,
5280 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs
[] = {
5283 .pa_start
= 0x49024000,
5284 .pa_end
= 0x490240ff,
5285 .flags
= ADDR_TYPE_RT
5290 /* l4_abe -> mcbsp2 (dma) */
5291 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma
= {
5292 .master
= &omap44xx_l4_abe_hwmod
,
5293 .slave
= &omap44xx_mcbsp2_hwmod
,
5294 .clk
= "ocp_abe_iclk",
5295 .addr
= omap44xx_mcbsp2_dma_addrs
,
5296 .user
= OCP_USER_SDMA
,
5299 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs
[] = {
5302 .pa_start
= 0x40126000,
5303 .pa_end
= 0x401260ff,
5304 .flags
= ADDR_TYPE_RT
5309 /* l4_abe -> mcbsp3 */
5310 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3
= {
5311 .master
= &omap44xx_l4_abe_hwmod
,
5312 .slave
= &omap44xx_mcbsp3_hwmod
,
5313 .clk
= "ocp_abe_iclk",
5314 .addr
= omap44xx_mcbsp3_addrs
,
5315 .user
= OCP_USER_MPU
,
5318 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs
[] = {
5321 .pa_start
= 0x49026000,
5322 .pa_end
= 0x490260ff,
5323 .flags
= ADDR_TYPE_RT
5328 /* l4_abe -> mcbsp3 (dma) */
5329 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma
= {
5330 .master
= &omap44xx_l4_abe_hwmod
,
5331 .slave
= &omap44xx_mcbsp3_hwmod
,
5332 .clk
= "ocp_abe_iclk",
5333 .addr
= omap44xx_mcbsp3_dma_addrs
,
5334 .user
= OCP_USER_SDMA
,
5337 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs
[] = {
5339 .pa_start
= 0x48096000,
5340 .pa_end
= 0x480960ff,
5341 .flags
= ADDR_TYPE_RT
5346 /* l4_per -> mcbsp4 */
5347 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4
= {
5348 .master
= &omap44xx_l4_per_hwmod
,
5349 .slave
= &omap44xx_mcbsp4_hwmod
,
5351 .addr
= omap44xx_mcbsp4_addrs
,
5352 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5355 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs
[] = {
5358 .pa_start
= 0x40132000,
5359 .pa_end
= 0x4013207f,
5360 .flags
= ADDR_TYPE_RT
5365 /* l4_abe -> mcpdm */
5366 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm
= {
5367 .master
= &omap44xx_l4_abe_hwmod
,
5368 .slave
= &omap44xx_mcpdm_hwmod
,
5369 .clk
= "ocp_abe_iclk",
5370 .addr
= omap44xx_mcpdm_addrs
,
5371 .user
= OCP_USER_MPU
,
5374 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs
[] = {
5377 .pa_start
= 0x49032000,
5378 .pa_end
= 0x4903207f,
5379 .flags
= ADDR_TYPE_RT
5384 /* l4_abe -> mcpdm (dma) */
5385 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma
= {
5386 .master
= &omap44xx_l4_abe_hwmod
,
5387 .slave
= &omap44xx_mcpdm_hwmod
,
5388 .clk
= "ocp_abe_iclk",
5389 .addr
= omap44xx_mcpdm_dma_addrs
,
5390 .user
= OCP_USER_SDMA
,
5393 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs
[] = {
5395 .pa_start
= 0x48098000,
5396 .pa_end
= 0x480981ff,
5397 .flags
= ADDR_TYPE_RT
5402 /* l4_per -> mcspi1 */
5403 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1
= {
5404 .master
= &omap44xx_l4_per_hwmod
,
5405 .slave
= &omap44xx_mcspi1_hwmod
,
5407 .addr
= omap44xx_mcspi1_addrs
,
5408 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5411 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs
[] = {
5413 .pa_start
= 0x4809a000,
5414 .pa_end
= 0x4809a1ff,
5415 .flags
= ADDR_TYPE_RT
5420 /* l4_per -> mcspi2 */
5421 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2
= {
5422 .master
= &omap44xx_l4_per_hwmod
,
5423 .slave
= &omap44xx_mcspi2_hwmod
,
5425 .addr
= omap44xx_mcspi2_addrs
,
5426 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5429 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs
[] = {
5431 .pa_start
= 0x480b8000,
5432 .pa_end
= 0x480b81ff,
5433 .flags
= ADDR_TYPE_RT
5438 /* l4_per -> mcspi3 */
5439 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3
= {
5440 .master
= &omap44xx_l4_per_hwmod
,
5441 .slave
= &omap44xx_mcspi3_hwmod
,
5443 .addr
= omap44xx_mcspi3_addrs
,
5444 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5447 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs
[] = {
5449 .pa_start
= 0x480ba000,
5450 .pa_end
= 0x480ba1ff,
5451 .flags
= ADDR_TYPE_RT
5456 /* l4_per -> mcspi4 */
5457 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4
= {
5458 .master
= &omap44xx_l4_per_hwmod
,
5459 .slave
= &omap44xx_mcspi4_hwmod
,
5461 .addr
= omap44xx_mcspi4_addrs
,
5462 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5465 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs
[] = {
5467 .pa_start
= 0x4809c000,
5468 .pa_end
= 0x4809c3ff,
5469 .flags
= ADDR_TYPE_RT
5474 /* l4_per -> mmc1 */
5475 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1
= {
5476 .master
= &omap44xx_l4_per_hwmod
,
5477 .slave
= &omap44xx_mmc1_hwmod
,
5479 .addr
= omap44xx_mmc1_addrs
,
5480 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5483 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs
[] = {
5485 .pa_start
= 0x480b4000,
5486 .pa_end
= 0x480b43ff,
5487 .flags
= ADDR_TYPE_RT
5492 /* l4_per -> mmc2 */
5493 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2
= {
5494 .master
= &omap44xx_l4_per_hwmod
,
5495 .slave
= &omap44xx_mmc2_hwmod
,
5497 .addr
= omap44xx_mmc2_addrs
,
5498 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5501 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs
[] = {
5503 .pa_start
= 0x480ad000,
5504 .pa_end
= 0x480ad3ff,
5505 .flags
= ADDR_TYPE_RT
5510 /* l4_per -> mmc3 */
5511 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3
= {
5512 .master
= &omap44xx_l4_per_hwmod
,
5513 .slave
= &omap44xx_mmc3_hwmod
,
5515 .addr
= omap44xx_mmc3_addrs
,
5516 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5519 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs
[] = {
5521 .pa_start
= 0x480d1000,
5522 .pa_end
= 0x480d13ff,
5523 .flags
= ADDR_TYPE_RT
5528 /* l4_per -> mmc4 */
5529 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4
= {
5530 .master
= &omap44xx_l4_per_hwmod
,
5531 .slave
= &omap44xx_mmc4_hwmod
,
5533 .addr
= omap44xx_mmc4_addrs
,
5534 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5537 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs
[] = {
5539 .pa_start
= 0x480d5000,
5540 .pa_end
= 0x480d53ff,
5541 .flags
= ADDR_TYPE_RT
5546 /* l4_per -> mmc5 */
5547 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5
= {
5548 .master
= &omap44xx_l4_per_hwmod
,
5549 .slave
= &omap44xx_mmc5_hwmod
,
5551 .addr
= omap44xx_mmc5_addrs
,
5552 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5555 /* l3_main_2 -> ocmc_ram */
5556 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram
= {
5557 .master
= &omap44xx_l3_main_2_hwmod
,
5558 .slave
= &omap44xx_ocmc_ram_hwmod
,
5560 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5563 static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs
[] = {
5565 .pa_start
= 0x4a0ad000,
5566 .pa_end
= 0x4a0ad01f,
5567 .flags
= ADDR_TYPE_RT
5572 /* l4_cfg -> ocp2scp_usb_phy */
5573 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy
= {
5574 .master
= &omap44xx_l4_cfg_hwmod
,
5575 .slave
= &omap44xx_ocp2scp_usb_phy_hwmod
,
5577 .addr
= omap44xx_ocp2scp_usb_phy_addrs
,
5578 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5581 static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs
[] = {
5583 .pa_start
= 0x48243000,
5584 .pa_end
= 0x48243fff,
5585 .flags
= ADDR_TYPE_RT
5590 /* mpu_private -> prcm_mpu */
5591 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu
= {
5592 .master
= &omap44xx_mpu_private_hwmod
,
5593 .slave
= &omap44xx_prcm_mpu_hwmod
,
5595 .addr
= omap44xx_prcm_mpu_addrs
,
5596 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5599 static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs
[] = {
5601 .pa_start
= 0x4a004000,
5602 .pa_end
= 0x4a004fff,
5603 .flags
= ADDR_TYPE_RT
5608 /* l4_wkup -> cm_core_aon */
5609 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon
= {
5610 .master
= &omap44xx_l4_wkup_hwmod
,
5611 .slave
= &omap44xx_cm_core_aon_hwmod
,
5612 .clk
= "l4_wkup_clk_mux_ck",
5613 .addr
= omap44xx_cm_core_aon_addrs
,
5614 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5617 static struct omap_hwmod_addr_space omap44xx_cm_core_addrs
[] = {
5619 .pa_start
= 0x4a008000,
5620 .pa_end
= 0x4a009fff,
5621 .flags
= ADDR_TYPE_RT
5626 /* l4_cfg -> cm_core */
5627 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core
= {
5628 .master
= &omap44xx_l4_cfg_hwmod
,
5629 .slave
= &omap44xx_cm_core_hwmod
,
5631 .addr
= omap44xx_cm_core_addrs
,
5632 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5635 static struct omap_hwmod_addr_space omap44xx_prm_addrs
[] = {
5637 .pa_start
= 0x4a306000,
5638 .pa_end
= 0x4a307fff,
5639 .flags
= ADDR_TYPE_RT
5644 /* l4_wkup -> prm */
5645 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm
= {
5646 .master
= &omap44xx_l4_wkup_hwmod
,
5647 .slave
= &omap44xx_prm_hwmod
,
5648 .clk
= "l4_wkup_clk_mux_ck",
5649 .addr
= omap44xx_prm_addrs
,
5650 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5653 static struct omap_hwmod_addr_space omap44xx_scrm_addrs
[] = {
5655 .pa_start
= 0x4a30a000,
5656 .pa_end
= 0x4a30a7ff,
5657 .flags
= ADDR_TYPE_RT
5662 /* l4_wkup -> scrm */
5663 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm
= {
5664 .master
= &omap44xx_l4_wkup_hwmod
,
5665 .slave
= &omap44xx_scrm_hwmod
,
5666 .clk
= "l4_wkup_clk_mux_ck",
5667 .addr
= omap44xx_scrm_addrs
,
5668 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5671 /* l3_main_2 -> sl2if */
5672 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if
= {
5673 .master
= &omap44xx_l3_main_2_hwmod
,
5674 .slave
= &omap44xx_sl2if_hwmod
,
5676 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5679 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs
[] = {
5681 .pa_start
= 0x4012c000,
5682 .pa_end
= 0x4012c3ff,
5683 .flags
= ADDR_TYPE_RT
5688 /* l4_abe -> slimbus1 */
5689 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1
= {
5690 .master
= &omap44xx_l4_abe_hwmod
,
5691 .slave
= &omap44xx_slimbus1_hwmod
,
5692 .clk
= "ocp_abe_iclk",
5693 .addr
= omap44xx_slimbus1_addrs
,
5694 .user
= OCP_USER_MPU
,
5697 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs
[] = {
5699 .pa_start
= 0x4902c000,
5700 .pa_end
= 0x4902c3ff,
5701 .flags
= ADDR_TYPE_RT
5706 /* l4_abe -> slimbus1 (dma) */
5707 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma
= {
5708 .master
= &omap44xx_l4_abe_hwmod
,
5709 .slave
= &omap44xx_slimbus1_hwmod
,
5710 .clk
= "ocp_abe_iclk",
5711 .addr
= omap44xx_slimbus1_dma_addrs
,
5712 .user
= OCP_USER_SDMA
,
5715 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs
[] = {
5717 .pa_start
= 0x48076000,
5718 .pa_end
= 0x480763ff,
5719 .flags
= ADDR_TYPE_RT
5724 /* l4_per -> slimbus2 */
5725 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2
= {
5726 .master
= &omap44xx_l4_per_hwmod
,
5727 .slave
= &omap44xx_slimbus2_hwmod
,
5729 .addr
= omap44xx_slimbus2_addrs
,
5730 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5733 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs
[] = {
5735 .pa_start
= 0x4a0dd000,
5736 .pa_end
= 0x4a0dd03f,
5737 .flags
= ADDR_TYPE_RT
5742 /* l4_cfg -> smartreflex_core */
5743 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core
= {
5744 .master
= &omap44xx_l4_cfg_hwmod
,
5745 .slave
= &omap44xx_smartreflex_core_hwmod
,
5747 .addr
= omap44xx_smartreflex_core_addrs
,
5748 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5751 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs
[] = {
5753 .pa_start
= 0x4a0db000,
5754 .pa_end
= 0x4a0db03f,
5755 .flags
= ADDR_TYPE_RT
5760 /* l4_cfg -> smartreflex_iva */
5761 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva
= {
5762 .master
= &omap44xx_l4_cfg_hwmod
,
5763 .slave
= &omap44xx_smartreflex_iva_hwmod
,
5765 .addr
= omap44xx_smartreflex_iva_addrs
,
5766 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5769 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs
[] = {
5771 .pa_start
= 0x4a0d9000,
5772 .pa_end
= 0x4a0d903f,
5773 .flags
= ADDR_TYPE_RT
5778 /* l4_cfg -> smartreflex_mpu */
5779 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu
= {
5780 .master
= &omap44xx_l4_cfg_hwmod
,
5781 .slave
= &omap44xx_smartreflex_mpu_hwmod
,
5783 .addr
= omap44xx_smartreflex_mpu_addrs
,
5784 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5787 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs
[] = {
5789 .pa_start
= 0x4a0f6000,
5790 .pa_end
= 0x4a0f6fff,
5791 .flags
= ADDR_TYPE_RT
5796 /* l4_cfg -> spinlock */
5797 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock
= {
5798 .master
= &omap44xx_l4_cfg_hwmod
,
5799 .slave
= &omap44xx_spinlock_hwmod
,
5801 .addr
= omap44xx_spinlock_addrs
,
5802 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5805 static struct omap_hwmod_addr_space omap44xx_timer1_addrs
[] = {
5807 .pa_start
= 0x4a318000,
5808 .pa_end
= 0x4a31807f,
5809 .flags
= ADDR_TYPE_RT
5814 /* l4_wkup -> timer1 */
5815 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1
= {
5816 .master
= &omap44xx_l4_wkup_hwmod
,
5817 .slave
= &omap44xx_timer1_hwmod
,
5818 .clk
= "l4_wkup_clk_mux_ck",
5819 .addr
= omap44xx_timer1_addrs
,
5820 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5823 static struct omap_hwmod_addr_space omap44xx_timer2_addrs
[] = {
5825 .pa_start
= 0x48032000,
5826 .pa_end
= 0x4803207f,
5827 .flags
= ADDR_TYPE_RT
5832 /* l4_per -> timer2 */
5833 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2
= {
5834 .master
= &omap44xx_l4_per_hwmod
,
5835 .slave
= &omap44xx_timer2_hwmod
,
5837 .addr
= omap44xx_timer2_addrs
,
5838 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5841 static struct omap_hwmod_addr_space omap44xx_timer3_addrs
[] = {
5843 .pa_start
= 0x48034000,
5844 .pa_end
= 0x4803407f,
5845 .flags
= ADDR_TYPE_RT
5850 /* l4_per -> timer3 */
5851 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3
= {
5852 .master
= &omap44xx_l4_per_hwmod
,
5853 .slave
= &omap44xx_timer3_hwmod
,
5855 .addr
= omap44xx_timer3_addrs
,
5856 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5859 static struct omap_hwmod_addr_space omap44xx_timer4_addrs
[] = {
5861 .pa_start
= 0x48036000,
5862 .pa_end
= 0x4803607f,
5863 .flags
= ADDR_TYPE_RT
5868 /* l4_per -> timer4 */
5869 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4
= {
5870 .master
= &omap44xx_l4_per_hwmod
,
5871 .slave
= &omap44xx_timer4_hwmod
,
5873 .addr
= omap44xx_timer4_addrs
,
5874 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5877 static struct omap_hwmod_addr_space omap44xx_timer5_addrs
[] = {
5879 .pa_start
= 0x40138000,
5880 .pa_end
= 0x4013807f,
5881 .flags
= ADDR_TYPE_RT
5886 /* l4_abe -> timer5 */
5887 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5
= {
5888 .master
= &omap44xx_l4_abe_hwmod
,
5889 .slave
= &omap44xx_timer5_hwmod
,
5890 .clk
= "ocp_abe_iclk",
5891 .addr
= omap44xx_timer5_addrs
,
5892 .user
= OCP_USER_MPU
,
5895 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs
[] = {
5897 .pa_start
= 0x49038000,
5898 .pa_end
= 0x4903807f,
5899 .flags
= ADDR_TYPE_RT
5904 /* l4_abe -> timer5 (dma) */
5905 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma
= {
5906 .master
= &omap44xx_l4_abe_hwmod
,
5907 .slave
= &omap44xx_timer5_hwmod
,
5908 .clk
= "ocp_abe_iclk",
5909 .addr
= omap44xx_timer5_dma_addrs
,
5910 .user
= OCP_USER_SDMA
,
5913 static struct omap_hwmod_addr_space omap44xx_timer6_addrs
[] = {
5915 .pa_start
= 0x4013a000,
5916 .pa_end
= 0x4013a07f,
5917 .flags
= ADDR_TYPE_RT
5922 /* l4_abe -> timer6 */
5923 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6
= {
5924 .master
= &omap44xx_l4_abe_hwmod
,
5925 .slave
= &omap44xx_timer6_hwmod
,
5926 .clk
= "ocp_abe_iclk",
5927 .addr
= omap44xx_timer6_addrs
,
5928 .user
= OCP_USER_MPU
,
5931 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs
[] = {
5933 .pa_start
= 0x4903a000,
5934 .pa_end
= 0x4903a07f,
5935 .flags
= ADDR_TYPE_RT
5940 /* l4_abe -> timer6 (dma) */
5941 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma
= {
5942 .master
= &omap44xx_l4_abe_hwmod
,
5943 .slave
= &omap44xx_timer6_hwmod
,
5944 .clk
= "ocp_abe_iclk",
5945 .addr
= omap44xx_timer6_dma_addrs
,
5946 .user
= OCP_USER_SDMA
,
5949 static struct omap_hwmod_addr_space omap44xx_timer7_addrs
[] = {
5951 .pa_start
= 0x4013c000,
5952 .pa_end
= 0x4013c07f,
5953 .flags
= ADDR_TYPE_RT
5958 /* l4_abe -> timer7 */
5959 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7
= {
5960 .master
= &omap44xx_l4_abe_hwmod
,
5961 .slave
= &omap44xx_timer7_hwmod
,
5962 .clk
= "ocp_abe_iclk",
5963 .addr
= omap44xx_timer7_addrs
,
5964 .user
= OCP_USER_MPU
,
5967 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs
[] = {
5969 .pa_start
= 0x4903c000,
5970 .pa_end
= 0x4903c07f,
5971 .flags
= ADDR_TYPE_RT
5976 /* l4_abe -> timer7 (dma) */
5977 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma
= {
5978 .master
= &omap44xx_l4_abe_hwmod
,
5979 .slave
= &omap44xx_timer7_hwmod
,
5980 .clk
= "ocp_abe_iclk",
5981 .addr
= omap44xx_timer7_dma_addrs
,
5982 .user
= OCP_USER_SDMA
,
5985 static struct omap_hwmod_addr_space omap44xx_timer8_addrs
[] = {
5987 .pa_start
= 0x4013e000,
5988 .pa_end
= 0x4013e07f,
5989 .flags
= ADDR_TYPE_RT
5994 /* l4_abe -> timer8 */
5995 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8
= {
5996 .master
= &omap44xx_l4_abe_hwmod
,
5997 .slave
= &omap44xx_timer8_hwmod
,
5998 .clk
= "ocp_abe_iclk",
5999 .addr
= omap44xx_timer8_addrs
,
6000 .user
= OCP_USER_MPU
,
6003 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs
[] = {
6005 .pa_start
= 0x4903e000,
6006 .pa_end
= 0x4903e07f,
6007 .flags
= ADDR_TYPE_RT
6012 /* l4_abe -> timer8 (dma) */
6013 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma
= {
6014 .master
= &omap44xx_l4_abe_hwmod
,
6015 .slave
= &omap44xx_timer8_hwmod
,
6016 .clk
= "ocp_abe_iclk",
6017 .addr
= omap44xx_timer8_dma_addrs
,
6018 .user
= OCP_USER_SDMA
,
6021 static struct omap_hwmod_addr_space omap44xx_timer9_addrs
[] = {
6023 .pa_start
= 0x4803e000,
6024 .pa_end
= 0x4803e07f,
6025 .flags
= ADDR_TYPE_RT
6030 /* l4_per -> timer9 */
6031 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9
= {
6032 .master
= &omap44xx_l4_per_hwmod
,
6033 .slave
= &omap44xx_timer9_hwmod
,
6035 .addr
= omap44xx_timer9_addrs
,
6036 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6039 static struct omap_hwmod_addr_space omap44xx_timer10_addrs
[] = {
6041 .pa_start
= 0x48086000,
6042 .pa_end
= 0x4808607f,
6043 .flags
= ADDR_TYPE_RT
6048 /* l4_per -> timer10 */
6049 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10
= {
6050 .master
= &omap44xx_l4_per_hwmod
,
6051 .slave
= &omap44xx_timer10_hwmod
,
6053 .addr
= omap44xx_timer10_addrs
,
6054 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6057 static struct omap_hwmod_addr_space omap44xx_timer11_addrs
[] = {
6059 .pa_start
= 0x48088000,
6060 .pa_end
= 0x4808807f,
6061 .flags
= ADDR_TYPE_RT
6066 /* l4_per -> timer11 */
6067 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11
= {
6068 .master
= &omap44xx_l4_per_hwmod
,
6069 .slave
= &omap44xx_timer11_hwmod
,
6071 .addr
= omap44xx_timer11_addrs
,
6072 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6075 static struct omap_hwmod_addr_space omap44xx_uart1_addrs
[] = {
6077 .pa_start
= 0x4806a000,
6078 .pa_end
= 0x4806a0ff,
6079 .flags
= ADDR_TYPE_RT
6084 /* l4_per -> uart1 */
6085 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1
= {
6086 .master
= &omap44xx_l4_per_hwmod
,
6087 .slave
= &omap44xx_uart1_hwmod
,
6089 .addr
= omap44xx_uart1_addrs
,
6090 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6093 static struct omap_hwmod_addr_space omap44xx_uart2_addrs
[] = {
6095 .pa_start
= 0x4806c000,
6096 .pa_end
= 0x4806c0ff,
6097 .flags
= ADDR_TYPE_RT
6102 /* l4_per -> uart2 */
6103 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2
= {
6104 .master
= &omap44xx_l4_per_hwmod
,
6105 .slave
= &omap44xx_uart2_hwmod
,
6107 .addr
= omap44xx_uart2_addrs
,
6108 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6111 static struct omap_hwmod_addr_space omap44xx_uart3_addrs
[] = {
6113 .pa_start
= 0x48020000,
6114 .pa_end
= 0x480200ff,
6115 .flags
= ADDR_TYPE_RT
6120 /* l4_per -> uart3 */
6121 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3
= {
6122 .master
= &omap44xx_l4_per_hwmod
,
6123 .slave
= &omap44xx_uart3_hwmod
,
6125 .addr
= omap44xx_uart3_addrs
,
6126 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6129 static struct omap_hwmod_addr_space omap44xx_uart4_addrs
[] = {
6131 .pa_start
= 0x4806e000,
6132 .pa_end
= 0x4806e0ff,
6133 .flags
= ADDR_TYPE_RT
6138 /* l4_per -> uart4 */
6139 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4
= {
6140 .master
= &omap44xx_l4_per_hwmod
,
6141 .slave
= &omap44xx_uart4_hwmod
,
6143 .addr
= omap44xx_uart4_addrs
,
6144 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6147 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs
[] = {
6149 .pa_start
= 0x4a0a9000,
6150 .pa_end
= 0x4a0a93ff,
6151 .flags
= ADDR_TYPE_RT
6156 /* l4_cfg -> usb_host_fs */
6157 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs
= {
6158 .master
= &omap44xx_l4_cfg_hwmod
,
6159 .slave
= &omap44xx_usb_host_fs_hwmod
,
6161 .addr
= omap44xx_usb_host_fs_addrs
,
6162 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6165 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs
[] = {
6168 .pa_start
= 0x4a064000,
6169 .pa_end
= 0x4a0647ff,
6170 .flags
= ADDR_TYPE_RT
6174 .pa_start
= 0x4a064800,
6175 .pa_end
= 0x4a064bff,
6179 .pa_start
= 0x4a064c00,
6180 .pa_end
= 0x4a064fff,
6185 /* l4_cfg -> usb_host_hs */
6186 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs
= {
6187 .master
= &omap44xx_l4_cfg_hwmod
,
6188 .slave
= &omap44xx_usb_host_hs_hwmod
,
6190 .addr
= omap44xx_usb_host_hs_addrs
,
6191 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6194 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs
[] = {
6196 .pa_start
= 0x4a0ab000,
6197 .pa_end
= 0x4a0ab7ff,
6198 .flags
= ADDR_TYPE_RT
6203 /* l4_cfg -> usb_otg_hs */
6204 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs
= {
6205 .master
= &omap44xx_l4_cfg_hwmod
,
6206 .slave
= &omap44xx_usb_otg_hs_hwmod
,
6208 .addr
= omap44xx_usb_otg_hs_addrs
,
6209 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6212 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs
[] = {
6215 .pa_start
= 0x4a062000,
6216 .pa_end
= 0x4a063fff,
6217 .flags
= ADDR_TYPE_RT
6222 /* l4_cfg -> usb_tll_hs */
6223 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs
= {
6224 .master
= &omap44xx_l4_cfg_hwmod
,
6225 .slave
= &omap44xx_usb_tll_hs_hwmod
,
6227 .addr
= omap44xx_usb_tll_hs_addrs
,
6228 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6231 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs
[] = {
6233 .pa_start
= 0x4a314000,
6234 .pa_end
= 0x4a31407f,
6235 .flags
= ADDR_TYPE_RT
6240 /* l4_wkup -> wd_timer2 */
6241 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2
= {
6242 .master
= &omap44xx_l4_wkup_hwmod
,
6243 .slave
= &omap44xx_wd_timer2_hwmod
,
6244 .clk
= "l4_wkup_clk_mux_ck",
6245 .addr
= omap44xx_wd_timer2_addrs
,
6246 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6249 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs
[] = {
6251 .pa_start
= 0x40130000,
6252 .pa_end
= 0x4013007f,
6253 .flags
= ADDR_TYPE_RT
6258 /* l4_abe -> wd_timer3 */
6259 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3
= {
6260 .master
= &omap44xx_l4_abe_hwmod
,
6261 .slave
= &omap44xx_wd_timer3_hwmod
,
6262 .clk
= "ocp_abe_iclk",
6263 .addr
= omap44xx_wd_timer3_addrs
,
6264 .user
= OCP_USER_MPU
,
6267 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs
[] = {
6269 .pa_start
= 0x49030000,
6270 .pa_end
= 0x4903007f,
6271 .flags
= ADDR_TYPE_RT
6276 /* l4_abe -> wd_timer3 (dma) */
6277 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma
= {
6278 .master
= &omap44xx_l4_abe_hwmod
,
6279 .slave
= &omap44xx_wd_timer3_hwmod
,
6280 .clk
= "ocp_abe_iclk",
6281 .addr
= omap44xx_wd_timer3_dma_addrs
,
6282 .user
= OCP_USER_SDMA
,
6285 static struct omap_hwmod_ocp_if
*omap44xx_hwmod_ocp_ifs
[] __initdata
= {
6286 &omap44xx_c2c__c2c_target_fw
,
6287 &omap44xx_l4_cfg__c2c_target_fw
,
6288 &omap44xx_l3_main_1__dmm
,
6290 &omap44xx_c2c__emif_fw
,
6291 &omap44xx_dmm__emif_fw
,
6292 &omap44xx_l4_cfg__emif_fw
,
6293 &omap44xx_iva__l3_instr
,
6294 &omap44xx_l3_main_3__l3_instr
,
6295 &omap44xx_ocp_wp_noc__l3_instr
,
6296 &omap44xx_dsp__l3_main_1
,
6297 &omap44xx_dss__l3_main_1
,
6298 &omap44xx_l3_main_2__l3_main_1
,
6299 &omap44xx_l4_cfg__l3_main_1
,
6300 &omap44xx_mmc1__l3_main_1
,
6301 &omap44xx_mmc2__l3_main_1
,
6302 &omap44xx_mpu__l3_main_1
,
6303 &omap44xx_c2c_target_fw__l3_main_2
,
6304 &omap44xx_debugss__l3_main_2
,
6305 &omap44xx_dma_system__l3_main_2
,
6306 &omap44xx_fdif__l3_main_2
,
6307 &omap44xx_gpu__l3_main_2
,
6308 &omap44xx_hsi__l3_main_2
,
6309 &omap44xx_ipu__l3_main_2
,
6310 &omap44xx_iss__l3_main_2
,
6311 &omap44xx_iva__l3_main_2
,
6312 &omap44xx_l3_main_1__l3_main_2
,
6313 &omap44xx_l4_cfg__l3_main_2
,
6314 /* &omap44xx_usb_host_fs__l3_main_2, */
6315 &omap44xx_usb_host_hs__l3_main_2
,
6316 &omap44xx_usb_otg_hs__l3_main_2
,
6317 &omap44xx_l3_main_1__l3_main_3
,
6318 &omap44xx_l3_main_2__l3_main_3
,
6319 &omap44xx_l4_cfg__l3_main_3
,
6320 &omap44xx_aess__l4_abe
,
6321 &omap44xx_dsp__l4_abe
,
6322 &omap44xx_l3_main_1__l4_abe
,
6323 &omap44xx_mpu__l4_abe
,
6324 &omap44xx_l3_main_1__l4_cfg
,
6325 &omap44xx_l3_main_2__l4_per
,
6326 &omap44xx_l4_cfg__l4_wkup
,
6327 &omap44xx_mpu__mpu_private
,
6328 &omap44xx_l4_cfg__ocp_wp_noc
,
6329 &omap44xx_l4_abe__aess
,
6330 &omap44xx_l4_abe__aess_dma
,
6331 &omap44xx_l3_main_2__c2c
,
6332 &omap44xx_l4_wkup__counter_32k
,
6333 &omap44xx_l4_cfg__ctrl_module_core
,
6334 &omap44xx_l4_cfg__ctrl_module_pad_core
,
6335 &omap44xx_l4_wkup__ctrl_module_wkup
,
6336 &omap44xx_l4_wkup__ctrl_module_pad_wkup
,
6337 &omap44xx_l3_instr__debugss
,
6338 &omap44xx_l4_cfg__dma_system
,
6339 &omap44xx_l4_abe__dmic
,
6340 &omap44xx_l4_abe__dmic_dma
,
6342 /* &omap44xx_dsp__sl2if, */
6343 &omap44xx_l4_cfg__dsp
,
6344 &omap44xx_l3_main_2__dss
,
6345 &omap44xx_l4_per__dss
,
6346 &omap44xx_l3_main_2__dss_dispc
,
6347 &omap44xx_l4_per__dss_dispc
,
6348 &omap44xx_l3_main_2__dss_dsi1
,
6349 &omap44xx_l4_per__dss_dsi1
,
6350 &omap44xx_l3_main_2__dss_dsi2
,
6351 &omap44xx_l4_per__dss_dsi2
,
6352 &omap44xx_l3_main_2__dss_hdmi
,
6353 &omap44xx_l4_per__dss_hdmi
,
6354 &omap44xx_l3_main_2__dss_rfbi
,
6355 &omap44xx_l4_per__dss_rfbi
,
6356 &omap44xx_l3_main_2__dss_venc
,
6357 &omap44xx_l4_per__dss_venc
,
6358 &omap44xx_l4_per__elm
,
6359 &omap44xx_emif_fw__emif1
,
6360 &omap44xx_emif_fw__emif2
,
6361 &omap44xx_l4_cfg__fdif
,
6362 &omap44xx_l4_wkup__gpio1
,
6363 &omap44xx_l4_per__gpio2
,
6364 &omap44xx_l4_per__gpio3
,
6365 &omap44xx_l4_per__gpio4
,
6366 &omap44xx_l4_per__gpio5
,
6367 &omap44xx_l4_per__gpio6
,
6368 &omap44xx_l3_main_2__gpmc
,
6369 &omap44xx_l3_main_2__gpu
,
6370 &omap44xx_l4_per__hdq1w
,
6371 &omap44xx_l4_cfg__hsi
,
6372 &omap44xx_l4_per__i2c1
,
6373 &omap44xx_l4_per__i2c2
,
6374 &omap44xx_l4_per__i2c3
,
6375 &omap44xx_l4_per__i2c4
,
6376 &omap44xx_l3_main_2__ipu
,
6377 &omap44xx_l3_main_2__iss
,
6378 /* &omap44xx_iva__sl2if, */
6379 &omap44xx_l3_main_2__iva
,
6380 &omap44xx_l4_wkup__kbd
,
6381 &omap44xx_l4_cfg__mailbox
,
6382 &omap44xx_l4_abe__mcasp
,
6383 &omap44xx_l4_abe__mcasp_dma
,
6384 &omap44xx_l4_abe__mcbsp1
,
6385 &omap44xx_l4_abe__mcbsp1_dma
,
6386 &omap44xx_l4_abe__mcbsp2
,
6387 &omap44xx_l4_abe__mcbsp2_dma
,
6388 &omap44xx_l4_abe__mcbsp3
,
6389 &omap44xx_l4_abe__mcbsp3_dma
,
6390 &omap44xx_l4_per__mcbsp4
,
6391 &omap44xx_l4_abe__mcpdm
,
6392 &omap44xx_l4_abe__mcpdm_dma
,
6393 &omap44xx_l4_per__mcspi1
,
6394 &omap44xx_l4_per__mcspi2
,
6395 &omap44xx_l4_per__mcspi3
,
6396 &omap44xx_l4_per__mcspi4
,
6397 &omap44xx_l4_per__mmc1
,
6398 &omap44xx_l4_per__mmc2
,
6399 &omap44xx_l4_per__mmc3
,
6400 &omap44xx_l4_per__mmc4
,
6401 &omap44xx_l4_per__mmc5
,
6402 &omap44xx_l3_main_2__mmu_ipu
,
6403 &omap44xx_l4_cfg__mmu_dsp
,
6404 &omap44xx_l3_main_2__ocmc_ram
,
6405 &omap44xx_l4_cfg__ocp2scp_usb_phy
,
6406 &omap44xx_mpu_private__prcm_mpu
,
6407 &omap44xx_l4_wkup__cm_core_aon
,
6408 &omap44xx_l4_cfg__cm_core
,
6409 &omap44xx_l4_wkup__prm
,
6410 &omap44xx_l4_wkup__scrm
,
6411 /* &omap44xx_l3_main_2__sl2if, */
6412 &omap44xx_l4_abe__slimbus1
,
6413 &omap44xx_l4_abe__slimbus1_dma
,
6414 &omap44xx_l4_per__slimbus2
,
6415 &omap44xx_l4_cfg__smartreflex_core
,
6416 &omap44xx_l4_cfg__smartreflex_iva
,
6417 &omap44xx_l4_cfg__smartreflex_mpu
,
6418 &omap44xx_l4_cfg__spinlock
,
6419 &omap44xx_l4_wkup__timer1
,
6420 &omap44xx_l4_per__timer2
,
6421 &omap44xx_l4_per__timer3
,
6422 &omap44xx_l4_per__timer4
,
6423 &omap44xx_l4_abe__timer5
,
6424 &omap44xx_l4_abe__timer5_dma
,
6425 &omap44xx_l4_abe__timer6
,
6426 &omap44xx_l4_abe__timer6_dma
,
6427 &omap44xx_l4_abe__timer7
,
6428 &omap44xx_l4_abe__timer7_dma
,
6429 &omap44xx_l4_abe__timer8
,
6430 &omap44xx_l4_abe__timer8_dma
,
6431 &omap44xx_l4_per__timer9
,
6432 &omap44xx_l4_per__timer10
,
6433 &omap44xx_l4_per__timer11
,
6434 &omap44xx_l4_per__uart1
,
6435 &omap44xx_l4_per__uart2
,
6436 &omap44xx_l4_per__uart3
,
6437 &omap44xx_l4_per__uart4
,
6438 /* &omap44xx_l4_cfg__usb_host_fs, */
6439 &omap44xx_l4_cfg__usb_host_hs
,
6440 &omap44xx_l4_cfg__usb_otg_hs
,
6441 &omap44xx_l4_cfg__usb_tll_hs
,
6442 &omap44xx_l4_wkup__wd_timer2
,
6443 &omap44xx_l4_abe__wd_timer3
,
6444 &omap44xx_l4_abe__wd_timer3_dma
,
6448 int __init
omap44xx_hwmod_init(void)
6451 return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs
);