arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2010 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22
  23 #include <plat/omap_hwmod.h>
  24 #include <plat/cpu.h>
  25 #include <plat/gpio.h>
  26 #include <plat/dma.h>
  27
  28 #include "omap_hwmod_common_data.h"
  29
  30 #include "cm1_44xx.h"
  31 #include "cm2_44xx.h"
  32 #include "prm44xx.h"
  33 #include "prm-regbits-44xx.h"
  34 #include "wd_timer.h"
  35
  36 /* Base offset for all OMAP4 interrupts external to MPUSS */
  37 #define OMAP44XX_IRQ_GIC_START  32
  38
  39 /* Base offset for all OMAP4 dma requests */
  40 #define OMAP44XX_DMA_REQ_START  1
  41
  42 /* Backward references (IPs with Bus Master capability) */
  43 static struct omap_hwmod omap44xx_dma_system_hwmod;
  44 static struct omap_hwmod omap44xx_dmm_hwmod;
  45 static struct omap_hwmod omap44xx_dsp_hwmod;
  46 static struct omap_hwmod omap44xx_emif_fw_hwmod;
  47 static struct omap_hwmod omap44xx_iva_hwmod;
  48 static struct omap_hwmod omap44xx_l3_instr_hwmod;
  49 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
  50 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
  51 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
  52 static struct omap_hwmod omap44xx_l4_abe_hwmod;
  53 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
  54 static struct omap_hwmod omap44xx_l4_per_hwmod;
  55 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
  56 static struct omap_hwmod omap44xx_mpu_hwmod;
  57 static struct omap_hwmod omap44xx_mpu_private_hwmod;
  58
  59 /*
  60  * Interconnects omap_hwmod structures
  61  * hwmods that compose the global OMAP interconnect
  62  */
  63
  64 /*
  65  * 'dmm' class
  66  * instance(s): dmm
  67  */
  68 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  69         .name   = "dmm",
  70 };
  71
  72 /* dmm interface data */
  73 /* l3_main_1 -> dmm */
  74 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
  75         .master         = &omap44xx_l3_main_1_hwmod,
  76         .slave          = &omap44xx_dmm_hwmod,
  77         .clk            = "l3_div_ck",
  78         .user           = OCP_USER_SDMA,
  79 };
  80
  81 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
  82         {
  83                 .pa_start       = 0x4e000000,
  84                 .pa_end         = 0x4e0007ff,
  85                 .flags          = ADDR_TYPE_RT
  86         },
  87 };
  88
  89 /* mpu -> dmm */
  90 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
  91         .master         = &omap44xx_mpu_hwmod,
  92         .slave          = &omap44xx_dmm_hwmod,
  93         .clk            = "l3_div_ck",
  94         .addr           = omap44xx_dmm_addrs,
  95         .addr_cnt       = ARRAY_SIZE(omap44xx_dmm_addrs),
  96         .user           = OCP_USER_MPU,
  97 };
  98
  99 /* dmm slave ports */
 100 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
 101         &omap44xx_l3_main_1__dmm,
 102         &omap44xx_mpu__dmm,
 103 };
 104
 105 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
 106         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
 107 };
 108
 109 static struct omap_hwmod omap44xx_dmm_hwmod = {
 110         .name           = "dmm",
 111         .class          = &omap44xx_dmm_hwmod_class,
 112         .slaves         = omap44xx_dmm_slaves,
 113         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmm_slaves),
 114         .mpu_irqs       = omap44xx_dmm_irqs,
 115         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dmm_irqs),
 116         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 117 };
 118
 119 /*
 120  * 'emif_fw' class
 121  * instance(s): emif_fw
 122  */
 123 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 124         .name   = "emif_fw",
 125 };
 126
 127 /* emif_fw interface data */
 128 /* dmm -> emif_fw */
 129 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
 130         .master         = &omap44xx_dmm_hwmod,
 131         .slave          = &omap44xx_emif_fw_hwmod,
 132         .clk            = "l3_div_ck",
 133         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 134 };
 135
 136 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
 137         {
 138                 .pa_start       = 0x4a20c000,
 139                 .pa_end         = 0x4a20c0ff,
 140                 .flags          = ADDR_TYPE_RT
 141         },
 142 };
 143
 144 /* l4_cfg -> emif_fw */
 145 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
 146         .master         = &omap44xx_l4_cfg_hwmod,
 147         .slave          = &omap44xx_emif_fw_hwmod,
 148         .clk            = "l4_div_ck",
 149         .addr           = omap44xx_emif_fw_addrs,
 150         .addr_cnt       = ARRAY_SIZE(omap44xx_emif_fw_addrs),
 151         .user           = OCP_USER_MPU,
 152 };
 153
 154 /* emif_fw slave ports */
 155 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
 156         &omap44xx_dmm__emif_fw,
 157         &omap44xx_l4_cfg__emif_fw,
 158 };
 159
 160 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 161         .name           = "emif_fw",
 162         .class          = &omap44xx_emif_fw_hwmod_class,
 163         .slaves         = omap44xx_emif_fw_slaves,
 164         .slaves_cnt     = ARRAY_SIZE(omap44xx_emif_fw_slaves),
 165         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 166 };
 167
 168 /*
 169  * 'l3' class
 170  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 171  */
 172 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 173         .name   = "l3",
 174 };
 175
 176 /* l3_instr interface data */
 177 /* iva -> l3_instr */
 178 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
 179         .master         = &omap44xx_iva_hwmod,
 180         .slave          = &omap44xx_l3_instr_hwmod,
 181         .clk            = "l3_div_ck",
 182         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 183 };
 184
 185 /* l3_main_3 -> l3_instr */
 186 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
 187         .master         = &omap44xx_l3_main_3_hwmod,
 188         .slave          = &omap44xx_l3_instr_hwmod,
 189         .clk            = "l3_div_ck",
 190         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 191 };
 192
 193 /* l3_instr slave ports */
 194 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
 195         &omap44xx_iva__l3_instr,
 196         &omap44xx_l3_main_3__l3_instr,
 197 };
 198
 199 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 200         .name           = "l3_instr",
 201         .class          = &omap44xx_l3_hwmod_class,
 202         .slaves         = omap44xx_l3_instr_slaves,
 203         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_instr_slaves),
 204         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 205 };
 206
 207 /* l3_main_1 interface data */
 208 /* dsp -> l3_main_1 */
 209 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
 210         .master         = &omap44xx_dsp_hwmod,
 211         .slave          = &omap44xx_l3_main_1_hwmod,
 212         .clk            = "l3_div_ck",
 213         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 214 };
 215
 216 /* l3_main_2 -> l3_main_1 */
 217 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
 218         .master         = &omap44xx_l3_main_2_hwmod,
 219         .slave          = &omap44xx_l3_main_1_hwmod,
 220         .clk            = "l3_div_ck",
 221         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 222 };
 223
 224 /* l4_cfg -> l3_main_1 */
 225 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
 226         .master         = &omap44xx_l4_cfg_hwmod,
 227         .slave          = &omap44xx_l3_main_1_hwmod,
 228         .clk            = "l4_div_ck",
 229         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 230 };
 231
 232 /* mpu -> l3_main_1 */
 233 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
 234         .master         = &omap44xx_mpu_hwmod,
 235         .slave          = &omap44xx_l3_main_1_hwmod,
 236         .clk            = "l3_div_ck",
 237         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 238 };
 239
 240 /* l3_main_1 slave ports */
 241 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
 242         &omap44xx_dsp__l3_main_1,
 243         &omap44xx_l3_main_2__l3_main_1,
 244         &omap44xx_l4_cfg__l3_main_1,
 245         &omap44xx_mpu__l3_main_1,
 246 };
 247
 248 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 249         .name           = "l3_main_1",
 250         .class          = &omap44xx_l3_hwmod_class,
 251         .slaves         = omap44xx_l3_main_1_slaves,
 252         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
 253         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 254 };
 255
 256 /* l3_main_2 interface data */
 257 /* dma_system -> l3_main_2 */
 258 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
 259         .master         = &omap44xx_dma_system_hwmod,
 260         .slave          = &omap44xx_l3_main_2_hwmod,
 261         .clk            = "l3_div_ck",
 262         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 263 };
 264
 265 /* iva -> l3_main_2 */
 266 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
 267         .master         = &omap44xx_iva_hwmod,
 268         .slave          = &omap44xx_l3_main_2_hwmod,
 269         .clk            = "l3_div_ck",
 270         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 271 };
 272
 273 /* l3_main_1 -> l3_main_2 */
 274 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
 275         .master         = &omap44xx_l3_main_1_hwmod,
 276         .slave          = &omap44xx_l3_main_2_hwmod,
 277         .clk            = "l3_div_ck",
 278         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 279 };
 280
 281 /* l4_cfg -> l3_main_2 */
 282 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
 283         .master         = &omap44xx_l4_cfg_hwmod,
 284         .slave          = &omap44xx_l3_main_2_hwmod,
 285         .clk            = "l4_div_ck",
 286         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 287 };
 288
 289 /* l3_main_2 slave ports */
 290 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
 291         &omap44xx_dma_system__l3_main_2,
 292         &omap44xx_iva__l3_main_2,
 293         &omap44xx_l3_main_1__l3_main_2,
 294         &omap44xx_l4_cfg__l3_main_2,
 295 };
 296
 297 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 298         .name           = "l3_main_2",
 299         .class          = &omap44xx_l3_hwmod_class,
 300         .slaves         = omap44xx_l3_main_2_slaves,
 301         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
 302         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 303 };
 304
 305 /* l3_main_3 interface data */
 306 /* l3_main_1 -> l3_main_3 */
 307 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
 308         .master         = &omap44xx_l3_main_1_hwmod,
 309         .slave          = &omap44xx_l3_main_3_hwmod,
 310         .clk            = "l3_div_ck",
 311         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 312 };
 313
 314 /* l3_main_2 -> l3_main_3 */
 315 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
 316         .master         = &omap44xx_l3_main_2_hwmod,
 317         .slave          = &omap44xx_l3_main_3_hwmod,
 318         .clk            = "l3_div_ck",
 319         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 320 };
 321
 322 /* l4_cfg -> l3_main_3 */
 323 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
 324         .master         = &omap44xx_l4_cfg_hwmod,
 325         .slave          = &omap44xx_l3_main_3_hwmod,
 326         .clk            = "l4_div_ck",
 327         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 328 };
 329
 330 /* l3_main_3 slave ports */
 331 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
 332         &omap44xx_l3_main_1__l3_main_3,
 333         &omap44xx_l3_main_2__l3_main_3,
 334         &omap44xx_l4_cfg__l3_main_3,
 335 };
 336
 337 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 338         .name           = "l3_main_3",
 339         .class          = &omap44xx_l3_hwmod_class,
 340         .slaves         = omap44xx_l3_main_3_slaves,
 341         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
 342         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 343 };
 344
 345 /*
 346  * 'l4' class
 347  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 348  */
 349 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 350         .name   = "l4",
 351 };
 352
 353 /* l4_abe interface data */
 354 /* dsp -> l4_abe */
 355 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
 356         .master         = &omap44xx_dsp_hwmod,
 357         .slave          = &omap44xx_l4_abe_hwmod,
 358         .clk            = "ocp_abe_iclk",
 359         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 360 };
 361
 362 /* l3_main_1 -> l4_abe */
 363 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
 364         .master         = &omap44xx_l3_main_1_hwmod,
 365         .slave          = &omap44xx_l4_abe_hwmod,
 366         .clk            = "l3_div_ck",
 367         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 368 };
 369
 370 /* mpu -> l4_abe */
 371 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
 372         .master         = &omap44xx_mpu_hwmod,
 373         .slave          = &omap44xx_l4_abe_hwmod,
 374         .clk            = "ocp_abe_iclk",
 375         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 376 };
 377
 378 /* l4_abe slave ports */
 379 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
 380         &omap44xx_dsp__l4_abe,
 381         &omap44xx_l3_main_1__l4_abe,
 382         &omap44xx_mpu__l4_abe,
 383 };
 384
 385 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 386         .name           = "l4_abe",
 387         .class          = &omap44xx_l4_hwmod_class,
 388         .slaves         = omap44xx_l4_abe_slaves,
 389         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_abe_slaves),
 390         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 391 };
 392
 393 /* l4_cfg interface data */
 394 /* l3_main_1 -> l4_cfg */
 395 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
 396         .master         = &omap44xx_l3_main_1_hwmod,
 397         .slave          = &omap44xx_l4_cfg_hwmod,
 398         .clk            = "l3_div_ck",
 399         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 400 };
 401
 402 /* l4_cfg slave ports */
 403 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
 404         &omap44xx_l3_main_1__l4_cfg,
 405 };
 406
 407 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 408         .name           = "l4_cfg",
 409         .class          = &omap44xx_l4_hwmod_class,
 410         .slaves         = omap44xx_l4_cfg_slaves,
 411         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
 412         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 413 };
 414
 415 /* l4_per interface data */
 416 /* l3_main_2 -> l4_per */
 417 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
 418         .master         = &omap44xx_l3_main_2_hwmod,
 419         .slave          = &omap44xx_l4_per_hwmod,
 420         .clk            = "l3_div_ck",
 421         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 422 };
 423
 424 /* l4_per slave ports */
 425 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
 426         &omap44xx_l3_main_2__l4_per,
 427 };
 428
 429 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 430         .name           = "l4_per",
 431         .class          = &omap44xx_l4_hwmod_class,
 432         .slaves         = omap44xx_l4_per_slaves,
 433         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_per_slaves),
 434         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 435 };
 436
 437 /* l4_wkup interface data */
 438 /* l4_cfg -> l4_wkup */
 439 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
 440         .master         = &omap44xx_l4_cfg_hwmod,
 441         .slave          = &omap44xx_l4_wkup_hwmod,
 442         .clk            = "l4_div_ck",
 443         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 444 };
 445
 446 /* l4_wkup slave ports */
 447 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
 448         &omap44xx_l4_cfg__l4_wkup,
 449 };
 450
 451 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 452         .name           = "l4_wkup",
 453         .class          = &omap44xx_l4_hwmod_class,
 454         .slaves         = omap44xx_l4_wkup_slaves,
 455         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
 456         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 457 };
 458
 459 /*
 460  * 'mpu_bus' class
 461  * instance(s): mpu_private
 462  */
 463 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 464         .name   = "mpu_bus",
 465 };
 466
 467 /* mpu_private interface data */
 468 /* mpu -> mpu_private */
 469 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
 470         .master         = &omap44xx_mpu_hwmod,
 471         .slave          = &omap44xx_mpu_private_hwmod,
 472         .clk            = "l3_div_ck",
 473         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 474 };
 475
 476 /* mpu_private slave ports */
 477 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
 478         &omap44xx_mpu__mpu_private,
 479 };
 480
 481 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 482         .name           = "mpu_private",
 483         .class          = &omap44xx_mpu_bus_hwmod_class,
 484         .slaves         = omap44xx_mpu_private_slaves,
 485         .slaves_cnt     = ARRAY_SIZE(omap44xx_mpu_private_slaves),
 486         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 487 };
 488
 489 /*
 490  * Modules omap_hwmod structures
 491  *
 492  * The following IPs are excluded for the moment because:
 493  * - They do not need an explicit SW control using omap_hwmod API.
 494  * - They still need to be validated with the driver
 495  *   properly adapted to omap_hwmod / omap_device
 496  *
 497  *  aess
 498  *  bandgap
 499  *  c2c
 500  *  c2c_target_fw
 501  *  cm_core
 502  *  cm_core_aon
 503  *  counter_32k
 504  *  ctrl_module_core
 505  *  ctrl_module_pad_core
 506  *  ctrl_module_pad_wkup
 507  *  ctrl_module_wkup
 508  *  debugss
 509  *  dmic
 510  *  dss
 511  *  dss_dispc
 512  *  dss_dsi1
 513  *  dss_dsi2
 514  *  dss_hdmi
 515  *  dss_rfbi
 516  *  dss_venc
 517  *  efuse_ctrl_cust
 518  *  efuse_ctrl_std
 519  *  elm
 520  *  emif1
 521  *  emif2
 522  *  fdif
 523  *  gpmc
 524  *  gpu
 525  *  hdq1w
 526  *  hsi
 527  *  ipu
 528  *  iss
 529  *  kbd
 530  *  mailbox
 531  *  mcasp
 532  *  mcbsp1
 533  *  mcbsp2
 534  *  mcbsp3
 535  *  mcbsp4
 536  *  mcpdm
 537  *  mcspi1
 538  *  mcspi2
 539  *  mcspi3
 540  *  mcspi4
 541  *  mmc1
 542  *  mmc2
 543  *  mmc3
 544  *  mmc4
 545  *  mmc5
 546  *  mpu_c0
 547  *  mpu_c1
 548  *  ocmc_ram
 549  *  ocp2scp_usb_phy
 550  *  ocp_wp_noc
 551  *  prcm
 552  *  prcm_mpu
 553  *  prm
 554  *  scrm
 555  *  sl2if
 556  *  slimbus1
 557  *  slimbus2
 558  *  spinlock
 559  *  timer1
 560  *  timer10
 561  *  timer11
 562  *  timer2
 563  *  timer3
 564  *  timer4
 565  *  timer5
 566  *  timer6
 567  *  timer7
 568  *  timer8
 569  *  timer9
 570  *  usb_host_fs
 571  *  usb_host_hs
 572  *  usb_otg_hs
 573  *  usb_phy_cm
 574  *  usb_tll_hs
 575  *  usim
 576  */
 577
 578 /*
 579  * 'dma' class
 580  * dma controller for data exchange between memory to memory (i.e. internal or
 581  * external memory) and gp peripherals to memory or memory to gp peripherals
 582  */
 583
 584 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 585         .rev_offs       = 0x0000,
 586         .sysc_offs      = 0x002c,
 587         .syss_offs      = 0x0028,
 588         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 589                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 590                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 591                            SYSS_HAS_RESET_STATUS),
 592         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 593                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 594         .sysc_fields    = &omap_hwmod_sysc_type1,
 595 };
 596
 597 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 598         .name   = "dma",
 599         .sysc   = &omap44xx_dma_sysc,
 600 };
 601
 602 /* dma dev_attr */
 603 static struct omap_dma_dev_attr dma_dev_attr = {
 604         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 605                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 606         .lch_count      = 32,
 607 };
 608
 609 /* dma_system */
 610 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 611         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 612         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 613         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 614         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 615 };
 616
 617 /* dma_system master ports */
 618 static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
 619         &omap44xx_dma_system__l3_main_2,
 620 };
 621
 622 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
 623         {
 624                 .pa_start       = 0x4a056000,
 625                 .pa_end         = 0x4a0560ff,
 626                 .flags          = ADDR_TYPE_RT
 627         },
 628 };
 629
 630 /* l4_cfg -> dma_system */
 631 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
 632         .master         = &omap44xx_l4_cfg_hwmod,
 633         .slave          = &omap44xx_dma_system_hwmod,
 634         .clk            = "l4_div_ck",
 635         .addr           = omap44xx_dma_system_addrs,
 636         .addr_cnt       = ARRAY_SIZE(omap44xx_dma_system_addrs),
 637         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 638 };
 639
 640 /* dma_system slave ports */
 641 static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
 642         &omap44xx_l4_cfg__dma_system,
 643 };
 644
 645 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 646         .name           = "dma_system",
 647         .class          = &omap44xx_dma_hwmod_class,
 648         .mpu_irqs       = omap44xx_dma_system_irqs,
 649         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dma_system_irqs),
 650         .main_clk       = "l3_div_ck",
 651         .prcm = {
 652                 .omap4 = {
 653                         .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
 654                 },
 655         },
 656         .dev_attr       = &dma_dev_attr,
 657         .slaves         = omap44xx_dma_system_slaves,
 658         .slaves_cnt     = ARRAY_SIZE(omap44xx_dma_system_slaves),
 659         .masters        = omap44xx_dma_system_masters,
 660         .masters_cnt    = ARRAY_SIZE(omap44xx_dma_system_masters),
 661         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 662 };
 663
 664 /*
 665  * 'dsp' class
 666  * dsp sub-system
 667  */
 668
 669 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 670         .name   = "dsp",
 671 };
 672
 673 /* dsp */
 674 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 675         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
 676 };
 677
 678 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 679         { .name = "mmu_cache", .rst_shift = 1 },
 680 };
 681
 682 static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
 683         { .name = "dsp", .rst_shift = 0 },
 684 };
 685
 686 /* dsp -> iva */
 687 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
 688         .master         = &omap44xx_dsp_hwmod,
 689         .slave          = &omap44xx_iva_hwmod,
 690         .clk            = "dpll_iva_m5x2_ck",
 691 };
 692
 693 /* dsp master ports */
 694 static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
 695         &omap44xx_dsp__l3_main_1,
 696         &omap44xx_dsp__l4_abe,
 697         &omap44xx_dsp__iva,
 698 };
 699
 700 /* l4_cfg -> dsp */
 701 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
 702         .master         = &omap44xx_l4_cfg_hwmod,
 703         .slave          = &omap44xx_dsp_hwmod,
 704         .clk            = "l4_div_ck",
 705         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 706 };
 707
 708 /* dsp slave ports */
 709 static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
 710         &omap44xx_l4_cfg__dsp,
 711 };
 712
 713 /* Pseudo hwmod for reset control purpose only */
 714 static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
 715         .name           = "dsp_c0",
 716         .class          = &omap44xx_dsp_hwmod_class,
 717         .flags          = HWMOD_INIT_NO_RESET,
 718         .rst_lines      = omap44xx_dsp_c0_resets,
 719         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_c0_resets),
 720         .prcm = {
 721                 .omap4 = {
 722                         .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
 723                 },
 724         },
 725         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 726 };
 727
 728 static struct omap_hwmod omap44xx_dsp_hwmod = {
 729         .name           = "dsp",
 730         .class          = &omap44xx_dsp_hwmod_class,
 731         .mpu_irqs       = omap44xx_dsp_irqs,
 732         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dsp_irqs),
 733         .rst_lines      = omap44xx_dsp_resets,
 734         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 735         .main_clk       = "dsp_fck",
 736         .prcm = {
 737                 .omap4 = {
 738                         .clkctrl_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
 739                         .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
 740                 },
 741         },
 742         .slaves         = omap44xx_dsp_slaves,
 743         .slaves_cnt     = ARRAY_SIZE(omap44xx_dsp_slaves),
 744         .masters        = omap44xx_dsp_masters,
 745         .masters_cnt    = ARRAY_SIZE(omap44xx_dsp_masters),
 746         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 747 };
 748
 749 /*
 750  * 'gpio' class
 751  * general purpose io module
 752  */
 753
 754 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
 755         .rev_offs       = 0x0000,
 756         .sysc_offs      = 0x0010,
 757         .syss_offs      = 0x0114,
 758         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 759                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 760                            SYSS_HAS_RESET_STATUS),
 761         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 762                            SIDLE_SMART_WKUP),
 763         .sysc_fields    = &omap_hwmod_sysc_type1,
 764 };
 765
 766 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
 767         .name   = "gpio",
 768         .sysc   = &omap44xx_gpio_sysc,
 769         .rev    = 2,
 770 };
 771
 772 /* gpio dev_attr */
 773 static struct omap_gpio_dev_attr gpio_dev_attr = {
 774         .bank_width     = 32,
 775         .dbck_flag      = true,
 776 };
 777
 778 /* gpio1 */
 779 static struct omap_hwmod omap44xx_gpio1_hwmod;
 780 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
 781         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
 782 };
 783
 784 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
 785         {
 786                 .pa_start       = 0x4a310000,
 787                 .pa_end         = 0x4a3101ff,
 788                 .flags          = ADDR_TYPE_RT
 789         },
 790 };
 791
 792 /* l4_wkup -> gpio1 */
 793 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
 794         .master         = &omap44xx_l4_wkup_hwmod,
 795         .slave          = &omap44xx_gpio1_hwmod,
 796         .clk            = "l4_wkup_clk_mux_ck",
 797         .addr           = omap44xx_gpio1_addrs,
 798         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio1_addrs),
 799         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 800 };
 801
 802 /* gpio1 slave ports */
 803 static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
 804         &omap44xx_l4_wkup__gpio1,
 805 };
 806
 807 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 808         { .role = "dbclk", .clk = "gpio1_dbclk" },
 809 };
 810
 811 static struct omap_hwmod omap44xx_gpio1_hwmod = {
 812         .name           = "gpio1",
 813         .class          = &omap44xx_gpio_hwmod_class,
 814         .mpu_irqs       = omap44xx_gpio1_irqs,
 815         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio1_irqs),
 816         .main_clk       = "gpio1_ick",
 817         .prcm = {
 818                 .omap4 = {
 819                         .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
 820                 },
 821         },
 822         .opt_clks       = gpio1_opt_clks,
 823         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 824         .dev_attr       = &gpio_dev_attr,
 825         .slaves         = omap44xx_gpio1_slaves,
 826         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio1_slaves),
 827         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 828 };
 829
 830 /* gpio2 */
 831 static struct omap_hwmod omap44xx_gpio2_hwmod;
 832 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
 833         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
 834 };
 835
 836 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
 837         {
 838                 .pa_start       = 0x48055000,
 839                 .pa_end         = 0x480551ff,
 840                 .flags          = ADDR_TYPE_RT
 841         },
 842 };
 843
 844 /* l4_per -> gpio2 */
 845 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
 846         .master         = &omap44xx_l4_per_hwmod,
 847         .slave          = &omap44xx_gpio2_hwmod,
 848         .clk            = "l4_div_ck",
 849         .addr           = omap44xx_gpio2_addrs,
 850         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio2_addrs),
 851         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 852 };
 853
 854 /* gpio2 slave ports */
 855 static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
 856         &omap44xx_l4_per__gpio2,
 857 };
 858
 859 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 860         { .role = "dbclk", .clk = "gpio2_dbclk" },
 861 };
 862
 863 static struct omap_hwmod omap44xx_gpio2_hwmod = {
 864         .name           = "gpio2",
 865         .class          = &omap44xx_gpio_hwmod_class,
 866         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 867         .mpu_irqs       = omap44xx_gpio2_irqs,
 868         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio2_irqs),
 869         .main_clk       = "gpio2_ick",
 870         .prcm = {
 871                 .omap4 = {
 872                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
 873                 },
 874         },
 875         .opt_clks       = gpio2_opt_clks,
 876         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 877         .dev_attr       = &gpio_dev_attr,
 878         .slaves         = omap44xx_gpio2_slaves,
 879         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio2_slaves),
 880         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 881 };
 882
 883 /* gpio3 */
 884 static struct omap_hwmod omap44xx_gpio3_hwmod;
 885 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
 886         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
 887 };
 888
 889 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
 890         {
 891                 .pa_start       = 0x48057000,
 892                 .pa_end         = 0x480571ff,
 893                 .flags          = ADDR_TYPE_RT
 894         },
 895 };
 896
 897 /* l4_per -> gpio3 */
 898 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
 899         .master         = &omap44xx_l4_per_hwmod,
 900         .slave          = &omap44xx_gpio3_hwmod,
 901         .clk            = "l4_div_ck",
 902         .addr           = omap44xx_gpio3_addrs,
 903         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio3_addrs),
 904         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 905 };
 906
 907 /* gpio3 slave ports */
 908 static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
 909         &omap44xx_l4_per__gpio3,
 910 };
 911
 912 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 913         { .role = "dbclk", .clk = "gpio3_dbclk" },
 914 };
 915
 916 static struct omap_hwmod omap44xx_gpio3_hwmod = {
 917         .name           = "gpio3",
 918         .class          = &omap44xx_gpio_hwmod_class,
 919         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 920         .mpu_irqs       = omap44xx_gpio3_irqs,
 921         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio3_irqs),
 922         .main_clk       = "gpio3_ick",
 923         .prcm = {
 924                 .omap4 = {
 925                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
 926                 },
 927         },
 928         .opt_clks       = gpio3_opt_clks,
 929         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 930         .dev_attr       = &gpio_dev_attr,
 931         .slaves         = omap44xx_gpio3_slaves,
 932         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio3_slaves),
 933         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 934 };
 935
 936 /* gpio4 */
 937 static struct omap_hwmod omap44xx_gpio4_hwmod;
 938 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
 939         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
 940 };
 941
 942 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
 943         {
 944                 .pa_start       = 0x48059000,
 945                 .pa_end         = 0x480591ff,
 946                 .flags          = ADDR_TYPE_RT
 947         },
 948 };
 949
 950 /* l4_per -> gpio4 */
 951 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
 952         .master         = &omap44xx_l4_per_hwmod,
 953         .slave          = &omap44xx_gpio4_hwmod,
 954         .clk            = "l4_div_ck",
 955         .addr           = omap44xx_gpio4_addrs,
 956         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio4_addrs),
 957         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 958 };
 959
 960 /* gpio4 slave ports */
 961 static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
 962         &omap44xx_l4_per__gpio4,
 963 };
 964
 965 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 966         { .role = "dbclk", .clk = "gpio4_dbclk" },
 967 };
 968
 969 static struct omap_hwmod omap44xx_gpio4_hwmod = {
 970         .name           = "gpio4",
 971         .class          = &omap44xx_gpio_hwmod_class,
 972         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 973         .mpu_irqs       = omap44xx_gpio4_irqs,
 974         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio4_irqs),
 975         .main_clk       = "gpio4_ick",
 976         .prcm = {
 977                 .omap4 = {
 978                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
 979                 },
 980         },
 981         .opt_clks       = gpio4_opt_clks,
 982         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 983         .dev_attr       = &gpio_dev_attr,
 984         .slaves         = omap44xx_gpio4_slaves,
 985         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio4_slaves),
 986         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 987 };
 988
 989 /* gpio5 */
 990 static struct omap_hwmod omap44xx_gpio5_hwmod;
 991 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
 992         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
 993 };
 994
 995 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
 996         {
 997                 .pa_start       = 0x4805b000,
 998                 .pa_end         = 0x4805b1ff,
 999                 .flags          = ADDR_TYPE_RT
1000         },
1001 };
1002
1003 /* l4_per -> gpio5 */
1004 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
1005         .master         = &omap44xx_l4_per_hwmod,
1006         .slave          = &omap44xx_gpio5_hwmod,
1007         .clk            = "l4_div_ck",
1008         .addr           = omap44xx_gpio5_addrs,
1009         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio5_addrs),
1010         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1011 };
1012
1013 /* gpio5 slave ports */
1014 static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
1015         &omap44xx_l4_per__gpio5,
1016 };
1017
1018 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1019         { .role = "dbclk", .clk = "gpio5_dbclk" },
1020 };
1021
1022 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1023         .name           = "gpio5",
1024         .class          = &omap44xx_gpio_hwmod_class,
1025         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1026         .mpu_irqs       = omap44xx_gpio5_irqs,
1027         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio5_irqs),
1028         .main_clk       = "gpio5_ick",
1029         .prcm = {
1030                 .omap4 = {
1031                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1032                 },
1033         },
1034         .opt_clks       = gpio5_opt_clks,
1035         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1036         .dev_attr       = &gpio_dev_attr,
1037         .slaves         = omap44xx_gpio5_slaves,
1038         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio5_slaves),
1039         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1040 };
1041
1042 /* gpio6 */
1043 static struct omap_hwmod omap44xx_gpio6_hwmod;
1044 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1045         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1046 };
1047
1048 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
1049         {
1050                 .pa_start       = 0x4805d000,
1051                 .pa_end         = 0x4805d1ff,
1052                 .flags          = ADDR_TYPE_RT
1053         },
1054 };
1055
1056 /* l4_per -> gpio6 */
1057 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
1058         .master         = &omap44xx_l4_per_hwmod,
1059         .slave          = &omap44xx_gpio6_hwmod,
1060         .clk            = "l4_div_ck",
1061         .addr           = omap44xx_gpio6_addrs,
1062         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio6_addrs),
1063         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1064 };
1065
1066 /* gpio6 slave ports */
1067 static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
1068         &omap44xx_l4_per__gpio6,
1069 };
1070
1071 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1072         { .role = "dbclk", .clk = "gpio6_dbclk" },
1073 };
1074
1075 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1076         .name           = "gpio6",
1077         .class          = &omap44xx_gpio_hwmod_class,
1078         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1079         .mpu_irqs       = omap44xx_gpio6_irqs,
1080         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio6_irqs),
1081         .main_clk       = "gpio6_ick",
1082         .prcm = {
1083                 .omap4 = {
1084                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1085                 },
1086         },
1087         .opt_clks       = gpio6_opt_clks,
1088         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1089         .dev_attr       = &gpio_dev_attr,
1090         .slaves         = omap44xx_gpio6_slaves,
1091         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio6_slaves),
1092         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1093 };
1094
1095 /*
1096  * 'i2c' class
1097  * multimaster high-speed i2c controller
1098  */
1099
1100 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1101         .sysc_offs      = 0x0010,
1102         .syss_offs      = 0x0090,
1103         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1104                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1105                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1106         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1107                            SIDLE_SMART_WKUP),
1108         .sysc_fields    = &omap_hwmod_sysc_type1,
1109 };
1110
1111 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1112         .name   = "i2c",
1113         .sysc   = &omap44xx_i2c_sysc,
1114 };
1115
1116 /* i2c1 */
1117 static struct omap_hwmod omap44xx_i2c1_hwmod;
1118 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1119         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1120 };
1121
1122 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1123         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1124         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1125 };
1126
1127 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
1128         {
1129                 .pa_start       = 0x48070000,
1130                 .pa_end         = 0x480700ff,
1131                 .flags          = ADDR_TYPE_RT
1132         },
1133 };
1134
1135 /* l4_per -> i2c1 */
1136 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
1137         .master         = &omap44xx_l4_per_hwmod,
1138         .slave          = &omap44xx_i2c1_hwmod,
1139         .clk            = "l4_div_ck",
1140         .addr           = omap44xx_i2c1_addrs,
1141         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c1_addrs),
1142         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1143 };
1144
1145 /* i2c1 slave ports */
1146 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
1147         &omap44xx_l4_per__i2c1,
1148 };
1149
1150 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1151         .name           = "i2c1",
1152         .class          = &omap44xx_i2c_hwmod_class,
1153         .flags          = HWMOD_INIT_NO_RESET,
1154         .mpu_irqs       = omap44xx_i2c1_irqs,
1155         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c1_irqs),
1156         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
1157         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
1158         .main_clk       = "i2c1_fck",
1159         .prcm = {
1160                 .omap4 = {
1161                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
1162                 },
1163         },
1164         .slaves         = omap44xx_i2c1_slaves,
1165         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c1_slaves),
1166         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1167 };
1168
1169 /* i2c2 */
1170 static struct omap_hwmod omap44xx_i2c2_hwmod;
1171 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1172         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1173 };
1174
1175 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1176         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1177         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1178 };
1179
1180 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
1181         {
1182                 .pa_start       = 0x48072000,
1183                 .pa_end         = 0x480720ff,
1184                 .flags          = ADDR_TYPE_RT
1185         },
1186 };
1187
1188 /* l4_per -> i2c2 */
1189 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
1190         .master         = &omap44xx_l4_per_hwmod,
1191         .slave          = &omap44xx_i2c2_hwmod,
1192         .clk            = "l4_div_ck",
1193         .addr           = omap44xx_i2c2_addrs,
1194         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c2_addrs),
1195         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1196 };
1197
1198 /* i2c2 slave ports */
1199 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
1200         &omap44xx_l4_per__i2c2,
1201 };
1202
1203 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1204         .name           = "i2c2",
1205         .class          = &omap44xx_i2c_hwmod_class,
1206         .flags          = HWMOD_INIT_NO_RESET,
1207         .mpu_irqs       = omap44xx_i2c2_irqs,
1208         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c2_irqs),
1209         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
1210         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
1211         .main_clk       = "i2c2_fck",
1212         .prcm = {
1213                 .omap4 = {
1214                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
1215                 },
1216         },
1217         .slaves         = omap44xx_i2c2_slaves,
1218         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c2_slaves),
1219         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1220 };
1221
1222 /* i2c3 */
1223 static struct omap_hwmod omap44xx_i2c3_hwmod;
1224 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1225         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1226 };
1227
1228 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1229         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1230         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1231 };
1232
1233 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
1234         {
1235                 .pa_start       = 0x48060000,
1236                 .pa_end         = 0x480600ff,
1237                 .flags          = ADDR_TYPE_RT
1238         },
1239 };
1240
1241 /* l4_per -> i2c3 */
1242 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
1243         .master         = &omap44xx_l4_per_hwmod,
1244         .slave          = &omap44xx_i2c3_hwmod,
1245         .clk            = "l4_div_ck",
1246         .addr           = omap44xx_i2c3_addrs,
1247         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c3_addrs),
1248         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1249 };
1250
1251 /* i2c3 slave ports */
1252 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
1253         &omap44xx_l4_per__i2c3,
1254 };
1255
1256 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1257         .name           = "i2c3",
1258         .class          = &omap44xx_i2c_hwmod_class,
1259         .flags          = HWMOD_INIT_NO_RESET,
1260         .mpu_irqs       = omap44xx_i2c3_irqs,
1261         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c3_irqs),
1262         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
1263         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
1264         .main_clk       = "i2c3_fck",
1265         .prcm = {
1266                 .omap4 = {
1267                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
1268                 },
1269         },
1270         .slaves         = omap44xx_i2c3_slaves,
1271         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c3_slaves),
1272         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1273 };
1274
1275 /* i2c4 */
1276 static struct omap_hwmod omap44xx_i2c4_hwmod;
1277 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1278         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1279 };
1280
1281 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1282         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1283         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1284 };
1285
1286 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
1287         {
1288                 .pa_start       = 0x48350000,
1289                 .pa_end         = 0x483500ff,
1290                 .flags          = ADDR_TYPE_RT
1291         },
1292 };
1293
1294 /* l4_per -> i2c4 */
1295 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
1296         .master         = &omap44xx_l4_per_hwmod,
1297         .slave          = &omap44xx_i2c4_hwmod,
1298         .clk            = "l4_div_ck",
1299         .addr           = omap44xx_i2c4_addrs,
1300         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c4_addrs),
1301         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1302 };
1303
1304 /* i2c4 slave ports */
1305 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
1306         &omap44xx_l4_per__i2c4,
1307 };
1308
1309 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1310         .name           = "i2c4",
1311         .class          = &omap44xx_i2c_hwmod_class,
1312         .flags          = HWMOD_INIT_NO_RESET,
1313         .mpu_irqs       = omap44xx_i2c4_irqs,
1314         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c4_irqs),
1315         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
1316         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
1317         .main_clk       = "i2c4_fck",
1318         .prcm = {
1319                 .omap4 = {
1320                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
1321                 },
1322         },
1323         .slaves         = omap44xx_i2c4_slaves,
1324         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c4_slaves),
1325         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1326 };
1327
1328 /*
1329  * 'iva' class
1330  * multi-standard video encoder/decoder hardware accelerator
1331  */
1332
1333 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1334         .name   = "iva",
1335 };
1336
1337 /* iva */
1338 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1339         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1340         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1341         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1342 };
1343
1344 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1345         { .name = "logic", .rst_shift = 2 },
1346 };
1347
1348 static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
1349         { .name = "seq0", .rst_shift = 0 },
1350 };
1351
1352 static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
1353         { .name = "seq1", .rst_shift = 1 },
1354 };
1355
1356 /* iva master ports */
1357 static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
1358         &omap44xx_iva__l3_main_2,
1359         &omap44xx_iva__l3_instr,
1360 };
1361
1362 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
1363         {
1364                 .pa_start       = 0x5a000000,
1365                 .pa_end         = 0x5a07ffff,
1366                 .flags          = ADDR_TYPE_RT
1367         },
1368 };
1369
1370 /* l3_main_2 -> iva */
1371 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
1372         .master         = &omap44xx_l3_main_2_hwmod,
1373         .slave          = &omap44xx_iva_hwmod,
1374         .clk            = "l3_div_ck",
1375         .addr           = omap44xx_iva_addrs,
1376         .addr_cnt       = ARRAY_SIZE(omap44xx_iva_addrs),
1377         .user           = OCP_USER_MPU,
1378 };
1379
1380 /* iva slave ports */
1381 static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
1382         &omap44xx_dsp__iva,
1383         &omap44xx_l3_main_2__iva,
1384 };
1385
1386 /* Pseudo hwmod for reset control purpose only */
1387 static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
1388         .name           = "iva_seq0",
1389         .class          = &omap44xx_iva_hwmod_class,
1390         .flags          = HWMOD_INIT_NO_RESET,
1391         .rst_lines      = omap44xx_iva_seq0_resets,
1392         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq0_resets),
1393         .prcm = {
1394                 .omap4 = {
1395                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
1396                 },
1397         },
1398         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1399 };
1400
1401 /* Pseudo hwmod for reset control purpose only */
1402 static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
1403         .name           = "iva_seq1",
1404         .class          = &omap44xx_iva_hwmod_class,
1405         .flags          = HWMOD_INIT_NO_RESET,
1406         .rst_lines      = omap44xx_iva_seq1_resets,
1407         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq1_resets),
1408         .prcm = {
1409                 .omap4 = {
1410                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
1411                 },
1412         },
1413         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1414 };
1415
1416 static struct omap_hwmod omap44xx_iva_hwmod = {
1417         .name           = "iva",
1418         .class          = &omap44xx_iva_hwmod_class,
1419         .mpu_irqs       = omap44xx_iva_irqs,
1420         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_iva_irqs),
1421         .rst_lines      = omap44xx_iva_resets,
1422         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1423         .main_clk       = "iva_fck",
1424         .prcm = {
1425                 .omap4 = {
1426                         .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1427                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
1428                 },
1429         },
1430         .slaves         = omap44xx_iva_slaves,
1431         .slaves_cnt     = ARRAY_SIZE(omap44xx_iva_slaves),
1432         .masters        = omap44xx_iva_masters,
1433         .masters_cnt    = ARRAY_SIZE(omap44xx_iva_masters),
1434         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1435 };
1436
1437 /*
1438  * 'mpu' class
1439  * mpu sub-system
1440  */
1441
1442 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
1443         .name   = "mpu",
1444 };
1445
1446 /* mpu */
1447 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
1448         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
1449         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
1450         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
1451 };
1452
1453 /* mpu master ports */
1454 static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
1455         &omap44xx_mpu__l3_main_1,
1456         &omap44xx_mpu__l4_abe,
1457         &omap44xx_mpu__dmm,
1458 };
1459
1460 static struct omap_hwmod omap44xx_mpu_hwmod = {
1461         .name           = "mpu",
1462         .class          = &omap44xx_mpu_hwmod_class,
1463         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1464         .mpu_irqs       = omap44xx_mpu_irqs,
1465         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mpu_irqs),
1466         .main_clk       = "dpll_mpu_m2_ck",
1467         .prcm = {
1468                 .omap4 = {
1469                         .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
1470                 },
1471         },
1472         .masters        = omap44xx_mpu_masters,
1473         .masters_cnt    = ARRAY_SIZE(omap44xx_mpu_masters),
1474         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1475 };
1476
1477 /*
1478  * 'smartreflex' class
1479  * smartreflex module (monitor silicon performance and outputs a measure of
1480  * performance error)
1481  */
1482
1483 /* The IP is not compliant to type1 / type2 scheme */
1484 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
1485         .sidle_shift    = 24,
1486         .enwkup_shift   = 26,
1487 };
1488
1489 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
1490         .sysc_offs      = 0x0038,
1491         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1492         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1493                            SIDLE_SMART_WKUP),
1494         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
1495 };
1496
1497 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
1498         .name   = "smartreflex",
1499         .sysc   = &omap44xx_smartreflex_sysc,
1500         .rev    = 2,
1501 };
1502
1503 /* smartreflex_core */
1504 static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
1505 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
1506         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
1507 };
1508
1509 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
1510         {
1511                 .pa_start       = 0x4a0dd000,
1512                 .pa_end         = 0x4a0dd03f,
1513                 .flags          = ADDR_TYPE_RT
1514         },
1515 };
1516
1517 /* l4_cfg -> smartreflex_core */
1518 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
1519         .master         = &omap44xx_l4_cfg_hwmod,
1520         .slave          = &omap44xx_smartreflex_core_hwmod,
1521         .clk            = "l4_div_ck",
1522         .addr           = omap44xx_smartreflex_core_addrs,
1523         .addr_cnt       = ARRAY_SIZE(omap44xx_smartreflex_core_addrs),
1524         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1525 };
1526
1527 /* smartreflex_core slave ports */
1528 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
1529         &omap44xx_l4_cfg__smartreflex_core,
1530 };
1531
1532 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
1533         .name           = "smartreflex_core",
1534         .class          = &omap44xx_smartreflex_hwmod_class,
1535         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
1536         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_smartreflex_core_irqs),
1537         .main_clk       = "smartreflex_core_fck",
1538         .vdd_name       = "core",
1539         .prcm = {
1540                 .omap4 = {
1541                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
1542                 },
1543         },
1544         .slaves         = omap44xx_smartreflex_core_slaves,
1545         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
1546         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1547 };
1548
1549 /* smartreflex_iva */
1550 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
1551 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
1552         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
1553 };
1554
1555 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
1556         {
1557                 .pa_start       = 0x4a0db000,
1558                 .pa_end         = 0x4a0db03f,
1559                 .flags          = ADDR_TYPE_RT
1560         },
1561 };
1562
1563 /* l4_cfg -> smartreflex_iva */
1564 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
1565         .master         = &omap44xx_l4_cfg_hwmod,
1566         .slave          = &omap44xx_smartreflex_iva_hwmod,
1567         .clk            = "l4_div_ck",
1568         .addr           = omap44xx_smartreflex_iva_addrs,
1569         .addr_cnt       = ARRAY_SIZE(omap44xx_smartreflex_iva_addrs),
1570         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1571 };
1572
1573 /* smartreflex_iva slave ports */
1574 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
1575         &omap44xx_l4_cfg__smartreflex_iva,
1576 };
1577
1578 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
1579         .name           = "smartreflex_iva",
1580         .class          = &omap44xx_smartreflex_hwmod_class,
1581         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
1582         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs),
1583         .main_clk       = "smartreflex_iva_fck",
1584         .vdd_name       = "iva",
1585         .prcm = {
1586                 .omap4 = {
1587                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
1588                 },
1589         },
1590         .slaves         = omap44xx_smartreflex_iva_slaves,
1591         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
1592         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1593 };
1594
1595 /* smartreflex_mpu */
1596 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
1597 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
1598         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
1599 };
1600
1601 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
1602         {
1603                 .pa_start       = 0x4a0d9000,
1604                 .pa_end         = 0x4a0d903f,
1605                 .flags          = ADDR_TYPE_RT
1606         },
1607 };
1608
1609 /* l4_cfg -> smartreflex_mpu */
1610 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
1611         .master         = &omap44xx_l4_cfg_hwmod,
1612         .slave          = &omap44xx_smartreflex_mpu_hwmod,
1613         .clk            = "l4_div_ck",
1614         .addr           = omap44xx_smartreflex_mpu_addrs,
1615         .addr_cnt       = ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs),
1616         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1617 };
1618
1619 /* smartreflex_mpu slave ports */
1620 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
1621         &omap44xx_l4_cfg__smartreflex_mpu,
1622 };
1623
1624 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
1625         .name           = "smartreflex_mpu",
1626         .class          = &omap44xx_smartreflex_hwmod_class,
1627         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
1628         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs),
1629         .main_clk       = "smartreflex_mpu_fck",
1630         .vdd_name       = "mpu",
1631         .prcm = {
1632                 .omap4 = {
1633                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
1634                 },
1635         },
1636         .slaves         = omap44xx_smartreflex_mpu_slaves,
1637         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
1638         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1639 };
1640
1641 /*
1642  * 'uart' class
1643  * universal asynchronous receiver/transmitter (uart)
1644  */
1645
1646 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
1647         .rev_offs       = 0x0050,
1648         .sysc_offs      = 0x0054,
1649         .syss_offs      = 0x0058,
1650         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1651                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1652                            SYSS_HAS_RESET_STATUS),
1653         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1654                            SIDLE_SMART_WKUP),
1655         .sysc_fields    = &omap_hwmod_sysc_type1,
1656 };
1657
1658 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
1659         .name   = "uart",
1660         .sysc   = &omap44xx_uart_sysc,
1661 };
1662
1663 /* uart1 */
1664 static struct omap_hwmod omap44xx_uart1_hwmod;
1665 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
1666         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
1667 };
1668
1669 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
1670         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
1671         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
1672 };
1673
1674 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
1675         {
1676                 .pa_start       = 0x4806a000,
1677                 .pa_end         = 0x4806a0ff,
1678                 .flags          = ADDR_TYPE_RT
1679         },
1680 };
1681
1682 /* l4_per -> uart1 */
1683 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
1684         .master         = &omap44xx_l4_per_hwmod,
1685         .slave          = &omap44xx_uart1_hwmod,
1686         .clk            = "l4_div_ck",
1687         .addr           = omap44xx_uart1_addrs,
1688         .addr_cnt       = ARRAY_SIZE(omap44xx_uart1_addrs),
1689         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1690 };
1691
1692 /* uart1 slave ports */
1693 static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
1694         &omap44xx_l4_per__uart1,
1695 };
1696
1697 static struct omap_hwmod omap44xx_uart1_hwmod = {
1698         .name           = "uart1",
1699         .class          = &omap44xx_uart_hwmod_class,
1700         .mpu_irqs       = omap44xx_uart1_irqs,
1701         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart1_irqs),
1702         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
1703         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart1_sdma_reqs),
1704         .main_clk       = "uart1_fck",
1705         .prcm = {
1706                 .omap4 = {
1707                         .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
1708                 },
1709         },
1710         .slaves         = omap44xx_uart1_slaves,
1711         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart1_slaves),
1712         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1713 };
1714
1715 /* uart2 */
1716 static struct omap_hwmod omap44xx_uart2_hwmod;
1717 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
1718         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
1719 };
1720
1721 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
1722         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
1723         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
1724 };
1725
1726 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
1727         {
1728                 .pa_start       = 0x4806c000,
1729                 .pa_end         = 0x4806c0ff,
1730                 .flags          = ADDR_TYPE_RT
1731         },
1732 };
1733
1734 /* l4_per -> uart2 */
1735 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
1736         .master         = &omap44xx_l4_per_hwmod,
1737         .slave          = &omap44xx_uart2_hwmod,
1738         .clk            = "l4_div_ck",
1739         .addr           = omap44xx_uart2_addrs,
1740         .addr_cnt       = ARRAY_SIZE(omap44xx_uart2_addrs),
1741         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1742 };
1743
1744 /* uart2 slave ports */
1745 static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
1746         &omap44xx_l4_per__uart2,
1747 };
1748
1749 static struct omap_hwmod omap44xx_uart2_hwmod = {
1750         .name           = "uart2",
1751         .class          = &omap44xx_uart_hwmod_class,
1752         .mpu_irqs       = omap44xx_uart2_irqs,
1753         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart2_irqs),
1754         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
1755         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart2_sdma_reqs),
1756         .main_clk       = "uart2_fck",
1757         .prcm = {
1758                 .omap4 = {
1759                         .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
1760                 },
1761         },
1762         .slaves         = omap44xx_uart2_slaves,
1763         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart2_slaves),
1764         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1765 };
1766
1767 /* uart3 */
1768 static struct omap_hwmod omap44xx_uart3_hwmod;
1769 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
1770         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
1771 };
1772
1773 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
1774         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
1775         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
1776 };
1777
1778 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
1779         {
1780                 .pa_start       = 0x48020000,
1781                 .pa_end         = 0x480200ff,
1782                 .flags          = ADDR_TYPE_RT
1783         },
1784 };
1785
1786 /* l4_per -> uart3 */
1787 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
1788         .master         = &omap44xx_l4_per_hwmod,
1789         .slave          = &omap44xx_uart3_hwmod,
1790         .clk            = "l4_div_ck",
1791         .addr           = omap44xx_uart3_addrs,
1792         .addr_cnt       = ARRAY_SIZE(omap44xx_uart3_addrs),
1793         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1794 };
1795
1796 /* uart3 slave ports */
1797 static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
1798         &omap44xx_l4_per__uart3,
1799 };
1800
1801 static struct omap_hwmod omap44xx_uart3_hwmod = {
1802         .name           = "uart3",
1803         .class          = &omap44xx_uart_hwmod_class,
1804         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1805         .mpu_irqs       = omap44xx_uart3_irqs,
1806         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart3_irqs),
1807         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
1808         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart3_sdma_reqs),
1809         .main_clk       = "uart3_fck",
1810         .prcm = {
1811                 .omap4 = {
1812                         .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
1813                 },
1814         },
1815         .slaves         = omap44xx_uart3_slaves,
1816         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart3_slaves),
1817         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1818 };
1819
1820 /* uart4 */
1821 static struct omap_hwmod omap44xx_uart4_hwmod;
1822 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
1823         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
1824 };
1825
1826 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
1827         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
1828         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
1829 };
1830
1831 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
1832         {
1833                 .pa_start       = 0x4806e000,
1834                 .pa_end         = 0x4806e0ff,
1835                 .flags          = ADDR_TYPE_RT
1836         },
1837 };
1838
1839 /* l4_per -> uart4 */
1840 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
1841         .master         = &omap44xx_l4_per_hwmod,
1842         .slave          = &omap44xx_uart4_hwmod,
1843         .clk            = "l4_div_ck",
1844         .addr           = omap44xx_uart4_addrs,
1845         .addr_cnt       = ARRAY_SIZE(omap44xx_uart4_addrs),
1846         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1847 };
1848
1849 /* uart4 slave ports */
1850 static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
1851         &omap44xx_l4_per__uart4,
1852 };
1853
1854 static struct omap_hwmod omap44xx_uart4_hwmod = {
1855         .name           = "uart4",
1856         .class          = &omap44xx_uart_hwmod_class,
1857         .mpu_irqs       = omap44xx_uart4_irqs,
1858         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart4_irqs),
1859         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
1860         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart4_sdma_reqs),
1861         .main_clk       = "uart4_fck",
1862         .prcm = {
1863                 .omap4 = {
1864                         .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
1865                 },
1866         },
1867         .slaves         = omap44xx_uart4_slaves,
1868         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart4_slaves),
1869         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1870 };
1871
1872 /*
1873  * 'wd_timer' class
1874  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1875  * overflow condition
1876  */
1877
1878 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
1879         .rev_offs       = 0x0000,
1880         .sysc_offs      = 0x0010,
1881         .syss_offs      = 0x0014,
1882         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1883                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1884         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1885                            SIDLE_SMART_WKUP),
1886         .sysc_fields    = &omap_hwmod_sysc_type1,
1887 };
1888
1889 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
1890         .name           = "wd_timer",
1891         .sysc           = &omap44xx_wd_timer_sysc,
1892         .pre_shutdown   = &omap2_wd_timer_disable,
1893 };
1894
1895 /* wd_timer2 */
1896 static struct omap_hwmod omap44xx_wd_timer2_hwmod;
1897 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
1898         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
1899 };
1900
1901 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
1902         {
1903                 .pa_start       = 0x4a314000,
1904                 .pa_end         = 0x4a31407f,
1905                 .flags          = ADDR_TYPE_RT
1906         },
1907 };
1908
1909 /* l4_wkup -> wd_timer2 */
1910 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
1911         .master         = &omap44xx_l4_wkup_hwmod,
1912         .slave          = &omap44xx_wd_timer2_hwmod,
1913         .clk            = "l4_wkup_clk_mux_ck",
1914         .addr           = omap44xx_wd_timer2_addrs,
1915         .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer2_addrs),
1916         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1917 };
1918
1919 /* wd_timer2 slave ports */
1920 static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
1921         &omap44xx_l4_wkup__wd_timer2,
1922 };
1923
1924 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
1925         .name           = "wd_timer2",
1926         .class          = &omap44xx_wd_timer_hwmod_class,
1927         .mpu_irqs       = omap44xx_wd_timer2_irqs,
1928         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
1929         .main_clk       = "wd_timer2_fck",
1930         .prcm = {
1931                 .omap4 = {
1932                         .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
1933                 },
1934         },
1935         .slaves         = omap44xx_wd_timer2_slaves,
1936         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
1937         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1938 };
1939
1940 /* wd_timer3 */
1941 static struct omap_hwmod omap44xx_wd_timer3_hwmod;
1942 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
1943         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
1944 };
1945
1946 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
1947         {
1948                 .pa_start       = 0x40130000,
1949                 .pa_end         = 0x4013007f,
1950                 .flags          = ADDR_TYPE_RT
1951         },
1952 };
1953
1954 /* l4_abe -> wd_timer3 */
1955 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
1956         .master         = &omap44xx_l4_abe_hwmod,
1957         .slave          = &omap44xx_wd_timer3_hwmod,
1958         .clk            = "ocp_abe_iclk",
1959         .addr           = omap44xx_wd_timer3_addrs,
1960         .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer3_addrs),
1961         .user           = OCP_USER_MPU,
1962 };
1963
1964 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
1965         {
1966                 .pa_start       = 0x49030000,
1967                 .pa_end         = 0x4903007f,
1968                 .flags          = ADDR_TYPE_RT
1969         },
1970 };
1971
1972 /* l4_abe -> wd_timer3 (dma) */
1973 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
1974         .master         = &omap44xx_l4_abe_hwmod,
1975         .slave          = &omap44xx_wd_timer3_hwmod,
1976         .clk            = "ocp_abe_iclk",
1977         .addr           = omap44xx_wd_timer3_dma_addrs,
1978         .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
1979         .user           = OCP_USER_SDMA,
1980 };
1981
1982 /* wd_timer3 slave ports */
1983 static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
1984         &omap44xx_l4_abe__wd_timer3,
1985         &omap44xx_l4_abe__wd_timer3_dma,
1986 };
1987
1988 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
1989         .name           = "wd_timer3",
1990         .class          = &omap44xx_wd_timer_hwmod_class,
1991         .mpu_irqs       = omap44xx_wd_timer3_irqs,
1992         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
1993         .main_clk       = "wd_timer3_fck",
1994         .prcm = {
1995                 .omap4 = {
1996                         .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
1997                 },
1998         },
1999         .slaves         = omap44xx_wd_timer3_slaves,
2000         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
2001         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2002 };
2003
2004 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
2005
2006         /* dmm class */
2007         &omap44xx_dmm_hwmod,
2008
2009         /* emif_fw class */
2010         &omap44xx_emif_fw_hwmod,
2011
2012         /* l3 class */
2013         &omap44xx_l3_instr_hwmod,
2014         &omap44xx_l3_main_1_hwmod,
2015         &omap44xx_l3_main_2_hwmod,
2016         &omap44xx_l3_main_3_hwmod,
2017
2018         /* l4 class */
2019         &omap44xx_l4_abe_hwmod,
2020         &omap44xx_l4_cfg_hwmod,
2021         &omap44xx_l4_per_hwmod,
2022         &omap44xx_l4_wkup_hwmod,
2023
2024         /* mpu_bus class */
2025         &omap44xx_mpu_private_hwmod,
2026
2027         /* dma class */
2028         &omap44xx_dma_system_hwmod,
2029
2030         /* dsp class */
2031         &omap44xx_dsp_hwmod,
2032         &omap44xx_dsp_c0_hwmod,
2033
2034         /* gpio class */
2035         &omap44xx_gpio1_hwmod,
2036         &omap44xx_gpio2_hwmod,
2037         &omap44xx_gpio3_hwmod,
2038         &omap44xx_gpio4_hwmod,
2039         &omap44xx_gpio5_hwmod,
2040         &omap44xx_gpio6_hwmod,
2041
2042         /* i2c class */
2043         &omap44xx_i2c1_hwmod,
2044         &omap44xx_i2c2_hwmod,
2045         &omap44xx_i2c3_hwmod,
2046         &omap44xx_i2c4_hwmod,
2047
2048         /* iva class */
2049         &omap44xx_iva_hwmod,
2050         &omap44xx_iva_seq0_hwmod,
2051         &omap44xx_iva_seq1_hwmod,
2052
2053         /* mpu class */
2054         &omap44xx_mpu_hwmod,
2055
2056         /* smartreflex class */
2057         &omap44xx_smartreflex_core_hwmod,
2058         &omap44xx_smartreflex_iva_hwmod,
2059         &omap44xx_smartreflex_mpu_hwmod,
2060
2061         /* uart class */
2062         &omap44xx_uart1_hwmod,
2063         &omap44xx_uart2_hwmod,
2064         &omap44xx_uart3_hwmod,
2065         &omap44xx_uart4_hwmod,
2066
2067         /* wd_timer class */
2068         &omap44xx_wd_timer2_hwmod,
2069         &omap44xx_wd_timer3_hwmod,
2070
2071         NULL,
2072 };
2073
2074 int __init omap44xx_hwmod_init(void)
2075 {
2076         return omap_hwmod_init(omap44xx_hwmods);
2077 }
2078