2 * Hardware modules present on the OMAP44xx chips
4 * Copyright (C) 2009-2012 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
22 #include <linux/platform_data/gpio-omap.h>
23 #include <linux/power/smartreflex.h>
24 #include <linux/platform_data/omap_ocp2scp.h>
25 #include <linux/i2c-omap.h>
27 #include <linux/omap-dma.h>
29 #include <linux/platform_data/spi-omap2-mcspi.h>
30 #include <linux/platform_data/asoc-ti-mcbsp.h>
31 #include <linux/platform_data/iommu-omap.h>
32 #include <plat/dmtimer.h>
34 #include "omap_hwmod.h"
35 #include "omap_hwmod_common_data.h"
39 #include "prm-regbits-44xx.h"
44 /* Base offset for all OMAP4 interrupts external to MPUSS */
45 #define OMAP44XX_IRQ_GIC_START 32
47 /* Base offset for all OMAP4 dma requests */
48 #define OMAP44XX_DMA_REQ_START 1
55 * 'c2c_target_fw' class
56 * instance(s): c2c_target_fw
58 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class
= {
59 .name
= "c2c_target_fw",
63 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod
= {
64 .name
= "c2c_target_fw",
65 .class = &omap44xx_c2c_target_fw_hwmod_class
,
66 .clkdm_name
= "d2d_clkdm",
69 .clkctrl_offs
= OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET
,
70 .context_offs
= OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET
,
79 static struct omap_hwmod_class omap44xx_dmm_hwmod_class
= {
84 static struct omap_hwmod_irq_info omap44xx_dmm_irqs
[] = {
85 { .irq
= 113 + OMAP44XX_IRQ_GIC_START
},
89 static struct omap_hwmod omap44xx_dmm_hwmod
= {
91 .class = &omap44xx_dmm_hwmod_class
,
92 .clkdm_name
= "l3_emif_clkdm",
93 .mpu_irqs
= omap44xx_dmm_irqs
,
96 .clkctrl_offs
= OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET
,
97 .context_offs
= OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET
,
104 * instance(s): emif_fw
106 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class
= {
111 static struct omap_hwmod omap44xx_emif_fw_hwmod
= {
113 .class = &omap44xx_emif_fw_hwmod_class
,
114 .clkdm_name
= "l3_emif_clkdm",
117 .clkctrl_offs
= OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET
,
118 .context_offs
= OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET
,
125 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
127 static struct omap_hwmod_class omap44xx_l3_hwmod_class
= {
132 static struct omap_hwmod omap44xx_l3_instr_hwmod
= {
134 .class = &omap44xx_l3_hwmod_class
,
135 .clkdm_name
= "l3_instr_clkdm",
138 .clkctrl_offs
= OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET
,
139 .context_offs
= OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET
,
140 .modulemode
= MODULEMODE_HWCTRL
,
146 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs
[] = {
147 { .name
= "dbg_err", .irq
= 9 + OMAP44XX_IRQ_GIC_START
},
148 { .name
= "app_err", .irq
= 10 + OMAP44XX_IRQ_GIC_START
},
152 static struct omap_hwmod omap44xx_l3_main_1_hwmod
= {
154 .class = &omap44xx_l3_hwmod_class
,
155 .clkdm_name
= "l3_1_clkdm",
156 .mpu_irqs
= omap44xx_l3_main_1_irqs
,
159 .clkctrl_offs
= OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET
,
160 .context_offs
= OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET
,
166 static struct omap_hwmod omap44xx_l3_main_2_hwmod
= {
168 .class = &omap44xx_l3_hwmod_class
,
169 .clkdm_name
= "l3_2_clkdm",
172 .clkctrl_offs
= OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET
,
173 .context_offs
= OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET
,
179 static struct omap_hwmod omap44xx_l3_main_3_hwmod
= {
181 .class = &omap44xx_l3_hwmod_class
,
182 .clkdm_name
= "l3_instr_clkdm",
185 .clkctrl_offs
= OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET
,
186 .context_offs
= OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET
,
187 .modulemode
= MODULEMODE_HWCTRL
,
194 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
196 static struct omap_hwmod_class omap44xx_l4_hwmod_class
= {
201 static struct omap_hwmod omap44xx_l4_abe_hwmod
= {
203 .class = &omap44xx_l4_hwmod_class
,
204 .clkdm_name
= "abe_clkdm",
207 .clkctrl_offs
= OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET
,
208 .context_offs
= OMAP4_RM_ABE_AESS_CONTEXT_OFFSET
,
209 .lostcontext_mask
= OMAP4430_LOSTMEM_AESSMEM_MASK
,
210 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
216 static struct omap_hwmod omap44xx_l4_cfg_hwmod
= {
218 .class = &omap44xx_l4_hwmod_class
,
219 .clkdm_name
= "l4_cfg_clkdm",
222 .clkctrl_offs
= OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET
,
223 .context_offs
= OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET
,
229 static struct omap_hwmod omap44xx_l4_per_hwmod
= {
231 .class = &omap44xx_l4_hwmod_class
,
232 .clkdm_name
= "l4_per_clkdm",
235 .clkctrl_offs
= OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET
,
236 .context_offs
= OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET
,
242 static struct omap_hwmod omap44xx_l4_wkup_hwmod
= {
244 .class = &omap44xx_l4_hwmod_class
,
245 .clkdm_name
= "l4_wkup_clkdm",
248 .clkctrl_offs
= OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET
,
249 .context_offs
= OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET
,
256 * instance(s): mpu_private
258 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class
= {
263 static struct omap_hwmod omap44xx_mpu_private_hwmod
= {
264 .name
= "mpu_private",
265 .class = &omap44xx_mpu_bus_hwmod_class
,
266 .clkdm_name
= "mpuss_clkdm",
269 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
276 * instance(s): ocp_wp_noc
278 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class
= {
279 .name
= "ocp_wp_noc",
283 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod
= {
284 .name
= "ocp_wp_noc",
285 .class = &omap44xx_ocp_wp_noc_hwmod_class
,
286 .clkdm_name
= "l3_instr_clkdm",
289 .clkctrl_offs
= OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET
,
290 .context_offs
= OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET
,
291 .modulemode
= MODULEMODE_HWCTRL
,
297 * Modules omap_hwmod structures
299 * The following IPs are excluded for the moment because:
300 * - They do not need an explicit SW control using omap_hwmod API.
301 * - They still need to be validated with the driver
302 * properly adapted to omap_hwmod / omap_device
309 * audio engine sub system
312 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc
= {
315 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
),
316 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
317 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
|
318 MSTANDBY_SMART_WKUP
),
319 .sysc_fields
= &omap_hwmod_sysc_type2
,
322 static struct omap_hwmod_class omap44xx_aess_hwmod_class
= {
324 .sysc
= &omap44xx_aess_sysc
,
325 .enable_preprogram
= omap_hwmod_aess_preprogram
,
329 static struct omap_hwmod_irq_info omap44xx_aess_irqs
[] = {
330 { .irq
= 99 + OMAP44XX_IRQ_GIC_START
},
334 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs
[] = {
335 { .name
= "fifo0", .dma_req
= 100 + OMAP44XX_DMA_REQ_START
},
336 { .name
= "fifo1", .dma_req
= 101 + OMAP44XX_DMA_REQ_START
},
337 { .name
= "fifo2", .dma_req
= 102 + OMAP44XX_DMA_REQ_START
},
338 { .name
= "fifo3", .dma_req
= 103 + OMAP44XX_DMA_REQ_START
},
339 { .name
= "fifo4", .dma_req
= 104 + OMAP44XX_DMA_REQ_START
},
340 { .name
= "fifo5", .dma_req
= 105 + OMAP44XX_DMA_REQ_START
},
341 { .name
= "fifo6", .dma_req
= 106 + OMAP44XX_DMA_REQ_START
},
342 { .name
= "fifo7", .dma_req
= 107 + OMAP44XX_DMA_REQ_START
},
346 static struct omap_hwmod omap44xx_aess_hwmod
= {
348 .class = &omap44xx_aess_hwmod_class
,
349 .clkdm_name
= "abe_clkdm",
350 .mpu_irqs
= omap44xx_aess_irqs
,
351 .sdma_reqs
= omap44xx_aess_sdma_reqs
,
352 .main_clk
= "aess_fclk",
355 .clkctrl_offs
= OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET
,
356 .context_offs
= OMAP4_RM_ABE_AESS_CONTEXT_OFFSET
,
357 .lostcontext_mask
= OMAP4430_LOSTCONTEXT_DFF_MASK
,
358 .modulemode
= MODULEMODE_SWCTRL
,
365 * chip 2 chip interface used to plug the ape soc (omap) with an external modem
369 static struct omap_hwmod_class omap44xx_c2c_hwmod_class
= {
374 static struct omap_hwmod_irq_info omap44xx_c2c_irqs
[] = {
375 { .irq
= 88 + OMAP44XX_IRQ_GIC_START
},
379 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs
[] = {
380 { .dma_req
= 68 + OMAP44XX_DMA_REQ_START
},
384 static struct omap_hwmod omap44xx_c2c_hwmod
= {
386 .class = &omap44xx_c2c_hwmod_class
,
387 .clkdm_name
= "d2d_clkdm",
388 .mpu_irqs
= omap44xx_c2c_irqs
,
389 .sdma_reqs
= omap44xx_c2c_sdma_reqs
,
392 .clkctrl_offs
= OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET
,
393 .context_offs
= OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET
,
400 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
403 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc
= {
406 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
407 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
),
408 .sysc_fields
= &omap_hwmod_sysc_type1
,
411 static struct omap_hwmod_class omap44xx_counter_hwmod_class
= {
413 .sysc
= &omap44xx_counter_sysc
,
417 static struct omap_hwmod omap44xx_counter_32k_hwmod
= {
418 .name
= "counter_32k",
419 .class = &omap44xx_counter_hwmod_class
,
420 .clkdm_name
= "l4_wkup_clkdm",
421 .flags
= HWMOD_SWSUP_SIDLE
,
422 .main_clk
= "sys_32k_ck",
425 .clkctrl_offs
= OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET
,
426 .context_offs
= OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET
,
432 * 'ctrl_module' class
433 * attila core control module + core pad control module + wkup pad control
434 * module + attila wkup control module
437 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc
= {
440 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
441 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
443 .sysc_fields
= &omap_hwmod_sysc_type2
,
446 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class
= {
447 .name
= "ctrl_module",
448 .sysc
= &omap44xx_ctrl_module_sysc
,
451 /* ctrl_module_core */
452 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs
[] = {
453 { .irq
= 8 + OMAP44XX_IRQ_GIC_START
},
457 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod
= {
458 .name
= "ctrl_module_core",
459 .class = &omap44xx_ctrl_module_hwmod_class
,
460 .clkdm_name
= "l4_cfg_clkdm",
461 .mpu_irqs
= omap44xx_ctrl_module_core_irqs
,
464 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
469 /* ctrl_module_pad_core */
470 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod
= {
471 .name
= "ctrl_module_pad_core",
472 .class = &omap44xx_ctrl_module_hwmod_class
,
473 .clkdm_name
= "l4_cfg_clkdm",
476 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
481 /* ctrl_module_wkup */
482 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod
= {
483 .name
= "ctrl_module_wkup",
484 .class = &omap44xx_ctrl_module_hwmod_class
,
485 .clkdm_name
= "l4_wkup_clkdm",
488 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
493 /* ctrl_module_pad_wkup */
494 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod
= {
495 .name
= "ctrl_module_pad_wkup",
496 .class = &omap44xx_ctrl_module_hwmod_class
,
497 .clkdm_name
= "l4_wkup_clkdm",
500 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
507 * debug and emulation sub system
510 static struct omap_hwmod_class omap44xx_debugss_hwmod_class
= {
515 static struct omap_hwmod omap44xx_debugss_hwmod
= {
517 .class = &omap44xx_debugss_hwmod_class
,
518 .clkdm_name
= "emu_sys_clkdm",
519 .main_clk
= "trace_clk_div_ck",
522 .clkctrl_offs
= OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET
,
523 .context_offs
= OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET
,
530 * dma controller for data exchange between memory to memory (i.e. internal or
531 * external memory) and gp peripherals to memory or memory to gp peripherals
534 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc
= {
538 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
539 SYSC_HAS_EMUFREE
| SYSC_HAS_MIDLEMODE
|
540 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
541 SYSS_HAS_RESET_STATUS
),
542 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
543 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
544 .sysc_fields
= &omap_hwmod_sysc_type1
,
547 static struct omap_hwmod_class omap44xx_dma_hwmod_class
= {
549 .sysc
= &omap44xx_dma_sysc
,
553 static struct omap_dma_dev_attr dma_dev_attr
= {
554 .dev_caps
= RESERVE_CHANNEL
| DMA_LINKED_LCH
| GLOBAL_PRIORITY
|
555 IS_CSSA_32
| IS_CDSA_32
| IS_RW_PRIORITY
,
560 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs
[] = {
561 { .name
= "0", .irq
= 12 + OMAP44XX_IRQ_GIC_START
},
562 { .name
= "1", .irq
= 13 + OMAP44XX_IRQ_GIC_START
},
563 { .name
= "2", .irq
= 14 + OMAP44XX_IRQ_GIC_START
},
564 { .name
= "3", .irq
= 15 + OMAP44XX_IRQ_GIC_START
},
568 static struct omap_hwmod omap44xx_dma_system_hwmod
= {
569 .name
= "dma_system",
570 .class = &omap44xx_dma_hwmod_class
,
571 .clkdm_name
= "l3_dma_clkdm",
572 .mpu_irqs
= omap44xx_dma_system_irqs
,
573 .main_clk
= "l3_div_ck",
576 .clkctrl_offs
= OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET
,
577 .context_offs
= OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET
,
580 .dev_attr
= &dma_dev_attr
,
585 * digital microphone controller
588 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc
= {
591 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
592 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
593 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
595 .sysc_fields
= &omap_hwmod_sysc_type2
,
598 static struct omap_hwmod_class omap44xx_dmic_hwmod_class
= {
600 .sysc
= &omap44xx_dmic_sysc
,
604 static struct omap_hwmod_irq_info omap44xx_dmic_irqs
[] = {
605 { .irq
= 114 + OMAP44XX_IRQ_GIC_START
},
609 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs
[] = {
610 { .dma_req
= 66 + OMAP44XX_DMA_REQ_START
},
614 static struct omap_hwmod omap44xx_dmic_hwmod
= {
616 .class = &omap44xx_dmic_hwmod_class
,
617 .clkdm_name
= "abe_clkdm",
618 .mpu_irqs
= omap44xx_dmic_irqs
,
619 .sdma_reqs
= omap44xx_dmic_sdma_reqs
,
620 .main_clk
= "func_dmic_abe_gfclk",
623 .clkctrl_offs
= OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET
,
624 .context_offs
= OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET
,
625 .modulemode
= MODULEMODE_SWCTRL
,
635 static struct omap_hwmod_class omap44xx_dsp_hwmod_class
= {
640 static struct omap_hwmod_irq_info omap44xx_dsp_irqs
[] = {
641 { .irq
= 28 + OMAP44XX_IRQ_GIC_START
},
645 static struct omap_hwmod_rst_info omap44xx_dsp_resets
[] = {
646 { .name
= "dsp", .rst_shift
= 0 },
649 static struct omap_hwmod omap44xx_dsp_hwmod
= {
651 .class = &omap44xx_dsp_hwmod_class
,
652 .clkdm_name
= "tesla_clkdm",
653 .mpu_irqs
= omap44xx_dsp_irqs
,
654 .rst_lines
= omap44xx_dsp_resets
,
655 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_dsp_resets
),
656 .main_clk
= "dpll_iva_m4x2_ck",
659 .clkctrl_offs
= OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET
,
660 .rstctrl_offs
= OMAP4_RM_TESLA_RSTCTRL_OFFSET
,
661 .context_offs
= OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET
,
662 .modulemode
= MODULEMODE_HWCTRL
,
672 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc
= {
675 .sysc_flags
= SYSS_HAS_RESET_STATUS
,
678 static struct omap_hwmod_class omap44xx_dss_hwmod_class
= {
680 .sysc
= &omap44xx_dss_sysc
,
681 .reset
= omap_dss_reset
,
685 static struct omap_hwmod_opt_clk dss_opt_clks
[] = {
686 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
687 { .role
= "tv_clk", .clk
= "dss_tv_clk" },
688 { .role
= "hdmi_clk", .clk
= "dss_48mhz_clk" },
691 static struct omap_hwmod omap44xx_dss_hwmod
= {
693 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
694 .class = &omap44xx_dss_hwmod_class
,
695 .clkdm_name
= "l3_dss_clkdm",
696 .main_clk
= "dss_dss_clk",
699 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
700 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
703 .opt_clks
= dss_opt_clks
,
704 .opt_clks_cnt
= ARRAY_SIZE(dss_opt_clks
),
712 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc
= {
716 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
717 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_MIDLEMODE
|
718 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
719 SYSS_HAS_RESET_STATUS
),
720 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
721 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
722 .sysc_fields
= &omap_hwmod_sysc_type1
,
725 static struct omap_hwmod_class omap44xx_dispc_hwmod_class
= {
727 .sysc
= &omap44xx_dispc_sysc
,
731 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs
[] = {
732 { .irq
= 25 + OMAP44XX_IRQ_GIC_START
},
736 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs
[] = {
737 { .dma_req
= 5 + OMAP44XX_DMA_REQ_START
},
741 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr
= {
743 .has_framedonetv_irq
= 1
746 static struct omap_hwmod omap44xx_dss_dispc_hwmod
= {
748 .class = &omap44xx_dispc_hwmod_class
,
749 .clkdm_name
= "l3_dss_clkdm",
750 .mpu_irqs
= omap44xx_dss_dispc_irqs
,
751 .sdma_reqs
= omap44xx_dss_dispc_sdma_reqs
,
752 .main_clk
= "dss_dss_clk",
755 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
756 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
759 .dev_attr
= &omap44xx_dss_dispc_dev_attr
764 * display serial interface controller
767 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc
= {
771 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
772 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
773 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
774 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
775 .sysc_fields
= &omap_hwmod_sysc_type1
,
778 static struct omap_hwmod_class omap44xx_dsi_hwmod_class
= {
780 .sysc
= &omap44xx_dsi_sysc
,
784 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs
[] = {
785 { .irq
= 53 + OMAP44XX_IRQ_GIC_START
},
789 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs
[] = {
790 { .dma_req
= 74 + OMAP44XX_DMA_REQ_START
},
794 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks
[] = {
795 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
798 static struct omap_hwmod omap44xx_dss_dsi1_hwmod
= {
800 .class = &omap44xx_dsi_hwmod_class
,
801 .clkdm_name
= "l3_dss_clkdm",
802 .mpu_irqs
= omap44xx_dss_dsi1_irqs
,
803 .sdma_reqs
= omap44xx_dss_dsi1_sdma_reqs
,
804 .main_clk
= "dss_dss_clk",
807 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
808 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
811 .opt_clks
= dss_dsi1_opt_clks
,
812 .opt_clks_cnt
= ARRAY_SIZE(dss_dsi1_opt_clks
),
816 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs
[] = {
817 { .irq
= 84 + OMAP44XX_IRQ_GIC_START
},
821 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs
[] = {
822 { .dma_req
= 83 + OMAP44XX_DMA_REQ_START
},
826 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks
[] = {
827 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
830 static struct omap_hwmod omap44xx_dss_dsi2_hwmod
= {
832 .class = &omap44xx_dsi_hwmod_class
,
833 .clkdm_name
= "l3_dss_clkdm",
834 .mpu_irqs
= omap44xx_dss_dsi2_irqs
,
835 .sdma_reqs
= omap44xx_dss_dsi2_sdma_reqs
,
836 .main_clk
= "dss_dss_clk",
839 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
840 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
843 .opt_clks
= dss_dsi2_opt_clks
,
844 .opt_clks_cnt
= ARRAY_SIZE(dss_dsi2_opt_clks
),
852 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc
= {
855 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
857 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
859 .sysc_fields
= &omap_hwmod_sysc_type2
,
862 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class
= {
864 .sysc
= &omap44xx_hdmi_sysc
,
868 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs
[] = {
869 { .irq
= 101 + OMAP44XX_IRQ_GIC_START
},
873 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs
[] = {
874 { .dma_req
= 75 + OMAP44XX_DMA_REQ_START
},
878 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks
[] = {
879 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
882 static struct omap_hwmod omap44xx_dss_hdmi_hwmod
= {
884 .class = &omap44xx_hdmi_hwmod_class
,
885 .clkdm_name
= "l3_dss_clkdm",
887 * HDMI audio requires to use no-idle mode. Hence,
888 * set idle mode by software.
890 .flags
= HWMOD_SWSUP_SIDLE
,
891 .mpu_irqs
= omap44xx_dss_hdmi_irqs
,
892 .sdma_reqs
= omap44xx_dss_hdmi_sdma_reqs
,
893 .main_clk
= "dss_48mhz_clk",
896 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
897 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
900 .opt_clks
= dss_hdmi_opt_clks
,
901 .opt_clks_cnt
= ARRAY_SIZE(dss_hdmi_opt_clks
),
906 * remote frame buffer interface
909 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc
= {
913 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SIDLEMODE
|
914 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
915 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
916 .sysc_fields
= &omap_hwmod_sysc_type1
,
919 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class
= {
921 .sysc
= &omap44xx_rfbi_sysc
,
925 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs
[] = {
926 { .dma_req
= 13 + OMAP44XX_DMA_REQ_START
},
930 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks
[] = {
931 { .role
= "ick", .clk
= "dss_fck" },
934 static struct omap_hwmod omap44xx_dss_rfbi_hwmod
= {
936 .class = &omap44xx_rfbi_hwmod_class
,
937 .clkdm_name
= "l3_dss_clkdm",
938 .sdma_reqs
= omap44xx_dss_rfbi_sdma_reqs
,
939 .main_clk
= "dss_dss_clk",
942 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
943 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
946 .opt_clks
= dss_rfbi_opt_clks
,
947 .opt_clks_cnt
= ARRAY_SIZE(dss_rfbi_opt_clks
),
955 static struct omap_hwmod_class omap44xx_venc_hwmod_class
= {
960 static struct omap_hwmod omap44xx_dss_venc_hwmod
= {
962 .class = &omap44xx_venc_hwmod_class
,
963 .clkdm_name
= "l3_dss_clkdm",
964 .main_clk
= "dss_tv_clk",
967 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
968 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
975 * bch error location module
978 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc
= {
982 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
983 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
984 SYSS_HAS_RESET_STATUS
),
985 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
986 .sysc_fields
= &omap_hwmod_sysc_type1
,
989 static struct omap_hwmod_class omap44xx_elm_hwmod_class
= {
991 .sysc
= &omap44xx_elm_sysc
,
995 static struct omap_hwmod_irq_info omap44xx_elm_irqs
[] = {
996 { .irq
= 4 + OMAP44XX_IRQ_GIC_START
},
1000 static struct omap_hwmod omap44xx_elm_hwmod
= {
1002 .class = &omap44xx_elm_hwmod_class
,
1003 .clkdm_name
= "l4_per_clkdm",
1004 .mpu_irqs
= omap44xx_elm_irqs
,
1007 .clkctrl_offs
= OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET
,
1008 .context_offs
= OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET
,
1015 * external memory interface no1
1018 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc
= {
1022 static struct omap_hwmod_class omap44xx_emif_hwmod_class
= {
1024 .sysc
= &omap44xx_emif_sysc
,
1028 static struct omap_hwmod_irq_info omap44xx_emif1_irqs
[] = {
1029 { .irq
= 110 + OMAP44XX_IRQ_GIC_START
},
1033 static struct omap_hwmod omap44xx_emif1_hwmod
= {
1035 .class = &omap44xx_emif_hwmod_class
,
1036 .clkdm_name
= "l3_emif_clkdm",
1037 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
1038 .mpu_irqs
= omap44xx_emif1_irqs
,
1039 .main_clk
= "ddrphy_ck",
1042 .clkctrl_offs
= OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET
,
1043 .context_offs
= OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET
,
1044 .modulemode
= MODULEMODE_HWCTRL
,
1050 static struct omap_hwmod_irq_info omap44xx_emif2_irqs
[] = {
1051 { .irq
= 111 + OMAP44XX_IRQ_GIC_START
},
1055 static struct omap_hwmod omap44xx_emif2_hwmod
= {
1057 .class = &omap44xx_emif_hwmod_class
,
1058 .clkdm_name
= "l3_emif_clkdm",
1059 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
1060 .mpu_irqs
= omap44xx_emif2_irqs
,
1061 .main_clk
= "ddrphy_ck",
1064 .clkctrl_offs
= OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET
,
1065 .context_offs
= OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET
,
1066 .modulemode
= MODULEMODE_HWCTRL
,
1073 * face detection hw accelerator module
1076 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc
= {
1078 .sysc_offs
= 0x0010,
1080 * FDIF needs 100 OCP clk cycles delay after a softreset before
1081 * accessing sysconfig again.
1082 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1083 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1085 * TODO: Indicate errata when available.
1088 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_RESET_STATUS
|
1089 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1090 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1091 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
1092 .sysc_fields
= &omap_hwmod_sysc_type2
,
1095 static struct omap_hwmod_class omap44xx_fdif_hwmod_class
= {
1097 .sysc
= &omap44xx_fdif_sysc
,
1101 static struct omap_hwmod_irq_info omap44xx_fdif_irqs
[] = {
1102 { .irq
= 69 + OMAP44XX_IRQ_GIC_START
},
1106 static struct omap_hwmod omap44xx_fdif_hwmod
= {
1108 .class = &omap44xx_fdif_hwmod_class
,
1109 .clkdm_name
= "iss_clkdm",
1110 .mpu_irqs
= omap44xx_fdif_irqs
,
1111 .main_clk
= "fdif_fck",
1114 .clkctrl_offs
= OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET
,
1115 .context_offs
= OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET
,
1116 .modulemode
= MODULEMODE_SWCTRL
,
1123 * general purpose io module
1126 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc
= {
1128 .sysc_offs
= 0x0010,
1129 .syss_offs
= 0x0114,
1130 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
1131 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
1132 SYSS_HAS_RESET_STATUS
),
1133 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1135 .sysc_fields
= &omap_hwmod_sysc_type1
,
1138 static struct omap_hwmod_class omap44xx_gpio_hwmod_class
= {
1140 .sysc
= &omap44xx_gpio_sysc
,
1145 static struct omap_gpio_dev_attr gpio_dev_attr
= {
1151 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs
[] = {
1152 { .irq
= 29 + OMAP44XX_IRQ_GIC_START
},
1156 static struct omap_hwmod_opt_clk gpio1_opt_clks
[] = {
1157 { .role
= "dbclk", .clk
= "gpio1_dbclk" },
1160 static struct omap_hwmod omap44xx_gpio1_hwmod
= {
1162 .class = &omap44xx_gpio_hwmod_class
,
1163 .clkdm_name
= "l4_wkup_clkdm",
1164 .mpu_irqs
= omap44xx_gpio1_irqs
,
1165 .main_clk
= "l4_wkup_clk_mux_ck",
1168 .clkctrl_offs
= OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET
,
1169 .context_offs
= OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET
,
1170 .modulemode
= MODULEMODE_HWCTRL
,
1173 .opt_clks
= gpio1_opt_clks
,
1174 .opt_clks_cnt
= ARRAY_SIZE(gpio1_opt_clks
),
1175 .dev_attr
= &gpio_dev_attr
,
1179 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs
[] = {
1180 { .irq
= 30 + OMAP44XX_IRQ_GIC_START
},
1184 static struct omap_hwmod_opt_clk gpio2_opt_clks
[] = {
1185 { .role
= "dbclk", .clk
= "gpio2_dbclk" },
1188 static struct omap_hwmod omap44xx_gpio2_hwmod
= {
1190 .class = &omap44xx_gpio_hwmod_class
,
1191 .clkdm_name
= "l4_per_clkdm",
1192 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1193 .mpu_irqs
= omap44xx_gpio2_irqs
,
1194 .main_clk
= "l4_div_ck",
1197 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET
,
1198 .context_offs
= OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET
,
1199 .modulemode
= MODULEMODE_HWCTRL
,
1202 .opt_clks
= gpio2_opt_clks
,
1203 .opt_clks_cnt
= ARRAY_SIZE(gpio2_opt_clks
),
1204 .dev_attr
= &gpio_dev_attr
,
1208 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs
[] = {
1209 { .irq
= 31 + OMAP44XX_IRQ_GIC_START
},
1213 static struct omap_hwmod_opt_clk gpio3_opt_clks
[] = {
1214 { .role
= "dbclk", .clk
= "gpio3_dbclk" },
1217 static struct omap_hwmod omap44xx_gpio3_hwmod
= {
1219 .class = &omap44xx_gpio_hwmod_class
,
1220 .clkdm_name
= "l4_per_clkdm",
1221 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1222 .mpu_irqs
= omap44xx_gpio3_irqs
,
1223 .main_clk
= "l4_div_ck",
1226 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET
,
1227 .context_offs
= OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET
,
1228 .modulemode
= MODULEMODE_HWCTRL
,
1231 .opt_clks
= gpio3_opt_clks
,
1232 .opt_clks_cnt
= ARRAY_SIZE(gpio3_opt_clks
),
1233 .dev_attr
= &gpio_dev_attr
,
1237 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs
[] = {
1238 { .irq
= 32 + OMAP44XX_IRQ_GIC_START
},
1242 static struct omap_hwmod_opt_clk gpio4_opt_clks
[] = {
1243 { .role
= "dbclk", .clk
= "gpio4_dbclk" },
1246 static struct omap_hwmod omap44xx_gpio4_hwmod
= {
1248 .class = &omap44xx_gpio_hwmod_class
,
1249 .clkdm_name
= "l4_per_clkdm",
1250 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1251 .mpu_irqs
= omap44xx_gpio4_irqs
,
1252 .main_clk
= "l4_div_ck",
1255 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET
,
1256 .context_offs
= OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET
,
1257 .modulemode
= MODULEMODE_HWCTRL
,
1260 .opt_clks
= gpio4_opt_clks
,
1261 .opt_clks_cnt
= ARRAY_SIZE(gpio4_opt_clks
),
1262 .dev_attr
= &gpio_dev_attr
,
1266 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs
[] = {
1267 { .irq
= 33 + OMAP44XX_IRQ_GIC_START
},
1271 static struct omap_hwmod_opt_clk gpio5_opt_clks
[] = {
1272 { .role
= "dbclk", .clk
= "gpio5_dbclk" },
1275 static struct omap_hwmod omap44xx_gpio5_hwmod
= {
1277 .class = &omap44xx_gpio_hwmod_class
,
1278 .clkdm_name
= "l4_per_clkdm",
1279 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1280 .mpu_irqs
= omap44xx_gpio5_irqs
,
1281 .main_clk
= "l4_div_ck",
1284 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET
,
1285 .context_offs
= OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET
,
1286 .modulemode
= MODULEMODE_HWCTRL
,
1289 .opt_clks
= gpio5_opt_clks
,
1290 .opt_clks_cnt
= ARRAY_SIZE(gpio5_opt_clks
),
1291 .dev_attr
= &gpio_dev_attr
,
1295 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs
[] = {
1296 { .irq
= 34 + OMAP44XX_IRQ_GIC_START
},
1300 static struct omap_hwmod_opt_clk gpio6_opt_clks
[] = {
1301 { .role
= "dbclk", .clk
= "gpio6_dbclk" },
1304 static struct omap_hwmod omap44xx_gpio6_hwmod
= {
1306 .class = &omap44xx_gpio_hwmod_class
,
1307 .clkdm_name
= "l4_per_clkdm",
1308 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1309 .mpu_irqs
= omap44xx_gpio6_irqs
,
1310 .main_clk
= "l4_div_ck",
1313 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET
,
1314 .context_offs
= OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET
,
1315 .modulemode
= MODULEMODE_HWCTRL
,
1318 .opt_clks
= gpio6_opt_clks
,
1319 .opt_clks_cnt
= ARRAY_SIZE(gpio6_opt_clks
),
1320 .dev_attr
= &gpio_dev_attr
,
1325 * general purpose memory controller
1328 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc
= {
1330 .sysc_offs
= 0x0010,
1331 .syss_offs
= 0x0014,
1332 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SIDLEMODE
|
1333 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1334 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1335 .sysc_fields
= &omap_hwmod_sysc_type1
,
1338 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class
= {
1340 .sysc
= &omap44xx_gpmc_sysc
,
1344 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs
[] = {
1345 { .irq
= 20 + OMAP44XX_IRQ_GIC_START
},
1349 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs
[] = {
1350 { .dma_req
= 3 + OMAP44XX_DMA_REQ_START
},
1354 static struct omap_hwmod omap44xx_gpmc_hwmod
= {
1356 .class = &omap44xx_gpmc_hwmod_class
,
1357 .clkdm_name
= "l3_2_clkdm",
1359 * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
1360 * block. It is not being added due to any known bugs with
1361 * resetting the GPMC IP block, but rather because any timings
1362 * set by the bootloader are not being correctly programmed by
1363 * the kernel from the board file or DT data.
1364 * HWMOD_INIT_NO_RESET should be removed ASAP.
1366 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
1367 .mpu_irqs
= omap44xx_gpmc_irqs
,
1368 .sdma_reqs
= omap44xx_gpmc_sdma_reqs
,
1371 .clkctrl_offs
= OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET
,
1372 .context_offs
= OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET
,
1373 .modulemode
= MODULEMODE_HWCTRL
,
1380 * 2d/3d graphics accelerator
1383 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc
= {
1384 .rev_offs
= 0x1fc00,
1385 .sysc_offs
= 0x1fc10,
1386 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
),
1387 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1388 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1389 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1390 .sysc_fields
= &omap_hwmod_sysc_type2
,
1393 static struct omap_hwmod_class omap44xx_gpu_hwmod_class
= {
1395 .sysc
= &omap44xx_gpu_sysc
,
1399 static struct omap_hwmod_irq_info omap44xx_gpu_irqs
[] = {
1400 { .irq
= 21 + OMAP44XX_IRQ_GIC_START
},
1404 static struct omap_hwmod omap44xx_gpu_hwmod
= {
1406 .class = &omap44xx_gpu_hwmod_class
,
1407 .clkdm_name
= "l3_gfx_clkdm",
1408 .mpu_irqs
= omap44xx_gpu_irqs
,
1409 .main_clk
= "sgx_clk_mux",
1412 .clkctrl_offs
= OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET
,
1413 .context_offs
= OMAP4_RM_GFX_GFX_CONTEXT_OFFSET
,
1414 .modulemode
= MODULEMODE_SWCTRL
,
1421 * hdq / 1-wire serial interface controller
1424 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc
= {
1426 .sysc_offs
= 0x0014,
1427 .syss_offs
= 0x0018,
1428 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SOFTRESET
|
1429 SYSS_HAS_RESET_STATUS
),
1430 .sysc_fields
= &omap_hwmod_sysc_type1
,
1433 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class
= {
1435 .sysc
= &omap44xx_hdq1w_sysc
,
1439 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs
[] = {
1440 { .irq
= 58 + OMAP44XX_IRQ_GIC_START
},
1444 static struct omap_hwmod omap44xx_hdq1w_hwmod
= {
1446 .class = &omap44xx_hdq1w_hwmod_class
,
1447 .clkdm_name
= "l4_per_clkdm",
1448 .flags
= HWMOD_INIT_NO_RESET
, /* XXX temporary */
1449 .mpu_irqs
= omap44xx_hdq1w_irqs
,
1450 .main_clk
= "func_12m_fclk",
1453 .clkctrl_offs
= OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET
,
1454 .context_offs
= OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET
,
1455 .modulemode
= MODULEMODE_SWCTRL
,
1462 * mipi high-speed synchronous serial interface (multichannel and full-duplex
1466 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc
= {
1468 .sysc_offs
= 0x0010,
1469 .syss_offs
= 0x0014,
1470 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_EMUFREE
|
1471 SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
|
1472 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1473 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1474 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1475 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1476 .sysc_fields
= &omap_hwmod_sysc_type1
,
1479 static struct omap_hwmod_class omap44xx_hsi_hwmod_class
= {
1481 .sysc
= &omap44xx_hsi_sysc
,
1485 static struct omap_hwmod_irq_info omap44xx_hsi_irqs
[] = {
1486 { .name
= "mpu_p1", .irq
= 67 + OMAP44XX_IRQ_GIC_START
},
1487 { .name
= "mpu_p2", .irq
= 68 + OMAP44XX_IRQ_GIC_START
},
1488 { .name
= "mpu_dma", .irq
= 71 + OMAP44XX_IRQ_GIC_START
},
1492 static struct omap_hwmod omap44xx_hsi_hwmod
= {
1494 .class = &omap44xx_hsi_hwmod_class
,
1495 .clkdm_name
= "l3_init_clkdm",
1496 .mpu_irqs
= omap44xx_hsi_irqs
,
1497 .main_clk
= "hsi_fck",
1500 .clkctrl_offs
= OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET
,
1501 .context_offs
= OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET
,
1502 .modulemode
= MODULEMODE_HWCTRL
,
1509 * multimaster high-speed i2c controller
1512 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc
= {
1513 .sysc_offs
= 0x0010,
1514 .syss_offs
= 0x0090,
1515 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
1516 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
1517 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1518 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1520 .clockact
= CLOCKACT_TEST_ICLK
,
1521 .sysc_fields
= &omap_hwmod_sysc_type1
,
1524 static struct omap_hwmod_class omap44xx_i2c_hwmod_class
= {
1526 .sysc
= &omap44xx_i2c_sysc
,
1527 .rev
= OMAP_I2C_IP_VERSION_2
,
1528 .reset
= &omap_i2c_reset
,
1531 static struct omap_i2c_dev_attr i2c_dev_attr
= {
1532 .flags
= OMAP_I2C_FLAG_BUS_SHIFT_NONE
,
1536 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs
[] = {
1537 { .irq
= 56 + OMAP44XX_IRQ_GIC_START
},
1541 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs
[] = {
1542 { .name
= "tx", .dma_req
= 26 + OMAP44XX_DMA_REQ_START
},
1543 { .name
= "rx", .dma_req
= 27 + OMAP44XX_DMA_REQ_START
},
1547 static struct omap_hwmod omap44xx_i2c1_hwmod
= {
1549 .class = &omap44xx_i2c_hwmod_class
,
1550 .clkdm_name
= "l4_per_clkdm",
1551 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1552 .mpu_irqs
= omap44xx_i2c1_irqs
,
1553 .sdma_reqs
= omap44xx_i2c1_sdma_reqs
,
1554 .main_clk
= "func_96m_fclk",
1557 .clkctrl_offs
= OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET
,
1558 .context_offs
= OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET
,
1559 .modulemode
= MODULEMODE_SWCTRL
,
1562 .dev_attr
= &i2c_dev_attr
,
1566 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs
[] = {
1567 { .irq
= 57 + OMAP44XX_IRQ_GIC_START
},
1571 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs
[] = {
1572 { .name
= "tx", .dma_req
= 28 + OMAP44XX_DMA_REQ_START
},
1573 { .name
= "rx", .dma_req
= 29 + OMAP44XX_DMA_REQ_START
},
1577 static struct omap_hwmod omap44xx_i2c2_hwmod
= {
1579 .class = &omap44xx_i2c_hwmod_class
,
1580 .clkdm_name
= "l4_per_clkdm",
1581 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1582 .mpu_irqs
= omap44xx_i2c2_irqs
,
1583 .sdma_reqs
= omap44xx_i2c2_sdma_reqs
,
1584 .main_clk
= "func_96m_fclk",
1587 .clkctrl_offs
= OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET
,
1588 .context_offs
= OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET
,
1589 .modulemode
= MODULEMODE_SWCTRL
,
1592 .dev_attr
= &i2c_dev_attr
,
1596 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs
[] = {
1597 { .irq
= 61 + OMAP44XX_IRQ_GIC_START
},
1601 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs
[] = {
1602 { .name
= "tx", .dma_req
= 24 + OMAP44XX_DMA_REQ_START
},
1603 { .name
= "rx", .dma_req
= 25 + OMAP44XX_DMA_REQ_START
},
1607 static struct omap_hwmod omap44xx_i2c3_hwmod
= {
1609 .class = &omap44xx_i2c_hwmod_class
,
1610 .clkdm_name
= "l4_per_clkdm",
1611 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1612 .mpu_irqs
= omap44xx_i2c3_irqs
,
1613 .sdma_reqs
= omap44xx_i2c3_sdma_reqs
,
1614 .main_clk
= "func_96m_fclk",
1617 .clkctrl_offs
= OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET
,
1618 .context_offs
= OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET
,
1619 .modulemode
= MODULEMODE_SWCTRL
,
1622 .dev_attr
= &i2c_dev_attr
,
1626 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs
[] = {
1627 { .irq
= 62 + OMAP44XX_IRQ_GIC_START
},
1631 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs
[] = {
1632 { .name
= "tx", .dma_req
= 123 + OMAP44XX_DMA_REQ_START
},
1633 { .name
= "rx", .dma_req
= 124 + OMAP44XX_DMA_REQ_START
},
1637 static struct omap_hwmod omap44xx_i2c4_hwmod
= {
1639 .class = &omap44xx_i2c_hwmod_class
,
1640 .clkdm_name
= "l4_per_clkdm",
1641 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1642 .mpu_irqs
= omap44xx_i2c4_irqs
,
1643 .sdma_reqs
= omap44xx_i2c4_sdma_reqs
,
1644 .main_clk
= "func_96m_fclk",
1647 .clkctrl_offs
= OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET
,
1648 .context_offs
= OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET
,
1649 .modulemode
= MODULEMODE_SWCTRL
,
1652 .dev_attr
= &i2c_dev_attr
,
1657 * imaging processor unit
1660 static struct omap_hwmod_class omap44xx_ipu_hwmod_class
= {
1665 static struct omap_hwmod_irq_info omap44xx_ipu_irqs
[] = {
1666 { .irq
= 100 + OMAP44XX_IRQ_GIC_START
},
1670 static struct omap_hwmod_rst_info omap44xx_ipu_resets
[] = {
1671 { .name
= "cpu0", .rst_shift
= 0 },
1672 { .name
= "cpu1", .rst_shift
= 1 },
1675 static struct omap_hwmod omap44xx_ipu_hwmod
= {
1677 .class = &omap44xx_ipu_hwmod_class
,
1678 .clkdm_name
= "ducati_clkdm",
1679 .mpu_irqs
= omap44xx_ipu_irqs
,
1680 .rst_lines
= omap44xx_ipu_resets
,
1681 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_ipu_resets
),
1682 .main_clk
= "ducati_clk_mux_ck",
1685 .clkctrl_offs
= OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET
,
1686 .rstctrl_offs
= OMAP4_RM_DUCATI_RSTCTRL_OFFSET
,
1687 .context_offs
= OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET
,
1688 .modulemode
= MODULEMODE_HWCTRL
,
1695 * external images sensor pixel data processor
1698 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc
= {
1700 .sysc_offs
= 0x0010,
1702 * ISS needs 100 OCP clk cycles delay after a softreset before
1703 * accessing sysconfig again.
1704 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1705 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1707 * TODO: Indicate errata when available.
1710 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_RESET_STATUS
|
1711 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1712 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1713 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1714 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1715 .sysc_fields
= &omap_hwmod_sysc_type2
,
1718 static struct omap_hwmod_class omap44xx_iss_hwmod_class
= {
1720 .sysc
= &omap44xx_iss_sysc
,
1724 static struct omap_hwmod_irq_info omap44xx_iss_irqs
[] = {
1725 { .irq
= 24 + OMAP44XX_IRQ_GIC_START
},
1729 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs
[] = {
1730 { .name
= "1", .dma_req
= 8 + OMAP44XX_DMA_REQ_START
},
1731 { .name
= "2", .dma_req
= 9 + OMAP44XX_DMA_REQ_START
},
1732 { .name
= "3", .dma_req
= 11 + OMAP44XX_DMA_REQ_START
},
1733 { .name
= "4", .dma_req
= 12 + OMAP44XX_DMA_REQ_START
},
1737 static struct omap_hwmod_opt_clk iss_opt_clks
[] = {
1738 { .role
= "ctrlclk", .clk
= "iss_ctrlclk" },
1741 static struct omap_hwmod omap44xx_iss_hwmod
= {
1743 .class = &omap44xx_iss_hwmod_class
,
1744 .clkdm_name
= "iss_clkdm",
1745 .mpu_irqs
= omap44xx_iss_irqs
,
1746 .sdma_reqs
= omap44xx_iss_sdma_reqs
,
1747 .main_clk
= "ducati_clk_mux_ck",
1750 .clkctrl_offs
= OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET
,
1751 .context_offs
= OMAP4_RM_CAM_ISS_CONTEXT_OFFSET
,
1752 .modulemode
= MODULEMODE_SWCTRL
,
1755 .opt_clks
= iss_opt_clks
,
1756 .opt_clks_cnt
= ARRAY_SIZE(iss_opt_clks
),
1761 * multi-standard video encoder/decoder hardware accelerator
1764 static struct omap_hwmod_class omap44xx_iva_hwmod_class
= {
1769 static struct omap_hwmod_irq_info omap44xx_iva_irqs
[] = {
1770 { .name
= "sync_1", .irq
= 103 + OMAP44XX_IRQ_GIC_START
},
1771 { .name
= "sync_0", .irq
= 104 + OMAP44XX_IRQ_GIC_START
},
1772 { .name
= "mailbox_0", .irq
= 107 + OMAP44XX_IRQ_GIC_START
},
1776 static struct omap_hwmod_rst_info omap44xx_iva_resets
[] = {
1777 { .name
= "seq0", .rst_shift
= 0 },
1778 { .name
= "seq1", .rst_shift
= 1 },
1779 { .name
= "logic", .rst_shift
= 2 },
1782 static struct omap_hwmod omap44xx_iva_hwmod
= {
1784 .class = &omap44xx_iva_hwmod_class
,
1785 .clkdm_name
= "ivahd_clkdm",
1786 .mpu_irqs
= omap44xx_iva_irqs
,
1787 .rst_lines
= omap44xx_iva_resets
,
1788 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_iva_resets
),
1789 .main_clk
= "dpll_iva_m5x2_ck",
1792 .clkctrl_offs
= OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET
,
1793 .rstctrl_offs
= OMAP4_RM_IVAHD_RSTCTRL_OFFSET
,
1794 .context_offs
= OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET
,
1795 .modulemode
= MODULEMODE_HWCTRL
,
1802 * keyboard controller
1805 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc
= {
1807 .sysc_offs
= 0x0010,
1808 .syss_offs
= 0x0014,
1809 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
1810 SYSC_HAS_EMUFREE
| SYSC_HAS_ENAWAKEUP
|
1811 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
1812 SYSS_HAS_RESET_STATUS
),
1813 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1814 .sysc_fields
= &omap_hwmod_sysc_type1
,
1817 static struct omap_hwmod_class omap44xx_kbd_hwmod_class
= {
1819 .sysc
= &omap44xx_kbd_sysc
,
1823 static struct omap_hwmod_irq_info omap44xx_kbd_irqs
[] = {
1824 { .irq
= 120 + OMAP44XX_IRQ_GIC_START
},
1828 static struct omap_hwmod omap44xx_kbd_hwmod
= {
1830 .class = &omap44xx_kbd_hwmod_class
,
1831 .clkdm_name
= "l4_wkup_clkdm",
1832 .mpu_irqs
= omap44xx_kbd_irqs
,
1833 .main_clk
= "sys_32k_ck",
1836 .clkctrl_offs
= OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET
,
1837 .context_offs
= OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET
,
1838 .modulemode
= MODULEMODE_SWCTRL
,
1845 * mailbox module allowing communication between the on-chip processors using a
1846 * queued mailbox-interrupt mechanism.
1849 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc
= {
1851 .sysc_offs
= 0x0010,
1852 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
1853 SYSC_HAS_SOFTRESET
),
1854 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1855 .sysc_fields
= &omap_hwmod_sysc_type2
,
1858 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class
= {
1860 .sysc
= &omap44xx_mailbox_sysc
,
1864 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs
[] = {
1865 { .irq
= 26 + OMAP44XX_IRQ_GIC_START
},
1869 static struct omap_hwmod omap44xx_mailbox_hwmod
= {
1871 .class = &omap44xx_mailbox_hwmod_class
,
1872 .clkdm_name
= "l4_cfg_clkdm",
1873 .mpu_irqs
= omap44xx_mailbox_irqs
,
1876 .clkctrl_offs
= OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET
,
1877 .context_offs
= OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET
,
1884 * multi-channel audio serial port controller
1887 /* The IP is not compliant to type1 / type2 scheme */
1888 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp
= {
1892 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc
= {
1893 .sysc_offs
= 0x0004,
1894 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
1895 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1897 .sysc_fields
= &omap_hwmod_sysc_type_mcasp
,
1900 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class
= {
1902 .sysc
= &omap44xx_mcasp_sysc
,
1906 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs
[] = {
1907 { .name
= "arevt", .irq
= 108 + OMAP44XX_IRQ_GIC_START
},
1908 { .name
= "axevt", .irq
= 109 + OMAP44XX_IRQ_GIC_START
},
1912 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs
[] = {
1913 { .name
= "axevt", .dma_req
= 7 + OMAP44XX_DMA_REQ_START
},
1914 { .name
= "arevt", .dma_req
= 10 + OMAP44XX_DMA_REQ_START
},
1918 static struct omap_hwmod omap44xx_mcasp_hwmod
= {
1920 .class = &omap44xx_mcasp_hwmod_class
,
1921 .clkdm_name
= "abe_clkdm",
1922 .mpu_irqs
= omap44xx_mcasp_irqs
,
1923 .sdma_reqs
= omap44xx_mcasp_sdma_reqs
,
1924 .main_clk
= "func_mcasp_abe_gfclk",
1927 .clkctrl_offs
= OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET
,
1928 .context_offs
= OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET
,
1929 .modulemode
= MODULEMODE_SWCTRL
,
1936 * multi channel buffered serial port controller
1939 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc
= {
1940 .sysc_offs
= 0x008c,
1941 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_ENAWAKEUP
|
1942 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1943 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1944 .sysc_fields
= &omap_hwmod_sysc_type1
,
1947 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class
= {
1949 .sysc
= &omap44xx_mcbsp_sysc
,
1950 .rev
= MCBSP_CONFIG_TYPE4
,
1954 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs
[] = {
1955 { .name
= "common", .irq
= 17 + OMAP44XX_IRQ_GIC_START
},
1959 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs
[] = {
1960 { .name
= "tx", .dma_req
= 32 + OMAP44XX_DMA_REQ_START
},
1961 { .name
= "rx", .dma_req
= 33 + OMAP44XX_DMA_REQ_START
},
1965 static struct omap_hwmod_opt_clk mcbsp1_opt_clks
[] = {
1966 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
1967 { .role
= "prcm_fck", .clk
= "mcbsp1_sync_mux_ck" },
1970 static struct omap_hwmod omap44xx_mcbsp1_hwmod
= {
1972 .class = &omap44xx_mcbsp_hwmod_class
,
1973 .clkdm_name
= "abe_clkdm",
1974 .mpu_irqs
= omap44xx_mcbsp1_irqs
,
1975 .sdma_reqs
= omap44xx_mcbsp1_sdma_reqs
,
1976 .main_clk
= "func_mcbsp1_gfclk",
1979 .clkctrl_offs
= OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET
,
1980 .context_offs
= OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET
,
1981 .modulemode
= MODULEMODE_SWCTRL
,
1984 .opt_clks
= mcbsp1_opt_clks
,
1985 .opt_clks_cnt
= ARRAY_SIZE(mcbsp1_opt_clks
),
1989 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs
[] = {
1990 { .name
= "common", .irq
= 22 + OMAP44XX_IRQ_GIC_START
},
1994 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs
[] = {
1995 { .name
= "tx", .dma_req
= 16 + OMAP44XX_DMA_REQ_START
},
1996 { .name
= "rx", .dma_req
= 17 + OMAP44XX_DMA_REQ_START
},
2000 static struct omap_hwmod_opt_clk mcbsp2_opt_clks
[] = {
2001 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
2002 { .role
= "prcm_fck", .clk
= "mcbsp2_sync_mux_ck" },
2005 static struct omap_hwmod omap44xx_mcbsp2_hwmod
= {
2007 .class = &omap44xx_mcbsp_hwmod_class
,
2008 .clkdm_name
= "abe_clkdm",
2009 .mpu_irqs
= omap44xx_mcbsp2_irqs
,
2010 .sdma_reqs
= omap44xx_mcbsp2_sdma_reqs
,
2011 .main_clk
= "func_mcbsp2_gfclk",
2014 .clkctrl_offs
= OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET
,
2015 .context_offs
= OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET
,
2016 .modulemode
= MODULEMODE_SWCTRL
,
2019 .opt_clks
= mcbsp2_opt_clks
,
2020 .opt_clks_cnt
= ARRAY_SIZE(mcbsp2_opt_clks
),
2024 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs
[] = {
2025 { .name
= "common", .irq
= 23 + OMAP44XX_IRQ_GIC_START
},
2029 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs
[] = {
2030 { .name
= "tx", .dma_req
= 18 + OMAP44XX_DMA_REQ_START
},
2031 { .name
= "rx", .dma_req
= 19 + OMAP44XX_DMA_REQ_START
},
2035 static struct omap_hwmod_opt_clk mcbsp3_opt_clks
[] = {
2036 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
2037 { .role
= "prcm_fck", .clk
= "mcbsp3_sync_mux_ck" },
2040 static struct omap_hwmod omap44xx_mcbsp3_hwmod
= {
2042 .class = &omap44xx_mcbsp_hwmod_class
,
2043 .clkdm_name
= "abe_clkdm",
2044 .mpu_irqs
= omap44xx_mcbsp3_irqs
,
2045 .sdma_reqs
= omap44xx_mcbsp3_sdma_reqs
,
2046 .main_clk
= "func_mcbsp3_gfclk",
2049 .clkctrl_offs
= OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET
,
2050 .context_offs
= OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET
,
2051 .modulemode
= MODULEMODE_SWCTRL
,
2054 .opt_clks
= mcbsp3_opt_clks
,
2055 .opt_clks_cnt
= ARRAY_SIZE(mcbsp3_opt_clks
),
2059 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs
[] = {
2060 { .name
= "common", .irq
= 16 + OMAP44XX_IRQ_GIC_START
},
2064 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs
[] = {
2065 { .name
= "tx", .dma_req
= 30 + OMAP44XX_DMA_REQ_START
},
2066 { .name
= "rx", .dma_req
= 31 + OMAP44XX_DMA_REQ_START
},
2070 static struct omap_hwmod_opt_clk mcbsp4_opt_clks
[] = {
2071 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
2072 { .role
= "prcm_fck", .clk
= "mcbsp4_sync_mux_ck" },
2075 static struct omap_hwmod omap44xx_mcbsp4_hwmod
= {
2077 .class = &omap44xx_mcbsp_hwmod_class
,
2078 .clkdm_name
= "l4_per_clkdm",
2079 .mpu_irqs
= omap44xx_mcbsp4_irqs
,
2080 .sdma_reqs
= omap44xx_mcbsp4_sdma_reqs
,
2081 .main_clk
= "per_mcbsp4_gfclk",
2084 .clkctrl_offs
= OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET
,
2085 .context_offs
= OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET
,
2086 .modulemode
= MODULEMODE_SWCTRL
,
2089 .opt_clks
= mcbsp4_opt_clks
,
2090 .opt_clks_cnt
= ARRAY_SIZE(mcbsp4_opt_clks
),
2095 * multi channel pdm controller (proprietary interface with phoenix power
2099 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc
= {
2101 .sysc_offs
= 0x0010,
2102 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
2103 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
2104 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2106 .sysc_fields
= &omap_hwmod_sysc_type2
,
2109 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class
= {
2111 .sysc
= &omap44xx_mcpdm_sysc
,
2115 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs
[] = {
2116 { .irq
= 112 + OMAP44XX_IRQ_GIC_START
},
2120 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs
[] = {
2121 { .name
= "up_link", .dma_req
= 64 + OMAP44XX_DMA_REQ_START
},
2122 { .name
= "dn_link", .dma_req
= 65 + OMAP44XX_DMA_REQ_START
},
2126 static struct omap_hwmod omap44xx_mcpdm_hwmod
= {
2128 .class = &omap44xx_mcpdm_hwmod_class
,
2129 .clkdm_name
= "abe_clkdm",
2131 * It's suspected that the McPDM requires an off-chip main
2132 * functional clock, controlled via I2C. This IP block is
2133 * currently reset very early during boot, before I2C is
2134 * available, so it doesn't seem that we have any choice in
2135 * the kernel other than to avoid resetting it.
2137 * Also, McPDM needs to be configured to NO_IDLE mode when it
2138 * is in used otherwise vital clocks will be gated which
2139 * results 'slow motion' audio playback.
2141 .flags
= HWMOD_EXT_OPT_MAIN_CLK
| HWMOD_SWSUP_SIDLE
,
2142 .mpu_irqs
= omap44xx_mcpdm_irqs
,
2143 .sdma_reqs
= omap44xx_mcpdm_sdma_reqs
,
2144 .main_clk
= "pad_clks_ck",
2147 .clkctrl_offs
= OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET
,
2148 .context_offs
= OMAP4_RM_ABE_PDM_CONTEXT_OFFSET
,
2149 .modulemode
= MODULEMODE_SWCTRL
,
2156 * multichannel serial port interface (mcspi) / master/slave synchronous serial
2160 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc
= {
2162 .sysc_offs
= 0x0010,
2163 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
2164 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
2165 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2167 .sysc_fields
= &omap_hwmod_sysc_type2
,
2170 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class
= {
2172 .sysc
= &omap44xx_mcspi_sysc
,
2173 .rev
= OMAP4_MCSPI_REV
,
2177 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs
[] = {
2178 { .irq
= 65 + OMAP44XX_IRQ_GIC_START
},
2182 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs
[] = {
2183 { .name
= "tx0", .dma_req
= 34 + OMAP44XX_DMA_REQ_START
},
2184 { .name
= "rx0", .dma_req
= 35 + OMAP44XX_DMA_REQ_START
},
2185 { .name
= "tx1", .dma_req
= 36 + OMAP44XX_DMA_REQ_START
},
2186 { .name
= "rx1", .dma_req
= 37 + OMAP44XX_DMA_REQ_START
},
2187 { .name
= "tx2", .dma_req
= 38 + OMAP44XX_DMA_REQ_START
},
2188 { .name
= "rx2", .dma_req
= 39 + OMAP44XX_DMA_REQ_START
},
2189 { .name
= "tx3", .dma_req
= 40 + OMAP44XX_DMA_REQ_START
},
2190 { .name
= "rx3", .dma_req
= 41 + OMAP44XX_DMA_REQ_START
},
2194 /* mcspi1 dev_attr */
2195 static struct omap2_mcspi_dev_attr mcspi1_dev_attr
= {
2196 .num_chipselect
= 4,
2199 static struct omap_hwmod omap44xx_mcspi1_hwmod
= {
2201 .class = &omap44xx_mcspi_hwmod_class
,
2202 .clkdm_name
= "l4_per_clkdm",
2203 .mpu_irqs
= omap44xx_mcspi1_irqs
,
2204 .sdma_reqs
= omap44xx_mcspi1_sdma_reqs
,
2205 .main_clk
= "func_48m_fclk",
2208 .clkctrl_offs
= OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET
,
2209 .context_offs
= OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET
,
2210 .modulemode
= MODULEMODE_SWCTRL
,
2213 .dev_attr
= &mcspi1_dev_attr
,
2217 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs
[] = {
2218 { .irq
= 66 + OMAP44XX_IRQ_GIC_START
},
2222 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs
[] = {
2223 { .name
= "tx0", .dma_req
= 42 + OMAP44XX_DMA_REQ_START
},
2224 { .name
= "rx0", .dma_req
= 43 + OMAP44XX_DMA_REQ_START
},
2225 { .name
= "tx1", .dma_req
= 44 + OMAP44XX_DMA_REQ_START
},
2226 { .name
= "rx1", .dma_req
= 45 + OMAP44XX_DMA_REQ_START
},
2230 /* mcspi2 dev_attr */
2231 static struct omap2_mcspi_dev_attr mcspi2_dev_attr
= {
2232 .num_chipselect
= 2,
2235 static struct omap_hwmod omap44xx_mcspi2_hwmod
= {
2237 .class = &omap44xx_mcspi_hwmod_class
,
2238 .clkdm_name
= "l4_per_clkdm",
2239 .mpu_irqs
= omap44xx_mcspi2_irqs
,
2240 .sdma_reqs
= omap44xx_mcspi2_sdma_reqs
,
2241 .main_clk
= "func_48m_fclk",
2244 .clkctrl_offs
= OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET
,
2245 .context_offs
= OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET
,
2246 .modulemode
= MODULEMODE_SWCTRL
,
2249 .dev_attr
= &mcspi2_dev_attr
,
2253 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs
[] = {
2254 { .irq
= 91 + OMAP44XX_IRQ_GIC_START
},
2258 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs
[] = {
2259 { .name
= "tx0", .dma_req
= 14 + OMAP44XX_DMA_REQ_START
},
2260 { .name
= "rx0", .dma_req
= 15 + OMAP44XX_DMA_REQ_START
},
2261 { .name
= "tx1", .dma_req
= 22 + OMAP44XX_DMA_REQ_START
},
2262 { .name
= "rx1", .dma_req
= 23 + OMAP44XX_DMA_REQ_START
},
2266 /* mcspi3 dev_attr */
2267 static struct omap2_mcspi_dev_attr mcspi3_dev_attr
= {
2268 .num_chipselect
= 2,
2271 static struct omap_hwmod omap44xx_mcspi3_hwmod
= {
2273 .class = &omap44xx_mcspi_hwmod_class
,
2274 .clkdm_name
= "l4_per_clkdm",
2275 .mpu_irqs
= omap44xx_mcspi3_irqs
,
2276 .sdma_reqs
= omap44xx_mcspi3_sdma_reqs
,
2277 .main_clk
= "func_48m_fclk",
2280 .clkctrl_offs
= OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET
,
2281 .context_offs
= OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET
,
2282 .modulemode
= MODULEMODE_SWCTRL
,
2285 .dev_attr
= &mcspi3_dev_attr
,
2289 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs
[] = {
2290 { .irq
= 48 + OMAP44XX_IRQ_GIC_START
},
2294 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs
[] = {
2295 { .name
= "tx0", .dma_req
= 69 + OMAP44XX_DMA_REQ_START
},
2296 { .name
= "rx0", .dma_req
= 70 + OMAP44XX_DMA_REQ_START
},
2300 /* mcspi4 dev_attr */
2301 static struct omap2_mcspi_dev_attr mcspi4_dev_attr
= {
2302 .num_chipselect
= 1,
2305 static struct omap_hwmod omap44xx_mcspi4_hwmod
= {
2307 .class = &omap44xx_mcspi_hwmod_class
,
2308 .clkdm_name
= "l4_per_clkdm",
2309 .mpu_irqs
= omap44xx_mcspi4_irqs
,
2310 .sdma_reqs
= omap44xx_mcspi4_sdma_reqs
,
2311 .main_clk
= "func_48m_fclk",
2314 .clkctrl_offs
= OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET
,
2315 .context_offs
= OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET
,
2316 .modulemode
= MODULEMODE_SWCTRL
,
2319 .dev_attr
= &mcspi4_dev_attr
,
2324 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2327 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc
= {
2329 .sysc_offs
= 0x0010,
2330 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_MIDLEMODE
|
2331 SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
2332 SYSC_HAS_SOFTRESET
),
2333 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2334 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
2335 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
2336 .sysc_fields
= &omap_hwmod_sysc_type2
,
2339 static struct omap_hwmod_class omap44xx_mmc_hwmod_class
= {
2341 .sysc
= &omap44xx_mmc_sysc
,
2345 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs
[] = {
2346 { .irq
= 83 + OMAP44XX_IRQ_GIC_START
},
2350 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs
[] = {
2351 { .name
= "tx", .dma_req
= 60 + OMAP44XX_DMA_REQ_START
},
2352 { .name
= "rx", .dma_req
= 61 + OMAP44XX_DMA_REQ_START
},
2357 static struct omap_mmc_dev_attr mmc1_dev_attr
= {
2358 .flags
= OMAP_HSMMC_SUPPORTS_DUAL_VOLT
,
2361 static struct omap_hwmod omap44xx_mmc1_hwmod
= {
2363 .class = &omap44xx_mmc_hwmod_class
,
2364 .clkdm_name
= "l3_init_clkdm",
2365 .mpu_irqs
= omap44xx_mmc1_irqs
,
2366 .sdma_reqs
= omap44xx_mmc1_sdma_reqs
,
2367 .main_clk
= "hsmmc1_fclk",
2370 .clkctrl_offs
= OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET
,
2371 .context_offs
= OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET
,
2372 .modulemode
= MODULEMODE_SWCTRL
,
2375 .dev_attr
= &mmc1_dev_attr
,
2379 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs
[] = {
2380 { .irq
= 86 + OMAP44XX_IRQ_GIC_START
},
2384 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs
[] = {
2385 { .name
= "tx", .dma_req
= 46 + OMAP44XX_DMA_REQ_START
},
2386 { .name
= "rx", .dma_req
= 47 + OMAP44XX_DMA_REQ_START
},
2390 static struct omap_hwmod omap44xx_mmc2_hwmod
= {
2392 .class = &omap44xx_mmc_hwmod_class
,
2393 .clkdm_name
= "l3_init_clkdm",
2394 .mpu_irqs
= omap44xx_mmc2_irqs
,
2395 .sdma_reqs
= omap44xx_mmc2_sdma_reqs
,
2396 .main_clk
= "hsmmc2_fclk",
2399 .clkctrl_offs
= OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET
,
2400 .context_offs
= OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET
,
2401 .modulemode
= MODULEMODE_SWCTRL
,
2407 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs
[] = {
2408 { .irq
= 94 + OMAP44XX_IRQ_GIC_START
},
2412 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs
[] = {
2413 { .name
= "tx", .dma_req
= 76 + OMAP44XX_DMA_REQ_START
},
2414 { .name
= "rx", .dma_req
= 77 + OMAP44XX_DMA_REQ_START
},
2418 static struct omap_hwmod omap44xx_mmc3_hwmod
= {
2420 .class = &omap44xx_mmc_hwmod_class
,
2421 .clkdm_name
= "l4_per_clkdm",
2422 .mpu_irqs
= omap44xx_mmc3_irqs
,
2423 .sdma_reqs
= omap44xx_mmc3_sdma_reqs
,
2424 .main_clk
= "func_48m_fclk",
2427 .clkctrl_offs
= OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET
,
2428 .context_offs
= OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET
,
2429 .modulemode
= MODULEMODE_SWCTRL
,
2435 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs
[] = {
2436 { .irq
= 96 + OMAP44XX_IRQ_GIC_START
},
2440 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs
[] = {
2441 { .name
= "tx", .dma_req
= 56 + OMAP44XX_DMA_REQ_START
},
2442 { .name
= "rx", .dma_req
= 57 + OMAP44XX_DMA_REQ_START
},
2446 static struct omap_hwmod omap44xx_mmc4_hwmod
= {
2448 .class = &omap44xx_mmc_hwmod_class
,
2449 .clkdm_name
= "l4_per_clkdm",
2450 .mpu_irqs
= omap44xx_mmc4_irqs
,
2451 .sdma_reqs
= omap44xx_mmc4_sdma_reqs
,
2452 .main_clk
= "func_48m_fclk",
2455 .clkctrl_offs
= OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET
,
2456 .context_offs
= OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET
,
2457 .modulemode
= MODULEMODE_SWCTRL
,
2463 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs
[] = {
2464 { .irq
= 59 + OMAP44XX_IRQ_GIC_START
},
2468 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs
[] = {
2469 { .name
= "tx", .dma_req
= 58 + OMAP44XX_DMA_REQ_START
},
2470 { .name
= "rx", .dma_req
= 59 + OMAP44XX_DMA_REQ_START
},
2474 static struct omap_hwmod omap44xx_mmc5_hwmod
= {
2476 .class = &omap44xx_mmc_hwmod_class
,
2477 .clkdm_name
= "l4_per_clkdm",
2478 .mpu_irqs
= omap44xx_mmc5_irqs
,
2479 .sdma_reqs
= omap44xx_mmc5_sdma_reqs
,
2480 .main_clk
= "func_48m_fclk",
2483 .clkctrl_offs
= OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET
,
2484 .context_offs
= OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET
,
2485 .modulemode
= MODULEMODE_SWCTRL
,
2492 * The memory management unit performs virtual to physical address translation
2493 * for its requestors.
2496 static struct omap_hwmod_class_sysconfig mmu_sysc
= {
2500 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
2501 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
),
2502 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
2503 .sysc_fields
= &omap_hwmod_sysc_type1
,
2506 static struct omap_hwmod_class omap44xx_mmu_hwmod_class
= {
2513 static struct omap_mmu_dev_attr mmu_ipu_dev_attr
= {
2515 .da_end
= 0xfffff000,
2516 .nr_tlb_entries
= 32,
2519 static struct omap_hwmod omap44xx_mmu_ipu_hwmod
;
2520 static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs
[] = {
2521 { .irq
= 100 + OMAP44XX_IRQ_GIC_START
, },
2525 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets
[] = {
2526 { .name
= "mmu_cache", .rst_shift
= 2 },
2529 static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs
[] = {
2531 .pa_start
= 0x55082000,
2532 .pa_end
= 0x550820ff,
2533 .flags
= ADDR_TYPE_RT
,
2538 /* l3_main_2 -> mmu_ipu */
2539 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu
= {
2540 .master
= &omap44xx_l3_main_2_hwmod
,
2541 .slave
= &omap44xx_mmu_ipu_hwmod
,
2543 .addr
= omap44xx_mmu_ipu_addrs
,
2544 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2547 static struct omap_hwmod omap44xx_mmu_ipu_hwmod
= {
2549 .class = &omap44xx_mmu_hwmod_class
,
2550 .clkdm_name
= "ducati_clkdm",
2551 .mpu_irqs
= omap44xx_mmu_ipu_irqs
,
2552 .rst_lines
= omap44xx_mmu_ipu_resets
,
2553 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_mmu_ipu_resets
),
2554 .main_clk
= "ducati_clk_mux_ck",
2557 .clkctrl_offs
= OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET
,
2558 .rstctrl_offs
= OMAP4_RM_DUCATI_RSTCTRL_OFFSET
,
2559 .context_offs
= OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET
,
2560 .modulemode
= MODULEMODE_HWCTRL
,
2563 .dev_attr
= &mmu_ipu_dev_attr
,
2568 static struct omap_mmu_dev_attr mmu_dsp_dev_attr
= {
2570 .da_end
= 0xfffff000,
2571 .nr_tlb_entries
= 32,
2574 static struct omap_hwmod omap44xx_mmu_dsp_hwmod
;
2575 static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs
[] = {
2576 { .irq
= 28 + OMAP44XX_IRQ_GIC_START
},
2580 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets
[] = {
2581 { .name
= "mmu_cache", .rst_shift
= 1 },
2584 static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs
[] = {
2586 .pa_start
= 0x4a066000,
2587 .pa_end
= 0x4a0660ff,
2588 .flags
= ADDR_TYPE_RT
,
2594 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp
= {
2595 .master
= &omap44xx_l4_cfg_hwmod
,
2596 .slave
= &omap44xx_mmu_dsp_hwmod
,
2598 .addr
= omap44xx_mmu_dsp_addrs
,
2599 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2602 static struct omap_hwmod omap44xx_mmu_dsp_hwmod
= {
2604 .class = &omap44xx_mmu_hwmod_class
,
2605 .clkdm_name
= "tesla_clkdm",
2606 .mpu_irqs
= omap44xx_mmu_dsp_irqs
,
2607 .rst_lines
= omap44xx_mmu_dsp_resets
,
2608 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_mmu_dsp_resets
),
2609 .main_clk
= "dpll_iva_m4x2_ck",
2612 .clkctrl_offs
= OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET
,
2613 .rstctrl_offs
= OMAP4_RM_TESLA_RSTCTRL_OFFSET
,
2614 .context_offs
= OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET
,
2615 .modulemode
= MODULEMODE_HWCTRL
,
2618 .dev_attr
= &mmu_dsp_dev_attr
,
2626 static struct omap_hwmod_class omap44xx_mpu_hwmod_class
= {
2631 static struct omap_hwmod_irq_info omap44xx_mpu_irqs
[] = {
2632 { .name
= "pmu0", .irq
= 54 + OMAP44XX_IRQ_GIC_START
},
2633 { .name
= "pmu1", .irq
= 55 + OMAP44XX_IRQ_GIC_START
},
2634 { .name
= "pl310", .irq
= 0 + OMAP44XX_IRQ_GIC_START
},
2635 { .name
= "cti0", .irq
= 1 + OMAP44XX_IRQ_GIC_START
},
2636 { .name
= "cti1", .irq
= 2 + OMAP44XX_IRQ_GIC_START
},
2640 static struct omap_hwmod omap44xx_mpu_hwmod
= {
2642 .class = &omap44xx_mpu_hwmod_class
,
2643 .clkdm_name
= "mpuss_clkdm",
2644 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
2645 .mpu_irqs
= omap44xx_mpu_irqs
,
2646 .main_clk
= "dpll_mpu_m2_ck",
2649 .clkctrl_offs
= OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET
,
2650 .context_offs
= OMAP4_RM_MPU_MPU_CONTEXT_OFFSET
,
2657 * top-level core on-chip ram
2660 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class
= {
2665 static struct omap_hwmod omap44xx_ocmc_ram_hwmod
= {
2667 .class = &omap44xx_ocmc_ram_hwmod_class
,
2668 .clkdm_name
= "l3_2_clkdm",
2671 .clkctrl_offs
= OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET
,
2672 .context_offs
= OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET
,
2679 * bridge to transform ocp interface protocol to scp (serial control port)
2683 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc
= {
2685 .sysc_offs
= 0x0010,
2686 .syss_offs
= 0x0014,
2687 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SIDLEMODE
|
2688 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
2689 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
2690 .sysc_fields
= &omap_hwmod_sysc_type1
,
2693 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class
= {
2695 .sysc
= &omap44xx_ocp2scp_sysc
,
2698 /* ocp2scp dev_attr */
2699 static struct resource omap44xx_usb_phy_and_pll_addrs
[] = {
2702 .start
= 0x4a0ad080,
2704 .flags
= IORESOURCE_MEM
,
2709 static struct omap_ocp2scp_dev ocp2scp_dev_attr
[] = {
2711 .drv_name
= "omap-usb2",
2712 .res
= omap44xx_usb_phy_and_pll_addrs
,
2717 /* ocp2scp_usb_phy */
2718 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod
= {
2719 .name
= "ocp2scp_usb_phy",
2720 .class = &omap44xx_ocp2scp_hwmod_class
,
2721 .clkdm_name
= "l3_init_clkdm",
2723 * ocp2scp_usb_phy_phy_48m is provided by the OMAP4 PRCM IP
2724 * block as an "optional clock," and normally should never be
2725 * specified as the main_clk for an OMAP IP block. However it
2726 * turns out that this clock is actually the main clock for
2727 * the ocp2scp_usb_phy IP block:
2728 * http://lists.infradead.org/pipermail/linux-arm-kernel/2012-September/119943.html
2729 * So listing ocp2scp_usb_phy_phy_48m as a main_clk here seems
2730 * to be the best workaround.
2732 .main_clk
= "ocp2scp_usb_phy_phy_48m",
2735 .clkctrl_offs
= OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET
,
2736 .context_offs
= OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET
,
2737 .modulemode
= MODULEMODE_HWCTRL
,
2740 .dev_attr
= ocp2scp_dev_attr
,
2745 * power and reset manager (part of the prcm infrastructure) + clock manager 2
2746 * + clock manager 1 (in always on power domain) + local prm in mpu
2749 static struct omap_hwmod_class omap44xx_prcm_hwmod_class
= {
2754 static struct omap_hwmod omap44xx_prcm_mpu_hwmod
= {
2756 .class = &omap44xx_prcm_hwmod_class
,
2757 .clkdm_name
= "l4_wkup_clkdm",
2758 .flags
= HWMOD_NO_IDLEST
,
2761 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
2767 static struct omap_hwmod omap44xx_cm_core_aon_hwmod
= {
2768 .name
= "cm_core_aon",
2769 .class = &omap44xx_prcm_hwmod_class
,
2770 .flags
= HWMOD_NO_IDLEST
,
2773 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
2779 static struct omap_hwmod omap44xx_cm_core_hwmod
= {
2781 .class = &omap44xx_prcm_hwmod_class
,
2782 .flags
= HWMOD_NO_IDLEST
,
2785 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
2791 static struct omap_hwmod_irq_info omap44xx_prm_irqs
[] = {
2792 { .irq
= 11 + OMAP44XX_IRQ_GIC_START
},
2796 static struct omap_hwmod_rst_info omap44xx_prm_resets
[] = {
2797 { .name
= "rst_global_warm_sw", .rst_shift
= 0 },
2798 { .name
= "rst_global_cold_sw", .rst_shift
= 1 },
2801 static struct omap_hwmod omap44xx_prm_hwmod
= {
2803 .class = &omap44xx_prcm_hwmod_class
,
2804 .mpu_irqs
= omap44xx_prm_irqs
,
2805 .rst_lines
= omap44xx_prm_resets
,
2806 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_prm_resets
),
2811 * system clock and reset manager
2814 static struct omap_hwmod_class omap44xx_scrm_hwmod_class
= {
2819 static struct omap_hwmod omap44xx_scrm_hwmod
= {
2821 .class = &omap44xx_scrm_hwmod_class
,
2822 .clkdm_name
= "l4_wkup_clkdm",
2825 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
2832 * shared level 2 memory interface
2835 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class
= {
2840 static struct omap_hwmod omap44xx_sl2if_hwmod
= {
2842 .class = &omap44xx_sl2if_hwmod_class
,
2843 .clkdm_name
= "ivahd_clkdm",
2846 .clkctrl_offs
= OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET
,
2847 .context_offs
= OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET
,
2848 .modulemode
= MODULEMODE_HWCTRL
,
2855 * bidirectional, multi-drop, multi-channel two-line serial interface between
2856 * the device and external components
2859 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc
= {
2861 .sysc_offs
= 0x0010,
2862 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
2863 SYSC_HAS_SOFTRESET
),
2864 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2866 .sysc_fields
= &omap_hwmod_sysc_type2
,
2869 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class
= {
2871 .sysc
= &omap44xx_slimbus_sysc
,
2875 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs
[] = {
2876 { .irq
= 97 + OMAP44XX_IRQ_GIC_START
},
2880 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs
[] = {
2881 { .name
= "tx0", .dma_req
= 84 + OMAP44XX_DMA_REQ_START
},
2882 { .name
= "tx1", .dma_req
= 85 + OMAP44XX_DMA_REQ_START
},
2883 { .name
= "tx2", .dma_req
= 86 + OMAP44XX_DMA_REQ_START
},
2884 { .name
= "tx3", .dma_req
= 87 + OMAP44XX_DMA_REQ_START
},
2885 { .name
= "rx0", .dma_req
= 88 + OMAP44XX_DMA_REQ_START
},
2886 { .name
= "rx1", .dma_req
= 89 + OMAP44XX_DMA_REQ_START
},
2887 { .name
= "rx2", .dma_req
= 90 + OMAP44XX_DMA_REQ_START
},
2888 { .name
= "rx3", .dma_req
= 91 + OMAP44XX_DMA_REQ_START
},
2892 static struct omap_hwmod_opt_clk slimbus1_opt_clks
[] = {
2893 { .role
= "fclk_1", .clk
= "slimbus1_fclk_1" },
2894 { .role
= "fclk_0", .clk
= "slimbus1_fclk_0" },
2895 { .role
= "fclk_2", .clk
= "slimbus1_fclk_2" },
2896 { .role
= "slimbus_clk", .clk
= "slimbus1_slimbus_clk" },
2899 static struct omap_hwmod omap44xx_slimbus1_hwmod
= {
2901 .class = &omap44xx_slimbus_hwmod_class
,
2902 .clkdm_name
= "abe_clkdm",
2903 .mpu_irqs
= omap44xx_slimbus1_irqs
,
2904 .sdma_reqs
= omap44xx_slimbus1_sdma_reqs
,
2907 .clkctrl_offs
= OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET
,
2908 .context_offs
= OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET
,
2909 .modulemode
= MODULEMODE_SWCTRL
,
2912 .opt_clks
= slimbus1_opt_clks
,
2913 .opt_clks_cnt
= ARRAY_SIZE(slimbus1_opt_clks
),
2917 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs
[] = {
2918 { .irq
= 98 + OMAP44XX_IRQ_GIC_START
},
2922 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs
[] = {
2923 { .name
= "tx0", .dma_req
= 92 + OMAP44XX_DMA_REQ_START
},
2924 { .name
= "tx1", .dma_req
= 93 + OMAP44XX_DMA_REQ_START
},
2925 { .name
= "tx2", .dma_req
= 94 + OMAP44XX_DMA_REQ_START
},
2926 { .name
= "tx3", .dma_req
= 95 + OMAP44XX_DMA_REQ_START
},
2927 { .name
= "rx0", .dma_req
= 96 + OMAP44XX_DMA_REQ_START
},
2928 { .name
= "rx1", .dma_req
= 97 + OMAP44XX_DMA_REQ_START
},
2929 { .name
= "rx2", .dma_req
= 98 + OMAP44XX_DMA_REQ_START
},
2930 { .name
= "rx3", .dma_req
= 99 + OMAP44XX_DMA_REQ_START
},
2934 static struct omap_hwmod_opt_clk slimbus2_opt_clks
[] = {
2935 { .role
= "fclk_1", .clk
= "slimbus2_fclk_1" },
2936 { .role
= "fclk_0", .clk
= "slimbus2_fclk_0" },
2937 { .role
= "slimbus_clk", .clk
= "slimbus2_slimbus_clk" },
2940 static struct omap_hwmod omap44xx_slimbus2_hwmod
= {
2942 .class = &omap44xx_slimbus_hwmod_class
,
2943 .clkdm_name
= "l4_per_clkdm",
2944 .mpu_irqs
= omap44xx_slimbus2_irqs
,
2945 .sdma_reqs
= omap44xx_slimbus2_sdma_reqs
,
2948 .clkctrl_offs
= OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET
,
2949 .context_offs
= OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET
,
2950 .modulemode
= MODULEMODE_SWCTRL
,
2953 .opt_clks
= slimbus2_opt_clks
,
2954 .opt_clks_cnt
= ARRAY_SIZE(slimbus2_opt_clks
),
2958 * 'smartreflex' class
2959 * smartreflex module (monitor silicon performance and outputs a measure of
2960 * performance error)
2963 /* The IP is not compliant to type1 / type2 scheme */
2964 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex
= {
2969 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc
= {
2970 .sysc_offs
= 0x0038,
2971 .sysc_flags
= (SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
),
2972 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2974 .sysc_fields
= &omap_hwmod_sysc_type_smartreflex
,
2977 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class
= {
2978 .name
= "smartreflex",
2979 .sysc
= &omap44xx_smartreflex_sysc
,
2983 /* smartreflex_core */
2984 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr
= {
2985 .sensor_voltdm_name
= "core",
2988 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs
[] = {
2989 { .irq
= 19 + OMAP44XX_IRQ_GIC_START
},
2993 static struct omap_hwmod omap44xx_smartreflex_core_hwmod
= {
2994 .name
= "smartreflex_core",
2995 .class = &omap44xx_smartreflex_hwmod_class
,
2996 .clkdm_name
= "l4_ao_clkdm",
2997 .mpu_irqs
= omap44xx_smartreflex_core_irqs
,
2999 .main_clk
= "smartreflex_core_fck",
3002 .clkctrl_offs
= OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET
,
3003 .context_offs
= OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET
,
3004 .modulemode
= MODULEMODE_SWCTRL
,
3007 .dev_attr
= &smartreflex_core_dev_attr
,
3010 /* smartreflex_iva */
3011 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr
= {
3012 .sensor_voltdm_name
= "iva",
3015 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs
[] = {
3016 { .irq
= 102 + OMAP44XX_IRQ_GIC_START
},
3020 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod
= {
3021 .name
= "smartreflex_iva",
3022 .class = &omap44xx_smartreflex_hwmod_class
,
3023 .clkdm_name
= "l4_ao_clkdm",
3024 .mpu_irqs
= omap44xx_smartreflex_iva_irqs
,
3025 .main_clk
= "smartreflex_iva_fck",
3028 .clkctrl_offs
= OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET
,
3029 .context_offs
= OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET
,
3030 .modulemode
= MODULEMODE_SWCTRL
,
3033 .dev_attr
= &smartreflex_iva_dev_attr
,
3036 /* smartreflex_mpu */
3037 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr
= {
3038 .sensor_voltdm_name
= "mpu",
3041 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs
[] = {
3042 { .irq
= 18 + OMAP44XX_IRQ_GIC_START
},
3046 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod
= {
3047 .name
= "smartreflex_mpu",
3048 .class = &omap44xx_smartreflex_hwmod_class
,
3049 .clkdm_name
= "l4_ao_clkdm",
3050 .mpu_irqs
= omap44xx_smartreflex_mpu_irqs
,
3051 .main_clk
= "smartreflex_mpu_fck",
3054 .clkctrl_offs
= OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET
,
3055 .context_offs
= OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET
,
3056 .modulemode
= MODULEMODE_SWCTRL
,
3059 .dev_attr
= &smartreflex_mpu_dev_attr
,
3064 * spinlock provides hardware assistance for synchronizing the processes
3065 * running on multiple processors
3068 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc
= {
3070 .sysc_offs
= 0x0010,
3071 .syss_offs
= 0x0014,
3072 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
3073 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
3074 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
3075 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3077 .sysc_fields
= &omap_hwmod_sysc_type1
,
3080 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class
= {
3082 .sysc
= &omap44xx_spinlock_sysc
,
3086 static struct omap_hwmod omap44xx_spinlock_hwmod
= {
3088 .class = &omap44xx_spinlock_hwmod_class
,
3089 .clkdm_name
= "l4_cfg_clkdm",
3092 .clkctrl_offs
= OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET
,
3093 .context_offs
= OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET
,
3100 * general purpose timer module with accurate 1ms tick
3101 * This class contains several variants: ['timer_1ms', 'timer']
3104 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc
= {
3106 .sysc_offs
= 0x0010,
3107 .syss_offs
= 0x0014,
3108 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
3109 SYSC_HAS_EMUFREE
| SYSC_HAS_ENAWAKEUP
|
3110 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
3111 SYSS_HAS_RESET_STATUS
),
3112 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
3113 .clockact
= CLOCKACT_TEST_ICLK
,
3114 .sysc_fields
= &omap_hwmod_sysc_type1
,
3117 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class
= {
3119 .sysc
= &omap44xx_timer_1ms_sysc
,
3122 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc
= {
3124 .sysc_offs
= 0x0010,
3125 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
3126 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
3127 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3129 .sysc_fields
= &omap_hwmod_sysc_type2
,
3132 static struct omap_hwmod_class omap44xx_timer_hwmod_class
= {
3134 .sysc
= &omap44xx_timer_sysc
,
3137 /* always-on timers dev attribute */
3138 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr
= {
3139 .timer_capability
= OMAP_TIMER_ALWON
,
3142 /* pwm timers dev attribute */
3143 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr
= {
3144 .timer_capability
= OMAP_TIMER_HAS_PWM
,
3147 /* timers with DSP interrupt dev attribute */
3148 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr
= {
3149 .timer_capability
= OMAP_TIMER_HAS_DSP_IRQ
,
3152 /* pwm timers with DSP interrupt dev attribute */
3153 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr
= {
3154 .timer_capability
= OMAP_TIMER_HAS_DSP_IRQ
| OMAP_TIMER_HAS_PWM
,
3158 static struct omap_hwmod_irq_info omap44xx_timer1_irqs
[] = {
3159 { .irq
= 37 + OMAP44XX_IRQ_GIC_START
},
3163 static struct omap_hwmod omap44xx_timer1_hwmod
= {
3165 .class = &omap44xx_timer_1ms_hwmod_class
,
3166 .clkdm_name
= "l4_wkup_clkdm",
3167 .flags
= HWMOD_SET_DEFAULT_CLOCKACT
,
3168 .mpu_irqs
= omap44xx_timer1_irqs
,
3169 .main_clk
= "dmt1_clk_mux",
3172 .clkctrl_offs
= OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET
,
3173 .context_offs
= OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET
,
3174 .modulemode
= MODULEMODE_SWCTRL
,
3177 .dev_attr
= &capability_alwon_dev_attr
,
3181 static struct omap_hwmod_irq_info omap44xx_timer2_irqs
[] = {
3182 { .irq
= 38 + OMAP44XX_IRQ_GIC_START
},
3186 static struct omap_hwmod omap44xx_timer2_hwmod
= {
3188 .class = &omap44xx_timer_1ms_hwmod_class
,
3189 .clkdm_name
= "l4_per_clkdm",
3190 .flags
= HWMOD_SET_DEFAULT_CLOCKACT
,
3191 .mpu_irqs
= omap44xx_timer2_irqs
,
3192 .main_clk
= "cm2_dm2_mux",
3195 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET
,
3196 .context_offs
= OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET
,
3197 .modulemode
= MODULEMODE_SWCTRL
,
3203 static struct omap_hwmod_irq_info omap44xx_timer3_irqs
[] = {
3204 { .irq
= 39 + OMAP44XX_IRQ_GIC_START
},
3208 static struct omap_hwmod omap44xx_timer3_hwmod
= {
3210 .class = &omap44xx_timer_hwmod_class
,
3211 .clkdm_name
= "l4_per_clkdm",
3212 .mpu_irqs
= omap44xx_timer3_irqs
,
3213 .main_clk
= "cm2_dm3_mux",
3216 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET
,
3217 .context_offs
= OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET
,
3218 .modulemode
= MODULEMODE_SWCTRL
,
3224 static struct omap_hwmod_irq_info omap44xx_timer4_irqs
[] = {
3225 { .irq
= 40 + OMAP44XX_IRQ_GIC_START
},
3229 static struct omap_hwmod omap44xx_timer4_hwmod
= {
3231 .class = &omap44xx_timer_hwmod_class
,
3232 .clkdm_name
= "l4_per_clkdm",
3233 .mpu_irqs
= omap44xx_timer4_irqs
,
3234 .main_clk
= "cm2_dm4_mux",
3237 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET
,
3238 .context_offs
= OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET
,
3239 .modulemode
= MODULEMODE_SWCTRL
,
3245 static struct omap_hwmod_irq_info omap44xx_timer5_irqs
[] = {
3246 { .irq
= 41 + OMAP44XX_IRQ_GIC_START
},
3250 static struct omap_hwmod omap44xx_timer5_hwmod
= {
3252 .class = &omap44xx_timer_hwmod_class
,
3253 .clkdm_name
= "abe_clkdm",
3254 .mpu_irqs
= omap44xx_timer5_irqs
,
3255 .main_clk
= "timer5_sync_mux",
3258 .clkctrl_offs
= OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET
,
3259 .context_offs
= OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET
,
3260 .modulemode
= MODULEMODE_SWCTRL
,
3263 .dev_attr
= &capability_dsp_dev_attr
,
3267 static struct omap_hwmod_irq_info omap44xx_timer6_irqs
[] = {
3268 { .irq
= 42 + OMAP44XX_IRQ_GIC_START
},
3272 static struct omap_hwmod omap44xx_timer6_hwmod
= {
3274 .class = &omap44xx_timer_hwmod_class
,
3275 .clkdm_name
= "abe_clkdm",
3276 .mpu_irqs
= omap44xx_timer6_irqs
,
3277 .main_clk
= "timer6_sync_mux",
3280 .clkctrl_offs
= OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET
,
3281 .context_offs
= OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET
,
3282 .modulemode
= MODULEMODE_SWCTRL
,
3285 .dev_attr
= &capability_dsp_dev_attr
,
3289 static struct omap_hwmod_irq_info omap44xx_timer7_irqs
[] = {
3290 { .irq
= 43 + OMAP44XX_IRQ_GIC_START
},
3294 static struct omap_hwmod omap44xx_timer7_hwmod
= {
3296 .class = &omap44xx_timer_hwmod_class
,
3297 .clkdm_name
= "abe_clkdm",
3298 .mpu_irqs
= omap44xx_timer7_irqs
,
3299 .main_clk
= "timer7_sync_mux",
3302 .clkctrl_offs
= OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET
,
3303 .context_offs
= OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET
,
3304 .modulemode
= MODULEMODE_SWCTRL
,
3307 .dev_attr
= &capability_dsp_dev_attr
,
3311 static struct omap_hwmod_irq_info omap44xx_timer8_irqs
[] = {
3312 { .irq
= 44 + OMAP44XX_IRQ_GIC_START
},
3316 static struct omap_hwmod omap44xx_timer8_hwmod
= {
3318 .class = &omap44xx_timer_hwmod_class
,
3319 .clkdm_name
= "abe_clkdm",
3320 .mpu_irqs
= omap44xx_timer8_irqs
,
3321 .main_clk
= "timer8_sync_mux",
3324 .clkctrl_offs
= OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET
,
3325 .context_offs
= OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET
,
3326 .modulemode
= MODULEMODE_SWCTRL
,
3329 .dev_attr
= &capability_dsp_pwm_dev_attr
,
3333 static struct omap_hwmod_irq_info omap44xx_timer9_irqs
[] = {
3334 { .irq
= 45 + OMAP44XX_IRQ_GIC_START
},
3338 static struct omap_hwmod omap44xx_timer9_hwmod
= {
3340 .class = &omap44xx_timer_hwmod_class
,
3341 .clkdm_name
= "l4_per_clkdm",
3342 .mpu_irqs
= omap44xx_timer9_irqs
,
3343 .main_clk
= "cm2_dm9_mux",
3346 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET
,
3347 .context_offs
= OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET
,
3348 .modulemode
= MODULEMODE_SWCTRL
,
3351 .dev_attr
= &capability_pwm_dev_attr
,
3355 static struct omap_hwmod_irq_info omap44xx_timer10_irqs
[] = {
3356 { .irq
= 46 + OMAP44XX_IRQ_GIC_START
},
3360 static struct omap_hwmod omap44xx_timer10_hwmod
= {
3362 .class = &omap44xx_timer_1ms_hwmod_class
,
3363 .clkdm_name
= "l4_per_clkdm",
3364 .flags
= HWMOD_SET_DEFAULT_CLOCKACT
,
3365 .mpu_irqs
= omap44xx_timer10_irqs
,
3366 .main_clk
= "cm2_dm10_mux",
3369 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET
,
3370 .context_offs
= OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET
,
3371 .modulemode
= MODULEMODE_SWCTRL
,
3374 .dev_attr
= &capability_pwm_dev_attr
,
3378 static struct omap_hwmod_irq_info omap44xx_timer11_irqs
[] = {
3379 { .irq
= 47 + OMAP44XX_IRQ_GIC_START
},
3383 static struct omap_hwmod omap44xx_timer11_hwmod
= {
3385 .class = &omap44xx_timer_hwmod_class
,
3386 .clkdm_name
= "l4_per_clkdm",
3387 .mpu_irqs
= omap44xx_timer11_irqs
,
3388 .main_clk
= "cm2_dm11_mux",
3391 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET
,
3392 .context_offs
= OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET
,
3393 .modulemode
= MODULEMODE_SWCTRL
,
3396 .dev_attr
= &capability_pwm_dev_attr
,
3401 * universal asynchronous receiver/transmitter (uart)
3404 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc
= {
3406 .sysc_offs
= 0x0054,
3407 .syss_offs
= 0x0058,
3408 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
3409 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
3410 SYSS_HAS_RESET_STATUS
),
3411 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3413 .sysc_fields
= &omap_hwmod_sysc_type1
,
3416 static struct omap_hwmod_class omap44xx_uart_hwmod_class
= {
3418 .sysc
= &omap44xx_uart_sysc
,
3422 static struct omap_hwmod_irq_info omap44xx_uart1_irqs
[] = {
3423 { .irq
= 72 + OMAP44XX_IRQ_GIC_START
},
3427 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs
[] = {
3428 { .name
= "tx", .dma_req
= 48 + OMAP44XX_DMA_REQ_START
},
3429 { .name
= "rx", .dma_req
= 49 + OMAP44XX_DMA_REQ_START
},
3433 static struct omap_hwmod omap44xx_uart1_hwmod
= {
3435 .class = &omap44xx_uart_hwmod_class
,
3436 .clkdm_name
= "l4_per_clkdm",
3437 .mpu_irqs
= omap44xx_uart1_irqs
,
3438 .sdma_reqs
= omap44xx_uart1_sdma_reqs
,
3439 .main_clk
= "func_48m_fclk",
3442 .clkctrl_offs
= OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET
,
3443 .context_offs
= OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET
,
3444 .modulemode
= MODULEMODE_SWCTRL
,
3450 static struct omap_hwmod_irq_info omap44xx_uart2_irqs
[] = {
3451 { .irq
= 73 + OMAP44XX_IRQ_GIC_START
},
3455 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs
[] = {
3456 { .name
= "tx", .dma_req
= 50 + OMAP44XX_DMA_REQ_START
},
3457 { .name
= "rx", .dma_req
= 51 + OMAP44XX_DMA_REQ_START
},
3461 static struct omap_hwmod omap44xx_uart2_hwmod
= {
3463 .class = &omap44xx_uart_hwmod_class
,
3464 .clkdm_name
= "l4_per_clkdm",
3465 .mpu_irqs
= omap44xx_uart2_irqs
,
3466 .sdma_reqs
= omap44xx_uart2_sdma_reqs
,
3467 .main_clk
= "func_48m_fclk",
3470 .clkctrl_offs
= OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET
,
3471 .context_offs
= OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET
,
3472 .modulemode
= MODULEMODE_SWCTRL
,
3478 static struct omap_hwmod_irq_info omap44xx_uart3_irqs
[] = {
3479 { .irq
= 74 + OMAP44XX_IRQ_GIC_START
},
3483 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs
[] = {
3484 { .name
= "tx", .dma_req
= 52 + OMAP44XX_DMA_REQ_START
},
3485 { .name
= "rx", .dma_req
= 53 + OMAP44XX_DMA_REQ_START
},
3489 static struct omap_hwmod omap44xx_uart3_hwmod
= {
3491 .class = &omap44xx_uart_hwmod_class
,
3492 .clkdm_name
= "l4_per_clkdm",
3493 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
3494 .mpu_irqs
= omap44xx_uart3_irqs
,
3495 .sdma_reqs
= omap44xx_uart3_sdma_reqs
,
3496 .main_clk
= "func_48m_fclk",
3499 .clkctrl_offs
= OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET
,
3500 .context_offs
= OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET
,
3501 .modulemode
= MODULEMODE_SWCTRL
,
3507 static struct omap_hwmod_irq_info omap44xx_uart4_irqs
[] = {
3508 { .irq
= 70 + OMAP44XX_IRQ_GIC_START
},
3512 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs
[] = {
3513 { .name
= "tx", .dma_req
= 54 + OMAP44XX_DMA_REQ_START
},
3514 { .name
= "rx", .dma_req
= 55 + OMAP44XX_DMA_REQ_START
},
3518 static struct omap_hwmod omap44xx_uart4_hwmod
= {
3520 .class = &omap44xx_uart_hwmod_class
,
3521 .clkdm_name
= "l4_per_clkdm",
3522 .mpu_irqs
= omap44xx_uart4_irqs
,
3523 .sdma_reqs
= omap44xx_uart4_sdma_reqs
,
3524 .main_clk
= "func_48m_fclk",
3527 .clkctrl_offs
= OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET
,
3528 .context_offs
= OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET
,
3529 .modulemode
= MODULEMODE_SWCTRL
,
3535 * 'usb_host_fs' class
3536 * full-speed usb host controller
3539 /* The IP is not compliant to type1 / type2 scheme */
3540 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs
= {
3546 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc
= {
3548 .sysc_offs
= 0x0210,
3549 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
|
3550 SYSC_HAS_SOFTRESET
),
3551 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3553 .sysc_fields
= &omap_hwmod_sysc_type_usb_host_fs
,
3556 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class
= {
3557 .name
= "usb_host_fs",
3558 .sysc
= &omap44xx_usb_host_fs_sysc
,
3562 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs
[] = {
3563 { .name
= "std", .irq
= 89 + OMAP44XX_IRQ_GIC_START
},
3564 { .name
= "smi", .irq
= 90 + OMAP44XX_IRQ_GIC_START
},
3568 static struct omap_hwmod omap44xx_usb_host_fs_hwmod
= {
3569 .name
= "usb_host_fs",
3570 .class = &omap44xx_usb_host_fs_hwmod_class
,
3571 .clkdm_name
= "l3_init_clkdm",
3572 .mpu_irqs
= omap44xx_usb_host_fs_irqs
,
3573 .main_clk
= "usb_host_fs_fck",
3576 .clkctrl_offs
= OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET
,
3577 .context_offs
= OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET
,
3578 .modulemode
= MODULEMODE_SWCTRL
,
3584 * 'usb_host_hs' class
3585 * high-speed multi-port usb host controller
3588 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc
= {
3590 .sysc_offs
= 0x0010,
3591 .syss_offs
= 0x0014,
3592 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
|
3593 SYSC_HAS_SOFTRESET
),
3594 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3595 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
3596 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
3597 .sysc_fields
= &omap_hwmod_sysc_type2
,
3600 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class
= {
3601 .name
= "usb_host_hs",
3602 .sysc
= &omap44xx_usb_host_hs_sysc
,
3606 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs
[] = {
3607 { .name
= "ohci-irq", .irq
= 76 + OMAP44XX_IRQ_GIC_START
},
3608 { .name
= "ehci-irq", .irq
= 77 + OMAP44XX_IRQ_GIC_START
},
3612 static struct omap_hwmod omap44xx_usb_host_hs_hwmod
= {
3613 .name
= "usb_host_hs",
3614 .class = &omap44xx_usb_host_hs_hwmod_class
,
3615 .clkdm_name
= "l3_init_clkdm",
3616 .main_clk
= "usb_host_hs_fck",
3619 .clkctrl_offs
= OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET
,
3620 .context_offs
= OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET
,
3621 .modulemode
= MODULEMODE_SWCTRL
,
3624 .mpu_irqs
= omap44xx_usb_host_hs_irqs
,
3627 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3631 * In the following configuration :
3632 * - USBHOST module is set to smart-idle mode
3633 * - PRCM asserts idle_req to the USBHOST module ( This typically
3634 * happens when the system is going to a low power mode : all ports
3635 * have been suspended, the master part of the USBHOST module has
3636 * entered the standby state, and SW has cut the functional clocks)
3637 * - an USBHOST interrupt occurs before the module is able to answer
3638 * idle_ack, typically a remote wakeup IRQ.
3639 * Then the USB HOST module will enter a deadlock situation where it
3640 * is no more accessible nor functional.
3643 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3647 * Errata: USB host EHCI may stall when entering smart-standby mode
3651 * When the USBHOST module is set to smart-standby mode, and when it is
3652 * ready to enter the standby state (i.e. all ports are suspended and
3653 * all attached devices are in suspend mode), then it can wrongly assert
3654 * the Mstandby signal too early while there are still some residual OCP
3655 * transactions ongoing. If this condition occurs, the internal state
3656 * machine may go to an undefined state and the USB link may be stuck
3657 * upon the next resume.
3660 * Don't use smart standby; use only force standby,
3661 * hence HWMOD_SWSUP_MSTANDBY
3665 * During system boot; If the hwmod framework resets the module
3666 * the module will have smart idle settings; which can lead to deadlock
3667 * (above Errata Id:i660); so, dont reset the module during boot;
3668 * Use HWMOD_INIT_NO_RESET.
3671 .flags
= HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
|
3672 HWMOD_INIT_NO_RESET
,
3676 * 'usb_otg_hs' class
3677 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3680 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc
= {
3682 .sysc_offs
= 0x0404,
3683 .syss_offs
= 0x0408,
3684 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
3685 SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
|
3686 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
3687 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3688 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
3690 .sysc_fields
= &omap_hwmod_sysc_type1
,
3693 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class
= {
3694 .name
= "usb_otg_hs",
3695 .sysc
= &omap44xx_usb_otg_hs_sysc
,
3699 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs
[] = {
3700 { .name
= "mc", .irq
= 92 + OMAP44XX_IRQ_GIC_START
},
3701 { .name
= "dma", .irq
= 93 + OMAP44XX_IRQ_GIC_START
},
3705 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks
[] = {
3706 { .role
= "xclk", .clk
= "usb_otg_hs_xclk" },
3709 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod
= {
3710 .name
= "usb_otg_hs",
3711 .class = &omap44xx_usb_otg_hs_hwmod_class
,
3712 .clkdm_name
= "l3_init_clkdm",
3713 .flags
= HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
,
3714 .mpu_irqs
= omap44xx_usb_otg_hs_irqs
,
3715 .main_clk
= "usb_otg_hs_ick",
3718 .clkctrl_offs
= OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET
,
3719 .context_offs
= OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET
,
3720 .modulemode
= MODULEMODE_HWCTRL
,
3723 .opt_clks
= usb_otg_hs_opt_clks
,
3724 .opt_clks_cnt
= ARRAY_SIZE(usb_otg_hs_opt_clks
),
3728 * 'usb_tll_hs' class
3729 * usb_tll_hs module is the adapter on the usb_host_hs ports
3732 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc
= {
3734 .sysc_offs
= 0x0010,
3735 .syss_offs
= 0x0014,
3736 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
3737 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
3739 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
3740 .sysc_fields
= &omap_hwmod_sysc_type1
,
3743 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class
= {
3744 .name
= "usb_tll_hs",
3745 .sysc
= &omap44xx_usb_tll_hs_sysc
,
3748 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs
[] = {
3749 { .name
= "tll-irq", .irq
= 78 + OMAP44XX_IRQ_GIC_START
},
3753 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod
= {
3754 .name
= "usb_tll_hs",
3755 .class = &omap44xx_usb_tll_hs_hwmod_class
,
3756 .clkdm_name
= "l3_init_clkdm",
3757 .mpu_irqs
= omap44xx_usb_tll_hs_irqs
,
3758 .main_clk
= "usb_tll_hs_ick",
3761 .clkctrl_offs
= OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET
,
3762 .context_offs
= OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET
,
3763 .modulemode
= MODULEMODE_HWCTRL
,
3770 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3771 * overflow condition
3774 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc
= {
3776 .sysc_offs
= 0x0010,
3777 .syss_offs
= 0x0014,
3778 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_SIDLEMODE
|
3779 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
3780 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3782 .sysc_fields
= &omap_hwmod_sysc_type1
,
3785 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class
= {
3787 .sysc
= &omap44xx_wd_timer_sysc
,
3788 .pre_shutdown
= &omap2_wd_timer_disable
,
3789 .reset
= &omap2_wd_timer_reset
,
3793 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs
[] = {
3794 { .irq
= 80 + OMAP44XX_IRQ_GIC_START
},
3798 static struct omap_hwmod omap44xx_wd_timer2_hwmod
= {
3799 .name
= "wd_timer2",
3800 .class = &omap44xx_wd_timer_hwmod_class
,
3801 .clkdm_name
= "l4_wkup_clkdm",
3802 .mpu_irqs
= omap44xx_wd_timer2_irqs
,
3803 .main_clk
= "sys_32k_ck",
3806 .clkctrl_offs
= OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET
,
3807 .context_offs
= OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET
,
3808 .modulemode
= MODULEMODE_SWCTRL
,
3814 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs
[] = {
3815 { .irq
= 36 + OMAP44XX_IRQ_GIC_START
},
3819 static struct omap_hwmod omap44xx_wd_timer3_hwmod
= {
3820 .name
= "wd_timer3",
3821 .class = &omap44xx_wd_timer_hwmod_class
,
3822 .clkdm_name
= "abe_clkdm",
3823 .mpu_irqs
= omap44xx_wd_timer3_irqs
,
3824 .main_clk
= "sys_32k_ck",
3827 .clkctrl_offs
= OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET
,
3828 .context_offs
= OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET
,
3829 .modulemode
= MODULEMODE_SWCTRL
,
3839 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs
[] = {
3841 .pa_start
= 0x4a204000,
3842 .pa_end
= 0x4a2040ff,
3843 .flags
= ADDR_TYPE_RT
3848 /* c2c -> c2c_target_fw */
3849 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw
= {
3850 .master
= &omap44xx_c2c_hwmod
,
3851 .slave
= &omap44xx_c2c_target_fw_hwmod
,
3852 .clk
= "div_core_ck",
3853 .addr
= omap44xx_c2c_target_fw_addrs
,
3854 .user
= OCP_USER_MPU
,
3857 /* l4_cfg -> c2c_target_fw */
3858 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw
= {
3859 .master
= &omap44xx_l4_cfg_hwmod
,
3860 .slave
= &omap44xx_c2c_target_fw_hwmod
,
3862 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3865 /* l3_main_1 -> dmm */
3866 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm
= {
3867 .master
= &omap44xx_l3_main_1_hwmod
,
3868 .slave
= &omap44xx_dmm_hwmod
,
3870 .user
= OCP_USER_SDMA
,
3873 static struct omap_hwmod_addr_space omap44xx_dmm_addrs
[] = {
3875 .pa_start
= 0x4e000000,
3876 .pa_end
= 0x4e0007ff,
3877 .flags
= ADDR_TYPE_RT
3883 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm
= {
3884 .master
= &omap44xx_mpu_hwmod
,
3885 .slave
= &omap44xx_dmm_hwmod
,
3887 .addr
= omap44xx_dmm_addrs
,
3888 .user
= OCP_USER_MPU
,
3891 /* c2c -> emif_fw */
3892 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw
= {
3893 .master
= &omap44xx_c2c_hwmod
,
3894 .slave
= &omap44xx_emif_fw_hwmod
,
3895 .clk
= "div_core_ck",
3896 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3899 /* dmm -> emif_fw */
3900 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw
= {
3901 .master
= &omap44xx_dmm_hwmod
,
3902 .slave
= &omap44xx_emif_fw_hwmod
,
3904 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3907 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs
[] = {
3909 .pa_start
= 0x4a20c000,
3910 .pa_end
= 0x4a20c0ff,
3911 .flags
= ADDR_TYPE_RT
3916 /* l4_cfg -> emif_fw */
3917 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw
= {
3918 .master
= &omap44xx_l4_cfg_hwmod
,
3919 .slave
= &omap44xx_emif_fw_hwmod
,
3921 .addr
= omap44xx_emif_fw_addrs
,
3922 .user
= OCP_USER_MPU
,
3925 /* iva -> l3_instr */
3926 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr
= {
3927 .master
= &omap44xx_iva_hwmod
,
3928 .slave
= &omap44xx_l3_instr_hwmod
,
3930 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3933 /* l3_main_3 -> l3_instr */
3934 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr
= {
3935 .master
= &omap44xx_l3_main_3_hwmod
,
3936 .slave
= &omap44xx_l3_instr_hwmod
,
3938 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3941 /* ocp_wp_noc -> l3_instr */
3942 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr
= {
3943 .master
= &omap44xx_ocp_wp_noc_hwmod
,
3944 .slave
= &omap44xx_l3_instr_hwmod
,
3946 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3949 /* dsp -> l3_main_1 */
3950 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1
= {
3951 .master
= &omap44xx_dsp_hwmod
,
3952 .slave
= &omap44xx_l3_main_1_hwmod
,
3954 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3957 /* dss -> l3_main_1 */
3958 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1
= {
3959 .master
= &omap44xx_dss_hwmod
,
3960 .slave
= &omap44xx_l3_main_1_hwmod
,
3962 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3965 /* l3_main_2 -> l3_main_1 */
3966 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1
= {
3967 .master
= &omap44xx_l3_main_2_hwmod
,
3968 .slave
= &omap44xx_l3_main_1_hwmod
,
3970 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3973 /* l4_cfg -> l3_main_1 */
3974 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1
= {
3975 .master
= &omap44xx_l4_cfg_hwmod
,
3976 .slave
= &omap44xx_l3_main_1_hwmod
,
3978 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3981 /* mmc1 -> l3_main_1 */
3982 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1
= {
3983 .master
= &omap44xx_mmc1_hwmod
,
3984 .slave
= &omap44xx_l3_main_1_hwmod
,
3986 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3989 /* mmc2 -> l3_main_1 */
3990 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1
= {
3991 .master
= &omap44xx_mmc2_hwmod
,
3992 .slave
= &omap44xx_l3_main_1_hwmod
,
3994 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3997 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs
[] = {
3999 .pa_start
= 0x44000000,
4000 .pa_end
= 0x44000fff,
4001 .flags
= ADDR_TYPE_RT
4006 /* mpu -> l3_main_1 */
4007 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1
= {
4008 .master
= &omap44xx_mpu_hwmod
,
4009 .slave
= &omap44xx_l3_main_1_hwmod
,
4011 .addr
= omap44xx_l3_main_1_addrs
,
4012 .user
= OCP_USER_MPU
,
4015 /* c2c_target_fw -> l3_main_2 */
4016 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2
= {
4017 .master
= &omap44xx_c2c_target_fw_hwmod
,
4018 .slave
= &omap44xx_l3_main_2_hwmod
,
4020 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4023 /* debugss -> l3_main_2 */
4024 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2
= {
4025 .master
= &omap44xx_debugss_hwmod
,
4026 .slave
= &omap44xx_l3_main_2_hwmod
,
4027 .clk
= "dbgclk_mux_ck",
4028 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4031 /* dma_system -> l3_main_2 */
4032 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2
= {
4033 .master
= &omap44xx_dma_system_hwmod
,
4034 .slave
= &omap44xx_l3_main_2_hwmod
,
4036 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4039 /* fdif -> l3_main_2 */
4040 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2
= {
4041 .master
= &omap44xx_fdif_hwmod
,
4042 .slave
= &omap44xx_l3_main_2_hwmod
,
4044 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4047 /* gpu -> l3_main_2 */
4048 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2
= {
4049 .master
= &omap44xx_gpu_hwmod
,
4050 .slave
= &omap44xx_l3_main_2_hwmod
,
4052 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4055 /* hsi -> l3_main_2 */
4056 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2
= {
4057 .master
= &omap44xx_hsi_hwmod
,
4058 .slave
= &omap44xx_l3_main_2_hwmod
,
4060 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4063 /* ipu -> l3_main_2 */
4064 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2
= {
4065 .master
= &omap44xx_ipu_hwmod
,
4066 .slave
= &omap44xx_l3_main_2_hwmod
,
4068 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4071 /* iss -> l3_main_2 */
4072 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2
= {
4073 .master
= &omap44xx_iss_hwmod
,
4074 .slave
= &omap44xx_l3_main_2_hwmod
,
4076 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4079 /* iva -> l3_main_2 */
4080 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2
= {
4081 .master
= &omap44xx_iva_hwmod
,
4082 .slave
= &omap44xx_l3_main_2_hwmod
,
4084 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4087 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs
[] = {
4089 .pa_start
= 0x44800000,
4090 .pa_end
= 0x44801fff,
4091 .flags
= ADDR_TYPE_RT
4096 /* l3_main_1 -> l3_main_2 */
4097 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2
= {
4098 .master
= &omap44xx_l3_main_1_hwmod
,
4099 .slave
= &omap44xx_l3_main_2_hwmod
,
4101 .addr
= omap44xx_l3_main_2_addrs
,
4102 .user
= OCP_USER_MPU
,
4105 /* l4_cfg -> l3_main_2 */
4106 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2
= {
4107 .master
= &omap44xx_l4_cfg_hwmod
,
4108 .slave
= &omap44xx_l3_main_2_hwmod
,
4110 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4113 /* usb_host_fs -> l3_main_2 */
4114 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2
= {
4115 .master
= &omap44xx_usb_host_fs_hwmod
,
4116 .slave
= &omap44xx_l3_main_2_hwmod
,
4118 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4121 /* usb_host_hs -> l3_main_2 */
4122 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2
= {
4123 .master
= &omap44xx_usb_host_hs_hwmod
,
4124 .slave
= &omap44xx_l3_main_2_hwmod
,
4126 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4129 /* usb_otg_hs -> l3_main_2 */
4130 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2
= {
4131 .master
= &omap44xx_usb_otg_hs_hwmod
,
4132 .slave
= &omap44xx_l3_main_2_hwmod
,
4134 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4137 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs
[] = {
4139 .pa_start
= 0x45000000,
4140 .pa_end
= 0x45000fff,
4141 .flags
= ADDR_TYPE_RT
4146 /* l3_main_1 -> l3_main_3 */
4147 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3
= {
4148 .master
= &omap44xx_l3_main_1_hwmod
,
4149 .slave
= &omap44xx_l3_main_3_hwmod
,
4151 .addr
= omap44xx_l3_main_3_addrs
,
4152 .user
= OCP_USER_MPU
,
4155 /* l3_main_2 -> l3_main_3 */
4156 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3
= {
4157 .master
= &omap44xx_l3_main_2_hwmod
,
4158 .slave
= &omap44xx_l3_main_3_hwmod
,
4160 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4163 /* l4_cfg -> l3_main_3 */
4164 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3
= {
4165 .master
= &omap44xx_l4_cfg_hwmod
,
4166 .slave
= &omap44xx_l3_main_3_hwmod
,
4168 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4171 /* aess -> l4_abe */
4172 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe
= {
4173 .master
= &omap44xx_aess_hwmod
,
4174 .slave
= &omap44xx_l4_abe_hwmod
,
4175 .clk
= "ocp_abe_iclk",
4176 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4180 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe
= {
4181 .master
= &omap44xx_dsp_hwmod
,
4182 .slave
= &omap44xx_l4_abe_hwmod
,
4183 .clk
= "ocp_abe_iclk",
4184 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4187 /* l3_main_1 -> l4_abe */
4188 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe
= {
4189 .master
= &omap44xx_l3_main_1_hwmod
,
4190 .slave
= &omap44xx_l4_abe_hwmod
,
4192 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4196 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe
= {
4197 .master
= &omap44xx_mpu_hwmod
,
4198 .slave
= &omap44xx_l4_abe_hwmod
,
4199 .clk
= "ocp_abe_iclk",
4200 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4203 /* l3_main_1 -> l4_cfg */
4204 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg
= {
4205 .master
= &omap44xx_l3_main_1_hwmod
,
4206 .slave
= &omap44xx_l4_cfg_hwmod
,
4208 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4211 /* l3_main_2 -> l4_per */
4212 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per
= {
4213 .master
= &omap44xx_l3_main_2_hwmod
,
4214 .slave
= &omap44xx_l4_per_hwmod
,
4216 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4219 /* l4_cfg -> l4_wkup */
4220 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup
= {
4221 .master
= &omap44xx_l4_cfg_hwmod
,
4222 .slave
= &omap44xx_l4_wkup_hwmod
,
4224 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4227 /* mpu -> mpu_private */
4228 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private
= {
4229 .master
= &omap44xx_mpu_hwmod
,
4230 .slave
= &omap44xx_mpu_private_hwmod
,
4232 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4235 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs
[] = {
4237 .pa_start
= 0x4a102000,
4238 .pa_end
= 0x4a10207f,
4239 .flags
= ADDR_TYPE_RT
4244 /* l4_cfg -> ocp_wp_noc */
4245 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc
= {
4246 .master
= &omap44xx_l4_cfg_hwmod
,
4247 .slave
= &omap44xx_ocp_wp_noc_hwmod
,
4249 .addr
= omap44xx_ocp_wp_noc_addrs
,
4250 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4253 static struct omap_hwmod_addr_space omap44xx_aess_addrs
[] = {
4256 .pa_start
= 0x40180000,
4257 .pa_end
= 0x4018ffff
4261 .pa_start
= 0x401a0000,
4262 .pa_end
= 0x401a1fff
4266 .pa_start
= 0x401c0000,
4267 .pa_end
= 0x401c5fff
4271 .pa_start
= 0x401e0000,
4272 .pa_end
= 0x401e1fff
4276 .pa_start
= 0x401f1000,
4277 .pa_end
= 0x401f13ff,
4278 .flags
= ADDR_TYPE_RT
4283 /* l4_abe -> aess */
4284 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess
= {
4285 .master
= &omap44xx_l4_abe_hwmod
,
4286 .slave
= &omap44xx_aess_hwmod
,
4287 .clk
= "ocp_abe_iclk",
4288 .addr
= omap44xx_aess_addrs
,
4289 .user
= OCP_USER_MPU
,
4292 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs
[] = {
4295 .pa_start
= 0x49080000,
4296 .pa_end
= 0x4908ffff
4300 .pa_start
= 0x490a0000,
4301 .pa_end
= 0x490a1fff
4305 .pa_start
= 0x490c0000,
4306 .pa_end
= 0x490c5fff
4310 .pa_start
= 0x490e0000,
4311 .pa_end
= 0x490e1fff
4315 .pa_start
= 0x490f1000,
4316 .pa_end
= 0x490f13ff,
4317 .flags
= ADDR_TYPE_RT
4322 /* l4_abe -> aess (dma) */
4323 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma
= {
4324 .master
= &omap44xx_l4_abe_hwmod
,
4325 .slave
= &omap44xx_aess_hwmod
,
4326 .clk
= "ocp_abe_iclk",
4327 .addr
= omap44xx_aess_dma_addrs
,
4328 .user
= OCP_USER_SDMA
,
4331 /* l3_main_2 -> c2c */
4332 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c
= {
4333 .master
= &omap44xx_l3_main_2_hwmod
,
4334 .slave
= &omap44xx_c2c_hwmod
,
4336 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4339 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs
[] = {
4341 .pa_start
= 0x4a304000,
4342 .pa_end
= 0x4a30401f,
4343 .flags
= ADDR_TYPE_RT
4348 /* l4_wkup -> counter_32k */
4349 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k
= {
4350 .master
= &omap44xx_l4_wkup_hwmod
,
4351 .slave
= &omap44xx_counter_32k_hwmod
,
4352 .clk
= "l4_wkup_clk_mux_ck",
4353 .addr
= omap44xx_counter_32k_addrs
,
4354 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4357 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs
[] = {
4359 .pa_start
= 0x4a002000,
4360 .pa_end
= 0x4a0027ff,
4361 .flags
= ADDR_TYPE_RT
4366 /* l4_cfg -> ctrl_module_core */
4367 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core
= {
4368 .master
= &omap44xx_l4_cfg_hwmod
,
4369 .slave
= &omap44xx_ctrl_module_core_hwmod
,
4371 .addr
= omap44xx_ctrl_module_core_addrs
,
4372 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4375 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs
[] = {
4377 .pa_start
= 0x4a100000,
4378 .pa_end
= 0x4a1007ff,
4379 .flags
= ADDR_TYPE_RT
4384 /* l4_cfg -> ctrl_module_pad_core */
4385 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core
= {
4386 .master
= &omap44xx_l4_cfg_hwmod
,
4387 .slave
= &omap44xx_ctrl_module_pad_core_hwmod
,
4389 .addr
= omap44xx_ctrl_module_pad_core_addrs
,
4390 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4393 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs
[] = {
4395 .pa_start
= 0x4a30c000,
4396 .pa_end
= 0x4a30c7ff,
4397 .flags
= ADDR_TYPE_RT
4402 /* l4_wkup -> ctrl_module_wkup */
4403 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup
= {
4404 .master
= &omap44xx_l4_wkup_hwmod
,
4405 .slave
= &omap44xx_ctrl_module_wkup_hwmod
,
4406 .clk
= "l4_wkup_clk_mux_ck",
4407 .addr
= omap44xx_ctrl_module_wkup_addrs
,
4408 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4411 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs
[] = {
4413 .pa_start
= 0x4a31e000,
4414 .pa_end
= 0x4a31e7ff,
4415 .flags
= ADDR_TYPE_RT
4420 /* l4_wkup -> ctrl_module_pad_wkup */
4421 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup
= {
4422 .master
= &omap44xx_l4_wkup_hwmod
,
4423 .slave
= &omap44xx_ctrl_module_pad_wkup_hwmod
,
4424 .clk
= "l4_wkup_clk_mux_ck",
4425 .addr
= omap44xx_ctrl_module_pad_wkup_addrs
,
4426 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4429 static struct omap_hwmod_addr_space omap44xx_debugss_addrs
[] = {
4431 .pa_start
= 0x54160000,
4432 .pa_end
= 0x54167fff,
4433 .flags
= ADDR_TYPE_RT
4438 /* l3_instr -> debugss */
4439 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss
= {
4440 .master
= &omap44xx_l3_instr_hwmod
,
4441 .slave
= &omap44xx_debugss_hwmod
,
4443 .addr
= omap44xx_debugss_addrs
,
4444 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4447 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs
[] = {
4449 .pa_start
= 0x4a056000,
4450 .pa_end
= 0x4a056fff,
4451 .flags
= ADDR_TYPE_RT
4456 /* l4_cfg -> dma_system */
4457 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system
= {
4458 .master
= &omap44xx_l4_cfg_hwmod
,
4459 .slave
= &omap44xx_dma_system_hwmod
,
4461 .addr
= omap44xx_dma_system_addrs
,
4462 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4465 static struct omap_hwmod_addr_space omap44xx_dmic_addrs
[] = {
4468 .pa_start
= 0x4012e000,
4469 .pa_end
= 0x4012e07f,
4470 .flags
= ADDR_TYPE_RT
4475 /* l4_abe -> dmic */
4476 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic
= {
4477 .master
= &omap44xx_l4_abe_hwmod
,
4478 .slave
= &omap44xx_dmic_hwmod
,
4479 .clk
= "ocp_abe_iclk",
4480 .addr
= omap44xx_dmic_addrs
,
4481 .user
= OCP_USER_MPU
,
4484 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs
[] = {
4487 .pa_start
= 0x4902e000,
4488 .pa_end
= 0x4902e07f,
4489 .flags
= ADDR_TYPE_RT
4494 /* l4_abe -> dmic (dma) */
4495 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma
= {
4496 .master
= &omap44xx_l4_abe_hwmod
,
4497 .slave
= &omap44xx_dmic_hwmod
,
4498 .clk
= "ocp_abe_iclk",
4499 .addr
= omap44xx_dmic_dma_addrs
,
4500 .user
= OCP_USER_SDMA
,
4504 static struct omap_hwmod_ocp_if omap44xx_dsp__iva
= {
4505 .master
= &omap44xx_dsp_hwmod
,
4506 .slave
= &omap44xx_iva_hwmod
,
4507 .clk
= "dpll_iva_m5x2_ck",
4508 .user
= OCP_USER_DSP
,
4512 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if
= {
4513 .master
= &omap44xx_dsp_hwmod
,
4514 .slave
= &omap44xx_sl2if_hwmod
,
4515 .clk
= "dpll_iva_m5x2_ck",
4516 .user
= OCP_USER_DSP
,
4520 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp
= {
4521 .master
= &omap44xx_l4_cfg_hwmod
,
4522 .slave
= &omap44xx_dsp_hwmod
,
4524 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4527 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs
[] = {
4529 .pa_start
= 0x58000000,
4530 .pa_end
= 0x5800007f,
4531 .flags
= ADDR_TYPE_RT
4536 /* l3_main_2 -> dss */
4537 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss
= {
4538 .master
= &omap44xx_l3_main_2_hwmod
,
4539 .slave
= &omap44xx_dss_hwmod
,
4541 .addr
= omap44xx_dss_dma_addrs
,
4542 .user
= OCP_USER_SDMA
,
4545 static struct omap_hwmod_addr_space omap44xx_dss_addrs
[] = {
4547 .pa_start
= 0x48040000,
4548 .pa_end
= 0x4804007f,
4549 .flags
= ADDR_TYPE_RT
4555 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss
= {
4556 .master
= &omap44xx_l4_per_hwmod
,
4557 .slave
= &omap44xx_dss_hwmod
,
4559 .addr
= omap44xx_dss_addrs
,
4560 .user
= OCP_USER_MPU
,
4563 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs
[] = {
4565 .pa_start
= 0x58001000,
4566 .pa_end
= 0x58001fff,
4567 .flags
= ADDR_TYPE_RT
4572 /* l3_main_2 -> dss_dispc */
4573 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc
= {
4574 .master
= &omap44xx_l3_main_2_hwmod
,
4575 .slave
= &omap44xx_dss_dispc_hwmod
,
4577 .addr
= omap44xx_dss_dispc_dma_addrs
,
4578 .user
= OCP_USER_SDMA
,
4581 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs
[] = {
4583 .pa_start
= 0x48041000,
4584 .pa_end
= 0x48041fff,
4585 .flags
= ADDR_TYPE_RT
4590 /* l4_per -> dss_dispc */
4591 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc
= {
4592 .master
= &omap44xx_l4_per_hwmod
,
4593 .slave
= &omap44xx_dss_dispc_hwmod
,
4595 .addr
= omap44xx_dss_dispc_addrs
,
4596 .user
= OCP_USER_MPU
,
4599 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs
[] = {
4601 .pa_start
= 0x58004000,
4602 .pa_end
= 0x580041ff,
4603 .flags
= ADDR_TYPE_RT
4608 /* l3_main_2 -> dss_dsi1 */
4609 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1
= {
4610 .master
= &omap44xx_l3_main_2_hwmod
,
4611 .slave
= &omap44xx_dss_dsi1_hwmod
,
4613 .addr
= omap44xx_dss_dsi1_dma_addrs
,
4614 .user
= OCP_USER_SDMA
,
4617 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs
[] = {
4619 .pa_start
= 0x48044000,
4620 .pa_end
= 0x480441ff,
4621 .flags
= ADDR_TYPE_RT
4626 /* l4_per -> dss_dsi1 */
4627 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1
= {
4628 .master
= &omap44xx_l4_per_hwmod
,
4629 .slave
= &omap44xx_dss_dsi1_hwmod
,
4631 .addr
= omap44xx_dss_dsi1_addrs
,
4632 .user
= OCP_USER_MPU
,
4635 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs
[] = {
4637 .pa_start
= 0x58005000,
4638 .pa_end
= 0x580051ff,
4639 .flags
= ADDR_TYPE_RT
4644 /* l3_main_2 -> dss_dsi2 */
4645 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2
= {
4646 .master
= &omap44xx_l3_main_2_hwmod
,
4647 .slave
= &omap44xx_dss_dsi2_hwmod
,
4649 .addr
= omap44xx_dss_dsi2_dma_addrs
,
4650 .user
= OCP_USER_SDMA
,
4653 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs
[] = {
4655 .pa_start
= 0x48045000,
4656 .pa_end
= 0x480451ff,
4657 .flags
= ADDR_TYPE_RT
4662 /* l4_per -> dss_dsi2 */
4663 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2
= {
4664 .master
= &omap44xx_l4_per_hwmod
,
4665 .slave
= &omap44xx_dss_dsi2_hwmod
,
4667 .addr
= omap44xx_dss_dsi2_addrs
,
4668 .user
= OCP_USER_MPU
,
4671 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs
[] = {
4673 .pa_start
= 0x58006000,
4674 .pa_end
= 0x58006fff,
4675 .flags
= ADDR_TYPE_RT
4680 /* l3_main_2 -> dss_hdmi */
4681 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi
= {
4682 .master
= &omap44xx_l3_main_2_hwmod
,
4683 .slave
= &omap44xx_dss_hdmi_hwmod
,
4685 .addr
= omap44xx_dss_hdmi_dma_addrs
,
4686 .user
= OCP_USER_SDMA
,
4689 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs
[] = {
4691 .pa_start
= 0x48046000,
4692 .pa_end
= 0x48046fff,
4693 .flags
= ADDR_TYPE_RT
4698 /* l4_per -> dss_hdmi */
4699 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi
= {
4700 .master
= &omap44xx_l4_per_hwmod
,
4701 .slave
= &omap44xx_dss_hdmi_hwmod
,
4703 .addr
= omap44xx_dss_hdmi_addrs
,
4704 .user
= OCP_USER_MPU
,
4707 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs
[] = {
4709 .pa_start
= 0x58002000,
4710 .pa_end
= 0x580020ff,
4711 .flags
= ADDR_TYPE_RT
4716 /* l3_main_2 -> dss_rfbi */
4717 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi
= {
4718 .master
= &omap44xx_l3_main_2_hwmod
,
4719 .slave
= &omap44xx_dss_rfbi_hwmod
,
4721 .addr
= omap44xx_dss_rfbi_dma_addrs
,
4722 .user
= OCP_USER_SDMA
,
4725 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs
[] = {
4727 .pa_start
= 0x48042000,
4728 .pa_end
= 0x480420ff,
4729 .flags
= ADDR_TYPE_RT
4734 /* l4_per -> dss_rfbi */
4735 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi
= {
4736 .master
= &omap44xx_l4_per_hwmod
,
4737 .slave
= &omap44xx_dss_rfbi_hwmod
,
4739 .addr
= omap44xx_dss_rfbi_addrs
,
4740 .user
= OCP_USER_MPU
,
4743 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs
[] = {
4745 .pa_start
= 0x58003000,
4746 .pa_end
= 0x580030ff,
4747 .flags
= ADDR_TYPE_RT
4752 /* l3_main_2 -> dss_venc */
4753 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc
= {
4754 .master
= &omap44xx_l3_main_2_hwmod
,
4755 .slave
= &omap44xx_dss_venc_hwmod
,
4757 .addr
= omap44xx_dss_venc_dma_addrs
,
4758 .user
= OCP_USER_SDMA
,
4761 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs
[] = {
4763 .pa_start
= 0x48043000,
4764 .pa_end
= 0x480430ff,
4765 .flags
= ADDR_TYPE_RT
4770 /* l4_per -> dss_venc */
4771 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc
= {
4772 .master
= &omap44xx_l4_per_hwmod
,
4773 .slave
= &omap44xx_dss_venc_hwmod
,
4775 .addr
= omap44xx_dss_venc_addrs
,
4776 .user
= OCP_USER_MPU
,
4779 static struct omap_hwmod_addr_space omap44xx_elm_addrs
[] = {
4781 .pa_start
= 0x48078000,
4782 .pa_end
= 0x48078fff,
4783 .flags
= ADDR_TYPE_RT
4789 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm
= {
4790 .master
= &omap44xx_l4_per_hwmod
,
4791 .slave
= &omap44xx_elm_hwmod
,
4793 .addr
= omap44xx_elm_addrs
,
4794 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4797 static struct omap_hwmod_addr_space omap44xx_emif1_addrs
[] = {
4799 .pa_start
= 0x4c000000,
4800 .pa_end
= 0x4c0000ff,
4801 .flags
= ADDR_TYPE_RT
4806 /* emif_fw -> emif1 */
4807 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1
= {
4808 .master
= &omap44xx_emif_fw_hwmod
,
4809 .slave
= &omap44xx_emif1_hwmod
,
4811 .addr
= omap44xx_emif1_addrs
,
4812 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4815 static struct omap_hwmod_addr_space omap44xx_emif2_addrs
[] = {
4817 .pa_start
= 0x4d000000,
4818 .pa_end
= 0x4d0000ff,
4819 .flags
= ADDR_TYPE_RT
4824 /* emif_fw -> emif2 */
4825 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2
= {
4826 .master
= &omap44xx_emif_fw_hwmod
,
4827 .slave
= &omap44xx_emif2_hwmod
,
4829 .addr
= omap44xx_emif2_addrs
,
4830 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4833 static struct omap_hwmod_addr_space omap44xx_fdif_addrs
[] = {
4835 .pa_start
= 0x4a10a000,
4836 .pa_end
= 0x4a10a1ff,
4837 .flags
= ADDR_TYPE_RT
4842 /* l4_cfg -> fdif */
4843 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif
= {
4844 .master
= &omap44xx_l4_cfg_hwmod
,
4845 .slave
= &omap44xx_fdif_hwmod
,
4847 .addr
= omap44xx_fdif_addrs
,
4848 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4851 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs
[] = {
4853 .pa_start
= 0x4a310000,
4854 .pa_end
= 0x4a3101ff,
4855 .flags
= ADDR_TYPE_RT
4860 /* l4_wkup -> gpio1 */
4861 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1
= {
4862 .master
= &omap44xx_l4_wkup_hwmod
,
4863 .slave
= &omap44xx_gpio1_hwmod
,
4864 .clk
= "l4_wkup_clk_mux_ck",
4865 .addr
= omap44xx_gpio1_addrs
,
4866 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4869 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs
[] = {
4871 .pa_start
= 0x48055000,
4872 .pa_end
= 0x480551ff,
4873 .flags
= ADDR_TYPE_RT
4878 /* l4_per -> gpio2 */
4879 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2
= {
4880 .master
= &omap44xx_l4_per_hwmod
,
4881 .slave
= &omap44xx_gpio2_hwmod
,
4883 .addr
= omap44xx_gpio2_addrs
,
4884 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4887 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs
[] = {
4889 .pa_start
= 0x48057000,
4890 .pa_end
= 0x480571ff,
4891 .flags
= ADDR_TYPE_RT
4896 /* l4_per -> gpio3 */
4897 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3
= {
4898 .master
= &omap44xx_l4_per_hwmod
,
4899 .slave
= &omap44xx_gpio3_hwmod
,
4901 .addr
= omap44xx_gpio3_addrs
,
4902 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4905 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs
[] = {
4907 .pa_start
= 0x48059000,
4908 .pa_end
= 0x480591ff,
4909 .flags
= ADDR_TYPE_RT
4914 /* l4_per -> gpio4 */
4915 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4
= {
4916 .master
= &omap44xx_l4_per_hwmod
,
4917 .slave
= &omap44xx_gpio4_hwmod
,
4919 .addr
= omap44xx_gpio4_addrs
,
4920 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4923 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs
[] = {
4925 .pa_start
= 0x4805b000,
4926 .pa_end
= 0x4805b1ff,
4927 .flags
= ADDR_TYPE_RT
4932 /* l4_per -> gpio5 */
4933 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5
= {
4934 .master
= &omap44xx_l4_per_hwmod
,
4935 .slave
= &omap44xx_gpio5_hwmod
,
4937 .addr
= omap44xx_gpio5_addrs
,
4938 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4941 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs
[] = {
4943 .pa_start
= 0x4805d000,
4944 .pa_end
= 0x4805d1ff,
4945 .flags
= ADDR_TYPE_RT
4950 /* l4_per -> gpio6 */
4951 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6
= {
4952 .master
= &omap44xx_l4_per_hwmod
,
4953 .slave
= &omap44xx_gpio6_hwmod
,
4955 .addr
= omap44xx_gpio6_addrs
,
4956 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4959 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs
[] = {
4961 .pa_start
= 0x50000000,
4962 .pa_end
= 0x500003ff,
4963 .flags
= ADDR_TYPE_RT
4968 /* l3_main_2 -> gpmc */
4969 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc
= {
4970 .master
= &omap44xx_l3_main_2_hwmod
,
4971 .slave
= &omap44xx_gpmc_hwmod
,
4973 .addr
= omap44xx_gpmc_addrs
,
4974 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4977 static struct omap_hwmod_addr_space omap44xx_gpu_addrs
[] = {
4979 .pa_start
= 0x56000000,
4980 .pa_end
= 0x5600ffff,
4981 .flags
= ADDR_TYPE_RT
4986 /* l3_main_2 -> gpu */
4987 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu
= {
4988 .master
= &omap44xx_l3_main_2_hwmod
,
4989 .slave
= &omap44xx_gpu_hwmod
,
4991 .addr
= omap44xx_gpu_addrs
,
4992 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4995 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs
[] = {
4997 .pa_start
= 0x480b2000,
4998 .pa_end
= 0x480b201f,
4999 .flags
= ADDR_TYPE_RT
5004 /* l4_per -> hdq1w */
5005 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w
= {
5006 .master
= &omap44xx_l4_per_hwmod
,
5007 .slave
= &omap44xx_hdq1w_hwmod
,
5009 .addr
= omap44xx_hdq1w_addrs
,
5010 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5013 static struct omap_hwmod_addr_space omap44xx_hsi_addrs
[] = {
5015 .pa_start
= 0x4a058000,
5016 .pa_end
= 0x4a05bfff,
5017 .flags
= ADDR_TYPE_RT
5023 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi
= {
5024 .master
= &omap44xx_l4_cfg_hwmod
,
5025 .slave
= &omap44xx_hsi_hwmod
,
5027 .addr
= omap44xx_hsi_addrs
,
5028 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5031 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs
[] = {
5033 .pa_start
= 0x48070000,
5034 .pa_end
= 0x480700ff,
5035 .flags
= ADDR_TYPE_RT
5040 /* l4_per -> i2c1 */
5041 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1
= {
5042 .master
= &omap44xx_l4_per_hwmod
,
5043 .slave
= &omap44xx_i2c1_hwmod
,
5045 .addr
= omap44xx_i2c1_addrs
,
5046 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5049 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs
[] = {
5051 .pa_start
= 0x48072000,
5052 .pa_end
= 0x480720ff,
5053 .flags
= ADDR_TYPE_RT
5058 /* l4_per -> i2c2 */
5059 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2
= {
5060 .master
= &omap44xx_l4_per_hwmod
,
5061 .slave
= &omap44xx_i2c2_hwmod
,
5063 .addr
= omap44xx_i2c2_addrs
,
5064 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5067 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs
[] = {
5069 .pa_start
= 0x48060000,
5070 .pa_end
= 0x480600ff,
5071 .flags
= ADDR_TYPE_RT
5076 /* l4_per -> i2c3 */
5077 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3
= {
5078 .master
= &omap44xx_l4_per_hwmod
,
5079 .slave
= &omap44xx_i2c3_hwmod
,
5081 .addr
= omap44xx_i2c3_addrs
,
5082 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5085 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs
[] = {
5087 .pa_start
= 0x48350000,
5088 .pa_end
= 0x483500ff,
5089 .flags
= ADDR_TYPE_RT
5094 /* l4_per -> i2c4 */
5095 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4
= {
5096 .master
= &omap44xx_l4_per_hwmod
,
5097 .slave
= &omap44xx_i2c4_hwmod
,
5099 .addr
= omap44xx_i2c4_addrs
,
5100 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5103 /* l3_main_2 -> ipu */
5104 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu
= {
5105 .master
= &omap44xx_l3_main_2_hwmod
,
5106 .slave
= &omap44xx_ipu_hwmod
,
5108 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5111 static struct omap_hwmod_addr_space omap44xx_iss_addrs
[] = {
5113 .pa_start
= 0x52000000,
5114 .pa_end
= 0x520000ff,
5115 .flags
= ADDR_TYPE_RT
5120 /* l3_main_2 -> iss */
5121 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss
= {
5122 .master
= &omap44xx_l3_main_2_hwmod
,
5123 .slave
= &omap44xx_iss_hwmod
,
5125 .addr
= omap44xx_iss_addrs
,
5126 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5130 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if
= {
5131 .master
= &omap44xx_iva_hwmod
,
5132 .slave
= &omap44xx_sl2if_hwmod
,
5133 .clk
= "dpll_iva_m5x2_ck",
5134 .user
= OCP_USER_IVA
,
5137 static struct omap_hwmod_addr_space omap44xx_iva_addrs
[] = {
5139 .pa_start
= 0x5a000000,
5140 .pa_end
= 0x5a07ffff,
5141 .flags
= ADDR_TYPE_RT
5146 /* l3_main_2 -> iva */
5147 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva
= {
5148 .master
= &omap44xx_l3_main_2_hwmod
,
5149 .slave
= &omap44xx_iva_hwmod
,
5151 .addr
= omap44xx_iva_addrs
,
5152 .user
= OCP_USER_MPU
,
5155 static struct omap_hwmod_addr_space omap44xx_kbd_addrs
[] = {
5157 .pa_start
= 0x4a31c000,
5158 .pa_end
= 0x4a31c07f,
5159 .flags
= ADDR_TYPE_RT
5164 /* l4_wkup -> kbd */
5165 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd
= {
5166 .master
= &omap44xx_l4_wkup_hwmod
,
5167 .slave
= &omap44xx_kbd_hwmod
,
5168 .clk
= "l4_wkup_clk_mux_ck",
5169 .addr
= omap44xx_kbd_addrs
,
5170 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5173 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs
[] = {
5175 .pa_start
= 0x4a0f4000,
5176 .pa_end
= 0x4a0f41ff,
5177 .flags
= ADDR_TYPE_RT
5182 /* l4_cfg -> mailbox */
5183 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox
= {
5184 .master
= &omap44xx_l4_cfg_hwmod
,
5185 .slave
= &omap44xx_mailbox_hwmod
,
5187 .addr
= omap44xx_mailbox_addrs
,
5188 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5191 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs
[] = {
5193 .pa_start
= 0x40128000,
5194 .pa_end
= 0x401283ff,
5195 .flags
= ADDR_TYPE_RT
5200 /* l4_abe -> mcasp */
5201 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp
= {
5202 .master
= &omap44xx_l4_abe_hwmod
,
5203 .slave
= &omap44xx_mcasp_hwmod
,
5204 .clk
= "ocp_abe_iclk",
5205 .addr
= omap44xx_mcasp_addrs
,
5206 .user
= OCP_USER_MPU
,
5209 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs
[] = {
5211 .pa_start
= 0x49028000,
5212 .pa_end
= 0x490283ff,
5213 .flags
= ADDR_TYPE_RT
5218 /* l4_abe -> mcasp (dma) */
5219 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma
= {
5220 .master
= &omap44xx_l4_abe_hwmod
,
5221 .slave
= &omap44xx_mcasp_hwmod
,
5222 .clk
= "ocp_abe_iclk",
5223 .addr
= omap44xx_mcasp_dma_addrs
,
5224 .user
= OCP_USER_SDMA
,
5227 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs
[] = {
5230 .pa_start
= 0x40122000,
5231 .pa_end
= 0x401220ff,
5232 .flags
= ADDR_TYPE_RT
5237 /* l4_abe -> mcbsp1 */
5238 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1
= {
5239 .master
= &omap44xx_l4_abe_hwmod
,
5240 .slave
= &omap44xx_mcbsp1_hwmod
,
5241 .clk
= "ocp_abe_iclk",
5242 .addr
= omap44xx_mcbsp1_addrs
,
5243 .user
= OCP_USER_MPU
,
5246 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs
[] = {
5249 .pa_start
= 0x49022000,
5250 .pa_end
= 0x490220ff,
5251 .flags
= ADDR_TYPE_RT
5256 /* l4_abe -> mcbsp1 (dma) */
5257 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma
= {
5258 .master
= &omap44xx_l4_abe_hwmod
,
5259 .slave
= &omap44xx_mcbsp1_hwmod
,
5260 .clk
= "ocp_abe_iclk",
5261 .addr
= omap44xx_mcbsp1_dma_addrs
,
5262 .user
= OCP_USER_SDMA
,
5265 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs
[] = {
5268 .pa_start
= 0x40124000,
5269 .pa_end
= 0x401240ff,
5270 .flags
= ADDR_TYPE_RT
5275 /* l4_abe -> mcbsp2 */
5276 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2
= {
5277 .master
= &omap44xx_l4_abe_hwmod
,
5278 .slave
= &omap44xx_mcbsp2_hwmod
,
5279 .clk
= "ocp_abe_iclk",
5280 .addr
= omap44xx_mcbsp2_addrs
,
5281 .user
= OCP_USER_MPU
,
5284 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs
[] = {
5287 .pa_start
= 0x49024000,
5288 .pa_end
= 0x490240ff,
5289 .flags
= ADDR_TYPE_RT
5294 /* l4_abe -> mcbsp2 (dma) */
5295 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma
= {
5296 .master
= &omap44xx_l4_abe_hwmod
,
5297 .slave
= &omap44xx_mcbsp2_hwmod
,
5298 .clk
= "ocp_abe_iclk",
5299 .addr
= omap44xx_mcbsp2_dma_addrs
,
5300 .user
= OCP_USER_SDMA
,
5303 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs
[] = {
5306 .pa_start
= 0x40126000,
5307 .pa_end
= 0x401260ff,
5308 .flags
= ADDR_TYPE_RT
5313 /* l4_abe -> mcbsp3 */
5314 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3
= {
5315 .master
= &omap44xx_l4_abe_hwmod
,
5316 .slave
= &omap44xx_mcbsp3_hwmod
,
5317 .clk
= "ocp_abe_iclk",
5318 .addr
= omap44xx_mcbsp3_addrs
,
5319 .user
= OCP_USER_MPU
,
5322 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs
[] = {
5325 .pa_start
= 0x49026000,
5326 .pa_end
= 0x490260ff,
5327 .flags
= ADDR_TYPE_RT
5332 /* l4_abe -> mcbsp3 (dma) */
5333 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma
= {
5334 .master
= &omap44xx_l4_abe_hwmod
,
5335 .slave
= &omap44xx_mcbsp3_hwmod
,
5336 .clk
= "ocp_abe_iclk",
5337 .addr
= omap44xx_mcbsp3_dma_addrs
,
5338 .user
= OCP_USER_SDMA
,
5341 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs
[] = {
5343 .pa_start
= 0x48096000,
5344 .pa_end
= 0x480960ff,
5345 .flags
= ADDR_TYPE_RT
5350 /* l4_per -> mcbsp4 */
5351 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4
= {
5352 .master
= &omap44xx_l4_per_hwmod
,
5353 .slave
= &omap44xx_mcbsp4_hwmod
,
5355 .addr
= omap44xx_mcbsp4_addrs
,
5356 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5359 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs
[] = {
5362 .pa_start
= 0x40132000,
5363 .pa_end
= 0x4013207f,
5364 .flags
= ADDR_TYPE_RT
5369 /* l4_abe -> mcpdm */
5370 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm
= {
5371 .master
= &omap44xx_l4_abe_hwmod
,
5372 .slave
= &omap44xx_mcpdm_hwmod
,
5373 .clk
= "ocp_abe_iclk",
5374 .addr
= omap44xx_mcpdm_addrs
,
5375 .user
= OCP_USER_MPU
,
5378 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs
[] = {
5381 .pa_start
= 0x49032000,
5382 .pa_end
= 0x4903207f,
5383 .flags
= ADDR_TYPE_RT
5388 /* l4_abe -> mcpdm (dma) */
5389 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma
= {
5390 .master
= &omap44xx_l4_abe_hwmod
,
5391 .slave
= &omap44xx_mcpdm_hwmod
,
5392 .clk
= "ocp_abe_iclk",
5393 .addr
= omap44xx_mcpdm_dma_addrs
,
5394 .user
= OCP_USER_SDMA
,
5397 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs
[] = {
5399 .pa_start
= 0x48098000,
5400 .pa_end
= 0x480981ff,
5401 .flags
= ADDR_TYPE_RT
5406 /* l4_per -> mcspi1 */
5407 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1
= {
5408 .master
= &omap44xx_l4_per_hwmod
,
5409 .slave
= &omap44xx_mcspi1_hwmod
,
5411 .addr
= omap44xx_mcspi1_addrs
,
5412 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5415 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs
[] = {
5417 .pa_start
= 0x4809a000,
5418 .pa_end
= 0x4809a1ff,
5419 .flags
= ADDR_TYPE_RT
5424 /* l4_per -> mcspi2 */
5425 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2
= {
5426 .master
= &omap44xx_l4_per_hwmod
,
5427 .slave
= &omap44xx_mcspi2_hwmod
,
5429 .addr
= omap44xx_mcspi2_addrs
,
5430 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5433 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs
[] = {
5435 .pa_start
= 0x480b8000,
5436 .pa_end
= 0x480b81ff,
5437 .flags
= ADDR_TYPE_RT
5442 /* l4_per -> mcspi3 */
5443 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3
= {
5444 .master
= &omap44xx_l4_per_hwmod
,
5445 .slave
= &omap44xx_mcspi3_hwmod
,
5447 .addr
= omap44xx_mcspi3_addrs
,
5448 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5451 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs
[] = {
5453 .pa_start
= 0x480ba000,
5454 .pa_end
= 0x480ba1ff,
5455 .flags
= ADDR_TYPE_RT
5460 /* l4_per -> mcspi4 */
5461 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4
= {
5462 .master
= &omap44xx_l4_per_hwmod
,
5463 .slave
= &omap44xx_mcspi4_hwmod
,
5465 .addr
= omap44xx_mcspi4_addrs
,
5466 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5469 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs
[] = {
5471 .pa_start
= 0x4809c000,
5472 .pa_end
= 0x4809c3ff,
5473 .flags
= ADDR_TYPE_RT
5478 /* l4_per -> mmc1 */
5479 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1
= {
5480 .master
= &omap44xx_l4_per_hwmod
,
5481 .slave
= &omap44xx_mmc1_hwmod
,
5483 .addr
= omap44xx_mmc1_addrs
,
5484 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5487 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs
[] = {
5489 .pa_start
= 0x480b4000,
5490 .pa_end
= 0x480b43ff,
5491 .flags
= ADDR_TYPE_RT
5496 /* l4_per -> mmc2 */
5497 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2
= {
5498 .master
= &omap44xx_l4_per_hwmod
,
5499 .slave
= &omap44xx_mmc2_hwmod
,
5501 .addr
= omap44xx_mmc2_addrs
,
5502 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5505 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs
[] = {
5507 .pa_start
= 0x480ad000,
5508 .pa_end
= 0x480ad3ff,
5509 .flags
= ADDR_TYPE_RT
5514 /* l4_per -> mmc3 */
5515 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3
= {
5516 .master
= &omap44xx_l4_per_hwmod
,
5517 .slave
= &omap44xx_mmc3_hwmod
,
5519 .addr
= omap44xx_mmc3_addrs
,
5520 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5523 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs
[] = {
5525 .pa_start
= 0x480d1000,
5526 .pa_end
= 0x480d13ff,
5527 .flags
= ADDR_TYPE_RT
5532 /* l4_per -> mmc4 */
5533 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4
= {
5534 .master
= &omap44xx_l4_per_hwmod
,
5535 .slave
= &omap44xx_mmc4_hwmod
,
5537 .addr
= omap44xx_mmc4_addrs
,
5538 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5541 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs
[] = {
5543 .pa_start
= 0x480d5000,
5544 .pa_end
= 0x480d53ff,
5545 .flags
= ADDR_TYPE_RT
5550 /* l4_per -> mmc5 */
5551 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5
= {
5552 .master
= &omap44xx_l4_per_hwmod
,
5553 .slave
= &omap44xx_mmc5_hwmod
,
5555 .addr
= omap44xx_mmc5_addrs
,
5556 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5559 /* l3_main_2 -> ocmc_ram */
5560 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram
= {
5561 .master
= &omap44xx_l3_main_2_hwmod
,
5562 .slave
= &omap44xx_ocmc_ram_hwmod
,
5564 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5567 static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs
[] = {
5569 .pa_start
= 0x4a0ad000,
5570 .pa_end
= 0x4a0ad01f,
5571 .flags
= ADDR_TYPE_RT
5576 /* l4_cfg -> ocp2scp_usb_phy */
5577 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy
= {
5578 .master
= &omap44xx_l4_cfg_hwmod
,
5579 .slave
= &omap44xx_ocp2scp_usb_phy_hwmod
,
5581 .addr
= omap44xx_ocp2scp_usb_phy_addrs
,
5582 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5585 static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs
[] = {
5587 .pa_start
= 0x48243000,
5588 .pa_end
= 0x48243fff,
5589 .flags
= ADDR_TYPE_RT
5594 /* mpu_private -> prcm_mpu */
5595 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu
= {
5596 .master
= &omap44xx_mpu_private_hwmod
,
5597 .slave
= &omap44xx_prcm_mpu_hwmod
,
5599 .addr
= omap44xx_prcm_mpu_addrs
,
5600 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5603 static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs
[] = {
5605 .pa_start
= 0x4a004000,
5606 .pa_end
= 0x4a004fff,
5607 .flags
= ADDR_TYPE_RT
5612 /* l4_wkup -> cm_core_aon */
5613 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon
= {
5614 .master
= &omap44xx_l4_wkup_hwmod
,
5615 .slave
= &omap44xx_cm_core_aon_hwmod
,
5616 .clk
= "l4_wkup_clk_mux_ck",
5617 .addr
= omap44xx_cm_core_aon_addrs
,
5618 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5621 static struct omap_hwmod_addr_space omap44xx_cm_core_addrs
[] = {
5623 .pa_start
= 0x4a008000,
5624 .pa_end
= 0x4a009fff,
5625 .flags
= ADDR_TYPE_RT
5630 /* l4_cfg -> cm_core */
5631 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core
= {
5632 .master
= &omap44xx_l4_cfg_hwmod
,
5633 .slave
= &omap44xx_cm_core_hwmod
,
5635 .addr
= omap44xx_cm_core_addrs
,
5636 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5639 static struct omap_hwmod_addr_space omap44xx_prm_addrs
[] = {
5641 .pa_start
= 0x4a306000,
5642 .pa_end
= 0x4a307fff,
5643 .flags
= ADDR_TYPE_RT
5648 /* l4_wkup -> prm */
5649 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm
= {
5650 .master
= &omap44xx_l4_wkup_hwmod
,
5651 .slave
= &omap44xx_prm_hwmod
,
5652 .clk
= "l4_wkup_clk_mux_ck",
5653 .addr
= omap44xx_prm_addrs
,
5654 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5657 static struct omap_hwmod_addr_space omap44xx_scrm_addrs
[] = {
5659 .pa_start
= 0x4a30a000,
5660 .pa_end
= 0x4a30a7ff,
5661 .flags
= ADDR_TYPE_RT
5666 /* l4_wkup -> scrm */
5667 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm
= {
5668 .master
= &omap44xx_l4_wkup_hwmod
,
5669 .slave
= &omap44xx_scrm_hwmod
,
5670 .clk
= "l4_wkup_clk_mux_ck",
5671 .addr
= omap44xx_scrm_addrs
,
5672 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5675 /* l3_main_2 -> sl2if */
5676 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if
= {
5677 .master
= &omap44xx_l3_main_2_hwmod
,
5678 .slave
= &omap44xx_sl2if_hwmod
,
5680 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5683 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs
[] = {
5685 .pa_start
= 0x4012c000,
5686 .pa_end
= 0x4012c3ff,
5687 .flags
= ADDR_TYPE_RT
5692 /* l4_abe -> slimbus1 */
5693 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1
= {
5694 .master
= &omap44xx_l4_abe_hwmod
,
5695 .slave
= &omap44xx_slimbus1_hwmod
,
5696 .clk
= "ocp_abe_iclk",
5697 .addr
= omap44xx_slimbus1_addrs
,
5698 .user
= OCP_USER_MPU
,
5701 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs
[] = {
5703 .pa_start
= 0x4902c000,
5704 .pa_end
= 0x4902c3ff,
5705 .flags
= ADDR_TYPE_RT
5710 /* l4_abe -> slimbus1 (dma) */
5711 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma
= {
5712 .master
= &omap44xx_l4_abe_hwmod
,
5713 .slave
= &omap44xx_slimbus1_hwmod
,
5714 .clk
= "ocp_abe_iclk",
5715 .addr
= omap44xx_slimbus1_dma_addrs
,
5716 .user
= OCP_USER_SDMA
,
5719 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs
[] = {
5721 .pa_start
= 0x48076000,
5722 .pa_end
= 0x480763ff,
5723 .flags
= ADDR_TYPE_RT
5728 /* l4_per -> slimbus2 */
5729 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2
= {
5730 .master
= &omap44xx_l4_per_hwmod
,
5731 .slave
= &omap44xx_slimbus2_hwmod
,
5733 .addr
= omap44xx_slimbus2_addrs
,
5734 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5737 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs
[] = {
5739 .pa_start
= 0x4a0dd000,
5740 .pa_end
= 0x4a0dd03f,
5741 .flags
= ADDR_TYPE_RT
5746 /* l4_cfg -> smartreflex_core */
5747 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core
= {
5748 .master
= &omap44xx_l4_cfg_hwmod
,
5749 .slave
= &omap44xx_smartreflex_core_hwmod
,
5751 .addr
= omap44xx_smartreflex_core_addrs
,
5752 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5755 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs
[] = {
5757 .pa_start
= 0x4a0db000,
5758 .pa_end
= 0x4a0db03f,
5759 .flags
= ADDR_TYPE_RT
5764 /* l4_cfg -> smartreflex_iva */
5765 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva
= {
5766 .master
= &omap44xx_l4_cfg_hwmod
,
5767 .slave
= &omap44xx_smartreflex_iva_hwmod
,
5769 .addr
= omap44xx_smartreflex_iva_addrs
,
5770 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5773 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs
[] = {
5775 .pa_start
= 0x4a0d9000,
5776 .pa_end
= 0x4a0d903f,
5777 .flags
= ADDR_TYPE_RT
5782 /* l4_cfg -> smartreflex_mpu */
5783 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu
= {
5784 .master
= &omap44xx_l4_cfg_hwmod
,
5785 .slave
= &omap44xx_smartreflex_mpu_hwmod
,
5787 .addr
= omap44xx_smartreflex_mpu_addrs
,
5788 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5791 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs
[] = {
5793 .pa_start
= 0x4a0f6000,
5794 .pa_end
= 0x4a0f6fff,
5795 .flags
= ADDR_TYPE_RT
5800 /* l4_cfg -> spinlock */
5801 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock
= {
5802 .master
= &omap44xx_l4_cfg_hwmod
,
5803 .slave
= &omap44xx_spinlock_hwmod
,
5805 .addr
= omap44xx_spinlock_addrs
,
5806 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5809 static struct omap_hwmod_addr_space omap44xx_timer1_addrs
[] = {
5811 .pa_start
= 0x4a318000,
5812 .pa_end
= 0x4a31807f,
5813 .flags
= ADDR_TYPE_RT
5818 /* l4_wkup -> timer1 */
5819 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1
= {
5820 .master
= &omap44xx_l4_wkup_hwmod
,
5821 .slave
= &omap44xx_timer1_hwmod
,
5822 .clk
= "l4_wkup_clk_mux_ck",
5823 .addr
= omap44xx_timer1_addrs
,
5824 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5827 static struct omap_hwmod_addr_space omap44xx_timer2_addrs
[] = {
5829 .pa_start
= 0x48032000,
5830 .pa_end
= 0x4803207f,
5831 .flags
= ADDR_TYPE_RT
5836 /* l4_per -> timer2 */
5837 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2
= {
5838 .master
= &omap44xx_l4_per_hwmod
,
5839 .slave
= &omap44xx_timer2_hwmod
,
5841 .addr
= omap44xx_timer2_addrs
,
5842 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5845 static struct omap_hwmod_addr_space omap44xx_timer3_addrs
[] = {
5847 .pa_start
= 0x48034000,
5848 .pa_end
= 0x4803407f,
5849 .flags
= ADDR_TYPE_RT
5854 /* l4_per -> timer3 */
5855 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3
= {
5856 .master
= &omap44xx_l4_per_hwmod
,
5857 .slave
= &omap44xx_timer3_hwmod
,
5859 .addr
= omap44xx_timer3_addrs
,
5860 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5863 static struct omap_hwmod_addr_space omap44xx_timer4_addrs
[] = {
5865 .pa_start
= 0x48036000,
5866 .pa_end
= 0x4803607f,
5867 .flags
= ADDR_TYPE_RT
5872 /* l4_per -> timer4 */
5873 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4
= {
5874 .master
= &omap44xx_l4_per_hwmod
,
5875 .slave
= &omap44xx_timer4_hwmod
,
5877 .addr
= omap44xx_timer4_addrs
,
5878 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5881 static struct omap_hwmod_addr_space omap44xx_timer5_addrs
[] = {
5883 .pa_start
= 0x40138000,
5884 .pa_end
= 0x4013807f,
5885 .flags
= ADDR_TYPE_RT
5890 /* l4_abe -> timer5 */
5891 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5
= {
5892 .master
= &omap44xx_l4_abe_hwmod
,
5893 .slave
= &omap44xx_timer5_hwmod
,
5894 .clk
= "ocp_abe_iclk",
5895 .addr
= omap44xx_timer5_addrs
,
5896 .user
= OCP_USER_MPU
,
5899 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs
[] = {
5901 .pa_start
= 0x49038000,
5902 .pa_end
= 0x4903807f,
5903 .flags
= ADDR_TYPE_RT
5908 /* l4_abe -> timer5 (dma) */
5909 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma
= {
5910 .master
= &omap44xx_l4_abe_hwmod
,
5911 .slave
= &omap44xx_timer5_hwmod
,
5912 .clk
= "ocp_abe_iclk",
5913 .addr
= omap44xx_timer5_dma_addrs
,
5914 .user
= OCP_USER_SDMA
,
5917 static struct omap_hwmod_addr_space omap44xx_timer6_addrs
[] = {
5919 .pa_start
= 0x4013a000,
5920 .pa_end
= 0x4013a07f,
5921 .flags
= ADDR_TYPE_RT
5926 /* l4_abe -> timer6 */
5927 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6
= {
5928 .master
= &omap44xx_l4_abe_hwmod
,
5929 .slave
= &omap44xx_timer6_hwmod
,
5930 .clk
= "ocp_abe_iclk",
5931 .addr
= omap44xx_timer6_addrs
,
5932 .user
= OCP_USER_MPU
,
5935 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs
[] = {
5937 .pa_start
= 0x4903a000,
5938 .pa_end
= 0x4903a07f,
5939 .flags
= ADDR_TYPE_RT
5944 /* l4_abe -> timer6 (dma) */
5945 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma
= {
5946 .master
= &omap44xx_l4_abe_hwmod
,
5947 .slave
= &omap44xx_timer6_hwmod
,
5948 .clk
= "ocp_abe_iclk",
5949 .addr
= omap44xx_timer6_dma_addrs
,
5950 .user
= OCP_USER_SDMA
,
5953 static struct omap_hwmod_addr_space omap44xx_timer7_addrs
[] = {
5955 .pa_start
= 0x4013c000,
5956 .pa_end
= 0x4013c07f,
5957 .flags
= ADDR_TYPE_RT
5962 /* l4_abe -> timer7 */
5963 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7
= {
5964 .master
= &omap44xx_l4_abe_hwmod
,
5965 .slave
= &omap44xx_timer7_hwmod
,
5966 .clk
= "ocp_abe_iclk",
5967 .addr
= omap44xx_timer7_addrs
,
5968 .user
= OCP_USER_MPU
,
5971 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs
[] = {
5973 .pa_start
= 0x4903c000,
5974 .pa_end
= 0x4903c07f,
5975 .flags
= ADDR_TYPE_RT
5980 /* l4_abe -> timer7 (dma) */
5981 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma
= {
5982 .master
= &omap44xx_l4_abe_hwmod
,
5983 .slave
= &omap44xx_timer7_hwmod
,
5984 .clk
= "ocp_abe_iclk",
5985 .addr
= omap44xx_timer7_dma_addrs
,
5986 .user
= OCP_USER_SDMA
,
5989 static struct omap_hwmod_addr_space omap44xx_timer8_addrs
[] = {
5991 .pa_start
= 0x4013e000,
5992 .pa_end
= 0x4013e07f,
5993 .flags
= ADDR_TYPE_RT
5998 /* l4_abe -> timer8 */
5999 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8
= {
6000 .master
= &omap44xx_l4_abe_hwmod
,
6001 .slave
= &omap44xx_timer8_hwmod
,
6002 .clk
= "ocp_abe_iclk",
6003 .addr
= omap44xx_timer8_addrs
,
6004 .user
= OCP_USER_MPU
,
6007 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs
[] = {
6009 .pa_start
= 0x4903e000,
6010 .pa_end
= 0x4903e07f,
6011 .flags
= ADDR_TYPE_RT
6016 /* l4_abe -> timer8 (dma) */
6017 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma
= {
6018 .master
= &omap44xx_l4_abe_hwmod
,
6019 .slave
= &omap44xx_timer8_hwmod
,
6020 .clk
= "ocp_abe_iclk",
6021 .addr
= omap44xx_timer8_dma_addrs
,
6022 .user
= OCP_USER_SDMA
,
6025 static struct omap_hwmod_addr_space omap44xx_timer9_addrs
[] = {
6027 .pa_start
= 0x4803e000,
6028 .pa_end
= 0x4803e07f,
6029 .flags
= ADDR_TYPE_RT
6034 /* l4_per -> timer9 */
6035 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9
= {
6036 .master
= &omap44xx_l4_per_hwmod
,
6037 .slave
= &omap44xx_timer9_hwmod
,
6039 .addr
= omap44xx_timer9_addrs
,
6040 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6043 static struct omap_hwmod_addr_space omap44xx_timer10_addrs
[] = {
6045 .pa_start
= 0x48086000,
6046 .pa_end
= 0x4808607f,
6047 .flags
= ADDR_TYPE_RT
6052 /* l4_per -> timer10 */
6053 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10
= {
6054 .master
= &omap44xx_l4_per_hwmod
,
6055 .slave
= &omap44xx_timer10_hwmod
,
6057 .addr
= omap44xx_timer10_addrs
,
6058 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6061 static struct omap_hwmod_addr_space omap44xx_timer11_addrs
[] = {
6063 .pa_start
= 0x48088000,
6064 .pa_end
= 0x4808807f,
6065 .flags
= ADDR_TYPE_RT
6070 /* l4_per -> timer11 */
6071 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11
= {
6072 .master
= &omap44xx_l4_per_hwmod
,
6073 .slave
= &omap44xx_timer11_hwmod
,
6075 .addr
= omap44xx_timer11_addrs
,
6076 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6079 static struct omap_hwmod_addr_space omap44xx_uart1_addrs
[] = {
6081 .pa_start
= 0x4806a000,
6082 .pa_end
= 0x4806a0ff,
6083 .flags
= ADDR_TYPE_RT
6088 /* l4_per -> uart1 */
6089 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1
= {
6090 .master
= &omap44xx_l4_per_hwmod
,
6091 .slave
= &omap44xx_uart1_hwmod
,
6093 .addr
= omap44xx_uart1_addrs
,
6094 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6097 static struct omap_hwmod_addr_space omap44xx_uart2_addrs
[] = {
6099 .pa_start
= 0x4806c000,
6100 .pa_end
= 0x4806c0ff,
6101 .flags
= ADDR_TYPE_RT
6106 /* l4_per -> uart2 */
6107 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2
= {
6108 .master
= &omap44xx_l4_per_hwmod
,
6109 .slave
= &omap44xx_uart2_hwmod
,
6111 .addr
= omap44xx_uart2_addrs
,
6112 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6115 static struct omap_hwmod_addr_space omap44xx_uart3_addrs
[] = {
6117 .pa_start
= 0x48020000,
6118 .pa_end
= 0x480200ff,
6119 .flags
= ADDR_TYPE_RT
6124 /* l4_per -> uart3 */
6125 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3
= {
6126 .master
= &omap44xx_l4_per_hwmod
,
6127 .slave
= &omap44xx_uart3_hwmod
,
6129 .addr
= omap44xx_uart3_addrs
,
6130 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6133 static struct omap_hwmod_addr_space omap44xx_uart4_addrs
[] = {
6135 .pa_start
= 0x4806e000,
6136 .pa_end
= 0x4806e0ff,
6137 .flags
= ADDR_TYPE_RT
6142 /* l4_per -> uart4 */
6143 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4
= {
6144 .master
= &omap44xx_l4_per_hwmod
,
6145 .slave
= &omap44xx_uart4_hwmod
,
6147 .addr
= omap44xx_uart4_addrs
,
6148 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6151 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs
[] = {
6153 .pa_start
= 0x4a0a9000,
6154 .pa_end
= 0x4a0a93ff,
6155 .flags
= ADDR_TYPE_RT
6160 /* l4_cfg -> usb_host_fs */
6161 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs
= {
6162 .master
= &omap44xx_l4_cfg_hwmod
,
6163 .slave
= &omap44xx_usb_host_fs_hwmod
,
6165 .addr
= omap44xx_usb_host_fs_addrs
,
6166 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6169 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs
[] = {
6172 .pa_start
= 0x4a064000,
6173 .pa_end
= 0x4a0647ff,
6174 .flags
= ADDR_TYPE_RT
6178 .pa_start
= 0x4a064800,
6179 .pa_end
= 0x4a064bff,
6183 .pa_start
= 0x4a064c00,
6184 .pa_end
= 0x4a064fff,
6189 /* l4_cfg -> usb_host_hs */
6190 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs
= {
6191 .master
= &omap44xx_l4_cfg_hwmod
,
6192 .slave
= &omap44xx_usb_host_hs_hwmod
,
6194 .addr
= omap44xx_usb_host_hs_addrs
,
6195 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6198 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs
[] = {
6200 .pa_start
= 0x4a0ab000,
6201 .pa_end
= 0x4a0ab7ff,
6202 .flags
= ADDR_TYPE_RT
6207 /* l4_cfg -> usb_otg_hs */
6208 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs
= {
6209 .master
= &omap44xx_l4_cfg_hwmod
,
6210 .slave
= &omap44xx_usb_otg_hs_hwmod
,
6212 .addr
= omap44xx_usb_otg_hs_addrs
,
6213 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6216 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs
[] = {
6219 .pa_start
= 0x4a062000,
6220 .pa_end
= 0x4a063fff,
6221 .flags
= ADDR_TYPE_RT
6226 /* l4_cfg -> usb_tll_hs */
6227 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs
= {
6228 .master
= &omap44xx_l4_cfg_hwmod
,
6229 .slave
= &omap44xx_usb_tll_hs_hwmod
,
6231 .addr
= omap44xx_usb_tll_hs_addrs
,
6232 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6235 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs
[] = {
6237 .pa_start
= 0x4a314000,
6238 .pa_end
= 0x4a31407f,
6239 .flags
= ADDR_TYPE_RT
6244 /* l4_wkup -> wd_timer2 */
6245 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2
= {
6246 .master
= &omap44xx_l4_wkup_hwmod
,
6247 .slave
= &omap44xx_wd_timer2_hwmod
,
6248 .clk
= "l4_wkup_clk_mux_ck",
6249 .addr
= omap44xx_wd_timer2_addrs
,
6250 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
6253 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs
[] = {
6255 .pa_start
= 0x40130000,
6256 .pa_end
= 0x4013007f,
6257 .flags
= ADDR_TYPE_RT
6262 /* l4_abe -> wd_timer3 */
6263 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3
= {
6264 .master
= &omap44xx_l4_abe_hwmod
,
6265 .slave
= &omap44xx_wd_timer3_hwmod
,
6266 .clk
= "ocp_abe_iclk",
6267 .addr
= omap44xx_wd_timer3_addrs
,
6268 .user
= OCP_USER_MPU
,
6271 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs
[] = {
6273 .pa_start
= 0x49030000,
6274 .pa_end
= 0x4903007f,
6275 .flags
= ADDR_TYPE_RT
6280 /* l4_abe -> wd_timer3 (dma) */
6281 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma
= {
6282 .master
= &omap44xx_l4_abe_hwmod
,
6283 .slave
= &omap44xx_wd_timer3_hwmod
,
6284 .clk
= "ocp_abe_iclk",
6285 .addr
= omap44xx_wd_timer3_dma_addrs
,
6286 .user
= OCP_USER_SDMA
,
6289 static struct omap_hwmod_ocp_if
*omap44xx_hwmod_ocp_ifs
[] __initdata
= {
6290 &omap44xx_c2c__c2c_target_fw
,
6291 &omap44xx_l4_cfg__c2c_target_fw
,
6292 &omap44xx_l3_main_1__dmm
,
6294 &omap44xx_c2c__emif_fw
,
6295 &omap44xx_dmm__emif_fw
,
6296 &omap44xx_l4_cfg__emif_fw
,
6297 &omap44xx_iva__l3_instr
,
6298 &omap44xx_l3_main_3__l3_instr
,
6299 &omap44xx_ocp_wp_noc__l3_instr
,
6300 &omap44xx_dsp__l3_main_1
,
6301 &omap44xx_dss__l3_main_1
,
6302 &omap44xx_l3_main_2__l3_main_1
,
6303 &omap44xx_l4_cfg__l3_main_1
,
6304 &omap44xx_mmc1__l3_main_1
,
6305 &omap44xx_mmc2__l3_main_1
,
6306 &omap44xx_mpu__l3_main_1
,
6307 &omap44xx_c2c_target_fw__l3_main_2
,
6308 &omap44xx_debugss__l3_main_2
,
6309 &omap44xx_dma_system__l3_main_2
,
6310 &omap44xx_fdif__l3_main_2
,
6311 &omap44xx_gpu__l3_main_2
,
6312 &omap44xx_hsi__l3_main_2
,
6313 &omap44xx_ipu__l3_main_2
,
6314 &omap44xx_iss__l3_main_2
,
6315 &omap44xx_iva__l3_main_2
,
6316 &omap44xx_l3_main_1__l3_main_2
,
6317 &omap44xx_l4_cfg__l3_main_2
,
6318 /* &omap44xx_usb_host_fs__l3_main_2, */
6319 &omap44xx_usb_host_hs__l3_main_2
,
6320 &omap44xx_usb_otg_hs__l3_main_2
,
6321 &omap44xx_l3_main_1__l3_main_3
,
6322 &omap44xx_l3_main_2__l3_main_3
,
6323 &omap44xx_l4_cfg__l3_main_3
,
6324 &omap44xx_aess__l4_abe
,
6325 &omap44xx_dsp__l4_abe
,
6326 &omap44xx_l3_main_1__l4_abe
,
6327 &omap44xx_mpu__l4_abe
,
6328 &omap44xx_l3_main_1__l4_cfg
,
6329 &omap44xx_l3_main_2__l4_per
,
6330 &omap44xx_l4_cfg__l4_wkup
,
6331 &omap44xx_mpu__mpu_private
,
6332 &omap44xx_l4_cfg__ocp_wp_noc
,
6333 &omap44xx_l4_abe__aess
,
6334 &omap44xx_l4_abe__aess_dma
,
6335 &omap44xx_l3_main_2__c2c
,
6336 &omap44xx_l4_wkup__counter_32k
,
6337 &omap44xx_l4_cfg__ctrl_module_core
,
6338 &omap44xx_l4_cfg__ctrl_module_pad_core
,
6339 &omap44xx_l4_wkup__ctrl_module_wkup
,
6340 &omap44xx_l4_wkup__ctrl_module_pad_wkup
,
6341 &omap44xx_l3_instr__debugss
,
6342 &omap44xx_l4_cfg__dma_system
,
6343 &omap44xx_l4_abe__dmic
,
6344 &omap44xx_l4_abe__dmic_dma
,
6346 /* &omap44xx_dsp__sl2if, */
6347 &omap44xx_l4_cfg__dsp
,
6348 &omap44xx_l3_main_2__dss
,
6349 &omap44xx_l4_per__dss
,
6350 &omap44xx_l3_main_2__dss_dispc
,
6351 &omap44xx_l4_per__dss_dispc
,
6352 &omap44xx_l3_main_2__dss_dsi1
,
6353 &omap44xx_l4_per__dss_dsi1
,
6354 &omap44xx_l3_main_2__dss_dsi2
,
6355 &omap44xx_l4_per__dss_dsi2
,
6356 &omap44xx_l3_main_2__dss_hdmi
,
6357 &omap44xx_l4_per__dss_hdmi
,
6358 &omap44xx_l3_main_2__dss_rfbi
,
6359 &omap44xx_l4_per__dss_rfbi
,
6360 &omap44xx_l3_main_2__dss_venc
,
6361 &omap44xx_l4_per__dss_venc
,
6362 &omap44xx_l4_per__elm
,
6363 &omap44xx_emif_fw__emif1
,
6364 &omap44xx_emif_fw__emif2
,
6365 &omap44xx_l4_cfg__fdif
,
6366 &omap44xx_l4_wkup__gpio1
,
6367 &omap44xx_l4_per__gpio2
,
6368 &omap44xx_l4_per__gpio3
,
6369 &omap44xx_l4_per__gpio4
,
6370 &omap44xx_l4_per__gpio5
,
6371 &omap44xx_l4_per__gpio6
,
6372 &omap44xx_l3_main_2__gpmc
,
6373 &omap44xx_l3_main_2__gpu
,
6374 &omap44xx_l4_per__hdq1w
,
6375 &omap44xx_l4_cfg__hsi
,
6376 &omap44xx_l4_per__i2c1
,
6377 &omap44xx_l4_per__i2c2
,
6378 &omap44xx_l4_per__i2c3
,
6379 &omap44xx_l4_per__i2c4
,
6380 &omap44xx_l3_main_2__ipu
,
6381 &omap44xx_l3_main_2__iss
,
6382 /* &omap44xx_iva__sl2if, */
6383 &omap44xx_l3_main_2__iva
,
6384 &omap44xx_l4_wkup__kbd
,
6385 &omap44xx_l4_cfg__mailbox
,
6386 &omap44xx_l4_abe__mcasp
,
6387 &omap44xx_l4_abe__mcasp_dma
,
6388 &omap44xx_l4_abe__mcbsp1
,
6389 &omap44xx_l4_abe__mcbsp1_dma
,
6390 &omap44xx_l4_abe__mcbsp2
,
6391 &omap44xx_l4_abe__mcbsp2_dma
,
6392 &omap44xx_l4_abe__mcbsp3
,
6393 &omap44xx_l4_abe__mcbsp3_dma
,
6394 &omap44xx_l4_per__mcbsp4
,
6395 &omap44xx_l4_abe__mcpdm
,
6396 &omap44xx_l4_abe__mcpdm_dma
,
6397 &omap44xx_l4_per__mcspi1
,
6398 &omap44xx_l4_per__mcspi2
,
6399 &omap44xx_l4_per__mcspi3
,
6400 &omap44xx_l4_per__mcspi4
,
6401 &omap44xx_l4_per__mmc1
,
6402 &omap44xx_l4_per__mmc2
,
6403 &omap44xx_l4_per__mmc3
,
6404 &omap44xx_l4_per__mmc4
,
6405 &omap44xx_l4_per__mmc5
,
6406 &omap44xx_l3_main_2__mmu_ipu
,
6407 &omap44xx_l4_cfg__mmu_dsp
,
6408 &omap44xx_l3_main_2__ocmc_ram
,
6409 &omap44xx_l4_cfg__ocp2scp_usb_phy
,
6410 &omap44xx_mpu_private__prcm_mpu
,
6411 &omap44xx_l4_wkup__cm_core_aon
,
6412 &omap44xx_l4_cfg__cm_core
,
6413 &omap44xx_l4_wkup__prm
,
6414 &omap44xx_l4_wkup__scrm
,
6415 /* &omap44xx_l3_main_2__sl2if, */
6416 &omap44xx_l4_abe__slimbus1
,
6417 &omap44xx_l4_abe__slimbus1_dma
,
6418 &omap44xx_l4_per__slimbus2
,
6419 &omap44xx_l4_cfg__smartreflex_core
,
6420 &omap44xx_l4_cfg__smartreflex_iva
,
6421 &omap44xx_l4_cfg__smartreflex_mpu
,
6422 &omap44xx_l4_cfg__spinlock
,
6423 &omap44xx_l4_wkup__timer1
,
6424 &omap44xx_l4_per__timer2
,
6425 &omap44xx_l4_per__timer3
,
6426 &omap44xx_l4_per__timer4
,
6427 &omap44xx_l4_abe__timer5
,
6428 &omap44xx_l4_abe__timer5_dma
,
6429 &omap44xx_l4_abe__timer6
,
6430 &omap44xx_l4_abe__timer6_dma
,
6431 &omap44xx_l4_abe__timer7
,
6432 &omap44xx_l4_abe__timer7_dma
,
6433 &omap44xx_l4_abe__timer8
,
6434 &omap44xx_l4_abe__timer8_dma
,
6435 &omap44xx_l4_per__timer9
,
6436 &omap44xx_l4_per__timer10
,
6437 &omap44xx_l4_per__timer11
,
6438 &omap44xx_l4_per__uart1
,
6439 &omap44xx_l4_per__uart2
,
6440 &omap44xx_l4_per__uart3
,
6441 &omap44xx_l4_per__uart4
,
6442 /* &omap44xx_l4_cfg__usb_host_fs, */
6443 &omap44xx_l4_cfg__usb_host_hs
,
6444 &omap44xx_l4_cfg__usb_otg_hs
,
6445 &omap44xx_l4_cfg__usb_tll_hs
,
6446 &omap44xx_l4_wkup__wd_timer2
,
6447 &omap44xx_l4_abe__wd_timer3
,
6448 &omap44xx_l4_abe__wd_timer3_dma
,
6452 int __init
omap44xx_hwmod_init(void)
6455 return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs
);