arch/arm/mach-omap2/omap_hwmod_54xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP54xx chips
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Paul Walmsley
   7  * Benoit Cousson
   8  *
   9  * This file is automatically generated from the OMAP hardware databases.
  10  * We respectfully ask that any modifications to this file be coordinated
  11  * with the public linux-omap@vger.kernel.org mailing list and the
  12  * authors above to ensure that the autogeneration scripts are kept
  13  * up-to-date with the file contents.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19
  20 #include <linux/io.h>
  21 #include <linux/platform_data/gpio-omap.h>
  22 #include <linux/power/smartreflex.h>
  23 #include <linux/i2c-omap.h>
  24
  25 #include <linux/omap-dma.h>
  26 #include <linux/platform_data/spi-omap2-mcspi.h>
  27 #include <linux/platform_data/asoc-ti-mcbsp.h>
  28 #include <plat/dmtimer.h>
  29
  30 #include "omap_hwmod.h"
  31 #include "omap_hwmod_common_data.h"
  32 #include "cm1_54xx.h"
  33 #include "cm2_54xx.h"
  34 #include "prm54xx.h"
  35 #include "prm-regbits-54xx.h"
  36 #include "i2c.h"
  37 #include "mmc.h"
  38 #include "wd_timer.h"
  39
  40 /* Base offset for all OMAP5 interrupts external to MPUSS */
  41 #define OMAP54XX_IRQ_GIC_START  32
  42
  43 /* Base offset for all OMAP5 dma requests */
  44 #define OMAP54XX_DMA_REQ_START  1
  45
  46
  47 /*
  48  * IP blocks
  49  */
  50
  51 /*
  52  * 'dmm' class
  53  * instance(s): dmm
  54  */
  55 static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
  56         .name   = "dmm",
  57 };
  58
  59 /* dmm */
  60 static struct omap_hwmod omap54xx_dmm_hwmod = {
  61         .name           = "dmm",
  62         .class          = &omap54xx_dmm_hwmod_class,
  63         .clkdm_name     = "emif_clkdm",
  64         .prcm = {
  65                 .omap4 = {
  66                         .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
  67                         .context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
  68                 },
  69         },
  70 };
  71
  72 /*
  73  * 'l3' class
  74  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
  75  */
  76 static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
  77         .name   = "l3",
  78 };
  79
  80 /* l3_instr */
  81 static struct omap_hwmod omap54xx_l3_instr_hwmod = {
  82         .name           = "l3_instr",
  83         .class          = &omap54xx_l3_hwmod_class,
  84         .clkdm_name     = "l3instr_clkdm",
  85         .prcm = {
  86                 .omap4 = {
  87                         .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  88                         .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  89                         .modulemode   = MODULEMODE_HWCTRL,
  90                 },
  91         },
  92 };
  93
  94 /* l3_main_1 */
  95 static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
  96         .name           = "l3_main_1",
  97         .class          = &omap54xx_l3_hwmod_class,
  98         .clkdm_name     = "l3main1_clkdm",
  99         .prcm = {
 100                 .omap4 = {
 101                         .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
 102                         .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
 103                 },
 104         },
 105 };
 106
 107 /* l3_main_2 */
 108 static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
 109         .name           = "l3_main_2",
 110         .class          = &omap54xx_l3_hwmod_class,
 111         .clkdm_name     = "l3main2_clkdm",
 112         .prcm = {
 113                 .omap4 = {
 114                         .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
 115                         .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
 116                 },
 117         },
 118 };
 119
 120 /* l3_main_3 */
 121 static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
 122         .name           = "l3_main_3",
 123         .class          = &omap54xx_l3_hwmod_class,
 124         .clkdm_name     = "l3instr_clkdm",
 125         .prcm = {
 126                 .omap4 = {
 127                         .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
 128                         .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
 129                         .modulemode   = MODULEMODE_HWCTRL,
 130                 },
 131         },
 132 };
 133
 134 /*
 135  * 'l4' class
 136  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 137  */
 138 static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
 139         .name   = "l4",
 140 };
 141
 142 /* l4_abe */
 143 static struct omap_hwmod omap54xx_l4_abe_hwmod = {
 144         .name           = "l4_abe",
 145         .class          = &omap54xx_l4_hwmod_class,
 146         .clkdm_name     = "abe_clkdm",
 147         .prcm = {
 148                 .omap4 = {
 149                         .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
 150                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 151                 },
 152         },
 153 };
 154
 155 /* l4_cfg */
 156 static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
 157         .name           = "l4_cfg",
 158         .class          = &omap54xx_l4_hwmod_class,
 159         .clkdm_name     = "l4cfg_clkdm",
 160         .prcm = {
 161                 .omap4 = {
 162                         .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 163                         .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 164                 },
 165         },
 166 };
 167
 168 /* l4_per */
 169 static struct omap_hwmod omap54xx_l4_per_hwmod = {
 170         .name           = "l4_per",
 171         .class          = &omap54xx_l4_hwmod_class,
 172         .clkdm_name     = "l4per_clkdm",
 173         .prcm = {
 174                 .omap4 = {
 175                         .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
 176                         .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 177                 },
 178         },
 179 };
 180
 181 /* l4_wkup */
 182 static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
 183         .name           = "l4_wkup",
 184         .class          = &omap54xx_l4_hwmod_class,
 185         .clkdm_name     = "wkupaon_clkdm",
 186         .prcm = {
 187                 .omap4 = {
 188                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
 189                         .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
 190                 },
 191         },
 192 };
 193
 194 /*
 195  * 'mpu_bus' class
 196  * instance(s): mpu_private
 197  */
 198 static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
 199         .name   = "mpu_bus",
 200 };
 201
 202 /* mpu_private */
 203 static struct omap_hwmod omap54xx_mpu_private_hwmod = {
 204         .name           = "mpu_private",
 205         .class          = &omap54xx_mpu_bus_hwmod_class,
 206         .clkdm_name     = "mpu_clkdm",
 207         .prcm = {
 208                 .omap4 = {
 209                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 210                 },
 211         },
 212 };
 213
 214 /*
 215  * 'counter' class
 216  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 217  */
 218
 219 static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = {
 220         .rev_offs       = 0x0000,
 221         .sysc_offs      = 0x0010,
 222         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 223         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 224         .sysc_fields    = &omap_hwmod_sysc_type1,
 225 };
 226
 227 static struct omap_hwmod_class omap54xx_counter_hwmod_class = {
 228         .name   = "counter",
 229         .sysc   = &omap54xx_counter_sysc,
 230 };
 231
 232 /* counter_32k */
 233 static struct omap_hwmod omap54xx_counter_32k_hwmod = {
 234         .name           = "counter_32k",
 235         .class          = &omap54xx_counter_hwmod_class,
 236         .clkdm_name     = "wkupaon_clkdm",
 237         .flags          = HWMOD_SWSUP_SIDLE,
 238         .main_clk       = "wkupaon_iclk_mux",
 239         .prcm = {
 240                 .omap4 = {
 241                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
 242                         .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
 243                 },
 244         },
 245 };
 246
 247 /*
 248  * 'dma' class
 249  * dma controller for data exchange between memory to memory (i.e. internal or
 250  * external memory) and gp peripherals to memory or memory to gp peripherals
 251  */
 252
 253 static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc = {
 254         .rev_offs       = 0x0000,
 255         .sysc_offs      = 0x002c,
 256         .syss_offs      = 0x0028,
 257         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 258                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 259                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 260                            SYSS_HAS_RESET_STATUS),
 261         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 262                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 263         .sysc_fields    = &omap_hwmod_sysc_type1,
 264 };
 265
 266 static struct omap_hwmod_class omap54xx_dma_hwmod_class = {
 267         .name   = "dma",
 268         .sysc   = &omap54xx_dma_sysc,
 269 };
 270
 271 /* dma dev_attr */
 272 static struct omap_dma_dev_attr dma_dev_attr = {
 273         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 274                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 275         .lch_count      = 32,
 276 };
 277
 278 /* dma_system */
 279 static struct omap_hwmod_irq_info omap54xx_dma_system_irqs[] = {
 280         { .name = "0", .irq = 12 + OMAP54XX_IRQ_GIC_START },
 281         { .name = "1", .irq = 13 + OMAP54XX_IRQ_GIC_START },
 282         { .name = "2", .irq = 14 + OMAP54XX_IRQ_GIC_START },
 283         { .name = "3", .irq = 15 + OMAP54XX_IRQ_GIC_START },
 284         { .irq = -1 }
 285 };
 286
 287 static struct omap_hwmod omap54xx_dma_system_hwmod = {
 288         .name           = "dma_system",
 289         .class          = &omap54xx_dma_hwmod_class,
 290         .clkdm_name     = "dma_clkdm",
 291         .mpu_irqs       = omap54xx_dma_system_irqs,
 292         .main_clk       = "l3_iclk_div",
 293         .prcm = {
 294                 .omap4 = {
 295                         .clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
 296                         .context_offs = OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
 297                 },
 298         },
 299         .dev_attr       = &dma_dev_attr,
 300 };
 301
 302 /*
 303  * 'dmic' class
 304  * digital microphone controller
 305  */
 306
 307 static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc = {
 308         .rev_offs       = 0x0000,
 309         .sysc_offs      = 0x0010,
 310         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 311                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 312         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 313                            SIDLE_SMART_WKUP),
 314         .sysc_fields    = &omap_hwmod_sysc_type2,
 315 };
 316
 317 static struct omap_hwmod_class omap54xx_dmic_hwmod_class = {
 318         .name   = "dmic",
 319         .sysc   = &omap54xx_dmic_sysc,
 320 };
 321
 322 /* dmic */
 323 static struct omap_hwmod omap54xx_dmic_hwmod = {
 324         .name           = "dmic",
 325         .class          = &omap54xx_dmic_hwmod_class,
 326         .clkdm_name     = "abe_clkdm",
 327         .main_clk       = "dmic_gfclk",
 328         .prcm = {
 329                 .omap4 = {
 330                         .clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET,
 331                         .context_offs = OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET,
 332                         .modulemode   = MODULEMODE_SWCTRL,
 333                 },
 334         },
 335 };
 336
 337 /*
 338  * 'emif' class
 339  * external memory interface no1 (wrapper)
 340  */
 341
 342 static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
 343         .rev_offs       = 0x0000,
 344 };
 345
 346 static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
 347         .name   = "emif",
 348         .sysc   = &omap54xx_emif_sysc,
 349 };
 350
 351 /* emif1 */
 352 static struct omap_hwmod omap54xx_emif1_hwmod = {
 353         .name           = "emif1",
 354         .class          = &omap54xx_emif_hwmod_class,
 355         .clkdm_name     = "emif_clkdm",
 356         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
 357         .main_clk       = "dpll_core_h11x2_ck",
 358         .prcm = {
 359                 .omap4 = {
 360                         .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
 361                         .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
 362                         .modulemode   = MODULEMODE_HWCTRL,
 363                 },
 364         },
 365 };
 366
 367 /* emif2 */
 368 static struct omap_hwmod omap54xx_emif2_hwmod = {
 369         .name           = "emif2",
 370         .class          = &omap54xx_emif_hwmod_class,
 371         .clkdm_name     = "emif_clkdm",
 372         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
 373         .main_clk       = "dpll_core_h11x2_ck",
 374         .prcm = {
 375                 .omap4 = {
 376                         .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
 377                         .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
 378                         .modulemode   = MODULEMODE_HWCTRL,
 379                 },
 380         },
 381 };
 382
 383 /*
 384  * 'gpio' class
 385  * general purpose io module
 386  */
 387
 388 static struct omap_hwmod_class_sysconfig omap54xx_gpio_sysc = {
 389         .rev_offs       = 0x0000,
 390         .sysc_offs      = 0x0010,
 391         .syss_offs      = 0x0114,
 392         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 393                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 394                            SYSS_HAS_RESET_STATUS),
 395         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 396                            SIDLE_SMART_WKUP),
 397         .sysc_fields    = &omap_hwmod_sysc_type1,
 398 };
 399
 400 static struct omap_hwmod_class omap54xx_gpio_hwmod_class = {
 401         .name   = "gpio",
 402         .sysc   = &omap54xx_gpio_sysc,
 403         .rev    = 2,
 404 };
 405
 406 /* gpio dev_attr */
 407 static struct omap_gpio_dev_attr gpio_dev_attr = {
 408         .bank_width     = 32,
 409         .dbck_flag      = true,
 410 };
 411
 412 /* gpio1 */
 413 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 414         { .role = "dbclk", .clk = "gpio1_dbclk" },
 415 };
 416
 417 static struct omap_hwmod omap54xx_gpio1_hwmod = {
 418         .name           = "gpio1",
 419         .class          = &omap54xx_gpio_hwmod_class,
 420         .clkdm_name     = "wkupaon_clkdm",
 421         .main_clk       = "wkupaon_iclk_mux",
 422         .prcm = {
 423                 .omap4 = {
 424                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
 425                         .context_offs = OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
 426                         .modulemode   = MODULEMODE_HWCTRL,
 427                 },
 428         },
 429         .opt_clks       = gpio1_opt_clks,
 430         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 431         .dev_attr       = &gpio_dev_attr,
 432 };
 433
 434 /* gpio2 */
 435 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 436         { .role = "dbclk", .clk = "gpio2_dbclk" },
 437 };
 438
 439 static struct omap_hwmod omap54xx_gpio2_hwmod = {
 440         .name           = "gpio2",
 441         .class          = &omap54xx_gpio_hwmod_class,
 442         .clkdm_name     = "l4per_clkdm",
 443         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 444         .main_clk       = "l4_root_clk_div",
 445         .prcm = {
 446                 .omap4 = {
 447                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
 448                         .context_offs = OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
 449                         .modulemode   = MODULEMODE_HWCTRL,
 450                 },
 451         },
 452         .opt_clks       = gpio2_opt_clks,
 453         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 454         .dev_attr       = &gpio_dev_attr,
 455 };
 456
 457 /* gpio3 */
 458 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 459         { .role = "dbclk", .clk = "gpio3_dbclk" },
 460 };
 461
 462 static struct omap_hwmod omap54xx_gpio3_hwmod = {
 463         .name           = "gpio3",
 464         .class          = &omap54xx_gpio_hwmod_class,
 465         .clkdm_name     = "l4per_clkdm",
 466         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 467         .main_clk       = "l4_root_clk_div",
 468         .prcm = {
 469                 .omap4 = {
 470                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
 471                         .context_offs = OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
 472                         .modulemode   = MODULEMODE_HWCTRL,
 473                 },
 474         },
 475         .opt_clks       = gpio3_opt_clks,
 476         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 477         .dev_attr       = &gpio_dev_attr,
 478 };
 479
 480 /* gpio4 */
 481 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 482         { .role = "dbclk", .clk = "gpio4_dbclk" },
 483 };
 484
 485 static struct omap_hwmod omap54xx_gpio4_hwmod = {
 486         .name           = "gpio4",
 487         .class          = &omap54xx_gpio_hwmod_class,
 488         .clkdm_name     = "l4per_clkdm",
 489         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 490         .main_clk       = "l4_root_clk_div",
 491         .prcm = {
 492                 .omap4 = {
 493                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
 494                         .context_offs = OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
 495                         .modulemode   = MODULEMODE_HWCTRL,
 496                 },
 497         },
 498         .opt_clks       = gpio4_opt_clks,
 499         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 500         .dev_attr       = &gpio_dev_attr,
 501 };
 502
 503 /* gpio5 */
 504 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 505         { .role = "dbclk", .clk = "gpio5_dbclk" },
 506 };
 507
 508 static struct omap_hwmod omap54xx_gpio5_hwmod = {
 509         .name           = "gpio5",
 510         .class          = &omap54xx_gpio_hwmod_class,
 511         .clkdm_name     = "l4per_clkdm",
 512         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 513         .main_clk       = "l4_root_clk_div",
 514         .prcm = {
 515                 .omap4 = {
 516                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
 517                         .context_offs = OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
 518                         .modulemode   = MODULEMODE_HWCTRL,
 519                 },
 520         },
 521         .opt_clks       = gpio5_opt_clks,
 522         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
 523         .dev_attr       = &gpio_dev_attr,
 524 };
 525
 526 /* gpio6 */
 527 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
 528         { .role = "dbclk", .clk = "gpio6_dbclk" },
 529 };
 530
 531 static struct omap_hwmod omap54xx_gpio6_hwmod = {
 532         .name           = "gpio6",
 533         .class          = &omap54xx_gpio_hwmod_class,
 534         .clkdm_name     = "l4per_clkdm",
 535         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 536         .main_clk       = "l4_root_clk_div",
 537         .prcm = {
 538                 .omap4 = {
 539                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
 540                         .context_offs = OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
 541                         .modulemode   = MODULEMODE_HWCTRL,
 542                 },
 543         },
 544         .opt_clks       = gpio6_opt_clks,
 545         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
 546         .dev_attr       = &gpio_dev_attr,
 547 };
 548
 549 /* gpio7 */
 550 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
 551         { .role = "dbclk", .clk = "gpio7_dbclk" },
 552 };
 553
 554 static struct omap_hwmod omap54xx_gpio7_hwmod = {
 555         .name           = "gpio7",
 556         .class          = &omap54xx_gpio_hwmod_class,
 557         .clkdm_name     = "l4per_clkdm",
 558         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 559         .main_clk       = "l4_root_clk_div",
 560         .prcm = {
 561                 .omap4 = {
 562                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
 563                         .context_offs = OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
 564                         .modulemode   = MODULEMODE_HWCTRL,
 565                 },
 566         },
 567         .opt_clks       = gpio7_opt_clks,
 568         .opt_clks_cnt   = ARRAY_SIZE(gpio7_opt_clks),
 569         .dev_attr       = &gpio_dev_attr,
 570 };
 571
 572 /* gpio8 */
 573 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
 574         { .role = "dbclk", .clk = "gpio8_dbclk" },
 575 };
 576
 577 static struct omap_hwmod omap54xx_gpio8_hwmod = {
 578         .name           = "gpio8",
 579         .class          = &omap54xx_gpio_hwmod_class,
 580         .clkdm_name     = "l4per_clkdm",
 581         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 582         .main_clk       = "l4_root_clk_div",
 583         .prcm = {
 584                 .omap4 = {
 585                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
 586                         .context_offs = OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
 587                         .modulemode   = MODULEMODE_HWCTRL,
 588                 },
 589         },
 590         .opt_clks       = gpio8_opt_clks,
 591         .opt_clks_cnt   = ARRAY_SIZE(gpio8_opt_clks),
 592         .dev_attr       = &gpio_dev_attr,
 593 };
 594
 595 /*
 596  * 'i2c' class
 597  * multimaster high-speed i2c controller
 598  */
 599
 600 static struct omap_hwmod_class_sysconfig omap54xx_i2c_sysc = {
 601         .sysc_offs      = 0x0010,
 602         .syss_offs      = 0x0090,
 603         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 604                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 605                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 606         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 607                            SIDLE_SMART_WKUP),
 608         .clockact       = CLOCKACT_TEST_ICLK,
 609         .sysc_fields    = &omap_hwmod_sysc_type1,
 610 };
 611
 612 static struct omap_hwmod_class omap54xx_i2c_hwmod_class = {
 613         .name   = "i2c",
 614         .sysc   = &omap54xx_i2c_sysc,
 615         .reset  = &omap_i2c_reset,
 616         .rev    = OMAP_I2C_IP_VERSION_2,
 617 };
 618
 619 /* i2c dev_attr */
 620 static struct omap_i2c_dev_attr i2c_dev_attr = {
 621         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
 622 };
 623
 624 /* i2c1 */
 625 static struct omap_hwmod omap54xx_i2c1_hwmod = {
 626         .name           = "i2c1",
 627         .class          = &omap54xx_i2c_hwmod_class,
 628         .clkdm_name     = "l4per_clkdm",
 629         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 630         .main_clk       = "func_96m_fclk",
 631         .prcm = {
 632                 .omap4 = {
 633                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
 634                         .context_offs = OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
 635                         .modulemode   = MODULEMODE_SWCTRL,
 636                 },
 637         },
 638         .dev_attr       = &i2c_dev_attr,
 639 };
 640
 641 /* i2c2 */
 642 static struct omap_hwmod omap54xx_i2c2_hwmod = {
 643         .name           = "i2c2",
 644         .class          = &omap54xx_i2c_hwmod_class,
 645         .clkdm_name     = "l4per_clkdm",
 646         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 647         .main_clk       = "func_96m_fclk",
 648         .prcm = {
 649                 .omap4 = {
 650                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
 651                         .context_offs = OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
 652                         .modulemode   = MODULEMODE_SWCTRL,
 653                 },
 654         },
 655         .dev_attr       = &i2c_dev_attr,
 656 };
 657
 658 /* i2c3 */
 659 static struct omap_hwmod omap54xx_i2c3_hwmod = {
 660         .name           = "i2c3",
 661         .class          = &omap54xx_i2c_hwmod_class,
 662         .clkdm_name     = "l4per_clkdm",
 663         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 664         .main_clk       = "func_96m_fclk",
 665         .prcm = {
 666                 .omap4 = {
 667                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
 668                         .context_offs = OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
 669                         .modulemode   = MODULEMODE_SWCTRL,
 670                 },
 671         },
 672         .dev_attr       = &i2c_dev_attr,
 673 };
 674
 675 /* i2c4 */
 676 static struct omap_hwmod omap54xx_i2c4_hwmod = {
 677         .name           = "i2c4",
 678         .class          = &omap54xx_i2c_hwmod_class,
 679         .clkdm_name     = "l4per_clkdm",
 680         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 681         .main_clk       = "func_96m_fclk",
 682         .prcm = {
 683                 .omap4 = {
 684                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
 685                         .context_offs = OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
 686                         .modulemode   = MODULEMODE_SWCTRL,
 687                 },
 688         },
 689         .dev_attr       = &i2c_dev_attr,
 690 };
 691
 692 /* i2c5 */
 693 static struct omap_hwmod omap54xx_i2c5_hwmod = {
 694         .name           = "i2c5",
 695         .class          = &omap54xx_i2c_hwmod_class,
 696         .clkdm_name     = "l4per_clkdm",
 697         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 698         .main_clk       = "func_96m_fclk",
 699         .prcm = {
 700                 .omap4 = {
 701                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET,
 702                         .context_offs = OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET,
 703                         .modulemode   = MODULEMODE_SWCTRL,
 704                 },
 705         },
 706         .dev_attr       = &i2c_dev_attr,
 707 };
 708
 709 /*
 710  * 'kbd' class
 711  * keyboard controller
 712  */
 713
 714 static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc = {
 715         .rev_offs       = 0x0000,
 716         .sysc_offs      = 0x0010,
 717         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
 718                            SYSC_HAS_SOFTRESET),
 719         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 720         .sysc_fields    = &omap_hwmod_sysc_type1,
 721 };
 722
 723 static struct omap_hwmod_class omap54xx_kbd_hwmod_class = {
 724         .name   = "kbd",
 725         .sysc   = &omap54xx_kbd_sysc,
 726 };
 727
 728 /* kbd */
 729 static struct omap_hwmod omap54xx_kbd_hwmod = {
 730         .name           = "kbd",
 731         .class          = &omap54xx_kbd_hwmod_class,
 732         .clkdm_name     = "wkupaon_clkdm",
 733         .main_clk       = "sys_32k_ck",
 734         .prcm = {
 735                 .omap4 = {
 736                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET,
 737                         .context_offs = OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET,
 738                         .modulemode   = MODULEMODE_SWCTRL,
 739                 },
 740         },
 741 };
 742
 743 /*
 744  * 'mcbsp' class
 745  * multi channel buffered serial port controller
 746  */
 747
 748 static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = {
 749         .sysc_offs      = 0x008c,
 750         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
 751                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 752         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 753         .sysc_fields    = &omap_hwmod_sysc_type1,
 754 };
 755
 756 static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = {
 757         .name   = "mcbsp",
 758         .sysc   = &omap54xx_mcbsp_sysc,
 759         .rev    = MCBSP_CONFIG_TYPE4,
 760 };
 761
 762 /* mcbsp1 */
 763 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
 764         { .role = "pad_fck", .clk = "pad_clks_ck" },
 765         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
 766 };
 767
 768 static struct omap_hwmod omap54xx_mcbsp1_hwmod = {
 769         .name           = "mcbsp1",
 770         .class          = &omap54xx_mcbsp_hwmod_class,
 771         .clkdm_name     = "abe_clkdm",
 772         .main_clk       = "mcbsp1_gfclk",
 773         .prcm = {
 774                 .omap4 = {
 775                         .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET,
 776                         .context_offs = OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET,
 777                         .modulemode   = MODULEMODE_SWCTRL,
 778                 },
 779         },
 780         .opt_clks       = mcbsp1_opt_clks,
 781         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
 782 };
 783
 784 /* mcbsp2 */
 785 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
 786         { .role = "pad_fck", .clk = "pad_clks_ck" },
 787         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
 788 };
 789
 790 static struct omap_hwmod omap54xx_mcbsp2_hwmod = {
 791         .name           = "mcbsp2",
 792         .class          = &omap54xx_mcbsp_hwmod_class,
 793         .clkdm_name     = "abe_clkdm",
 794         .main_clk       = "mcbsp2_gfclk",
 795         .prcm = {
 796                 .omap4 = {
 797                         .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET,
 798                         .context_offs = OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET,
 799                         .modulemode   = MODULEMODE_SWCTRL,
 800                 },
 801         },
 802         .opt_clks       = mcbsp2_opt_clks,
 803         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
 804 };
 805
 806 /* mcbsp3 */
 807 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
 808         { .role = "pad_fck", .clk = "pad_clks_ck" },
 809         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
 810 };
 811
 812 static struct omap_hwmod omap54xx_mcbsp3_hwmod = {
 813         .name           = "mcbsp3",
 814         .class          = &omap54xx_mcbsp_hwmod_class,
 815         .clkdm_name     = "abe_clkdm",
 816         .main_clk       = "mcbsp3_gfclk",
 817         .prcm = {
 818                 .omap4 = {
 819                         .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET,
 820                         .context_offs = OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET,
 821                         .modulemode   = MODULEMODE_SWCTRL,
 822                 },
 823         },
 824         .opt_clks       = mcbsp3_opt_clks,
 825         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
 826 };
 827
 828 /*
 829  * 'mcpdm' class
 830  * multi channel pdm controller (proprietary interface with phoenix power
 831  * ic)
 832  */
 833
 834 static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc = {
 835         .rev_offs       = 0x0000,
 836         .sysc_offs      = 0x0010,
 837         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 838                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 839         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 840                            SIDLE_SMART_WKUP),
 841         .sysc_fields    = &omap_hwmod_sysc_type2,
 842 };
 843
 844 static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class = {
 845         .name   = "mcpdm",
 846         .sysc   = &omap54xx_mcpdm_sysc,
 847 };
 848
 849 /* mcpdm */
 850 static struct omap_hwmod omap54xx_mcpdm_hwmod = {
 851         .name           = "mcpdm",
 852         .class          = &omap54xx_mcpdm_hwmod_class,
 853         .clkdm_name     = "abe_clkdm",
 854         /*
 855          * It's suspected that the McPDM requires an off-chip main
 856          * functional clock, controlled via I2C.  This IP block is
 857          * currently reset very early during boot, before I2C is
 858          * available, so it doesn't seem that we have any choice in
 859          * the kernel other than to avoid resetting it.  XXX This is
 860          * really a hardware issue workaround: every IP block should
 861          * be able to source its main functional clock from either
 862          * on-chip or off-chip sources.  McPDM seems to be the only
 863          * current exception.
 864          */
 865
 866         .flags          = HWMOD_EXT_OPT_MAIN_CLK,
 867         .main_clk       = "pad_clks_ck",
 868         .prcm = {
 869                 .omap4 = {
 870                         .clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET,
 871                         .context_offs = OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET,
 872                         .modulemode   = MODULEMODE_SWCTRL,
 873                 },
 874         },
 875 };
 876
 877 /*
 878  * 'mcspi' class
 879  * multichannel serial port interface (mcspi) / master/slave synchronous serial
 880  * bus
 881  */
 882
 883 static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = {
 884         .rev_offs       = 0x0000,
 885         .sysc_offs      = 0x0010,
 886         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 887                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 888         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 889                            SIDLE_SMART_WKUP),
 890         .sysc_fields    = &omap_hwmod_sysc_type2,
 891 };
 892
 893 static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = {
 894         .name   = "mcspi",
 895         .sysc   = &omap54xx_mcspi_sysc,
 896         .rev    = OMAP4_MCSPI_REV,
 897 };
 898
 899 /* mcspi1 */
 900 /* mcspi1 dev_attr */
 901 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
 902         .num_chipselect = 4,
 903 };
 904
 905 static struct omap_hwmod omap54xx_mcspi1_hwmod = {
 906         .name           = "mcspi1",
 907         .class          = &omap54xx_mcspi_hwmod_class,
 908         .clkdm_name     = "l4per_clkdm",
 909         .main_clk       = "func_48m_fclk",
 910         .prcm = {
 911                 .omap4 = {
 912                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
 913                         .context_offs = OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
 914                         .modulemode   = MODULEMODE_SWCTRL,
 915                 },
 916         },
 917         .dev_attr       = &mcspi1_dev_attr,
 918 };
 919
 920 /* mcspi2 */
 921 /* mcspi2 dev_attr */
 922 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
 923         .num_chipselect = 2,
 924 };
 925
 926 static struct omap_hwmod omap54xx_mcspi2_hwmod = {
 927         .name           = "mcspi2",
 928         .class          = &omap54xx_mcspi_hwmod_class,
 929         .clkdm_name     = "l4per_clkdm",
 930         .main_clk       = "func_48m_fclk",
 931         .prcm = {
 932                 .omap4 = {
 933                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
 934                         .context_offs = OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
 935                         .modulemode   = MODULEMODE_SWCTRL,
 936                 },
 937         },
 938         .dev_attr       = &mcspi2_dev_attr,
 939 };
 940
 941 /* mcspi3 */
 942 /* mcspi3 dev_attr */
 943 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
 944         .num_chipselect = 2,
 945 };
 946
 947 static struct omap_hwmod omap54xx_mcspi3_hwmod = {
 948         .name           = "mcspi3",
 949         .class          = &omap54xx_mcspi_hwmod_class,
 950         .clkdm_name     = "l4per_clkdm",
 951         .main_clk       = "func_48m_fclk",
 952         .prcm = {
 953                 .omap4 = {
 954                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
 955                         .context_offs = OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
 956                         .modulemode   = MODULEMODE_SWCTRL,
 957                 },
 958         },
 959         .dev_attr       = &mcspi3_dev_attr,
 960 };
 961
 962 /* mcspi4 */
 963 /* mcspi4 dev_attr */
 964 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
 965         .num_chipselect = 1,
 966 };
 967
 968 static struct omap_hwmod omap54xx_mcspi4_hwmod = {
 969         .name           = "mcspi4",
 970         .class          = &omap54xx_mcspi_hwmod_class,
 971         .clkdm_name     = "l4per_clkdm",
 972         .main_clk       = "func_48m_fclk",
 973         .prcm = {
 974                 .omap4 = {
 975                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
 976                         .context_offs = OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
 977                         .modulemode   = MODULEMODE_SWCTRL,
 978                 },
 979         },
 980         .dev_attr       = &mcspi4_dev_attr,
 981 };
 982
 983 /*
 984  * 'mmc' class
 985  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
 986  */
 987
 988 static struct omap_hwmod_class_sysconfig omap54xx_mmc_sysc = {
 989         .rev_offs       = 0x0000,
 990         .sysc_offs      = 0x0010,
 991         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 992                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 993                            SYSC_HAS_SOFTRESET),
 994         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 995                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 996                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 997         .sysc_fields    = &omap_hwmod_sysc_type2,
 998 };
 999
1000 static struct omap_hwmod_class omap54xx_mmc_hwmod_class = {
1001         .name   = "mmc",
1002         .sysc   = &omap54xx_mmc_sysc,
1003 };
1004
1005 /* mmc1 */
1006 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1007         { .role = "32khz_clk", .clk = "mmc1_32khz_clk" },
1008 };
1009
1010 /* mmc1 dev_attr */
1011 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1012         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1013 };
1014
1015 static struct omap_hwmod omap54xx_mmc1_hwmod = {
1016         .name           = "mmc1",
1017         .class          = &omap54xx_mmc_hwmod_class,
1018         .clkdm_name     = "l3init_clkdm",
1019         .main_clk       = "mmc1_fclk",
1020         .prcm = {
1021                 .omap4 = {
1022                         .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1023                         .context_offs = OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1024                         .modulemode   = MODULEMODE_SWCTRL,
1025                 },
1026         },
1027         .opt_clks       = mmc1_opt_clks,
1028         .opt_clks_cnt   = ARRAY_SIZE(mmc1_opt_clks),
1029         .dev_attr       = &mmc1_dev_attr,
1030 };
1031
1032 /* mmc2 */
1033 static struct omap_hwmod omap54xx_mmc2_hwmod = {
1034         .name           = "mmc2",
1035         .class          = &omap54xx_mmc_hwmod_class,
1036         .clkdm_name     = "l3init_clkdm",
1037         .main_clk       = "mmc2_fclk",
1038         .prcm = {
1039                 .omap4 = {
1040                         .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1041                         .context_offs = OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1042                         .modulemode   = MODULEMODE_SWCTRL,
1043                 },
1044         },
1045 };
1046
1047 /* mmc3 */
1048 static struct omap_hwmod omap54xx_mmc3_hwmod = {
1049         .name           = "mmc3",
1050         .class          = &omap54xx_mmc_hwmod_class,
1051         .clkdm_name     = "l4per_clkdm",
1052         .main_clk       = "func_48m_fclk",
1053         .prcm = {
1054                 .omap4 = {
1055                         .clkctrl_offs = OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1056                         .context_offs = OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1057                         .modulemode   = MODULEMODE_SWCTRL,
1058                 },
1059         },
1060 };
1061
1062 /* mmc4 */
1063 static struct omap_hwmod omap54xx_mmc4_hwmod = {
1064         .name           = "mmc4",
1065         .class          = &omap54xx_mmc_hwmod_class,
1066         .clkdm_name     = "l4per_clkdm",
1067         .main_clk       = "func_48m_fclk",
1068         .prcm = {
1069                 .omap4 = {
1070                         .clkctrl_offs = OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1071                         .context_offs = OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1072                         .modulemode   = MODULEMODE_SWCTRL,
1073                 },
1074         },
1075 };
1076
1077 /* mmc5 */
1078 static struct omap_hwmod omap54xx_mmc5_hwmod = {
1079         .name           = "mmc5",
1080         .class          = &omap54xx_mmc_hwmod_class,
1081         .clkdm_name     = "l4per_clkdm",
1082         .main_clk       = "func_96m_fclk",
1083         .prcm = {
1084                 .omap4 = {
1085                         .clkctrl_offs = OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET,
1086                         .context_offs = OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET,
1087                         .modulemode   = MODULEMODE_SWCTRL,
1088                 },
1089         },
1090 };
1091
1092 /*
1093  * 'mpu' class
1094  * mpu sub-system
1095  */
1096
1097 static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
1098         .name   = "mpu",
1099 };
1100
1101 /* mpu */
1102 static struct omap_hwmod omap54xx_mpu_hwmod = {
1103         .name           = "mpu",
1104         .class          = &omap54xx_mpu_hwmod_class,
1105         .clkdm_name     = "mpu_clkdm",
1106         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1107         .main_clk       = "dpll_mpu_m2_ck",
1108         .prcm = {
1109                 .omap4 = {
1110                         .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1111                         .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
1112                 },
1113         },
1114 };
1115
1116 /*
1117  * 'timer' class
1118  * general purpose timer module with accurate 1ms tick
1119  * This class contains several variants: ['timer_1ms', 'timer']
1120  */
1121
1122 static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = {
1123         .rev_offs       = 0x0000,
1124         .sysc_offs      = 0x0010,
1125         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1126                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1127         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1128                            SIDLE_SMART_WKUP),
1129         .sysc_fields    = &omap_hwmod_sysc_type2,
1130         .clockact       = CLOCKACT_TEST_ICLK,
1131 };
1132
1133 static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = {
1134         .name   = "timer",
1135         .sysc   = &omap54xx_timer_1ms_sysc,
1136 };
1137
1138 static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc = {
1139         .rev_offs       = 0x0000,
1140         .sysc_offs      = 0x0010,
1141         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1142                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1143         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1144                            SIDLE_SMART_WKUP),
1145         .sysc_fields    = &omap_hwmod_sysc_type2,
1146 };
1147
1148 static struct omap_hwmod_class omap54xx_timer_hwmod_class = {
1149         .name   = "timer",
1150         .sysc   = &omap54xx_timer_sysc,
1151 };
1152
1153 /* timer1 */
1154 static struct omap_hwmod omap54xx_timer1_hwmod = {
1155         .name           = "timer1",
1156         .class          = &omap54xx_timer_1ms_hwmod_class,
1157         .clkdm_name     = "wkupaon_clkdm",
1158         .main_clk       = "timer1_gfclk_mux",
1159         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1160         .prcm = {
1161                 .omap4 = {
1162                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1163                         .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1164                         .modulemode   = MODULEMODE_SWCTRL,
1165                 },
1166         },
1167 };
1168
1169 /* timer2 */
1170 static struct omap_hwmod omap54xx_timer2_hwmod = {
1171         .name           = "timer2",
1172         .class          = &omap54xx_timer_1ms_hwmod_class,
1173         .clkdm_name     = "l4per_clkdm",
1174         .main_clk       = "timer2_gfclk_mux",
1175         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1176         .prcm = {
1177                 .omap4 = {
1178                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1179                         .context_offs = OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1180                         .modulemode   = MODULEMODE_SWCTRL,
1181                 },
1182         },
1183 };
1184
1185 /* timer3 */
1186 static struct omap_hwmod omap54xx_timer3_hwmod = {
1187         .name           = "timer3",
1188         .class          = &omap54xx_timer_hwmod_class,
1189         .clkdm_name     = "l4per_clkdm",
1190         .main_clk       = "timer3_gfclk_mux",
1191         .prcm = {
1192                 .omap4 = {
1193                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1194                         .context_offs = OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1195                         .modulemode   = MODULEMODE_SWCTRL,
1196                 },
1197         },
1198 };
1199
1200 /* timer4 */
1201 static struct omap_hwmod omap54xx_timer4_hwmod = {
1202         .name           = "timer4",
1203         .class          = &omap54xx_timer_hwmod_class,
1204         .clkdm_name     = "l4per_clkdm",
1205         .main_clk       = "timer4_gfclk_mux",
1206         .prcm = {
1207                 .omap4 = {
1208                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1209                         .context_offs = OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1210                         .modulemode   = MODULEMODE_SWCTRL,
1211                 },
1212         },
1213 };
1214
1215 /* timer5 */
1216 static struct omap_hwmod omap54xx_timer5_hwmod = {
1217         .name           = "timer5",
1218         .class          = &omap54xx_timer_hwmod_class,
1219         .clkdm_name     = "abe_clkdm",
1220         .main_clk       = "timer5_gfclk_mux",
1221         .prcm = {
1222                 .omap4 = {
1223                         .clkctrl_offs = OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET,
1224                         .context_offs = OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET,
1225                         .modulemode   = MODULEMODE_SWCTRL,
1226                 },
1227         },
1228 };
1229
1230 /* timer6 */
1231 static struct omap_hwmod omap54xx_timer6_hwmod = {
1232         .name           = "timer6",
1233         .class          = &omap54xx_timer_hwmod_class,
1234         .clkdm_name     = "abe_clkdm",
1235         .main_clk       = "timer6_gfclk_mux",
1236         .prcm = {
1237                 .omap4 = {
1238                         .clkctrl_offs = OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET,
1239                         .context_offs = OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET,
1240                         .modulemode   = MODULEMODE_SWCTRL,
1241                 },
1242         },
1243 };
1244
1245 /* timer7 */
1246 static struct omap_hwmod omap54xx_timer7_hwmod = {
1247         .name           = "timer7",
1248         .class          = &omap54xx_timer_hwmod_class,
1249         .clkdm_name     = "abe_clkdm",
1250         .main_clk       = "timer7_gfclk_mux",
1251         .prcm = {
1252                 .omap4 = {
1253                         .clkctrl_offs = OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET,
1254                         .context_offs = OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET,
1255                         .modulemode   = MODULEMODE_SWCTRL,
1256                 },
1257         },
1258 };
1259
1260 /* timer8 */
1261 static struct omap_hwmod omap54xx_timer8_hwmod = {
1262         .name           = "timer8",
1263         .class          = &omap54xx_timer_hwmod_class,
1264         .clkdm_name     = "abe_clkdm",
1265         .main_clk       = "timer8_gfclk_mux",
1266         .prcm = {
1267                 .omap4 = {
1268                         .clkctrl_offs = OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET,
1269                         .context_offs = OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET,
1270                         .modulemode   = MODULEMODE_SWCTRL,
1271                 },
1272         },
1273 };
1274
1275 /* timer9 */
1276 static struct omap_hwmod omap54xx_timer9_hwmod = {
1277         .name           = "timer9",
1278         .class          = &omap54xx_timer_hwmod_class,
1279         .clkdm_name     = "l4per_clkdm",
1280         .main_clk       = "timer9_gfclk_mux",
1281         .prcm = {
1282                 .omap4 = {
1283                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1284                         .context_offs = OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1285                         .modulemode   = MODULEMODE_SWCTRL,
1286                 },
1287         },
1288 };
1289
1290 /* timer10 */
1291 static struct omap_hwmod omap54xx_timer10_hwmod = {
1292         .name           = "timer10",
1293         .class          = &omap54xx_timer_1ms_hwmod_class,
1294         .clkdm_name     = "l4per_clkdm",
1295         .main_clk       = "timer10_gfclk_mux",
1296         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1297         .prcm = {
1298                 .omap4 = {
1299                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1300                         .context_offs = OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1301                         .modulemode   = MODULEMODE_SWCTRL,
1302                 },
1303         },
1304 };
1305
1306 /* timer11 */
1307 static struct omap_hwmod omap54xx_timer11_hwmod = {
1308         .name           = "timer11",
1309         .class          = &omap54xx_timer_hwmod_class,
1310         .clkdm_name     = "l4per_clkdm",
1311         .main_clk       = "timer11_gfclk_mux",
1312         .prcm = {
1313                 .omap4 = {
1314                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1315                         .context_offs = OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1316                         .modulemode   = MODULEMODE_SWCTRL,
1317                 },
1318         },
1319 };
1320
1321 /*
1322  * 'uart' class
1323  * universal asynchronous receiver/transmitter (uart)
1324  */
1325
1326 static struct omap_hwmod_class_sysconfig omap54xx_uart_sysc = {
1327         .rev_offs       = 0x0050,
1328         .sysc_offs      = 0x0054,
1329         .syss_offs      = 0x0058,
1330         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1331                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1332                            SYSS_HAS_RESET_STATUS),
1333         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1334                            SIDLE_SMART_WKUP),
1335         .sysc_fields    = &omap_hwmod_sysc_type1,
1336 };
1337
1338 static struct omap_hwmod_class omap54xx_uart_hwmod_class = {
1339         .name   = "uart",
1340         .sysc   = &omap54xx_uart_sysc,
1341 };
1342
1343 /* uart1 */
1344 static struct omap_hwmod omap54xx_uart1_hwmod = {
1345         .name           = "uart1",
1346         .class          = &omap54xx_uart_hwmod_class,
1347         .clkdm_name     = "l4per_clkdm",
1348         .main_clk       = "func_48m_fclk",
1349         .prcm = {
1350                 .omap4 = {
1351                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
1352                         .context_offs = OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET,
1353                         .modulemode   = MODULEMODE_SWCTRL,
1354                 },
1355         },
1356 };
1357
1358 /* uart2 */
1359 static struct omap_hwmod omap54xx_uart2_hwmod = {
1360         .name           = "uart2",
1361         .class          = &omap54xx_uart_hwmod_class,
1362         .clkdm_name     = "l4per_clkdm",
1363         .main_clk       = "func_48m_fclk",
1364         .prcm = {
1365                 .omap4 = {
1366                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
1367                         .context_offs = OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET,
1368                         .modulemode   = MODULEMODE_SWCTRL,
1369                 },
1370         },
1371 };
1372
1373 /* uart3 */
1374 static struct omap_hwmod omap54xx_uart3_hwmod = {
1375         .name           = "uart3",
1376         .class          = &omap54xx_uart_hwmod_class,
1377         .clkdm_name     = "l4per_clkdm",
1378         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1379         .main_clk       = "func_48m_fclk",
1380         .prcm = {
1381                 .omap4 = {
1382                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
1383                         .context_offs = OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET,
1384                         .modulemode   = MODULEMODE_SWCTRL,
1385                 },
1386         },
1387 };
1388
1389 /* uart4 */
1390 static struct omap_hwmod omap54xx_uart4_hwmod = {
1391         .name           = "uart4",
1392         .class          = &omap54xx_uart_hwmod_class,
1393         .clkdm_name     = "l4per_clkdm",
1394         .main_clk       = "func_48m_fclk",
1395         .prcm = {
1396                 .omap4 = {
1397                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
1398                         .context_offs = OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET,
1399                         .modulemode   = MODULEMODE_SWCTRL,
1400                 },
1401         },
1402 };
1403
1404 /* uart5 */
1405 static struct omap_hwmod omap54xx_uart5_hwmod = {
1406         .name           = "uart5",
1407         .class          = &omap54xx_uart_hwmod_class,
1408         .clkdm_name     = "l4per_clkdm",
1409         .main_clk       = "func_48m_fclk",
1410         .prcm = {
1411                 .omap4 = {
1412                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
1413                         .context_offs = OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET,
1414                         .modulemode   = MODULEMODE_SWCTRL,
1415                 },
1416         },
1417 };
1418
1419 /* uart6 */
1420 static struct omap_hwmod omap54xx_uart6_hwmod = {
1421         .name           = "uart6",
1422         .class          = &omap54xx_uart_hwmod_class,
1423         .clkdm_name     = "l4per_clkdm",
1424         .main_clk       = "func_48m_fclk",
1425         .prcm = {
1426                 .omap4 = {
1427                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET,
1428                         .context_offs = OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET,
1429                         .modulemode   = MODULEMODE_SWCTRL,
1430                 },
1431         },
1432 };
1433
1434 /*
1435  * 'usb_otg_ss' class
1436  * 2.0 super speed (usb_otg_ss) controller
1437  */
1438
1439 static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = {
1440         .rev_offs       = 0x0000,
1441         .sysc_offs      = 0x0010,
1442         .sysc_flags     = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
1443                            SYSC_HAS_SIDLEMODE),
1444         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1445                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1446                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1447         .sysc_fields    = &omap_hwmod_sysc_type2,
1448 };
1449
1450 static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = {
1451         .name   = "usb_otg_ss",
1452         .sysc   = &omap54xx_usb_otg_ss_sysc,
1453 };
1454
1455 /* usb_otg_ss */
1456 static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = {
1457         { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" },
1458 };
1459
1460 static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
1461         .name           = "usb_otg_ss",
1462         .class          = &omap54xx_usb_otg_ss_hwmod_class,
1463         .clkdm_name     = "l3init_clkdm",
1464         .flags          = HWMOD_SWSUP_SIDLE,
1465         .main_clk       = "dpll_core_h13x2_ck",
1466         .prcm = {
1467                 .omap4 = {
1468                         .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET,
1469                         .context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET,
1470                         .modulemode   = MODULEMODE_HWCTRL,
1471                 },
1472         },
1473         .opt_clks       = usb_otg_ss_opt_clks,
1474         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss_opt_clks),
1475 };
1476
1477 /*
1478  * 'wd_timer' class
1479  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1480  * overflow condition
1481  */
1482
1483 static struct omap_hwmod_class_sysconfig omap54xx_wd_timer_sysc = {
1484         .rev_offs       = 0x0000,
1485         .sysc_offs      = 0x0010,
1486         .syss_offs      = 0x0014,
1487         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1488                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1489         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1490                            SIDLE_SMART_WKUP),
1491         .sysc_fields    = &omap_hwmod_sysc_type1,
1492 };
1493
1494 static struct omap_hwmod_class omap54xx_wd_timer_hwmod_class = {
1495         .name           = "wd_timer",
1496         .sysc           = &omap54xx_wd_timer_sysc,
1497         .pre_shutdown   = &omap2_wd_timer_disable,
1498 };
1499
1500 /* wd_timer2 */
1501 static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
1502         .name           = "wd_timer2",
1503         .class          = &omap54xx_wd_timer_hwmod_class,
1504         .clkdm_name     = "wkupaon_clkdm",
1505         .main_clk       = "sys_32k_ck",
1506         .prcm = {
1507                 .omap4 = {
1508                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
1509                         .context_offs = OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
1510                         .modulemode   = MODULEMODE_SWCTRL,
1511                 },
1512         },
1513 };
1514
1515
1516 /*
1517  * Interfaces
1518  */
1519
1520 /* l3_main_1 -> dmm */
1521 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = {
1522         .master         = &omap54xx_l3_main_1_hwmod,
1523         .slave          = &omap54xx_dmm_hwmod,
1524         .clk            = "l3_iclk_div",
1525         .user           = OCP_USER_SDMA,
1526 };
1527
1528 /* l3_main_3 -> l3_instr */
1529 static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
1530         .master         = &omap54xx_l3_main_3_hwmod,
1531         .slave          = &omap54xx_l3_instr_hwmod,
1532         .clk            = "l3_iclk_div",
1533         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1534 };
1535
1536 /* l3_main_2 -> l3_main_1 */
1537 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
1538         .master         = &omap54xx_l3_main_2_hwmod,
1539         .slave          = &omap54xx_l3_main_1_hwmod,
1540         .clk            = "l3_iclk_div",
1541         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1542 };
1543
1544 /* l4_cfg -> l3_main_1 */
1545 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
1546         .master         = &omap54xx_l4_cfg_hwmod,
1547         .slave          = &omap54xx_l3_main_1_hwmod,
1548         .clk            = "l3_iclk_div",
1549         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1550 };
1551
1552 /* mpu -> l3_main_1 */
1553 static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
1554         .master         = &omap54xx_mpu_hwmod,
1555         .slave          = &omap54xx_l3_main_1_hwmod,
1556         .clk            = "l3_iclk_div",
1557         .user           = OCP_USER_MPU,
1558 };
1559
1560 /* l3_main_1 -> l3_main_2 */
1561 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
1562         .master         = &omap54xx_l3_main_1_hwmod,
1563         .slave          = &omap54xx_l3_main_2_hwmod,
1564         .clk            = "l3_iclk_div",
1565         .user           = OCP_USER_MPU,
1566 };
1567
1568 /* l4_cfg -> l3_main_2 */
1569 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
1570         .master         = &omap54xx_l4_cfg_hwmod,
1571         .slave          = &omap54xx_l3_main_2_hwmod,
1572         .clk            = "l3_iclk_div",
1573         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1574 };
1575
1576 /* l3_main_1 -> l3_main_3 */
1577 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
1578         .master         = &omap54xx_l3_main_1_hwmod,
1579         .slave          = &omap54xx_l3_main_3_hwmod,
1580         .clk            = "l3_iclk_div",
1581         .user           = OCP_USER_MPU,
1582 };
1583
1584 /* l3_main_2 -> l3_main_3 */
1585 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
1586         .master         = &omap54xx_l3_main_2_hwmod,
1587         .slave          = &omap54xx_l3_main_3_hwmod,
1588         .clk            = "l3_iclk_div",
1589         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1590 };
1591
1592 /* l4_cfg -> l3_main_3 */
1593 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
1594         .master         = &omap54xx_l4_cfg_hwmod,
1595         .slave          = &omap54xx_l3_main_3_hwmod,
1596         .clk            = "l3_iclk_div",
1597         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1598 };
1599
1600 /* l3_main_1 -> l4_abe */
1601 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = {
1602         .master         = &omap54xx_l3_main_1_hwmod,
1603         .slave          = &omap54xx_l4_abe_hwmod,
1604         .clk            = "abe_iclk",
1605         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1606 };
1607
1608 /* mpu -> l4_abe */
1609 static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = {
1610         .master         = &omap54xx_mpu_hwmod,
1611         .slave          = &omap54xx_l4_abe_hwmod,
1612         .clk            = "abe_iclk",
1613         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1614 };
1615
1616 /* l3_main_1 -> l4_cfg */
1617 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
1618         .master         = &omap54xx_l3_main_1_hwmod,
1619         .slave          = &omap54xx_l4_cfg_hwmod,
1620         .clk            = "l4_root_clk_div",
1621         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1622 };
1623
1624 /* l3_main_2 -> l4_per */
1625 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
1626         .master         = &omap54xx_l3_main_2_hwmod,
1627         .slave          = &omap54xx_l4_per_hwmod,
1628         .clk            = "l4_root_clk_div",
1629         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1630 };
1631
1632 /* l3_main_1 -> l4_wkup */
1633 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
1634         .master         = &omap54xx_l3_main_1_hwmod,
1635         .slave          = &omap54xx_l4_wkup_hwmod,
1636         .clk            = "wkupaon_iclk_mux",
1637         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1638 };
1639
1640 /* mpu -> mpu_private */
1641 static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
1642         .master         = &omap54xx_mpu_hwmod,
1643         .slave          = &omap54xx_mpu_private_hwmod,
1644         .clk            = "l3_iclk_div",
1645         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1646 };
1647
1648 /* l4_wkup -> counter_32k */
1649 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = {
1650         .master         = &omap54xx_l4_wkup_hwmod,
1651         .slave          = &omap54xx_counter_32k_hwmod,
1652         .clk            = "wkupaon_iclk_mux",
1653         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1654 };
1655
1656 static struct omap_hwmod_addr_space omap54xx_dma_system_addrs[] = {
1657         {
1658                 .pa_start       = 0x4a056000,
1659                 .pa_end         = 0x4a056fff,
1660                 .flags          = ADDR_TYPE_RT
1661         },
1662         { }
1663 };
1664
1665 /* l4_cfg -> dma_system */
1666 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system = {
1667         .master         = &omap54xx_l4_cfg_hwmod,
1668         .slave          = &omap54xx_dma_system_hwmod,
1669         .clk            = "l4_root_clk_div",
1670         .addr           = omap54xx_dma_system_addrs,
1671         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1672 };
1673
1674 /* l4_abe -> dmic */
1675 static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = {
1676         .master         = &omap54xx_l4_abe_hwmod,
1677         .slave          = &omap54xx_dmic_hwmod,
1678         .clk            = "abe_iclk",
1679         .user           = OCP_USER_MPU,
1680 };
1681
1682 /* mpu -> emif1 */
1683 static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
1684         .master         = &omap54xx_mpu_hwmod,
1685         .slave          = &omap54xx_emif1_hwmod,
1686         .clk            = "dpll_core_h11x2_ck",
1687         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1688 };
1689
1690 /* mpu -> emif2 */
1691 static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
1692         .master         = &omap54xx_mpu_hwmod,
1693         .slave          = &omap54xx_emif2_hwmod,
1694         .clk            = "dpll_core_h11x2_ck",
1695         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1696 };
1697
1698 /* l4_wkup -> gpio1 */
1699 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__gpio1 = {
1700         .master         = &omap54xx_l4_wkup_hwmod,
1701         .slave          = &omap54xx_gpio1_hwmod,
1702         .clk            = "wkupaon_iclk_mux",
1703         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1704 };
1705
1706 /* l4_per -> gpio2 */
1707 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio2 = {
1708         .master         = &omap54xx_l4_per_hwmod,
1709         .slave          = &omap54xx_gpio2_hwmod,
1710         .clk            = "l4_root_clk_div",
1711         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1712 };
1713
1714 /* l4_per -> gpio3 */
1715 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio3 = {
1716         .master         = &omap54xx_l4_per_hwmod,
1717         .slave          = &omap54xx_gpio3_hwmod,
1718         .clk            = "l4_root_clk_div",
1719         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1720 };
1721
1722 /* l4_per -> gpio4 */
1723 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio4 = {
1724         .master         = &omap54xx_l4_per_hwmod,
1725         .slave          = &omap54xx_gpio4_hwmod,
1726         .clk            = "l4_root_clk_div",
1727         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1728 };
1729
1730 /* l4_per -> gpio5 */
1731 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio5 = {
1732         .master         = &omap54xx_l4_per_hwmod,
1733         .slave          = &omap54xx_gpio5_hwmod,
1734         .clk            = "l4_root_clk_div",
1735         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1736 };
1737
1738 /* l4_per -> gpio6 */
1739 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio6 = {
1740         .master         = &omap54xx_l4_per_hwmod,
1741         .slave          = &omap54xx_gpio6_hwmod,
1742         .clk            = "l4_root_clk_div",
1743         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1744 };
1745
1746 /* l4_per -> gpio7 */
1747 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio7 = {
1748         .master         = &omap54xx_l4_per_hwmod,
1749         .slave          = &omap54xx_gpio7_hwmod,
1750         .clk            = "l4_root_clk_div",
1751         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1752 };
1753
1754 /* l4_per -> gpio8 */
1755 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio8 = {
1756         .master         = &omap54xx_l4_per_hwmod,
1757         .slave          = &omap54xx_gpio8_hwmod,
1758         .clk            = "l4_root_clk_div",
1759         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1760 };
1761
1762 /* l4_per -> i2c1 */
1763 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c1 = {
1764         .master         = &omap54xx_l4_per_hwmod,
1765         .slave          = &omap54xx_i2c1_hwmod,
1766         .clk            = "l4_root_clk_div",
1767         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1768 };
1769
1770 /* l4_per -> i2c2 */
1771 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c2 = {
1772         .master         = &omap54xx_l4_per_hwmod,
1773         .slave          = &omap54xx_i2c2_hwmod,
1774         .clk            = "l4_root_clk_div",
1775         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1776 };
1777
1778 /* l4_per -> i2c3 */
1779 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c3 = {
1780         .master         = &omap54xx_l4_per_hwmod,
1781         .slave          = &omap54xx_i2c3_hwmod,
1782         .clk            = "l4_root_clk_div",
1783         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1784 };
1785
1786 /* l4_per -> i2c4 */
1787 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c4 = {
1788         .master         = &omap54xx_l4_per_hwmod,
1789         .slave          = &omap54xx_i2c4_hwmod,
1790         .clk            = "l4_root_clk_div",
1791         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1792 };
1793
1794 /* l4_per -> i2c5 */
1795 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c5 = {
1796         .master         = &omap54xx_l4_per_hwmod,
1797         .slave          = &omap54xx_i2c5_hwmod,
1798         .clk            = "l4_root_clk_div",
1799         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1800 };
1801
1802 /* l4_wkup -> kbd */
1803 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = {
1804         .master         = &omap54xx_l4_wkup_hwmod,
1805         .slave          = &omap54xx_kbd_hwmod,
1806         .clk            = "wkupaon_iclk_mux",
1807         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1808 };
1809
1810 /* l4_abe -> mcbsp1 */
1811 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = {
1812         .master         = &omap54xx_l4_abe_hwmod,
1813         .slave          = &omap54xx_mcbsp1_hwmod,
1814         .clk            = "abe_iclk",
1815         .user           = OCP_USER_MPU,
1816 };
1817
1818 /* l4_abe -> mcbsp2 */
1819 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2 = {
1820         .master         = &omap54xx_l4_abe_hwmod,
1821         .slave          = &omap54xx_mcbsp2_hwmod,
1822         .clk            = "abe_iclk",
1823         .user           = OCP_USER_MPU,
1824 };
1825
1826 /* l4_abe -> mcbsp3 */
1827 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3 = {
1828         .master         = &omap54xx_l4_abe_hwmod,
1829         .slave          = &omap54xx_mcbsp3_hwmod,
1830         .clk            = "abe_iclk",
1831         .user           = OCP_USER_MPU,
1832 };
1833
1834 /* l4_abe -> mcpdm */
1835 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm = {
1836         .master         = &omap54xx_l4_abe_hwmod,
1837         .slave          = &omap54xx_mcpdm_hwmod,
1838         .clk            = "abe_iclk",
1839         .user           = OCP_USER_MPU,
1840 };
1841
1842 /* l4_per -> mcspi1 */
1843 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi1 = {
1844         .master         = &omap54xx_l4_per_hwmod,
1845         .slave          = &omap54xx_mcspi1_hwmod,
1846         .clk            = "l4_root_clk_div",
1847         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1848 };
1849
1850 /* l4_per -> mcspi2 */
1851 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi2 = {
1852         .master         = &omap54xx_l4_per_hwmod,
1853         .slave          = &omap54xx_mcspi2_hwmod,
1854         .clk            = "l4_root_clk_div",
1855         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1856 };
1857
1858 /* l4_per -> mcspi3 */
1859 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi3 = {
1860         .master         = &omap54xx_l4_per_hwmod,
1861         .slave          = &omap54xx_mcspi3_hwmod,
1862         .clk            = "l4_root_clk_div",
1863         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1864 };
1865
1866 /* l4_per -> mcspi4 */
1867 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4 = {
1868         .master         = &omap54xx_l4_per_hwmod,
1869         .slave          = &omap54xx_mcspi4_hwmod,
1870         .clk            = "l4_root_clk_div",
1871         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1872 };
1873
1874 /* l4_per -> mmc1 */
1875 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc1 = {
1876         .master         = &omap54xx_l4_per_hwmod,
1877         .slave          = &omap54xx_mmc1_hwmod,
1878         .clk            = "l3_iclk_div",
1879         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1880 };
1881
1882 /* l4_per -> mmc2 */
1883 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc2 = {
1884         .master         = &omap54xx_l4_per_hwmod,
1885         .slave          = &omap54xx_mmc2_hwmod,
1886         .clk            = "l3_iclk_div",
1887         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1888 };
1889
1890 /* l4_per -> mmc3 */
1891 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc3 = {
1892         .master         = &omap54xx_l4_per_hwmod,
1893         .slave          = &omap54xx_mmc3_hwmod,
1894         .clk            = "l4_root_clk_div",
1895         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1896 };
1897
1898 /* l4_per -> mmc4 */
1899 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc4 = {
1900         .master         = &omap54xx_l4_per_hwmod,
1901         .slave          = &omap54xx_mmc4_hwmod,
1902         .clk            = "l4_root_clk_div",
1903         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1904 };
1905
1906 /* l4_per -> mmc5 */
1907 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc5 = {
1908         .master         = &omap54xx_l4_per_hwmod,
1909         .slave          = &omap54xx_mmc5_hwmod,
1910         .clk            = "l4_root_clk_div",
1911         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1912 };
1913
1914 /* l4_cfg -> mpu */
1915 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
1916         .master         = &omap54xx_l4_cfg_hwmod,
1917         .slave          = &omap54xx_mpu_hwmod,
1918         .clk            = "l4_root_clk_div",
1919         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1920 };
1921
1922 /* l4_wkup -> timer1 */
1923 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
1924         .master         = &omap54xx_l4_wkup_hwmod,
1925         .slave          = &omap54xx_timer1_hwmod,
1926         .clk            = "wkupaon_iclk_mux",
1927         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1928 };
1929
1930 /* l4_per -> timer2 */
1931 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2 = {
1932         .master         = &omap54xx_l4_per_hwmod,
1933         .slave          = &omap54xx_timer2_hwmod,
1934         .clk            = "l4_root_clk_div",
1935         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1936 };
1937
1938 /* l4_per -> timer3 */
1939 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3 = {
1940         .master         = &omap54xx_l4_per_hwmod,
1941         .slave          = &omap54xx_timer3_hwmod,
1942         .clk            = "l4_root_clk_div",
1943         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1944 };
1945
1946 /* l4_per -> timer4 */
1947 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4 = {
1948         .master         = &omap54xx_l4_per_hwmod,
1949         .slave          = &omap54xx_timer4_hwmod,
1950         .clk            = "l4_root_clk_div",
1951         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1952 };
1953
1954 /* l4_abe -> timer5 */
1955 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5 = {
1956         .master         = &omap54xx_l4_abe_hwmod,
1957         .slave          = &omap54xx_timer5_hwmod,
1958         .clk            = "abe_iclk",
1959         .user           = OCP_USER_MPU,
1960 };
1961
1962 /* l4_abe -> timer6 */
1963 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6 = {
1964         .master         = &omap54xx_l4_abe_hwmod,
1965         .slave          = &omap54xx_timer6_hwmod,
1966         .clk            = "abe_iclk",
1967         .user           = OCP_USER_MPU,
1968 };
1969
1970 /* l4_abe -> timer7 */
1971 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7 = {
1972         .master         = &omap54xx_l4_abe_hwmod,
1973         .slave          = &omap54xx_timer7_hwmod,
1974         .clk            = "abe_iclk",
1975         .user           = OCP_USER_MPU,
1976 };
1977
1978 /* l4_abe -> timer8 */
1979 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8 = {
1980         .master         = &omap54xx_l4_abe_hwmod,
1981         .slave          = &omap54xx_timer8_hwmod,
1982         .clk            = "abe_iclk",
1983         .user           = OCP_USER_MPU,
1984 };
1985
1986 /* l4_per -> timer9 */
1987 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9 = {
1988         .master         = &omap54xx_l4_per_hwmod,
1989         .slave          = &omap54xx_timer9_hwmod,
1990         .clk            = "l4_root_clk_div",
1991         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1992 };
1993
1994 /* l4_per -> timer10 */
1995 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10 = {
1996         .master         = &omap54xx_l4_per_hwmod,
1997         .slave          = &omap54xx_timer10_hwmod,
1998         .clk            = "l4_root_clk_div",
1999         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2000 };
2001
2002 /* l4_per -> timer11 */
2003 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11 = {
2004         .master         = &omap54xx_l4_per_hwmod,
2005         .slave          = &omap54xx_timer11_hwmod,
2006         .clk            = "l4_root_clk_div",
2007         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2008 };
2009
2010 /* l4_per -> uart1 */
2011 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart1 = {
2012         .master         = &omap54xx_l4_per_hwmod,
2013         .slave          = &omap54xx_uart1_hwmod,
2014         .clk            = "l4_root_clk_div",
2015         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2016 };
2017
2018 /* l4_per -> uart2 */
2019 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart2 = {
2020         .master         = &omap54xx_l4_per_hwmod,
2021         .slave          = &omap54xx_uart2_hwmod,
2022         .clk            = "l4_root_clk_div",
2023         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2024 };
2025
2026 /* l4_per -> uart3 */
2027 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart3 = {
2028         .master         = &omap54xx_l4_per_hwmod,
2029         .slave          = &omap54xx_uart3_hwmod,
2030         .clk            = "l4_root_clk_div",
2031         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2032 };
2033
2034 /* l4_per -> uart4 */
2035 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart4 = {
2036         .master         = &omap54xx_l4_per_hwmod,
2037         .slave          = &omap54xx_uart4_hwmod,
2038         .clk            = "l4_root_clk_div",
2039         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2040 };
2041
2042 /* l4_per -> uart5 */
2043 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart5 = {
2044         .master         = &omap54xx_l4_per_hwmod,
2045         .slave          = &omap54xx_uart5_hwmod,
2046         .clk            = "l4_root_clk_div",
2047         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2048 };
2049
2050 /* l4_per -> uart6 */
2051 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart6 = {
2052         .master         = &omap54xx_l4_per_hwmod,
2053         .slave          = &omap54xx_uart6_hwmod,
2054         .clk            = "l4_root_clk_div",
2055         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2056 };
2057
2058 /* l4_cfg -> usb_otg_ss */
2059 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {
2060         .master         = &omap54xx_l4_cfg_hwmod,
2061         .slave          = &omap54xx_usb_otg_ss_hwmod,
2062         .clk            = "dpll_core_h13x2_ck",
2063         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2064 };
2065
2066 /* l4_wkup -> wd_timer2 */
2067 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__wd_timer2 = {
2068         .master         = &omap54xx_l4_wkup_hwmod,
2069         .slave          = &omap54xx_wd_timer2_hwmod,
2070         .clk            = "wkupaon_iclk_mux",
2071         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2072 };
2073
2074 static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
2075         &omap54xx_l3_main_1__dmm,
2076         &omap54xx_l3_main_3__l3_instr,
2077         &omap54xx_l3_main_2__l3_main_1,
2078         &omap54xx_l4_cfg__l3_main_1,
2079         &omap54xx_mpu__l3_main_1,
2080         &omap54xx_l3_main_1__l3_main_2,
2081         &omap54xx_l4_cfg__l3_main_2,
2082         &omap54xx_l3_main_1__l3_main_3,
2083         &omap54xx_l3_main_2__l3_main_3,
2084         &omap54xx_l4_cfg__l3_main_3,
2085         &omap54xx_l3_main_1__l4_abe,
2086         &omap54xx_mpu__l4_abe,
2087         &omap54xx_l3_main_1__l4_cfg,
2088         &omap54xx_l3_main_2__l4_per,
2089         &omap54xx_l3_main_1__l4_wkup,
2090         &omap54xx_mpu__mpu_private,
2091         &omap54xx_l4_wkup__counter_32k,
2092         &omap54xx_l4_cfg__dma_system,
2093         &omap54xx_l4_abe__dmic,
2094         &omap54xx_mpu__emif1,
2095         &omap54xx_mpu__emif2,
2096         &omap54xx_l4_wkup__gpio1,
2097         &omap54xx_l4_per__gpio2,
2098         &omap54xx_l4_per__gpio3,
2099         &omap54xx_l4_per__gpio4,
2100         &omap54xx_l4_per__gpio5,
2101         &omap54xx_l4_per__gpio6,
2102         &omap54xx_l4_per__gpio7,
2103         &omap54xx_l4_per__gpio8,
2104         &omap54xx_l4_per__i2c1,
2105         &omap54xx_l4_per__i2c2,
2106         &omap54xx_l4_per__i2c3,
2107         &omap54xx_l4_per__i2c4,
2108         &omap54xx_l4_per__i2c5,
2109         &omap54xx_l4_wkup__kbd,
2110         &omap54xx_l4_abe__mcbsp1,
2111         &omap54xx_l4_abe__mcbsp2,
2112         &omap54xx_l4_abe__mcbsp3,
2113         &omap54xx_l4_abe__mcpdm,
2114         &omap54xx_l4_per__mcspi1,
2115         &omap54xx_l4_per__mcspi2,
2116         &omap54xx_l4_per__mcspi3,
2117         &omap54xx_l4_per__mcspi4,
2118         &omap54xx_l4_per__mmc1,
2119         &omap54xx_l4_per__mmc2,
2120         &omap54xx_l4_per__mmc3,
2121         &omap54xx_l4_per__mmc4,
2122         &omap54xx_l4_per__mmc5,
2123         &omap54xx_l4_cfg__mpu,
2124         &omap54xx_l4_wkup__timer1,
2125         &omap54xx_l4_per__timer2,
2126         &omap54xx_l4_per__timer3,
2127         &omap54xx_l4_per__timer4,
2128         &omap54xx_l4_abe__timer5,
2129         &omap54xx_l4_abe__timer6,
2130         &omap54xx_l4_abe__timer7,
2131         &omap54xx_l4_abe__timer8,
2132         &omap54xx_l4_per__timer9,
2133         &omap54xx_l4_per__timer10,
2134         &omap54xx_l4_per__timer11,
2135         &omap54xx_l4_per__uart1,
2136         &omap54xx_l4_per__uart2,
2137         &omap54xx_l4_per__uart3,
2138         &omap54xx_l4_per__uart4,
2139         &omap54xx_l4_per__uart5,
2140         &omap54xx_l4_per__uart6,
2141         &omap54xx_l4_cfg__usb_otg_ss,
2142         &omap54xx_l4_wkup__wd_timer2,
2143         NULL,
2144 };
2145
2146 int __init omap54xx_hwmod_init(void)
2147 {
2148         omap_hwmod_init();
2149         return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);
2150 }