2 * Hardware modules present on the DRA7xx chips
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
21 #include <linux/platform_data/gpio-omap.h>
22 #include <linux/platform_data/hsmmc-omap.h>
23 #include <linux/power/smartreflex.h>
24 #include <linux/i2c-omap.h>
26 #include <linux/omap-dma.h>
27 #include <linux/platform_data/spi-omap2-mcspi.h>
28 #include <linux/platform_data/asoc-ti-mcbsp.h>
29 #include <plat/dmtimer.h>
31 #include "omap_hwmod.h"
32 #include "omap_hwmod_common_data.h"
40 /* Base offset for all DRA7XX interrupts external to MPUSS */
41 #define DRA7XX_IRQ_GIC_START 32
43 /* Base offset for all DRA7XX dma requests */
44 #define DRA7XX_DMA_REQ_START 1
55 static struct omap_hwmod_class dra7xx_dmm_hwmod_class
= {
60 static struct omap_hwmod dra7xx_dmm_hwmod
= {
62 .class = &dra7xx_dmm_hwmod_class
,
63 .clkdm_name
= "emif_clkdm",
66 .clkctrl_offs
= DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET
,
67 .context_offs
= DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET
,
74 * instance(s): l3_instr, l3_main_1, l3_main_2
76 static struct omap_hwmod_class dra7xx_l3_hwmod_class
= {
81 static struct omap_hwmod dra7xx_l3_instr_hwmod
= {
83 .class = &dra7xx_l3_hwmod_class
,
84 .clkdm_name
= "l3instr_clkdm",
87 .clkctrl_offs
= DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET
,
88 .context_offs
= DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET
,
89 .modulemode
= MODULEMODE_HWCTRL
,
95 static struct omap_hwmod dra7xx_l3_main_1_hwmod
= {
97 .class = &dra7xx_l3_hwmod_class
,
98 .clkdm_name
= "l3main1_clkdm",
101 .clkctrl_offs
= DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET
,
102 .context_offs
= DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET
,
108 static struct omap_hwmod dra7xx_l3_main_2_hwmod
= {
110 .class = &dra7xx_l3_hwmod_class
,
111 .clkdm_name
= "l3instr_clkdm",
114 .clkctrl_offs
= DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET
,
115 .context_offs
= DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET
,
116 .modulemode
= MODULEMODE_HWCTRL
,
123 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
125 static struct omap_hwmod_class dra7xx_l4_hwmod_class
= {
130 static struct omap_hwmod dra7xx_l4_cfg_hwmod
= {
132 .class = &dra7xx_l4_hwmod_class
,
133 .clkdm_name
= "l4cfg_clkdm",
136 .clkctrl_offs
= DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET
,
137 .context_offs
= DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET
,
143 static struct omap_hwmod dra7xx_l4_per1_hwmod
= {
145 .class = &dra7xx_l4_hwmod_class
,
146 .clkdm_name
= "l4per_clkdm",
149 .clkctrl_offs
= DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET
,
150 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
156 static struct omap_hwmod dra7xx_l4_per2_hwmod
= {
158 .class = &dra7xx_l4_hwmod_class
,
159 .clkdm_name
= "l4per2_clkdm",
162 .clkctrl_offs
= DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET
,
163 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
169 static struct omap_hwmod dra7xx_l4_per3_hwmod
= {
171 .class = &dra7xx_l4_hwmod_class
,
172 .clkdm_name
= "l4per3_clkdm",
175 .clkctrl_offs
= DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET
,
176 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
182 static struct omap_hwmod dra7xx_l4_wkup_hwmod
= {
184 .class = &dra7xx_l4_hwmod_class
,
185 .clkdm_name
= "wkupaon_clkdm",
188 .clkctrl_offs
= DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET
,
189 .context_offs
= DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET
,
199 static struct omap_hwmod_class dra7xx_atl_hwmod_class
= {
204 static struct omap_hwmod dra7xx_atl_hwmod
= {
206 .class = &dra7xx_atl_hwmod_class
,
207 .clkdm_name
= "atl_clkdm",
208 .main_clk
= "atl_gfclk_mux",
211 .clkctrl_offs
= DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET
,
212 .context_offs
= DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET
,
213 .modulemode
= MODULEMODE_SWCTRL
,
223 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class
= {
228 static struct omap_hwmod dra7xx_bb2d_hwmod
= {
230 .class = &dra7xx_bb2d_hwmod_class
,
231 .clkdm_name
= "dss_clkdm",
232 .main_clk
= "dpll_core_h24x2_ck",
235 .clkctrl_offs
= DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET
,
236 .context_offs
= DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET
,
237 .modulemode
= MODULEMODE_SWCTRL
,
247 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc
= {
250 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
251 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
253 .sysc_fields
= &omap_hwmod_sysc_type1
,
256 static struct omap_hwmod_class dra7xx_counter_hwmod_class
= {
258 .sysc
= &dra7xx_counter_sysc
,
262 static struct omap_hwmod dra7xx_counter_32k_hwmod
= {
263 .name
= "counter_32k",
264 .class = &dra7xx_counter_hwmod_class
,
265 .clkdm_name
= "wkupaon_clkdm",
266 .flags
= HWMOD_SWSUP_SIDLE
,
267 .main_clk
= "wkupaon_iclk_mux",
270 .clkctrl_offs
= DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET
,
271 .context_offs
= DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET
,
277 * 'ctrl_module' class
281 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class
= {
282 .name
= "ctrl_module",
285 /* ctrl_module_wkup */
286 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod
= {
287 .name
= "ctrl_module_wkup",
288 .class = &dra7xx_ctrl_module_hwmod_class
,
289 .clkdm_name
= "wkupaon_clkdm",
292 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
299 * cpsw/gmac sub system
301 static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc
= {
305 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_MIDLEMODE
|
306 SYSS_HAS_RESET_STATUS
),
307 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| MSTANDBY_FORCE
|
309 .sysc_fields
= &omap_hwmod_sysc_type3
,
312 static struct omap_hwmod_class dra7xx_gmac_hwmod_class
= {
314 .sysc
= &dra7xx_gmac_sysc
,
317 static struct omap_hwmod dra7xx_gmac_hwmod
= {
319 .class = &dra7xx_gmac_hwmod_class
,
320 .clkdm_name
= "gmac_clkdm",
321 .flags
= (HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
),
322 .main_clk
= "dpll_gmac_ck",
326 .clkctrl_offs
= DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET
,
327 .context_offs
= DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET
,
328 .modulemode
= MODULEMODE_SWCTRL
,
336 static struct omap_hwmod_class dra7xx_mdio_hwmod_class
= {
337 .name
= "davinci_mdio",
340 static struct omap_hwmod dra7xx_mdio_hwmod
= {
341 .name
= "davinci_mdio",
342 .class = &dra7xx_mdio_hwmod_class
,
343 .clkdm_name
= "gmac_clkdm",
344 .main_clk
= "dpll_gmac_ck",
352 static struct omap_hwmod_class dra7xx_dcan_hwmod_class
= {
357 static struct omap_hwmod dra7xx_dcan1_hwmod
= {
359 .class = &dra7xx_dcan_hwmod_class
,
360 .clkdm_name
= "wkupaon_clkdm",
361 .main_clk
= "dcan1_sys_clk_mux",
364 .clkctrl_offs
= DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET
,
365 .context_offs
= DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET
,
366 .modulemode
= MODULEMODE_SWCTRL
,
372 static struct omap_hwmod dra7xx_dcan2_hwmod
= {
374 .class = &dra7xx_dcan_hwmod_class
,
375 .clkdm_name
= "l4per2_clkdm",
376 .main_clk
= "sys_clkin1",
379 .clkctrl_offs
= DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET
,
380 .context_offs
= DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET
,
381 .modulemode
= MODULEMODE_SWCTRL
,
391 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc
= {
395 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
396 SYSC_HAS_EMUFREE
| SYSC_HAS_MIDLEMODE
|
397 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
398 SYSS_HAS_RESET_STATUS
),
399 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
400 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
401 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
402 .sysc_fields
= &omap_hwmod_sysc_type1
,
405 static struct omap_hwmod_class dra7xx_dma_hwmod_class
= {
407 .sysc
= &dra7xx_dma_sysc
,
411 static struct omap_dma_dev_attr dma_dev_attr
= {
412 .dev_caps
= RESERVE_CHANNEL
| DMA_LINKED_LCH
| GLOBAL_PRIORITY
|
413 IS_CSSA_32
| IS_CDSA_32
| IS_RW_PRIORITY
,
418 static struct omap_hwmod dra7xx_dma_system_hwmod
= {
419 .name
= "dma_system",
420 .class = &dra7xx_dma_hwmod_class
,
421 .clkdm_name
= "dma_clkdm",
422 .main_clk
= "l3_iclk_div",
425 .clkctrl_offs
= DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET
,
426 .context_offs
= DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET
,
429 .dev_attr
= &dma_dev_attr
,
436 static struct omap_hwmod_class dra7xx_tpcc_hwmod_class
= {
440 static struct omap_hwmod dra7xx_tpcc_hwmod
= {
442 .class = &dra7xx_tpcc_hwmod_class
,
443 .clkdm_name
= "l3main1_clkdm",
444 .main_clk
= "l3_iclk_div",
447 .clkctrl_offs
= DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET
,
448 .context_offs
= DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET
,
457 static struct omap_hwmod_class dra7xx_tptc_hwmod_class
= {
462 static struct omap_hwmod dra7xx_tptc0_hwmod
= {
464 .class = &dra7xx_tptc_hwmod_class
,
465 .clkdm_name
= "l3main1_clkdm",
466 .flags
= HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
,
467 .main_clk
= "l3_iclk_div",
470 .clkctrl_offs
= DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET
,
471 .context_offs
= DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET
,
472 .modulemode
= MODULEMODE_HWCTRL
,
478 static struct omap_hwmod dra7xx_tptc1_hwmod
= {
480 .class = &dra7xx_tptc_hwmod_class
,
481 .clkdm_name
= "l3main1_clkdm",
482 .flags
= HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
,
483 .main_clk
= "l3_iclk_div",
486 .clkctrl_offs
= DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET
,
487 .context_offs
= DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET
,
488 .modulemode
= MODULEMODE_HWCTRL
,
498 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc
= {
501 .sysc_flags
= SYSS_HAS_RESET_STATUS
,
504 static struct omap_hwmod_class dra7xx_dss_hwmod_class
= {
506 .sysc
= &dra7xx_dss_sysc
,
507 .reset
= omap_dss_reset
,
511 static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs
[] = {
512 { .dma_req
= 75 + DRA7XX_DMA_REQ_START
},
516 static struct omap_hwmod_opt_clk dss_opt_clks
[] = {
517 { .role
= "dss_clk", .clk
= "dss_dss_clk" },
518 { .role
= "hdmi_phy_clk", .clk
= "dss_48mhz_clk" },
519 { .role
= "32khz_clk", .clk
= "dss_32khz_clk" },
520 { .role
= "video2_clk", .clk
= "dss_video2_clk" },
521 { .role
= "video1_clk", .clk
= "dss_video1_clk" },
522 { .role
= "hdmi_clk", .clk
= "dss_hdmi_clk" },
523 { .role
= "hdcp_clk", .clk
= "dss_deshdcp_clk" },
526 static struct omap_hwmod dra7xx_dss_hwmod
= {
528 .class = &dra7xx_dss_hwmod_class
,
529 .clkdm_name
= "dss_clkdm",
530 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
531 .sdma_reqs
= dra7xx_dss_sdma_reqs
,
532 .main_clk
= "dss_dss_clk",
535 .clkctrl_offs
= DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET
,
536 .context_offs
= DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET
,
537 .modulemode
= MODULEMODE_SWCTRL
,
540 .opt_clks
= dss_opt_clks
,
541 .opt_clks_cnt
= ARRAY_SIZE(dss_opt_clks
),
549 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc
= {
553 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
554 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_MIDLEMODE
|
555 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
556 SYSS_HAS_RESET_STATUS
),
557 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
558 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
559 .sysc_fields
= &omap_hwmod_sysc_type1
,
562 static struct omap_hwmod_class dra7xx_dispc_hwmod_class
= {
564 .sysc
= &dra7xx_dispc_sysc
,
568 /* dss_dispc dev_attr */
569 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr
= {
570 .has_framedonetv_irq
= 1,
574 static struct omap_hwmod dra7xx_dss_dispc_hwmod
= {
576 .class = &dra7xx_dispc_hwmod_class
,
577 .clkdm_name
= "dss_clkdm",
578 .main_clk
= "dss_dss_clk",
581 .clkctrl_offs
= DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET
,
582 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
585 .dev_attr
= &dss_dispc_dev_attr
,
586 .parent_hwmod
= &dra7xx_dss_hwmod
,
594 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc
= {
597 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
599 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
601 .sysc_fields
= &omap_hwmod_sysc_type2
,
604 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class
= {
606 .sysc
= &dra7xx_hdmi_sysc
,
611 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks
[] = {
612 { .role
= "sys_clk", .clk
= "dss_hdmi_clk" },
615 static struct omap_hwmod dra7xx_dss_hdmi_hwmod
= {
617 .class = &dra7xx_hdmi_hwmod_class
,
618 .clkdm_name
= "dss_clkdm",
619 .main_clk
= "dss_48mhz_clk",
622 .clkctrl_offs
= DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET
,
623 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
626 .opt_clks
= dss_hdmi_opt_clks
,
627 .opt_clks_cnt
= ARRAY_SIZE(dss_hdmi_opt_clks
),
628 .parent_hwmod
= &dra7xx_dss_hwmod
,
636 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc
= {
640 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
641 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
642 SYSS_HAS_RESET_STATUS
),
643 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
645 .sysc_fields
= &omap_hwmod_sysc_type1
,
648 static struct omap_hwmod_class dra7xx_elm_hwmod_class
= {
650 .sysc
= &dra7xx_elm_sysc
,
655 static struct omap_hwmod dra7xx_elm_hwmod
= {
657 .class = &dra7xx_elm_hwmod_class
,
658 .clkdm_name
= "l4per_clkdm",
659 .main_clk
= "l3_iclk_div",
662 .clkctrl_offs
= DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET
,
663 .context_offs
= DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET
,
673 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc
= {
677 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
678 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
679 SYSS_HAS_RESET_STATUS
),
680 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
682 .sysc_fields
= &omap_hwmod_sysc_type1
,
685 static struct omap_hwmod_class dra7xx_gpio_hwmod_class
= {
687 .sysc
= &dra7xx_gpio_sysc
,
692 static struct omap_gpio_dev_attr gpio_dev_attr
= {
698 static struct omap_hwmod_opt_clk gpio1_opt_clks
[] = {
699 { .role
= "dbclk", .clk
= "gpio1_dbclk" },
702 static struct omap_hwmod dra7xx_gpio1_hwmod
= {
704 .class = &dra7xx_gpio_hwmod_class
,
705 .clkdm_name
= "wkupaon_clkdm",
706 .main_clk
= "wkupaon_iclk_mux",
709 .clkctrl_offs
= DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET
,
710 .context_offs
= DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET
,
711 .modulemode
= MODULEMODE_HWCTRL
,
714 .opt_clks
= gpio1_opt_clks
,
715 .opt_clks_cnt
= ARRAY_SIZE(gpio1_opt_clks
),
716 .dev_attr
= &gpio_dev_attr
,
720 static struct omap_hwmod_opt_clk gpio2_opt_clks
[] = {
721 { .role
= "dbclk", .clk
= "gpio2_dbclk" },
724 static struct omap_hwmod dra7xx_gpio2_hwmod
= {
726 .class = &dra7xx_gpio_hwmod_class
,
727 .clkdm_name
= "l4per_clkdm",
728 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
729 .main_clk
= "l3_iclk_div",
732 .clkctrl_offs
= DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET
,
733 .context_offs
= DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET
,
734 .modulemode
= MODULEMODE_HWCTRL
,
737 .opt_clks
= gpio2_opt_clks
,
738 .opt_clks_cnt
= ARRAY_SIZE(gpio2_opt_clks
),
739 .dev_attr
= &gpio_dev_attr
,
743 static struct omap_hwmod_opt_clk gpio3_opt_clks
[] = {
744 { .role
= "dbclk", .clk
= "gpio3_dbclk" },
747 static struct omap_hwmod dra7xx_gpio3_hwmod
= {
749 .class = &dra7xx_gpio_hwmod_class
,
750 .clkdm_name
= "l4per_clkdm",
751 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
752 .main_clk
= "l3_iclk_div",
755 .clkctrl_offs
= DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET
,
756 .context_offs
= DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET
,
757 .modulemode
= MODULEMODE_HWCTRL
,
760 .opt_clks
= gpio3_opt_clks
,
761 .opt_clks_cnt
= ARRAY_SIZE(gpio3_opt_clks
),
762 .dev_attr
= &gpio_dev_attr
,
766 static struct omap_hwmod_opt_clk gpio4_opt_clks
[] = {
767 { .role
= "dbclk", .clk
= "gpio4_dbclk" },
770 static struct omap_hwmod dra7xx_gpio4_hwmod
= {
772 .class = &dra7xx_gpio_hwmod_class
,
773 .clkdm_name
= "l4per_clkdm",
774 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
775 .main_clk
= "l3_iclk_div",
778 .clkctrl_offs
= DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET
,
779 .context_offs
= DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET
,
780 .modulemode
= MODULEMODE_HWCTRL
,
783 .opt_clks
= gpio4_opt_clks
,
784 .opt_clks_cnt
= ARRAY_SIZE(gpio4_opt_clks
),
785 .dev_attr
= &gpio_dev_attr
,
789 static struct omap_hwmod_opt_clk gpio5_opt_clks
[] = {
790 { .role
= "dbclk", .clk
= "gpio5_dbclk" },
793 static struct omap_hwmod dra7xx_gpio5_hwmod
= {
795 .class = &dra7xx_gpio_hwmod_class
,
796 .clkdm_name
= "l4per_clkdm",
797 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
798 .main_clk
= "l3_iclk_div",
801 .clkctrl_offs
= DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET
,
802 .context_offs
= DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET
,
803 .modulemode
= MODULEMODE_HWCTRL
,
806 .opt_clks
= gpio5_opt_clks
,
807 .opt_clks_cnt
= ARRAY_SIZE(gpio5_opt_clks
),
808 .dev_attr
= &gpio_dev_attr
,
812 static struct omap_hwmod_opt_clk gpio6_opt_clks
[] = {
813 { .role
= "dbclk", .clk
= "gpio6_dbclk" },
816 static struct omap_hwmod dra7xx_gpio6_hwmod
= {
818 .class = &dra7xx_gpio_hwmod_class
,
819 .clkdm_name
= "l4per_clkdm",
820 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
821 .main_clk
= "l3_iclk_div",
824 .clkctrl_offs
= DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET
,
825 .context_offs
= DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET
,
826 .modulemode
= MODULEMODE_HWCTRL
,
829 .opt_clks
= gpio6_opt_clks
,
830 .opt_clks_cnt
= ARRAY_SIZE(gpio6_opt_clks
),
831 .dev_attr
= &gpio_dev_attr
,
835 static struct omap_hwmod_opt_clk gpio7_opt_clks
[] = {
836 { .role
= "dbclk", .clk
= "gpio7_dbclk" },
839 static struct omap_hwmod dra7xx_gpio7_hwmod
= {
841 .class = &dra7xx_gpio_hwmod_class
,
842 .clkdm_name
= "l4per_clkdm",
843 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
844 .main_clk
= "l3_iclk_div",
847 .clkctrl_offs
= DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET
,
848 .context_offs
= DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET
,
849 .modulemode
= MODULEMODE_HWCTRL
,
852 .opt_clks
= gpio7_opt_clks
,
853 .opt_clks_cnt
= ARRAY_SIZE(gpio7_opt_clks
),
854 .dev_attr
= &gpio_dev_attr
,
858 static struct omap_hwmod_opt_clk gpio8_opt_clks
[] = {
859 { .role
= "dbclk", .clk
= "gpio8_dbclk" },
862 static struct omap_hwmod dra7xx_gpio8_hwmod
= {
864 .class = &dra7xx_gpio_hwmod_class
,
865 .clkdm_name
= "l4per_clkdm",
866 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
867 .main_clk
= "l3_iclk_div",
870 .clkctrl_offs
= DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET
,
871 .context_offs
= DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET
,
872 .modulemode
= MODULEMODE_HWCTRL
,
875 .opt_clks
= gpio8_opt_clks
,
876 .opt_clks_cnt
= ARRAY_SIZE(gpio8_opt_clks
),
877 .dev_attr
= &gpio_dev_attr
,
885 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc
= {
889 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SIDLEMODE
|
890 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
891 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
892 .sysc_fields
= &omap_hwmod_sysc_type1
,
895 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class
= {
897 .sysc
= &dra7xx_gpmc_sysc
,
902 static struct omap_hwmod dra7xx_gpmc_hwmod
= {
904 .class = &dra7xx_gpmc_hwmod_class
,
905 .clkdm_name
= "l3main1_clkdm",
906 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
907 .flags
= DEBUG_OMAP_GPMC_HWMOD_FLAGS
,
908 .main_clk
= "l3_iclk_div",
911 .clkctrl_offs
= DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET
,
912 .context_offs
= DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET
,
913 .modulemode
= MODULEMODE_HWCTRL
,
923 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc
= {
927 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SOFTRESET
|
928 SYSS_HAS_RESET_STATUS
),
929 .sysc_fields
= &omap_hwmod_sysc_type1
,
932 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class
= {
934 .sysc
= &dra7xx_hdq1w_sysc
,
939 static struct omap_hwmod dra7xx_hdq1w_hwmod
= {
941 .class = &dra7xx_hdq1w_hwmod_class
,
942 .clkdm_name
= "l4per_clkdm",
943 .flags
= HWMOD_INIT_NO_RESET
,
944 .main_clk
= "func_12m_fclk",
947 .clkctrl_offs
= DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET
,
948 .context_offs
= DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET
,
949 .modulemode
= MODULEMODE_SWCTRL
,
959 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc
= {
962 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
963 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
964 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
965 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
967 .clockact
= CLOCKACT_TEST_ICLK
,
968 .sysc_fields
= &omap_hwmod_sysc_type1
,
971 static struct omap_hwmod_class dra7xx_i2c_hwmod_class
= {
973 .sysc
= &dra7xx_i2c_sysc
,
974 .reset
= &omap_i2c_reset
,
975 .rev
= OMAP_I2C_IP_VERSION_2
,
979 static struct omap_i2c_dev_attr i2c_dev_attr
= {
980 .flags
= OMAP_I2C_FLAG_BUS_SHIFT_NONE
,
984 static struct omap_hwmod dra7xx_i2c1_hwmod
= {
986 .class = &dra7xx_i2c_hwmod_class
,
987 .clkdm_name
= "l4per_clkdm",
988 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
989 .main_clk
= "func_96m_fclk",
992 .clkctrl_offs
= DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET
,
993 .context_offs
= DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET
,
994 .modulemode
= MODULEMODE_SWCTRL
,
997 .dev_attr
= &i2c_dev_attr
,
1001 static struct omap_hwmod dra7xx_i2c2_hwmod
= {
1003 .class = &dra7xx_i2c_hwmod_class
,
1004 .clkdm_name
= "l4per_clkdm",
1005 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1006 .main_clk
= "func_96m_fclk",
1009 .clkctrl_offs
= DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET
,
1010 .context_offs
= DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET
,
1011 .modulemode
= MODULEMODE_SWCTRL
,
1014 .dev_attr
= &i2c_dev_attr
,
1018 static struct omap_hwmod dra7xx_i2c3_hwmod
= {
1020 .class = &dra7xx_i2c_hwmod_class
,
1021 .clkdm_name
= "l4per_clkdm",
1022 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1023 .main_clk
= "func_96m_fclk",
1026 .clkctrl_offs
= DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET
,
1027 .context_offs
= DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET
,
1028 .modulemode
= MODULEMODE_SWCTRL
,
1031 .dev_attr
= &i2c_dev_attr
,
1035 static struct omap_hwmod dra7xx_i2c4_hwmod
= {
1037 .class = &dra7xx_i2c_hwmod_class
,
1038 .clkdm_name
= "l4per_clkdm",
1039 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1040 .main_clk
= "func_96m_fclk",
1043 .clkctrl_offs
= DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET
,
1044 .context_offs
= DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET
,
1045 .modulemode
= MODULEMODE_SWCTRL
,
1048 .dev_attr
= &i2c_dev_attr
,
1052 static struct omap_hwmod dra7xx_i2c5_hwmod
= {
1054 .class = &dra7xx_i2c_hwmod_class
,
1055 .clkdm_name
= "ipu_clkdm",
1056 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1057 .main_clk
= "func_96m_fclk",
1060 .clkctrl_offs
= DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET
,
1061 .context_offs
= DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET
,
1062 .modulemode
= MODULEMODE_SWCTRL
,
1065 .dev_attr
= &i2c_dev_attr
,
1073 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc
= {
1075 .sysc_offs
= 0x0010,
1076 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
1077 SYSC_HAS_SOFTRESET
),
1078 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1079 .sysc_fields
= &omap_hwmod_sysc_type2
,
1082 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class
= {
1084 .sysc
= &dra7xx_mailbox_sysc
,
1088 static struct omap_hwmod dra7xx_mailbox1_hwmod
= {
1090 .class = &dra7xx_mailbox_hwmod_class
,
1091 .clkdm_name
= "l4cfg_clkdm",
1094 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET
,
1095 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET
,
1101 static struct omap_hwmod dra7xx_mailbox2_hwmod
= {
1103 .class = &dra7xx_mailbox_hwmod_class
,
1104 .clkdm_name
= "l4cfg_clkdm",
1107 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET
,
1108 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET
,
1114 static struct omap_hwmod dra7xx_mailbox3_hwmod
= {
1116 .class = &dra7xx_mailbox_hwmod_class
,
1117 .clkdm_name
= "l4cfg_clkdm",
1120 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET
,
1121 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET
,
1127 static struct omap_hwmod dra7xx_mailbox4_hwmod
= {
1129 .class = &dra7xx_mailbox_hwmod_class
,
1130 .clkdm_name
= "l4cfg_clkdm",
1133 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET
,
1134 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET
,
1140 static struct omap_hwmod dra7xx_mailbox5_hwmod
= {
1142 .class = &dra7xx_mailbox_hwmod_class
,
1143 .clkdm_name
= "l4cfg_clkdm",
1146 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET
,
1147 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET
,
1153 static struct omap_hwmod dra7xx_mailbox6_hwmod
= {
1155 .class = &dra7xx_mailbox_hwmod_class
,
1156 .clkdm_name
= "l4cfg_clkdm",
1159 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET
,
1160 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET
,
1166 static struct omap_hwmod dra7xx_mailbox7_hwmod
= {
1168 .class = &dra7xx_mailbox_hwmod_class
,
1169 .clkdm_name
= "l4cfg_clkdm",
1172 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET
,
1173 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET
,
1179 static struct omap_hwmod dra7xx_mailbox8_hwmod
= {
1181 .class = &dra7xx_mailbox_hwmod_class
,
1182 .clkdm_name
= "l4cfg_clkdm",
1185 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET
,
1186 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET
,
1192 static struct omap_hwmod dra7xx_mailbox9_hwmod
= {
1194 .class = &dra7xx_mailbox_hwmod_class
,
1195 .clkdm_name
= "l4cfg_clkdm",
1198 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET
,
1199 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET
,
1205 static struct omap_hwmod dra7xx_mailbox10_hwmod
= {
1206 .name
= "mailbox10",
1207 .class = &dra7xx_mailbox_hwmod_class
,
1208 .clkdm_name
= "l4cfg_clkdm",
1211 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET
,
1212 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET
,
1218 static struct omap_hwmod dra7xx_mailbox11_hwmod
= {
1219 .name
= "mailbox11",
1220 .class = &dra7xx_mailbox_hwmod_class
,
1221 .clkdm_name
= "l4cfg_clkdm",
1224 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET
,
1225 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET
,
1231 static struct omap_hwmod dra7xx_mailbox12_hwmod
= {
1232 .name
= "mailbox12",
1233 .class = &dra7xx_mailbox_hwmod_class
,
1234 .clkdm_name
= "l4cfg_clkdm",
1237 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET
,
1238 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET
,
1244 static struct omap_hwmod dra7xx_mailbox13_hwmod
= {
1245 .name
= "mailbox13",
1246 .class = &dra7xx_mailbox_hwmod_class
,
1247 .clkdm_name
= "l4cfg_clkdm",
1250 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET
,
1251 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET
,
1261 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc
= {
1263 .sysc_offs
= 0x0010,
1264 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
1265 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1266 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1268 .sysc_fields
= &omap_hwmod_sysc_type2
,
1271 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class
= {
1273 .sysc
= &dra7xx_mcspi_sysc
,
1274 .rev
= OMAP4_MCSPI_REV
,
1278 /* mcspi1 dev_attr */
1279 static struct omap2_mcspi_dev_attr mcspi1_dev_attr
= {
1280 .num_chipselect
= 4,
1283 static struct omap_hwmod dra7xx_mcspi1_hwmod
= {
1285 .class = &dra7xx_mcspi_hwmod_class
,
1286 .clkdm_name
= "l4per_clkdm",
1287 .main_clk
= "func_48m_fclk",
1290 .clkctrl_offs
= DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET
,
1291 .context_offs
= DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET
,
1292 .modulemode
= MODULEMODE_SWCTRL
,
1295 .dev_attr
= &mcspi1_dev_attr
,
1299 /* mcspi2 dev_attr */
1300 static struct omap2_mcspi_dev_attr mcspi2_dev_attr
= {
1301 .num_chipselect
= 2,
1304 static struct omap_hwmod dra7xx_mcspi2_hwmod
= {
1306 .class = &dra7xx_mcspi_hwmod_class
,
1307 .clkdm_name
= "l4per_clkdm",
1308 .main_clk
= "func_48m_fclk",
1311 .clkctrl_offs
= DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET
,
1312 .context_offs
= DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET
,
1313 .modulemode
= MODULEMODE_SWCTRL
,
1316 .dev_attr
= &mcspi2_dev_attr
,
1320 /* mcspi3 dev_attr */
1321 static struct omap2_mcspi_dev_attr mcspi3_dev_attr
= {
1322 .num_chipselect
= 2,
1325 static struct omap_hwmod dra7xx_mcspi3_hwmod
= {
1327 .class = &dra7xx_mcspi_hwmod_class
,
1328 .clkdm_name
= "l4per_clkdm",
1329 .main_clk
= "func_48m_fclk",
1332 .clkctrl_offs
= DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET
,
1333 .context_offs
= DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET
,
1334 .modulemode
= MODULEMODE_SWCTRL
,
1337 .dev_attr
= &mcspi3_dev_attr
,
1341 /* mcspi4 dev_attr */
1342 static struct omap2_mcspi_dev_attr mcspi4_dev_attr
= {
1343 .num_chipselect
= 1,
1346 static struct omap_hwmod dra7xx_mcspi4_hwmod
= {
1348 .class = &dra7xx_mcspi_hwmod_class
,
1349 .clkdm_name
= "l4per_clkdm",
1350 .main_clk
= "func_48m_fclk",
1353 .clkctrl_offs
= DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET
,
1354 .context_offs
= DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET
,
1355 .modulemode
= MODULEMODE_SWCTRL
,
1358 .dev_attr
= &mcspi4_dev_attr
,
1365 static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc
= {
1366 .sysc_offs
= 0x0004,
1367 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
1368 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1369 .sysc_fields
= &omap_hwmod_sysc_type3
,
1372 static struct omap_hwmod_class dra7xx_mcasp_hwmod_class
= {
1374 .sysc
= &dra7xx_mcasp_sysc
,
1378 static struct omap_hwmod_opt_clk mcasp3_opt_clks
[] = {
1379 { .role
= "ahclkx", .clk
= "mcasp3_ahclkx_mux" },
1382 static struct omap_hwmod dra7xx_mcasp3_hwmod
= {
1384 .class = &dra7xx_mcasp_hwmod_class
,
1385 .clkdm_name
= "l4per2_clkdm",
1386 .main_clk
= "mcasp3_aux_gfclk_mux",
1387 .flags
= HWMOD_OPT_CLKS_NEEDED
,
1390 .clkctrl_offs
= DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET
,
1391 .context_offs
= DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET
,
1392 .modulemode
= MODULEMODE_SWCTRL
,
1395 .opt_clks
= mcasp3_opt_clks
,
1396 .opt_clks_cnt
= ARRAY_SIZE(mcasp3_opt_clks
),
1404 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc
= {
1406 .sysc_offs
= 0x0010,
1407 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_MIDLEMODE
|
1408 SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
1409 SYSC_HAS_SOFTRESET
),
1410 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1411 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1412 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1413 .sysc_fields
= &omap_hwmod_sysc_type2
,
1416 static struct omap_hwmod_class dra7xx_mmc_hwmod_class
= {
1418 .sysc
= &dra7xx_mmc_sysc
,
1422 static struct omap_hwmod_opt_clk mmc1_opt_clks
[] = {
1423 { .role
= "clk32k", .clk
= "mmc1_clk32k" },
1427 static struct omap_hsmmc_dev_attr mmc1_dev_attr
= {
1428 .flags
= OMAP_HSMMC_SUPPORTS_DUAL_VOLT
,
1431 static struct omap_hwmod dra7xx_mmc1_hwmod
= {
1433 .class = &dra7xx_mmc_hwmod_class
,
1434 .clkdm_name
= "l3init_clkdm",
1435 .main_clk
= "mmc1_fclk_div",
1438 .clkctrl_offs
= DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET
,
1439 .context_offs
= DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET
,
1440 .modulemode
= MODULEMODE_SWCTRL
,
1443 .opt_clks
= mmc1_opt_clks
,
1444 .opt_clks_cnt
= ARRAY_SIZE(mmc1_opt_clks
),
1445 .dev_attr
= &mmc1_dev_attr
,
1449 static struct omap_hwmod_opt_clk mmc2_opt_clks
[] = {
1450 { .role
= "clk32k", .clk
= "mmc2_clk32k" },
1453 static struct omap_hwmod dra7xx_mmc2_hwmod
= {
1455 .class = &dra7xx_mmc_hwmod_class
,
1456 .clkdm_name
= "l3init_clkdm",
1457 .main_clk
= "mmc2_fclk_div",
1460 .clkctrl_offs
= DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET
,
1461 .context_offs
= DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET
,
1462 .modulemode
= MODULEMODE_SWCTRL
,
1465 .opt_clks
= mmc2_opt_clks
,
1466 .opt_clks_cnt
= ARRAY_SIZE(mmc2_opt_clks
),
1470 static struct omap_hwmod_opt_clk mmc3_opt_clks
[] = {
1471 { .role
= "clk32k", .clk
= "mmc3_clk32k" },
1474 static struct omap_hwmod dra7xx_mmc3_hwmod
= {
1476 .class = &dra7xx_mmc_hwmod_class
,
1477 .clkdm_name
= "l4per_clkdm",
1478 .main_clk
= "mmc3_gfclk_div",
1481 .clkctrl_offs
= DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET
,
1482 .context_offs
= DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET
,
1483 .modulemode
= MODULEMODE_SWCTRL
,
1486 .opt_clks
= mmc3_opt_clks
,
1487 .opt_clks_cnt
= ARRAY_SIZE(mmc3_opt_clks
),
1491 static struct omap_hwmod_opt_clk mmc4_opt_clks
[] = {
1492 { .role
= "clk32k", .clk
= "mmc4_clk32k" },
1495 static struct omap_hwmod dra7xx_mmc4_hwmod
= {
1497 .class = &dra7xx_mmc_hwmod_class
,
1498 .clkdm_name
= "l4per_clkdm",
1499 .main_clk
= "mmc4_gfclk_div",
1502 .clkctrl_offs
= DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET
,
1503 .context_offs
= DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET
,
1504 .modulemode
= MODULEMODE_SWCTRL
,
1507 .opt_clks
= mmc4_opt_clks
,
1508 .opt_clks_cnt
= ARRAY_SIZE(mmc4_opt_clks
),
1516 static struct omap_hwmod_class dra7xx_mpu_hwmod_class
= {
1521 static struct omap_hwmod dra7xx_mpu_hwmod
= {
1523 .class = &dra7xx_mpu_hwmod_class
,
1524 .clkdm_name
= "mpu_clkdm",
1525 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
1526 .main_clk
= "dpll_mpu_m2_ck",
1529 .clkctrl_offs
= DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET
,
1530 .context_offs
= DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET
,
1540 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc
= {
1542 .sysc_offs
= 0x0010,
1543 .syss_offs
= 0x0014,
1544 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SIDLEMODE
|
1545 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1546 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1547 .sysc_fields
= &omap_hwmod_sysc_type1
,
1550 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class
= {
1552 .sysc
= &dra7xx_ocp2scp_sysc
,
1556 static struct omap_hwmod dra7xx_ocp2scp1_hwmod
= {
1558 .class = &dra7xx_ocp2scp_hwmod_class
,
1559 .clkdm_name
= "l3init_clkdm",
1560 .main_clk
= "l4_root_clk_div",
1563 .clkctrl_offs
= DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET
,
1564 .context_offs
= DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET
,
1565 .modulemode
= MODULEMODE_HWCTRL
,
1571 static struct omap_hwmod dra7xx_ocp2scp3_hwmod
= {
1573 .class = &dra7xx_ocp2scp_hwmod_class
,
1574 .clkdm_name
= "l3init_clkdm",
1575 .main_clk
= "l4_root_clk_div",
1578 .clkctrl_offs
= DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET
,
1579 .context_offs
= DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET
,
1580 .modulemode
= MODULEMODE_HWCTRL
,
1591 * As noted in documentation for _reset() in omap_hwmod.c, the stock reset
1592 * functionality of OMAP HWMOD layer does not deassert the hardreset lines
1593 * associated with an IP automatically leaving the driver to handle that
1594 * by itself. This does not work for PCIeSS which needs the reset lines
1595 * deasserted for the driver to start accessing registers.
1597 * We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset
1598 * lines after asserting them.
1600 static int dra7xx_pciess_reset(struct omap_hwmod
*oh
)
1604 for (i
= 0; i
< oh
->rst_lines_cnt
; i
++) {
1605 omap_hwmod_assert_hardreset(oh
, oh
->rst_lines
[i
].name
);
1606 omap_hwmod_deassert_hardreset(oh
, oh
->rst_lines
[i
].name
);
1612 static struct omap_hwmod_class dra7xx_pciess_hwmod_class
= {
1614 .reset
= dra7xx_pciess_reset
,
1618 static struct omap_hwmod_rst_info dra7xx_pciess1_resets
[] = {
1619 { .name
= "pcie", .rst_shift
= 0 },
1622 static struct omap_hwmod dra7xx_pciess1_hwmod
= {
1624 .class = &dra7xx_pciess_hwmod_class
,
1625 .clkdm_name
= "pcie_clkdm",
1626 .rst_lines
= dra7xx_pciess1_resets
,
1627 .rst_lines_cnt
= ARRAY_SIZE(dra7xx_pciess1_resets
),
1628 .main_clk
= "l4_root_clk_div",
1631 .clkctrl_offs
= DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET
,
1632 .rstctrl_offs
= DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET
,
1633 .context_offs
= DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET
,
1634 .modulemode
= MODULEMODE_SWCTRL
,
1640 static struct omap_hwmod_rst_info dra7xx_pciess2_resets
[] = {
1641 { .name
= "pcie", .rst_shift
= 1 },
1645 static struct omap_hwmod dra7xx_pciess2_hwmod
= {
1647 .class = &dra7xx_pciess_hwmod_class
,
1648 .clkdm_name
= "pcie_clkdm",
1649 .rst_lines
= dra7xx_pciess2_resets
,
1650 .rst_lines_cnt
= ARRAY_SIZE(dra7xx_pciess2_resets
),
1651 .main_clk
= "l4_root_clk_div",
1654 .clkctrl_offs
= DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET
,
1655 .rstctrl_offs
= DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET
,
1656 .context_offs
= DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET
,
1657 .modulemode
= MODULEMODE_SWCTRL
,
1667 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc
= {
1668 .sysc_offs
= 0x0010,
1669 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
1670 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1672 .sysc_fields
= &omap_hwmod_sysc_type2
,
1675 static struct omap_hwmod_class dra7xx_qspi_hwmod_class
= {
1677 .sysc
= &dra7xx_qspi_sysc
,
1681 static struct omap_hwmod dra7xx_qspi_hwmod
= {
1683 .class = &dra7xx_qspi_hwmod_class
,
1684 .clkdm_name
= "l4per2_clkdm",
1685 .main_clk
= "qspi_gfclk_div",
1688 .clkctrl_offs
= DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET
,
1689 .context_offs
= DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET
,
1690 .modulemode
= MODULEMODE_SWCTRL
,
1699 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc
= {
1700 .sysc_offs
= 0x0078,
1701 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
1702 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1704 .sysc_fields
= &omap_hwmod_sysc_type3
,
1707 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class
= {
1709 .sysc
= &dra7xx_rtcss_sysc
,
1713 static struct omap_hwmod dra7xx_rtcss_hwmod
= {
1715 .class = &dra7xx_rtcss_hwmod_class
,
1716 .clkdm_name
= "rtc_clkdm",
1717 .main_clk
= "sys_32k_ck",
1720 .clkctrl_offs
= DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET
,
1721 .context_offs
= DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET
,
1722 .modulemode
= MODULEMODE_SWCTRL
,
1732 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc
= {
1733 .sysc_offs
= 0x0000,
1734 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
),
1735 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1736 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1737 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1738 .sysc_fields
= &omap_hwmod_sysc_type2
,
1741 static struct omap_hwmod_class dra7xx_sata_hwmod_class
= {
1743 .sysc
= &dra7xx_sata_sysc
,
1748 static struct omap_hwmod dra7xx_sata_hwmod
= {
1750 .class = &dra7xx_sata_hwmod_class
,
1751 .clkdm_name
= "l3init_clkdm",
1752 .flags
= HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
,
1753 .main_clk
= "func_48m_fclk",
1757 .clkctrl_offs
= DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET
,
1758 .context_offs
= DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET
,
1759 .modulemode
= MODULEMODE_SWCTRL
,
1765 * 'smartreflex' class
1769 /* The IP is not compliant to type1 / type2 scheme */
1770 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex
= {
1775 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc
= {
1776 .sysc_offs
= 0x0038,
1777 .sysc_flags
= (SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
),
1778 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1780 .sysc_fields
= &omap_hwmod_sysc_type_smartreflex
,
1783 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class
= {
1784 .name
= "smartreflex",
1785 .sysc
= &dra7xx_smartreflex_sysc
,
1789 /* smartreflex_core */
1790 /* smartreflex_core dev_attr */
1791 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr
= {
1792 .sensor_voltdm_name
= "core",
1795 static struct omap_hwmod dra7xx_smartreflex_core_hwmod
= {
1796 .name
= "smartreflex_core",
1797 .class = &dra7xx_smartreflex_hwmod_class
,
1798 .clkdm_name
= "coreaon_clkdm",
1799 .main_clk
= "wkupaon_iclk_mux",
1802 .clkctrl_offs
= DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET
,
1803 .context_offs
= DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET
,
1804 .modulemode
= MODULEMODE_SWCTRL
,
1807 .dev_attr
= &smartreflex_core_dev_attr
,
1810 /* smartreflex_mpu */
1811 /* smartreflex_mpu dev_attr */
1812 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr
= {
1813 .sensor_voltdm_name
= "mpu",
1816 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod
= {
1817 .name
= "smartreflex_mpu",
1818 .class = &dra7xx_smartreflex_hwmod_class
,
1819 .clkdm_name
= "coreaon_clkdm",
1820 .main_clk
= "wkupaon_iclk_mux",
1823 .clkctrl_offs
= DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET
,
1824 .context_offs
= DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET
,
1825 .modulemode
= MODULEMODE_SWCTRL
,
1828 .dev_attr
= &smartreflex_mpu_dev_attr
,
1836 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc
= {
1838 .sysc_offs
= 0x0010,
1839 .syss_offs
= 0x0014,
1840 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
1841 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
1842 SYSS_HAS_RESET_STATUS
),
1843 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1844 .sysc_fields
= &omap_hwmod_sysc_type1
,
1847 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class
= {
1849 .sysc
= &dra7xx_spinlock_sysc
,
1853 static struct omap_hwmod dra7xx_spinlock_hwmod
= {
1855 .class = &dra7xx_spinlock_hwmod_class
,
1856 .clkdm_name
= "l4cfg_clkdm",
1857 .main_clk
= "l3_iclk_div",
1860 .clkctrl_offs
= DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET
,
1861 .context_offs
= DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET
,
1869 * This class contains several variants: ['timer_1ms', 'timer_secure',
1873 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc
= {
1875 .sysc_offs
= 0x0010,
1876 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
1877 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1878 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1880 .sysc_fields
= &omap_hwmod_sysc_type2
,
1883 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class
= {
1885 .sysc
= &dra7xx_timer_1ms_sysc
,
1888 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc
= {
1890 .sysc_offs
= 0x0010,
1891 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
1892 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1893 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1895 .sysc_fields
= &omap_hwmod_sysc_type2
,
1898 static struct omap_hwmod_class dra7xx_timer_hwmod_class
= {
1900 .sysc
= &dra7xx_timer_sysc
,
1904 static struct omap_hwmod dra7xx_timer1_hwmod
= {
1906 .class = &dra7xx_timer_1ms_hwmod_class
,
1907 .clkdm_name
= "wkupaon_clkdm",
1908 .main_clk
= "timer1_gfclk_mux",
1911 .clkctrl_offs
= DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET
,
1912 .context_offs
= DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET
,
1913 .modulemode
= MODULEMODE_SWCTRL
,
1919 static struct omap_hwmod dra7xx_timer2_hwmod
= {
1921 .class = &dra7xx_timer_1ms_hwmod_class
,
1922 .clkdm_name
= "l4per_clkdm",
1923 .main_clk
= "timer2_gfclk_mux",
1926 .clkctrl_offs
= DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET
,
1927 .context_offs
= DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET
,
1928 .modulemode
= MODULEMODE_SWCTRL
,
1934 static struct omap_hwmod dra7xx_timer3_hwmod
= {
1936 .class = &dra7xx_timer_hwmod_class
,
1937 .clkdm_name
= "l4per_clkdm",
1938 .main_clk
= "timer3_gfclk_mux",
1941 .clkctrl_offs
= DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET
,
1942 .context_offs
= DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET
,
1943 .modulemode
= MODULEMODE_SWCTRL
,
1949 static struct omap_hwmod dra7xx_timer4_hwmod
= {
1951 .class = &dra7xx_timer_hwmod_class
,
1952 .clkdm_name
= "l4per_clkdm",
1953 .main_clk
= "timer4_gfclk_mux",
1956 .clkctrl_offs
= DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET
,
1957 .context_offs
= DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET
,
1958 .modulemode
= MODULEMODE_SWCTRL
,
1964 static struct omap_hwmod dra7xx_timer5_hwmod
= {
1966 .class = &dra7xx_timer_hwmod_class
,
1967 .clkdm_name
= "ipu_clkdm",
1968 .main_clk
= "timer5_gfclk_mux",
1971 .clkctrl_offs
= DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET
,
1972 .context_offs
= DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET
,
1973 .modulemode
= MODULEMODE_SWCTRL
,
1979 static struct omap_hwmod dra7xx_timer6_hwmod
= {
1981 .class = &dra7xx_timer_hwmod_class
,
1982 .clkdm_name
= "ipu_clkdm",
1983 .main_clk
= "timer6_gfclk_mux",
1986 .clkctrl_offs
= DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET
,
1987 .context_offs
= DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET
,
1988 .modulemode
= MODULEMODE_SWCTRL
,
1994 static struct omap_hwmod dra7xx_timer7_hwmod
= {
1996 .class = &dra7xx_timer_hwmod_class
,
1997 .clkdm_name
= "ipu_clkdm",
1998 .main_clk
= "timer7_gfclk_mux",
2001 .clkctrl_offs
= DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET
,
2002 .context_offs
= DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET
,
2003 .modulemode
= MODULEMODE_SWCTRL
,
2009 static struct omap_hwmod dra7xx_timer8_hwmod
= {
2011 .class = &dra7xx_timer_hwmod_class
,
2012 .clkdm_name
= "ipu_clkdm",
2013 .main_clk
= "timer8_gfclk_mux",
2016 .clkctrl_offs
= DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET
,
2017 .context_offs
= DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET
,
2018 .modulemode
= MODULEMODE_SWCTRL
,
2024 static struct omap_hwmod dra7xx_timer9_hwmod
= {
2026 .class = &dra7xx_timer_hwmod_class
,
2027 .clkdm_name
= "l4per_clkdm",
2028 .main_clk
= "timer9_gfclk_mux",
2031 .clkctrl_offs
= DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET
,
2032 .context_offs
= DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET
,
2033 .modulemode
= MODULEMODE_SWCTRL
,
2039 static struct omap_hwmod dra7xx_timer10_hwmod
= {
2041 .class = &dra7xx_timer_1ms_hwmod_class
,
2042 .clkdm_name
= "l4per_clkdm",
2043 .main_clk
= "timer10_gfclk_mux",
2046 .clkctrl_offs
= DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET
,
2047 .context_offs
= DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET
,
2048 .modulemode
= MODULEMODE_SWCTRL
,
2054 static struct omap_hwmod dra7xx_timer11_hwmod
= {
2056 .class = &dra7xx_timer_hwmod_class
,
2057 .clkdm_name
= "l4per_clkdm",
2058 .main_clk
= "timer11_gfclk_mux",
2061 .clkctrl_offs
= DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET
,
2062 .context_offs
= DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET
,
2063 .modulemode
= MODULEMODE_SWCTRL
,
2069 static struct omap_hwmod dra7xx_timer13_hwmod
= {
2071 .class = &dra7xx_timer_hwmod_class
,
2072 .clkdm_name
= "l4per3_clkdm",
2073 .main_clk
= "timer13_gfclk_mux",
2076 .clkctrl_offs
= DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET
,
2077 .context_offs
= DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET
,
2078 .modulemode
= MODULEMODE_SWCTRL
,
2084 static struct omap_hwmod dra7xx_timer14_hwmod
= {
2086 .class = &dra7xx_timer_hwmod_class
,
2087 .clkdm_name
= "l4per3_clkdm",
2088 .main_clk
= "timer14_gfclk_mux",
2091 .clkctrl_offs
= DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET
,
2092 .context_offs
= DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET
,
2093 .modulemode
= MODULEMODE_SWCTRL
,
2099 static struct omap_hwmod dra7xx_timer15_hwmod
= {
2101 .class = &dra7xx_timer_hwmod_class
,
2102 .clkdm_name
= "l4per3_clkdm",
2103 .main_clk
= "timer15_gfclk_mux",
2106 .clkctrl_offs
= DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET
,
2107 .context_offs
= DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET
,
2108 .modulemode
= MODULEMODE_SWCTRL
,
2114 static struct omap_hwmod dra7xx_timer16_hwmod
= {
2116 .class = &dra7xx_timer_hwmod_class
,
2117 .clkdm_name
= "l4per3_clkdm",
2118 .main_clk
= "timer16_gfclk_mux",
2121 .clkctrl_offs
= DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET
,
2122 .context_offs
= DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET
,
2123 .modulemode
= MODULEMODE_SWCTRL
,
2133 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc
= {
2135 .sysc_offs
= 0x0054,
2136 .syss_offs
= 0x0058,
2137 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
2138 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
2139 SYSS_HAS_RESET_STATUS
),
2140 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2142 .sysc_fields
= &omap_hwmod_sysc_type1
,
2145 static struct omap_hwmod_class dra7xx_uart_hwmod_class
= {
2147 .sysc
= &dra7xx_uart_sysc
,
2151 static struct omap_hwmod dra7xx_uart1_hwmod
= {
2153 .class = &dra7xx_uart_hwmod_class
,
2154 .clkdm_name
= "l4per_clkdm",
2155 .main_clk
= "uart1_gfclk_mux",
2156 .flags
= HWMOD_SWSUP_SIDLE_ACT
| DEBUG_OMAP2UART1_FLAGS
,
2159 .clkctrl_offs
= DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET
,
2160 .context_offs
= DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET
,
2161 .modulemode
= MODULEMODE_SWCTRL
,
2167 static struct omap_hwmod dra7xx_uart2_hwmod
= {
2169 .class = &dra7xx_uart_hwmod_class
,
2170 .clkdm_name
= "l4per_clkdm",
2171 .main_clk
= "uart2_gfclk_mux",
2172 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
2175 .clkctrl_offs
= DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET
,
2176 .context_offs
= DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET
,
2177 .modulemode
= MODULEMODE_SWCTRL
,
2183 static struct omap_hwmod dra7xx_uart3_hwmod
= {
2185 .class = &dra7xx_uart_hwmod_class
,
2186 .clkdm_name
= "l4per_clkdm",
2187 .main_clk
= "uart3_gfclk_mux",
2188 .flags
= HWMOD_SWSUP_SIDLE_ACT
| DEBUG_OMAP4UART3_FLAGS
,
2191 .clkctrl_offs
= DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET
,
2192 .context_offs
= DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET
,
2193 .modulemode
= MODULEMODE_SWCTRL
,
2199 static struct omap_hwmod dra7xx_uart4_hwmod
= {
2201 .class = &dra7xx_uart_hwmod_class
,
2202 .clkdm_name
= "l4per_clkdm",
2203 .main_clk
= "uart4_gfclk_mux",
2204 .flags
= HWMOD_SWSUP_SIDLE_ACT
| DEBUG_OMAP4UART4_FLAGS
,
2207 .clkctrl_offs
= DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET
,
2208 .context_offs
= DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET
,
2209 .modulemode
= MODULEMODE_SWCTRL
,
2215 static struct omap_hwmod dra7xx_uart5_hwmod
= {
2217 .class = &dra7xx_uart_hwmod_class
,
2218 .clkdm_name
= "l4per_clkdm",
2219 .main_clk
= "uart5_gfclk_mux",
2220 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
2223 .clkctrl_offs
= DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET
,
2224 .context_offs
= DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET
,
2225 .modulemode
= MODULEMODE_SWCTRL
,
2231 static struct omap_hwmod dra7xx_uart6_hwmod
= {
2233 .class = &dra7xx_uart_hwmod_class
,
2234 .clkdm_name
= "ipu_clkdm",
2235 .main_clk
= "uart6_gfclk_mux",
2236 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
2239 .clkctrl_offs
= DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET
,
2240 .context_offs
= DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET
,
2241 .modulemode
= MODULEMODE_SWCTRL
,
2247 static struct omap_hwmod dra7xx_uart7_hwmod
= {
2249 .class = &dra7xx_uart_hwmod_class
,
2250 .clkdm_name
= "l4per2_clkdm",
2251 .main_clk
= "uart7_gfclk_mux",
2252 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
2255 .clkctrl_offs
= DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET
,
2256 .context_offs
= DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET
,
2257 .modulemode
= MODULEMODE_SWCTRL
,
2263 static struct omap_hwmod dra7xx_uart8_hwmod
= {
2265 .class = &dra7xx_uart_hwmod_class
,
2266 .clkdm_name
= "l4per2_clkdm",
2267 .main_clk
= "uart8_gfclk_mux",
2268 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
2271 .clkctrl_offs
= DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET
,
2272 .context_offs
= DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET
,
2273 .modulemode
= MODULEMODE_SWCTRL
,
2279 static struct omap_hwmod dra7xx_uart9_hwmod
= {
2281 .class = &dra7xx_uart_hwmod_class
,
2282 .clkdm_name
= "l4per2_clkdm",
2283 .main_clk
= "uart9_gfclk_mux",
2284 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
2287 .clkctrl_offs
= DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET
,
2288 .context_offs
= DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET
,
2289 .modulemode
= MODULEMODE_SWCTRL
,
2295 static struct omap_hwmod dra7xx_uart10_hwmod
= {
2297 .class = &dra7xx_uart_hwmod_class
,
2298 .clkdm_name
= "wkupaon_clkdm",
2299 .main_clk
= "uart10_gfclk_mux",
2300 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
2303 .clkctrl_offs
= DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET
,
2304 .context_offs
= DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET
,
2305 .modulemode
= MODULEMODE_SWCTRL
,
2311 * 'usb_otg_ss' class
2315 static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc
= {
2317 .sysc_offs
= 0x0010,
2318 .sysc_flags
= (SYSC_HAS_DMADISABLE
| SYSC_HAS_MIDLEMODE
|
2319 SYSC_HAS_SIDLEMODE
),
2320 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2321 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
2322 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
2323 .sysc_fields
= &omap_hwmod_sysc_type2
,
2326 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class
= {
2327 .name
= "usb_otg_ss",
2328 .sysc
= &dra7xx_usb_otg_ss_sysc
,
2332 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks
[] = {
2333 { .role
= "refclk960m", .clk
= "usb_otg_ss1_refclk960m" },
2336 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod
= {
2337 .name
= "usb_otg_ss1",
2338 .class = &dra7xx_usb_otg_ss_hwmod_class
,
2339 .clkdm_name
= "l3init_clkdm",
2340 .main_clk
= "dpll_core_h13x2_ck",
2343 .clkctrl_offs
= DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET
,
2344 .context_offs
= DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET
,
2345 .modulemode
= MODULEMODE_HWCTRL
,
2348 .opt_clks
= usb_otg_ss1_opt_clks
,
2349 .opt_clks_cnt
= ARRAY_SIZE(usb_otg_ss1_opt_clks
),
2353 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks
[] = {
2354 { .role
= "refclk960m", .clk
= "usb_otg_ss2_refclk960m" },
2357 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod
= {
2358 .name
= "usb_otg_ss2",
2359 .class = &dra7xx_usb_otg_ss_hwmod_class
,
2360 .clkdm_name
= "l3init_clkdm",
2361 .main_clk
= "dpll_core_h13x2_ck",
2364 .clkctrl_offs
= DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET
,
2365 .context_offs
= DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET
,
2366 .modulemode
= MODULEMODE_HWCTRL
,
2369 .opt_clks
= usb_otg_ss2_opt_clks
,
2370 .opt_clks_cnt
= ARRAY_SIZE(usb_otg_ss2_opt_clks
),
2374 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod
= {
2375 .name
= "usb_otg_ss3",
2376 .class = &dra7xx_usb_otg_ss_hwmod_class
,
2377 .clkdm_name
= "l3init_clkdm",
2378 .main_clk
= "dpll_core_h13x2_ck",
2381 .clkctrl_offs
= DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET
,
2382 .context_offs
= DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET
,
2383 .modulemode
= MODULEMODE_HWCTRL
,
2389 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod
= {
2390 .name
= "usb_otg_ss4",
2391 .class = &dra7xx_usb_otg_ss_hwmod_class
,
2392 .clkdm_name
= "l3init_clkdm",
2393 .main_clk
= "dpll_core_h13x2_ck",
2396 .clkctrl_offs
= DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET
,
2397 .context_offs
= DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET
,
2398 .modulemode
= MODULEMODE_HWCTRL
,
2408 static struct omap_hwmod_class dra7xx_vcp_hwmod_class
= {
2413 static struct omap_hwmod dra7xx_vcp1_hwmod
= {
2415 .class = &dra7xx_vcp_hwmod_class
,
2416 .clkdm_name
= "l3main1_clkdm",
2417 .main_clk
= "l3_iclk_div",
2420 .clkctrl_offs
= DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET
,
2421 .context_offs
= DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET
,
2427 static struct omap_hwmod dra7xx_vcp2_hwmod
= {
2429 .class = &dra7xx_vcp_hwmod_class
,
2430 .clkdm_name
= "l3main1_clkdm",
2431 .main_clk
= "l3_iclk_div",
2434 .clkctrl_offs
= DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET
,
2435 .context_offs
= DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET
,
2445 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc
= {
2447 .sysc_offs
= 0x0010,
2448 .syss_offs
= 0x0014,
2449 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_SIDLEMODE
|
2450 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
2451 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2453 .sysc_fields
= &omap_hwmod_sysc_type1
,
2456 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class
= {
2458 .sysc
= &dra7xx_wd_timer_sysc
,
2459 .pre_shutdown
= &omap2_wd_timer_disable
,
2460 .reset
= &omap2_wd_timer_reset
,
2464 static struct omap_hwmod dra7xx_wd_timer2_hwmod
= {
2465 .name
= "wd_timer2",
2466 .class = &dra7xx_wd_timer_hwmod_class
,
2467 .clkdm_name
= "wkupaon_clkdm",
2468 .main_clk
= "sys_32k_ck",
2471 .clkctrl_offs
= DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET
,
2472 .context_offs
= DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET
,
2473 .modulemode
= MODULEMODE_SWCTRL
,
2483 /* l3_main_1 -> dmm */
2484 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm
= {
2485 .master
= &dra7xx_l3_main_1_hwmod
,
2486 .slave
= &dra7xx_dmm_hwmod
,
2487 .clk
= "l3_iclk_div",
2488 .user
= OCP_USER_SDMA
,
2491 /* l3_main_2 -> l3_instr */
2492 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr
= {
2493 .master
= &dra7xx_l3_main_2_hwmod
,
2494 .slave
= &dra7xx_l3_instr_hwmod
,
2495 .clk
= "l3_iclk_div",
2496 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2499 /* l4_cfg -> l3_main_1 */
2500 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1
= {
2501 .master
= &dra7xx_l4_cfg_hwmod
,
2502 .slave
= &dra7xx_l3_main_1_hwmod
,
2503 .clk
= "l3_iclk_div",
2504 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2507 /* mpu -> l3_main_1 */
2508 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1
= {
2509 .master
= &dra7xx_mpu_hwmod
,
2510 .slave
= &dra7xx_l3_main_1_hwmod
,
2511 .clk
= "l3_iclk_div",
2512 .user
= OCP_USER_MPU
,
2515 /* l3_main_1 -> l3_main_2 */
2516 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2
= {
2517 .master
= &dra7xx_l3_main_1_hwmod
,
2518 .slave
= &dra7xx_l3_main_2_hwmod
,
2519 .clk
= "l3_iclk_div",
2520 .user
= OCP_USER_MPU
,
2523 /* l4_cfg -> l3_main_2 */
2524 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2
= {
2525 .master
= &dra7xx_l4_cfg_hwmod
,
2526 .slave
= &dra7xx_l3_main_2_hwmod
,
2527 .clk
= "l3_iclk_div",
2528 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2531 /* l3_main_1 -> l4_cfg */
2532 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg
= {
2533 .master
= &dra7xx_l3_main_1_hwmod
,
2534 .slave
= &dra7xx_l4_cfg_hwmod
,
2535 .clk
= "l3_iclk_div",
2536 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2539 /* l3_main_1 -> l4_per1 */
2540 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1
= {
2541 .master
= &dra7xx_l3_main_1_hwmod
,
2542 .slave
= &dra7xx_l4_per1_hwmod
,
2543 .clk
= "l3_iclk_div",
2544 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2547 /* l3_main_1 -> l4_per2 */
2548 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2
= {
2549 .master
= &dra7xx_l3_main_1_hwmod
,
2550 .slave
= &dra7xx_l4_per2_hwmod
,
2551 .clk
= "l3_iclk_div",
2552 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2555 /* l3_main_1 -> l4_per3 */
2556 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3
= {
2557 .master
= &dra7xx_l3_main_1_hwmod
,
2558 .slave
= &dra7xx_l4_per3_hwmod
,
2559 .clk
= "l3_iclk_div",
2560 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2563 /* l3_main_1 -> l4_wkup */
2564 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup
= {
2565 .master
= &dra7xx_l3_main_1_hwmod
,
2566 .slave
= &dra7xx_l4_wkup_hwmod
,
2567 .clk
= "wkupaon_iclk_mux",
2568 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2571 /* l4_per2 -> atl */
2572 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl
= {
2573 .master
= &dra7xx_l4_per2_hwmod
,
2574 .slave
= &dra7xx_atl_hwmod
,
2575 .clk
= "l3_iclk_div",
2576 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2579 /* l3_main_1 -> bb2d */
2580 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d
= {
2581 .master
= &dra7xx_l3_main_1_hwmod
,
2582 .slave
= &dra7xx_bb2d_hwmod
,
2583 .clk
= "l3_iclk_div",
2584 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2587 /* l4_wkup -> counter_32k */
2588 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k
= {
2589 .master
= &dra7xx_l4_wkup_hwmod
,
2590 .slave
= &dra7xx_counter_32k_hwmod
,
2591 .clk
= "wkupaon_iclk_mux",
2592 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2595 /* l4_wkup -> ctrl_module_wkup */
2596 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup
= {
2597 .master
= &dra7xx_l4_wkup_hwmod
,
2598 .slave
= &dra7xx_ctrl_module_wkup_hwmod
,
2599 .clk
= "wkupaon_iclk_mux",
2600 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2603 static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0
= {
2604 .master
= &dra7xx_l4_per2_hwmod
,
2605 .slave
= &dra7xx_gmac_hwmod
,
2606 .clk
= "dpll_gmac_ck",
2607 .user
= OCP_USER_MPU
,
2610 static struct omap_hwmod_ocp_if dra7xx_gmac__mdio
= {
2611 .master
= &dra7xx_gmac_hwmod
,
2612 .slave
= &dra7xx_mdio_hwmod
,
2613 .user
= OCP_USER_MPU
,
2616 /* l4_wkup -> dcan1 */
2617 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1
= {
2618 .master
= &dra7xx_l4_wkup_hwmod
,
2619 .slave
= &dra7xx_dcan1_hwmod
,
2620 .clk
= "wkupaon_iclk_mux",
2621 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2624 /* l4_per2 -> dcan2 */
2625 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2
= {
2626 .master
= &dra7xx_l4_per2_hwmod
,
2627 .slave
= &dra7xx_dcan2_hwmod
,
2628 .clk
= "l3_iclk_div",
2629 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2632 static struct omap_hwmod_addr_space dra7xx_dma_system_addrs
[] = {
2634 .pa_start
= 0x4a056000,
2635 .pa_end
= 0x4a056fff,
2636 .flags
= ADDR_TYPE_RT
2641 /* l4_cfg -> dma_system */
2642 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system
= {
2643 .master
= &dra7xx_l4_cfg_hwmod
,
2644 .slave
= &dra7xx_dma_system_hwmod
,
2645 .clk
= "l3_iclk_div",
2646 .addr
= dra7xx_dma_system_addrs
,
2647 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2650 /* l3_main_1 -> tpcc */
2651 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc
= {
2652 .master
= &dra7xx_l3_main_1_hwmod
,
2653 .slave
= &dra7xx_tpcc_hwmod
,
2654 .clk
= "l3_iclk_div",
2655 .user
= OCP_USER_MPU
,
2658 /* l3_main_1 -> tptc0 */
2659 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc0
= {
2660 .master
= &dra7xx_l3_main_1_hwmod
,
2661 .slave
= &dra7xx_tptc0_hwmod
,
2662 .clk
= "l3_iclk_div",
2663 .user
= OCP_USER_MPU
,
2666 /* l3_main_1 -> tptc1 */
2667 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1
= {
2668 .master
= &dra7xx_l3_main_1_hwmod
,
2669 .slave
= &dra7xx_tptc1_hwmod
,
2670 .clk
= "l3_iclk_div",
2671 .user
= OCP_USER_MPU
,
2674 static struct omap_hwmod_addr_space dra7xx_dss_addrs
[] = {
2677 .pa_start
= 0x58000000,
2678 .pa_end
= 0x5800007f,
2679 .flags
= ADDR_TYPE_RT
2683 /* l3_main_1 -> dss */
2684 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss
= {
2685 .master
= &dra7xx_l3_main_1_hwmod
,
2686 .slave
= &dra7xx_dss_hwmod
,
2687 .clk
= "l3_iclk_div",
2688 .addr
= dra7xx_dss_addrs
,
2689 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2692 static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs
[] = {
2695 .pa_start
= 0x58001000,
2696 .pa_end
= 0x58001fff,
2697 .flags
= ADDR_TYPE_RT
2701 /* l3_main_1 -> dispc */
2702 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc
= {
2703 .master
= &dra7xx_l3_main_1_hwmod
,
2704 .slave
= &dra7xx_dss_dispc_hwmod
,
2705 .clk
= "l3_iclk_div",
2706 .addr
= dra7xx_dss_dispc_addrs
,
2707 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2710 static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs
[] = {
2713 .pa_start
= 0x58040000,
2714 .pa_end
= 0x580400ff,
2715 .flags
= ADDR_TYPE_RT
2720 /* l3_main_1 -> dispc */
2721 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi
= {
2722 .master
= &dra7xx_l3_main_1_hwmod
,
2723 .slave
= &dra7xx_dss_hdmi_hwmod
,
2724 .clk
= "l3_iclk_div",
2725 .addr
= dra7xx_dss_hdmi_addrs
,
2726 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2729 /* l4_per2 -> mcasp3 */
2730 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3
= {
2731 .master
= &dra7xx_l4_per2_hwmod
,
2732 .slave
= &dra7xx_mcasp3_hwmod
,
2733 .clk
= "l4_root_clk_div",
2734 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2737 /* l3_main_1 -> mcasp3 */
2738 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3
= {
2739 .master
= &dra7xx_l3_main_1_hwmod
,
2740 .slave
= &dra7xx_mcasp3_hwmod
,
2741 .clk
= "l3_iclk_div",
2742 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2745 /* l4_per1 -> elm */
2746 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm
= {
2747 .master
= &dra7xx_l4_per1_hwmod
,
2748 .slave
= &dra7xx_elm_hwmod
,
2749 .clk
= "l3_iclk_div",
2750 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2753 /* l4_wkup -> gpio1 */
2754 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1
= {
2755 .master
= &dra7xx_l4_wkup_hwmod
,
2756 .slave
= &dra7xx_gpio1_hwmod
,
2757 .clk
= "wkupaon_iclk_mux",
2758 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2761 /* l4_per1 -> gpio2 */
2762 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2
= {
2763 .master
= &dra7xx_l4_per1_hwmod
,
2764 .slave
= &dra7xx_gpio2_hwmod
,
2765 .clk
= "l3_iclk_div",
2766 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2769 /* l4_per1 -> gpio3 */
2770 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3
= {
2771 .master
= &dra7xx_l4_per1_hwmod
,
2772 .slave
= &dra7xx_gpio3_hwmod
,
2773 .clk
= "l3_iclk_div",
2774 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2777 /* l4_per1 -> gpio4 */
2778 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4
= {
2779 .master
= &dra7xx_l4_per1_hwmod
,
2780 .slave
= &dra7xx_gpio4_hwmod
,
2781 .clk
= "l3_iclk_div",
2782 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2785 /* l4_per1 -> gpio5 */
2786 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5
= {
2787 .master
= &dra7xx_l4_per1_hwmod
,
2788 .slave
= &dra7xx_gpio5_hwmod
,
2789 .clk
= "l3_iclk_div",
2790 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2793 /* l4_per1 -> gpio6 */
2794 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6
= {
2795 .master
= &dra7xx_l4_per1_hwmod
,
2796 .slave
= &dra7xx_gpio6_hwmod
,
2797 .clk
= "l3_iclk_div",
2798 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2801 /* l4_per1 -> gpio7 */
2802 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7
= {
2803 .master
= &dra7xx_l4_per1_hwmod
,
2804 .slave
= &dra7xx_gpio7_hwmod
,
2805 .clk
= "l3_iclk_div",
2806 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2809 /* l4_per1 -> gpio8 */
2810 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8
= {
2811 .master
= &dra7xx_l4_per1_hwmod
,
2812 .slave
= &dra7xx_gpio8_hwmod
,
2813 .clk
= "l3_iclk_div",
2814 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2817 /* l3_main_1 -> gpmc */
2818 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc
= {
2819 .master
= &dra7xx_l3_main_1_hwmod
,
2820 .slave
= &dra7xx_gpmc_hwmod
,
2821 .clk
= "l3_iclk_div",
2822 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2825 static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs
[] = {
2827 .pa_start
= 0x480b2000,
2828 .pa_end
= 0x480b201f,
2829 .flags
= ADDR_TYPE_RT
2834 /* l4_per1 -> hdq1w */
2835 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w
= {
2836 .master
= &dra7xx_l4_per1_hwmod
,
2837 .slave
= &dra7xx_hdq1w_hwmod
,
2838 .clk
= "l3_iclk_div",
2839 .addr
= dra7xx_hdq1w_addrs
,
2840 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2843 /* l4_per1 -> i2c1 */
2844 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1
= {
2845 .master
= &dra7xx_l4_per1_hwmod
,
2846 .slave
= &dra7xx_i2c1_hwmod
,
2847 .clk
= "l3_iclk_div",
2848 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2851 /* l4_per1 -> i2c2 */
2852 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2
= {
2853 .master
= &dra7xx_l4_per1_hwmod
,
2854 .slave
= &dra7xx_i2c2_hwmod
,
2855 .clk
= "l3_iclk_div",
2856 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2859 /* l4_per1 -> i2c3 */
2860 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3
= {
2861 .master
= &dra7xx_l4_per1_hwmod
,
2862 .slave
= &dra7xx_i2c3_hwmod
,
2863 .clk
= "l3_iclk_div",
2864 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2867 /* l4_per1 -> i2c4 */
2868 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4
= {
2869 .master
= &dra7xx_l4_per1_hwmod
,
2870 .slave
= &dra7xx_i2c4_hwmod
,
2871 .clk
= "l3_iclk_div",
2872 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2875 /* l4_per1 -> i2c5 */
2876 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5
= {
2877 .master
= &dra7xx_l4_per1_hwmod
,
2878 .slave
= &dra7xx_i2c5_hwmod
,
2879 .clk
= "l3_iclk_div",
2880 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2883 /* l4_cfg -> mailbox1 */
2884 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1
= {
2885 .master
= &dra7xx_l4_cfg_hwmod
,
2886 .slave
= &dra7xx_mailbox1_hwmod
,
2887 .clk
= "l3_iclk_div",
2888 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2891 /* l4_per3 -> mailbox2 */
2892 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2
= {
2893 .master
= &dra7xx_l4_per3_hwmod
,
2894 .slave
= &dra7xx_mailbox2_hwmod
,
2895 .clk
= "l3_iclk_div",
2896 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2899 /* l4_per3 -> mailbox3 */
2900 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3
= {
2901 .master
= &dra7xx_l4_per3_hwmod
,
2902 .slave
= &dra7xx_mailbox3_hwmod
,
2903 .clk
= "l3_iclk_div",
2904 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2907 /* l4_per3 -> mailbox4 */
2908 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4
= {
2909 .master
= &dra7xx_l4_per3_hwmod
,
2910 .slave
= &dra7xx_mailbox4_hwmod
,
2911 .clk
= "l3_iclk_div",
2912 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2915 /* l4_per3 -> mailbox5 */
2916 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5
= {
2917 .master
= &dra7xx_l4_per3_hwmod
,
2918 .slave
= &dra7xx_mailbox5_hwmod
,
2919 .clk
= "l3_iclk_div",
2920 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2923 /* l4_per3 -> mailbox6 */
2924 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6
= {
2925 .master
= &dra7xx_l4_per3_hwmod
,
2926 .slave
= &dra7xx_mailbox6_hwmod
,
2927 .clk
= "l3_iclk_div",
2928 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2931 /* l4_per3 -> mailbox7 */
2932 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7
= {
2933 .master
= &dra7xx_l4_per3_hwmod
,
2934 .slave
= &dra7xx_mailbox7_hwmod
,
2935 .clk
= "l3_iclk_div",
2936 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2939 /* l4_per3 -> mailbox8 */
2940 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8
= {
2941 .master
= &dra7xx_l4_per3_hwmod
,
2942 .slave
= &dra7xx_mailbox8_hwmod
,
2943 .clk
= "l3_iclk_div",
2944 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2947 /* l4_per3 -> mailbox9 */
2948 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9
= {
2949 .master
= &dra7xx_l4_per3_hwmod
,
2950 .slave
= &dra7xx_mailbox9_hwmod
,
2951 .clk
= "l3_iclk_div",
2952 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2955 /* l4_per3 -> mailbox10 */
2956 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10
= {
2957 .master
= &dra7xx_l4_per3_hwmod
,
2958 .slave
= &dra7xx_mailbox10_hwmod
,
2959 .clk
= "l3_iclk_div",
2960 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2963 /* l4_per3 -> mailbox11 */
2964 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11
= {
2965 .master
= &dra7xx_l4_per3_hwmod
,
2966 .slave
= &dra7xx_mailbox11_hwmod
,
2967 .clk
= "l3_iclk_div",
2968 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2971 /* l4_per3 -> mailbox12 */
2972 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12
= {
2973 .master
= &dra7xx_l4_per3_hwmod
,
2974 .slave
= &dra7xx_mailbox12_hwmod
,
2975 .clk
= "l3_iclk_div",
2976 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2979 /* l4_per3 -> mailbox13 */
2980 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13
= {
2981 .master
= &dra7xx_l4_per3_hwmod
,
2982 .slave
= &dra7xx_mailbox13_hwmod
,
2983 .clk
= "l3_iclk_div",
2984 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2987 /* l4_per1 -> mcspi1 */
2988 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1
= {
2989 .master
= &dra7xx_l4_per1_hwmod
,
2990 .slave
= &dra7xx_mcspi1_hwmod
,
2991 .clk
= "l3_iclk_div",
2992 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2995 /* l4_per1 -> mcspi2 */
2996 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2
= {
2997 .master
= &dra7xx_l4_per1_hwmod
,
2998 .slave
= &dra7xx_mcspi2_hwmod
,
2999 .clk
= "l3_iclk_div",
3000 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3003 /* l4_per1 -> mcspi3 */
3004 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3
= {
3005 .master
= &dra7xx_l4_per1_hwmod
,
3006 .slave
= &dra7xx_mcspi3_hwmod
,
3007 .clk
= "l3_iclk_div",
3008 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3011 /* l4_per1 -> mcspi4 */
3012 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4
= {
3013 .master
= &dra7xx_l4_per1_hwmod
,
3014 .slave
= &dra7xx_mcspi4_hwmod
,
3015 .clk
= "l3_iclk_div",
3016 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3019 /* l4_per1 -> mmc1 */
3020 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1
= {
3021 .master
= &dra7xx_l4_per1_hwmod
,
3022 .slave
= &dra7xx_mmc1_hwmod
,
3023 .clk
= "l3_iclk_div",
3024 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3027 /* l4_per1 -> mmc2 */
3028 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2
= {
3029 .master
= &dra7xx_l4_per1_hwmod
,
3030 .slave
= &dra7xx_mmc2_hwmod
,
3031 .clk
= "l3_iclk_div",
3032 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3035 /* l4_per1 -> mmc3 */
3036 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3
= {
3037 .master
= &dra7xx_l4_per1_hwmod
,
3038 .slave
= &dra7xx_mmc3_hwmod
,
3039 .clk
= "l3_iclk_div",
3040 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3043 /* l4_per1 -> mmc4 */
3044 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4
= {
3045 .master
= &dra7xx_l4_per1_hwmod
,
3046 .slave
= &dra7xx_mmc4_hwmod
,
3047 .clk
= "l3_iclk_div",
3048 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3052 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu
= {
3053 .master
= &dra7xx_l4_cfg_hwmod
,
3054 .slave
= &dra7xx_mpu_hwmod
,
3055 .clk
= "l3_iclk_div",
3056 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3059 /* l4_cfg -> ocp2scp1 */
3060 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1
= {
3061 .master
= &dra7xx_l4_cfg_hwmod
,
3062 .slave
= &dra7xx_ocp2scp1_hwmod
,
3063 .clk
= "l4_root_clk_div",
3064 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3067 /* l4_cfg -> ocp2scp3 */
3068 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3
= {
3069 .master
= &dra7xx_l4_cfg_hwmod
,
3070 .slave
= &dra7xx_ocp2scp3_hwmod
,
3071 .clk
= "l4_root_clk_div",
3072 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3075 /* l3_main_1 -> pciess1 */
3076 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1
= {
3077 .master
= &dra7xx_l3_main_1_hwmod
,
3078 .slave
= &dra7xx_pciess1_hwmod
,
3079 .clk
= "l3_iclk_div",
3080 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3083 /* l4_cfg -> pciess1 */
3084 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1
= {
3085 .master
= &dra7xx_l4_cfg_hwmod
,
3086 .slave
= &dra7xx_pciess1_hwmod
,
3087 .clk
= "l4_root_clk_div",
3088 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3091 /* l3_main_1 -> pciess2 */
3092 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2
= {
3093 .master
= &dra7xx_l3_main_1_hwmod
,
3094 .slave
= &dra7xx_pciess2_hwmod
,
3095 .clk
= "l3_iclk_div",
3096 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3099 /* l4_cfg -> pciess2 */
3100 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2
= {
3101 .master
= &dra7xx_l4_cfg_hwmod
,
3102 .slave
= &dra7xx_pciess2_hwmod
,
3103 .clk
= "l4_root_clk_div",
3104 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3107 static struct omap_hwmod_addr_space dra7xx_qspi_addrs
[] = {
3109 .pa_start
= 0x4b300000,
3110 .pa_end
= 0x4b30007f,
3111 .flags
= ADDR_TYPE_RT
3116 /* l3_main_1 -> qspi */
3117 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi
= {
3118 .master
= &dra7xx_l3_main_1_hwmod
,
3119 .slave
= &dra7xx_qspi_hwmod
,
3120 .clk
= "l3_iclk_div",
3121 .addr
= dra7xx_qspi_addrs
,
3122 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3125 /* l4_per3 -> rtcss */
3126 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss
= {
3127 .master
= &dra7xx_l4_per3_hwmod
,
3128 .slave
= &dra7xx_rtcss_hwmod
,
3129 .clk
= "l4_root_clk_div",
3130 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3133 static struct omap_hwmod_addr_space dra7xx_sata_addrs
[] = {
3136 .pa_start
= 0x4a141100,
3137 .pa_end
= 0x4a141107,
3138 .flags
= ADDR_TYPE_RT
3143 /* l4_cfg -> sata */
3144 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata
= {
3145 .master
= &dra7xx_l4_cfg_hwmod
,
3146 .slave
= &dra7xx_sata_hwmod
,
3147 .clk
= "l3_iclk_div",
3148 .addr
= dra7xx_sata_addrs
,
3149 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3152 static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs
[] = {
3154 .pa_start
= 0x4a0dd000,
3155 .pa_end
= 0x4a0dd07f,
3156 .flags
= ADDR_TYPE_RT
3161 /* l4_cfg -> smartreflex_core */
3162 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core
= {
3163 .master
= &dra7xx_l4_cfg_hwmod
,
3164 .slave
= &dra7xx_smartreflex_core_hwmod
,
3165 .clk
= "l4_root_clk_div",
3166 .addr
= dra7xx_smartreflex_core_addrs
,
3167 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3170 static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs
[] = {
3172 .pa_start
= 0x4a0d9000,
3173 .pa_end
= 0x4a0d907f,
3174 .flags
= ADDR_TYPE_RT
3179 /* l4_cfg -> smartreflex_mpu */
3180 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu
= {
3181 .master
= &dra7xx_l4_cfg_hwmod
,
3182 .slave
= &dra7xx_smartreflex_mpu_hwmod
,
3183 .clk
= "l4_root_clk_div",
3184 .addr
= dra7xx_smartreflex_mpu_addrs
,
3185 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3188 /* l4_cfg -> spinlock */
3189 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock
= {
3190 .master
= &dra7xx_l4_cfg_hwmod
,
3191 .slave
= &dra7xx_spinlock_hwmod
,
3192 .clk
= "l3_iclk_div",
3193 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3196 /* l4_wkup -> timer1 */
3197 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1
= {
3198 .master
= &dra7xx_l4_wkup_hwmod
,
3199 .slave
= &dra7xx_timer1_hwmod
,
3200 .clk
= "wkupaon_iclk_mux",
3201 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3204 /* l4_per1 -> timer2 */
3205 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2
= {
3206 .master
= &dra7xx_l4_per1_hwmod
,
3207 .slave
= &dra7xx_timer2_hwmod
,
3208 .clk
= "l3_iclk_div",
3209 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3212 /* l4_per1 -> timer3 */
3213 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3
= {
3214 .master
= &dra7xx_l4_per1_hwmod
,
3215 .slave
= &dra7xx_timer3_hwmod
,
3216 .clk
= "l3_iclk_div",
3217 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3220 /* l4_per1 -> timer4 */
3221 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4
= {
3222 .master
= &dra7xx_l4_per1_hwmod
,
3223 .slave
= &dra7xx_timer4_hwmod
,
3224 .clk
= "l3_iclk_div",
3225 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3228 /* l4_per3 -> timer5 */
3229 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5
= {
3230 .master
= &dra7xx_l4_per3_hwmod
,
3231 .slave
= &dra7xx_timer5_hwmod
,
3232 .clk
= "l3_iclk_div",
3233 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3236 /* l4_per3 -> timer6 */
3237 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6
= {
3238 .master
= &dra7xx_l4_per3_hwmod
,
3239 .slave
= &dra7xx_timer6_hwmod
,
3240 .clk
= "l3_iclk_div",
3241 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3244 /* l4_per3 -> timer7 */
3245 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7
= {
3246 .master
= &dra7xx_l4_per3_hwmod
,
3247 .slave
= &dra7xx_timer7_hwmod
,
3248 .clk
= "l3_iclk_div",
3249 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3252 /* l4_per3 -> timer8 */
3253 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8
= {
3254 .master
= &dra7xx_l4_per3_hwmod
,
3255 .slave
= &dra7xx_timer8_hwmod
,
3256 .clk
= "l3_iclk_div",
3257 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3260 /* l4_per1 -> timer9 */
3261 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9
= {
3262 .master
= &dra7xx_l4_per1_hwmod
,
3263 .slave
= &dra7xx_timer9_hwmod
,
3264 .clk
= "l3_iclk_div",
3265 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3268 /* l4_per1 -> timer10 */
3269 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10
= {
3270 .master
= &dra7xx_l4_per1_hwmod
,
3271 .slave
= &dra7xx_timer10_hwmod
,
3272 .clk
= "l3_iclk_div",
3273 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3276 /* l4_per1 -> timer11 */
3277 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11
= {
3278 .master
= &dra7xx_l4_per1_hwmod
,
3279 .slave
= &dra7xx_timer11_hwmod
,
3280 .clk
= "l3_iclk_div",
3281 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3284 /* l4_per3 -> timer13 */
3285 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13
= {
3286 .master
= &dra7xx_l4_per3_hwmod
,
3287 .slave
= &dra7xx_timer13_hwmod
,
3288 .clk
= "l3_iclk_div",
3289 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3292 /* l4_per3 -> timer14 */
3293 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14
= {
3294 .master
= &dra7xx_l4_per3_hwmod
,
3295 .slave
= &dra7xx_timer14_hwmod
,
3296 .clk
= "l3_iclk_div",
3297 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3300 /* l4_per3 -> timer15 */
3301 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15
= {
3302 .master
= &dra7xx_l4_per3_hwmod
,
3303 .slave
= &dra7xx_timer15_hwmod
,
3304 .clk
= "l3_iclk_div",
3305 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3308 /* l4_per3 -> timer16 */
3309 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16
= {
3310 .master
= &dra7xx_l4_per3_hwmod
,
3311 .slave
= &dra7xx_timer16_hwmod
,
3312 .clk
= "l3_iclk_div",
3313 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3316 /* l4_per1 -> uart1 */
3317 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1
= {
3318 .master
= &dra7xx_l4_per1_hwmod
,
3319 .slave
= &dra7xx_uart1_hwmod
,
3320 .clk
= "l3_iclk_div",
3321 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3324 /* l4_per1 -> uart2 */
3325 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2
= {
3326 .master
= &dra7xx_l4_per1_hwmod
,
3327 .slave
= &dra7xx_uart2_hwmod
,
3328 .clk
= "l3_iclk_div",
3329 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3332 /* l4_per1 -> uart3 */
3333 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3
= {
3334 .master
= &dra7xx_l4_per1_hwmod
,
3335 .slave
= &dra7xx_uart3_hwmod
,
3336 .clk
= "l3_iclk_div",
3337 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3340 /* l4_per1 -> uart4 */
3341 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4
= {
3342 .master
= &dra7xx_l4_per1_hwmod
,
3343 .slave
= &dra7xx_uart4_hwmod
,
3344 .clk
= "l3_iclk_div",
3345 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3348 /* l4_per1 -> uart5 */
3349 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5
= {
3350 .master
= &dra7xx_l4_per1_hwmod
,
3351 .slave
= &dra7xx_uart5_hwmod
,
3352 .clk
= "l3_iclk_div",
3353 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3356 /* l4_per1 -> uart6 */
3357 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6
= {
3358 .master
= &dra7xx_l4_per1_hwmod
,
3359 .slave
= &dra7xx_uart6_hwmod
,
3360 .clk
= "l3_iclk_div",
3361 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3364 /* l4_per2 -> uart7 */
3365 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7
= {
3366 .master
= &dra7xx_l4_per2_hwmod
,
3367 .slave
= &dra7xx_uart7_hwmod
,
3368 .clk
= "l3_iclk_div",
3369 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3372 /* l4_per2 -> uart8 */
3373 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8
= {
3374 .master
= &dra7xx_l4_per2_hwmod
,
3375 .slave
= &dra7xx_uart8_hwmod
,
3376 .clk
= "l3_iclk_div",
3377 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3380 /* l4_per2 -> uart9 */
3381 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9
= {
3382 .master
= &dra7xx_l4_per2_hwmod
,
3383 .slave
= &dra7xx_uart9_hwmod
,
3384 .clk
= "l3_iclk_div",
3385 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3388 /* l4_wkup -> uart10 */
3389 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10
= {
3390 .master
= &dra7xx_l4_wkup_hwmod
,
3391 .slave
= &dra7xx_uart10_hwmod
,
3392 .clk
= "wkupaon_iclk_mux",
3393 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3396 /* l4_per3 -> usb_otg_ss1 */
3397 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1
= {
3398 .master
= &dra7xx_l4_per3_hwmod
,
3399 .slave
= &dra7xx_usb_otg_ss1_hwmod
,
3400 .clk
= "dpll_core_h13x2_ck",
3401 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3404 /* l4_per3 -> usb_otg_ss2 */
3405 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2
= {
3406 .master
= &dra7xx_l4_per3_hwmod
,
3407 .slave
= &dra7xx_usb_otg_ss2_hwmod
,
3408 .clk
= "dpll_core_h13x2_ck",
3409 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3412 /* l4_per3 -> usb_otg_ss3 */
3413 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3
= {
3414 .master
= &dra7xx_l4_per3_hwmod
,
3415 .slave
= &dra7xx_usb_otg_ss3_hwmod
,
3416 .clk
= "dpll_core_h13x2_ck",
3417 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3420 /* l4_per3 -> usb_otg_ss4 */
3421 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4
= {
3422 .master
= &dra7xx_l4_per3_hwmod
,
3423 .slave
= &dra7xx_usb_otg_ss4_hwmod
,
3424 .clk
= "dpll_core_h13x2_ck",
3425 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3428 /* l3_main_1 -> vcp1 */
3429 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1
= {
3430 .master
= &dra7xx_l3_main_1_hwmod
,
3431 .slave
= &dra7xx_vcp1_hwmod
,
3432 .clk
= "l3_iclk_div",
3433 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3436 /* l4_per2 -> vcp1 */
3437 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1
= {
3438 .master
= &dra7xx_l4_per2_hwmod
,
3439 .slave
= &dra7xx_vcp1_hwmod
,
3440 .clk
= "l3_iclk_div",
3441 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3444 /* l3_main_1 -> vcp2 */
3445 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2
= {
3446 .master
= &dra7xx_l3_main_1_hwmod
,
3447 .slave
= &dra7xx_vcp2_hwmod
,
3448 .clk
= "l3_iclk_div",
3449 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3452 /* l4_per2 -> vcp2 */
3453 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2
= {
3454 .master
= &dra7xx_l4_per2_hwmod
,
3455 .slave
= &dra7xx_vcp2_hwmod
,
3456 .clk
= "l3_iclk_div",
3457 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3460 /* l4_wkup -> wd_timer2 */
3461 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2
= {
3462 .master
= &dra7xx_l4_wkup_hwmod
,
3463 .slave
= &dra7xx_wd_timer2_hwmod
,
3464 .clk
= "wkupaon_iclk_mux",
3465 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3468 static struct omap_hwmod_ocp_if
*dra7xx_hwmod_ocp_ifs
[] __initdata
= {
3469 &dra7xx_l3_main_1__dmm
,
3470 &dra7xx_l3_main_2__l3_instr
,
3471 &dra7xx_l4_cfg__l3_main_1
,
3472 &dra7xx_mpu__l3_main_1
,
3473 &dra7xx_l3_main_1__l3_main_2
,
3474 &dra7xx_l4_cfg__l3_main_2
,
3475 &dra7xx_l3_main_1__l4_cfg
,
3476 &dra7xx_l3_main_1__l4_per1
,
3477 &dra7xx_l3_main_1__l4_per2
,
3478 &dra7xx_l3_main_1__l4_per3
,
3479 &dra7xx_l3_main_1__l4_wkup
,
3480 &dra7xx_l4_per2__atl
,
3481 &dra7xx_l3_main_1__bb2d
,
3482 &dra7xx_l4_wkup__counter_32k
,
3483 &dra7xx_l4_wkup__ctrl_module_wkup
,
3484 &dra7xx_l4_wkup__dcan1
,
3485 &dra7xx_l4_per2__dcan2
,
3486 &dra7xx_l4_per2__cpgmac0
,
3487 &dra7xx_l4_per2__mcasp3
,
3488 &dra7xx_l3_main_1__mcasp3
,
3490 &dra7xx_l4_cfg__dma_system
,
3491 &dra7xx_l3_main_1__tpcc
,
3492 &dra7xx_l3_main_1__tptc0
,
3493 &dra7xx_l3_main_1__tptc1
,
3494 &dra7xx_l3_main_1__dss
,
3495 &dra7xx_l3_main_1__dispc
,
3496 &dra7xx_l3_main_1__hdmi
,
3497 &dra7xx_l4_per1__elm
,
3498 &dra7xx_l4_wkup__gpio1
,
3499 &dra7xx_l4_per1__gpio2
,
3500 &dra7xx_l4_per1__gpio3
,
3501 &dra7xx_l4_per1__gpio4
,
3502 &dra7xx_l4_per1__gpio5
,
3503 &dra7xx_l4_per1__gpio6
,
3504 &dra7xx_l4_per1__gpio7
,
3505 &dra7xx_l4_per1__gpio8
,
3506 &dra7xx_l3_main_1__gpmc
,
3507 &dra7xx_l4_per1__hdq1w
,
3508 &dra7xx_l4_per1__i2c1
,
3509 &dra7xx_l4_per1__i2c2
,
3510 &dra7xx_l4_per1__i2c3
,
3511 &dra7xx_l4_per1__i2c4
,
3512 &dra7xx_l4_per1__i2c5
,
3513 &dra7xx_l4_cfg__mailbox1
,
3514 &dra7xx_l4_per3__mailbox2
,
3515 &dra7xx_l4_per3__mailbox3
,
3516 &dra7xx_l4_per3__mailbox4
,
3517 &dra7xx_l4_per3__mailbox5
,
3518 &dra7xx_l4_per3__mailbox6
,
3519 &dra7xx_l4_per3__mailbox7
,
3520 &dra7xx_l4_per3__mailbox8
,
3521 &dra7xx_l4_per3__mailbox9
,
3522 &dra7xx_l4_per3__mailbox10
,
3523 &dra7xx_l4_per3__mailbox11
,
3524 &dra7xx_l4_per3__mailbox12
,
3525 &dra7xx_l4_per3__mailbox13
,
3526 &dra7xx_l4_per1__mcspi1
,
3527 &dra7xx_l4_per1__mcspi2
,
3528 &dra7xx_l4_per1__mcspi3
,
3529 &dra7xx_l4_per1__mcspi4
,
3530 &dra7xx_l4_per1__mmc1
,
3531 &dra7xx_l4_per1__mmc2
,
3532 &dra7xx_l4_per1__mmc3
,
3533 &dra7xx_l4_per1__mmc4
,
3534 &dra7xx_l4_cfg__mpu
,
3535 &dra7xx_l4_cfg__ocp2scp1
,
3536 &dra7xx_l4_cfg__ocp2scp3
,
3537 &dra7xx_l3_main_1__pciess1
,
3538 &dra7xx_l4_cfg__pciess1
,
3539 &dra7xx_l3_main_1__pciess2
,
3540 &dra7xx_l4_cfg__pciess2
,
3541 &dra7xx_l3_main_1__qspi
,
3542 &dra7xx_l4_per3__rtcss
,
3543 &dra7xx_l4_cfg__sata
,
3544 &dra7xx_l4_cfg__smartreflex_core
,
3545 &dra7xx_l4_cfg__smartreflex_mpu
,
3546 &dra7xx_l4_cfg__spinlock
,
3547 &dra7xx_l4_wkup__timer1
,
3548 &dra7xx_l4_per1__timer2
,
3549 &dra7xx_l4_per1__timer3
,
3550 &dra7xx_l4_per1__timer4
,
3551 &dra7xx_l4_per3__timer5
,
3552 &dra7xx_l4_per3__timer6
,
3553 &dra7xx_l4_per3__timer7
,
3554 &dra7xx_l4_per3__timer8
,
3555 &dra7xx_l4_per1__timer9
,
3556 &dra7xx_l4_per1__timer10
,
3557 &dra7xx_l4_per1__timer11
,
3558 &dra7xx_l4_per3__timer13
,
3559 &dra7xx_l4_per3__timer14
,
3560 &dra7xx_l4_per3__timer15
,
3561 &dra7xx_l4_per3__timer16
,
3562 &dra7xx_l4_per1__uart1
,
3563 &dra7xx_l4_per1__uart2
,
3564 &dra7xx_l4_per1__uart3
,
3565 &dra7xx_l4_per1__uart4
,
3566 &dra7xx_l4_per1__uart5
,
3567 &dra7xx_l4_per1__uart6
,
3568 &dra7xx_l4_per2__uart7
,
3569 &dra7xx_l4_per2__uart8
,
3570 &dra7xx_l4_per2__uart9
,
3571 &dra7xx_l4_wkup__uart10
,
3572 &dra7xx_l4_per3__usb_otg_ss1
,
3573 &dra7xx_l4_per3__usb_otg_ss2
,
3574 &dra7xx_l4_per3__usb_otg_ss3
,
3575 &dra7xx_l3_main_1__vcp1
,
3576 &dra7xx_l4_per2__vcp1
,
3577 &dra7xx_l3_main_1__vcp2
,
3578 &dra7xx_l4_per2__vcp2
,
3579 &dra7xx_l4_wkup__wd_timer2
,
3583 static struct omap_hwmod_ocp_if
*dra74x_hwmod_ocp_ifs
[] __initdata
= {
3584 &dra7xx_l4_per3__usb_otg_ss4
,
3588 static struct omap_hwmod_ocp_if
*dra72x_hwmod_ocp_ifs
[] __initdata
= {
3592 int __init
dra7xx_hwmod_init(void)
3597 ret
= omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs
);
3599 if (!ret
&& soc_is_dra74x())
3600 return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs
);
3601 else if (!ret
&& soc_is_dra72x())
3602 return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs
);