2 * Hardware modules present on the DRA7xx chips
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
21 #include <linux/platform_data/gpio-omap.h>
22 #include <linux/platform_data/hsmmc-omap.h>
23 #include <linux/power/smartreflex.h>
24 #include <linux/i2c-omap.h>
26 #include <linux/omap-dma.h>
27 #include <linux/platform_data/spi-omap2-mcspi.h>
28 #include <linux/platform_data/asoc-ti-mcbsp.h>
29 #include <plat/dmtimer.h>
31 #include "omap_hwmod.h"
32 #include "omap_hwmod_common_data.h"
40 /* Base offset for all DRA7XX interrupts external to MPUSS */
41 #define DRA7XX_IRQ_GIC_START 32
43 /* Base offset for all DRA7XX dma requests */
44 #define DRA7XX_DMA_REQ_START 1
53 * instance(s): l3_instr, l3_main_1, l3_main_2
55 static struct omap_hwmod_class dra7xx_l3_hwmod_class
= {
60 static struct omap_hwmod dra7xx_l3_instr_hwmod
= {
62 .class = &dra7xx_l3_hwmod_class
,
63 .clkdm_name
= "l3instr_clkdm",
66 .clkctrl_offs
= DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET
,
67 .context_offs
= DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET
,
68 .modulemode
= MODULEMODE_HWCTRL
,
74 static struct omap_hwmod dra7xx_l3_main_1_hwmod
= {
76 .class = &dra7xx_l3_hwmod_class
,
77 .clkdm_name
= "l3main1_clkdm",
80 .clkctrl_offs
= DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET
,
81 .context_offs
= DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET
,
87 static struct omap_hwmod dra7xx_l3_main_2_hwmod
= {
89 .class = &dra7xx_l3_hwmod_class
,
90 .clkdm_name
= "l3instr_clkdm",
93 .clkctrl_offs
= DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET
,
94 .context_offs
= DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET
,
95 .modulemode
= MODULEMODE_HWCTRL
,
102 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
104 static struct omap_hwmod_class dra7xx_l4_hwmod_class
= {
109 static struct omap_hwmod dra7xx_l4_cfg_hwmod
= {
111 .class = &dra7xx_l4_hwmod_class
,
112 .clkdm_name
= "l4cfg_clkdm",
115 .clkctrl_offs
= DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET
,
116 .context_offs
= DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET
,
122 static struct omap_hwmod dra7xx_l4_per1_hwmod
= {
124 .class = &dra7xx_l4_hwmod_class
,
125 .clkdm_name
= "l4per_clkdm",
128 .clkctrl_offs
= DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET
,
129 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
135 static struct omap_hwmod dra7xx_l4_per2_hwmod
= {
137 .class = &dra7xx_l4_hwmod_class
,
138 .clkdm_name
= "l4per2_clkdm",
141 .clkctrl_offs
= DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET
,
142 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
148 static struct omap_hwmod dra7xx_l4_per3_hwmod
= {
150 .class = &dra7xx_l4_hwmod_class
,
151 .clkdm_name
= "l4per3_clkdm",
154 .clkctrl_offs
= DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET
,
155 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
161 static struct omap_hwmod dra7xx_l4_wkup_hwmod
= {
163 .class = &dra7xx_l4_hwmod_class
,
164 .clkdm_name
= "wkupaon_clkdm",
167 .clkctrl_offs
= DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET
,
168 .context_offs
= DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET
,
178 static struct omap_hwmod_class dra7xx_atl_hwmod_class
= {
183 static struct omap_hwmod dra7xx_atl_hwmod
= {
185 .class = &dra7xx_atl_hwmod_class
,
186 .clkdm_name
= "atl_clkdm",
187 .main_clk
= "atl_gfclk_mux",
190 .clkctrl_offs
= DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET
,
191 .context_offs
= DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET
,
192 .modulemode
= MODULEMODE_SWCTRL
,
202 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class
= {
207 static struct omap_hwmod dra7xx_bb2d_hwmod
= {
209 .class = &dra7xx_bb2d_hwmod_class
,
210 .clkdm_name
= "dss_clkdm",
211 .main_clk
= "dpll_core_h24x2_ck",
214 .clkctrl_offs
= DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET
,
215 .context_offs
= DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET
,
216 .modulemode
= MODULEMODE_SWCTRL
,
226 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc
= {
229 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
230 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
232 .sysc_fields
= &omap_hwmod_sysc_type1
,
235 static struct omap_hwmod_class dra7xx_counter_hwmod_class
= {
237 .sysc
= &dra7xx_counter_sysc
,
241 static struct omap_hwmod dra7xx_counter_32k_hwmod
= {
242 .name
= "counter_32k",
243 .class = &dra7xx_counter_hwmod_class
,
244 .clkdm_name
= "wkupaon_clkdm",
245 .flags
= HWMOD_SWSUP_SIDLE
,
246 .main_clk
= "wkupaon_iclk_mux",
249 .clkctrl_offs
= DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET
,
250 .context_offs
= DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET
,
256 * 'ctrl_module' class
260 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class
= {
261 .name
= "ctrl_module",
264 /* ctrl_module_wkup */
265 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod
= {
266 .name
= "ctrl_module_wkup",
267 .class = &dra7xx_ctrl_module_hwmod_class
,
268 .clkdm_name
= "wkupaon_clkdm",
271 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
278 * cpsw/gmac sub system
280 static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc
= {
284 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_MIDLEMODE
|
285 SYSS_HAS_RESET_STATUS
),
286 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| MSTANDBY_FORCE
|
288 .sysc_fields
= &omap_hwmod_sysc_type3
,
291 static struct omap_hwmod_class dra7xx_gmac_hwmod_class
= {
293 .sysc
= &dra7xx_gmac_sysc
,
296 static struct omap_hwmod dra7xx_gmac_hwmod
= {
298 .class = &dra7xx_gmac_hwmod_class
,
299 .clkdm_name
= "gmac_clkdm",
300 .flags
= (HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
),
301 .main_clk
= "dpll_gmac_ck",
305 .clkctrl_offs
= DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET
,
306 .context_offs
= DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET
,
307 .modulemode
= MODULEMODE_SWCTRL
,
315 static struct omap_hwmod_class dra7xx_mdio_hwmod_class
= {
316 .name
= "davinci_mdio",
319 static struct omap_hwmod dra7xx_mdio_hwmod
= {
320 .name
= "davinci_mdio",
321 .class = &dra7xx_mdio_hwmod_class
,
322 .clkdm_name
= "gmac_clkdm",
323 .main_clk
= "dpll_gmac_ck",
331 static struct omap_hwmod_class dra7xx_dcan_hwmod_class
= {
336 static struct omap_hwmod dra7xx_dcan1_hwmod
= {
338 .class = &dra7xx_dcan_hwmod_class
,
339 .clkdm_name
= "wkupaon_clkdm",
340 .main_clk
= "dcan1_sys_clk_mux",
343 .clkctrl_offs
= DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET
,
344 .context_offs
= DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET
,
345 .modulemode
= MODULEMODE_SWCTRL
,
351 static struct omap_hwmod dra7xx_dcan2_hwmod
= {
353 .class = &dra7xx_dcan_hwmod_class
,
354 .clkdm_name
= "l4per2_clkdm",
355 .main_clk
= "sys_clkin1",
358 .clkctrl_offs
= DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET
,
359 .context_offs
= DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET
,
360 .modulemode
= MODULEMODE_SWCTRL
,
370 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc
= {
374 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
375 SYSC_HAS_EMUFREE
| SYSC_HAS_MIDLEMODE
|
376 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
377 SYSS_HAS_RESET_STATUS
),
378 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
379 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
380 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
381 .sysc_fields
= &omap_hwmod_sysc_type1
,
384 static struct omap_hwmod_class dra7xx_dma_hwmod_class
= {
386 .sysc
= &dra7xx_dma_sysc
,
390 static struct omap_dma_dev_attr dma_dev_attr
= {
391 .dev_caps
= RESERVE_CHANNEL
| DMA_LINKED_LCH
| GLOBAL_PRIORITY
|
392 IS_CSSA_32
| IS_CDSA_32
| IS_RW_PRIORITY
,
397 static struct omap_hwmod dra7xx_dma_system_hwmod
= {
398 .name
= "dma_system",
399 .class = &dra7xx_dma_hwmod_class
,
400 .clkdm_name
= "dma_clkdm",
401 .main_clk
= "l3_iclk_div",
404 .clkctrl_offs
= DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET
,
405 .context_offs
= DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET
,
408 .dev_attr
= &dma_dev_attr
,
416 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc
= {
419 .sysc_flags
= SYSS_HAS_RESET_STATUS
,
422 static struct omap_hwmod_class dra7xx_dss_hwmod_class
= {
424 .sysc
= &dra7xx_dss_sysc
,
425 .reset
= omap_dss_reset
,
429 static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs
[] = {
430 { .dma_req
= 75 + DRA7XX_DMA_REQ_START
},
434 static struct omap_hwmod_opt_clk dss_opt_clks
[] = {
435 { .role
= "dss_clk", .clk
= "dss_dss_clk" },
436 { .role
= "hdmi_phy_clk", .clk
= "dss_48mhz_clk" },
437 { .role
= "32khz_clk", .clk
= "dss_32khz_clk" },
438 { .role
= "video2_clk", .clk
= "dss_video2_clk" },
439 { .role
= "video1_clk", .clk
= "dss_video1_clk" },
440 { .role
= "hdmi_clk", .clk
= "dss_hdmi_clk" },
443 static struct omap_hwmod dra7xx_dss_hwmod
= {
445 .class = &dra7xx_dss_hwmod_class
,
446 .clkdm_name
= "dss_clkdm",
447 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
448 .sdma_reqs
= dra7xx_dss_sdma_reqs
,
449 .main_clk
= "dss_dss_clk",
452 .clkctrl_offs
= DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET
,
453 .context_offs
= DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET
,
454 .modulemode
= MODULEMODE_SWCTRL
,
457 .opt_clks
= dss_opt_clks
,
458 .opt_clks_cnt
= ARRAY_SIZE(dss_opt_clks
),
466 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc
= {
470 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
471 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_MIDLEMODE
|
472 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
473 SYSS_HAS_RESET_STATUS
),
474 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
475 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
476 .sysc_fields
= &omap_hwmod_sysc_type1
,
479 static struct omap_hwmod_class dra7xx_dispc_hwmod_class
= {
481 .sysc
= &dra7xx_dispc_sysc
,
485 /* dss_dispc dev_attr */
486 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr
= {
487 .has_framedonetv_irq
= 1,
491 static struct omap_hwmod dra7xx_dss_dispc_hwmod
= {
493 .class = &dra7xx_dispc_hwmod_class
,
494 .clkdm_name
= "dss_clkdm",
495 .main_clk
= "dss_dss_clk",
498 .clkctrl_offs
= DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET
,
499 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
502 .dev_attr
= &dss_dispc_dev_attr
,
510 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc
= {
513 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
515 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
517 .sysc_fields
= &omap_hwmod_sysc_type2
,
520 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class
= {
522 .sysc
= &dra7xx_hdmi_sysc
,
527 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks
[] = {
528 { .role
= "sys_clk", .clk
= "dss_hdmi_clk" },
531 static struct omap_hwmod dra7xx_dss_hdmi_hwmod
= {
533 .class = &dra7xx_hdmi_hwmod_class
,
534 .clkdm_name
= "dss_clkdm",
535 .main_clk
= "dss_48mhz_clk",
538 .clkctrl_offs
= DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET
,
539 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
542 .opt_clks
= dss_hdmi_opt_clks
,
543 .opt_clks_cnt
= ARRAY_SIZE(dss_hdmi_opt_clks
),
551 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc
= {
555 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
556 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
557 SYSS_HAS_RESET_STATUS
),
558 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
560 .sysc_fields
= &omap_hwmod_sysc_type1
,
563 static struct omap_hwmod_class dra7xx_elm_hwmod_class
= {
565 .sysc
= &dra7xx_elm_sysc
,
570 static struct omap_hwmod dra7xx_elm_hwmod
= {
572 .class = &dra7xx_elm_hwmod_class
,
573 .clkdm_name
= "l4per_clkdm",
574 .main_clk
= "l3_iclk_div",
577 .clkctrl_offs
= DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET
,
578 .context_offs
= DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET
,
588 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc
= {
592 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
593 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
594 SYSS_HAS_RESET_STATUS
),
595 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
597 .sysc_fields
= &omap_hwmod_sysc_type1
,
600 static struct omap_hwmod_class dra7xx_gpio_hwmod_class
= {
602 .sysc
= &dra7xx_gpio_sysc
,
607 static struct omap_gpio_dev_attr gpio_dev_attr
= {
613 static struct omap_hwmod_opt_clk gpio1_opt_clks
[] = {
614 { .role
= "dbclk", .clk
= "gpio1_dbclk" },
617 static struct omap_hwmod dra7xx_gpio1_hwmod
= {
619 .class = &dra7xx_gpio_hwmod_class
,
620 .clkdm_name
= "wkupaon_clkdm",
621 .main_clk
= "wkupaon_iclk_mux",
624 .clkctrl_offs
= DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET
,
625 .context_offs
= DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET
,
626 .modulemode
= MODULEMODE_HWCTRL
,
629 .opt_clks
= gpio1_opt_clks
,
630 .opt_clks_cnt
= ARRAY_SIZE(gpio1_opt_clks
),
631 .dev_attr
= &gpio_dev_attr
,
635 static struct omap_hwmod_opt_clk gpio2_opt_clks
[] = {
636 { .role
= "dbclk", .clk
= "gpio2_dbclk" },
639 static struct omap_hwmod dra7xx_gpio2_hwmod
= {
641 .class = &dra7xx_gpio_hwmod_class
,
642 .clkdm_name
= "l4per_clkdm",
643 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
644 .main_clk
= "l3_iclk_div",
647 .clkctrl_offs
= DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET
,
648 .context_offs
= DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET
,
649 .modulemode
= MODULEMODE_HWCTRL
,
652 .opt_clks
= gpio2_opt_clks
,
653 .opt_clks_cnt
= ARRAY_SIZE(gpio2_opt_clks
),
654 .dev_attr
= &gpio_dev_attr
,
658 static struct omap_hwmod_opt_clk gpio3_opt_clks
[] = {
659 { .role
= "dbclk", .clk
= "gpio3_dbclk" },
662 static struct omap_hwmod dra7xx_gpio3_hwmod
= {
664 .class = &dra7xx_gpio_hwmod_class
,
665 .clkdm_name
= "l4per_clkdm",
666 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
667 .main_clk
= "l3_iclk_div",
670 .clkctrl_offs
= DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET
,
671 .context_offs
= DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET
,
672 .modulemode
= MODULEMODE_HWCTRL
,
675 .opt_clks
= gpio3_opt_clks
,
676 .opt_clks_cnt
= ARRAY_SIZE(gpio3_opt_clks
),
677 .dev_attr
= &gpio_dev_attr
,
681 static struct omap_hwmod_opt_clk gpio4_opt_clks
[] = {
682 { .role
= "dbclk", .clk
= "gpio4_dbclk" },
685 static struct omap_hwmod dra7xx_gpio4_hwmod
= {
687 .class = &dra7xx_gpio_hwmod_class
,
688 .clkdm_name
= "l4per_clkdm",
689 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
690 .main_clk
= "l3_iclk_div",
693 .clkctrl_offs
= DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET
,
694 .context_offs
= DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET
,
695 .modulemode
= MODULEMODE_HWCTRL
,
698 .opt_clks
= gpio4_opt_clks
,
699 .opt_clks_cnt
= ARRAY_SIZE(gpio4_opt_clks
),
700 .dev_attr
= &gpio_dev_attr
,
704 static struct omap_hwmod_opt_clk gpio5_opt_clks
[] = {
705 { .role
= "dbclk", .clk
= "gpio5_dbclk" },
708 static struct omap_hwmod dra7xx_gpio5_hwmod
= {
710 .class = &dra7xx_gpio_hwmod_class
,
711 .clkdm_name
= "l4per_clkdm",
712 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
713 .main_clk
= "l3_iclk_div",
716 .clkctrl_offs
= DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET
,
717 .context_offs
= DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET
,
718 .modulemode
= MODULEMODE_HWCTRL
,
721 .opt_clks
= gpio5_opt_clks
,
722 .opt_clks_cnt
= ARRAY_SIZE(gpio5_opt_clks
),
723 .dev_attr
= &gpio_dev_attr
,
727 static struct omap_hwmod_opt_clk gpio6_opt_clks
[] = {
728 { .role
= "dbclk", .clk
= "gpio6_dbclk" },
731 static struct omap_hwmod dra7xx_gpio6_hwmod
= {
733 .class = &dra7xx_gpio_hwmod_class
,
734 .clkdm_name
= "l4per_clkdm",
735 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
736 .main_clk
= "l3_iclk_div",
739 .clkctrl_offs
= DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET
,
740 .context_offs
= DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET
,
741 .modulemode
= MODULEMODE_HWCTRL
,
744 .opt_clks
= gpio6_opt_clks
,
745 .opt_clks_cnt
= ARRAY_SIZE(gpio6_opt_clks
),
746 .dev_attr
= &gpio_dev_attr
,
750 static struct omap_hwmod_opt_clk gpio7_opt_clks
[] = {
751 { .role
= "dbclk", .clk
= "gpio7_dbclk" },
754 static struct omap_hwmod dra7xx_gpio7_hwmod
= {
756 .class = &dra7xx_gpio_hwmod_class
,
757 .clkdm_name
= "l4per_clkdm",
758 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
759 .main_clk
= "l3_iclk_div",
762 .clkctrl_offs
= DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET
,
763 .context_offs
= DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET
,
764 .modulemode
= MODULEMODE_HWCTRL
,
767 .opt_clks
= gpio7_opt_clks
,
768 .opt_clks_cnt
= ARRAY_SIZE(gpio7_opt_clks
),
769 .dev_attr
= &gpio_dev_attr
,
773 static struct omap_hwmod_opt_clk gpio8_opt_clks
[] = {
774 { .role
= "dbclk", .clk
= "gpio8_dbclk" },
777 static struct omap_hwmod dra7xx_gpio8_hwmod
= {
779 .class = &dra7xx_gpio_hwmod_class
,
780 .clkdm_name
= "l4per_clkdm",
781 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
782 .main_clk
= "l3_iclk_div",
785 .clkctrl_offs
= DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET
,
786 .context_offs
= DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET
,
787 .modulemode
= MODULEMODE_HWCTRL
,
790 .opt_clks
= gpio8_opt_clks
,
791 .opt_clks_cnt
= ARRAY_SIZE(gpio8_opt_clks
),
792 .dev_attr
= &gpio_dev_attr
,
800 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc
= {
804 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SIDLEMODE
|
805 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
806 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
808 .sysc_fields
= &omap_hwmod_sysc_type1
,
811 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class
= {
813 .sysc
= &dra7xx_gpmc_sysc
,
818 static struct omap_hwmod dra7xx_gpmc_hwmod
= {
820 .class = &dra7xx_gpmc_hwmod_class
,
821 .clkdm_name
= "l3main1_clkdm",
822 .flags
= (HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
|
824 .main_clk
= "l3_iclk_div",
827 .clkctrl_offs
= DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET
,
828 .context_offs
= DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET
,
829 .modulemode
= MODULEMODE_HWCTRL
,
839 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc
= {
843 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SOFTRESET
|
844 SYSS_HAS_RESET_STATUS
),
845 .sysc_fields
= &omap_hwmod_sysc_type1
,
848 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class
= {
850 .sysc
= &dra7xx_hdq1w_sysc
,
855 static struct omap_hwmod dra7xx_hdq1w_hwmod
= {
857 .class = &dra7xx_hdq1w_hwmod_class
,
858 .clkdm_name
= "l4per_clkdm",
859 .flags
= HWMOD_INIT_NO_RESET
,
860 .main_clk
= "func_12m_fclk",
863 .clkctrl_offs
= DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET
,
864 .context_offs
= DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET
,
865 .modulemode
= MODULEMODE_SWCTRL
,
875 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc
= {
878 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
879 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
880 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
881 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
883 .clockact
= CLOCKACT_TEST_ICLK
,
884 .sysc_fields
= &omap_hwmod_sysc_type1
,
887 static struct omap_hwmod_class dra7xx_i2c_hwmod_class
= {
889 .sysc
= &dra7xx_i2c_sysc
,
890 .reset
= &omap_i2c_reset
,
891 .rev
= OMAP_I2C_IP_VERSION_2
,
895 static struct omap_i2c_dev_attr i2c_dev_attr
= {
896 .flags
= OMAP_I2C_FLAG_BUS_SHIFT_NONE
,
900 static struct omap_hwmod dra7xx_i2c1_hwmod
= {
902 .class = &dra7xx_i2c_hwmod_class
,
903 .clkdm_name
= "l4per_clkdm",
904 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
905 .main_clk
= "func_96m_fclk",
908 .clkctrl_offs
= DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET
,
909 .context_offs
= DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET
,
910 .modulemode
= MODULEMODE_SWCTRL
,
913 .dev_attr
= &i2c_dev_attr
,
917 static struct omap_hwmod dra7xx_i2c2_hwmod
= {
919 .class = &dra7xx_i2c_hwmod_class
,
920 .clkdm_name
= "l4per_clkdm",
921 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
922 .main_clk
= "func_96m_fclk",
925 .clkctrl_offs
= DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET
,
926 .context_offs
= DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET
,
927 .modulemode
= MODULEMODE_SWCTRL
,
930 .dev_attr
= &i2c_dev_attr
,
934 static struct omap_hwmod dra7xx_i2c3_hwmod
= {
936 .class = &dra7xx_i2c_hwmod_class
,
937 .clkdm_name
= "l4per_clkdm",
938 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
939 .main_clk
= "func_96m_fclk",
942 .clkctrl_offs
= DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET
,
943 .context_offs
= DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET
,
944 .modulemode
= MODULEMODE_SWCTRL
,
947 .dev_attr
= &i2c_dev_attr
,
951 static struct omap_hwmod dra7xx_i2c4_hwmod
= {
953 .class = &dra7xx_i2c_hwmod_class
,
954 .clkdm_name
= "l4per_clkdm",
955 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
956 .main_clk
= "func_96m_fclk",
959 .clkctrl_offs
= DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET
,
960 .context_offs
= DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET
,
961 .modulemode
= MODULEMODE_SWCTRL
,
964 .dev_attr
= &i2c_dev_attr
,
968 static struct omap_hwmod dra7xx_i2c5_hwmod
= {
970 .class = &dra7xx_i2c_hwmod_class
,
971 .clkdm_name
= "ipu_clkdm",
972 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
973 .main_clk
= "func_96m_fclk",
976 .clkctrl_offs
= DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET
,
977 .context_offs
= DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET
,
978 .modulemode
= MODULEMODE_SWCTRL
,
981 .dev_attr
= &i2c_dev_attr
,
989 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc
= {
992 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
994 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
995 .sysc_fields
= &omap_hwmod_sysc_type2
,
998 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class
= {
1000 .sysc
= &dra7xx_mailbox_sysc
,
1004 static struct omap_hwmod dra7xx_mailbox1_hwmod
= {
1006 .class = &dra7xx_mailbox_hwmod_class
,
1007 .clkdm_name
= "l4cfg_clkdm",
1010 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET
,
1011 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET
,
1017 static struct omap_hwmod dra7xx_mailbox2_hwmod
= {
1019 .class = &dra7xx_mailbox_hwmod_class
,
1020 .clkdm_name
= "l4cfg_clkdm",
1023 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET
,
1024 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET
,
1030 static struct omap_hwmod dra7xx_mailbox3_hwmod
= {
1032 .class = &dra7xx_mailbox_hwmod_class
,
1033 .clkdm_name
= "l4cfg_clkdm",
1036 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET
,
1037 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET
,
1043 static struct omap_hwmod dra7xx_mailbox4_hwmod
= {
1045 .class = &dra7xx_mailbox_hwmod_class
,
1046 .clkdm_name
= "l4cfg_clkdm",
1049 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET
,
1050 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET
,
1056 static struct omap_hwmod dra7xx_mailbox5_hwmod
= {
1058 .class = &dra7xx_mailbox_hwmod_class
,
1059 .clkdm_name
= "l4cfg_clkdm",
1062 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET
,
1063 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET
,
1069 static struct omap_hwmod dra7xx_mailbox6_hwmod
= {
1071 .class = &dra7xx_mailbox_hwmod_class
,
1072 .clkdm_name
= "l4cfg_clkdm",
1075 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET
,
1076 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET
,
1082 static struct omap_hwmod dra7xx_mailbox7_hwmod
= {
1084 .class = &dra7xx_mailbox_hwmod_class
,
1085 .clkdm_name
= "l4cfg_clkdm",
1088 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET
,
1089 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET
,
1095 static struct omap_hwmod dra7xx_mailbox8_hwmod
= {
1097 .class = &dra7xx_mailbox_hwmod_class
,
1098 .clkdm_name
= "l4cfg_clkdm",
1101 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET
,
1102 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET
,
1108 static struct omap_hwmod dra7xx_mailbox9_hwmod
= {
1110 .class = &dra7xx_mailbox_hwmod_class
,
1111 .clkdm_name
= "l4cfg_clkdm",
1114 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET
,
1115 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET
,
1121 static struct omap_hwmod dra7xx_mailbox10_hwmod
= {
1122 .name
= "mailbox10",
1123 .class = &dra7xx_mailbox_hwmod_class
,
1124 .clkdm_name
= "l4cfg_clkdm",
1127 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET
,
1128 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET
,
1134 static struct omap_hwmod dra7xx_mailbox11_hwmod
= {
1135 .name
= "mailbox11",
1136 .class = &dra7xx_mailbox_hwmod_class
,
1137 .clkdm_name
= "l4cfg_clkdm",
1140 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET
,
1141 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET
,
1147 static struct omap_hwmod dra7xx_mailbox12_hwmod
= {
1148 .name
= "mailbox12",
1149 .class = &dra7xx_mailbox_hwmod_class
,
1150 .clkdm_name
= "l4cfg_clkdm",
1153 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET
,
1154 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET
,
1160 static struct omap_hwmod dra7xx_mailbox13_hwmod
= {
1161 .name
= "mailbox13",
1162 .class = &dra7xx_mailbox_hwmod_class
,
1163 .clkdm_name
= "l4cfg_clkdm",
1166 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET
,
1167 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET
,
1177 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc
= {
1179 .sysc_offs
= 0x0010,
1180 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
1181 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1182 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1184 .sysc_fields
= &omap_hwmod_sysc_type2
,
1187 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class
= {
1189 .sysc
= &dra7xx_mcspi_sysc
,
1190 .rev
= OMAP4_MCSPI_REV
,
1194 /* mcspi1 dev_attr */
1195 static struct omap2_mcspi_dev_attr mcspi1_dev_attr
= {
1196 .num_chipselect
= 4,
1199 static struct omap_hwmod dra7xx_mcspi1_hwmod
= {
1201 .class = &dra7xx_mcspi_hwmod_class
,
1202 .clkdm_name
= "l4per_clkdm",
1203 .main_clk
= "func_48m_fclk",
1206 .clkctrl_offs
= DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET
,
1207 .context_offs
= DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET
,
1208 .modulemode
= MODULEMODE_SWCTRL
,
1211 .dev_attr
= &mcspi1_dev_attr
,
1215 /* mcspi2 dev_attr */
1216 static struct omap2_mcspi_dev_attr mcspi2_dev_attr
= {
1217 .num_chipselect
= 2,
1220 static struct omap_hwmod dra7xx_mcspi2_hwmod
= {
1222 .class = &dra7xx_mcspi_hwmod_class
,
1223 .clkdm_name
= "l4per_clkdm",
1224 .main_clk
= "func_48m_fclk",
1227 .clkctrl_offs
= DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET
,
1228 .context_offs
= DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET
,
1229 .modulemode
= MODULEMODE_SWCTRL
,
1232 .dev_attr
= &mcspi2_dev_attr
,
1236 /* mcspi3 dev_attr */
1237 static struct omap2_mcspi_dev_attr mcspi3_dev_attr
= {
1238 .num_chipselect
= 2,
1241 static struct omap_hwmod dra7xx_mcspi3_hwmod
= {
1243 .class = &dra7xx_mcspi_hwmod_class
,
1244 .clkdm_name
= "l4per_clkdm",
1245 .main_clk
= "func_48m_fclk",
1248 .clkctrl_offs
= DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET
,
1249 .context_offs
= DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET
,
1250 .modulemode
= MODULEMODE_SWCTRL
,
1253 .dev_attr
= &mcspi3_dev_attr
,
1257 /* mcspi4 dev_attr */
1258 static struct omap2_mcspi_dev_attr mcspi4_dev_attr
= {
1259 .num_chipselect
= 1,
1262 static struct omap_hwmod dra7xx_mcspi4_hwmod
= {
1264 .class = &dra7xx_mcspi_hwmod_class
,
1265 .clkdm_name
= "l4per_clkdm",
1266 .main_clk
= "func_48m_fclk",
1269 .clkctrl_offs
= DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET
,
1270 .context_offs
= DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET
,
1271 .modulemode
= MODULEMODE_SWCTRL
,
1274 .dev_attr
= &mcspi4_dev_attr
,
1282 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc
= {
1284 .sysc_offs
= 0x0010,
1285 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_MIDLEMODE
|
1286 SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
1287 SYSC_HAS_SOFTRESET
),
1288 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1289 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1290 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1291 .sysc_fields
= &omap_hwmod_sysc_type2
,
1294 static struct omap_hwmod_class dra7xx_mmc_hwmod_class
= {
1296 .sysc
= &dra7xx_mmc_sysc
,
1300 static struct omap_hwmod_opt_clk mmc1_opt_clks
[] = {
1301 { .role
= "clk32k", .clk
= "mmc1_clk32k" },
1305 static struct omap_hsmmc_dev_attr mmc1_dev_attr
= {
1306 .flags
= OMAP_HSMMC_SUPPORTS_DUAL_VOLT
,
1309 static struct omap_hwmod dra7xx_mmc1_hwmod
= {
1311 .class = &dra7xx_mmc_hwmod_class
,
1312 .clkdm_name
= "l3init_clkdm",
1313 .main_clk
= "mmc1_fclk_div",
1316 .clkctrl_offs
= DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET
,
1317 .context_offs
= DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET
,
1318 .modulemode
= MODULEMODE_SWCTRL
,
1321 .opt_clks
= mmc1_opt_clks
,
1322 .opt_clks_cnt
= ARRAY_SIZE(mmc1_opt_clks
),
1323 .dev_attr
= &mmc1_dev_attr
,
1327 static struct omap_hwmod_opt_clk mmc2_opt_clks
[] = {
1328 { .role
= "clk32k", .clk
= "mmc2_clk32k" },
1331 static struct omap_hwmod dra7xx_mmc2_hwmod
= {
1333 .class = &dra7xx_mmc_hwmod_class
,
1334 .clkdm_name
= "l3init_clkdm",
1335 .main_clk
= "mmc2_fclk_div",
1338 .clkctrl_offs
= DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET
,
1339 .context_offs
= DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET
,
1340 .modulemode
= MODULEMODE_SWCTRL
,
1343 .opt_clks
= mmc2_opt_clks
,
1344 .opt_clks_cnt
= ARRAY_SIZE(mmc2_opt_clks
),
1348 static struct omap_hwmod_opt_clk mmc3_opt_clks
[] = {
1349 { .role
= "clk32k", .clk
= "mmc3_clk32k" },
1352 static struct omap_hwmod dra7xx_mmc3_hwmod
= {
1354 .class = &dra7xx_mmc_hwmod_class
,
1355 .clkdm_name
= "l4per_clkdm",
1356 .main_clk
= "mmc3_gfclk_div",
1359 .clkctrl_offs
= DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET
,
1360 .context_offs
= DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET
,
1361 .modulemode
= MODULEMODE_SWCTRL
,
1364 .opt_clks
= mmc3_opt_clks
,
1365 .opt_clks_cnt
= ARRAY_SIZE(mmc3_opt_clks
),
1369 static struct omap_hwmod_opt_clk mmc4_opt_clks
[] = {
1370 { .role
= "clk32k", .clk
= "mmc4_clk32k" },
1373 static struct omap_hwmod dra7xx_mmc4_hwmod
= {
1375 .class = &dra7xx_mmc_hwmod_class
,
1376 .clkdm_name
= "l4per_clkdm",
1377 .main_clk
= "mmc4_gfclk_div",
1380 .clkctrl_offs
= DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET
,
1381 .context_offs
= DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET
,
1382 .modulemode
= MODULEMODE_SWCTRL
,
1385 .opt_clks
= mmc4_opt_clks
,
1386 .opt_clks_cnt
= ARRAY_SIZE(mmc4_opt_clks
),
1394 static struct omap_hwmod_class dra7xx_mpu_hwmod_class
= {
1399 static struct omap_hwmod dra7xx_mpu_hwmod
= {
1401 .class = &dra7xx_mpu_hwmod_class
,
1402 .clkdm_name
= "mpu_clkdm",
1403 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
1404 .main_clk
= "dpll_mpu_m2_ck",
1407 .clkctrl_offs
= DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET
,
1408 .context_offs
= DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET
,
1418 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc
= {
1420 .sysc_offs
= 0x0010,
1421 .syss_offs
= 0x0014,
1422 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SIDLEMODE
|
1423 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1424 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1426 .sysc_fields
= &omap_hwmod_sysc_type1
,
1429 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class
= {
1431 .sysc
= &dra7xx_ocp2scp_sysc
,
1435 static struct omap_hwmod dra7xx_ocp2scp1_hwmod
= {
1437 .class = &dra7xx_ocp2scp_hwmod_class
,
1438 .clkdm_name
= "l3init_clkdm",
1439 .main_clk
= "l4_root_clk_div",
1442 .clkctrl_offs
= DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET
,
1443 .context_offs
= DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET
,
1444 .modulemode
= MODULEMODE_HWCTRL
,
1450 static struct omap_hwmod dra7xx_ocp2scp3_hwmod
= {
1452 .class = &dra7xx_ocp2scp_hwmod_class
,
1453 .clkdm_name
= "l3init_clkdm",
1454 .main_clk
= "l4_root_clk_div",
1457 .clkctrl_offs
= DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET
,
1458 .context_offs
= DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET
,
1459 .modulemode
= MODULEMODE_HWCTRL
,
1469 static struct omap_hwmod_class dra7xx_pcie_hwmod_class
= {
1474 static struct omap_hwmod dra7xx_pcie1_hwmod
= {
1476 .class = &dra7xx_pcie_hwmod_class
,
1477 .clkdm_name
= "pcie_clkdm",
1478 .main_clk
= "l4_root_clk_div",
1481 .clkctrl_offs
= DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET
,
1482 .modulemode
= MODULEMODE_SWCTRL
,
1488 static struct omap_hwmod dra7xx_pcie2_hwmod
= {
1490 .class = &dra7xx_pcie_hwmod_class
,
1491 .clkdm_name
= "pcie_clkdm",
1492 .main_clk
= "l4_root_clk_div",
1495 .clkctrl_offs
= DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET
,
1496 .modulemode
= MODULEMODE_SWCTRL
,
1506 static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class
= {
1511 static struct omap_hwmod dra7xx_pcie1_phy_hwmod
= {
1512 .name
= "pcie1-phy",
1513 .class = &dra7xx_pcie_phy_hwmod_class
,
1514 .clkdm_name
= "l3init_clkdm",
1515 .main_clk
= "l4_root_clk_div",
1518 .clkctrl_offs
= DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET
,
1519 .context_offs
= DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET
,
1520 .modulemode
= MODULEMODE_SWCTRL
,
1526 static struct omap_hwmod dra7xx_pcie2_phy_hwmod
= {
1527 .name
= "pcie2-phy",
1528 .class = &dra7xx_pcie_phy_hwmod_class
,
1529 .clkdm_name
= "l3init_clkdm",
1530 .main_clk
= "l4_root_clk_div",
1533 .clkctrl_offs
= DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET
,
1534 .context_offs
= DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET
,
1535 .modulemode
= MODULEMODE_SWCTRL
,
1545 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc
= {
1546 .sysc_offs
= 0x0010,
1547 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
1548 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1550 .sysc_fields
= &omap_hwmod_sysc_type2
,
1553 static struct omap_hwmod_class dra7xx_qspi_hwmod_class
= {
1555 .sysc
= &dra7xx_qspi_sysc
,
1559 static struct omap_hwmod dra7xx_qspi_hwmod
= {
1561 .class = &dra7xx_qspi_hwmod_class
,
1562 .clkdm_name
= "l4per2_clkdm",
1563 .main_clk
= "qspi_gfclk_div",
1566 .clkctrl_offs
= DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET
,
1567 .context_offs
= DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET
,
1568 .modulemode
= MODULEMODE_SWCTRL
,
1577 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc
= {
1578 .sysc_offs
= 0x0078,
1579 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
1580 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1582 .sysc_fields
= &omap_hwmod_sysc_type3
,
1585 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class
= {
1587 .sysc
= &dra7xx_rtcss_sysc
,
1591 static struct omap_hwmod dra7xx_rtcss_hwmod
= {
1593 .class = &dra7xx_rtcss_hwmod_class
,
1594 .clkdm_name
= "rtc_clkdm",
1595 .main_clk
= "sys_32k_ck",
1598 .clkctrl_offs
= DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET
,
1599 .context_offs
= DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET
,
1600 .modulemode
= MODULEMODE_SWCTRL
,
1610 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc
= {
1611 .sysc_offs
= 0x0000,
1612 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
),
1613 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1614 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1615 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1616 .sysc_fields
= &omap_hwmod_sysc_type2
,
1619 static struct omap_hwmod_class dra7xx_sata_hwmod_class
= {
1621 .sysc
= &dra7xx_sata_sysc
,
1626 static struct omap_hwmod dra7xx_sata_hwmod
= {
1628 .class = &dra7xx_sata_hwmod_class
,
1629 .clkdm_name
= "l3init_clkdm",
1630 .flags
= HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
,
1631 .main_clk
= "func_48m_fclk",
1635 .clkctrl_offs
= DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET
,
1636 .context_offs
= DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET
,
1637 .modulemode
= MODULEMODE_SWCTRL
,
1643 * 'smartreflex' class
1647 /* The IP is not compliant to type1 / type2 scheme */
1648 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex
= {
1653 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc
= {
1654 .sysc_offs
= 0x0038,
1655 .sysc_flags
= (SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
),
1656 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1658 .sysc_fields
= &omap_hwmod_sysc_type_smartreflex
,
1661 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class
= {
1662 .name
= "smartreflex",
1663 .sysc
= &dra7xx_smartreflex_sysc
,
1667 /* smartreflex_core */
1668 /* smartreflex_core dev_attr */
1669 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr
= {
1670 .sensor_voltdm_name
= "core",
1673 static struct omap_hwmod dra7xx_smartreflex_core_hwmod
= {
1674 .name
= "smartreflex_core",
1675 .class = &dra7xx_smartreflex_hwmod_class
,
1676 .clkdm_name
= "coreaon_clkdm",
1677 .main_clk
= "wkupaon_iclk_mux",
1680 .clkctrl_offs
= DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET
,
1681 .context_offs
= DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET
,
1682 .modulemode
= MODULEMODE_SWCTRL
,
1685 .dev_attr
= &smartreflex_core_dev_attr
,
1688 /* smartreflex_mpu */
1689 /* smartreflex_mpu dev_attr */
1690 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr
= {
1691 .sensor_voltdm_name
= "mpu",
1694 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod
= {
1695 .name
= "smartreflex_mpu",
1696 .class = &dra7xx_smartreflex_hwmod_class
,
1697 .clkdm_name
= "coreaon_clkdm",
1698 .main_clk
= "wkupaon_iclk_mux",
1701 .clkctrl_offs
= DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET
,
1702 .context_offs
= DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET
,
1703 .modulemode
= MODULEMODE_SWCTRL
,
1706 .dev_attr
= &smartreflex_mpu_dev_attr
,
1714 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc
= {
1716 .sysc_offs
= 0x0010,
1717 .syss_offs
= 0x0014,
1718 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
1719 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
1720 SYSS_HAS_RESET_STATUS
),
1721 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1722 .sysc_fields
= &omap_hwmod_sysc_type1
,
1725 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class
= {
1727 .sysc
= &dra7xx_spinlock_sysc
,
1731 static struct omap_hwmod dra7xx_spinlock_hwmod
= {
1733 .class = &dra7xx_spinlock_hwmod_class
,
1734 .clkdm_name
= "l4cfg_clkdm",
1735 .main_clk
= "l3_iclk_div",
1738 .clkctrl_offs
= DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET
,
1739 .context_offs
= DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET
,
1747 * This class contains several variants: ['timer_1ms', 'timer_secure',
1751 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc
= {
1753 .sysc_offs
= 0x0010,
1754 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
1755 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1756 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1758 .sysc_fields
= &omap_hwmod_sysc_type2
,
1761 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class
= {
1763 .sysc
= &dra7xx_timer_1ms_sysc
,
1766 static struct omap_hwmod_class_sysconfig dra7xx_timer_secure_sysc
= {
1768 .sysc_offs
= 0x0010,
1769 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
1770 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1771 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1773 .sysc_fields
= &omap_hwmod_sysc_type2
,
1776 static struct omap_hwmod_class dra7xx_timer_secure_hwmod_class
= {
1778 .sysc
= &dra7xx_timer_secure_sysc
,
1781 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc
= {
1783 .sysc_offs
= 0x0010,
1784 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
1785 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1786 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1788 .sysc_fields
= &omap_hwmod_sysc_type2
,
1791 static struct omap_hwmod_class dra7xx_timer_hwmod_class
= {
1793 .sysc
= &dra7xx_timer_sysc
,
1797 static struct omap_hwmod dra7xx_timer1_hwmod
= {
1799 .class = &dra7xx_timer_1ms_hwmod_class
,
1800 .clkdm_name
= "wkupaon_clkdm",
1801 .main_clk
= "timer1_gfclk_mux",
1804 .clkctrl_offs
= DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET
,
1805 .context_offs
= DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET
,
1806 .modulemode
= MODULEMODE_SWCTRL
,
1812 static struct omap_hwmod dra7xx_timer2_hwmod
= {
1814 .class = &dra7xx_timer_1ms_hwmod_class
,
1815 .clkdm_name
= "l4per_clkdm",
1816 .main_clk
= "timer2_gfclk_mux",
1819 .clkctrl_offs
= DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET
,
1820 .context_offs
= DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET
,
1821 .modulemode
= MODULEMODE_SWCTRL
,
1827 static struct omap_hwmod dra7xx_timer3_hwmod
= {
1829 .class = &dra7xx_timer_hwmod_class
,
1830 .clkdm_name
= "l4per_clkdm",
1831 .main_clk
= "timer3_gfclk_mux",
1834 .clkctrl_offs
= DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET
,
1835 .context_offs
= DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET
,
1836 .modulemode
= MODULEMODE_SWCTRL
,
1842 static struct omap_hwmod dra7xx_timer4_hwmod
= {
1844 .class = &dra7xx_timer_secure_hwmod_class
,
1845 .clkdm_name
= "l4per_clkdm",
1846 .main_clk
= "timer4_gfclk_mux",
1849 .clkctrl_offs
= DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET
,
1850 .context_offs
= DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET
,
1851 .modulemode
= MODULEMODE_SWCTRL
,
1857 static struct omap_hwmod dra7xx_timer5_hwmod
= {
1859 .class = &dra7xx_timer_hwmod_class
,
1860 .clkdm_name
= "ipu_clkdm",
1861 .main_clk
= "timer5_gfclk_mux",
1864 .clkctrl_offs
= DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET
,
1865 .context_offs
= DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET
,
1866 .modulemode
= MODULEMODE_SWCTRL
,
1872 static struct omap_hwmod dra7xx_timer6_hwmod
= {
1874 .class = &dra7xx_timer_hwmod_class
,
1875 .clkdm_name
= "ipu_clkdm",
1876 .main_clk
= "timer6_gfclk_mux",
1879 .clkctrl_offs
= DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET
,
1880 .context_offs
= DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET
,
1881 .modulemode
= MODULEMODE_SWCTRL
,
1887 static struct omap_hwmod dra7xx_timer7_hwmod
= {
1889 .class = &dra7xx_timer_hwmod_class
,
1890 .clkdm_name
= "ipu_clkdm",
1891 .main_clk
= "timer7_gfclk_mux",
1894 .clkctrl_offs
= DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET
,
1895 .context_offs
= DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET
,
1896 .modulemode
= MODULEMODE_SWCTRL
,
1902 static struct omap_hwmod dra7xx_timer8_hwmod
= {
1904 .class = &dra7xx_timer_hwmod_class
,
1905 .clkdm_name
= "ipu_clkdm",
1906 .main_clk
= "timer8_gfclk_mux",
1909 .clkctrl_offs
= DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET
,
1910 .context_offs
= DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET
,
1911 .modulemode
= MODULEMODE_SWCTRL
,
1917 static struct omap_hwmod dra7xx_timer9_hwmod
= {
1919 .class = &dra7xx_timer_hwmod_class
,
1920 .clkdm_name
= "l4per_clkdm",
1921 .main_clk
= "timer9_gfclk_mux",
1924 .clkctrl_offs
= DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET
,
1925 .context_offs
= DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET
,
1926 .modulemode
= MODULEMODE_SWCTRL
,
1932 static struct omap_hwmod dra7xx_timer10_hwmod
= {
1934 .class = &dra7xx_timer_1ms_hwmod_class
,
1935 .clkdm_name
= "l4per_clkdm",
1936 .main_clk
= "timer10_gfclk_mux",
1939 .clkctrl_offs
= DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET
,
1940 .context_offs
= DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET
,
1941 .modulemode
= MODULEMODE_SWCTRL
,
1947 static struct omap_hwmod dra7xx_timer11_hwmod
= {
1949 .class = &dra7xx_timer_hwmod_class
,
1950 .clkdm_name
= "l4per_clkdm",
1951 .main_clk
= "timer11_gfclk_mux",
1954 .clkctrl_offs
= DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET
,
1955 .context_offs
= DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET
,
1956 .modulemode
= MODULEMODE_SWCTRL
,
1966 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc
= {
1968 .sysc_offs
= 0x0054,
1969 .syss_offs
= 0x0058,
1970 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
1971 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
1972 SYSS_HAS_RESET_STATUS
),
1973 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1975 .sysc_fields
= &omap_hwmod_sysc_type1
,
1978 static struct omap_hwmod_class dra7xx_uart_hwmod_class
= {
1980 .sysc
= &dra7xx_uart_sysc
,
1984 static struct omap_hwmod dra7xx_uart1_hwmod
= {
1986 .class = &dra7xx_uart_hwmod_class
,
1987 .clkdm_name
= "l4per_clkdm",
1988 .main_clk
= "uart1_gfclk_mux",
1989 .flags
= HWMOD_SWSUP_SIDLE_ACT
| DEBUG_OMAP2UART1_FLAGS
,
1992 .clkctrl_offs
= DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET
,
1993 .context_offs
= DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET
,
1994 .modulemode
= MODULEMODE_SWCTRL
,
2000 static struct omap_hwmod dra7xx_uart2_hwmod
= {
2002 .class = &dra7xx_uart_hwmod_class
,
2003 .clkdm_name
= "l4per_clkdm",
2004 .main_clk
= "uart2_gfclk_mux",
2005 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
2008 .clkctrl_offs
= DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET
,
2009 .context_offs
= DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET
,
2010 .modulemode
= MODULEMODE_SWCTRL
,
2016 static struct omap_hwmod dra7xx_uart3_hwmod
= {
2018 .class = &dra7xx_uart_hwmod_class
,
2019 .clkdm_name
= "l4per_clkdm",
2020 .main_clk
= "uart3_gfclk_mux",
2021 .flags
= HWMOD_SWSUP_SIDLE_ACT
| DEBUG_OMAP4UART3_FLAGS
,
2024 .clkctrl_offs
= DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET
,
2025 .context_offs
= DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET
,
2026 .modulemode
= MODULEMODE_SWCTRL
,
2032 static struct omap_hwmod dra7xx_uart4_hwmod
= {
2034 .class = &dra7xx_uart_hwmod_class
,
2035 .clkdm_name
= "l4per_clkdm",
2036 .main_clk
= "uart4_gfclk_mux",
2037 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
2040 .clkctrl_offs
= DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET
,
2041 .context_offs
= DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET
,
2042 .modulemode
= MODULEMODE_SWCTRL
,
2048 static struct omap_hwmod dra7xx_uart5_hwmod
= {
2050 .class = &dra7xx_uart_hwmod_class
,
2051 .clkdm_name
= "l4per_clkdm",
2052 .main_clk
= "uart5_gfclk_mux",
2053 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
2056 .clkctrl_offs
= DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET
,
2057 .context_offs
= DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET
,
2058 .modulemode
= MODULEMODE_SWCTRL
,
2064 static struct omap_hwmod dra7xx_uart6_hwmod
= {
2066 .class = &dra7xx_uart_hwmod_class
,
2067 .clkdm_name
= "ipu_clkdm",
2068 .main_clk
= "uart6_gfclk_mux",
2069 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
2072 .clkctrl_offs
= DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET
,
2073 .context_offs
= DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET
,
2074 .modulemode
= MODULEMODE_SWCTRL
,
2080 static struct omap_hwmod dra7xx_uart7_hwmod
= {
2082 .class = &dra7xx_uart_hwmod_class
,
2083 .clkdm_name
= "l4per2_clkdm",
2084 .main_clk
= "uart7_gfclk_mux",
2085 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
2088 .clkctrl_offs
= DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET
,
2089 .context_offs
= DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET
,
2090 .modulemode
= MODULEMODE_SWCTRL
,
2096 static struct omap_hwmod dra7xx_uart8_hwmod
= {
2098 .class = &dra7xx_uart_hwmod_class
,
2099 .clkdm_name
= "l4per2_clkdm",
2100 .main_clk
= "uart8_gfclk_mux",
2101 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
2104 .clkctrl_offs
= DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET
,
2105 .context_offs
= DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET
,
2106 .modulemode
= MODULEMODE_SWCTRL
,
2112 static struct omap_hwmod dra7xx_uart9_hwmod
= {
2114 .class = &dra7xx_uart_hwmod_class
,
2115 .clkdm_name
= "l4per2_clkdm",
2116 .main_clk
= "uart9_gfclk_mux",
2117 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
2120 .clkctrl_offs
= DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET
,
2121 .context_offs
= DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET
,
2122 .modulemode
= MODULEMODE_SWCTRL
,
2128 static struct omap_hwmod dra7xx_uart10_hwmod
= {
2130 .class = &dra7xx_uart_hwmod_class
,
2131 .clkdm_name
= "wkupaon_clkdm",
2132 .main_clk
= "uart10_gfclk_mux",
2133 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
2136 .clkctrl_offs
= DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET
,
2137 .context_offs
= DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET
,
2138 .modulemode
= MODULEMODE_SWCTRL
,
2144 * 'usb_otg_ss' class
2148 static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc
= {
2150 .sysc_offs
= 0x0010,
2151 .sysc_flags
= (SYSC_HAS_DMADISABLE
| SYSC_HAS_MIDLEMODE
|
2152 SYSC_HAS_SIDLEMODE
),
2153 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2154 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
2155 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
2156 .sysc_fields
= &omap_hwmod_sysc_type2
,
2159 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class
= {
2160 .name
= "usb_otg_ss",
2161 .sysc
= &dra7xx_usb_otg_ss_sysc
,
2165 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks
[] = {
2166 { .role
= "refclk960m", .clk
= "usb_otg_ss1_refclk960m" },
2169 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod
= {
2170 .name
= "usb_otg_ss1",
2171 .class = &dra7xx_usb_otg_ss_hwmod_class
,
2172 .clkdm_name
= "l3init_clkdm",
2173 .main_clk
= "dpll_core_h13x2_ck",
2176 .clkctrl_offs
= DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET
,
2177 .context_offs
= DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET
,
2178 .modulemode
= MODULEMODE_HWCTRL
,
2181 .opt_clks
= usb_otg_ss1_opt_clks
,
2182 .opt_clks_cnt
= ARRAY_SIZE(usb_otg_ss1_opt_clks
),
2186 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks
[] = {
2187 { .role
= "refclk960m", .clk
= "usb_otg_ss2_refclk960m" },
2190 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod
= {
2191 .name
= "usb_otg_ss2",
2192 .class = &dra7xx_usb_otg_ss_hwmod_class
,
2193 .clkdm_name
= "l3init_clkdm",
2194 .main_clk
= "dpll_core_h13x2_ck",
2197 .clkctrl_offs
= DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET
,
2198 .context_offs
= DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET
,
2199 .modulemode
= MODULEMODE_HWCTRL
,
2202 .opt_clks
= usb_otg_ss2_opt_clks
,
2203 .opt_clks_cnt
= ARRAY_SIZE(usb_otg_ss2_opt_clks
),
2207 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod
= {
2208 .name
= "usb_otg_ss3",
2209 .class = &dra7xx_usb_otg_ss_hwmod_class
,
2210 .clkdm_name
= "l3init_clkdm",
2211 .main_clk
= "dpll_core_h13x2_ck",
2214 .clkctrl_offs
= DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET
,
2215 .context_offs
= DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET
,
2216 .modulemode
= MODULEMODE_HWCTRL
,
2222 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod
= {
2223 .name
= "usb_otg_ss4",
2224 .class = &dra7xx_usb_otg_ss_hwmod_class
,
2225 .clkdm_name
= "l3init_clkdm",
2226 .main_clk
= "dpll_core_h13x2_ck",
2229 .clkctrl_offs
= DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET
,
2230 .context_offs
= DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET
,
2231 .modulemode
= MODULEMODE_HWCTRL
,
2241 static struct omap_hwmod_class dra7xx_vcp_hwmod_class
= {
2246 static struct omap_hwmod dra7xx_vcp1_hwmod
= {
2248 .class = &dra7xx_vcp_hwmod_class
,
2249 .clkdm_name
= "l3main1_clkdm",
2250 .main_clk
= "l3_iclk_div",
2253 .clkctrl_offs
= DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET
,
2254 .context_offs
= DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET
,
2260 static struct omap_hwmod dra7xx_vcp2_hwmod
= {
2262 .class = &dra7xx_vcp_hwmod_class
,
2263 .clkdm_name
= "l3main1_clkdm",
2264 .main_clk
= "l3_iclk_div",
2267 .clkctrl_offs
= DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET
,
2268 .context_offs
= DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET
,
2278 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc
= {
2280 .sysc_offs
= 0x0010,
2281 .syss_offs
= 0x0014,
2282 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_SIDLEMODE
|
2283 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
2284 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2286 .sysc_fields
= &omap_hwmod_sysc_type1
,
2289 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class
= {
2291 .sysc
= &dra7xx_wd_timer_sysc
,
2292 .pre_shutdown
= &omap2_wd_timer_disable
,
2293 .reset
= &omap2_wd_timer_reset
,
2297 static struct omap_hwmod dra7xx_wd_timer2_hwmod
= {
2298 .name
= "wd_timer2",
2299 .class = &dra7xx_wd_timer_hwmod_class
,
2300 .clkdm_name
= "wkupaon_clkdm",
2301 .main_clk
= "sys_32k_ck",
2304 .clkctrl_offs
= DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET
,
2305 .context_offs
= DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET
,
2306 .modulemode
= MODULEMODE_SWCTRL
,
2316 /* l3_main_2 -> l3_instr */
2317 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr
= {
2318 .master
= &dra7xx_l3_main_2_hwmod
,
2319 .slave
= &dra7xx_l3_instr_hwmod
,
2320 .clk
= "l3_iclk_div",
2321 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2324 /* l4_cfg -> l3_main_1 */
2325 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1
= {
2326 .master
= &dra7xx_l4_cfg_hwmod
,
2327 .slave
= &dra7xx_l3_main_1_hwmod
,
2328 .clk
= "l3_iclk_div",
2329 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2332 /* mpu -> l3_main_1 */
2333 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1
= {
2334 .master
= &dra7xx_mpu_hwmod
,
2335 .slave
= &dra7xx_l3_main_1_hwmod
,
2336 .clk
= "l3_iclk_div",
2337 .user
= OCP_USER_MPU
,
2340 /* l3_main_1 -> l3_main_2 */
2341 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2
= {
2342 .master
= &dra7xx_l3_main_1_hwmod
,
2343 .slave
= &dra7xx_l3_main_2_hwmod
,
2344 .clk
= "l3_iclk_div",
2345 .user
= OCP_USER_MPU
,
2348 /* l4_cfg -> l3_main_2 */
2349 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2
= {
2350 .master
= &dra7xx_l4_cfg_hwmod
,
2351 .slave
= &dra7xx_l3_main_2_hwmod
,
2352 .clk
= "l3_iclk_div",
2353 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2356 /* l3_main_1 -> l4_cfg */
2357 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg
= {
2358 .master
= &dra7xx_l3_main_1_hwmod
,
2359 .slave
= &dra7xx_l4_cfg_hwmod
,
2360 .clk
= "l3_iclk_div",
2361 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2364 /* l3_main_1 -> l4_per1 */
2365 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1
= {
2366 .master
= &dra7xx_l3_main_1_hwmod
,
2367 .slave
= &dra7xx_l4_per1_hwmod
,
2368 .clk
= "l3_iclk_div",
2369 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2372 /* l3_main_1 -> l4_per2 */
2373 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2
= {
2374 .master
= &dra7xx_l3_main_1_hwmod
,
2375 .slave
= &dra7xx_l4_per2_hwmod
,
2376 .clk
= "l3_iclk_div",
2377 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2380 /* l3_main_1 -> l4_per3 */
2381 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3
= {
2382 .master
= &dra7xx_l3_main_1_hwmod
,
2383 .slave
= &dra7xx_l4_per3_hwmod
,
2384 .clk
= "l3_iclk_div",
2385 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2388 /* l3_main_1 -> l4_wkup */
2389 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup
= {
2390 .master
= &dra7xx_l3_main_1_hwmod
,
2391 .slave
= &dra7xx_l4_wkup_hwmod
,
2392 .clk
= "wkupaon_iclk_mux",
2393 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2396 /* l4_per2 -> atl */
2397 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl
= {
2398 .master
= &dra7xx_l4_per2_hwmod
,
2399 .slave
= &dra7xx_atl_hwmod
,
2400 .clk
= "l3_iclk_div",
2401 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2404 /* l3_main_1 -> bb2d */
2405 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d
= {
2406 .master
= &dra7xx_l3_main_1_hwmod
,
2407 .slave
= &dra7xx_bb2d_hwmod
,
2408 .clk
= "l3_iclk_div",
2409 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2412 /* l4_wkup -> counter_32k */
2413 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k
= {
2414 .master
= &dra7xx_l4_wkup_hwmod
,
2415 .slave
= &dra7xx_counter_32k_hwmod
,
2416 .clk
= "wkupaon_iclk_mux",
2417 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2420 /* l4_wkup -> ctrl_module_wkup */
2421 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup
= {
2422 .master
= &dra7xx_l4_wkup_hwmod
,
2423 .slave
= &dra7xx_ctrl_module_wkup_hwmod
,
2424 .clk
= "wkupaon_iclk_mux",
2425 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2428 static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0
= {
2429 .master
= &dra7xx_l4_per2_hwmod
,
2430 .slave
= &dra7xx_gmac_hwmod
,
2431 .clk
= "dpll_gmac_ck",
2432 .user
= OCP_USER_MPU
,
2435 static struct omap_hwmod_ocp_if dra7xx_gmac__mdio
= {
2436 .master
= &dra7xx_gmac_hwmod
,
2437 .slave
= &dra7xx_mdio_hwmod
,
2438 .user
= OCP_USER_MPU
,
2441 /* l4_wkup -> dcan1 */
2442 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1
= {
2443 .master
= &dra7xx_l4_wkup_hwmod
,
2444 .slave
= &dra7xx_dcan1_hwmod
,
2445 .clk
= "wkupaon_iclk_mux",
2446 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2449 /* l4_per2 -> dcan2 */
2450 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2
= {
2451 .master
= &dra7xx_l4_per2_hwmod
,
2452 .slave
= &dra7xx_dcan2_hwmod
,
2453 .clk
= "l3_iclk_div",
2454 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2457 static struct omap_hwmod_addr_space dra7xx_dma_system_addrs
[] = {
2459 .pa_start
= 0x4a056000,
2460 .pa_end
= 0x4a056fff,
2461 .flags
= ADDR_TYPE_RT
2466 /* l4_cfg -> dma_system */
2467 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system
= {
2468 .master
= &dra7xx_l4_cfg_hwmod
,
2469 .slave
= &dra7xx_dma_system_hwmod
,
2470 .clk
= "l3_iclk_div",
2471 .addr
= dra7xx_dma_system_addrs
,
2472 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2475 static struct omap_hwmod_addr_space dra7xx_dss_addrs
[] = {
2478 .pa_start
= 0x58000000,
2479 .pa_end
= 0x5800007f,
2480 .flags
= ADDR_TYPE_RT
2484 /* l3_main_1 -> dss */
2485 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss
= {
2486 .master
= &dra7xx_l3_main_1_hwmod
,
2487 .slave
= &dra7xx_dss_hwmod
,
2488 .clk
= "l3_iclk_div",
2489 .addr
= dra7xx_dss_addrs
,
2490 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2493 static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs
[] = {
2496 .pa_start
= 0x58001000,
2497 .pa_end
= 0x58001fff,
2498 .flags
= ADDR_TYPE_RT
2502 /* l3_main_1 -> dispc */
2503 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc
= {
2504 .master
= &dra7xx_l3_main_1_hwmod
,
2505 .slave
= &dra7xx_dss_dispc_hwmod
,
2506 .clk
= "l3_iclk_div",
2507 .addr
= dra7xx_dss_dispc_addrs
,
2508 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2511 static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs
[] = {
2514 .pa_start
= 0x58040000,
2515 .pa_end
= 0x580400ff,
2516 .flags
= ADDR_TYPE_RT
2521 /* l3_main_1 -> dispc */
2522 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi
= {
2523 .master
= &dra7xx_l3_main_1_hwmod
,
2524 .slave
= &dra7xx_dss_hdmi_hwmod
,
2525 .clk
= "l3_iclk_div",
2526 .addr
= dra7xx_dss_hdmi_addrs
,
2527 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2530 static struct omap_hwmod_addr_space dra7xx_elm_addrs
[] = {
2532 .pa_start
= 0x48078000,
2533 .pa_end
= 0x48078fff,
2534 .flags
= ADDR_TYPE_RT
2539 /* l4_per1 -> elm */
2540 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm
= {
2541 .master
= &dra7xx_l4_per1_hwmod
,
2542 .slave
= &dra7xx_elm_hwmod
,
2543 .clk
= "l3_iclk_div",
2544 .addr
= dra7xx_elm_addrs
,
2545 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2548 /* l4_wkup -> gpio1 */
2549 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1
= {
2550 .master
= &dra7xx_l4_wkup_hwmod
,
2551 .slave
= &dra7xx_gpio1_hwmod
,
2552 .clk
= "wkupaon_iclk_mux",
2553 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2556 /* l4_per1 -> gpio2 */
2557 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2
= {
2558 .master
= &dra7xx_l4_per1_hwmod
,
2559 .slave
= &dra7xx_gpio2_hwmod
,
2560 .clk
= "l3_iclk_div",
2561 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2564 /* l4_per1 -> gpio3 */
2565 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3
= {
2566 .master
= &dra7xx_l4_per1_hwmod
,
2567 .slave
= &dra7xx_gpio3_hwmod
,
2568 .clk
= "l3_iclk_div",
2569 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2572 /* l4_per1 -> gpio4 */
2573 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4
= {
2574 .master
= &dra7xx_l4_per1_hwmod
,
2575 .slave
= &dra7xx_gpio4_hwmod
,
2576 .clk
= "l3_iclk_div",
2577 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2580 /* l4_per1 -> gpio5 */
2581 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5
= {
2582 .master
= &dra7xx_l4_per1_hwmod
,
2583 .slave
= &dra7xx_gpio5_hwmod
,
2584 .clk
= "l3_iclk_div",
2585 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2588 /* l4_per1 -> gpio6 */
2589 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6
= {
2590 .master
= &dra7xx_l4_per1_hwmod
,
2591 .slave
= &dra7xx_gpio6_hwmod
,
2592 .clk
= "l3_iclk_div",
2593 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2596 /* l4_per1 -> gpio7 */
2597 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7
= {
2598 .master
= &dra7xx_l4_per1_hwmod
,
2599 .slave
= &dra7xx_gpio7_hwmod
,
2600 .clk
= "l3_iclk_div",
2601 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2604 /* l4_per1 -> gpio8 */
2605 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8
= {
2606 .master
= &dra7xx_l4_per1_hwmod
,
2607 .slave
= &dra7xx_gpio8_hwmod
,
2608 .clk
= "l3_iclk_div",
2609 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2612 static struct omap_hwmod_addr_space dra7xx_gpmc_addrs
[] = {
2614 .pa_start
= 0x50000000,
2615 .pa_end
= 0x500003ff,
2616 .flags
= ADDR_TYPE_RT
2621 /* l3_main_1 -> gpmc */
2622 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc
= {
2623 .master
= &dra7xx_l3_main_1_hwmod
,
2624 .slave
= &dra7xx_gpmc_hwmod
,
2625 .clk
= "l3_iclk_div",
2626 .addr
= dra7xx_gpmc_addrs
,
2627 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2630 static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs
[] = {
2632 .pa_start
= 0x480b2000,
2633 .pa_end
= 0x480b201f,
2634 .flags
= ADDR_TYPE_RT
2639 /* l4_per1 -> hdq1w */
2640 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w
= {
2641 .master
= &dra7xx_l4_per1_hwmod
,
2642 .slave
= &dra7xx_hdq1w_hwmod
,
2643 .clk
= "l3_iclk_div",
2644 .addr
= dra7xx_hdq1w_addrs
,
2645 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2648 /* l4_per1 -> i2c1 */
2649 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1
= {
2650 .master
= &dra7xx_l4_per1_hwmod
,
2651 .slave
= &dra7xx_i2c1_hwmod
,
2652 .clk
= "l3_iclk_div",
2653 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2656 /* l4_per1 -> i2c2 */
2657 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2
= {
2658 .master
= &dra7xx_l4_per1_hwmod
,
2659 .slave
= &dra7xx_i2c2_hwmod
,
2660 .clk
= "l3_iclk_div",
2661 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2664 /* l4_per1 -> i2c3 */
2665 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3
= {
2666 .master
= &dra7xx_l4_per1_hwmod
,
2667 .slave
= &dra7xx_i2c3_hwmod
,
2668 .clk
= "l3_iclk_div",
2669 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2672 /* l4_per1 -> i2c4 */
2673 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4
= {
2674 .master
= &dra7xx_l4_per1_hwmod
,
2675 .slave
= &dra7xx_i2c4_hwmod
,
2676 .clk
= "l3_iclk_div",
2677 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2680 /* l4_per1 -> i2c5 */
2681 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5
= {
2682 .master
= &dra7xx_l4_per1_hwmod
,
2683 .slave
= &dra7xx_i2c5_hwmod
,
2684 .clk
= "l3_iclk_div",
2685 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2688 /* l4_cfg -> mailbox1 */
2689 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1
= {
2690 .master
= &dra7xx_l4_cfg_hwmod
,
2691 .slave
= &dra7xx_mailbox1_hwmod
,
2692 .clk
= "l3_iclk_div",
2693 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2696 /* l4_per3 -> mailbox2 */
2697 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2
= {
2698 .master
= &dra7xx_l4_per3_hwmod
,
2699 .slave
= &dra7xx_mailbox2_hwmod
,
2700 .clk
= "l3_iclk_div",
2701 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2704 /* l4_per3 -> mailbox3 */
2705 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3
= {
2706 .master
= &dra7xx_l4_per3_hwmod
,
2707 .slave
= &dra7xx_mailbox3_hwmod
,
2708 .clk
= "l3_iclk_div",
2709 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2712 /* l4_per3 -> mailbox4 */
2713 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4
= {
2714 .master
= &dra7xx_l4_per3_hwmod
,
2715 .slave
= &dra7xx_mailbox4_hwmod
,
2716 .clk
= "l3_iclk_div",
2717 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2720 /* l4_per3 -> mailbox5 */
2721 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5
= {
2722 .master
= &dra7xx_l4_per3_hwmod
,
2723 .slave
= &dra7xx_mailbox5_hwmod
,
2724 .clk
= "l3_iclk_div",
2725 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2728 /* l4_per3 -> mailbox6 */
2729 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6
= {
2730 .master
= &dra7xx_l4_per3_hwmod
,
2731 .slave
= &dra7xx_mailbox6_hwmod
,
2732 .clk
= "l3_iclk_div",
2733 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2736 /* l4_per3 -> mailbox7 */
2737 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7
= {
2738 .master
= &dra7xx_l4_per3_hwmod
,
2739 .slave
= &dra7xx_mailbox7_hwmod
,
2740 .clk
= "l3_iclk_div",
2741 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2744 /* l4_per3 -> mailbox8 */
2745 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8
= {
2746 .master
= &dra7xx_l4_per3_hwmod
,
2747 .slave
= &dra7xx_mailbox8_hwmod
,
2748 .clk
= "l3_iclk_div",
2749 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2752 /* l4_per3 -> mailbox9 */
2753 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9
= {
2754 .master
= &dra7xx_l4_per3_hwmod
,
2755 .slave
= &dra7xx_mailbox9_hwmod
,
2756 .clk
= "l3_iclk_div",
2757 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2760 /* l4_per3 -> mailbox10 */
2761 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10
= {
2762 .master
= &dra7xx_l4_per3_hwmod
,
2763 .slave
= &dra7xx_mailbox10_hwmod
,
2764 .clk
= "l3_iclk_div",
2765 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2768 /* l4_per3 -> mailbox11 */
2769 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11
= {
2770 .master
= &dra7xx_l4_per3_hwmod
,
2771 .slave
= &dra7xx_mailbox11_hwmod
,
2772 .clk
= "l3_iclk_div",
2773 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2776 /* l4_per3 -> mailbox12 */
2777 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12
= {
2778 .master
= &dra7xx_l4_per3_hwmod
,
2779 .slave
= &dra7xx_mailbox12_hwmod
,
2780 .clk
= "l3_iclk_div",
2781 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2784 /* l4_per3 -> mailbox13 */
2785 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13
= {
2786 .master
= &dra7xx_l4_per3_hwmod
,
2787 .slave
= &dra7xx_mailbox13_hwmod
,
2788 .clk
= "l3_iclk_div",
2789 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2792 /* l4_per1 -> mcspi1 */
2793 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1
= {
2794 .master
= &dra7xx_l4_per1_hwmod
,
2795 .slave
= &dra7xx_mcspi1_hwmod
,
2796 .clk
= "l3_iclk_div",
2797 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2800 /* l4_per1 -> mcspi2 */
2801 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2
= {
2802 .master
= &dra7xx_l4_per1_hwmod
,
2803 .slave
= &dra7xx_mcspi2_hwmod
,
2804 .clk
= "l3_iclk_div",
2805 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2808 /* l4_per1 -> mcspi3 */
2809 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3
= {
2810 .master
= &dra7xx_l4_per1_hwmod
,
2811 .slave
= &dra7xx_mcspi3_hwmod
,
2812 .clk
= "l3_iclk_div",
2813 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2816 /* l4_per1 -> mcspi4 */
2817 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4
= {
2818 .master
= &dra7xx_l4_per1_hwmod
,
2819 .slave
= &dra7xx_mcspi4_hwmod
,
2820 .clk
= "l3_iclk_div",
2821 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2824 /* l4_per1 -> mmc1 */
2825 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1
= {
2826 .master
= &dra7xx_l4_per1_hwmod
,
2827 .slave
= &dra7xx_mmc1_hwmod
,
2828 .clk
= "l3_iclk_div",
2829 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2832 /* l4_per1 -> mmc2 */
2833 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2
= {
2834 .master
= &dra7xx_l4_per1_hwmod
,
2835 .slave
= &dra7xx_mmc2_hwmod
,
2836 .clk
= "l3_iclk_div",
2837 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2840 /* l4_per1 -> mmc3 */
2841 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3
= {
2842 .master
= &dra7xx_l4_per1_hwmod
,
2843 .slave
= &dra7xx_mmc3_hwmod
,
2844 .clk
= "l3_iclk_div",
2845 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2848 /* l4_per1 -> mmc4 */
2849 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4
= {
2850 .master
= &dra7xx_l4_per1_hwmod
,
2851 .slave
= &dra7xx_mmc4_hwmod
,
2852 .clk
= "l3_iclk_div",
2853 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2857 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu
= {
2858 .master
= &dra7xx_l4_cfg_hwmod
,
2859 .slave
= &dra7xx_mpu_hwmod
,
2860 .clk
= "l3_iclk_div",
2861 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2864 /* l4_cfg -> ocp2scp1 */
2865 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1
= {
2866 .master
= &dra7xx_l4_cfg_hwmod
,
2867 .slave
= &dra7xx_ocp2scp1_hwmod
,
2868 .clk
= "l4_root_clk_div",
2869 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2872 /* l4_cfg -> ocp2scp3 */
2873 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3
= {
2874 .master
= &dra7xx_l4_cfg_hwmod
,
2875 .slave
= &dra7xx_ocp2scp3_hwmod
,
2876 .clk
= "l4_root_clk_div",
2877 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2880 /* l3_main_1 -> pcie1 */
2881 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie1
= {
2882 .master
= &dra7xx_l3_main_1_hwmod
,
2883 .slave
= &dra7xx_pcie1_hwmod
,
2884 .clk
= "l3_iclk_div",
2885 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2888 /* l4_cfg -> pcie1 */
2889 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1
= {
2890 .master
= &dra7xx_l4_cfg_hwmod
,
2891 .slave
= &dra7xx_pcie1_hwmod
,
2892 .clk
= "l4_root_clk_div",
2893 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2896 /* l3_main_1 -> pcie2 */
2897 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie2
= {
2898 .master
= &dra7xx_l3_main_1_hwmod
,
2899 .slave
= &dra7xx_pcie2_hwmod
,
2900 .clk
= "l3_iclk_div",
2901 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2904 /* l4_cfg -> pcie2 */
2905 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2
= {
2906 .master
= &dra7xx_l4_cfg_hwmod
,
2907 .slave
= &dra7xx_pcie2_hwmod
,
2908 .clk
= "l4_root_clk_div",
2909 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2912 /* l4_cfg -> pcie1 phy */
2913 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy
= {
2914 .master
= &dra7xx_l4_cfg_hwmod
,
2915 .slave
= &dra7xx_pcie1_phy_hwmod
,
2916 .clk
= "l4_root_clk_div",
2917 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2920 /* l4_cfg -> pcie2 phy */
2921 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2_phy
= {
2922 .master
= &dra7xx_l4_cfg_hwmod
,
2923 .slave
= &dra7xx_pcie2_phy_hwmod
,
2924 .clk
= "l4_root_clk_div",
2925 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2928 static struct omap_hwmod_addr_space dra7xx_qspi_addrs
[] = {
2930 .pa_start
= 0x4b300000,
2931 .pa_end
= 0x4b30007f,
2932 .flags
= ADDR_TYPE_RT
2937 /* l3_main_1 -> qspi */
2938 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi
= {
2939 .master
= &dra7xx_l3_main_1_hwmod
,
2940 .slave
= &dra7xx_qspi_hwmod
,
2941 .clk
= "l3_iclk_div",
2942 .addr
= dra7xx_qspi_addrs
,
2943 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2946 /* l4_per3 -> rtcss */
2947 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss
= {
2948 .master
= &dra7xx_l4_per3_hwmod
,
2949 .slave
= &dra7xx_rtcss_hwmod
,
2950 .clk
= "l4_root_clk_div",
2951 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2954 static struct omap_hwmod_addr_space dra7xx_sata_addrs
[] = {
2957 .pa_start
= 0x4a141100,
2958 .pa_end
= 0x4a141107,
2959 .flags
= ADDR_TYPE_RT
2964 /* l4_cfg -> sata */
2965 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata
= {
2966 .master
= &dra7xx_l4_cfg_hwmod
,
2967 .slave
= &dra7xx_sata_hwmod
,
2968 .clk
= "l3_iclk_div",
2969 .addr
= dra7xx_sata_addrs
,
2970 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2973 static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs
[] = {
2975 .pa_start
= 0x4a0dd000,
2976 .pa_end
= 0x4a0dd07f,
2977 .flags
= ADDR_TYPE_RT
2982 /* l4_cfg -> smartreflex_core */
2983 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core
= {
2984 .master
= &dra7xx_l4_cfg_hwmod
,
2985 .slave
= &dra7xx_smartreflex_core_hwmod
,
2986 .clk
= "l4_root_clk_div",
2987 .addr
= dra7xx_smartreflex_core_addrs
,
2988 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2991 static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs
[] = {
2993 .pa_start
= 0x4a0d9000,
2994 .pa_end
= 0x4a0d907f,
2995 .flags
= ADDR_TYPE_RT
3000 /* l4_cfg -> smartreflex_mpu */
3001 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu
= {
3002 .master
= &dra7xx_l4_cfg_hwmod
,
3003 .slave
= &dra7xx_smartreflex_mpu_hwmod
,
3004 .clk
= "l4_root_clk_div",
3005 .addr
= dra7xx_smartreflex_mpu_addrs
,
3006 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3009 static struct omap_hwmod_addr_space dra7xx_spinlock_addrs
[] = {
3011 .pa_start
= 0x4a0f6000,
3012 .pa_end
= 0x4a0f6fff,
3013 .flags
= ADDR_TYPE_RT
3018 /* l4_cfg -> spinlock */
3019 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock
= {
3020 .master
= &dra7xx_l4_cfg_hwmod
,
3021 .slave
= &dra7xx_spinlock_hwmod
,
3022 .clk
= "l3_iclk_div",
3023 .addr
= dra7xx_spinlock_addrs
,
3024 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3027 /* l4_wkup -> timer1 */
3028 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1
= {
3029 .master
= &dra7xx_l4_wkup_hwmod
,
3030 .slave
= &dra7xx_timer1_hwmod
,
3031 .clk
= "wkupaon_iclk_mux",
3032 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3035 /* l4_per1 -> timer2 */
3036 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2
= {
3037 .master
= &dra7xx_l4_per1_hwmod
,
3038 .slave
= &dra7xx_timer2_hwmod
,
3039 .clk
= "l3_iclk_div",
3040 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3043 /* l4_per1 -> timer3 */
3044 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3
= {
3045 .master
= &dra7xx_l4_per1_hwmod
,
3046 .slave
= &dra7xx_timer3_hwmod
,
3047 .clk
= "l3_iclk_div",
3048 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3051 /* l4_per1 -> timer4 */
3052 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4
= {
3053 .master
= &dra7xx_l4_per1_hwmod
,
3054 .slave
= &dra7xx_timer4_hwmod
,
3055 .clk
= "l3_iclk_div",
3056 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3059 /* l4_per3 -> timer5 */
3060 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5
= {
3061 .master
= &dra7xx_l4_per3_hwmod
,
3062 .slave
= &dra7xx_timer5_hwmod
,
3063 .clk
= "l3_iclk_div",
3064 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3067 /* l4_per3 -> timer6 */
3068 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6
= {
3069 .master
= &dra7xx_l4_per3_hwmod
,
3070 .slave
= &dra7xx_timer6_hwmod
,
3071 .clk
= "l3_iclk_div",
3072 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3075 /* l4_per3 -> timer7 */
3076 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7
= {
3077 .master
= &dra7xx_l4_per3_hwmod
,
3078 .slave
= &dra7xx_timer7_hwmod
,
3079 .clk
= "l3_iclk_div",
3080 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3083 /* l4_per3 -> timer8 */
3084 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8
= {
3085 .master
= &dra7xx_l4_per3_hwmod
,
3086 .slave
= &dra7xx_timer8_hwmod
,
3087 .clk
= "l3_iclk_div",
3088 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3091 /* l4_per1 -> timer9 */
3092 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9
= {
3093 .master
= &dra7xx_l4_per1_hwmod
,
3094 .slave
= &dra7xx_timer9_hwmod
,
3095 .clk
= "l3_iclk_div",
3096 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3099 /* l4_per1 -> timer10 */
3100 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10
= {
3101 .master
= &dra7xx_l4_per1_hwmod
,
3102 .slave
= &dra7xx_timer10_hwmod
,
3103 .clk
= "l3_iclk_div",
3104 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3107 /* l4_per1 -> timer11 */
3108 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11
= {
3109 .master
= &dra7xx_l4_per1_hwmod
,
3110 .slave
= &dra7xx_timer11_hwmod
,
3111 .clk
= "l3_iclk_div",
3112 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3115 /* l4_per1 -> uart1 */
3116 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1
= {
3117 .master
= &dra7xx_l4_per1_hwmod
,
3118 .slave
= &dra7xx_uart1_hwmod
,
3119 .clk
= "l3_iclk_div",
3120 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3123 /* l4_per1 -> uart2 */
3124 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2
= {
3125 .master
= &dra7xx_l4_per1_hwmod
,
3126 .slave
= &dra7xx_uart2_hwmod
,
3127 .clk
= "l3_iclk_div",
3128 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3131 /* l4_per1 -> uart3 */
3132 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3
= {
3133 .master
= &dra7xx_l4_per1_hwmod
,
3134 .slave
= &dra7xx_uart3_hwmod
,
3135 .clk
= "l3_iclk_div",
3136 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3139 /* l4_per1 -> uart4 */
3140 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4
= {
3141 .master
= &dra7xx_l4_per1_hwmod
,
3142 .slave
= &dra7xx_uart4_hwmod
,
3143 .clk
= "l3_iclk_div",
3144 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3147 /* l4_per1 -> uart5 */
3148 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5
= {
3149 .master
= &dra7xx_l4_per1_hwmod
,
3150 .slave
= &dra7xx_uart5_hwmod
,
3151 .clk
= "l3_iclk_div",
3152 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3155 /* l4_per1 -> uart6 */
3156 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6
= {
3157 .master
= &dra7xx_l4_per1_hwmod
,
3158 .slave
= &dra7xx_uart6_hwmod
,
3159 .clk
= "l3_iclk_div",
3160 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3163 /* l4_per2 -> uart7 */
3164 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7
= {
3165 .master
= &dra7xx_l4_per2_hwmod
,
3166 .slave
= &dra7xx_uart7_hwmod
,
3167 .clk
= "l3_iclk_div",
3168 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3171 /* l4_per2 -> uart8 */
3172 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8
= {
3173 .master
= &dra7xx_l4_per2_hwmod
,
3174 .slave
= &dra7xx_uart8_hwmod
,
3175 .clk
= "l3_iclk_div",
3176 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3179 /* l4_per2 -> uart9 */
3180 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9
= {
3181 .master
= &dra7xx_l4_per2_hwmod
,
3182 .slave
= &dra7xx_uart9_hwmod
,
3183 .clk
= "l3_iclk_div",
3184 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3187 /* l4_wkup -> uart10 */
3188 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10
= {
3189 .master
= &dra7xx_l4_wkup_hwmod
,
3190 .slave
= &dra7xx_uart10_hwmod
,
3191 .clk
= "wkupaon_iclk_mux",
3192 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3195 /* l4_per3 -> usb_otg_ss1 */
3196 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1
= {
3197 .master
= &dra7xx_l4_per3_hwmod
,
3198 .slave
= &dra7xx_usb_otg_ss1_hwmod
,
3199 .clk
= "dpll_core_h13x2_ck",
3200 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3203 /* l4_per3 -> usb_otg_ss2 */
3204 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2
= {
3205 .master
= &dra7xx_l4_per3_hwmod
,
3206 .slave
= &dra7xx_usb_otg_ss2_hwmod
,
3207 .clk
= "dpll_core_h13x2_ck",
3208 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3211 /* l4_per3 -> usb_otg_ss3 */
3212 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3
= {
3213 .master
= &dra7xx_l4_per3_hwmod
,
3214 .slave
= &dra7xx_usb_otg_ss3_hwmod
,
3215 .clk
= "dpll_core_h13x2_ck",
3216 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3219 /* l4_per3 -> usb_otg_ss4 */
3220 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4
= {
3221 .master
= &dra7xx_l4_per3_hwmod
,
3222 .slave
= &dra7xx_usb_otg_ss4_hwmod
,
3223 .clk
= "dpll_core_h13x2_ck",
3224 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3227 /* l3_main_1 -> vcp1 */
3228 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1
= {
3229 .master
= &dra7xx_l3_main_1_hwmod
,
3230 .slave
= &dra7xx_vcp1_hwmod
,
3231 .clk
= "l3_iclk_div",
3232 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3235 /* l4_per2 -> vcp1 */
3236 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1
= {
3237 .master
= &dra7xx_l4_per2_hwmod
,
3238 .slave
= &dra7xx_vcp1_hwmod
,
3239 .clk
= "l3_iclk_div",
3240 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3243 /* l3_main_1 -> vcp2 */
3244 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2
= {
3245 .master
= &dra7xx_l3_main_1_hwmod
,
3246 .slave
= &dra7xx_vcp2_hwmod
,
3247 .clk
= "l3_iclk_div",
3248 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3251 /* l4_per2 -> vcp2 */
3252 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2
= {
3253 .master
= &dra7xx_l4_per2_hwmod
,
3254 .slave
= &dra7xx_vcp2_hwmod
,
3255 .clk
= "l3_iclk_div",
3256 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3259 /* l4_wkup -> wd_timer2 */
3260 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2
= {
3261 .master
= &dra7xx_l4_wkup_hwmod
,
3262 .slave
= &dra7xx_wd_timer2_hwmod
,
3263 .clk
= "wkupaon_iclk_mux",
3264 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3267 static struct omap_hwmod_ocp_if
*dra7xx_hwmod_ocp_ifs
[] __initdata
= {
3268 &dra7xx_l3_main_2__l3_instr
,
3269 &dra7xx_l4_cfg__l3_main_1
,
3270 &dra7xx_mpu__l3_main_1
,
3271 &dra7xx_l3_main_1__l3_main_2
,
3272 &dra7xx_l4_cfg__l3_main_2
,
3273 &dra7xx_l3_main_1__l4_cfg
,
3274 &dra7xx_l3_main_1__l4_per1
,
3275 &dra7xx_l3_main_1__l4_per2
,
3276 &dra7xx_l3_main_1__l4_per3
,
3277 &dra7xx_l3_main_1__l4_wkup
,
3278 &dra7xx_l4_per2__atl
,
3279 &dra7xx_l3_main_1__bb2d
,
3280 &dra7xx_l4_wkup__counter_32k
,
3281 &dra7xx_l4_wkup__ctrl_module_wkup
,
3282 &dra7xx_l4_wkup__dcan1
,
3283 &dra7xx_l4_per2__dcan2
,
3284 &dra7xx_l4_per2__cpgmac0
,
3286 &dra7xx_l4_cfg__dma_system
,
3287 &dra7xx_l3_main_1__dss
,
3288 &dra7xx_l3_main_1__dispc
,
3289 &dra7xx_l3_main_1__hdmi
,
3290 &dra7xx_l4_per1__elm
,
3291 &dra7xx_l4_wkup__gpio1
,
3292 &dra7xx_l4_per1__gpio2
,
3293 &dra7xx_l4_per1__gpio3
,
3294 &dra7xx_l4_per1__gpio4
,
3295 &dra7xx_l4_per1__gpio5
,
3296 &dra7xx_l4_per1__gpio6
,
3297 &dra7xx_l4_per1__gpio7
,
3298 &dra7xx_l4_per1__gpio8
,
3299 &dra7xx_l3_main_1__gpmc
,
3300 &dra7xx_l4_per1__hdq1w
,
3301 &dra7xx_l4_per1__i2c1
,
3302 &dra7xx_l4_per1__i2c2
,
3303 &dra7xx_l4_per1__i2c3
,
3304 &dra7xx_l4_per1__i2c4
,
3305 &dra7xx_l4_per1__i2c5
,
3306 &dra7xx_l4_cfg__mailbox1
,
3307 &dra7xx_l4_per3__mailbox2
,
3308 &dra7xx_l4_per3__mailbox3
,
3309 &dra7xx_l4_per3__mailbox4
,
3310 &dra7xx_l4_per3__mailbox5
,
3311 &dra7xx_l4_per3__mailbox6
,
3312 &dra7xx_l4_per3__mailbox7
,
3313 &dra7xx_l4_per3__mailbox8
,
3314 &dra7xx_l4_per3__mailbox9
,
3315 &dra7xx_l4_per3__mailbox10
,
3316 &dra7xx_l4_per3__mailbox11
,
3317 &dra7xx_l4_per3__mailbox12
,
3318 &dra7xx_l4_per3__mailbox13
,
3319 &dra7xx_l4_per1__mcspi1
,
3320 &dra7xx_l4_per1__mcspi2
,
3321 &dra7xx_l4_per1__mcspi3
,
3322 &dra7xx_l4_per1__mcspi4
,
3323 &dra7xx_l4_per1__mmc1
,
3324 &dra7xx_l4_per1__mmc2
,
3325 &dra7xx_l4_per1__mmc3
,
3326 &dra7xx_l4_per1__mmc4
,
3327 &dra7xx_l4_cfg__mpu
,
3328 &dra7xx_l4_cfg__ocp2scp1
,
3329 &dra7xx_l4_cfg__ocp2scp3
,
3330 &dra7xx_l3_main_1__pcie1
,
3331 &dra7xx_l4_cfg__pcie1
,
3332 &dra7xx_l3_main_1__pcie2
,
3333 &dra7xx_l4_cfg__pcie2
,
3334 &dra7xx_l4_cfg__pcie1_phy
,
3335 &dra7xx_l4_cfg__pcie2_phy
,
3336 &dra7xx_l3_main_1__qspi
,
3337 &dra7xx_l4_per3__rtcss
,
3338 &dra7xx_l4_cfg__sata
,
3339 &dra7xx_l4_cfg__smartreflex_core
,
3340 &dra7xx_l4_cfg__smartreflex_mpu
,
3341 &dra7xx_l4_cfg__spinlock
,
3342 &dra7xx_l4_wkup__timer1
,
3343 &dra7xx_l4_per1__timer2
,
3344 &dra7xx_l4_per1__timer3
,
3345 &dra7xx_l4_per1__timer4
,
3346 &dra7xx_l4_per3__timer5
,
3347 &dra7xx_l4_per3__timer6
,
3348 &dra7xx_l4_per3__timer7
,
3349 &dra7xx_l4_per3__timer8
,
3350 &dra7xx_l4_per1__timer9
,
3351 &dra7xx_l4_per1__timer10
,
3352 &dra7xx_l4_per1__timer11
,
3353 &dra7xx_l4_per1__uart1
,
3354 &dra7xx_l4_per1__uart2
,
3355 &dra7xx_l4_per1__uart3
,
3356 &dra7xx_l4_per1__uart4
,
3357 &dra7xx_l4_per1__uart5
,
3358 &dra7xx_l4_per1__uart6
,
3359 &dra7xx_l4_per2__uart7
,
3360 &dra7xx_l4_per2__uart8
,
3361 &dra7xx_l4_per2__uart9
,
3362 &dra7xx_l4_wkup__uart10
,
3363 &dra7xx_l4_per3__usb_otg_ss1
,
3364 &dra7xx_l4_per3__usb_otg_ss2
,
3365 &dra7xx_l4_per3__usb_otg_ss3
,
3366 &dra7xx_l3_main_1__vcp1
,
3367 &dra7xx_l4_per2__vcp1
,
3368 &dra7xx_l3_main_1__vcp2
,
3369 &dra7xx_l4_per2__vcp2
,
3370 &dra7xx_l4_wkup__wd_timer2
,
3374 static struct omap_hwmod_ocp_if
*dra74x_hwmod_ocp_ifs
[] __initdata
= {
3375 &dra7xx_l4_per3__usb_otg_ss4
,
3379 static struct omap_hwmod_ocp_if
*dra72x_hwmod_ocp_ifs
[] __initdata
= {
3383 int __init
dra7xx_hwmod_init(void)
3388 ret
= omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs
);
3390 if (!ret
&& soc_is_dra74x())
3391 return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs
);
3392 else if (!ret
&& soc_is_dra72x())
3393 return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs
);