2 * Hardware modules present on the DRA7xx chips
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
21 #include <linux/platform_data/gpio-omap.h>
22 #include <linux/platform_data/hsmmc-omap.h>
23 #include <linux/power/smartreflex.h>
24 #include <linux/i2c-omap.h>
26 #include <linux/omap-dma.h>
27 #include <linux/platform_data/spi-omap2-mcspi.h>
28 #include <linux/platform_data/asoc-ti-mcbsp.h>
29 #include <plat/dmtimer.h>
31 #include "omap_hwmod.h"
32 #include "omap_hwmod_common_data.h"
40 /* Base offset for all DRA7XX interrupts external to MPUSS */
41 #define DRA7XX_IRQ_GIC_START 32
43 /* Base offset for all DRA7XX dma requests */
44 #define DRA7XX_DMA_REQ_START 1
53 * instance(s): l3_instr, l3_main_1, l3_main_2
55 static struct omap_hwmod_class dra7xx_l3_hwmod_class
= {
60 static struct omap_hwmod dra7xx_l3_instr_hwmod
= {
62 .class = &dra7xx_l3_hwmod_class
,
63 .clkdm_name
= "l3instr_clkdm",
66 .clkctrl_offs
= DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET
,
67 .context_offs
= DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET
,
68 .modulemode
= MODULEMODE_HWCTRL
,
74 static struct omap_hwmod dra7xx_l3_main_1_hwmod
= {
76 .class = &dra7xx_l3_hwmod_class
,
77 .clkdm_name
= "l3main1_clkdm",
80 .clkctrl_offs
= DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET
,
81 .context_offs
= DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET
,
87 static struct omap_hwmod dra7xx_l3_main_2_hwmod
= {
89 .class = &dra7xx_l3_hwmod_class
,
90 .clkdm_name
= "l3instr_clkdm",
93 .clkctrl_offs
= DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET
,
94 .context_offs
= DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET
,
95 .modulemode
= MODULEMODE_HWCTRL
,
102 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
104 static struct omap_hwmod_class dra7xx_l4_hwmod_class
= {
109 static struct omap_hwmod dra7xx_l4_cfg_hwmod
= {
111 .class = &dra7xx_l4_hwmod_class
,
112 .clkdm_name
= "l4cfg_clkdm",
115 .clkctrl_offs
= DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET
,
116 .context_offs
= DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET
,
122 static struct omap_hwmod dra7xx_l4_per1_hwmod
= {
124 .class = &dra7xx_l4_hwmod_class
,
125 .clkdm_name
= "l4per_clkdm",
128 .clkctrl_offs
= DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET
,
129 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
135 static struct omap_hwmod dra7xx_l4_per2_hwmod
= {
137 .class = &dra7xx_l4_hwmod_class
,
138 .clkdm_name
= "l4per2_clkdm",
141 .clkctrl_offs
= DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET
,
142 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
148 static struct omap_hwmod dra7xx_l4_per3_hwmod
= {
150 .class = &dra7xx_l4_hwmod_class
,
151 .clkdm_name
= "l4per3_clkdm",
154 .clkctrl_offs
= DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET
,
155 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
161 static struct omap_hwmod dra7xx_l4_wkup_hwmod
= {
163 .class = &dra7xx_l4_hwmod_class
,
164 .clkdm_name
= "wkupaon_clkdm",
167 .clkctrl_offs
= DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET
,
168 .context_offs
= DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET
,
178 static struct omap_hwmod_class dra7xx_atl_hwmod_class
= {
183 static struct omap_hwmod dra7xx_atl_hwmod
= {
185 .class = &dra7xx_atl_hwmod_class
,
186 .clkdm_name
= "atl_clkdm",
187 .main_clk
= "atl_gfclk_mux",
190 .clkctrl_offs
= DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET
,
191 .context_offs
= DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET
,
192 .modulemode
= MODULEMODE_SWCTRL
,
202 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class
= {
207 static struct omap_hwmod dra7xx_bb2d_hwmod
= {
209 .class = &dra7xx_bb2d_hwmod_class
,
210 .clkdm_name
= "dss_clkdm",
211 .main_clk
= "dpll_core_h24x2_ck",
214 .clkctrl_offs
= DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET
,
215 .context_offs
= DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET
,
216 .modulemode
= MODULEMODE_SWCTRL
,
226 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc
= {
229 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
230 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
232 .sysc_fields
= &omap_hwmod_sysc_type1
,
235 static struct omap_hwmod_class dra7xx_counter_hwmod_class
= {
237 .sysc
= &dra7xx_counter_sysc
,
241 static struct omap_hwmod dra7xx_counter_32k_hwmod
= {
242 .name
= "counter_32k",
243 .class = &dra7xx_counter_hwmod_class
,
244 .clkdm_name
= "wkupaon_clkdm",
245 .flags
= HWMOD_SWSUP_SIDLE
,
246 .main_clk
= "wkupaon_iclk_mux",
249 .clkctrl_offs
= DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET
,
250 .context_offs
= DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET
,
256 * 'ctrl_module' class
260 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class
= {
261 .name
= "ctrl_module",
264 /* ctrl_module_wkup */
265 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod
= {
266 .name
= "ctrl_module_wkup",
267 .class = &dra7xx_ctrl_module_hwmod_class
,
268 .clkdm_name
= "wkupaon_clkdm",
271 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
278 * cpsw/gmac sub system
280 static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc
= {
284 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_MIDLEMODE
|
285 SYSS_HAS_RESET_STATUS
),
286 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| MSTANDBY_FORCE
|
288 .sysc_fields
= &omap_hwmod_sysc_type3
,
291 static struct omap_hwmod_class dra7xx_gmac_hwmod_class
= {
293 .sysc
= &dra7xx_gmac_sysc
,
296 static struct omap_hwmod dra7xx_gmac_hwmod
= {
298 .class = &dra7xx_gmac_hwmod_class
,
299 .clkdm_name
= "gmac_clkdm",
300 .flags
= (HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
),
301 .main_clk
= "dpll_gmac_ck",
305 .clkctrl_offs
= DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET
,
306 .context_offs
= DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET
,
307 .modulemode
= MODULEMODE_SWCTRL
,
315 static struct omap_hwmod_class dra7xx_mdio_hwmod_class
= {
316 .name
= "davinci_mdio",
319 static struct omap_hwmod dra7xx_mdio_hwmod
= {
320 .name
= "davinci_mdio",
321 .class = &dra7xx_mdio_hwmod_class
,
322 .clkdm_name
= "gmac_clkdm",
323 .main_clk
= "dpll_gmac_ck",
331 static struct omap_hwmod_class dra7xx_dcan_hwmod_class
= {
336 static struct omap_hwmod dra7xx_dcan1_hwmod
= {
338 .class = &dra7xx_dcan_hwmod_class
,
339 .clkdm_name
= "wkupaon_clkdm",
340 .main_clk
= "dcan1_sys_clk_mux",
343 .clkctrl_offs
= DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET
,
344 .context_offs
= DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET
,
345 .modulemode
= MODULEMODE_SWCTRL
,
351 static struct omap_hwmod dra7xx_dcan2_hwmod
= {
353 .class = &dra7xx_dcan_hwmod_class
,
354 .clkdm_name
= "l4per2_clkdm",
355 .main_clk
= "sys_clkin1",
358 .clkctrl_offs
= DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET
,
359 .context_offs
= DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET
,
360 .modulemode
= MODULEMODE_SWCTRL
,
370 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc
= {
374 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
375 SYSC_HAS_EMUFREE
| SYSC_HAS_MIDLEMODE
|
376 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
377 SYSS_HAS_RESET_STATUS
),
378 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
379 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
380 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
381 .sysc_fields
= &omap_hwmod_sysc_type1
,
384 static struct omap_hwmod_class dra7xx_dma_hwmod_class
= {
386 .sysc
= &dra7xx_dma_sysc
,
390 static struct omap_dma_dev_attr dma_dev_attr
= {
391 .dev_caps
= RESERVE_CHANNEL
| DMA_LINKED_LCH
| GLOBAL_PRIORITY
|
392 IS_CSSA_32
| IS_CDSA_32
| IS_RW_PRIORITY
,
397 static struct omap_hwmod dra7xx_dma_system_hwmod
= {
398 .name
= "dma_system",
399 .class = &dra7xx_dma_hwmod_class
,
400 .clkdm_name
= "dma_clkdm",
401 .main_clk
= "l3_iclk_div",
404 .clkctrl_offs
= DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET
,
405 .context_offs
= DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET
,
408 .dev_attr
= &dma_dev_attr
,
416 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc
= {
419 .sysc_flags
= SYSS_HAS_RESET_STATUS
,
422 static struct omap_hwmod_class dra7xx_dss_hwmod_class
= {
424 .sysc
= &dra7xx_dss_sysc
,
425 .reset
= omap_dss_reset
,
429 static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs
[] = {
430 { .dma_req
= 75 + DRA7XX_DMA_REQ_START
},
434 static struct omap_hwmod_opt_clk dss_opt_clks
[] = {
435 { .role
= "dss_clk", .clk
= "dss_dss_clk" },
436 { .role
= "hdmi_phy_clk", .clk
= "dss_48mhz_clk" },
437 { .role
= "32khz_clk", .clk
= "dss_32khz_clk" },
438 { .role
= "video2_clk", .clk
= "dss_video2_clk" },
439 { .role
= "video1_clk", .clk
= "dss_video1_clk" },
440 { .role
= "hdmi_clk", .clk
= "dss_hdmi_clk" },
443 static struct omap_hwmod dra7xx_dss_hwmod
= {
445 .class = &dra7xx_dss_hwmod_class
,
446 .clkdm_name
= "dss_clkdm",
447 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
448 .sdma_reqs
= dra7xx_dss_sdma_reqs
,
449 .main_clk
= "dss_dss_clk",
452 .clkctrl_offs
= DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET
,
453 .context_offs
= DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET
,
454 .modulemode
= MODULEMODE_SWCTRL
,
457 .opt_clks
= dss_opt_clks
,
458 .opt_clks_cnt
= ARRAY_SIZE(dss_opt_clks
),
466 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc
= {
470 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
471 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_MIDLEMODE
|
472 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
473 SYSS_HAS_RESET_STATUS
),
474 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
475 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
476 .sysc_fields
= &omap_hwmod_sysc_type1
,
479 static struct omap_hwmod_class dra7xx_dispc_hwmod_class
= {
481 .sysc
= &dra7xx_dispc_sysc
,
485 /* dss_dispc dev_attr */
486 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr
= {
487 .has_framedonetv_irq
= 1,
491 static struct omap_hwmod dra7xx_dss_dispc_hwmod
= {
493 .class = &dra7xx_dispc_hwmod_class
,
494 .clkdm_name
= "dss_clkdm",
495 .main_clk
= "dss_dss_clk",
498 .clkctrl_offs
= DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET
,
499 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
502 .dev_attr
= &dss_dispc_dev_attr
,
510 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc
= {
513 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
515 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
517 .sysc_fields
= &omap_hwmod_sysc_type2
,
520 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class
= {
522 .sysc
= &dra7xx_hdmi_sysc
,
527 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks
[] = {
528 { .role
= "sys_clk", .clk
= "dss_hdmi_clk" },
531 static struct omap_hwmod dra7xx_dss_hdmi_hwmod
= {
533 .class = &dra7xx_hdmi_hwmod_class
,
534 .clkdm_name
= "dss_clkdm",
535 .main_clk
= "dss_48mhz_clk",
538 .clkctrl_offs
= DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET
,
539 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
542 .opt_clks
= dss_hdmi_opt_clks
,
543 .opt_clks_cnt
= ARRAY_SIZE(dss_hdmi_opt_clks
),
551 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc
= {
555 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
556 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
557 SYSS_HAS_RESET_STATUS
),
558 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
560 .sysc_fields
= &omap_hwmod_sysc_type1
,
563 static struct omap_hwmod_class dra7xx_elm_hwmod_class
= {
565 .sysc
= &dra7xx_elm_sysc
,
570 static struct omap_hwmod dra7xx_elm_hwmod
= {
572 .class = &dra7xx_elm_hwmod_class
,
573 .clkdm_name
= "l4per_clkdm",
574 .main_clk
= "l3_iclk_div",
577 .clkctrl_offs
= DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET
,
578 .context_offs
= DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET
,
588 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc
= {
592 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
593 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
594 SYSS_HAS_RESET_STATUS
),
595 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
597 .sysc_fields
= &omap_hwmod_sysc_type1
,
600 static struct omap_hwmod_class dra7xx_gpio_hwmod_class
= {
602 .sysc
= &dra7xx_gpio_sysc
,
607 static struct omap_gpio_dev_attr gpio_dev_attr
= {
613 static struct omap_hwmod_opt_clk gpio1_opt_clks
[] = {
614 { .role
= "dbclk", .clk
= "gpio1_dbclk" },
617 static struct omap_hwmod dra7xx_gpio1_hwmod
= {
619 .class = &dra7xx_gpio_hwmod_class
,
620 .clkdm_name
= "wkupaon_clkdm",
621 .main_clk
= "wkupaon_iclk_mux",
624 .clkctrl_offs
= DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET
,
625 .context_offs
= DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET
,
626 .modulemode
= MODULEMODE_HWCTRL
,
629 .opt_clks
= gpio1_opt_clks
,
630 .opt_clks_cnt
= ARRAY_SIZE(gpio1_opt_clks
),
631 .dev_attr
= &gpio_dev_attr
,
635 static struct omap_hwmod_opt_clk gpio2_opt_clks
[] = {
636 { .role
= "dbclk", .clk
= "gpio2_dbclk" },
639 static struct omap_hwmod dra7xx_gpio2_hwmod
= {
641 .class = &dra7xx_gpio_hwmod_class
,
642 .clkdm_name
= "l4per_clkdm",
643 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
644 .main_clk
= "l3_iclk_div",
647 .clkctrl_offs
= DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET
,
648 .context_offs
= DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET
,
649 .modulemode
= MODULEMODE_HWCTRL
,
652 .opt_clks
= gpio2_opt_clks
,
653 .opt_clks_cnt
= ARRAY_SIZE(gpio2_opt_clks
),
654 .dev_attr
= &gpio_dev_attr
,
658 static struct omap_hwmod_opt_clk gpio3_opt_clks
[] = {
659 { .role
= "dbclk", .clk
= "gpio3_dbclk" },
662 static struct omap_hwmod dra7xx_gpio3_hwmod
= {
664 .class = &dra7xx_gpio_hwmod_class
,
665 .clkdm_name
= "l4per_clkdm",
666 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
667 .main_clk
= "l3_iclk_div",
670 .clkctrl_offs
= DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET
,
671 .context_offs
= DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET
,
672 .modulemode
= MODULEMODE_HWCTRL
,
675 .opt_clks
= gpio3_opt_clks
,
676 .opt_clks_cnt
= ARRAY_SIZE(gpio3_opt_clks
),
677 .dev_attr
= &gpio_dev_attr
,
681 static struct omap_hwmod_opt_clk gpio4_opt_clks
[] = {
682 { .role
= "dbclk", .clk
= "gpio4_dbclk" },
685 static struct omap_hwmod dra7xx_gpio4_hwmod
= {
687 .class = &dra7xx_gpio_hwmod_class
,
688 .clkdm_name
= "l4per_clkdm",
689 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
690 .main_clk
= "l3_iclk_div",
693 .clkctrl_offs
= DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET
,
694 .context_offs
= DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET
,
695 .modulemode
= MODULEMODE_HWCTRL
,
698 .opt_clks
= gpio4_opt_clks
,
699 .opt_clks_cnt
= ARRAY_SIZE(gpio4_opt_clks
),
700 .dev_attr
= &gpio_dev_attr
,
704 static struct omap_hwmod_opt_clk gpio5_opt_clks
[] = {
705 { .role
= "dbclk", .clk
= "gpio5_dbclk" },
708 static struct omap_hwmod dra7xx_gpio5_hwmod
= {
710 .class = &dra7xx_gpio_hwmod_class
,
711 .clkdm_name
= "l4per_clkdm",
712 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
713 .main_clk
= "l3_iclk_div",
716 .clkctrl_offs
= DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET
,
717 .context_offs
= DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET
,
718 .modulemode
= MODULEMODE_HWCTRL
,
721 .opt_clks
= gpio5_opt_clks
,
722 .opt_clks_cnt
= ARRAY_SIZE(gpio5_opt_clks
),
723 .dev_attr
= &gpio_dev_attr
,
727 static struct omap_hwmod_opt_clk gpio6_opt_clks
[] = {
728 { .role
= "dbclk", .clk
= "gpio6_dbclk" },
731 static struct omap_hwmod dra7xx_gpio6_hwmod
= {
733 .class = &dra7xx_gpio_hwmod_class
,
734 .clkdm_name
= "l4per_clkdm",
735 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
736 .main_clk
= "l3_iclk_div",
739 .clkctrl_offs
= DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET
,
740 .context_offs
= DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET
,
741 .modulemode
= MODULEMODE_HWCTRL
,
744 .opt_clks
= gpio6_opt_clks
,
745 .opt_clks_cnt
= ARRAY_SIZE(gpio6_opt_clks
),
746 .dev_attr
= &gpio_dev_attr
,
750 static struct omap_hwmod_opt_clk gpio7_opt_clks
[] = {
751 { .role
= "dbclk", .clk
= "gpio7_dbclk" },
754 static struct omap_hwmod dra7xx_gpio7_hwmod
= {
756 .class = &dra7xx_gpio_hwmod_class
,
757 .clkdm_name
= "l4per_clkdm",
758 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
759 .main_clk
= "l3_iclk_div",
762 .clkctrl_offs
= DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET
,
763 .context_offs
= DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET
,
764 .modulemode
= MODULEMODE_HWCTRL
,
767 .opt_clks
= gpio7_opt_clks
,
768 .opt_clks_cnt
= ARRAY_SIZE(gpio7_opt_clks
),
769 .dev_attr
= &gpio_dev_attr
,
773 static struct omap_hwmod_opt_clk gpio8_opt_clks
[] = {
774 { .role
= "dbclk", .clk
= "gpio8_dbclk" },
777 static struct omap_hwmod dra7xx_gpio8_hwmod
= {
779 .class = &dra7xx_gpio_hwmod_class
,
780 .clkdm_name
= "l4per_clkdm",
781 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
782 .main_clk
= "l3_iclk_div",
785 .clkctrl_offs
= DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET
,
786 .context_offs
= DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET
,
787 .modulemode
= MODULEMODE_HWCTRL
,
790 .opt_clks
= gpio8_opt_clks
,
791 .opt_clks_cnt
= ARRAY_SIZE(gpio8_opt_clks
),
792 .dev_attr
= &gpio_dev_attr
,
800 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc
= {
804 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SIDLEMODE
|
805 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
806 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
808 .sysc_fields
= &omap_hwmod_sysc_type1
,
811 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class
= {
813 .sysc
= &dra7xx_gpmc_sysc
,
818 static struct omap_hwmod dra7xx_gpmc_hwmod
= {
820 .class = &dra7xx_gpmc_hwmod_class
,
821 .clkdm_name
= "l3main1_clkdm",
822 .flags
= (HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
|
824 .main_clk
= "l3_iclk_div",
827 .clkctrl_offs
= DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET
,
828 .context_offs
= DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET
,
829 .modulemode
= MODULEMODE_HWCTRL
,
839 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc
= {
843 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SOFTRESET
|
844 SYSS_HAS_RESET_STATUS
),
845 .sysc_fields
= &omap_hwmod_sysc_type1
,
848 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class
= {
850 .sysc
= &dra7xx_hdq1w_sysc
,
855 static struct omap_hwmod dra7xx_hdq1w_hwmod
= {
857 .class = &dra7xx_hdq1w_hwmod_class
,
858 .clkdm_name
= "l4per_clkdm",
859 .flags
= HWMOD_INIT_NO_RESET
,
860 .main_clk
= "func_12m_fclk",
863 .clkctrl_offs
= DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET
,
864 .context_offs
= DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET
,
865 .modulemode
= MODULEMODE_SWCTRL
,
875 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc
= {
878 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
879 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
880 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
881 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
883 .clockact
= CLOCKACT_TEST_ICLK
,
884 .sysc_fields
= &omap_hwmod_sysc_type1
,
887 static struct omap_hwmod_class dra7xx_i2c_hwmod_class
= {
889 .sysc
= &dra7xx_i2c_sysc
,
890 .reset
= &omap_i2c_reset
,
891 .rev
= OMAP_I2C_IP_VERSION_2
,
895 static struct omap_i2c_dev_attr i2c_dev_attr
= {
896 .flags
= OMAP_I2C_FLAG_BUS_SHIFT_NONE
,
900 static struct omap_hwmod dra7xx_i2c1_hwmod
= {
902 .class = &dra7xx_i2c_hwmod_class
,
903 .clkdm_name
= "l4per_clkdm",
904 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
905 .main_clk
= "func_96m_fclk",
908 .clkctrl_offs
= DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET
,
909 .context_offs
= DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET
,
910 .modulemode
= MODULEMODE_SWCTRL
,
913 .dev_attr
= &i2c_dev_attr
,
917 static struct omap_hwmod dra7xx_i2c2_hwmod
= {
919 .class = &dra7xx_i2c_hwmod_class
,
920 .clkdm_name
= "l4per_clkdm",
921 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
922 .main_clk
= "func_96m_fclk",
925 .clkctrl_offs
= DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET
,
926 .context_offs
= DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET
,
927 .modulemode
= MODULEMODE_SWCTRL
,
930 .dev_attr
= &i2c_dev_attr
,
934 static struct omap_hwmod dra7xx_i2c3_hwmod
= {
936 .class = &dra7xx_i2c_hwmod_class
,
937 .clkdm_name
= "l4per_clkdm",
938 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
939 .main_clk
= "func_96m_fclk",
942 .clkctrl_offs
= DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET
,
943 .context_offs
= DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET
,
944 .modulemode
= MODULEMODE_SWCTRL
,
947 .dev_attr
= &i2c_dev_attr
,
951 static struct omap_hwmod dra7xx_i2c4_hwmod
= {
953 .class = &dra7xx_i2c_hwmod_class
,
954 .clkdm_name
= "l4per_clkdm",
955 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
956 .main_clk
= "func_96m_fclk",
959 .clkctrl_offs
= DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET
,
960 .context_offs
= DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET
,
961 .modulemode
= MODULEMODE_SWCTRL
,
964 .dev_attr
= &i2c_dev_attr
,
968 static struct omap_hwmod dra7xx_i2c5_hwmod
= {
970 .class = &dra7xx_i2c_hwmod_class
,
971 .clkdm_name
= "ipu_clkdm",
972 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
973 .main_clk
= "func_96m_fclk",
976 .clkctrl_offs
= DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET
,
977 .context_offs
= DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET
,
978 .modulemode
= MODULEMODE_SWCTRL
,
981 .dev_attr
= &i2c_dev_attr
,
989 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc
= {
992 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
994 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
995 .sysc_fields
= &omap_hwmod_sysc_type2
,
998 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class
= {
1000 .sysc
= &dra7xx_mailbox_sysc
,
1004 static struct omap_hwmod dra7xx_mailbox1_hwmod
= {
1006 .class = &dra7xx_mailbox_hwmod_class
,
1007 .clkdm_name
= "l4cfg_clkdm",
1010 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET
,
1011 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET
,
1017 static struct omap_hwmod dra7xx_mailbox2_hwmod
= {
1019 .class = &dra7xx_mailbox_hwmod_class
,
1020 .clkdm_name
= "l4cfg_clkdm",
1023 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET
,
1024 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET
,
1030 static struct omap_hwmod dra7xx_mailbox3_hwmod
= {
1032 .class = &dra7xx_mailbox_hwmod_class
,
1033 .clkdm_name
= "l4cfg_clkdm",
1036 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET
,
1037 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET
,
1043 static struct omap_hwmod dra7xx_mailbox4_hwmod
= {
1045 .class = &dra7xx_mailbox_hwmod_class
,
1046 .clkdm_name
= "l4cfg_clkdm",
1049 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET
,
1050 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET
,
1056 static struct omap_hwmod dra7xx_mailbox5_hwmod
= {
1058 .class = &dra7xx_mailbox_hwmod_class
,
1059 .clkdm_name
= "l4cfg_clkdm",
1062 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET
,
1063 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET
,
1069 static struct omap_hwmod dra7xx_mailbox6_hwmod
= {
1071 .class = &dra7xx_mailbox_hwmod_class
,
1072 .clkdm_name
= "l4cfg_clkdm",
1075 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET
,
1076 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET
,
1082 static struct omap_hwmod dra7xx_mailbox7_hwmod
= {
1084 .class = &dra7xx_mailbox_hwmod_class
,
1085 .clkdm_name
= "l4cfg_clkdm",
1088 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET
,
1089 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET
,
1095 static struct omap_hwmod dra7xx_mailbox8_hwmod
= {
1097 .class = &dra7xx_mailbox_hwmod_class
,
1098 .clkdm_name
= "l4cfg_clkdm",
1101 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET
,
1102 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET
,
1108 static struct omap_hwmod dra7xx_mailbox9_hwmod
= {
1110 .class = &dra7xx_mailbox_hwmod_class
,
1111 .clkdm_name
= "l4cfg_clkdm",
1114 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET
,
1115 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET
,
1121 static struct omap_hwmod dra7xx_mailbox10_hwmod
= {
1122 .name
= "mailbox10",
1123 .class = &dra7xx_mailbox_hwmod_class
,
1124 .clkdm_name
= "l4cfg_clkdm",
1127 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET
,
1128 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET
,
1134 static struct omap_hwmod dra7xx_mailbox11_hwmod
= {
1135 .name
= "mailbox11",
1136 .class = &dra7xx_mailbox_hwmod_class
,
1137 .clkdm_name
= "l4cfg_clkdm",
1140 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET
,
1141 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET
,
1147 static struct omap_hwmod dra7xx_mailbox12_hwmod
= {
1148 .name
= "mailbox12",
1149 .class = &dra7xx_mailbox_hwmod_class
,
1150 .clkdm_name
= "l4cfg_clkdm",
1153 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET
,
1154 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET
,
1160 static struct omap_hwmod dra7xx_mailbox13_hwmod
= {
1161 .name
= "mailbox13",
1162 .class = &dra7xx_mailbox_hwmod_class
,
1163 .clkdm_name
= "l4cfg_clkdm",
1166 .clkctrl_offs
= DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET
,
1167 .context_offs
= DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET
,
1177 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc
= {
1179 .sysc_offs
= 0x0010,
1180 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
1181 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1182 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1184 .sysc_fields
= &omap_hwmod_sysc_type2
,
1187 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class
= {
1189 .sysc
= &dra7xx_mcspi_sysc
,
1190 .rev
= OMAP4_MCSPI_REV
,
1194 /* mcspi1 dev_attr */
1195 static struct omap2_mcspi_dev_attr mcspi1_dev_attr
= {
1196 .num_chipselect
= 4,
1199 static struct omap_hwmod dra7xx_mcspi1_hwmod
= {
1201 .class = &dra7xx_mcspi_hwmod_class
,
1202 .clkdm_name
= "l4per_clkdm",
1203 .main_clk
= "func_48m_fclk",
1206 .clkctrl_offs
= DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET
,
1207 .context_offs
= DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET
,
1208 .modulemode
= MODULEMODE_SWCTRL
,
1211 .dev_attr
= &mcspi1_dev_attr
,
1215 /* mcspi2 dev_attr */
1216 static struct omap2_mcspi_dev_attr mcspi2_dev_attr
= {
1217 .num_chipselect
= 2,
1220 static struct omap_hwmod dra7xx_mcspi2_hwmod
= {
1222 .class = &dra7xx_mcspi_hwmod_class
,
1223 .clkdm_name
= "l4per_clkdm",
1224 .main_clk
= "func_48m_fclk",
1227 .clkctrl_offs
= DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET
,
1228 .context_offs
= DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET
,
1229 .modulemode
= MODULEMODE_SWCTRL
,
1232 .dev_attr
= &mcspi2_dev_attr
,
1236 /* mcspi3 dev_attr */
1237 static struct omap2_mcspi_dev_attr mcspi3_dev_attr
= {
1238 .num_chipselect
= 2,
1241 static struct omap_hwmod dra7xx_mcspi3_hwmod
= {
1243 .class = &dra7xx_mcspi_hwmod_class
,
1244 .clkdm_name
= "l4per_clkdm",
1245 .main_clk
= "func_48m_fclk",
1248 .clkctrl_offs
= DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET
,
1249 .context_offs
= DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET
,
1250 .modulemode
= MODULEMODE_SWCTRL
,
1253 .dev_attr
= &mcspi3_dev_attr
,
1257 /* mcspi4 dev_attr */
1258 static struct omap2_mcspi_dev_attr mcspi4_dev_attr
= {
1259 .num_chipselect
= 1,
1262 static struct omap_hwmod dra7xx_mcspi4_hwmod
= {
1264 .class = &dra7xx_mcspi_hwmod_class
,
1265 .clkdm_name
= "l4per_clkdm",
1266 .main_clk
= "func_48m_fclk",
1269 .clkctrl_offs
= DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET
,
1270 .context_offs
= DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET
,
1271 .modulemode
= MODULEMODE_SWCTRL
,
1274 .dev_attr
= &mcspi4_dev_attr
,
1282 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc
= {
1284 .sysc_offs
= 0x0010,
1285 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_MIDLEMODE
|
1286 SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
1287 SYSC_HAS_SOFTRESET
),
1288 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1289 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1290 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1291 .sysc_fields
= &omap_hwmod_sysc_type2
,
1294 static struct omap_hwmod_class dra7xx_mmc_hwmod_class
= {
1296 .sysc
= &dra7xx_mmc_sysc
,
1300 static struct omap_hwmod_opt_clk mmc1_opt_clks
[] = {
1301 { .role
= "clk32k", .clk
= "mmc1_clk32k" },
1305 static struct omap_hsmmc_dev_attr mmc1_dev_attr
= {
1306 .flags
= OMAP_HSMMC_SUPPORTS_DUAL_VOLT
,
1309 static struct omap_hwmod dra7xx_mmc1_hwmod
= {
1311 .class = &dra7xx_mmc_hwmod_class
,
1312 .clkdm_name
= "l3init_clkdm",
1313 .main_clk
= "mmc1_fclk_div",
1316 .clkctrl_offs
= DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET
,
1317 .context_offs
= DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET
,
1318 .modulemode
= MODULEMODE_SWCTRL
,
1321 .opt_clks
= mmc1_opt_clks
,
1322 .opt_clks_cnt
= ARRAY_SIZE(mmc1_opt_clks
),
1323 .dev_attr
= &mmc1_dev_attr
,
1327 static struct omap_hwmod_opt_clk mmc2_opt_clks
[] = {
1328 { .role
= "clk32k", .clk
= "mmc2_clk32k" },
1331 static struct omap_hwmod dra7xx_mmc2_hwmod
= {
1333 .class = &dra7xx_mmc_hwmod_class
,
1334 .clkdm_name
= "l3init_clkdm",
1335 .main_clk
= "mmc2_fclk_div",
1338 .clkctrl_offs
= DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET
,
1339 .context_offs
= DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET
,
1340 .modulemode
= MODULEMODE_SWCTRL
,
1343 .opt_clks
= mmc2_opt_clks
,
1344 .opt_clks_cnt
= ARRAY_SIZE(mmc2_opt_clks
),
1348 static struct omap_hwmod_opt_clk mmc3_opt_clks
[] = {
1349 { .role
= "clk32k", .clk
= "mmc3_clk32k" },
1352 static struct omap_hwmod dra7xx_mmc3_hwmod
= {
1354 .class = &dra7xx_mmc_hwmod_class
,
1355 .clkdm_name
= "l4per_clkdm",
1356 .main_clk
= "mmc3_gfclk_div",
1359 .clkctrl_offs
= DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET
,
1360 .context_offs
= DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET
,
1361 .modulemode
= MODULEMODE_SWCTRL
,
1364 .opt_clks
= mmc3_opt_clks
,
1365 .opt_clks_cnt
= ARRAY_SIZE(mmc3_opt_clks
),
1369 static struct omap_hwmod_opt_clk mmc4_opt_clks
[] = {
1370 { .role
= "clk32k", .clk
= "mmc4_clk32k" },
1373 static struct omap_hwmod dra7xx_mmc4_hwmod
= {
1375 .class = &dra7xx_mmc_hwmod_class
,
1376 .clkdm_name
= "l4per_clkdm",
1377 .main_clk
= "mmc4_gfclk_div",
1380 .clkctrl_offs
= DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET
,
1381 .context_offs
= DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET
,
1382 .modulemode
= MODULEMODE_SWCTRL
,
1385 .opt_clks
= mmc4_opt_clks
,
1386 .opt_clks_cnt
= ARRAY_SIZE(mmc4_opt_clks
),
1394 static struct omap_hwmod_class dra7xx_mpu_hwmod_class
= {
1399 static struct omap_hwmod dra7xx_mpu_hwmod
= {
1401 .class = &dra7xx_mpu_hwmod_class
,
1402 .clkdm_name
= "mpu_clkdm",
1403 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
1404 .main_clk
= "dpll_mpu_m2_ck",
1407 .clkctrl_offs
= DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET
,
1408 .context_offs
= DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET
,
1418 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc
= {
1420 .sysc_offs
= 0x0010,
1421 .syss_offs
= 0x0014,
1422 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SIDLEMODE
|
1423 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1424 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1426 .sysc_fields
= &omap_hwmod_sysc_type1
,
1429 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class
= {
1431 .sysc
= &dra7xx_ocp2scp_sysc
,
1435 static struct omap_hwmod dra7xx_ocp2scp1_hwmod
= {
1437 .class = &dra7xx_ocp2scp_hwmod_class
,
1438 .clkdm_name
= "l3init_clkdm",
1439 .main_clk
= "l4_root_clk_div",
1442 .clkctrl_offs
= DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET
,
1443 .context_offs
= DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET
,
1444 .modulemode
= MODULEMODE_HWCTRL
,
1450 static struct omap_hwmod dra7xx_ocp2scp3_hwmod
= {
1452 .class = &dra7xx_ocp2scp_hwmod_class
,
1453 .clkdm_name
= "l3init_clkdm",
1454 .main_clk
= "l4_root_clk_div",
1457 .clkctrl_offs
= DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET
,
1458 .context_offs
= DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET
,
1459 .modulemode
= MODULEMODE_HWCTRL
,
1469 static struct omap_hwmod_class dra7xx_pciess_hwmod_class
= {
1474 static struct omap_hwmod dra7xx_pciess1_hwmod
= {
1476 .class = &dra7xx_pciess_hwmod_class
,
1477 .clkdm_name
= "pcie_clkdm",
1478 .main_clk
= "l4_root_clk_div",
1481 .clkctrl_offs
= DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET
,
1482 .context_offs
= DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET
,
1483 .modulemode
= MODULEMODE_SWCTRL
,
1489 static struct omap_hwmod dra7xx_pciess2_hwmod
= {
1491 .class = &dra7xx_pciess_hwmod_class
,
1492 .clkdm_name
= "pcie_clkdm",
1493 .main_clk
= "l4_root_clk_div",
1496 .clkctrl_offs
= DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET
,
1497 .context_offs
= DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET
,
1498 .modulemode
= MODULEMODE_SWCTRL
,
1508 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc
= {
1509 .sysc_offs
= 0x0010,
1510 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
1511 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1513 .sysc_fields
= &omap_hwmod_sysc_type2
,
1516 static struct omap_hwmod_class dra7xx_qspi_hwmod_class
= {
1518 .sysc
= &dra7xx_qspi_sysc
,
1522 static struct omap_hwmod dra7xx_qspi_hwmod
= {
1524 .class = &dra7xx_qspi_hwmod_class
,
1525 .clkdm_name
= "l4per2_clkdm",
1526 .main_clk
= "qspi_gfclk_div",
1529 .clkctrl_offs
= DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET
,
1530 .context_offs
= DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET
,
1531 .modulemode
= MODULEMODE_SWCTRL
,
1540 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc
= {
1541 .sysc_offs
= 0x0078,
1542 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
1543 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1545 .sysc_fields
= &omap_hwmod_sysc_type3
,
1548 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class
= {
1550 .sysc
= &dra7xx_rtcss_sysc
,
1554 static struct omap_hwmod dra7xx_rtcss_hwmod
= {
1556 .class = &dra7xx_rtcss_hwmod_class
,
1557 .clkdm_name
= "rtc_clkdm",
1558 .main_clk
= "sys_32k_ck",
1561 .clkctrl_offs
= DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET
,
1562 .context_offs
= DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET
,
1563 .modulemode
= MODULEMODE_SWCTRL
,
1573 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc
= {
1574 .sysc_offs
= 0x0000,
1575 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
),
1576 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1577 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1578 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1579 .sysc_fields
= &omap_hwmod_sysc_type2
,
1582 static struct omap_hwmod_class dra7xx_sata_hwmod_class
= {
1584 .sysc
= &dra7xx_sata_sysc
,
1589 static struct omap_hwmod dra7xx_sata_hwmod
= {
1591 .class = &dra7xx_sata_hwmod_class
,
1592 .clkdm_name
= "l3init_clkdm",
1593 .flags
= HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
,
1594 .main_clk
= "func_48m_fclk",
1598 .clkctrl_offs
= DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET
,
1599 .context_offs
= DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET
,
1600 .modulemode
= MODULEMODE_SWCTRL
,
1606 * 'smartreflex' class
1610 /* The IP is not compliant to type1 / type2 scheme */
1611 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex
= {
1616 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc
= {
1617 .sysc_offs
= 0x0038,
1618 .sysc_flags
= (SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
),
1619 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1621 .sysc_fields
= &omap_hwmod_sysc_type_smartreflex
,
1624 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class
= {
1625 .name
= "smartreflex",
1626 .sysc
= &dra7xx_smartreflex_sysc
,
1630 /* smartreflex_core */
1631 /* smartreflex_core dev_attr */
1632 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr
= {
1633 .sensor_voltdm_name
= "core",
1636 static struct omap_hwmod dra7xx_smartreflex_core_hwmod
= {
1637 .name
= "smartreflex_core",
1638 .class = &dra7xx_smartreflex_hwmod_class
,
1639 .clkdm_name
= "coreaon_clkdm",
1640 .main_clk
= "wkupaon_iclk_mux",
1643 .clkctrl_offs
= DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET
,
1644 .context_offs
= DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET
,
1645 .modulemode
= MODULEMODE_SWCTRL
,
1648 .dev_attr
= &smartreflex_core_dev_attr
,
1651 /* smartreflex_mpu */
1652 /* smartreflex_mpu dev_attr */
1653 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr
= {
1654 .sensor_voltdm_name
= "mpu",
1657 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod
= {
1658 .name
= "smartreflex_mpu",
1659 .class = &dra7xx_smartreflex_hwmod_class
,
1660 .clkdm_name
= "coreaon_clkdm",
1661 .main_clk
= "wkupaon_iclk_mux",
1664 .clkctrl_offs
= DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET
,
1665 .context_offs
= DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET
,
1666 .modulemode
= MODULEMODE_SWCTRL
,
1669 .dev_attr
= &smartreflex_mpu_dev_attr
,
1677 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc
= {
1679 .sysc_offs
= 0x0010,
1680 .syss_offs
= 0x0014,
1681 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
1682 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
1683 SYSS_HAS_RESET_STATUS
),
1684 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1685 .sysc_fields
= &omap_hwmod_sysc_type1
,
1688 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class
= {
1690 .sysc
= &dra7xx_spinlock_sysc
,
1694 static struct omap_hwmod dra7xx_spinlock_hwmod
= {
1696 .class = &dra7xx_spinlock_hwmod_class
,
1697 .clkdm_name
= "l4cfg_clkdm",
1698 .main_clk
= "l3_iclk_div",
1701 .clkctrl_offs
= DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET
,
1702 .context_offs
= DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET
,
1710 * This class contains several variants: ['timer_1ms', 'timer_secure',
1714 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc
= {
1716 .sysc_offs
= 0x0010,
1717 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
1718 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1719 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1721 .sysc_fields
= &omap_hwmod_sysc_type2
,
1724 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class
= {
1726 .sysc
= &dra7xx_timer_1ms_sysc
,
1729 static struct omap_hwmod_class_sysconfig dra7xx_timer_secure_sysc
= {
1731 .sysc_offs
= 0x0010,
1732 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
1733 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1734 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1736 .sysc_fields
= &omap_hwmod_sysc_type2
,
1739 static struct omap_hwmod_class dra7xx_timer_secure_hwmod_class
= {
1741 .sysc
= &dra7xx_timer_secure_sysc
,
1744 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc
= {
1746 .sysc_offs
= 0x0010,
1747 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
1748 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1749 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1751 .sysc_fields
= &omap_hwmod_sysc_type2
,
1754 static struct omap_hwmod_class dra7xx_timer_hwmod_class
= {
1756 .sysc
= &dra7xx_timer_sysc
,
1760 static struct omap_hwmod dra7xx_timer1_hwmod
= {
1762 .class = &dra7xx_timer_1ms_hwmod_class
,
1763 .clkdm_name
= "wkupaon_clkdm",
1764 .main_clk
= "timer1_gfclk_mux",
1767 .clkctrl_offs
= DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET
,
1768 .context_offs
= DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET
,
1769 .modulemode
= MODULEMODE_SWCTRL
,
1775 static struct omap_hwmod dra7xx_timer2_hwmod
= {
1777 .class = &dra7xx_timer_1ms_hwmod_class
,
1778 .clkdm_name
= "l4per_clkdm",
1779 .main_clk
= "timer2_gfclk_mux",
1782 .clkctrl_offs
= DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET
,
1783 .context_offs
= DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET
,
1784 .modulemode
= MODULEMODE_SWCTRL
,
1790 static struct omap_hwmod dra7xx_timer3_hwmod
= {
1792 .class = &dra7xx_timer_hwmod_class
,
1793 .clkdm_name
= "l4per_clkdm",
1794 .main_clk
= "timer3_gfclk_mux",
1797 .clkctrl_offs
= DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET
,
1798 .context_offs
= DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET
,
1799 .modulemode
= MODULEMODE_SWCTRL
,
1805 static struct omap_hwmod dra7xx_timer4_hwmod
= {
1807 .class = &dra7xx_timer_secure_hwmod_class
,
1808 .clkdm_name
= "l4per_clkdm",
1809 .main_clk
= "timer4_gfclk_mux",
1812 .clkctrl_offs
= DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET
,
1813 .context_offs
= DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET
,
1814 .modulemode
= MODULEMODE_SWCTRL
,
1820 static struct omap_hwmod dra7xx_timer5_hwmod
= {
1822 .class = &dra7xx_timer_hwmod_class
,
1823 .clkdm_name
= "ipu_clkdm",
1824 .main_clk
= "timer5_gfclk_mux",
1827 .clkctrl_offs
= DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET
,
1828 .context_offs
= DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET
,
1829 .modulemode
= MODULEMODE_SWCTRL
,
1835 static struct omap_hwmod dra7xx_timer6_hwmod
= {
1837 .class = &dra7xx_timer_hwmod_class
,
1838 .clkdm_name
= "ipu_clkdm",
1839 .main_clk
= "timer6_gfclk_mux",
1842 .clkctrl_offs
= DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET
,
1843 .context_offs
= DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET
,
1844 .modulemode
= MODULEMODE_SWCTRL
,
1850 static struct omap_hwmod dra7xx_timer7_hwmod
= {
1852 .class = &dra7xx_timer_hwmod_class
,
1853 .clkdm_name
= "ipu_clkdm",
1854 .main_clk
= "timer7_gfclk_mux",
1857 .clkctrl_offs
= DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET
,
1858 .context_offs
= DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET
,
1859 .modulemode
= MODULEMODE_SWCTRL
,
1865 static struct omap_hwmod dra7xx_timer8_hwmod
= {
1867 .class = &dra7xx_timer_hwmod_class
,
1868 .clkdm_name
= "ipu_clkdm",
1869 .main_clk
= "timer8_gfclk_mux",
1872 .clkctrl_offs
= DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET
,
1873 .context_offs
= DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET
,
1874 .modulemode
= MODULEMODE_SWCTRL
,
1880 static struct omap_hwmod dra7xx_timer9_hwmod
= {
1882 .class = &dra7xx_timer_hwmod_class
,
1883 .clkdm_name
= "l4per_clkdm",
1884 .main_clk
= "timer9_gfclk_mux",
1887 .clkctrl_offs
= DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET
,
1888 .context_offs
= DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET
,
1889 .modulemode
= MODULEMODE_SWCTRL
,
1895 static struct omap_hwmod dra7xx_timer10_hwmod
= {
1897 .class = &dra7xx_timer_1ms_hwmod_class
,
1898 .clkdm_name
= "l4per_clkdm",
1899 .main_clk
= "timer10_gfclk_mux",
1902 .clkctrl_offs
= DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET
,
1903 .context_offs
= DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET
,
1904 .modulemode
= MODULEMODE_SWCTRL
,
1910 static struct omap_hwmod dra7xx_timer11_hwmod
= {
1912 .class = &dra7xx_timer_hwmod_class
,
1913 .clkdm_name
= "l4per_clkdm",
1914 .main_clk
= "timer11_gfclk_mux",
1917 .clkctrl_offs
= DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET
,
1918 .context_offs
= DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET
,
1919 .modulemode
= MODULEMODE_SWCTRL
,
1929 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc
= {
1931 .sysc_offs
= 0x0054,
1932 .syss_offs
= 0x0058,
1933 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
1934 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
1935 SYSS_HAS_RESET_STATUS
),
1936 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1938 .sysc_fields
= &omap_hwmod_sysc_type1
,
1941 static struct omap_hwmod_class dra7xx_uart_hwmod_class
= {
1943 .sysc
= &dra7xx_uart_sysc
,
1947 static struct omap_hwmod dra7xx_uart1_hwmod
= {
1949 .class = &dra7xx_uart_hwmod_class
,
1950 .clkdm_name
= "l4per_clkdm",
1951 .main_clk
= "uart1_gfclk_mux",
1952 .flags
= HWMOD_SWSUP_SIDLE_ACT
| DEBUG_OMAP2UART1_FLAGS
,
1955 .clkctrl_offs
= DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET
,
1956 .context_offs
= DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET
,
1957 .modulemode
= MODULEMODE_SWCTRL
,
1963 static struct omap_hwmod dra7xx_uart2_hwmod
= {
1965 .class = &dra7xx_uart_hwmod_class
,
1966 .clkdm_name
= "l4per_clkdm",
1967 .main_clk
= "uart2_gfclk_mux",
1968 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
1971 .clkctrl_offs
= DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET
,
1972 .context_offs
= DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET
,
1973 .modulemode
= MODULEMODE_SWCTRL
,
1979 static struct omap_hwmod dra7xx_uart3_hwmod
= {
1981 .class = &dra7xx_uart_hwmod_class
,
1982 .clkdm_name
= "l4per_clkdm",
1983 .main_clk
= "uart3_gfclk_mux",
1984 .flags
= HWMOD_SWSUP_SIDLE_ACT
| DEBUG_OMAP4UART3_FLAGS
,
1987 .clkctrl_offs
= DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET
,
1988 .context_offs
= DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET
,
1989 .modulemode
= MODULEMODE_SWCTRL
,
1995 static struct omap_hwmod dra7xx_uart4_hwmod
= {
1997 .class = &dra7xx_uart_hwmod_class
,
1998 .clkdm_name
= "l4per_clkdm",
1999 .main_clk
= "uart4_gfclk_mux",
2000 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
2003 .clkctrl_offs
= DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET
,
2004 .context_offs
= DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET
,
2005 .modulemode
= MODULEMODE_SWCTRL
,
2011 static struct omap_hwmod dra7xx_uart5_hwmod
= {
2013 .class = &dra7xx_uart_hwmod_class
,
2014 .clkdm_name
= "l4per_clkdm",
2015 .main_clk
= "uart5_gfclk_mux",
2016 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
2019 .clkctrl_offs
= DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET
,
2020 .context_offs
= DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET
,
2021 .modulemode
= MODULEMODE_SWCTRL
,
2027 static struct omap_hwmod dra7xx_uart6_hwmod
= {
2029 .class = &dra7xx_uart_hwmod_class
,
2030 .clkdm_name
= "ipu_clkdm",
2031 .main_clk
= "uart6_gfclk_mux",
2032 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
2035 .clkctrl_offs
= DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET
,
2036 .context_offs
= DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET
,
2037 .modulemode
= MODULEMODE_SWCTRL
,
2043 static struct omap_hwmod dra7xx_uart7_hwmod
= {
2045 .class = &dra7xx_uart_hwmod_class
,
2046 .clkdm_name
= "l4per2_clkdm",
2047 .main_clk
= "uart7_gfclk_mux",
2048 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
2051 .clkctrl_offs
= DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET
,
2052 .context_offs
= DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET
,
2053 .modulemode
= MODULEMODE_SWCTRL
,
2059 static struct omap_hwmod dra7xx_uart8_hwmod
= {
2061 .class = &dra7xx_uart_hwmod_class
,
2062 .clkdm_name
= "l4per2_clkdm",
2063 .main_clk
= "uart8_gfclk_mux",
2064 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
2067 .clkctrl_offs
= DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET
,
2068 .context_offs
= DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET
,
2069 .modulemode
= MODULEMODE_SWCTRL
,
2075 static struct omap_hwmod dra7xx_uart9_hwmod
= {
2077 .class = &dra7xx_uart_hwmod_class
,
2078 .clkdm_name
= "l4per2_clkdm",
2079 .main_clk
= "uart9_gfclk_mux",
2080 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
2083 .clkctrl_offs
= DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET
,
2084 .context_offs
= DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET
,
2085 .modulemode
= MODULEMODE_SWCTRL
,
2091 static struct omap_hwmod dra7xx_uart10_hwmod
= {
2093 .class = &dra7xx_uart_hwmod_class
,
2094 .clkdm_name
= "wkupaon_clkdm",
2095 .main_clk
= "uart10_gfclk_mux",
2096 .flags
= HWMOD_SWSUP_SIDLE_ACT
,
2099 .clkctrl_offs
= DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET
,
2100 .context_offs
= DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET
,
2101 .modulemode
= MODULEMODE_SWCTRL
,
2107 * 'usb_otg_ss' class
2111 static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc
= {
2113 .sysc_offs
= 0x0010,
2114 .sysc_flags
= (SYSC_HAS_DMADISABLE
| SYSC_HAS_MIDLEMODE
|
2115 SYSC_HAS_SIDLEMODE
),
2116 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2117 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
2118 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
2119 .sysc_fields
= &omap_hwmod_sysc_type2
,
2122 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class
= {
2123 .name
= "usb_otg_ss",
2124 .sysc
= &dra7xx_usb_otg_ss_sysc
,
2128 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks
[] = {
2129 { .role
= "refclk960m", .clk
= "usb_otg_ss1_refclk960m" },
2132 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod
= {
2133 .name
= "usb_otg_ss1",
2134 .class = &dra7xx_usb_otg_ss_hwmod_class
,
2135 .clkdm_name
= "l3init_clkdm",
2136 .main_clk
= "dpll_core_h13x2_ck",
2139 .clkctrl_offs
= DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET
,
2140 .context_offs
= DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET
,
2141 .modulemode
= MODULEMODE_HWCTRL
,
2144 .opt_clks
= usb_otg_ss1_opt_clks
,
2145 .opt_clks_cnt
= ARRAY_SIZE(usb_otg_ss1_opt_clks
),
2149 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks
[] = {
2150 { .role
= "refclk960m", .clk
= "usb_otg_ss2_refclk960m" },
2153 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod
= {
2154 .name
= "usb_otg_ss2",
2155 .class = &dra7xx_usb_otg_ss_hwmod_class
,
2156 .clkdm_name
= "l3init_clkdm",
2157 .main_clk
= "dpll_core_h13x2_ck",
2160 .clkctrl_offs
= DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET
,
2161 .context_offs
= DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET
,
2162 .modulemode
= MODULEMODE_HWCTRL
,
2165 .opt_clks
= usb_otg_ss2_opt_clks
,
2166 .opt_clks_cnt
= ARRAY_SIZE(usb_otg_ss2_opt_clks
),
2170 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod
= {
2171 .name
= "usb_otg_ss3",
2172 .class = &dra7xx_usb_otg_ss_hwmod_class
,
2173 .clkdm_name
= "l3init_clkdm",
2174 .main_clk
= "dpll_core_h13x2_ck",
2177 .clkctrl_offs
= DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET
,
2178 .context_offs
= DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET
,
2179 .modulemode
= MODULEMODE_HWCTRL
,
2185 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod
= {
2186 .name
= "usb_otg_ss4",
2187 .class = &dra7xx_usb_otg_ss_hwmod_class
,
2188 .clkdm_name
= "l3init_clkdm",
2189 .main_clk
= "dpll_core_h13x2_ck",
2192 .clkctrl_offs
= DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET
,
2193 .context_offs
= DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET
,
2194 .modulemode
= MODULEMODE_HWCTRL
,
2204 static struct omap_hwmod_class dra7xx_vcp_hwmod_class
= {
2209 static struct omap_hwmod dra7xx_vcp1_hwmod
= {
2211 .class = &dra7xx_vcp_hwmod_class
,
2212 .clkdm_name
= "l3main1_clkdm",
2213 .main_clk
= "l3_iclk_div",
2216 .clkctrl_offs
= DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET
,
2217 .context_offs
= DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET
,
2223 static struct omap_hwmod dra7xx_vcp2_hwmod
= {
2225 .class = &dra7xx_vcp_hwmod_class
,
2226 .clkdm_name
= "l3main1_clkdm",
2227 .main_clk
= "l3_iclk_div",
2230 .clkctrl_offs
= DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET
,
2231 .context_offs
= DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET
,
2241 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc
= {
2243 .sysc_offs
= 0x0010,
2244 .syss_offs
= 0x0014,
2245 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_SIDLEMODE
|
2246 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
2247 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2249 .sysc_fields
= &omap_hwmod_sysc_type1
,
2252 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class
= {
2254 .sysc
= &dra7xx_wd_timer_sysc
,
2255 .pre_shutdown
= &omap2_wd_timer_disable
,
2256 .reset
= &omap2_wd_timer_reset
,
2260 static struct omap_hwmod dra7xx_wd_timer2_hwmod
= {
2261 .name
= "wd_timer2",
2262 .class = &dra7xx_wd_timer_hwmod_class
,
2263 .clkdm_name
= "wkupaon_clkdm",
2264 .main_clk
= "sys_32k_ck",
2267 .clkctrl_offs
= DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET
,
2268 .context_offs
= DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET
,
2269 .modulemode
= MODULEMODE_SWCTRL
,
2279 /* l3_main_2 -> l3_instr */
2280 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr
= {
2281 .master
= &dra7xx_l3_main_2_hwmod
,
2282 .slave
= &dra7xx_l3_instr_hwmod
,
2283 .clk
= "l3_iclk_div",
2284 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2287 /* l4_cfg -> l3_main_1 */
2288 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1
= {
2289 .master
= &dra7xx_l4_cfg_hwmod
,
2290 .slave
= &dra7xx_l3_main_1_hwmod
,
2291 .clk
= "l3_iclk_div",
2292 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2295 /* mpu -> l3_main_1 */
2296 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1
= {
2297 .master
= &dra7xx_mpu_hwmod
,
2298 .slave
= &dra7xx_l3_main_1_hwmod
,
2299 .clk
= "l3_iclk_div",
2300 .user
= OCP_USER_MPU
,
2303 /* l3_main_1 -> l3_main_2 */
2304 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2
= {
2305 .master
= &dra7xx_l3_main_1_hwmod
,
2306 .slave
= &dra7xx_l3_main_2_hwmod
,
2307 .clk
= "l3_iclk_div",
2308 .user
= OCP_USER_MPU
,
2311 /* l4_cfg -> l3_main_2 */
2312 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2
= {
2313 .master
= &dra7xx_l4_cfg_hwmod
,
2314 .slave
= &dra7xx_l3_main_2_hwmod
,
2315 .clk
= "l3_iclk_div",
2316 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2319 /* l3_main_1 -> l4_cfg */
2320 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg
= {
2321 .master
= &dra7xx_l3_main_1_hwmod
,
2322 .slave
= &dra7xx_l4_cfg_hwmod
,
2323 .clk
= "l3_iclk_div",
2324 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2327 /* l3_main_1 -> l4_per1 */
2328 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1
= {
2329 .master
= &dra7xx_l3_main_1_hwmod
,
2330 .slave
= &dra7xx_l4_per1_hwmod
,
2331 .clk
= "l3_iclk_div",
2332 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2335 /* l3_main_1 -> l4_per2 */
2336 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2
= {
2337 .master
= &dra7xx_l3_main_1_hwmod
,
2338 .slave
= &dra7xx_l4_per2_hwmod
,
2339 .clk
= "l3_iclk_div",
2340 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2343 /* l3_main_1 -> l4_per3 */
2344 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3
= {
2345 .master
= &dra7xx_l3_main_1_hwmod
,
2346 .slave
= &dra7xx_l4_per3_hwmod
,
2347 .clk
= "l3_iclk_div",
2348 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2351 /* l3_main_1 -> l4_wkup */
2352 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup
= {
2353 .master
= &dra7xx_l3_main_1_hwmod
,
2354 .slave
= &dra7xx_l4_wkup_hwmod
,
2355 .clk
= "wkupaon_iclk_mux",
2356 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2359 /* l4_per2 -> atl */
2360 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl
= {
2361 .master
= &dra7xx_l4_per2_hwmod
,
2362 .slave
= &dra7xx_atl_hwmod
,
2363 .clk
= "l3_iclk_div",
2364 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2367 /* l3_main_1 -> bb2d */
2368 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d
= {
2369 .master
= &dra7xx_l3_main_1_hwmod
,
2370 .slave
= &dra7xx_bb2d_hwmod
,
2371 .clk
= "l3_iclk_div",
2372 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2375 /* l4_wkup -> counter_32k */
2376 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k
= {
2377 .master
= &dra7xx_l4_wkup_hwmod
,
2378 .slave
= &dra7xx_counter_32k_hwmod
,
2379 .clk
= "wkupaon_iclk_mux",
2380 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2383 /* l4_wkup -> ctrl_module_wkup */
2384 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup
= {
2385 .master
= &dra7xx_l4_wkup_hwmod
,
2386 .slave
= &dra7xx_ctrl_module_wkup_hwmod
,
2387 .clk
= "wkupaon_iclk_mux",
2388 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2391 static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0
= {
2392 .master
= &dra7xx_l4_per2_hwmod
,
2393 .slave
= &dra7xx_gmac_hwmod
,
2394 .clk
= "dpll_gmac_ck",
2395 .user
= OCP_USER_MPU
,
2398 static struct omap_hwmod_ocp_if dra7xx_gmac__mdio
= {
2399 .master
= &dra7xx_gmac_hwmod
,
2400 .slave
= &dra7xx_mdio_hwmod
,
2401 .user
= OCP_USER_MPU
,
2404 /* l4_wkup -> dcan1 */
2405 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1
= {
2406 .master
= &dra7xx_l4_wkup_hwmod
,
2407 .slave
= &dra7xx_dcan1_hwmod
,
2408 .clk
= "wkupaon_iclk_mux",
2409 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2412 /* l4_per2 -> dcan2 */
2413 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2
= {
2414 .master
= &dra7xx_l4_per2_hwmod
,
2415 .slave
= &dra7xx_dcan2_hwmod
,
2416 .clk
= "l3_iclk_div",
2417 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2420 static struct omap_hwmod_addr_space dra7xx_dma_system_addrs
[] = {
2422 .pa_start
= 0x4a056000,
2423 .pa_end
= 0x4a056fff,
2424 .flags
= ADDR_TYPE_RT
2429 /* l4_cfg -> dma_system */
2430 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system
= {
2431 .master
= &dra7xx_l4_cfg_hwmod
,
2432 .slave
= &dra7xx_dma_system_hwmod
,
2433 .clk
= "l3_iclk_div",
2434 .addr
= dra7xx_dma_system_addrs
,
2435 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2438 static struct omap_hwmod_addr_space dra7xx_dss_addrs
[] = {
2441 .pa_start
= 0x58000000,
2442 .pa_end
= 0x5800007f,
2443 .flags
= ADDR_TYPE_RT
2447 /* l3_main_1 -> dss */
2448 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss
= {
2449 .master
= &dra7xx_l3_main_1_hwmod
,
2450 .slave
= &dra7xx_dss_hwmod
,
2451 .clk
= "l3_iclk_div",
2452 .addr
= dra7xx_dss_addrs
,
2453 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2456 static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs
[] = {
2459 .pa_start
= 0x58001000,
2460 .pa_end
= 0x58001fff,
2461 .flags
= ADDR_TYPE_RT
2465 /* l3_main_1 -> dispc */
2466 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc
= {
2467 .master
= &dra7xx_l3_main_1_hwmod
,
2468 .slave
= &dra7xx_dss_dispc_hwmod
,
2469 .clk
= "l3_iclk_div",
2470 .addr
= dra7xx_dss_dispc_addrs
,
2471 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2474 static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs
[] = {
2477 .pa_start
= 0x58040000,
2478 .pa_end
= 0x580400ff,
2479 .flags
= ADDR_TYPE_RT
2484 /* l3_main_1 -> dispc */
2485 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi
= {
2486 .master
= &dra7xx_l3_main_1_hwmod
,
2487 .slave
= &dra7xx_dss_hdmi_hwmod
,
2488 .clk
= "l3_iclk_div",
2489 .addr
= dra7xx_dss_hdmi_addrs
,
2490 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2493 static struct omap_hwmod_addr_space dra7xx_elm_addrs
[] = {
2495 .pa_start
= 0x48078000,
2496 .pa_end
= 0x48078fff,
2497 .flags
= ADDR_TYPE_RT
2502 /* l4_per1 -> elm */
2503 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm
= {
2504 .master
= &dra7xx_l4_per1_hwmod
,
2505 .slave
= &dra7xx_elm_hwmod
,
2506 .clk
= "l3_iclk_div",
2507 .addr
= dra7xx_elm_addrs
,
2508 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2511 /* l4_wkup -> gpio1 */
2512 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1
= {
2513 .master
= &dra7xx_l4_wkup_hwmod
,
2514 .slave
= &dra7xx_gpio1_hwmod
,
2515 .clk
= "wkupaon_iclk_mux",
2516 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2519 /* l4_per1 -> gpio2 */
2520 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2
= {
2521 .master
= &dra7xx_l4_per1_hwmod
,
2522 .slave
= &dra7xx_gpio2_hwmod
,
2523 .clk
= "l3_iclk_div",
2524 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2527 /* l4_per1 -> gpio3 */
2528 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3
= {
2529 .master
= &dra7xx_l4_per1_hwmod
,
2530 .slave
= &dra7xx_gpio3_hwmod
,
2531 .clk
= "l3_iclk_div",
2532 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2535 /* l4_per1 -> gpio4 */
2536 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4
= {
2537 .master
= &dra7xx_l4_per1_hwmod
,
2538 .slave
= &dra7xx_gpio4_hwmod
,
2539 .clk
= "l3_iclk_div",
2540 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2543 /* l4_per1 -> gpio5 */
2544 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5
= {
2545 .master
= &dra7xx_l4_per1_hwmod
,
2546 .slave
= &dra7xx_gpio5_hwmod
,
2547 .clk
= "l3_iclk_div",
2548 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2551 /* l4_per1 -> gpio6 */
2552 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6
= {
2553 .master
= &dra7xx_l4_per1_hwmod
,
2554 .slave
= &dra7xx_gpio6_hwmod
,
2555 .clk
= "l3_iclk_div",
2556 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2559 /* l4_per1 -> gpio7 */
2560 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7
= {
2561 .master
= &dra7xx_l4_per1_hwmod
,
2562 .slave
= &dra7xx_gpio7_hwmod
,
2563 .clk
= "l3_iclk_div",
2564 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2567 /* l4_per1 -> gpio8 */
2568 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8
= {
2569 .master
= &dra7xx_l4_per1_hwmod
,
2570 .slave
= &dra7xx_gpio8_hwmod
,
2571 .clk
= "l3_iclk_div",
2572 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2575 static struct omap_hwmod_addr_space dra7xx_gpmc_addrs
[] = {
2577 .pa_start
= 0x50000000,
2578 .pa_end
= 0x500003ff,
2579 .flags
= ADDR_TYPE_RT
2584 /* l3_main_1 -> gpmc */
2585 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc
= {
2586 .master
= &dra7xx_l3_main_1_hwmod
,
2587 .slave
= &dra7xx_gpmc_hwmod
,
2588 .clk
= "l3_iclk_div",
2589 .addr
= dra7xx_gpmc_addrs
,
2590 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2593 static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs
[] = {
2595 .pa_start
= 0x480b2000,
2596 .pa_end
= 0x480b201f,
2597 .flags
= ADDR_TYPE_RT
2602 /* l4_per1 -> hdq1w */
2603 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w
= {
2604 .master
= &dra7xx_l4_per1_hwmod
,
2605 .slave
= &dra7xx_hdq1w_hwmod
,
2606 .clk
= "l3_iclk_div",
2607 .addr
= dra7xx_hdq1w_addrs
,
2608 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2611 /* l4_per1 -> i2c1 */
2612 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1
= {
2613 .master
= &dra7xx_l4_per1_hwmod
,
2614 .slave
= &dra7xx_i2c1_hwmod
,
2615 .clk
= "l3_iclk_div",
2616 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2619 /* l4_per1 -> i2c2 */
2620 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2
= {
2621 .master
= &dra7xx_l4_per1_hwmod
,
2622 .slave
= &dra7xx_i2c2_hwmod
,
2623 .clk
= "l3_iclk_div",
2624 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2627 /* l4_per1 -> i2c3 */
2628 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3
= {
2629 .master
= &dra7xx_l4_per1_hwmod
,
2630 .slave
= &dra7xx_i2c3_hwmod
,
2631 .clk
= "l3_iclk_div",
2632 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2635 /* l4_per1 -> i2c4 */
2636 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4
= {
2637 .master
= &dra7xx_l4_per1_hwmod
,
2638 .slave
= &dra7xx_i2c4_hwmod
,
2639 .clk
= "l3_iclk_div",
2640 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2643 /* l4_per1 -> i2c5 */
2644 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5
= {
2645 .master
= &dra7xx_l4_per1_hwmod
,
2646 .slave
= &dra7xx_i2c5_hwmod
,
2647 .clk
= "l3_iclk_div",
2648 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2651 /* l4_cfg -> mailbox1 */
2652 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1
= {
2653 .master
= &dra7xx_l4_cfg_hwmod
,
2654 .slave
= &dra7xx_mailbox1_hwmod
,
2655 .clk
= "l3_iclk_div",
2656 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2659 /* l4_per3 -> mailbox2 */
2660 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2
= {
2661 .master
= &dra7xx_l4_per3_hwmod
,
2662 .slave
= &dra7xx_mailbox2_hwmod
,
2663 .clk
= "l3_iclk_div",
2664 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2667 /* l4_per3 -> mailbox3 */
2668 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3
= {
2669 .master
= &dra7xx_l4_per3_hwmod
,
2670 .slave
= &dra7xx_mailbox3_hwmod
,
2671 .clk
= "l3_iclk_div",
2672 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2675 /* l4_per3 -> mailbox4 */
2676 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4
= {
2677 .master
= &dra7xx_l4_per3_hwmod
,
2678 .slave
= &dra7xx_mailbox4_hwmod
,
2679 .clk
= "l3_iclk_div",
2680 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2683 /* l4_per3 -> mailbox5 */
2684 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5
= {
2685 .master
= &dra7xx_l4_per3_hwmod
,
2686 .slave
= &dra7xx_mailbox5_hwmod
,
2687 .clk
= "l3_iclk_div",
2688 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2691 /* l4_per3 -> mailbox6 */
2692 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6
= {
2693 .master
= &dra7xx_l4_per3_hwmod
,
2694 .slave
= &dra7xx_mailbox6_hwmod
,
2695 .clk
= "l3_iclk_div",
2696 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2699 /* l4_per3 -> mailbox7 */
2700 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7
= {
2701 .master
= &dra7xx_l4_per3_hwmod
,
2702 .slave
= &dra7xx_mailbox7_hwmod
,
2703 .clk
= "l3_iclk_div",
2704 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2707 /* l4_per3 -> mailbox8 */
2708 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8
= {
2709 .master
= &dra7xx_l4_per3_hwmod
,
2710 .slave
= &dra7xx_mailbox8_hwmod
,
2711 .clk
= "l3_iclk_div",
2712 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2715 /* l4_per3 -> mailbox9 */
2716 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9
= {
2717 .master
= &dra7xx_l4_per3_hwmod
,
2718 .slave
= &dra7xx_mailbox9_hwmod
,
2719 .clk
= "l3_iclk_div",
2720 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2723 /* l4_per3 -> mailbox10 */
2724 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10
= {
2725 .master
= &dra7xx_l4_per3_hwmod
,
2726 .slave
= &dra7xx_mailbox10_hwmod
,
2727 .clk
= "l3_iclk_div",
2728 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2731 /* l4_per3 -> mailbox11 */
2732 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11
= {
2733 .master
= &dra7xx_l4_per3_hwmod
,
2734 .slave
= &dra7xx_mailbox11_hwmod
,
2735 .clk
= "l3_iclk_div",
2736 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2739 /* l4_per3 -> mailbox12 */
2740 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12
= {
2741 .master
= &dra7xx_l4_per3_hwmod
,
2742 .slave
= &dra7xx_mailbox12_hwmod
,
2743 .clk
= "l3_iclk_div",
2744 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2747 /* l4_per3 -> mailbox13 */
2748 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13
= {
2749 .master
= &dra7xx_l4_per3_hwmod
,
2750 .slave
= &dra7xx_mailbox13_hwmod
,
2751 .clk
= "l3_iclk_div",
2752 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2755 /* l4_per1 -> mcspi1 */
2756 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1
= {
2757 .master
= &dra7xx_l4_per1_hwmod
,
2758 .slave
= &dra7xx_mcspi1_hwmod
,
2759 .clk
= "l3_iclk_div",
2760 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2763 /* l4_per1 -> mcspi2 */
2764 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2
= {
2765 .master
= &dra7xx_l4_per1_hwmod
,
2766 .slave
= &dra7xx_mcspi2_hwmod
,
2767 .clk
= "l3_iclk_div",
2768 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2771 /* l4_per1 -> mcspi3 */
2772 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3
= {
2773 .master
= &dra7xx_l4_per1_hwmod
,
2774 .slave
= &dra7xx_mcspi3_hwmod
,
2775 .clk
= "l3_iclk_div",
2776 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2779 /* l4_per1 -> mcspi4 */
2780 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4
= {
2781 .master
= &dra7xx_l4_per1_hwmod
,
2782 .slave
= &dra7xx_mcspi4_hwmod
,
2783 .clk
= "l3_iclk_div",
2784 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2787 /* l4_per1 -> mmc1 */
2788 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1
= {
2789 .master
= &dra7xx_l4_per1_hwmod
,
2790 .slave
= &dra7xx_mmc1_hwmod
,
2791 .clk
= "l3_iclk_div",
2792 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2795 /* l4_per1 -> mmc2 */
2796 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2
= {
2797 .master
= &dra7xx_l4_per1_hwmod
,
2798 .slave
= &dra7xx_mmc2_hwmod
,
2799 .clk
= "l3_iclk_div",
2800 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2803 /* l4_per1 -> mmc3 */
2804 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3
= {
2805 .master
= &dra7xx_l4_per1_hwmod
,
2806 .slave
= &dra7xx_mmc3_hwmod
,
2807 .clk
= "l3_iclk_div",
2808 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2811 /* l4_per1 -> mmc4 */
2812 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4
= {
2813 .master
= &dra7xx_l4_per1_hwmod
,
2814 .slave
= &dra7xx_mmc4_hwmod
,
2815 .clk
= "l3_iclk_div",
2816 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2820 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu
= {
2821 .master
= &dra7xx_l4_cfg_hwmod
,
2822 .slave
= &dra7xx_mpu_hwmod
,
2823 .clk
= "l3_iclk_div",
2824 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2827 /* l4_cfg -> ocp2scp1 */
2828 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1
= {
2829 .master
= &dra7xx_l4_cfg_hwmod
,
2830 .slave
= &dra7xx_ocp2scp1_hwmod
,
2831 .clk
= "l4_root_clk_div",
2832 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2835 /* l4_cfg -> ocp2scp3 */
2836 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3
= {
2837 .master
= &dra7xx_l4_cfg_hwmod
,
2838 .slave
= &dra7xx_ocp2scp3_hwmod
,
2839 .clk
= "l4_root_clk_div",
2840 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2843 /* l3_main_1 -> pciess1 */
2844 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1
= {
2845 .master
= &dra7xx_l3_main_1_hwmod
,
2846 .slave
= &dra7xx_pciess1_hwmod
,
2847 .clk
= "l3_iclk_div",
2848 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2851 /* l4_cfg -> pciess1 */
2852 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1
= {
2853 .master
= &dra7xx_l4_cfg_hwmod
,
2854 .slave
= &dra7xx_pciess1_hwmod
,
2855 .clk
= "l4_root_clk_div",
2856 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2859 /* l3_main_1 -> pciess2 */
2860 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2
= {
2861 .master
= &dra7xx_l3_main_1_hwmod
,
2862 .slave
= &dra7xx_pciess2_hwmod
,
2863 .clk
= "l3_iclk_div",
2864 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2867 /* l4_cfg -> pciess2 */
2868 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2
= {
2869 .master
= &dra7xx_l4_cfg_hwmod
,
2870 .slave
= &dra7xx_pciess2_hwmod
,
2871 .clk
= "l4_root_clk_div",
2872 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2875 static struct omap_hwmod_addr_space dra7xx_qspi_addrs
[] = {
2877 .pa_start
= 0x4b300000,
2878 .pa_end
= 0x4b30007f,
2879 .flags
= ADDR_TYPE_RT
2884 /* l3_main_1 -> qspi */
2885 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi
= {
2886 .master
= &dra7xx_l3_main_1_hwmod
,
2887 .slave
= &dra7xx_qspi_hwmod
,
2888 .clk
= "l3_iclk_div",
2889 .addr
= dra7xx_qspi_addrs
,
2890 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2893 /* l4_per3 -> rtcss */
2894 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss
= {
2895 .master
= &dra7xx_l4_per3_hwmod
,
2896 .slave
= &dra7xx_rtcss_hwmod
,
2897 .clk
= "l4_root_clk_div",
2898 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2901 static struct omap_hwmod_addr_space dra7xx_sata_addrs
[] = {
2904 .pa_start
= 0x4a141100,
2905 .pa_end
= 0x4a141107,
2906 .flags
= ADDR_TYPE_RT
2911 /* l4_cfg -> sata */
2912 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata
= {
2913 .master
= &dra7xx_l4_cfg_hwmod
,
2914 .slave
= &dra7xx_sata_hwmod
,
2915 .clk
= "l3_iclk_div",
2916 .addr
= dra7xx_sata_addrs
,
2917 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2920 static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs
[] = {
2922 .pa_start
= 0x4a0dd000,
2923 .pa_end
= 0x4a0dd07f,
2924 .flags
= ADDR_TYPE_RT
2929 /* l4_cfg -> smartreflex_core */
2930 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core
= {
2931 .master
= &dra7xx_l4_cfg_hwmod
,
2932 .slave
= &dra7xx_smartreflex_core_hwmod
,
2933 .clk
= "l4_root_clk_div",
2934 .addr
= dra7xx_smartreflex_core_addrs
,
2935 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2938 static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs
[] = {
2940 .pa_start
= 0x4a0d9000,
2941 .pa_end
= 0x4a0d907f,
2942 .flags
= ADDR_TYPE_RT
2947 /* l4_cfg -> smartreflex_mpu */
2948 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu
= {
2949 .master
= &dra7xx_l4_cfg_hwmod
,
2950 .slave
= &dra7xx_smartreflex_mpu_hwmod
,
2951 .clk
= "l4_root_clk_div",
2952 .addr
= dra7xx_smartreflex_mpu_addrs
,
2953 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2956 static struct omap_hwmod_addr_space dra7xx_spinlock_addrs
[] = {
2958 .pa_start
= 0x4a0f6000,
2959 .pa_end
= 0x4a0f6fff,
2960 .flags
= ADDR_TYPE_RT
2965 /* l4_cfg -> spinlock */
2966 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock
= {
2967 .master
= &dra7xx_l4_cfg_hwmod
,
2968 .slave
= &dra7xx_spinlock_hwmod
,
2969 .clk
= "l3_iclk_div",
2970 .addr
= dra7xx_spinlock_addrs
,
2971 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2974 /* l4_wkup -> timer1 */
2975 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1
= {
2976 .master
= &dra7xx_l4_wkup_hwmod
,
2977 .slave
= &dra7xx_timer1_hwmod
,
2978 .clk
= "wkupaon_iclk_mux",
2979 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2982 /* l4_per1 -> timer2 */
2983 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2
= {
2984 .master
= &dra7xx_l4_per1_hwmod
,
2985 .slave
= &dra7xx_timer2_hwmod
,
2986 .clk
= "l3_iclk_div",
2987 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2990 /* l4_per1 -> timer3 */
2991 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3
= {
2992 .master
= &dra7xx_l4_per1_hwmod
,
2993 .slave
= &dra7xx_timer3_hwmod
,
2994 .clk
= "l3_iclk_div",
2995 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2998 /* l4_per1 -> timer4 */
2999 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4
= {
3000 .master
= &dra7xx_l4_per1_hwmod
,
3001 .slave
= &dra7xx_timer4_hwmod
,
3002 .clk
= "l3_iclk_div",
3003 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3006 /* l4_per3 -> timer5 */
3007 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5
= {
3008 .master
= &dra7xx_l4_per3_hwmod
,
3009 .slave
= &dra7xx_timer5_hwmod
,
3010 .clk
= "l3_iclk_div",
3011 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3014 /* l4_per3 -> timer6 */
3015 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6
= {
3016 .master
= &dra7xx_l4_per3_hwmod
,
3017 .slave
= &dra7xx_timer6_hwmod
,
3018 .clk
= "l3_iclk_div",
3019 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3022 /* l4_per3 -> timer7 */
3023 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7
= {
3024 .master
= &dra7xx_l4_per3_hwmod
,
3025 .slave
= &dra7xx_timer7_hwmod
,
3026 .clk
= "l3_iclk_div",
3027 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3030 /* l4_per3 -> timer8 */
3031 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8
= {
3032 .master
= &dra7xx_l4_per3_hwmod
,
3033 .slave
= &dra7xx_timer8_hwmod
,
3034 .clk
= "l3_iclk_div",
3035 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3038 /* l4_per1 -> timer9 */
3039 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9
= {
3040 .master
= &dra7xx_l4_per1_hwmod
,
3041 .slave
= &dra7xx_timer9_hwmod
,
3042 .clk
= "l3_iclk_div",
3043 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3046 /* l4_per1 -> timer10 */
3047 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10
= {
3048 .master
= &dra7xx_l4_per1_hwmod
,
3049 .slave
= &dra7xx_timer10_hwmod
,
3050 .clk
= "l3_iclk_div",
3051 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3054 /* l4_per1 -> timer11 */
3055 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11
= {
3056 .master
= &dra7xx_l4_per1_hwmod
,
3057 .slave
= &dra7xx_timer11_hwmod
,
3058 .clk
= "l3_iclk_div",
3059 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3062 /* l4_per1 -> uart1 */
3063 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1
= {
3064 .master
= &dra7xx_l4_per1_hwmod
,
3065 .slave
= &dra7xx_uart1_hwmod
,
3066 .clk
= "l3_iclk_div",
3067 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3070 /* l4_per1 -> uart2 */
3071 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2
= {
3072 .master
= &dra7xx_l4_per1_hwmod
,
3073 .slave
= &dra7xx_uart2_hwmod
,
3074 .clk
= "l3_iclk_div",
3075 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3078 /* l4_per1 -> uart3 */
3079 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3
= {
3080 .master
= &dra7xx_l4_per1_hwmod
,
3081 .slave
= &dra7xx_uart3_hwmod
,
3082 .clk
= "l3_iclk_div",
3083 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3086 /* l4_per1 -> uart4 */
3087 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4
= {
3088 .master
= &dra7xx_l4_per1_hwmod
,
3089 .slave
= &dra7xx_uart4_hwmod
,
3090 .clk
= "l3_iclk_div",
3091 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3094 /* l4_per1 -> uart5 */
3095 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5
= {
3096 .master
= &dra7xx_l4_per1_hwmod
,
3097 .slave
= &dra7xx_uart5_hwmod
,
3098 .clk
= "l3_iclk_div",
3099 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3102 /* l4_per1 -> uart6 */
3103 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6
= {
3104 .master
= &dra7xx_l4_per1_hwmod
,
3105 .slave
= &dra7xx_uart6_hwmod
,
3106 .clk
= "l3_iclk_div",
3107 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3110 /* l4_per2 -> uart7 */
3111 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7
= {
3112 .master
= &dra7xx_l4_per2_hwmod
,
3113 .slave
= &dra7xx_uart7_hwmod
,
3114 .clk
= "l3_iclk_div",
3115 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3118 /* l4_per2 -> uart8 */
3119 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8
= {
3120 .master
= &dra7xx_l4_per2_hwmod
,
3121 .slave
= &dra7xx_uart8_hwmod
,
3122 .clk
= "l3_iclk_div",
3123 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3126 /* l4_per2 -> uart9 */
3127 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9
= {
3128 .master
= &dra7xx_l4_per2_hwmod
,
3129 .slave
= &dra7xx_uart9_hwmod
,
3130 .clk
= "l3_iclk_div",
3131 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3134 /* l4_wkup -> uart10 */
3135 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10
= {
3136 .master
= &dra7xx_l4_wkup_hwmod
,
3137 .slave
= &dra7xx_uart10_hwmod
,
3138 .clk
= "wkupaon_iclk_mux",
3139 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3142 /* l4_per3 -> usb_otg_ss1 */
3143 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1
= {
3144 .master
= &dra7xx_l4_per3_hwmod
,
3145 .slave
= &dra7xx_usb_otg_ss1_hwmod
,
3146 .clk
= "dpll_core_h13x2_ck",
3147 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3150 /* l4_per3 -> usb_otg_ss2 */
3151 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2
= {
3152 .master
= &dra7xx_l4_per3_hwmod
,
3153 .slave
= &dra7xx_usb_otg_ss2_hwmod
,
3154 .clk
= "dpll_core_h13x2_ck",
3155 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3158 /* l4_per3 -> usb_otg_ss3 */
3159 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3
= {
3160 .master
= &dra7xx_l4_per3_hwmod
,
3161 .slave
= &dra7xx_usb_otg_ss3_hwmod
,
3162 .clk
= "dpll_core_h13x2_ck",
3163 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3166 /* l4_per3 -> usb_otg_ss4 */
3167 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4
= {
3168 .master
= &dra7xx_l4_per3_hwmod
,
3169 .slave
= &dra7xx_usb_otg_ss4_hwmod
,
3170 .clk
= "dpll_core_h13x2_ck",
3171 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3174 /* l3_main_1 -> vcp1 */
3175 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1
= {
3176 .master
= &dra7xx_l3_main_1_hwmod
,
3177 .slave
= &dra7xx_vcp1_hwmod
,
3178 .clk
= "l3_iclk_div",
3179 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3182 /* l4_per2 -> vcp1 */
3183 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1
= {
3184 .master
= &dra7xx_l4_per2_hwmod
,
3185 .slave
= &dra7xx_vcp1_hwmod
,
3186 .clk
= "l3_iclk_div",
3187 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3190 /* l3_main_1 -> vcp2 */
3191 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2
= {
3192 .master
= &dra7xx_l3_main_1_hwmod
,
3193 .slave
= &dra7xx_vcp2_hwmod
,
3194 .clk
= "l3_iclk_div",
3195 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3198 /* l4_per2 -> vcp2 */
3199 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2
= {
3200 .master
= &dra7xx_l4_per2_hwmod
,
3201 .slave
= &dra7xx_vcp2_hwmod
,
3202 .clk
= "l3_iclk_div",
3203 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3206 /* l4_wkup -> wd_timer2 */
3207 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2
= {
3208 .master
= &dra7xx_l4_wkup_hwmod
,
3209 .slave
= &dra7xx_wd_timer2_hwmod
,
3210 .clk
= "wkupaon_iclk_mux",
3211 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3214 static struct omap_hwmod_ocp_if
*dra7xx_hwmod_ocp_ifs
[] __initdata
= {
3215 &dra7xx_l3_main_2__l3_instr
,
3216 &dra7xx_l4_cfg__l3_main_1
,
3217 &dra7xx_mpu__l3_main_1
,
3218 &dra7xx_l3_main_1__l3_main_2
,
3219 &dra7xx_l4_cfg__l3_main_2
,
3220 &dra7xx_l3_main_1__l4_cfg
,
3221 &dra7xx_l3_main_1__l4_per1
,
3222 &dra7xx_l3_main_1__l4_per2
,
3223 &dra7xx_l3_main_1__l4_per3
,
3224 &dra7xx_l3_main_1__l4_wkup
,
3225 &dra7xx_l4_per2__atl
,
3226 &dra7xx_l3_main_1__bb2d
,
3227 &dra7xx_l4_wkup__counter_32k
,
3228 &dra7xx_l4_wkup__ctrl_module_wkup
,
3229 &dra7xx_l4_wkup__dcan1
,
3230 &dra7xx_l4_per2__dcan2
,
3231 &dra7xx_l4_per2__cpgmac0
,
3233 &dra7xx_l4_cfg__dma_system
,
3234 &dra7xx_l3_main_1__dss
,
3235 &dra7xx_l3_main_1__dispc
,
3236 &dra7xx_l3_main_1__hdmi
,
3237 &dra7xx_l4_per1__elm
,
3238 &dra7xx_l4_wkup__gpio1
,
3239 &dra7xx_l4_per1__gpio2
,
3240 &dra7xx_l4_per1__gpio3
,
3241 &dra7xx_l4_per1__gpio4
,
3242 &dra7xx_l4_per1__gpio5
,
3243 &dra7xx_l4_per1__gpio6
,
3244 &dra7xx_l4_per1__gpio7
,
3245 &dra7xx_l4_per1__gpio8
,
3246 &dra7xx_l3_main_1__gpmc
,
3247 &dra7xx_l4_per1__hdq1w
,
3248 &dra7xx_l4_per1__i2c1
,
3249 &dra7xx_l4_per1__i2c2
,
3250 &dra7xx_l4_per1__i2c3
,
3251 &dra7xx_l4_per1__i2c4
,
3252 &dra7xx_l4_per1__i2c5
,
3253 &dra7xx_l4_cfg__mailbox1
,
3254 &dra7xx_l4_per3__mailbox2
,
3255 &dra7xx_l4_per3__mailbox3
,
3256 &dra7xx_l4_per3__mailbox4
,
3257 &dra7xx_l4_per3__mailbox5
,
3258 &dra7xx_l4_per3__mailbox6
,
3259 &dra7xx_l4_per3__mailbox7
,
3260 &dra7xx_l4_per3__mailbox8
,
3261 &dra7xx_l4_per3__mailbox9
,
3262 &dra7xx_l4_per3__mailbox10
,
3263 &dra7xx_l4_per3__mailbox11
,
3264 &dra7xx_l4_per3__mailbox12
,
3265 &dra7xx_l4_per3__mailbox13
,
3266 &dra7xx_l4_per1__mcspi1
,
3267 &dra7xx_l4_per1__mcspi2
,
3268 &dra7xx_l4_per1__mcspi3
,
3269 &dra7xx_l4_per1__mcspi4
,
3270 &dra7xx_l4_per1__mmc1
,
3271 &dra7xx_l4_per1__mmc2
,
3272 &dra7xx_l4_per1__mmc3
,
3273 &dra7xx_l4_per1__mmc4
,
3274 &dra7xx_l4_cfg__mpu
,
3275 &dra7xx_l4_cfg__ocp2scp1
,
3276 &dra7xx_l4_cfg__ocp2scp3
,
3277 &dra7xx_l3_main_1__pciess1
,
3278 &dra7xx_l4_cfg__pciess1
,
3279 &dra7xx_l3_main_1__pciess2
,
3280 &dra7xx_l4_cfg__pciess2
,
3281 &dra7xx_l3_main_1__qspi
,
3282 &dra7xx_l4_per3__rtcss
,
3283 &dra7xx_l4_cfg__sata
,
3284 &dra7xx_l4_cfg__smartreflex_core
,
3285 &dra7xx_l4_cfg__smartreflex_mpu
,
3286 &dra7xx_l4_cfg__spinlock
,
3287 &dra7xx_l4_wkup__timer1
,
3288 &dra7xx_l4_per1__timer2
,
3289 &dra7xx_l4_per1__timer3
,
3290 &dra7xx_l4_per1__timer4
,
3291 &dra7xx_l4_per3__timer5
,
3292 &dra7xx_l4_per3__timer6
,
3293 &dra7xx_l4_per3__timer7
,
3294 &dra7xx_l4_per3__timer8
,
3295 &dra7xx_l4_per1__timer9
,
3296 &dra7xx_l4_per1__timer10
,
3297 &dra7xx_l4_per1__timer11
,
3298 &dra7xx_l4_per1__uart1
,
3299 &dra7xx_l4_per1__uart2
,
3300 &dra7xx_l4_per1__uart3
,
3301 &dra7xx_l4_per1__uart4
,
3302 &dra7xx_l4_per1__uart5
,
3303 &dra7xx_l4_per1__uart6
,
3304 &dra7xx_l4_per2__uart7
,
3305 &dra7xx_l4_per2__uart8
,
3306 &dra7xx_l4_per2__uart9
,
3307 &dra7xx_l4_wkup__uart10
,
3308 &dra7xx_l4_per3__usb_otg_ss1
,
3309 &dra7xx_l4_per3__usb_otg_ss2
,
3310 &dra7xx_l4_per3__usb_otg_ss3
,
3311 &dra7xx_l3_main_1__vcp1
,
3312 &dra7xx_l4_per2__vcp1
,
3313 &dra7xx_l3_main_1__vcp2
,
3314 &dra7xx_l4_per2__vcp2
,
3315 &dra7xx_l4_wkup__wd_timer2
,
3319 static struct omap_hwmod_ocp_if
*dra74x_hwmod_ocp_ifs
[] __initdata
= {
3320 &dra7xx_l4_per3__usb_otg_ss4
,
3324 static struct omap_hwmod_ocp_if
*dra72x_hwmod_ocp_ifs
[] __initdata
= {
3328 int __init
dra7xx_hwmod_init(void)
3333 ret
= omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs
);
3335 if (!ret
&& soc_is_dra74x())
3336 return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs
);
3337 else if (!ret
&& soc_is_dra72x())
3338 return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs
);