4 * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
5 * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
18 #include <linux/platform_data/gpio-omap.h>
19 #include <linux/platform_data/hsmmc-omap.h>
20 #include <linux/platform_data/spi-omap2-mcspi.h>
21 #include <plat/dmtimer.h>
23 #include "omap_hwmod_common_data.h"
29 * DM816X hardware modules integration data
31 * Note: This is incomplete and at present, not generated from h/w database.
35 * The alwon .clkctrl_offs field is offset from the CM_ALWON, that's
36 * TRM 18.7.17 CM_ALWON device register values minus 0x1400.
38 #define DM816X_DM_ALWON_BASE 0x1400
39 #define DM816X_CM_ALWON_MCASP0_CLKCTRL (0x1540 - DM816X_DM_ALWON_BASE)
40 #define DM816X_CM_ALWON_MCASP1_CLKCTRL (0x1544 - DM816X_DM_ALWON_BASE)
41 #define DM816X_CM_ALWON_MCASP2_CLKCTRL (0x1548 - DM816X_DM_ALWON_BASE)
42 #define DM816X_CM_ALWON_MCBSP_CLKCTRL (0x154c - DM816X_DM_ALWON_BASE)
43 #define DM816X_CM_ALWON_UART_0_CLKCTRL (0x1550 - DM816X_DM_ALWON_BASE)
44 #define DM816X_CM_ALWON_UART_1_CLKCTRL (0x1554 - DM816X_DM_ALWON_BASE)
45 #define DM816X_CM_ALWON_UART_2_CLKCTRL (0x1558 - DM816X_DM_ALWON_BASE)
46 #define DM816X_CM_ALWON_GPIO_0_CLKCTRL (0x155c - DM816X_DM_ALWON_BASE)
47 #define DM816X_CM_ALWON_GPIO_1_CLKCTRL (0x1560 - DM816X_DM_ALWON_BASE)
48 #define DM816X_CM_ALWON_I2C_0_CLKCTRL (0x1564 - DM816X_DM_ALWON_BASE)
49 #define DM816X_CM_ALWON_I2C_1_CLKCTRL (0x1568 - DM816X_DM_ALWON_BASE)
50 #define DM816X_CM_ALWON_TIMER_1_CLKCTRL (0x1570 - DM816X_DM_ALWON_BASE)
51 #define DM816X_CM_ALWON_TIMER_2_CLKCTRL (0x1574 - DM816X_DM_ALWON_BASE)
52 #define DM816X_CM_ALWON_TIMER_3_CLKCTRL (0x1578 - DM816X_DM_ALWON_BASE)
53 #define DM816X_CM_ALWON_TIMER_4_CLKCTRL (0x157c - DM816X_DM_ALWON_BASE)
54 #define DM816X_CM_ALWON_TIMER_5_CLKCTRL (0x1580 - DM816X_DM_ALWON_BASE)
55 #define DM816X_CM_ALWON_TIMER_6_CLKCTRL (0x1584 - DM816X_DM_ALWON_BASE)
56 #define DM816X_CM_ALWON_TIMER_7_CLKCTRL (0x1588 - DM816X_DM_ALWON_BASE)
57 #define DM816X_CM_ALWON_WDTIMER_CLKCTRL (0x158c - DM816X_DM_ALWON_BASE)
58 #define DM816X_CM_ALWON_SPI_CLKCTRL (0x1590 - DM816X_DM_ALWON_BASE)
59 #define DM816X_CM_ALWON_MAILBOX_CLKCTRL (0x1594 - DM816X_DM_ALWON_BASE)
60 #define DM816X_CM_ALWON_SPINBOX_CLKCTRL (0x1598 - DM816X_DM_ALWON_BASE)
61 #define DM816X_CM_ALWON_MMUDATA_CLKCTRL (0x159c - DM816X_DM_ALWON_BASE)
62 #define DM816X_CM_ALWON_MMUCFG_CLKCTRL (0x15a8 - DM816X_DM_ALWON_BASE)
63 #define DM816X_CM_ALWON_SDIO_CLKCTRL (0x15b0 - DM816X_DM_ALWON_BASE)
64 #define DM816X_CM_ALWON_OCMC_0_CLKCTRL (0x15b4 - DM816X_DM_ALWON_BASE)
65 #define DM816X_CM_ALWON_OCMC_1_CLKCTRL (0x15b8 - DM816X_DM_ALWON_BASE)
66 #define DM816X_CM_ALWON_CONTRL_CLKCTRL (0x15c4 - DM816X_DM_ALWON_BASE)
67 #define DM816X_CM_ALWON_GPMC_CLKCTRL (0x15d0 - DM816X_DM_ALWON_BASE)
68 #define DM816X_CM_ALWON_ETHERNET_0_CLKCTRL (0x15d4 - DM816X_DM_ALWON_BASE)
69 #define DM816X_CM_ALWON_ETHERNET_1_CLKCTRL (0x15d8 - DM816X_DM_ALWON_BASE)
70 #define DM816X_CM_ALWON_MPU_CLKCTRL (0x15dc - DM816X_DM_ALWON_BASE)
71 #define DM816X_CM_ALWON_L3_CLKCTRL (0x15e4 - DM816X_DM_ALWON_BASE)
72 #define DM816X_CM_ALWON_L4HS_CLKCTRL (0x15e8 - DM816X_DM_ALWON_BASE)
73 #define DM816X_CM_ALWON_L4LS_CLKCTRL (0x15ec - DM816X_DM_ALWON_BASE)
74 #define DM816X_CM_ALWON_RTC_CLKCTRL (0x15f0 - DM816X_DM_ALWON_BASE)
75 #define DM816X_CM_ALWON_TPCC_CLKCTRL (0x15f4 - DM816X_DM_ALWON_BASE)
76 #define DM816X_CM_ALWON_TPTC0_CLKCTRL (0x15f8 - DM816X_DM_ALWON_BASE)
77 #define DM816X_CM_ALWON_TPTC1_CLKCTRL (0x15fc - DM816X_DM_ALWON_BASE)
78 #define DM816X_CM_ALWON_TPTC2_CLKCTRL (0x1600 - DM816X_DM_ALWON_BASE)
79 #define DM816X_CM_ALWON_TPTC3_CLKCTRL (0x1604 - DM816X_DM_ALWON_BASE)
80 #define DM816X_CM_ALWON_SR_0_CLKCTRL (0x1608 - DM816X_DM_ALWON_BASE)
81 #define DM816X_CM_ALWON_SR_1_CLKCTRL (0x160c - DM816X_DM_ALWON_BASE)
84 * The default .clkctrl_offs field is offset from CM_DEFAULT, that's
85 * TRM 18.7.6 CM_DEFAULT device register values minus 0x500
87 #define DM816X_CM_DEFAULT_OFFSET 0x500
88 #define DM816X_CM_DEFAULT_USB_CLKCTRL (0x558 - DM816X_CM_DEFAULT_OFFSET)
90 /* L3 Interconnect entries clocked at 125, 250 and 500MHz */
91 static struct omap_hwmod dm816x_alwon_l3_slow_hwmod
= {
92 .name
= "alwon_l3_slow",
93 .clkdm_name
= "alwon_l3s_clkdm",
94 .class = &l3_hwmod_class
,
95 .flags
= HWMOD_NO_IDLEST
,
98 static struct omap_hwmod dm816x_default_l3_slow_hwmod
= {
99 .name
= "default_l3_slow",
100 .clkdm_name
= "default_l3_slow_clkdm",
101 .class = &l3_hwmod_class
,
102 .flags
= HWMOD_NO_IDLEST
,
105 static struct omap_hwmod dm816x_alwon_l3_med_hwmod
= {
107 .clkdm_name
= "alwon_l3_med_clkdm",
108 .class = &l3_hwmod_class
,
109 .flags
= HWMOD_NO_IDLEST
,
112 static struct omap_hwmod dm816x_alwon_l3_fast_hwmod
= {
114 .clkdm_name
= "alwon_l3_fast_clkdm",
115 .class = &l3_hwmod_class
,
116 .flags
= HWMOD_NO_IDLEST
,
120 * L4 standard peripherals, see TRM table 1-12 for devices using this.
121 * See TRM table 1-73 for devices using the 125MHz SYSCLK6 clock.
123 static struct omap_hwmod dm816x_l4_ls_hwmod
= {
125 .clkdm_name
= "alwon_l3s_clkdm",
126 .class = &l4_hwmod_class
,
130 * L4 high-speed peripherals. For devices using this, please see the TRM
131 * table 1-13. On dm816x, only EMAC, MDIO and SATA use this. See also TRM
132 * table 1-73 for devices using 250MHz SYSCLK5 clock.
134 static struct omap_hwmod dm816x_l4_hs_hwmod
= {
136 .clkdm_name
= "alwon_l3_med_clkdm",
137 .class = &l4_hwmod_class
,
140 /* L3 slow -> L4 ls peripheral interface running at 125MHz */
141 static struct omap_hwmod_ocp_if dm816x_alwon_l3_slow__l4_ls
= {
142 .master
= &dm816x_alwon_l3_slow_hwmod
,
143 .slave
= &dm816x_l4_ls_hwmod
,
144 .user
= OCP_USER_MPU
,
147 /* L3 med -> L4 fast peripheral interface running at 250MHz */
148 static struct omap_hwmod_ocp_if dm816x_alwon_l3_slow__l4_hs
= {
149 .master
= &dm816x_alwon_l3_med_hwmod
,
150 .slave
= &dm816x_l4_hs_hwmod
,
151 .user
= OCP_USER_MPU
,
155 static struct omap_hwmod dm816x_mpu_hwmod
= {
157 .clkdm_name
= "alwon_mpu_clkdm",
158 .class = &mpu_hwmod_class
,
159 .flags
= HWMOD_INIT_NO_IDLE
,
160 .main_clk
= "mpu_ck",
163 .clkctrl_offs
= DM816X_CM_ALWON_MPU_CLKCTRL
,
164 .modulemode
= MODULEMODE_SWCTRL
,
169 static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_slow
= {
170 .master
= &dm816x_mpu_hwmod
,
171 .slave
= &dm816x_alwon_l3_slow_hwmod
,
172 .user
= OCP_USER_MPU
,
175 /* L3 med peripheral interface running at 250MHz */
176 static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_med
= {
177 .master
= &dm816x_mpu_hwmod
,
178 .slave
= &dm816x_alwon_l3_med_hwmod
,
179 .user
= OCP_USER_MPU
,
183 static struct omap_hwmod_class_sysconfig uart_sysc
= {
187 .sysc_flags
= SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
188 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
|
189 SYSS_HAS_RESET_STATUS
,
190 .idlemodes
= SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
192 .sysc_fields
= &omap_hwmod_sysc_type1
,
195 static struct omap_hwmod_class uart_class
= {
200 static struct omap_hwmod dm816x_uart1_hwmod
= {
202 .clkdm_name
= "alwon_l3s_clkdm",
203 .main_clk
= "sysclk10_ck",
206 .clkctrl_offs
= DM816X_CM_ALWON_UART_0_CLKCTRL
,
207 .modulemode
= MODULEMODE_SWCTRL
,
210 .class = &uart_class
,
211 .flags
= DEBUG_TI81XXUART1_FLAGS
,
214 static struct omap_hwmod_ocp_if dm816x_l4_ls__uart1
= {
215 .master
= &dm816x_l4_ls_hwmod
,
216 .slave
= &dm816x_uart1_hwmod
,
218 .user
= OCP_USER_MPU
,
221 static struct omap_hwmod dm816x_uart2_hwmod
= {
223 .clkdm_name
= "alwon_l3s_clkdm",
224 .main_clk
= "sysclk10_ck",
227 .clkctrl_offs
= DM816X_CM_ALWON_UART_1_CLKCTRL
,
228 .modulemode
= MODULEMODE_SWCTRL
,
231 .class = &uart_class
,
232 .flags
= DEBUG_TI81XXUART2_FLAGS
,
235 static struct omap_hwmod_ocp_if dm816x_l4_ls__uart2
= {
236 .master
= &dm816x_l4_ls_hwmod
,
237 .slave
= &dm816x_uart2_hwmod
,
239 .user
= OCP_USER_MPU
,
242 static struct omap_hwmod dm816x_uart3_hwmod
= {
244 .clkdm_name
= "alwon_l3s_clkdm",
245 .main_clk
= "sysclk10_ck",
248 .clkctrl_offs
= DM816X_CM_ALWON_UART_2_CLKCTRL
,
249 .modulemode
= MODULEMODE_SWCTRL
,
252 .class = &uart_class
,
253 .flags
= DEBUG_TI81XXUART3_FLAGS
,
256 static struct omap_hwmod_ocp_if dm816x_l4_ls__uart3
= {
257 .master
= &dm816x_l4_ls_hwmod
,
258 .slave
= &dm816x_uart3_hwmod
,
260 .user
= OCP_USER_MPU
,
263 static struct omap_hwmod_class_sysconfig wd_timer_sysc
= {
267 .sysc_flags
= SYSC_HAS_EMUFREE
| SYSC_HAS_SOFTRESET
|
268 SYSS_HAS_RESET_STATUS
,
269 .sysc_fields
= &omap_hwmod_sysc_type1
,
272 static struct omap_hwmod_class wd_timer_class
= {
274 .sysc
= &wd_timer_sysc
,
275 .pre_shutdown
= &omap2_wd_timer_disable
,
276 .reset
= &omap2_wd_timer_reset
,
279 static struct omap_hwmod dm816x_wd_timer_hwmod
= {
281 .clkdm_name
= "alwon_l3s_clkdm",
282 .main_clk
= "sysclk18_ck",
283 .flags
= HWMOD_NO_IDLEST
,
286 .clkctrl_offs
= DM816X_CM_ALWON_WDTIMER_CLKCTRL
,
287 .modulemode
= MODULEMODE_SWCTRL
,
290 .class = &wd_timer_class
,
293 static struct omap_hwmod_ocp_if dm816x_l4_ls__wd_timer1
= {
294 .master
= &dm816x_l4_ls_hwmod
,
295 .slave
= &dm816x_wd_timer_hwmod
,
297 .user
= OCP_USER_MPU
,
301 static struct omap_hwmod_class_sysconfig i2c_sysc
= {
305 .sysc_flags
= SYSC_HAS_SIDLEMODE
|
306 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
308 .idlemodes
= SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
,
309 .sysc_fields
= &omap_hwmod_sysc_type1
,
312 static struct omap_hwmod_class i2c_class
= {
317 static struct omap_hwmod dm81xx_i2c1_hwmod
= {
319 .clkdm_name
= "alwon_l3s_clkdm",
320 .main_clk
= "sysclk10_ck",
323 .clkctrl_offs
= DM816X_CM_ALWON_I2C_0_CLKCTRL
,
324 .modulemode
= MODULEMODE_SWCTRL
,
330 static struct omap_hwmod_ocp_if dm816x_l4_ls__i2c1
= {
331 .master
= &dm816x_l4_ls_hwmod
,
332 .slave
= &dm81xx_i2c1_hwmod
,
334 .user
= OCP_USER_MPU
,
337 static struct omap_hwmod dm816x_i2c2_hwmod
= {
339 .clkdm_name
= "alwon_l3s_clkdm",
340 .main_clk
= "sysclk10_ck",
343 .clkctrl_offs
= DM816X_CM_ALWON_I2C_1_CLKCTRL
,
344 .modulemode
= MODULEMODE_SWCTRL
,
350 static struct omap_hwmod_class_sysconfig dm81xx_elm_sysc
= {
354 .sysc_flags
= SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
356 SYSS_HAS_RESET_STATUS
,
357 .idlemodes
= SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
,
358 .sysc_fields
= &omap_hwmod_sysc_type1
,
361 static struct omap_hwmod_ocp_if dm816x_l4_ls__i2c2
= {
362 .master
= &dm816x_l4_ls_hwmod
,
363 .slave
= &dm816x_i2c2_hwmod
,
365 .user
= OCP_USER_MPU
,
368 static struct omap_hwmod_class dm81xx_elm_hwmod_class
= {
370 .sysc
= &dm81xx_elm_sysc
,
373 static struct omap_hwmod dm81xx_elm_hwmod
= {
375 .clkdm_name
= "alwon_l3s_clkdm",
376 .class = &dm81xx_elm_hwmod_class
,
377 .main_clk
= "sysclk6_ck",
380 static struct omap_hwmod_ocp_if dm81xx_l4_ls__elm
= {
381 .master
= &dm816x_l4_ls_hwmod
,
382 .slave
= &dm81xx_elm_hwmod
,
383 .user
= OCP_USER_MPU
,
386 static struct omap_hwmod_class_sysconfig dm81xx_gpio_sysc
= {
390 .sysc_flags
= SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
391 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
392 SYSS_HAS_RESET_STATUS
,
393 .idlemodes
= SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
395 .sysc_fields
= &omap_hwmod_sysc_type1
,
398 static struct omap_hwmod_class dm81xx_gpio_hwmod_class
= {
400 .sysc
= &dm81xx_gpio_sysc
,
404 static struct omap_gpio_dev_attr gpio_dev_attr
= {
409 static struct omap_hwmod_opt_clk gpio1_opt_clks
[] = {
410 { .role
= "dbclk", .clk
= "sysclk18_ck" },
413 static struct omap_hwmod dm81xx_gpio1_hwmod
= {
415 .clkdm_name
= "alwon_l3s_clkdm",
416 .class = &dm81xx_gpio_hwmod_class
,
417 .main_clk
= "sysclk6_ck",
420 .clkctrl_offs
= DM816X_CM_ALWON_GPIO_0_CLKCTRL
,
421 .modulemode
= MODULEMODE_SWCTRL
,
424 .opt_clks
= gpio1_opt_clks
,
425 .opt_clks_cnt
= ARRAY_SIZE(gpio1_opt_clks
),
426 .dev_attr
= &gpio_dev_attr
,
429 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio1
= {
430 .master
= &dm816x_l4_ls_hwmod
,
431 .slave
= &dm81xx_gpio1_hwmod
,
432 .user
= OCP_USER_MPU
,
435 static struct omap_hwmod_opt_clk gpio2_opt_clks
[] = {
436 { .role
= "dbclk", .clk
= "sysclk18_ck" },
439 static struct omap_hwmod dm81xx_gpio2_hwmod
= {
441 .clkdm_name
= "alwon_l3s_clkdm",
442 .class = &dm81xx_gpio_hwmod_class
,
443 .main_clk
= "sysclk6_ck",
446 .clkctrl_offs
= DM816X_CM_ALWON_GPIO_1_CLKCTRL
,
447 .modulemode
= MODULEMODE_SWCTRL
,
450 .opt_clks
= gpio2_opt_clks
,
451 .opt_clks_cnt
= ARRAY_SIZE(gpio2_opt_clks
),
452 .dev_attr
= &gpio_dev_attr
,
455 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2
= {
456 .master
= &dm816x_l4_ls_hwmod
,
457 .slave
= &dm81xx_gpio2_hwmod
,
458 .user
= OCP_USER_MPU
,
461 static struct omap_hwmod_class_sysconfig dm81xx_gpmc_sysc
= {
465 .sysc_flags
= SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
466 SYSC_HAS_AUTOIDLE
| SYSS_HAS_RESET_STATUS
,
467 .idlemodes
= SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
,
468 .sysc_fields
= &omap_hwmod_sysc_type1
,
471 static struct omap_hwmod_class dm81xx_gpmc_hwmod_class
= {
473 .sysc
= &dm81xx_gpmc_sysc
,
476 static struct omap_hwmod dm81xx_gpmc_hwmod
= {
478 .clkdm_name
= "alwon_l3s_clkdm",
479 .class = &dm81xx_gpmc_hwmod_class
,
480 .main_clk
= "sysclk6_ck",
481 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
482 .flags
= DEBUG_OMAP_GPMC_HWMOD_FLAGS
,
485 .clkctrl_offs
= DM816X_CM_ALWON_GPMC_CLKCTRL
,
486 .modulemode
= MODULEMODE_SWCTRL
,
491 struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__gpmc
= {
492 .master
= &dm816x_alwon_l3_slow_hwmod
,
493 .slave
= &dm81xx_gpmc_hwmod
,
494 .user
= OCP_USER_MPU
,
497 static struct omap_hwmod_class_sysconfig dm81xx_usbhsotg_sysc
= {
500 .sysc_flags
= SYSC_HAS_SIDLEMODE
| SYSC_HAS_MIDLEMODE
|
502 .idlemodes
= SIDLE_SMART
| MSTANDBY_FORCE
| MSTANDBY_SMART
,
503 .sysc_fields
= &omap_hwmod_sysc_type2
,
506 static struct omap_hwmod_class dm81xx_usbotg_class
= {
508 .sysc
= &dm81xx_usbhsotg_sysc
,
511 static struct omap_hwmod dm81xx_usbss_hwmod
= {
512 .name
= "usb_otg_hs",
513 .clkdm_name
= "default_l3_slow_clkdm",
514 .main_clk
= "sysclk6_ck",
517 .clkctrl_offs
= DM816X_CM_DEFAULT_USB_CLKCTRL
,
518 .modulemode
= MODULEMODE_SWCTRL
,
521 .class = &dm81xx_usbotg_class
,
524 static struct omap_hwmod_ocp_if dm81xx_default_l3_slow__usbss
= {
525 .master
= &dm816x_default_l3_slow_hwmod
,
526 .slave
= &dm81xx_usbss_hwmod
,
528 .user
= OCP_USER_MPU
,
531 static struct omap_hwmod_class_sysconfig dm816x_timer_sysc
= {
535 .sysc_flags
= SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
,
536 .idlemodes
= SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
538 .sysc_fields
= &omap_hwmod_sysc_type2
,
541 static struct omap_hwmod_class dm816x_timer_hwmod_class
= {
543 .sysc
= &dm816x_timer_sysc
,
546 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr
= {
547 .timer_capability
= OMAP_TIMER_ALWON
,
550 static struct omap_hwmod dm816x_timer1_hwmod
= {
552 .clkdm_name
= "alwon_l3s_clkdm",
553 .main_clk
= "timer1_fck",
556 .clkctrl_offs
= DM816X_CM_ALWON_TIMER_1_CLKCTRL
,
557 .modulemode
= MODULEMODE_SWCTRL
,
560 .dev_attr
= &capability_alwon_dev_attr
,
561 .class = &dm816x_timer_hwmod_class
,
564 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1
= {
565 .master
= &dm816x_l4_ls_hwmod
,
566 .slave
= &dm816x_timer1_hwmod
,
568 .user
= OCP_USER_MPU
,
571 static struct omap_hwmod dm816x_timer2_hwmod
= {
573 .clkdm_name
= "alwon_l3s_clkdm",
574 .main_clk
= "timer2_fck",
577 .clkctrl_offs
= DM816X_CM_ALWON_TIMER_2_CLKCTRL
,
578 .modulemode
= MODULEMODE_SWCTRL
,
581 .dev_attr
= &capability_alwon_dev_attr
,
582 .class = &dm816x_timer_hwmod_class
,
585 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer2
= {
586 .master
= &dm816x_l4_ls_hwmod
,
587 .slave
= &dm816x_timer2_hwmod
,
589 .user
= OCP_USER_MPU
,
592 static struct omap_hwmod dm816x_timer3_hwmod
= {
594 .clkdm_name
= "alwon_l3s_clkdm",
595 .main_clk
= "timer3_fck",
598 .clkctrl_offs
= DM816X_CM_ALWON_TIMER_3_CLKCTRL
,
599 .modulemode
= MODULEMODE_SWCTRL
,
602 .dev_attr
= &capability_alwon_dev_attr
,
603 .class = &dm816x_timer_hwmod_class
,
606 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer3
= {
607 .master
= &dm816x_l4_ls_hwmod
,
608 .slave
= &dm816x_timer3_hwmod
,
610 .user
= OCP_USER_MPU
,
613 static struct omap_hwmod dm816x_timer4_hwmod
= {
615 .clkdm_name
= "alwon_l3s_clkdm",
616 .main_clk
= "timer4_fck",
619 .clkctrl_offs
= DM816X_CM_ALWON_TIMER_4_CLKCTRL
,
620 .modulemode
= MODULEMODE_SWCTRL
,
623 .dev_attr
= &capability_alwon_dev_attr
,
624 .class = &dm816x_timer_hwmod_class
,
627 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer4
= {
628 .master
= &dm816x_l4_ls_hwmod
,
629 .slave
= &dm816x_timer4_hwmod
,
631 .user
= OCP_USER_MPU
,
634 static struct omap_hwmod dm816x_timer5_hwmod
= {
636 .clkdm_name
= "alwon_l3s_clkdm",
637 .main_clk
= "timer5_fck",
640 .clkctrl_offs
= DM816X_CM_ALWON_TIMER_5_CLKCTRL
,
641 .modulemode
= MODULEMODE_SWCTRL
,
644 .dev_attr
= &capability_alwon_dev_attr
,
645 .class = &dm816x_timer_hwmod_class
,
648 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer5
= {
649 .master
= &dm816x_l4_ls_hwmod
,
650 .slave
= &dm816x_timer5_hwmod
,
652 .user
= OCP_USER_MPU
,
655 static struct omap_hwmod dm816x_timer6_hwmod
= {
657 .clkdm_name
= "alwon_l3s_clkdm",
658 .main_clk
= "timer6_fck",
661 .clkctrl_offs
= DM816X_CM_ALWON_TIMER_6_CLKCTRL
,
662 .modulemode
= MODULEMODE_SWCTRL
,
665 .dev_attr
= &capability_alwon_dev_attr
,
666 .class = &dm816x_timer_hwmod_class
,
669 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer6
= {
670 .master
= &dm816x_l4_ls_hwmod
,
671 .slave
= &dm816x_timer6_hwmod
,
673 .user
= OCP_USER_MPU
,
676 static struct omap_hwmod dm816x_timer7_hwmod
= {
678 .clkdm_name
= "alwon_l3s_clkdm",
679 .main_clk
= "timer7_fck",
682 .clkctrl_offs
= DM816X_CM_ALWON_TIMER_7_CLKCTRL
,
683 .modulemode
= MODULEMODE_SWCTRL
,
686 .dev_attr
= &capability_alwon_dev_attr
,
687 .class = &dm816x_timer_hwmod_class
,
690 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer7
= {
691 .master
= &dm816x_l4_ls_hwmod
,
692 .slave
= &dm816x_timer7_hwmod
,
694 .user
= OCP_USER_MPU
,
698 static struct omap_hwmod_class_sysconfig dm816x_emac_sysc
= {
701 .sysc_flags
= SYSC_HAS_SOFTRESET
,
702 .sysc_fields
= &omap_hwmod_sysc_type2
,
705 static struct omap_hwmod_class dm816x_emac_hwmod_class
= {
707 .sysc
= &dm816x_emac_sysc
,
711 * On dm816x the MDIO is within EMAC0. As the MDIO driver is a separate
712 * driver probed before EMAC0, we let MDIO do the clock idling.
714 static struct omap_hwmod dm816x_emac0_hwmod
= {
716 .clkdm_name
= "alwon_ethernet_clkdm",
717 .class = &dm816x_emac_hwmod_class
,
720 static struct omap_hwmod_ocp_if dm816x_l4_hs__emac0
= {
721 .master
= &dm816x_l4_hs_hwmod
,
722 .slave
= &dm816x_emac0_hwmod
,
724 .user
= OCP_USER_MPU
,
727 static struct omap_hwmod_class dm816x_mdio_hwmod_class
= {
728 .name
= "davinci_mdio",
729 .sysc
= &dm816x_emac_sysc
,
732 struct omap_hwmod dm816x_emac0_mdio_hwmod
= {
733 .name
= "davinci_mdio",
734 .class = &dm816x_mdio_hwmod_class
,
735 .clkdm_name
= "alwon_ethernet_clkdm",
736 .main_clk
= "sysclk24_ck",
737 .flags
= HWMOD_NO_IDLEST
,
739 * REVISIT: This should be moved to the emac0_hwmod
740 * once we have a better way to handle device slaves.
744 .clkctrl_offs
= DM816X_CM_ALWON_ETHERNET_0_CLKCTRL
,
745 .modulemode
= MODULEMODE_SWCTRL
,
750 struct omap_hwmod_ocp_if dm816x_emac0__mdio
= {
751 .master
= &dm816x_l4_hs_hwmod
,
752 .slave
= &dm816x_emac0_mdio_hwmod
,
753 .user
= OCP_USER_MPU
,
756 static struct omap_hwmod dm816x_emac1_hwmod
= {
758 .clkdm_name
= "alwon_ethernet_clkdm",
759 .main_clk
= "sysclk24_ck",
760 .flags
= HWMOD_NO_IDLEST
,
763 .clkctrl_offs
= DM816X_CM_ALWON_ETHERNET_1_CLKCTRL
,
764 .modulemode
= MODULEMODE_SWCTRL
,
767 .class = &dm816x_emac_hwmod_class
,
770 static struct omap_hwmod_ocp_if dm816x_l4_hs__emac1
= {
771 .master
= &dm816x_l4_hs_hwmod
,
772 .slave
= &dm816x_emac1_hwmod
,
774 .user
= OCP_USER_MPU
,
777 static struct omap_hwmod_class_sysconfig dm816x_mmc_sysc
= {
781 .sysc_flags
= SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
782 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
783 SYSC_HAS_AUTOIDLE
| SYSS_HAS_RESET_STATUS
,
784 .idlemodes
= SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
,
785 .sysc_fields
= &omap_hwmod_sysc_type1
,
788 static struct omap_hwmod_class dm816x_mmc_class
= {
790 .sysc
= &dm816x_mmc_sysc
,
793 static struct omap_hwmod_opt_clk dm816x_mmc1_opt_clks
[] = {
794 { .role
= "dbck", .clk
= "sysclk18_ck", },
797 static struct omap_hsmmc_dev_attr mmc1_dev_attr
= {
798 .flags
= OMAP_HSMMC_SUPPORTS_DUAL_VOLT
,
801 static struct omap_hwmod dm816x_mmc1_hwmod
= {
803 .clkdm_name
= "alwon_l3s_clkdm",
804 .opt_clks
= dm816x_mmc1_opt_clks
,
805 .opt_clks_cnt
= ARRAY_SIZE(dm816x_mmc1_opt_clks
),
806 .main_clk
= "sysclk10_ck",
809 .clkctrl_offs
= DM816X_CM_ALWON_SDIO_CLKCTRL
,
810 .modulemode
= MODULEMODE_SWCTRL
,
813 .dev_attr
= &mmc1_dev_attr
,
814 .class = &dm816x_mmc_class
,
817 static struct omap_hwmod_ocp_if dm816x_l4_ls__mmc1
= {
818 .master
= &dm816x_l4_ls_hwmod
,
819 .slave
= &dm816x_mmc1_hwmod
,
821 .user
= OCP_USER_MPU
,
822 .flags
= OMAP_FIREWALL_L4
825 static struct omap_hwmod_class_sysconfig dm816x_mcspi_sysc
= {
829 .sysc_flags
= SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
830 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
831 SYSC_HAS_AUTOIDLE
| SYSS_HAS_RESET_STATUS
,
832 .idlemodes
= SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
,
833 .sysc_fields
= &omap_hwmod_sysc_type1
,
836 static struct omap_hwmod_class dm816x_mcspi_class
= {
838 .sysc
= &dm816x_mcspi_sysc
,
839 .rev
= OMAP3_MCSPI_REV
,
842 static struct omap2_mcspi_dev_attr dm816x_mcspi1_dev_attr
= {
846 static struct omap_hwmod dm816x_mcspi1_hwmod
= {
848 .clkdm_name
= "alwon_l3s_clkdm",
849 .main_clk
= "sysclk10_ck",
852 .clkctrl_offs
= DM816X_CM_ALWON_SPI_CLKCTRL
,
853 .modulemode
= MODULEMODE_SWCTRL
,
856 .class = &dm816x_mcspi_class
,
857 .dev_attr
= &dm816x_mcspi1_dev_attr
,
860 static struct omap_hwmod_ocp_if dm816x_l4_ls__mcspi1
= {
861 .master
= &dm816x_l4_ls_hwmod
,
862 .slave
= &dm816x_mcspi1_hwmod
,
864 .user
= OCP_USER_MPU
,
867 static struct omap_hwmod_class_sysconfig dm816x_mailbox_sysc
= {
871 .sysc_flags
= SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
872 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
,
873 .idlemodes
= SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
,
874 .sysc_fields
= &omap_hwmod_sysc_type1
,
877 static struct omap_hwmod_class dm816x_mailbox_hwmod_class
= {
879 .sysc
= &dm816x_mailbox_sysc
,
882 static struct omap_hwmod dm816x_mailbox_hwmod
= {
884 .clkdm_name
= "alwon_l3s_clkdm",
885 .class = &dm816x_mailbox_hwmod_class
,
886 .main_clk
= "sysclk6_ck",
889 .clkctrl_offs
= DM816X_CM_ALWON_MAILBOX_CLKCTRL
,
890 .modulemode
= MODULEMODE_SWCTRL
,
895 static struct omap_hwmod_ocp_if dm816x_l4_ls__mailbox
= {
896 .master
= &dm816x_l4_ls_hwmod
,
897 .slave
= &dm816x_mailbox_hwmod
,
898 .user
= OCP_USER_MPU
,
901 static struct omap_hwmod_class dm816x_tpcc_hwmod_class
= {
905 struct omap_hwmod dm816x_tpcc_hwmod
= {
907 .class = &dm816x_tpcc_hwmod_class
,
908 .clkdm_name
= "alwon_l3s_clkdm",
909 .main_clk
= "sysclk4_ck",
912 .clkctrl_offs
= DM816X_CM_ALWON_TPCC_CLKCTRL
,
913 .modulemode
= MODULEMODE_SWCTRL
,
918 struct omap_hwmod_ocp_if dm816x_alwon_l3_fast__tpcc
= {
919 .master
= &dm816x_alwon_l3_fast_hwmod
,
920 .slave
= &dm816x_tpcc_hwmod
,
922 .user
= OCP_USER_MPU
,
925 static struct omap_hwmod_addr_space dm816x_tptc0_addr_space
[] = {
927 .pa_start
= 0x49800000,
928 .pa_end
= 0x49800000 + SZ_8K
- 1,
929 .flags
= ADDR_TYPE_RT
,
934 static struct omap_hwmod_class dm816x_tptc0_hwmod_class
= {
938 struct omap_hwmod dm816x_tptc0_hwmod
= {
940 .class = &dm816x_tptc0_hwmod_class
,
941 .clkdm_name
= "alwon_l3s_clkdm",
942 .main_clk
= "sysclk4_ck",
945 .clkctrl_offs
= DM816X_CM_ALWON_TPTC0_CLKCTRL
,
946 .modulemode
= MODULEMODE_SWCTRL
,
951 struct omap_hwmod_ocp_if dm816x_alwon_l3_fast__tptc0
= {
952 .master
= &dm816x_alwon_l3_fast_hwmod
,
953 .slave
= &dm816x_tptc0_hwmod
,
955 .addr
= dm816x_tptc0_addr_space
,
956 .user
= OCP_USER_MPU
,
959 struct omap_hwmod_ocp_if dm816x_tptc0__alwon_l3_fast
= {
960 .master
= &dm816x_tptc0_hwmod
,
961 .slave
= &dm816x_alwon_l3_fast_hwmod
,
963 .addr
= dm816x_tptc0_addr_space
,
964 .user
= OCP_USER_MPU
,
967 static struct omap_hwmod_addr_space dm816x_tptc1_addr_space
[] = {
969 .pa_start
= 0x49900000,
970 .pa_end
= 0x49900000 + SZ_8K
- 1,
971 .flags
= ADDR_TYPE_RT
,
976 static struct omap_hwmod_class dm816x_tptc1_hwmod_class
= {
980 struct omap_hwmod dm816x_tptc1_hwmod
= {
982 .class = &dm816x_tptc1_hwmod_class
,
983 .clkdm_name
= "alwon_l3s_clkdm",
984 .main_clk
= "sysclk4_ck",
987 .clkctrl_offs
= DM816X_CM_ALWON_TPTC1_CLKCTRL
,
988 .modulemode
= MODULEMODE_SWCTRL
,
993 struct omap_hwmod_ocp_if dm816x_alwon_l3_fast__tptc1
= {
994 .master
= &dm816x_alwon_l3_fast_hwmod
,
995 .slave
= &dm816x_tptc1_hwmod
,
997 .addr
= dm816x_tptc1_addr_space
,
998 .user
= OCP_USER_MPU
,
1001 struct omap_hwmod_ocp_if dm816x_tptc1__alwon_l3_fast
= {
1002 .master
= &dm816x_tptc1_hwmod
,
1003 .slave
= &dm816x_alwon_l3_fast_hwmod
,
1004 .clk
= "sysclk4_ck",
1005 .addr
= dm816x_tptc1_addr_space
,
1006 .user
= OCP_USER_MPU
,
1009 static struct omap_hwmod_addr_space dm816x_tptc2_addr_space
[] = {
1011 .pa_start
= 0x49a00000,
1012 .pa_end
= 0x49a00000 + SZ_8K
- 1,
1013 .flags
= ADDR_TYPE_RT
,
1018 static struct omap_hwmod_class dm816x_tptc2_hwmod_class
= {
1022 struct omap_hwmod dm816x_tptc2_hwmod
= {
1024 .class = &dm816x_tptc2_hwmod_class
,
1025 .clkdm_name
= "alwon_l3s_clkdm",
1026 .main_clk
= "sysclk4_ck",
1029 .clkctrl_offs
= DM816X_CM_ALWON_TPTC2_CLKCTRL
,
1030 .modulemode
= MODULEMODE_SWCTRL
,
1035 struct omap_hwmod_ocp_if dm816x_alwon_l3_fast__tptc2
= {
1036 .master
= &dm816x_alwon_l3_fast_hwmod
,
1037 .slave
= &dm816x_tptc2_hwmod
,
1038 .clk
= "sysclk4_ck",
1039 .addr
= dm816x_tptc2_addr_space
,
1040 .user
= OCP_USER_MPU
,
1043 struct omap_hwmod_ocp_if dm816x_tptc2__alwon_l3_fast
= {
1044 .master
= &dm816x_tptc2_hwmod
,
1045 .slave
= &dm816x_alwon_l3_fast_hwmod
,
1046 .clk
= "sysclk4_ck",
1047 .addr
= dm816x_tptc2_addr_space
,
1048 .user
= OCP_USER_MPU
,
1051 static struct omap_hwmod_addr_space dm816x_tptc3_addr_space
[] = {
1053 .pa_start
= 0x49b00000,
1054 .pa_end
= 0x49b00000 + SZ_8K
- 1,
1055 .flags
= ADDR_TYPE_RT
,
1060 static struct omap_hwmod_class dm816x_tptc3_hwmod_class
= {
1064 struct omap_hwmod dm816x_tptc3_hwmod
= {
1066 .class = &dm816x_tptc3_hwmod_class
,
1067 .clkdm_name
= "alwon_l3s_clkdm",
1068 .main_clk
= "sysclk4_ck",
1071 .clkctrl_offs
= DM816X_CM_ALWON_TPTC3_CLKCTRL
,
1072 .modulemode
= MODULEMODE_SWCTRL
,
1077 struct omap_hwmod_ocp_if dm816x_alwon_l3_fast__tptc3
= {
1078 .master
= &dm816x_alwon_l3_fast_hwmod
,
1079 .slave
= &dm816x_tptc3_hwmod
,
1080 .clk
= "sysclk4_ck",
1081 .addr
= dm816x_tptc3_addr_space
,
1082 .user
= OCP_USER_MPU
,
1085 struct omap_hwmod_ocp_if dm816x_tptc3__alwon_l3_fast
= {
1086 .master
= &dm816x_tptc3_hwmod
,
1087 .slave
= &dm816x_alwon_l3_fast_hwmod
,
1088 .clk
= "sysclk4_ck",
1089 .addr
= dm816x_tptc3_addr_space
,
1090 .user
= OCP_USER_MPU
,
1093 static struct omap_hwmod_ocp_if
*dm816x_hwmod_ocp_ifs
[] __initdata
= {
1094 &dm816x_mpu__alwon_l3_slow
,
1095 &dm816x_mpu__alwon_l3_med
,
1096 &dm816x_alwon_l3_slow__l4_ls
,
1097 &dm816x_alwon_l3_slow__l4_hs
,
1098 &dm816x_l4_ls__uart1
,
1099 &dm816x_l4_ls__uart2
,
1100 &dm816x_l4_ls__uart3
,
1101 &dm816x_l4_ls__wd_timer1
,
1102 &dm816x_l4_ls__i2c1
,
1103 &dm816x_l4_ls__i2c2
,
1104 &dm81xx_l4_ls__gpio1
,
1105 &dm81xx_l4_ls__gpio2
,
1107 &dm816x_l4_ls__mmc1
,
1108 &dm816x_l4_ls__timer1
,
1109 &dm816x_l4_ls__timer2
,
1110 &dm816x_l4_ls__timer3
,
1111 &dm816x_l4_ls__timer4
,
1112 &dm816x_l4_ls__timer5
,
1113 &dm816x_l4_ls__timer6
,
1114 &dm816x_l4_ls__timer7
,
1115 &dm816x_l4_ls__mcspi1
,
1116 &dm816x_l4_ls__mailbox
,
1117 &dm816x_l4_hs__emac0
,
1118 &dm816x_emac0__mdio
,
1119 &dm816x_l4_hs__emac1
,
1120 &dm816x_alwon_l3_fast__tpcc
,
1121 &dm816x_alwon_l3_fast__tptc0
,
1122 &dm816x_alwon_l3_fast__tptc1
,
1123 &dm816x_alwon_l3_fast__tptc2
,
1124 &dm816x_alwon_l3_fast__tptc3
,
1125 &dm816x_tptc0__alwon_l3_fast
,
1126 &dm816x_tptc1__alwon_l3_fast
,
1127 &dm816x_tptc2__alwon_l3_fast
,
1128 &dm816x_tptc3__alwon_l3_fast
,
1129 &dm81xx_alwon_l3_slow__gpmc
,
1130 &dm81xx_default_l3_slow__usbss
,
1134 int __init
ti81xx_hwmod_init(void)
1137 return omap_hwmod_register_links(dm816x_hwmod_ocp_ifs
);