arch/arm/mach-omap2/omap_hwmod_81xx_data.c

   1 /*
   2  * DM81xx hwmod data.
   3  *
   4  * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
   5  * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/platform_data/gpio-omap.h>
  19 #include <linux/platform_data/hsmmc-omap.h>
  20 #include <linux/platform_data/spi-omap2-mcspi.h>
  21 #include <plat/dmtimer.h>
  22
  23 #include "omap_hwmod_common_data.h"
  24 #include "cm81xx.h"
  25 #include "ti81xx.h"
  26 #include "wd_timer.h"
  27
  28 /*
  29  * DM816X hardware modules integration data
  30  *
  31  * Note: This is incomplete and at present, not generated from h/w database.
  32  */
  33
  34 /*
  35  * Common alwon .clkctrl_offs from dm814x TRM "Table 2-278. CM_ALWON REGISTERS"
  36  * also dm816x TRM 18.7.17 CM_ALWON device register values minus 0x1400.
  37  */
  38 #define DM81XX_CM_ALWON_MCASP0_CLKCTRL          0x140
  39 #define DM81XX_CM_ALWON_MCASP1_CLKCTRL          0x144
  40 #define DM81XX_CM_ALWON_MCASP2_CLKCTRL          0x148
  41 #define DM81XX_CM_ALWON_MCBSP_CLKCTRL           0x14c
  42 #define DM81XX_CM_ALWON_UART_0_CLKCTRL          0x150
  43 #define DM81XX_CM_ALWON_UART_1_CLKCTRL          0x154
  44 #define DM81XX_CM_ALWON_UART_2_CLKCTRL          0x158
  45 #define DM81XX_CM_ALWON_GPIO_0_CLKCTRL          0x15c
  46 #define DM81XX_CM_ALWON_GPIO_1_CLKCTRL          0x160
  47 #define DM81XX_CM_ALWON_I2C_0_CLKCTRL           0x164
  48 #define DM81XX_CM_ALWON_I2C_1_CLKCTRL           0x168
  49 #define DM81XX_CM_ALWON_WDTIMER_CLKCTRL         0x18c
  50 #define DM81XX_CM_ALWON_SPI_CLKCTRL             0x190
  51 #define DM81XX_CM_ALWON_MAILBOX_CLKCTRL         0x194
  52 #define DM81XX_CM_ALWON_SPINBOX_CLKCTRL         0x198
  53 #define DM81XX_CM_ALWON_MMUDATA_CLKCTRL         0x19c
  54 #define DM81XX_CM_ALWON_MMUCFG_CLKCTRL          0x1a8
  55 #define DM81XX_CM_ALWON_CONTROL_CLKCTRL         0x1c4
  56 #define DM81XX_CM_ALWON_GPMC_CLKCTRL            0x1d0
  57 #define DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL      0x1d4
  58 #define DM81XX_CM_ALWON_L3_CLKCTRL              0x1e4
  59 #define DM81XX_CM_ALWON_L4HS_CLKCTRL            0x1e8
  60 #define DM81XX_CM_ALWON_L4LS_CLKCTRL            0x1ec
  61 #define DM81XX_CM_ALWON_RTC_CLKCTRL             0x1f0
  62 #define DM81XX_CM_ALWON_TPCC_CLKCTRL            0x1f4
  63 #define DM81XX_CM_ALWON_TPTC0_CLKCTRL           0x1f8
  64 #define DM81XX_CM_ALWON_TPTC1_CLKCTRL           0x1fc
  65 #define DM81XX_CM_ALWON_TPTC2_CLKCTRL           0x200
  66 #define DM81XX_CM_ALWON_TPTC3_CLKCTRL           0x204
  67
  68 /* Registers specific to dm814x */
  69 #define DM814X_CM_ALWON_MCASP_3_4_5_CLKCTRL     0x16c
  70 #define DM814X_CM_ALWON_ATL_CLKCTRL             0x170
  71 #define DM814X_CM_ALWON_MLB_CLKCTRL             0x174
  72 #define DM814X_CM_ALWON_PATA_CLKCTRL            0x178
  73 #define DM814X_CM_ALWON_UART_3_CLKCTRL          0x180
  74 #define DM814X_CM_ALWON_UART_4_CLKCTRL          0x184
  75 #define DM814X_CM_ALWON_UART_5_CLKCTRL          0x188
  76 #define DM814X_CM_ALWON_OCM_0_CLKCTRL           0x1b4
  77 #define DM814X_CM_ALWON_VCP_CLKCTRL             0x1b8
  78 #define DM814X_CM_ALWON_MPU_CLKCTRL             0x1dc
  79 #define DM814X_CM_ALWON_DEBUGSS_CLKCTRL         0x1e0
  80 #define DM814X_CM_ALWON_DCAN_0_1_CLKCTRL        0x218
  81 #define DM814X_CM_ALWON_MMCHS_0_CLKCTRL         0x21c
  82 #define DM814X_CM_ALWON_MMCHS_1_CLKCTRL         0x220
  83 #define DM814X_CM_ALWON_MMCHS_2_CLKCTRL         0x224
  84 #define DM814X_CM_ALWON_CUST_EFUSE_CLKCTRL      0x228
  85
  86 /* Registers specific to dm816x */
  87 #define DM816X_DM_ALWON_BASE            0x1400
  88 #define DM816X_CM_ALWON_TIMER_1_CLKCTRL (0x1570 - DM816X_DM_ALWON_BASE)
  89 #define DM816X_CM_ALWON_TIMER_2_CLKCTRL (0x1574 - DM816X_DM_ALWON_BASE)
  90 #define DM816X_CM_ALWON_TIMER_3_CLKCTRL (0x1578 - DM816X_DM_ALWON_BASE)
  91 #define DM816X_CM_ALWON_TIMER_4_CLKCTRL (0x157c - DM816X_DM_ALWON_BASE)
  92 #define DM816X_CM_ALWON_TIMER_5_CLKCTRL (0x1580 - DM816X_DM_ALWON_BASE)
  93 #define DM816X_CM_ALWON_TIMER_6_CLKCTRL (0x1584 - DM816X_DM_ALWON_BASE)
  94 #define DM816X_CM_ALWON_TIMER_7_CLKCTRL (0x1588 - DM816X_DM_ALWON_BASE)
  95 #define DM816X_CM_ALWON_SDIO_CLKCTRL    (0x15b0 - DM816X_DM_ALWON_BASE)
  96 #define DM816X_CM_ALWON_OCMC_0_CLKCTRL  (0x15b4 - DM816X_DM_ALWON_BASE)
  97 #define DM816X_CM_ALWON_OCMC_1_CLKCTRL  (0x15b8 - DM816X_DM_ALWON_BASE)
  98 #define DM816X_CM_ALWON_ETHERNET_1_CLKCTRL (0x15d8 - DM816X_DM_ALWON_BASE)
  99 #define DM816X_CM_ALWON_MPU_CLKCTRL     (0x15dc - DM816X_DM_ALWON_BASE)
 100 #define DM816X_CM_ALWON_SR_0_CLKCTRL    (0x1608 - DM816X_DM_ALWON_BASE)
 101 #define DM816X_CM_ALWON_SR_1_CLKCTRL    (0x160c - DM816X_DM_ALWON_BASE)
 102
 103 /*
 104  * The default .clkctrl_offs field is offset from CM_DEFAULT, that's
 105  * TRM 18.7.6 CM_DEFAULT device register values minus 0x500
 106  */
 107 #define DM81XX_CM_DEFAULT_OFFSET        0x500
 108 #define DM81XX_CM_DEFAULT_USB_CLKCTRL   (0x558 - DM81XX_CM_DEFAULT_OFFSET)
 109
 110 /* L3 Interconnect entries clocked at 125, 250 and 500MHz */
 111 static struct omap_hwmod dm81xx_alwon_l3_slow_hwmod = {
 112         .name           = "alwon_l3_slow",
 113         .clkdm_name     = "alwon_l3s_clkdm",
 114         .class          = &l3_hwmod_class,
 115         .flags          = HWMOD_NO_IDLEST,
 116 };
 117
 118 static struct omap_hwmod dm81xx_default_l3_slow_hwmod = {
 119         .name           = "default_l3_slow",
 120         .clkdm_name     = "default_l3_slow_clkdm",
 121         .class          = &l3_hwmod_class,
 122         .flags          = HWMOD_NO_IDLEST,
 123 };
 124
 125 static struct omap_hwmod dm81xx_alwon_l3_med_hwmod = {
 126         .name           = "l3_med",
 127         .clkdm_name     = "alwon_l3_med_clkdm",
 128         .class          = &l3_hwmod_class,
 129         .flags          = HWMOD_NO_IDLEST,
 130 };
 131
 132 static struct omap_hwmod dm81xx_alwon_l3_fast_hwmod = {
 133         .name           = "l3_fast",
 134         .clkdm_name     = "alwon_l3_fast_clkdm",
 135         .class          = &l3_hwmod_class,
 136         .flags          = HWMOD_NO_IDLEST,
 137 };
 138
 139 /*
 140  * L4 standard peripherals, see TRM table 1-12 for devices using this.
 141  * See TRM table 1-73 for devices using the 125MHz SYSCLK6 clock.
 142  */
 143 static struct omap_hwmod dm81xx_l4_ls_hwmod = {
 144         .name           = "l4_ls",
 145         .clkdm_name     = "alwon_l3s_clkdm",
 146         .class          = &l4_hwmod_class,
 147         .flags          = HWMOD_NO_IDLEST,
 148 };
 149
 150 /*
 151  * L4 high-speed peripherals. For devices using this, please see the TRM
 152  * table 1-13. On dm816x, only EMAC, MDIO and SATA use this. See also TRM
 153  * table 1-73 for devices using 250MHz SYSCLK5 clock.
 154  */
 155 static struct omap_hwmod dm81xx_l4_hs_hwmod = {
 156         .name           = "l4_hs",
 157         .clkdm_name     = "alwon_l3_med_clkdm",
 158         .class          = &l4_hwmod_class,
 159         .flags          = HWMOD_NO_IDLEST,
 160 };
 161
 162 /* L3 slow -> L4 ls peripheral interface running at 125MHz */
 163 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_ls = {
 164         .master = &dm81xx_alwon_l3_slow_hwmod,
 165         .slave  = &dm81xx_l4_ls_hwmod,
 166         .user   = OCP_USER_MPU,
 167 };
 168
 169 /* L3 med -> L4 fast peripheral interface running at 250MHz */
 170 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_hs = {
 171         .master = &dm81xx_alwon_l3_med_hwmod,
 172         .slave  = &dm81xx_l4_hs_hwmod,
 173         .user   = OCP_USER_MPU,
 174 };
 175
 176 /* MPU */
 177 static struct omap_hwmod dm814x_mpu_hwmod = {
 178         .name           = "mpu",
 179         .clkdm_name     = "alwon_l3s_clkdm",
 180         .class          = &mpu_hwmod_class,
 181         .flags          = HWMOD_INIT_NO_IDLE,
 182         .main_clk       = "mpu_ck",
 183         .prcm           = {
 184                 .omap4 = {
 185                         .clkctrl_offs = DM814X_CM_ALWON_MPU_CLKCTRL,
 186                         .modulemode = MODULEMODE_SWCTRL,
 187                 },
 188         },
 189 };
 190
 191 static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_slow = {
 192         .master         = &dm814x_mpu_hwmod,
 193         .slave          = &dm81xx_alwon_l3_slow_hwmod,
 194         .user           = OCP_USER_MPU,
 195 };
 196
 197 /* L3 med peripheral interface running at 200MHz */
 198 static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_med = {
 199         .master = &dm814x_mpu_hwmod,
 200         .slave  = &dm81xx_alwon_l3_med_hwmod,
 201         .user   = OCP_USER_MPU,
 202 };
 203
 204 static struct omap_hwmod dm816x_mpu_hwmod = {
 205         .name           = "mpu",
 206         .clkdm_name     = "alwon_mpu_clkdm",
 207         .class          = &mpu_hwmod_class,
 208         .flags          = HWMOD_INIT_NO_IDLE,
 209         .main_clk       = "mpu_ck",
 210         .prcm           = {
 211                 .omap4 = {
 212                         .clkctrl_offs = DM816X_CM_ALWON_MPU_CLKCTRL,
 213                         .modulemode = MODULEMODE_SWCTRL,
 214                 },
 215         },
 216 };
 217
 218 static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_slow = {
 219         .master         = &dm816x_mpu_hwmod,
 220         .slave          = &dm81xx_alwon_l3_slow_hwmod,
 221         .user           = OCP_USER_MPU,
 222 };
 223
 224 /* L3 med peripheral interface running at 250MHz */
 225 static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_med = {
 226         .master = &dm816x_mpu_hwmod,
 227         .slave  = &dm81xx_alwon_l3_med_hwmod,
 228         .user   = OCP_USER_MPU,
 229 };
 230
 231 /* RTC */
 232 static struct omap_hwmod_class_sysconfig ti81xx_rtc_sysc = {
 233         .rev_offs       = 0x74,
 234         .sysc_offs      = 0x78,
 235         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 236         .idlemodes      = SIDLE_FORCE | SIDLE_NO |
 237                           SIDLE_SMART | SIDLE_SMART_WKUP,
 238         .sysc_fields    = &omap_hwmod_sysc_type3,
 239 };
 240
 241 static struct omap_hwmod_class ti81xx_rtc_hwmod_class = {
 242         .name           = "rtc",
 243         .sysc           = &ti81xx_rtc_sysc,
 244 };
 245
 246 struct omap_hwmod ti81xx_rtc_hwmod = {
 247         .name           = "rtc",
 248         .class          = &ti81xx_rtc_hwmod_class,
 249         .clkdm_name     = "alwon_l3s_clkdm",
 250         .flags          = HWMOD_NO_IDLEST,
 251         .main_clk       = "sysclk18_ck",
 252         .prcm           = {
 253                 .omap4  = {
 254                         .clkctrl_offs = DM81XX_CM_ALWON_RTC_CLKCTRL,
 255                         .modulemode = MODULEMODE_SWCTRL,
 256                 },
 257         },
 258 };
 259
 260 static struct omap_hwmod_ocp_if ti81xx_l4_ls__rtc = {
 261         .master         = &dm81xx_l4_ls_hwmod,
 262         .slave          = &ti81xx_rtc_hwmod,
 263         .clk            = "sysclk6_ck",
 264         .user           = OCP_USER_MPU,
 265 };
 266
 267 /* UART common */
 268 static struct omap_hwmod_class_sysconfig uart_sysc = {
 269         .rev_offs       = 0x50,
 270         .sysc_offs      = 0x54,
 271         .syss_offs      = 0x58,
 272         .sysc_flags     = SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 273                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 274                                 SYSS_HAS_RESET_STATUS,
 275         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 276                                 MSTANDBY_SMART_WKUP,
 277         .sysc_fields    = &omap_hwmod_sysc_type1,
 278 };
 279
 280 static struct omap_hwmod_class uart_class = {
 281         .name = "uart",
 282         .sysc = &uart_sysc,
 283 };
 284
 285 static struct omap_hwmod dm81xx_uart1_hwmod = {
 286         .name           = "uart1",
 287         .clkdm_name     = "alwon_l3s_clkdm",
 288         .main_clk       = "sysclk10_ck",
 289         .prcm           = {
 290                 .omap4 = {
 291                         .clkctrl_offs = DM81XX_CM_ALWON_UART_0_CLKCTRL,
 292                         .modulemode = MODULEMODE_SWCTRL,
 293                 },
 294         },
 295         .class          = &uart_class,
 296         .flags          = DEBUG_TI81XXUART1_FLAGS,
 297 };
 298
 299 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart1 = {
 300         .master         = &dm81xx_l4_ls_hwmod,
 301         .slave          = &dm81xx_uart1_hwmod,
 302         .clk            = "sysclk6_ck",
 303         .user           = OCP_USER_MPU,
 304 };
 305
 306 static struct omap_hwmod dm81xx_uart2_hwmod = {
 307         .name           = "uart2",
 308         .clkdm_name     = "alwon_l3s_clkdm",
 309         .main_clk       = "sysclk10_ck",
 310         .prcm           = {
 311                 .omap4 = {
 312                         .clkctrl_offs = DM81XX_CM_ALWON_UART_1_CLKCTRL,
 313                         .modulemode = MODULEMODE_SWCTRL,
 314                 },
 315         },
 316         .class          = &uart_class,
 317         .flags          = DEBUG_TI81XXUART2_FLAGS,
 318 };
 319
 320 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart2 = {
 321         .master         = &dm81xx_l4_ls_hwmod,
 322         .slave          = &dm81xx_uart2_hwmod,
 323         .clk            = "sysclk6_ck",
 324         .user           = OCP_USER_MPU,
 325 };
 326
 327 static struct omap_hwmod dm81xx_uart3_hwmod = {
 328         .name           = "uart3",
 329         .clkdm_name     = "alwon_l3s_clkdm",
 330         .main_clk       = "sysclk10_ck",
 331         .prcm           = {
 332                 .omap4 = {
 333                         .clkctrl_offs = DM81XX_CM_ALWON_UART_2_CLKCTRL,
 334                         .modulemode = MODULEMODE_SWCTRL,
 335                 },
 336         },
 337         .class          = &uart_class,
 338         .flags          = DEBUG_TI81XXUART3_FLAGS,
 339 };
 340
 341 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart3 = {
 342         .master         = &dm81xx_l4_ls_hwmod,
 343         .slave          = &dm81xx_uart3_hwmod,
 344         .clk            = "sysclk6_ck",
 345         .user           = OCP_USER_MPU,
 346 };
 347
 348 static struct omap_hwmod_class_sysconfig wd_timer_sysc = {
 349         .rev_offs       = 0x0,
 350         .sysc_offs      = 0x10,
 351         .syss_offs      = 0x14,
 352         .sysc_flags     = SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
 353                                 SYSS_HAS_RESET_STATUS,
 354         .sysc_fields    = &omap_hwmod_sysc_type1,
 355 };
 356
 357 static struct omap_hwmod_class wd_timer_class = {
 358         .name           = "wd_timer",
 359         .sysc           = &wd_timer_sysc,
 360         .pre_shutdown   = &omap2_wd_timer_disable,
 361         .reset          = &omap2_wd_timer_reset,
 362 };
 363
 364 static struct omap_hwmod dm81xx_wd_timer_hwmod = {
 365         .name           = "wd_timer",
 366         .clkdm_name     = "alwon_l3s_clkdm",
 367         .main_clk       = "sysclk18_ck",
 368         .flags          = HWMOD_NO_IDLEST,
 369         .prcm           = {
 370                 .omap4 = {
 371                         .clkctrl_offs = DM81XX_CM_ALWON_WDTIMER_CLKCTRL,
 372                         .modulemode = MODULEMODE_SWCTRL,
 373                 },
 374         },
 375         .class          = &wd_timer_class,
 376 };
 377
 378 static struct omap_hwmod_ocp_if dm81xx_l4_ls__wd_timer1 = {
 379         .master         = &dm81xx_l4_ls_hwmod,
 380         .slave          = &dm81xx_wd_timer_hwmod,
 381         .clk            = "sysclk6_ck",
 382         .user           = OCP_USER_MPU,
 383 };
 384
 385 /* I2C common */
 386 static struct omap_hwmod_class_sysconfig i2c_sysc = {
 387         .rev_offs       = 0x0,
 388         .sysc_offs      = 0x10,
 389         .syss_offs      = 0x90,
 390         .sysc_flags     = SYSC_HAS_SIDLEMODE |
 391                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 392                                 SYSC_HAS_AUTOIDLE,
 393         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
 394         .sysc_fields    = &omap_hwmod_sysc_type1,
 395 };
 396
 397 static struct omap_hwmod_class i2c_class = {
 398         .name = "i2c",
 399         .sysc = &i2c_sysc,
 400 };
 401
 402 static struct omap_hwmod dm81xx_i2c1_hwmod = {
 403         .name           = "i2c1",
 404         .clkdm_name     = "alwon_l3s_clkdm",
 405         .main_clk       = "sysclk10_ck",
 406         .prcm           = {
 407                 .omap4 = {
 408                         .clkctrl_offs = DM81XX_CM_ALWON_I2C_0_CLKCTRL,
 409                         .modulemode = MODULEMODE_SWCTRL,
 410                 },
 411         },
 412         .class          = &i2c_class,
 413 };
 414
 415 static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c1 = {
 416         .master         = &dm81xx_l4_ls_hwmod,
 417         .slave          = &dm81xx_i2c1_hwmod,
 418         .clk            = "sysclk6_ck",
 419         .user           = OCP_USER_MPU,
 420 };
 421
 422 static struct omap_hwmod dm81xx_i2c2_hwmod = {
 423         .name           = "i2c2",
 424         .clkdm_name     = "alwon_l3s_clkdm",
 425         .main_clk       = "sysclk10_ck",
 426         .prcm           = {
 427                 .omap4 = {
 428                         .clkctrl_offs = DM81XX_CM_ALWON_I2C_1_CLKCTRL,
 429                         .modulemode = MODULEMODE_SWCTRL,
 430                 },
 431         },
 432         .class          = &i2c_class,
 433 };
 434
 435 static struct omap_hwmod_class_sysconfig dm81xx_elm_sysc = {
 436         .rev_offs       = 0x0000,
 437         .sysc_offs      = 0x0010,
 438         .syss_offs      = 0x0014,
 439         .sysc_flags     = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 440                                 SYSC_HAS_SOFTRESET |
 441                                 SYSS_HAS_RESET_STATUS,
 442         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
 443         .sysc_fields    = &omap_hwmod_sysc_type1,
 444 };
 445
 446 static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c2 = {
 447         .master         = &dm81xx_l4_ls_hwmod,
 448         .slave          = &dm81xx_i2c2_hwmod,
 449         .clk            = "sysclk6_ck",
 450         .user           = OCP_USER_MPU,
 451 };
 452
 453 static struct omap_hwmod_class dm81xx_elm_hwmod_class = {
 454         .name = "elm",
 455         .sysc = &dm81xx_elm_sysc,
 456 };
 457
 458 static struct omap_hwmod dm81xx_elm_hwmod = {
 459         .name           = "elm",
 460         .clkdm_name     = "alwon_l3s_clkdm",
 461         .class          = &dm81xx_elm_hwmod_class,
 462         .main_clk       = "sysclk6_ck",
 463 };
 464
 465 static struct omap_hwmod_ocp_if dm81xx_l4_ls__elm = {
 466         .master         = &dm81xx_l4_ls_hwmod,
 467         .slave          = &dm81xx_elm_hwmod,
 468         .user           = OCP_USER_MPU,
 469 };
 470
 471 static struct omap_hwmod_class_sysconfig dm81xx_gpio_sysc = {
 472         .rev_offs       = 0x0000,
 473         .sysc_offs      = 0x0010,
 474         .syss_offs      = 0x0114,
 475         .sysc_flags     = SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 476                                 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 477                                 SYSS_HAS_RESET_STATUS,
 478         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 479                                 SIDLE_SMART_WKUP,
 480         .sysc_fields    = &omap_hwmod_sysc_type1,
 481 };
 482
 483 static struct omap_hwmod_class dm81xx_gpio_hwmod_class = {
 484         .name   = "gpio",
 485         .sysc   = &dm81xx_gpio_sysc,
 486         .rev    = 2,
 487 };
 488
 489 static struct omap_gpio_dev_attr gpio_dev_attr = {
 490         .bank_width     = 32,
 491         .dbck_flag      = true,
 492 };
 493
 494 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 495         { .role = "dbclk", .clk = "sysclk18_ck" },
 496 };
 497
 498 static struct omap_hwmod dm81xx_gpio1_hwmod = {
 499         .name           = "gpio1",
 500         .clkdm_name     = "alwon_l3s_clkdm",
 501         .class          = &dm81xx_gpio_hwmod_class,
 502         .main_clk       = "sysclk6_ck",
 503         .prcm = {
 504                 .omap4 = {
 505                         .clkctrl_offs = DM81XX_CM_ALWON_GPIO_0_CLKCTRL,
 506                         .modulemode = MODULEMODE_SWCTRL,
 507                 },
 508         },
 509         .opt_clks       = gpio1_opt_clks,
 510         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 511         .dev_attr       = &gpio_dev_attr,
 512 };
 513
 514 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio1 = {
 515         .master         = &dm81xx_l4_ls_hwmod,
 516         .slave          = &dm81xx_gpio1_hwmod,
 517         .user           = OCP_USER_MPU,
 518 };
 519
 520 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 521         { .role = "dbclk", .clk = "sysclk18_ck" },
 522 };
 523
 524 static struct omap_hwmod dm81xx_gpio2_hwmod = {
 525         .name           = "gpio2",
 526         .clkdm_name     = "alwon_l3s_clkdm",
 527         .class          = &dm81xx_gpio_hwmod_class,
 528         .main_clk       = "sysclk6_ck",
 529         .prcm = {
 530                 .omap4 = {
 531                         .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL,
 532                         .modulemode = MODULEMODE_SWCTRL,
 533                 },
 534         },
 535         .opt_clks       = gpio2_opt_clks,
 536         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 537         .dev_attr       = &gpio_dev_attr,
 538 };
 539
 540 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = {
 541         .master         = &dm81xx_l4_ls_hwmod,
 542         .slave          = &dm81xx_gpio2_hwmod,
 543         .user           = OCP_USER_MPU,
 544 };
 545
 546 static struct omap_hwmod_class_sysconfig dm81xx_gpmc_sysc = {
 547         .rev_offs       = 0x0,
 548         .sysc_offs      = 0x10,
 549         .syss_offs      = 0x14,
 550         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 551                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
 552         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
 553         .sysc_fields    = &omap_hwmod_sysc_type1,
 554 };
 555
 556 static struct omap_hwmod_class dm81xx_gpmc_hwmod_class = {
 557         .name   = "gpmc",
 558         .sysc   = &dm81xx_gpmc_sysc,
 559 };
 560
 561 static struct omap_hwmod dm81xx_gpmc_hwmod = {
 562         .name           = "gpmc",
 563         .clkdm_name     = "alwon_l3s_clkdm",
 564         .class          = &dm81xx_gpmc_hwmod_class,
 565         .main_clk       = "sysclk6_ck",
 566         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
 567         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
 568         .prcm = {
 569                 .omap4 = {
 570                         .clkctrl_offs = DM81XX_CM_ALWON_GPMC_CLKCTRL,
 571                         .modulemode = MODULEMODE_SWCTRL,
 572                 },
 573         },
 574 };
 575
 576 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__gpmc = {
 577         .master         = &dm81xx_alwon_l3_slow_hwmod,
 578         .slave          = &dm81xx_gpmc_hwmod,
 579         .user           = OCP_USER_MPU,
 580 };
 581
 582 static struct omap_hwmod_class_sysconfig dm81xx_usbhsotg_sysc = {
 583         .rev_offs       = 0x0,
 584         .sysc_offs      = 0x10,
 585         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 586                                 SYSC_HAS_SOFTRESET,
 587         .idlemodes      = SIDLE_SMART | MSTANDBY_FORCE | MSTANDBY_SMART,
 588         .sysc_fields    = &omap_hwmod_sysc_type2,
 589 };
 590
 591 static struct omap_hwmod_class dm81xx_usbotg_class = {
 592         .name = "usbotg",
 593         .sysc = &dm81xx_usbhsotg_sysc,
 594 };
 595
 596 static struct omap_hwmod dm814x_usbss_hwmod = {
 597         .name           = "usb_otg_hs",
 598         .clkdm_name     = "default_l3_slow_clkdm",
 599         .main_clk       = "pll260dcoclkldo",    /* 481c5260.adpll.dcoclkldo */
 600         .prcm           = {
 601                 .omap4 = {
 602                         .clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL,
 603                         .modulemode = MODULEMODE_SWCTRL,
 604                 },
 605         },
 606         .class          = &dm81xx_usbotg_class,
 607 };
 608
 609 static struct omap_hwmod_ocp_if dm814x_default_l3_slow__usbss = {
 610         .master         = &dm81xx_default_l3_slow_hwmod,
 611         .slave          = &dm814x_usbss_hwmod,
 612         .clk            = "sysclk6_ck",
 613         .user           = OCP_USER_MPU,
 614 };
 615
 616 static struct omap_hwmod dm816x_usbss_hwmod = {
 617         .name           = "usb_otg_hs",
 618         .clkdm_name     = "default_l3_slow_clkdm",
 619         .main_clk       = "sysclk6_ck",
 620         .prcm           = {
 621                 .omap4 = {
 622                         .clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL,
 623                         .modulemode = MODULEMODE_SWCTRL,
 624                 },
 625         },
 626         .class          = &dm81xx_usbotg_class,
 627 };
 628
 629 static struct omap_hwmod_ocp_if dm816x_default_l3_slow__usbss = {
 630         .master         = &dm81xx_default_l3_slow_hwmod,
 631         .slave          = &dm816x_usbss_hwmod,
 632         .clk            = "sysclk6_ck",
 633         .user           = OCP_USER_MPU,
 634 };
 635
 636 static struct omap_hwmod_class_sysconfig dm816x_timer_sysc = {
 637         .rev_offs       = 0x0000,
 638         .sysc_offs      = 0x0010,
 639         .syss_offs      = 0x0014,
 640         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET,
 641         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 642                                 SIDLE_SMART_WKUP,
 643         .sysc_fields    = &omap_hwmod_sysc_type2,
 644 };
 645
 646 static struct omap_hwmod_class dm816x_timer_hwmod_class = {
 647         .name = "timer",
 648         .sysc = &dm816x_timer_sysc,
 649 };
 650
 651 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 652         .timer_capability       = OMAP_TIMER_ALWON,
 653 };
 654
 655 static struct omap_hwmod dm814x_timer1_hwmod = {
 656         .name           = "timer1",
 657         .clkdm_name     = "alwon_l3s_clkdm",
 658         .main_clk       = "timer1_fck",
 659         .dev_attr       = &capability_alwon_dev_attr,
 660         .class          = &dm816x_timer_hwmod_class,
 661         .flags          = HWMOD_NO_IDLEST,
 662 };
 663
 664 static struct omap_hwmod_ocp_if dm814x_l4_ls__timer1 = {
 665         .master         = &dm81xx_l4_ls_hwmod,
 666         .slave          = &dm814x_timer1_hwmod,
 667         .clk            = "timer1_fck",
 668         .user           = OCP_USER_MPU,
 669 };
 670
 671 static struct omap_hwmod dm816x_timer1_hwmod = {
 672         .name           = "timer1",
 673         .clkdm_name     = "alwon_l3s_clkdm",
 674         .main_clk       = "timer1_fck",
 675         .prcm           = {
 676                 .omap4 = {
 677                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_1_CLKCTRL,
 678                         .modulemode = MODULEMODE_SWCTRL,
 679                 },
 680         },
 681         .dev_attr       = &capability_alwon_dev_attr,
 682         .class          = &dm816x_timer_hwmod_class,
 683 };
 684
 685 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = {
 686         .master         = &dm81xx_l4_ls_hwmod,
 687         .slave          = &dm816x_timer1_hwmod,
 688         .clk            = "sysclk6_ck",
 689         .user           = OCP_USER_MPU,
 690 };
 691
 692 static struct omap_hwmod dm814x_timer2_hwmod = {
 693         .name           = "timer2",
 694         .clkdm_name     = "alwon_l3s_clkdm",
 695         .main_clk       = "timer2_fck",
 696         .dev_attr       = &capability_alwon_dev_attr,
 697         .class          = &dm816x_timer_hwmod_class,
 698         .flags          = HWMOD_NO_IDLEST,
 699 };
 700
 701 static struct omap_hwmod_ocp_if dm814x_l4_ls__timer2 = {
 702         .master         = &dm81xx_l4_ls_hwmod,
 703         .slave          = &dm814x_timer2_hwmod,
 704         .clk            = "timer2_fck",
 705         .user           = OCP_USER_MPU,
 706 };
 707
 708 static struct omap_hwmod dm816x_timer2_hwmod = {
 709         .name           = "timer2",
 710         .clkdm_name     = "alwon_l3s_clkdm",
 711         .main_clk       = "timer2_fck",
 712         .prcm           = {
 713                 .omap4 = {
 714                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_2_CLKCTRL,
 715                         .modulemode = MODULEMODE_SWCTRL,
 716                 },
 717         },
 718         .dev_attr       = &capability_alwon_dev_attr,
 719         .class          = &dm816x_timer_hwmod_class,
 720 };
 721
 722 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer2 = {
 723         .master         = &dm81xx_l4_ls_hwmod,
 724         .slave          = &dm816x_timer2_hwmod,
 725         .clk            = "sysclk6_ck",
 726         .user           = OCP_USER_MPU,
 727 };
 728
 729 static struct omap_hwmod dm816x_timer3_hwmod = {
 730         .name           = "timer3",
 731         .clkdm_name     = "alwon_l3s_clkdm",
 732         .main_clk       = "timer3_fck",
 733         .prcm           = {
 734                 .omap4 = {
 735                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_3_CLKCTRL,
 736                         .modulemode = MODULEMODE_SWCTRL,
 737                 },
 738         },
 739         .dev_attr       = &capability_alwon_dev_attr,
 740         .class          = &dm816x_timer_hwmod_class,
 741 };
 742
 743 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer3 = {
 744         .master         = &dm81xx_l4_ls_hwmod,
 745         .slave          = &dm816x_timer3_hwmod,
 746         .clk            = "sysclk6_ck",
 747         .user           = OCP_USER_MPU,
 748 };
 749
 750 static struct omap_hwmod dm816x_timer4_hwmod = {
 751         .name           = "timer4",
 752         .clkdm_name     = "alwon_l3s_clkdm",
 753         .main_clk       = "timer4_fck",
 754         .prcm           = {
 755                 .omap4 = {
 756                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_4_CLKCTRL,
 757                         .modulemode = MODULEMODE_SWCTRL,
 758                 },
 759         },
 760         .dev_attr       = &capability_alwon_dev_attr,
 761         .class          = &dm816x_timer_hwmod_class,
 762 };
 763
 764 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer4 = {
 765         .master         = &dm81xx_l4_ls_hwmod,
 766         .slave          = &dm816x_timer4_hwmod,
 767         .clk            = "sysclk6_ck",
 768         .user           = OCP_USER_MPU,
 769 };
 770
 771 static struct omap_hwmod dm816x_timer5_hwmod = {
 772         .name           = "timer5",
 773         .clkdm_name     = "alwon_l3s_clkdm",
 774         .main_clk       = "timer5_fck",
 775         .prcm           = {
 776                 .omap4 = {
 777                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_5_CLKCTRL,
 778                         .modulemode = MODULEMODE_SWCTRL,
 779                 },
 780         },
 781         .dev_attr       = &capability_alwon_dev_attr,
 782         .class          = &dm816x_timer_hwmod_class,
 783 };
 784
 785 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer5 = {
 786         .master         = &dm81xx_l4_ls_hwmod,
 787         .slave          = &dm816x_timer5_hwmod,
 788         .clk            = "sysclk6_ck",
 789         .user           = OCP_USER_MPU,
 790 };
 791
 792 static struct omap_hwmod dm816x_timer6_hwmod = {
 793         .name           = "timer6",
 794         .clkdm_name     = "alwon_l3s_clkdm",
 795         .main_clk       = "timer6_fck",
 796         .prcm           = {
 797                 .omap4 = {
 798                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_6_CLKCTRL,
 799                         .modulemode = MODULEMODE_SWCTRL,
 800                 },
 801         },
 802         .dev_attr       = &capability_alwon_dev_attr,
 803         .class          = &dm816x_timer_hwmod_class,
 804 };
 805
 806 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer6 = {
 807         .master         = &dm81xx_l4_ls_hwmod,
 808         .slave          = &dm816x_timer6_hwmod,
 809         .clk            = "sysclk6_ck",
 810         .user           = OCP_USER_MPU,
 811 };
 812
 813 static struct omap_hwmod dm816x_timer7_hwmod = {
 814         .name           = "timer7",
 815         .clkdm_name     = "alwon_l3s_clkdm",
 816         .main_clk       = "timer7_fck",
 817         .prcm           = {
 818                 .omap4 = {
 819                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_7_CLKCTRL,
 820                         .modulemode = MODULEMODE_SWCTRL,
 821                 },
 822         },
 823         .dev_attr       = &capability_alwon_dev_attr,
 824         .class          = &dm816x_timer_hwmod_class,
 825 };
 826
 827 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer7 = {
 828         .master         = &dm81xx_l4_ls_hwmod,
 829         .slave          = &dm816x_timer7_hwmod,
 830         .clk            = "sysclk6_ck",
 831         .user           = OCP_USER_MPU,
 832 };
 833
 834 /* CPSW on dm814x */
 835 static struct omap_hwmod_class_sysconfig dm814x_cpgmac_sysc = {
 836         .rev_offs       = 0x0,
 837         .sysc_offs      = 0x8,
 838         .syss_offs      = 0x4,
 839         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 840                           SYSS_HAS_RESET_STATUS,
 841         .idlemodes      = SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
 842                           MSTANDBY_NO,
 843         .sysc_fields    = &omap_hwmod_sysc_type3,
 844 };
 845
 846 static struct omap_hwmod_class dm814x_cpgmac0_hwmod_class = {
 847         .name           = "cpgmac0",
 848         .sysc           = &dm814x_cpgmac_sysc,
 849 };
 850
 851 static struct omap_hwmod dm814x_cpgmac0_hwmod = {
 852         .name           = "cpgmac0",
 853         .class          = &dm814x_cpgmac0_hwmod_class,
 854         .clkdm_name     = "alwon_ethernet_clkdm",
 855         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 856         .main_clk       = "cpsw_125mhz_gclk",
 857         .prcm           = {
 858                 .omap4  = {
 859                         .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL,
 860                         .modulemode = MODULEMODE_SWCTRL,
 861                 },
 862         },
 863 };
 864
 865 static struct omap_hwmod_class dm814x_mdio_hwmod_class = {
 866         .name           = "davinci_mdio",
 867 };
 868
 869 static struct omap_hwmod dm814x_mdio_hwmod = {
 870         .name           = "davinci_mdio",
 871         .class          = &dm814x_mdio_hwmod_class,
 872         .clkdm_name     = "alwon_ethernet_clkdm",
 873         .main_clk       = "cpsw_125mhz_gclk",
 874 };
 875
 876 static struct omap_hwmod_ocp_if dm814x_l4_hs__cpgmac0 = {
 877         .master         = &dm81xx_l4_hs_hwmod,
 878         .slave          = &dm814x_cpgmac0_hwmod,
 879         .clk            = "cpsw_125mhz_gclk",
 880         .user           = OCP_USER_MPU,
 881 };
 882
 883 static struct omap_hwmod_ocp_if dm814x_cpgmac0__mdio = {
 884         .master         = &dm814x_cpgmac0_hwmod,
 885         .slave          = &dm814x_mdio_hwmod,
 886         .user           = OCP_USER_MPU,
 887         .flags          = HWMOD_NO_IDLEST,
 888 };
 889
 890 /* EMAC Ethernet */
 891 static struct omap_hwmod_class_sysconfig dm816x_emac_sysc = {
 892         .rev_offs       = 0x0,
 893         .sysc_offs      = 0x4,
 894         .sysc_flags     = SYSC_HAS_SOFTRESET,
 895         .sysc_fields    = &omap_hwmod_sysc_type2,
 896 };
 897
 898 static struct omap_hwmod_class dm816x_emac_hwmod_class = {
 899         .name           = "emac",
 900         .sysc           = &dm816x_emac_sysc,
 901 };
 902
 903 /*
 904  * On dm816x the MDIO is within EMAC0. As the MDIO driver is a separate
 905  * driver probed before EMAC0, we let MDIO do the clock idling.
 906  */
 907 static struct omap_hwmod dm816x_emac0_hwmod = {
 908         .name           = "emac0",
 909         .clkdm_name     = "alwon_ethernet_clkdm",
 910         .class          = &dm816x_emac_hwmod_class,
 911         .flags          = HWMOD_NO_IDLEST,
 912 };
 913
 914 static struct omap_hwmod_ocp_if dm81xx_l4_hs__emac0 = {
 915         .master         = &dm81xx_l4_hs_hwmod,
 916         .slave          = &dm816x_emac0_hwmod,
 917         .clk            = "sysclk5_ck",
 918         .user           = OCP_USER_MPU,
 919 };
 920
 921 static struct omap_hwmod_class dm81xx_mdio_hwmod_class = {
 922         .name           = "davinci_mdio",
 923         .sysc           = &dm816x_emac_sysc,
 924 };
 925
 926 static struct omap_hwmod dm81xx_emac0_mdio_hwmod = {
 927         .name           = "davinci_mdio",
 928         .class          = &dm81xx_mdio_hwmod_class,
 929         .clkdm_name     = "alwon_ethernet_clkdm",
 930         .main_clk       = "sysclk24_ck",
 931         .flags          = HWMOD_NO_IDLEST,
 932         /*
 933          * REVISIT: This should be moved to the emac0_hwmod
 934          * once we have a better way to handle device slaves.
 935          */
 936         .prcm           = {
 937                 .omap4 = {
 938                         .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL,
 939                         .modulemode = MODULEMODE_SWCTRL,
 940                 },
 941         },
 942 };
 943
 944 static struct omap_hwmod_ocp_if dm81xx_emac0__mdio = {
 945         .master         = &dm81xx_l4_hs_hwmod,
 946         .slave          = &dm81xx_emac0_mdio_hwmod,
 947         .user           = OCP_USER_MPU,
 948 };
 949
 950 static struct omap_hwmod dm816x_emac1_hwmod = {
 951         .name           = "emac1",
 952         .clkdm_name     = "alwon_ethernet_clkdm",
 953         .main_clk       = "sysclk24_ck",
 954         .flags          = HWMOD_NO_IDLEST,
 955         .prcm           = {
 956                 .omap4 = {
 957                         .clkctrl_offs = DM816X_CM_ALWON_ETHERNET_1_CLKCTRL,
 958                         .modulemode = MODULEMODE_SWCTRL,
 959                 },
 960         },
 961         .class          = &dm816x_emac_hwmod_class,
 962 };
 963
 964 static struct omap_hwmod_ocp_if dm816x_l4_hs__emac1 = {
 965         .master         = &dm81xx_l4_hs_hwmod,
 966         .slave          = &dm816x_emac1_hwmod,
 967         .clk            = "sysclk5_ck",
 968         .user           = OCP_USER_MPU,
 969 };
 970
 971 static struct omap_hwmod_class_sysconfig dm81xx_mmc_sysc = {
 972         .rev_offs       = 0x0,
 973         .sysc_offs      = 0x110,
 974         .syss_offs      = 0x114,
 975         .sysc_flags     = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 976                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 977                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
 978         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
 979         .sysc_fields    = &omap_hwmod_sysc_type1,
 980 };
 981
 982 static struct omap_hwmod_class dm81xx_mmc_class = {
 983         .name = "mmc",
 984         .sysc = &dm81xx_mmc_sysc,
 985 };
 986
 987 static struct omap_hwmod_opt_clk dm81xx_mmc_opt_clks[] = {
 988         { .role = "dbck", .clk = "sysclk18_ck", },
 989 };
 990
 991 static struct omap_hsmmc_dev_attr mmc_dev_attr = {
 992 };
 993
 994 static struct omap_hwmod dm814x_mmc1_hwmod = {
 995         .name           = "mmc1",
 996         .clkdm_name     = "alwon_l3s_clkdm",
 997         .opt_clks       = dm81xx_mmc_opt_clks,
 998         .opt_clks_cnt   = ARRAY_SIZE(dm81xx_mmc_opt_clks),
 999         .main_clk       = "sysclk8_ck",
1000         .prcm           = {
1001                 .omap4 = {
1002                         .clkctrl_offs = DM814X_CM_ALWON_MMCHS_0_CLKCTRL,
1003                         .modulemode = MODULEMODE_SWCTRL,
1004                 },
1005         },
1006         .dev_attr       = &mmc_dev_attr,
1007         .class          = &dm81xx_mmc_class,
1008 };
1009
1010 static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc1 = {
1011         .master         = &dm81xx_l4_ls_hwmod,
1012         .slave          = &dm814x_mmc1_hwmod,
1013         .clk            = "sysclk6_ck",
1014         .user           = OCP_USER_MPU,
1015         .flags          = OMAP_FIREWALL_L4
1016 };
1017
1018 static struct omap_hwmod dm814x_mmc2_hwmod = {
1019         .name           = "mmc2",
1020         .clkdm_name     = "alwon_l3s_clkdm",
1021         .opt_clks       = dm81xx_mmc_opt_clks,
1022         .opt_clks_cnt   = ARRAY_SIZE(dm81xx_mmc_opt_clks),
1023         .main_clk       = "sysclk8_ck",
1024         .prcm           = {
1025                 .omap4 = {
1026                         .clkctrl_offs = DM814X_CM_ALWON_MMCHS_1_CLKCTRL,
1027                         .modulemode = MODULEMODE_SWCTRL,
1028                 },
1029         },
1030         .dev_attr       = &mmc_dev_attr,
1031         .class          = &dm81xx_mmc_class,
1032 };
1033
1034 static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc2 = {
1035         .master         = &dm81xx_l4_ls_hwmod,
1036         .slave          = &dm814x_mmc2_hwmod,
1037         .clk            = "sysclk6_ck",
1038         .user           = OCP_USER_MPU,
1039         .flags          = OMAP_FIREWALL_L4
1040 };
1041
1042 static struct omap_hwmod dm814x_mmc3_hwmod = {
1043         .name           = "mmc3",
1044         .clkdm_name     = "alwon_l3_med_clkdm",
1045         .opt_clks       = dm81xx_mmc_opt_clks,
1046         .opt_clks_cnt   = ARRAY_SIZE(dm81xx_mmc_opt_clks),
1047         .main_clk       = "sysclk8_ck",
1048         .prcm           = {
1049                 .omap4 = {
1050                         .clkctrl_offs = DM814X_CM_ALWON_MMCHS_2_CLKCTRL,
1051                         .modulemode = MODULEMODE_SWCTRL,
1052                 },
1053         },
1054         .dev_attr       = &mmc_dev_attr,
1055         .class          = &dm81xx_mmc_class,
1056 };
1057
1058 static struct omap_hwmod_ocp_if dm814x_alwon_l3_med__mmc3 = {
1059         .master         = &dm81xx_alwon_l3_med_hwmod,
1060         .slave          = &dm814x_mmc3_hwmod,
1061         .clk            = "sysclk4_ck",
1062         .user           = OCP_USER_MPU,
1063 };
1064
1065 static struct omap_hwmod dm816x_mmc1_hwmod = {
1066         .name           = "mmc1",
1067         .clkdm_name     = "alwon_l3s_clkdm",
1068         .opt_clks       = dm81xx_mmc_opt_clks,
1069         .opt_clks_cnt   = ARRAY_SIZE(dm81xx_mmc_opt_clks),
1070         .main_clk       = "sysclk10_ck",
1071         .prcm           = {
1072                 .omap4 = {
1073                         .clkctrl_offs = DM816X_CM_ALWON_SDIO_CLKCTRL,
1074                         .modulemode = MODULEMODE_SWCTRL,
1075                 },
1076         },
1077         .dev_attr       = &mmc_dev_attr,
1078         .class          = &dm81xx_mmc_class,
1079 };
1080
1081 static struct omap_hwmod_ocp_if dm816x_l4_ls__mmc1 = {
1082         .master         = &dm81xx_l4_ls_hwmod,
1083         .slave          = &dm816x_mmc1_hwmod,
1084         .clk            = "sysclk6_ck",
1085         .user           = OCP_USER_MPU,
1086         .flags          = OMAP_FIREWALL_L4
1087 };
1088
1089 static struct omap_hwmod_class_sysconfig dm816x_mcspi_sysc = {
1090         .rev_offs       = 0x0,
1091         .sysc_offs      = 0x110,
1092         .syss_offs      = 0x114,
1093         .sysc_flags     = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1094                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1095                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
1096         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
1097         .sysc_fields    = &omap_hwmod_sysc_type1,
1098 };
1099
1100 static struct omap_hwmod_class dm816x_mcspi_class = {
1101         .name = "mcspi",
1102         .sysc = &dm816x_mcspi_sysc,
1103         .rev = OMAP3_MCSPI_REV,
1104 };
1105
1106 static struct omap2_mcspi_dev_attr dm816x_mcspi1_dev_attr = {
1107         .num_chipselect = 4,
1108 };
1109
1110 static struct omap_hwmod dm81xx_mcspi1_hwmod = {
1111         .name           = "mcspi1",
1112         .clkdm_name     = "alwon_l3s_clkdm",
1113         .main_clk       = "sysclk10_ck",
1114         .prcm           = {
1115                 .omap4 = {
1116                         .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
1117                         .modulemode = MODULEMODE_SWCTRL,
1118                 },
1119         },
1120         .class          = &dm816x_mcspi_class,
1121         .dev_attr       = &dm816x_mcspi1_dev_attr,
1122 };
1123
1124 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = {
1125         .master         = &dm81xx_l4_ls_hwmod,
1126         .slave          = &dm81xx_mcspi1_hwmod,
1127         .clk            = "sysclk6_ck",
1128         .user           = OCP_USER_MPU,
1129 };
1130
1131 static struct omap_hwmod_class_sysconfig dm81xx_mailbox_sysc = {
1132         .rev_offs       = 0x000,
1133         .sysc_offs      = 0x010,
1134         .syss_offs      = 0x014,
1135         .sysc_flags     = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1136                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE,
1137         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
1138         .sysc_fields    = &omap_hwmod_sysc_type1,
1139 };
1140
1141 static struct omap_hwmod_class dm81xx_mailbox_hwmod_class = {
1142         .name = "mailbox",
1143         .sysc = &dm81xx_mailbox_sysc,
1144 };
1145
1146 static struct omap_hwmod dm81xx_mailbox_hwmod = {
1147         .name           = "mailbox",
1148         .clkdm_name     = "alwon_l3s_clkdm",
1149         .class          = &dm81xx_mailbox_hwmod_class,
1150         .main_clk       = "sysclk6_ck",
1151         .prcm           = {
1152                 .omap4 = {
1153                         .clkctrl_offs = DM81XX_CM_ALWON_MAILBOX_CLKCTRL,
1154                         .modulemode = MODULEMODE_SWCTRL,
1155                 },
1156         },
1157 };
1158
1159 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mailbox = {
1160         .master         = &dm81xx_l4_ls_hwmod,
1161         .slave          = &dm81xx_mailbox_hwmod,
1162         .user           = OCP_USER_MPU,
1163 };
1164
1165 static struct omap_hwmod_class_sysconfig dm81xx_spinbox_sysc = {
1166         .rev_offs       = 0x000,
1167         .sysc_offs      = 0x010,
1168         .syss_offs      = 0x014,
1169         .sysc_flags     = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1170                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE,
1171         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
1172         .sysc_fields    = &omap_hwmod_sysc_type1,
1173 };
1174
1175 static struct omap_hwmod_class dm81xx_spinbox_hwmod_class = {
1176         .name = "spinbox",
1177         .sysc = &dm81xx_spinbox_sysc,
1178 };
1179
1180 static struct omap_hwmod dm81xx_spinbox_hwmod = {
1181         .name           = "spinbox",
1182         .clkdm_name     = "alwon_l3s_clkdm",
1183         .class          = &dm81xx_spinbox_hwmod_class,
1184         .main_clk       = "sysclk6_ck",
1185         .prcm           = {
1186                 .omap4 = {
1187                         .clkctrl_offs = DM81XX_CM_ALWON_SPINBOX_CLKCTRL,
1188                         .modulemode = MODULEMODE_SWCTRL,
1189                 },
1190         },
1191 };
1192
1193 static struct omap_hwmod_ocp_if dm81xx_l4_ls__spinbox = {
1194         .master         = &dm81xx_l4_ls_hwmod,
1195         .slave          = &dm81xx_spinbox_hwmod,
1196         .user           = OCP_USER_MPU,
1197 };
1198
1199 static struct omap_hwmod_class dm81xx_tpcc_hwmod_class = {
1200         .name           = "tpcc",
1201 };
1202
1203 static struct omap_hwmod dm81xx_tpcc_hwmod = {
1204         .name           = "tpcc",
1205         .class          = &dm81xx_tpcc_hwmod_class,
1206         .clkdm_name     = "alwon_l3s_clkdm",
1207         .main_clk       = "sysclk4_ck",
1208         .prcm           = {
1209                 .omap4  = {
1210                         .clkctrl_offs   = DM81XX_CM_ALWON_TPCC_CLKCTRL,
1211                         .modulemode     = MODULEMODE_SWCTRL,
1212                 },
1213         },
1214 };
1215
1216 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tpcc = {
1217         .master         = &dm81xx_alwon_l3_fast_hwmod,
1218         .slave          = &dm81xx_tpcc_hwmod,
1219         .clk            = "sysclk4_ck",
1220         .user           = OCP_USER_MPU,
1221 };
1222
1223 static struct omap_hwmod_addr_space dm81xx_tptc0_addr_space[] = {
1224         {
1225                 .pa_start       = 0x49800000,
1226                 .pa_end         = 0x49800000 + SZ_8K - 1,
1227                 .flags          = ADDR_TYPE_RT,
1228         },
1229         { },
1230 };
1231
1232 static struct omap_hwmod_class dm81xx_tptc0_hwmod_class = {
1233         .name           = "tptc0",
1234 };
1235
1236 static struct omap_hwmod dm81xx_tptc0_hwmod = {
1237         .name           = "tptc0",
1238         .class          = &dm81xx_tptc0_hwmod_class,
1239         .clkdm_name     = "alwon_l3s_clkdm",
1240         .main_clk       = "sysclk4_ck",
1241         .prcm           = {
1242                 .omap4  = {
1243                         .clkctrl_offs   = DM81XX_CM_ALWON_TPTC0_CLKCTRL,
1244                         .modulemode     = MODULEMODE_SWCTRL,
1245                 },
1246         },
1247 };
1248
1249 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc0 = {
1250         .master         = &dm81xx_alwon_l3_fast_hwmod,
1251         .slave          = &dm81xx_tptc0_hwmod,
1252         .clk            = "sysclk4_ck",
1253         .addr           = dm81xx_tptc0_addr_space,
1254         .user           = OCP_USER_MPU,
1255 };
1256
1257 static struct omap_hwmod_ocp_if dm81xx_tptc0__alwon_l3_fast = {
1258         .master         = &dm81xx_tptc0_hwmod,
1259         .slave          = &dm81xx_alwon_l3_fast_hwmod,
1260         .clk            = "sysclk4_ck",
1261         .addr           = dm81xx_tptc0_addr_space,
1262         .user           = OCP_USER_MPU,
1263 };
1264
1265 static struct omap_hwmod_addr_space dm81xx_tptc1_addr_space[] = {
1266         {
1267                 .pa_start       = 0x49900000,
1268                 .pa_end         = 0x49900000 + SZ_8K - 1,
1269                 .flags          = ADDR_TYPE_RT,
1270         },
1271         { },
1272 };
1273
1274 static struct omap_hwmod_class dm81xx_tptc1_hwmod_class = {
1275         .name           = "tptc1",
1276 };
1277
1278 static struct omap_hwmod dm81xx_tptc1_hwmod = {
1279         .name           = "tptc1",
1280         .class          = &dm81xx_tptc1_hwmod_class,
1281         .clkdm_name     = "alwon_l3s_clkdm",
1282         .main_clk       = "sysclk4_ck",
1283         .prcm           = {
1284                 .omap4  = {
1285                         .clkctrl_offs   = DM81XX_CM_ALWON_TPTC1_CLKCTRL,
1286                         .modulemode     = MODULEMODE_SWCTRL,
1287                 },
1288         },
1289 };
1290
1291 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc1 = {
1292         .master         = &dm81xx_alwon_l3_fast_hwmod,
1293         .slave          = &dm81xx_tptc1_hwmod,
1294         .clk            = "sysclk4_ck",
1295         .addr           = dm81xx_tptc1_addr_space,
1296         .user           = OCP_USER_MPU,
1297 };
1298
1299 static struct omap_hwmod_ocp_if dm81xx_tptc1__alwon_l3_fast = {
1300         .master         = &dm81xx_tptc1_hwmod,
1301         .slave          = &dm81xx_alwon_l3_fast_hwmod,
1302         .clk            = "sysclk4_ck",
1303         .addr           = dm81xx_tptc1_addr_space,
1304         .user           = OCP_USER_MPU,
1305 };
1306
1307 static struct omap_hwmod_addr_space dm81xx_tptc2_addr_space[] = {
1308         {
1309                 .pa_start       = 0x49a00000,
1310                 .pa_end         = 0x49a00000 + SZ_8K - 1,
1311                 .flags          = ADDR_TYPE_RT,
1312         },
1313         { },
1314 };
1315
1316 static struct omap_hwmod_class dm81xx_tptc2_hwmod_class = {
1317         .name           = "tptc2",
1318 };
1319
1320 static struct omap_hwmod dm81xx_tptc2_hwmod = {
1321         .name           = "tptc2",
1322         .class          = &dm81xx_tptc2_hwmod_class,
1323         .clkdm_name     = "alwon_l3s_clkdm",
1324         .main_clk       = "sysclk4_ck",
1325         .prcm           = {
1326                 .omap4  = {
1327                         .clkctrl_offs   = DM81XX_CM_ALWON_TPTC2_CLKCTRL,
1328                         .modulemode     = MODULEMODE_SWCTRL,
1329                 },
1330         },
1331 };
1332
1333 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc2 = {
1334         .master         = &dm81xx_alwon_l3_fast_hwmod,
1335         .slave          = &dm81xx_tptc2_hwmod,
1336         .clk            = "sysclk4_ck",
1337         .addr           = dm81xx_tptc2_addr_space,
1338         .user           = OCP_USER_MPU,
1339 };
1340
1341 static struct omap_hwmod_ocp_if dm81xx_tptc2__alwon_l3_fast = {
1342         .master         = &dm81xx_tptc2_hwmod,
1343         .slave          = &dm81xx_alwon_l3_fast_hwmod,
1344         .clk            = "sysclk4_ck",
1345         .addr           = dm81xx_tptc2_addr_space,
1346         .user           = OCP_USER_MPU,
1347 };
1348
1349 static struct omap_hwmod_addr_space dm81xx_tptc3_addr_space[] = {
1350         {
1351                 .pa_start       = 0x49b00000,
1352                 .pa_end         = 0x49b00000 + SZ_8K - 1,
1353                 .flags          = ADDR_TYPE_RT,
1354         },
1355         { },
1356 };
1357
1358 static struct omap_hwmod_class dm81xx_tptc3_hwmod_class = {
1359         .name           = "tptc3",
1360 };
1361
1362 static struct omap_hwmod dm81xx_tptc3_hwmod = {
1363         .name           = "tptc3",
1364         .class          = &dm81xx_tptc3_hwmod_class,
1365         .clkdm_name     = "alwon_l3s_clkdm",
1366         .main_clk       = "sysclk4_ck",
1367         .prcm           = {
1368                 .omap4  = {
1369                         .clkctrl_offs   = DM81XX_CM_ALWON_TPTC3_CLKCTRL,
1370                         .modulemode     = MODULEMODE_SWCTRL,
1371                 },
1372         },
1373 };
1374
1375 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc3 = {
1376         .master         = &dm81xx_alwon_l3_fast_hwmod,
1377         .slave          = &dm81xx_tptc3_hwmod,
1378         .clk            = "sysclk4_ck",
1379         .addr           = dm81xx_tptc3_addr_space,
1380         .user           = OCP_USER_MPU,
1381 };
1382
1383 static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = {
1384         .master         = &dm81xx_tptc3_hwmod,
1385         .slave          = &dm81xx_alwon_l3_fast_hwmod,
1386         .clk            = "sysclk4_ck",
1387         .addr           = dm81xx_tptc3_addr_space,
1388         .user           = OCP_USER_MPU,
1389 };
1390
1391 /*
1392  * REVISIT: Test and enable the following once clocks work:
1393  * dm81xx_l4_ls__mailbox
1394  *
1395  * Also note that some devices share a single clkctrl_offs..
1396  * For example, i2c1 and 3 share one, and i2c2 and 4 share one.
1397  */
1398 static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = {
1399         &dm814x_mpu__alwon_l3_slow,
1400         &dm814x_mpu__alwon_l3_med,
1401         &dm81xx_alwon_l3_slow__l4_ls,
1402         &dm81xx_alwon_l3_slow__l4_hs,
1403         &dm81xx_l4_ls__uart1,
1404         &dm81xx_l4_ls__uart2,
1405         &dm81xx_l4_ls__uart3,
1406         &dm81xx_l4_ls__wd_timer1,
1407         &dm81xx_l4_ls__i2c1,
1408         &dm81xx_l4_ls__i2c2,
1409         &dm81xx_l4_ls__gpio1,
1410         &dm81xx_l4_ls__gpio2,
1411         &dm81xx_l4_ls__elm,
1412         &dm81xx_l4_ls__mcspi1,
1413         &dm814x_l4_ls__mmc1,
1414         &dm814x_l4_ls__mmc2,
1415         &ti81xx_l4_ls__rtc,
1416         &dm81xx_alwon_l3_fast__tpcc,
1417         &dm81xx_alwon_l3_fast__tptc0,
1418         &dm81xx_alwon_l3_fast__tptc1,
1419         &dm81xx_alwon_l3_fast__tptc2,
1420         &dm81xx_alwon_l3_fast__tptc3,
1421         &dm81xx_tptc0__alwon_l3_fast,
1422         &dm81xx_tptc1__alwon_l3_fast,
1423         &dm81xx_tptc2__alwon_l3_fast,
1424         &dm81xx_tptc3__alwon_l3_fast,
1425         &dm814x_l4_ls__timer1,
1426         &dm814x_l4_ls__timer2,
1427         &dm814x_l4_hs__cpgmac0,
1428         &dm814x_cpgmac0__mdio,
1429         &dm81xx_alwon_l3_slow__gpmc,
1430         &dm814x_default_l3_slow__usbss,
1431         &dm814x_alwon_l3_med__mmc3,
1432         NULL,
1433 };
1434
1435 int __init dm814x_hwmod_init(void)
1436 {
1437         omap_hwmod_init();
1438         return omap_hwmod_register_links(dm814x_hwmod_ocp_ifs);
1439 }
1440
1441 static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = {
1442         &dm816x_mpu__alwon_l3_slow,
1443         &dm816x_mpu__alwon_l3_med,
1444         &dm81xx_alwon_l3_slow__l4_ls,
1445         &dm81xx_alwon_l3_slow__l4_hs,
1446         &dm81xx_l4_ls__uart1,
1447         &dm81xx_l4_ls__uart2,
1448         &dm81xx_l4_ls__uart3,
1449         &dm81xx_l4_ls__wd_timer1,
1450         &dm81xx_l4_ls__i2c1,
1451         &dm81xx_l4_ls__i2c2,
1452         &dm81xx_l4_ls__gpio1,
1453         &dm81xx_l4_ls__gpio2,
1454         &dm81xx_l4_ls__elm,
1455         &ti81xx_l4_ls__rtc,
1456         &dm816x_l4_ls__mmc1,
1457         &dm816x_l4_ls__timer1,
1458         &dm816x_l4_ls__timer2,
1459         &dm816x_l4_ls__timer3,
1460         &dm816x_l4_ls__timer4,
1461         &dm816x_l4_ls__timer5,
1462         &dm816x_l4_ls__timer6,
1463         &dm816x_l4_ls__timer7,
1464         &dm81xx_l4_ls__mcspi1,
1465         &dm81xx_l4_ls__mailbox,
1466         &dm81xx_l4_ls__spinbox,
1467         &dm81xx_l4_hs__emac0,
1468         &dm81xx_emac0__mdio,
1469         &dm816x_l4_hs__emac1,
1470         &dm81xx_alwon_l3_fast__tpcc,
1471         &dm81xx_alwon_l3_fast__tptc0,
1472         &dm81xx_alwon_l3_fast__tptc1,
1473         &dm81xx_alwon_l3_fast__tptc2,
1474         &dm81xx_alwon_l3_fast__tptc3,
1475         &dm81xx_tptc0__alwon_l3_fast,
1476         &dm81xx_tptc1__alwon_l3_fast,
1477         &dm81xx_tptc2__alwon_l3_fast,
1478         &dm81xx_tptc3__alwon_l3_fast,
1479         &dm81xx_alwon_l3_slow__gpmc,
1480         &dm816x_default_l3_slow__usbss,
1481         NULL,
1482 };
1483
1484 int __init dm816x_hwmod_init(void)
1485 {
1486         omap_hwmod_init();
1487         return omap_hwmod_register_links(dm816x_hwmod_ocp_ifs);
1488 }