arch/arm/mach-omap2/omap_hwmod_81xx_data.c

   1 /*
   2  * DM81xx hwmod data.
   3  *
   4  * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
   5  * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/platform_data/gpio-omap.h>
  19 #include <linux/platform_data/hsmmc-omap.h>
  20 #include <linux/platform_data/spi-omap2-mcspi.h>
  21 #include <plat/dmtimer.h>
  22
  23 #include "omap_hwmod_common_data.h"
  24 #include "cm81xx.h"
  25 #include "ti81xx.h"
  26 #include "wd_timer.h"
  27
  28 /*
  29  * DM816X hardware modules integration data
  30  *
  31  * Note: This is incomplete and at present, not generated from h/w database.
  32  */
  33
  34 /*
  35  * Common alwon .clkctrl_offs from dm814x TRM "Table 2-278. CM_ALWON REGISTERS"
  36  * also dm816x TRM 18.7.17 CM_ALWON device register values minus 0x1400.
  37  */
  38 #define DM81XX_CM_ALWON_MCASP0_CLKCTRL          0x140
  39 #define DM81XX_CM_ALWON_MCASP1_CLKCTRL          0x144
  40 #define DM81XX_CM_ALWON_MCASP2_CLKCTRL          0x148
  41 #define DM81XX_CM_ALWON_MCBSP_CLKCTRL           0x14c
  42 #define DM81XX_CM_ALWON_UART_0_CLKCTRL          0x150
  43 #define DM81XX_CM_ALWON_UART_1_CLKCTRL          0x154
  44 #define DM81XX_CM_ALWON_UART_2_CLKCTRL          0x158
  45 #define DM81XX_CM_ALWON_GPIO_0_CLKCTRL          0x15c
  46 #define DM81XX_CM_ALWON_GPIO_1_CLKCTRL          0x160
  47 #define DM81XX_CM_ALWON_I2C_0_CLKCTRL           0x164
  48 #define DM81XX_CM_ALWON_I2C_1_CLKCTRL           0x168
  49 #define DM81XX_CM_ALWON_WDTIMER_CLKCTRL         0x18c
  50 #define DM81XX_CM_ALWON_SPI_CLKCTRL             0x190
  51 #define DM81XX_CM_ALWON_MAILBOX_CLKCTRL         0x194
  52 #define DM81XX_CM_ALWON_SPINBOX_CLKCTRL         0x198
  53 #define DM81XX_CM_ALWON_MMUDATA_CLKCTRL         0x19c
  54 #define DM81XX_CM_ALWON_MMUCFG_CLKCTRL          0x1a8
  55 #define DM81XX_CM_ALWON_CONTROL_CLKCTRL         0x1c4
  56 #define DM81XX_CM_ALWON_GPMC_CLKCTRL            0x1d0
  57 #define DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL      0x1d4
  58 #define DM81XX_CM_ALWON_L3_CLKCTRL              0x1e4
  59 #define DM81XX_CM_ALWON_L4HS_CLKCTRL            0x1e8
  60 #define DM81XX_CM_ALWON_L4LS_CLKCTRL            0x1ec
  61 #define DM81XX_CM_ALWON_RTC_CLKCTRL             0x1f0
  62 #define DM81XX_CM_ALWON_TPCC_CLKCTRL            0x1f4
  63 #define DM81XX_CM_ALWON_TPTC0_CLKCTRL           0x1f8
  64 #define DM81XX_CM_ALWON_TPTC1_CLKCTRL           0x1fc
  65 #define DM81XX_CM_ALWON_TPTC2_CLKCTRL           0x200
  66 #define DM81XX_CM_ALWON_TPTC3_CLKCTRL           0x204
  67
  68 /* Registers specific to dm814x */
  69 #define DM814X_CM_ALWON_MCASP_3_4_5_CLKCTRL     0x16c
  70 #define DM814X_CM_ALWON_ATL_CLKCTRL             0x170
  71 #define DM814X_CM_ALWON_MLB_CLKCTRL             0x174
  72 #define DM814X_CM_ALWON_PATA_CLKCTRL            0x178
  73 #define DM814X_CM_ALWON_UART_3_CLKCTRL          0x180
  74 #define DM814X_CM_ALWON_UART_4_CLKCTRL          0x184
  75 #define DM814X_CM_ALWON_UART_5_CLKCTRL          0x188
  76 #define DM814X_CM_ALWON_OCM_0_CLKCTRL           0x1b4
  77 #define DM814X_CM_ALWON_VCP_CLKCTRL             0x1b8
  78 #define DM814X_CM_ALWON_MPU_CLKCTRL             0x1dc
  79 #define DM814X_CM_ALWON_DEBUGSS_CLKCTRL         0x1e0
  80 #define DM814X_CM_ALWON_DCAN_0_1_CLKCTRL        0x218
  81 #define DM814X_CM_ALWON_MMCHS_0_CLKCTRL         0x21c
  82 #define DM814X_CM_ALWON_MMCHS_1_CLKCTRL         0x220
  83 #define DM814X_CM_ALWON_MMCHS_2_CLKCTRL         0x224
  84 #define DM814X_CM_ALWON_CUST_EFUSE_CLKCTRL      0x228
  85
  86 /* Registers specific to dm816x */
  87 #define DM816X_DM_ALWON_BASE            0x1400
  88 #define DM816X_CM_ALWON_TIMER_1_CLKCTRL (0x1570 - DM816X_DM_ALWON_BASE)
  89 #define DM816X_CM_ALWON_TIMER_2_CLKCTRL (0x1574 - DM816X_DM_ALWON_BASE)
  90 #define DM816X_CM_ALWON_TIMER_3_CLKCTRL (0x1578 - DM816X_DM_ALWON_BASE)
  91 #define DM816X_CM_ALWON_TIMER_4_CLKCTRL (0x157c - DM816X_DM_ALWON_BASE)
  92 #define DM816X_CM_ALWON_TIMER_5_CLKCTRL (0x1580 - DM816X_DM_ALWON_BASE)
  93 #define DM816X_CM_ALWON_TIMER_6_CLKCTRL (0x1584 - DM816X_DM_ALWON_BASE)
  94 #define DM816X_CM_ALWON_TIMER_7_CLKCTRL (0x1588 - DM816X_DM_ALWON_BASE)
  95 #define DM816X_CM_ALWON_SDIO_CLKCTRL    (0x15b0 - DM816X_DM_ALWON_BASE)
  96 #define DM816X_CM_ALWON_OCMC_0_CLKCTRL  (0x15b4 - DM816X_DM_ALWON_BASE)
  97 #define DM816X_CM_ALWON_OCMC_1_CLKCTRL  (0x15b8 - DM816X_DM_ALWON_BASE)
  98 #define DM816X_CM_ALWON_ETHERNET_1_CLKCTRL (0x15d8 - DM816X_DM_ALWON_BASE)
  99 #define DM816X_CM_ALWON_MPU_CLKCTRL     (0x15dc - DM816X_DM_ALWON_BASE)
 100 #define DM816X_CM_ALWON_SR_0_CLKCTRL    (0x1608 - DM816X_DM_ALWON_BASE)
 101 #define DM816X_CM_ALWON_SR_1_CLKCTRL    (0x160c - DM816X_DM_ALWON_BASE)
 102
 103 /*
 104  * The default .clkctrl_offs field is offset from CM_DEFAULT, that's
 105  * TRM 18.7.6 CM_DEFAULT device register values minus 0x500
 106  */
 107 #define DM81XX_CM_DEFAULT_OFFSET        0x500
 108 #define DM81XX_CM_DEFAULT_USB_CLKCTRL   (0x558 - DM81XX_CM_DEFAULT_OFFSET)
 109
 110 /* L3 Interconnect entries clocked at 125, 250 and 500MHz */
 111 static struct omap_hwmod dm81xx_alwon_l3_slow_hwmod = {
 112         .name           = "alwon_l3_slow",
 113         .clkdm_name     = "alwon_l3s_clkdm",
 114         .class          = &l3_hwmod_class,
 115         .flags          = HWMOD_NO_IDLEST,
 116 };
 117
 118 static struct omap_hwmod dm81xx_default_l3_slow_hwmod = {
 119         .name           = "default_l3_slow",
 120         .clkdm_name     = "default_l3_slow_clkdm",
 121         .class          = &l3_hwmod_class,
 122         .flags          = HWMOD_NO_IDLEST,
 123 };
 124
 125 static struct omap_hwmod dm81xx_alwon_l3_med_hwmod = {
 126         .name           = "l3_med",
 127         .clkdm_name     = "alwon_l3_med_clkdm",
 128         .class          = &l3_hwmod_class,
 129         .flags          = HWMOD_NO_IDLEST,
 130 };
 131
 132 static struct omap_hwmod dm81xx_alwon_l3_fast_hwmod = {
 133         .name           = "l3_fast",
 134         .clkdm_name     = "alwon_l3_fast_clkdm",
 135         .class          = &l3_hwmod_class,
 136         .flags          = HWMOD_NO_IDLEST,
 137 };
 138
 139 /*
 140  * L4 standard peripherals, see TRM table 1-12 for devices using this.
 141  * See TRM table 1-73 for devices using the 125MHz SYSCLK6 clock.
 142  */
 143 static struct omap_hwmod dm81xx_l4_ls_hwmod = {
 144         .name           = "l4_ls",
 145         .clkdm_name     = "alwon_l3s_clkdm",
 146         .class          = &l4_hwmod_class,
 147         .flags          = HWMOD_NO_IDLEST,
 148 };
 149
 150 /*
 151  * L4 high-speed peripherals. For devices using this, please see the TRM
 152  * table 1-13. On dm816x, only EMAC, MDIO and SATA use this. See also TRM
 153  * table 1-73 for devices using 250MHz SYSCLK5 clock.
 154  */
 155 static struct omap_hwmod dm81xx_l4_hs_hwmod = {
 156         .name           = "l4_hs",
 157         .clkdm_name     = "alwon_l3_med_clkdm",
 158         .class          = &l4_hwmod_class,
 159         .flags          = HWMOD_NO_IDLEST,
 160 };
 161
 162 /* L3 slow -> L4 ls peripheral interface running at 125MHz */
 163 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_ls = {
 164         .master = &dm81xx_alwon_l3_slow_hwmod,
 165         .slave  = &dm81xx_l4_ls_hwmod,
 166         .user   = OCP_USER_MPU,
 167 };
 168
 169 /* L3 med -> L4 fast peripheral interface running at 250MHz */
 170 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_hs = {
 171         .master = &dm81xx_alwon_l3_med_hwmod,
 172         .slave  = &dm81xx_l4_hs_hwmod,
 173         .user   = OCP_USER_MPU,
 174 };
 175
 176 /* MPU */
 177 static struct omap_hwmod dm814x_mpu_hwmod = {
 178         .name           = "mpu",
 179         .clkdm_name     = "alwon_l3s_clkdm",
 180         .class          = &mpu_hwmod_class,
 181         .flags          = HWMOD_INIT_NO_IDLE,
 182         .main_clk       = "mpu_ck",
 183         .prcm           = {
 184                 .omap4 = {
 185                         .clkctrl_offs = DM814X_CM_ALWON_MPU_CLKCTRL,
 186                         .modulemode = MODULEMODE_SWCTRL,
 187                 },
 188         },
 189 };
 190
 191 static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_slow = {
 192         .master         = &dm814x_mpu_hwmod,
 193         .slave          = &dm81xx_alwon_l3_slow_hwmod,
 194         .user           = OCP_USER_MPU,
 195 };
 196
 197 /* L3 med peripheral interface running at 200MHz */
 198 static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_med = {
 199         .master = &dm814x_mpu_hwmod,
 200         .slave  = &dm81xx_alwon_l3_med_hwmod,
 201         .user   = OCP_USER_MPU,
 202 };
 203
 204 static struct omap_hwmod dm816x_mpu_hwmod = {
 205         .name           = "mpu",
 206         .clkdm_name     = "alwon_mpu_clkdm",
 207         .class          = &mpu_hwmod_class,
 208         .flags          = HWMOD_INIT_NO_IDLE,
 209         .main_clk       = "mpu_ck",
 210         .prcm           = {
 211                 .omap4 = {
 212                         .clkctrl_offs = DM816X_CM_ALWON_MPU_CLKCTRL,
 213                         .modulemode = MODULEMODE_SWCTRL,
 214                 },
 215         },
 216 };
 217
 218 static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_slow = {
 219         .master         = &dm816x_mpu_hwmod,
 220         .slave          = &dm81xx_alwon_l3_slow_hwmod,
 221         .user           = OCP_USER_MPU,
 222 };
 223
 224 /* L3 med peripheral interface running at 250MHz */
 225 static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_med = {
 226         .master = &dm816x_mpu_hwmod,
 227         .slave  = &dm81xx_alwon_l3_med_hwmod,
 228         .user   = OCP_USER_MPU,
 229 };
 230
 231 /* RTC */
 232 static struct omap_hwmod_class_sysconfig ti81xx_rtc_sysc = {
 233         .rev_offs       = 0x74,
 234         .sysc_offs      = 0x78,
 235         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 236         .idlemodes      = SIDLE_FORCE | SIDLE_NO |
 237                           SIDLE_SMART | SIDLE_SMART_WKUP,
 238         .sysc_fields    = &omap_hwmod_sysc_type3,
 239 };
 240
 241 static struct omap_hwmod_class ti81xx_rtc_hwmod_class = {
 242         .name           = "rtc",
 243         .sysc           = &ti81xx_rtc_sysc,
 244 };
 245
 246 struct omap_hwmod ti81xx_rtc_hwmod = {
 247         .name           = "rtc",
 248         .class          = &ti81xx_rtc_hwmod_class,
 249         .clkdm_name     = "alwon_l3s_clkdm",
 250         .flags          = HWMOD_NO_IDLEST,
 251         .main_clk       = "sysclk18_ck",
 252         .prcm           = {
 253                 .omap4  = {
 254                         .clkctrl_offs = DM81XX_CM_ALWON_RTC_CLKCTRL,
 255                         .modulemode = MODULEMODE_SWCTRL,
 256                 },
 257         },
 258 };
 259
 260 static struct omap_hwmod_ocp_if ti81xx_l4_ls__rtc = {
 261         .master         = &dm81xx_l4_ls_hwmod,
 262         .slave          = &ti81xx_rtc_hwmod,
 263         .clk            = "sysclk6_ck",
 264         .user           = OCP_USER_MPU,
 265 };
 266
 267 /* UART common */
 268 static struct omap_hwmod_class_sysconfig uart_sysc = {
 269         .rev_offs       = 0x50,
 270         .sysc_offs      = 0x54,
 271         .syss_offs      = 0x58,
 272         .sysc_flags     = SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 273                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 274                                 SYSS_HAS_RESET_STATUS,
 275         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 276                                 MSTANDBY_SMART_WKUP,
 277         .sysc_fields    = &omap_hwmod_sysc_type1,
 278 };
 279
 280 static struct omap_hwmod_class uart_class = {
 281         .name = "uart",
 282         .sysc = &uart_sysc,
 283 };
 284
 285 static struct omap_hwmod dm81xx_uart1_hwmod = {
 286         .name           = "uart1",
 287         .clkdm_name     = "alwon_l3s_clkdm",
 288         .main_clk       = "sysclk10_ck",
 289         .prcm           = {
 290                 .omap4 = {
 291                         .clkctrl_offs = DM81XX_CM_ALWON_UART_0_CLKCTRL,
 292                         .modulemode = MODULEMODE_SWCTRL,
 293                 },
 294         },
 295         .class          = &uart_class,
 296         .flags          = DEBUG_TI81XXUART1_FLAGS,
 297 };
 298
 299 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart1 = {
 300         .master         = &dm81xx_l4_ls_hwmod,
 301         .slave          = &dm81xx_uart1_hwmod,
 302         .clk            = "sysclk6_ck",
 303         .user           = OCP_USER_MPU,
 304 };
 305
 306 static struct omap_hwmod dm81xx_uart2_hwmod = {
 307         .name           = "uart2",
 308         .clkdm_name     = "alwon_l3s_clkdm",
 309         .main_clk       = "sysclk10_ck",
 310         .prcm           = {
 311                 .omap4 = {
 312                         .clkctrl_offs = DM81XX_CM_ALWON_UART_1_CLKCTRL,
 313                         .modulemode = MODULEMODE_SWCTRL,
 314                 },
 315         },
 316         .class          = &uart_class,
 317         .flags          = DEBUG_TI81XXUART2_FLAGS,
 318 };
 319
 320 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart2 = {
 321         .master         = &dm81xx_l4_ls_hwmod,
 322         .slave          = &dm81xx_uart2_hwmod,
 323         .clk            = "sysclk6_ck",
 324         .user           = OCP_USER_MPU,
 325 };
 326
 327 static struct omap_hwmod dm81xx_uart3_hwmod = {
 328         .name           = "uart3",
 329         .clkdm_name     = "alwon_l3s_clkdm",
 330         .main_clk       = "sysclk10_ck",
 331         .prcm           = {
 332                 .omap4 = {
 333                         .clkctrl_offs = DM81XX_CM_ALWON_UART_2_CLKCTRL,
 334                         .modulemode = MODULEMODE_SWCTRL,
 335                 },
 336         },
 337         .class          = &uart_class,
 338         .flags          = DEBUG_TI81XXUART3_FLAGS,
 339 };
 340
 341 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart3 = {
 342         .master         = &dm81xx_l4_ls_hwmod,
 343         .slave          = &dm81xx_uart3_hwmod,
 344         .clk            = "sysclk6_ck",
 345         .user           = OCP_USER_MPU,
 346 };
 347
 348 static struct omap_hwmod_class_sysconfig wd_timer_sysc = {
 349         .rev_offs       = 0x0,
 350         .sysc_offs      = 0x10,
 351         .syss_offs      = 0x14,
 352         .sysc_flags     = SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
 353                                 SYSS_HAS_RESET_STATUS,
 354         .sysc_fields    = &omap_hwmod_sysc_type1,
 355 };
 356
 357 static struct omap_hwmod_class wd_timer_class = {
 358         .name           = "wd_timer",
 359         .sysc           = &wd_timer_sysc,
 360         .pre_shutdown   = &omap2_wd_timer_disable,
 361         .reset          = &omap2_wd_timer_reset,
 362 };
 363
 364 static struct omap_hwmod dm81xx_wd_timer_hwmod = {
 365         .name           = "wd_timer",
 366         .clkdm_name     = "alwon_l3s_clkdm",
 367         .main_clk       = "sysclk18_ck",
 368         .flags          = HWMOD_NO_IDLEST,
 369         .prcm           = {
 370                 .omap4 = {
 371                         .clkctrl_offs = DM81XX_CM_ALWON_WDTIMER_CLKCTRL,
 372                         .modulemode = MODULEMODE_SWCTRL,
 373                 },
 374         },
 375         .class          = &wd_timer_class,
 376 };
 377
 378 static struct omap_hwmod_ocp_if dm81xx_l4_ls__wd_timer1 = {
 379         .master         = &dm81xx_l4_ls_hwmod,
 380         .slave          = &dm81xx_wd_timer_hwmod,
 381         .clk            = "sysclk6_ck",
 382         .user           = OCP_USER_MPU,
 383 };
 384
 385 /* I2C common */
 386 static struct omap_hwmod_class_sysconfig i2c_sysc = {
 387         .rev_offs       = 0x0,
 388         .sysc_offs      = 0x10,
 389         .syss_offs      = 0x90,
 390         .sysc_flags     = SYSC_HAS_SIDLEMODE |
 391                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 392                                 SYSC_HAS_AUTOIDLE,
 393         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
 394         .sysc_fields    = &omap_hwmod_sysc_type1,
 395 };
 396
 397 static struct omap_hwmod_class i2c_class = {
 398         .name = "i2c",
 399         .sysc = &i2c_sysc,
 400 };
 401
 402 static struct omap_hwmod dm81xx_i2c1_hwmod = {
 403         .name           = "i2c1",
 404         .clkdm_name     = "alwon_l3s_clkdm",
 405         .main_clk       = "sysclk10_ck",
 406         .prcm           = {
 407                 .omap4 = {
 408                         .clkctrl_offs = DM81XX_CM_ALWON_I2C_0_CLKCTRL,
 409                         .modulemode = MODULEMODE_SWCTRL,
 410                 },
 411         },
 412         .class          = &i2c_class,
 413 };
 414
 415 static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c1 = {
 416         .master         = &dm81xx_l4_ls_hwmod,
 417         .slave          = &dm81xx_i2c1_hwmod,
 418         .clk            = "sysclk6_ck",
 419         .user           = OCP_USER_MPU,
 420 };
 421
 422 static struct omap_hwmod dm81xx_i2c2_hwmod = {
 423         .name           = "i2c2",
 424         .clkdm_name     = "alwon_l3s_clkdm",
 425         .main_clk       = "sysclk10_ck",
 426         .prcm           = {
 427                 .omap4 = {
 428                         .clkctrl_offs = DM81XX_CM_ALWON_I2C_1_CLKCTRL,
 429                         .modulemode = MODULEMODE_SWCTRL,
 430                 },
 431         },
 432         .class          = &i2c_class,
 433 };
 434
 435 static struct omap_hwmod_class_sysconfig dm81xx_elm_sysc = {
 436         .rev_offs       = 0x0000,
 437         .sysc_offs      = 0x0010,
 438         .syss_offs      = 0x0014,
 439         .sysc_flags     = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 440                                 SYSC_HAS_SOFTRESET |
 441                                 SYSS_HAS_RESET_STATUS,
 442         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
 443         .sysc_fields    = &omap_hwmod_sysc_type1,
 444 };
 445
 446 static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c2 = {
 447         .master         = &dm81xx_l4_ls_hwmod,
 448         .slave          = &dm81xx_i2c2_hwmod,
 449         .clk            = "sysclk6_ck",
 450         .user           = OCP_USER_MPU,
 451 };
 452
 453 static struct omap_hwmod_class dm81xx_elm_hwmod_class = {
 454         .name = "elm",
 455         .sysc = &dm81xx_elm_sysc,
 456 };
 457
 458 static struct omap_hwmod dm81xx_elm_hwmod = {
 459         .name           = "elm",
 460         .clkdm_name     = "alwon_l3s_clkdm",
 461         .class          = &dm81xx_elm_hwmod_class,
 462         .main_clk       = "sysclk6_ck",
 463 };
 464
 465 static struct omap_hwmod_ocp_if dm81xx_l4_ls__elm = {
 466         .master         = &dm81xx_l4_ls_hwmod,
 467         .slave          = &dm81xx_elm_hwmod,
 468         .clk            = "sysclk6_ck",
 469         .user           = OCP_USER_MPU,
 470 };
 471
 472 static struct omap_hwmod_class_sysconfig dm81xx_gpio_sysc = {
 473         .rev_offs       = 0x0000,
 474         .sysc_offs      = 0x0010,
 475         .syss_offs      = 0x0114,
 476         .sysc_flags     = SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 477                                 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 478                                 SYSS_HAS_RESET_STATUS,
 479         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 480                                 SIDLE_SMART_WKUP,
 481         .sysc_fields    = &omap_hwmod_sysc_type1,
 482 };
 483
 484 static struct omap_hwmod_class dm81xx_gpio_hwmod_class = {
 485         .name   = "gpio",
 486         .sysc   = &dm81xx_gpio_sysc,
 487         .rev    = 2,
 488 };
 489
 490 static struct omap_gpio_dev_attr gpio_dev_attr = {
 491         .bank_width     = 32,
 492         .dbck_flag      = true,
 493 };
 494
 495 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 496         { .role = "dbclk", .clk = "sysclk18_ck" },
 497 };
 498
 499 static struct omap_hwmod dm81xx_gpio1_hwmod = {
 500         .name           = "gpio1",
 501         .clkdm_name     = "alwon_l3s_clkdm",
 502         .class          = &dm81xx_gpio_hwmod_class,
 503         .main_clk       = "sysclk6_ck",
 504         .prcm = {
 505                 .omap4 = {
 506                         .clkctrl_offs = DM81XX_CM_ALWON_GPIO_0_CLKCTRL,
 507                         .modulemode = MODULEMODE_SWCTRL,
 508                 },
 509         },
 510         .opt_clks       = gpio1_opt_clks,
 511         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 512         .dev_attr       = &gpio_dev_attr,
 513 };
 514
 515 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio1 = {
 516         .master         = &dm81xx_l4_ls_hwmod,
 517         .slave          = &dm81xx_gpio1_hwmod,
 518         .clk            = "sysclk6_ck",
 519         .user           = OCP_USER_MPU,
 520 };
 521
 522 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 523         { .role = "dbclk", .clk = "sysclk18_ck" },
 524 };
 525
 526 static struct omap_hwmod dm81xx_gpio2_hwmod = {
 527         .name           = "gpio2",
 528         .clkdm_name     = "alwon_l3s_clkdm",
 529         .class          = &dm81xx_gpio_hwmod_class,
 530         .main_clk       = "sysclk6_ck",
 531         .prcm = {
 532                 .omap4 = {
 533                         .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL,
 534                         .modulemode = MODULEMODE_SWCTRL,
 535                 },
 536         },
 537         .opt_clks       = gpio2_opt_clks,
 538         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 539         .dev_attr       = &gpio_dev_attr,
 540 };
 541
 542 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = {
 543         .master         = &dm81xx_l4_ls_hwmod,
 544         .slave          = &dm81xx_gpio2_hwmod,
 545         .clk            = "sysclk6_ck",
 546         .user           = OCP_USER_MPU,
 547 };
 548
 549 static struct omap_hwmod_class_sysconfig dm81xx_gpmc_sysc = {
 550         .rev_offs       = 0x0,
 551         .sysc_offs      = 0x10,
 552         .syss_offs      = 0x14,
 553         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 554                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
 555         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
 556         .sysc_fields    = &omap_hwmod_sysc_type1,
 557 };
 558
 559 static struct omap_hwmod_class dm81xx_gpmc_hwmod_class = {
 560         .name   = "gpmc",
 561         .sysc   = &dm81xx_gpmc_sysc,
 562 };
 563
 564 static struct omap_hwmod dm81xx_gpmc_hwmod = {
 565         .name           = "gpmc",
 566         .clkdm_name     = "alwon_l3s_clkdm",
 567         .class          = &dm81xx_gpmc_hwmod_class,
 568         .main_clk       = "sysclk6_ck",
 569         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
 570         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
 571         .prcm = {
 572                 .omap4 = {
 573                         .clkctrl_offs = DM81XX_CM_ALWON_GPMC_CLKCTRL,
 574                         .modulemode = MODULEMODE_SWCTRL,
 575                 },
 576         },
 577 };
 578
 579 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__gpmc = {
 580         .master         = &dm81xx_alwon_l3_slow_hwmod,
 581         .slave          = &dm81xx_gpmc_hwmod,
 582         .user           = OCP_USER_MPU,
 583 };
 584
 585 static struct omap_hwmod_class_sysconfig dm81xx_usbhsotg_sysc = {
 586         .rev_offs       = 0x0,
 587         .sysc_offs      = 0x10,
 588         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 589                                 SYSC_HAS_SOFTRESET,
 590         .idlemodes      = SIDLE_SMART | MSTANDBY_FORCE | MSTANDBY_SMART,
 591         .sysc_fields    = &omap_hwmod_sysc_type2,
 592 };
 593
 594 static struct omap_hwmod_class dm81xx_usbotg_class = {
 595         .name = "usbotg",
 596         .sysc = &dm81xx_usbhsotg_sysc,
 597 };
 598
 599 static struct omap_hwmod dm814x_usbss_hwmod = {
 600         .name           = "usb_otg_hs",
 601         .clkdm_name     = "default_l3_slow_clkdm",
 602         .main_clk       = "pll260dcoclkldo",    /* 481c5260.adpll.dcoclkldo */
 603         .prcm           = {
 604                 .omap4 = {
 605                         .clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL,
 606                         .modulemode = MODULEMODE_SWCTRL,
 607                 },
 608         },
 609         .class          = &dm81xx_usbotg_class,
 610 };
 611
 612 static struct omap_hwmod_ocp_if dm814x_default_l3_slow__usbss = {
 613         .master         = &dm81xx_default_l3_slow_hwmod,
 614         .slave          = &dm814x_usbss_hwmod,
 615         .clk            = "sysclk6_ck",
 616         .user           = OCP_USER_MPU,
 617 };
 618
 619 static struct omap_hwmod dm816x_usbss_hwmod = {
 620         .name           = "usb_otg_hs",
 621         .clkdm_name     = "default_l3_slow_clkdm",
 622         .main_clk       = "sysclk6_ck",
 623         .prcm           = {
 624                 .omap4 = {
 625                         .clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL,
 626                         .modulemode = MODULEMODE_SWCTRL,
 627                 },
 628         },
 629         .class          = &dm81xx_usbotg_class,
 630 };
 631
 632 static struct omap_hwmod_ocp_if dm816x_default_l3_slow__usbss = {
 633         .master         = &dm81xx_default_l3_slow_hwmod,
 634         .slave          = &dm816x_usbss_hwmod,
 635         .clk            = "sysclk6_ck",
 636         .user           = OCP_USER_MPU,
 637 };
 638
 639 static struct omap_hwmod_class_sysconfig dm816x_timer_sysc = {
 640         .rev_offs       = 0x0000,
 641         .sysc_offs      = 0x0010,
 642         .syss_offs      = 0x0014,
 643         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET,
 644         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 645                                 SIDLE_SMART_WKUP,
 646         .sysc_fields    = &omap_hwmod_sysc_type2,
 647 };
 648
 649 static struct omap_hwmod_class dm816x_timer_hwmod_class = {
 650         .name = "timer",
 651         .sysc = &dm816x_timer_sysc,
 652 };
 653
 654 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 655         .timer_capability       = OMAP_TIMER_ALWON,
 656 };
 657
 658 static struct omap_hwmod dm814x_timer1_hwmod = {
 659         .name           = "timer1",
 660         .clkdm_name     = "alwon_l3s_clkdm",
 661         .main_clk       = "timer1_fck",
 662         .dev_attr       = &capability_alwon_dev_attr,
 663         .class          = &dm816x_timer_hwmod_class,
 664         .flags          = HWMOD_NO_IDLEST,
 665 };
 666
 667 static struct omap_hwmod_ocp_if dm814x_l4_ls__timer1 = {
 668         .master         = &dm81xx_l4_ls_hwmod,
 669         .slave          = &dm814x_timer1_hwmod,
 670         .clk            = "sysclk6_ck",
 671         .user           = OCP_USER_MPU,
 672 };
 673
 674 static struct omap_hwmod dm816x_timer1_hwmod = {
 675         .name           = "timer1",
 676         .clkdm_name     = "alwon_l3s_clkdm",
 677         .main_clk       = "timer1_fck",
 678         .prcm           = {
 679                 .omap4 = {
 680                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_1_CLKCTRL,
 681                         .modulemode = MODULEMODE_SWCTRL,
 682                 },
 683         },
 684         .dev_attr       = &capability_alwon_dev_attr,
 685         .class          = &dm816x_timer_hwmod_class,
 686 };
 687
 688 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = {
 689         .master         = &dm81xx_l4_ls_hwmod,
 690         .slave          = &dm816x_timer1_hwmod,
 691         .clk            = "sysclk6_ck",
 692         .user           = OCP_USER_MPU,
 693 };
 694
 695 static struct omap_hwmod dm814x_timer2_hwmod = {
 696         .name           = "timer2",
 697         .clkdm_name     = "alwon_l3s_clkdm",
 698         .main_clk       = "timer2_fck",
 699         .dev_attr       = &capability_alwon_dev_attr,
 700         .class          = &dm816x_timer_hwmod_class,
 701         .flags          = HWMOD_NO_IDLEST,
 702 };
 703
 704 static struct omap_hwmod_ocp_if dm814x_l4_ls__timer2 = {
 705         .master         = &dm81xx_l4_ls_hwmod,
 706         .slave          = &dm814x_timer2_hwmod,
 707         .clk            = "sysclk6_ck",
 708         .user           = OCP_USER_MPU,
 709 };
 710
 711 static struct omap_hwmod dm816x_timer2_hwmod = {
 712         .name           = "timer2",
 713         .clkdm_name     = "alwon_l3s_clkdm",
 714         .main_clk       = "timer2_fck",
 715         .prcm           = {
 716                 .omap4 = {
 717                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_2_CLKCTRL,
 718                         .modulemode = MODULEMODE_SWCTRL,
 719                 },
 720         },
 721         .dev_attr       = &capability_alwon_dev_attr,
 722         .class          = &dm816x_timer_hwmod_class,
 723 };
 724
 725 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer2 = {
 726         .master         = &dm81xx_l4_ls_hwmod,
 727         .slave          = &dm816x_timer2_hwmod,
 728         .clk            = "sysclk6_ck",
 729         .user           = OCP_USER_MPU,
 730 };
 731
 732 static struct omap_hwmod dm816x_timer3_hwmod = {
 733         .name           = "timer3",
 734         .clkdm_name     = "alwon_l3s_clkdm",
 735         .main_clk       = "timer3_fck",
 736         .prcm           = {
 737                 .omap4 = {
 738                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_3_CLKCTRL,
 739                         .modulemode = MODULEMODE_SWCTRL,
 740                 },
 741         },
 742         .dev_attr       = &capability_alwon_dev_attr,
 743         .class          = &dm816x_timer_hwmod_class,
 744 };
 745
 746 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer3 = {
 747         .master         = &dm81xx_l4_ls_hwmod,
 748         .slave          = &dm816x_timer3_hwmod,
 749         .clk            = "sysclk6_ck",
 750         .user           = OCP_USER_MPU,
 751 };
 752
 753 static struct omap_hwmod dm816x_timer4_hwmod = {
 754         .name           = "timer4",
 755         .clkdm_name     = "alwon_l3s_clkdm",
 756         .main_clk       = "timer4_fck",
 757         .prcm           = {
 758                 .omap4 = {
 759                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_4_CLKCTRL,
 760                         .modulemode = MODULEMODE_SWCTRL,
 761                 },
 762         },
 763         .dev_attr       = &capability_alwon_dev_attr,
 764         .class          = &dm816x_timer_hwmod_class,
 765 };
 766
 767 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer4 = {
 768         .master         = &dm81xx_l4_ls_hwmod,
 769         .slave          = &dm816x_timer4_hwmod,
 770         .clk            = "sysclk6_ck",
 771         .user           = OCP_USER_MPU,
 772 };
 773
 774 static struct omap_hwmod dm816x_timer5_hwmod = {
 775         .name           = "timer5",
 776         .clkdm_name     = "alwon_l3s_clkdm",
 777         .main_clk       = "timer5_fck",
 778         .prcm           = {
 779                 .omap4 = {
 780                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_5_CLKCTRL,
 781                         .modulemode = MODULEMODE_SWCTRL,
 782                 },
 783         },
 784         .dev_attr       = &capability_alwon_dev_attr,
 785         .class          = &dm816x_timer_hwmod_class,
 786 };
 787
 788 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer5 = {
 789         .master         = &dm81xx_l4_ls_hwmod,
 790         .slave          = &dm816x_timer5_hwmod,
 791         .clk            = "sysclk6_ck",
 792         .user           = OCP_USER_MPU,
 793 };
 794
 795 static struct omap_hwmod dm816x_timer6_hwmod = {
 796         .name           = "timer6",
 797         .clkdm_name     = "alwon_l3s_clkdm",
 798         .main_clk       = "timer6_fck",
 799         .prcm           = {
 800                 .omap4 = {
 801                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_6_CLKCTRL,
 802                         .modulemode = MODULEMODE_SWCTRL,
 803                 },
 804         },
 805         .dev_attr       = &capability_alwon_dev_attr,
 806         .class          = &dm816x_timer_hwmod_class,
 807 };
 808
 809 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer6 = {
 810         .master         = &dm81xx_l4_ls_hwmod,
 811         .slave          = &dm816x_timer6_hwmod,
 812         .clk            = "sysclk6_ck",
 813         .user           = OCP_USER_MPU,
 814 };
 815
 816 static struct omap_hwmod dm816x_timer7_hwmod = {
 817         .name           = "timer7",
 818         .clkdm_name     = "alwon_l3s_clkdm",
 819         .main_clk       = "timer7_fck",
 820         .prcm           = {
 821                 .omap4 = {
 822                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_7_CLKCTRL,
 823                         .modulemode = MODULEMODE_SWCTRL,
 824                 },
 825         },
 826         .dev_attr       = &capability_alwon_dev_attr,
 827         .class          = &dm816x_timer_hwmod_class,
 828 };
 829
 830 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer7 = {
 831         .master         = &dm81xx_l4_ls_hwmod,
 832         .slave          = &dm816x_timer7_hwmod,
 833         .clk            = "sysclk6_ck",
 834         .user           = OCP_USER_MPU,
 835 };
 836
 837 /* CPSW on dm814x */
 838 static struct omap_hwmod_class_sysconfig dm814x_cpgmac_sysc = {
 839         .rev_offs       = 0x0,
 840         .sysc_offs      = 0x8,
 841         .syss_offs      = 0x4,
 842         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 843                           SYSS_HAS_RESET_STATUS,
 844         .idlemodes      = SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
 845                           MSTANDBY_NO,
 846         .sysc_fields    = &omap_hwmod_sysc_type3,
 847 };
 848
 849 static struct omap_hwmod_class dm814x_cpgmac0_hwmod_class = {
 850         .name           = "cpgmac0",
 851         .sysc           = &dm814x_cpgmac_sysc,
 852 };
 853
 854 static struct omap_hwmod dm814x_cpgmac0_hwmod = {
 855         .name           = "cpgmac0",
 856         .class          = &dm814x_cpgmac0_hwmod_class,
 857         .clkdm_name     = "alwon_ethernet_clkdm",
 858         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 859         .main_clk       = "cpsw_125mhz_gclk",
 860         .prcm           = {
 861                 .omap4  = {
 862                         .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL,
 863                         .modulemode = MODULEMODE_SWCTRL,
 864                 },
 865         },
 866 };
 867
 868 static struct omap_hwmod_class dm814x_mdio_hwmod_class = {
 869         .name           = "davinci_mdio",
 870 };
 871
 872 static struct omap_hwmod dm814x_mdio_hwmod = {
 873         .name           = "davinci_mdio",
 874         .class          = &dm814x_mdio_hwmod_class,
 875         .clkdm_name     = "alwon_ethernet_clkdm",
 876         .main_clk       = "cpsw_125mhz_gclk",
 877 };
 878
 879 static struct omap_hwmod_ocp_if dm814x_l4_hs__cpgmac0 = {
 880         .master         = &dm81xx_l4_hs_hwmod,
 881         .slave          = &dm814x_cpgmac0_hwmod,
 882         .clk            = "cpsw_125mhz_gclk",
 883         .user           = OCP_USER_MPU,
 884 };
 885
 886 static struct omap_hwmod_ocp_if dm814x_cpgmac0__mdio = {
 887         .master         = &dm814x_cpgmac0_hwmod,
 888         .slave          = &dm814x_mdio_hwmod,
 889         .user           = OCP_USER_MPU,
 890         .flags          = HWMOD_NO_IDLEST,
 891 };
 892
 893 /* EMAC Ethernet */
 894 static struct omap_hwmod_class_sysconfig dm816x_emac_sysc = {
 895         .rev_offs       = 0x0,
 896         .sysc_offs      = 0x4,
 897         .sysc_flags     = SYSC_HAS_SOFTRESET,
 898         .sysc_fields    = &omap_hwmod_sysc_type2,
 899 };
 900
 901 static struct omap_hwmod_class dm816x_emac_hwmod_class = {
 902         .name           = "emac",
 903         .sysc           = &dm816x_emac_sysc,
 904 };
 905
 906 /*
 907  * On dm816x the MDIO is within EMAC0. As the MDIO driver is a separate
 908  * driver probed before EMAC0, we let MDIO do the clock idling.
 909  */
 910 static struct omap_hwmod dm816x_emac0_hwmod = {
 911         .name           = "emac0",
 912         .clkdm_name     = "alwon_ethernet_clkdm",
 913         .class          = &dm816x_emac_hwmod_class,
 914         .flags          = HWMOD_NO_IDLEST,
 915 };
 916
 917 static struct omap_hwmod_ocp_if dm81xx_l4_hs__emac0 = {
 918         .master         = &dm81xx_l4_hs_hwmod,
 919         .slave          = &dm816x_emac0_hwmod,
 920         .clk            = "sysclk5_ck",
 921         .user           = OCP_USER_MPU,
 922 };
 923
 924 static struct omap_hwmod_class dm81xx_mdio_hwmod_class = {
 925         .name           = "davinci_mdio",
 926         .sysc           = &dm816x_emac_sysc,
 927 };
 928
 929 static struct omap_hwmod dm81xx_emac0_mdio_hwmod = {
 930         .name           = "davinci_mdio",
 931         .class          = &dm81xx_mdio_hwmod_class,
 932         .clkdm_name     = "alwon_ethernet_clkdm",
 933         .main_clk       = "sysclk24_ck",
 934         .flags          = HWMOD_NO_IDLEST,
 935         /*
 936          * REVISIT: This should be moved to the emac0_hwmod
 937          * once we have a better way to handle device slaves.
 938          */
 939         .prcm           = {
 940                 .omap4 = {
 941                         .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL,
 942                         .modulemode = MODULEMODE_SWCTRL,
 943                 },
 944         },
 945 };
 946
 947 static struct omap_hwmod_ocp_if dm81xx_emac0__mdio = {
 948         .master         = &dm81xx_l4_hs_hwmod,
 949         .slave          = &dm81xx_emac0_mdio_hwmod,
 950         .user           = OCP_USER_MPU,
 951 };
 952
 953 static struct omap_hwmod dm816x_emac1_hwmod = {
 954         .name           = "emac1",
 955         .clkdm_name     = "alwon_ethernet_clkdm",
 956         .main_clk       = "sysclk24_ck",
 957         .flags          = HWMOD_NO_IDLEST,
 958         .prcm           = {
 959                 .omap4 = {
 960                         .clkctrl_offs = DM816X_CM_ALWON_ETHERNET_1_CLKCTRL,
 961                         .modulemode = MODULEMODE_SWCTRL,
 962                 },
 963         },
 964         .class          = &dm816x_emac_hwmod_class,
 965 };
 966
 967 static struct omap_hwmod_ocp_if dm816x_l4_hs__emac1 = {
 968         .master         = &dm81xx_l4_hs_hwmod,
 969         .slave          = &dm816x_emac1_hwmod,
 970         .clk            = "sysclk5_ck",
 971         .user           = OCP_USER_MPU,
 972 };
 973
 974 static struct omap_hwmod_class_sysconfig dm81xx_mmc_sysc = {
 975         .rev_offs       = 0x0,
 976         .sysc_offs      = 0x110,
 977         .syss_offs      = 0x114,
 978         .sysc_flags     = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 979                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 980                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
 981         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
 982         .sysc_fields    = &omap_hwmod_sysc_type1,
 983 };
 984
 985 static struct omap_hwmod_class dm81xx_mmc_class = {
 986         .name = "mmc",
 987         .sysc = &dm81xx_mmc_sysc,
 988 };
 989
 990 static struct omap_hwmod_opt_clk dm81xx_mmc_opt_clks[] = {
 991         { .role = "dbck", .clk = "sysclk18_ck", },
 992 };
 993
 994 static struct omap_hsmmc_dev_attr mmc_dev_attr = {
 995 };
 996
 997 static struct omap_hwmod dm814x_mmc1_hwmod = {
 998         .name           = "mmc1",
 999         .clkdm_name     = "alwon_l3s_clkdm",
1000         .opt_clks       = dm81xx_mmc_opt_clks,
1001         .opt_clks_cnt   = ARRAY_SIZE(dm81xx_mmc_opt_clks),
1002         .main_clk       = "sysclk8_ck",
1003         .prcm           = {
1004                 .omap4 = {
1005                         .clkctrl_offs = DM814X_CM_ALWON_MMCHS_0_CLKCTRL,
1006                         .modulemode = MODULEMODE_SWCTRL,
1007                 },
1008         },
1009         .dev_attr       = &mmc_dev_attr,
1010         .class          = &dm81xx_mmc_class,
1011 };
1012
1013 static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc1 = {
1014         .master         = &dm81xx_l4_ls_hwmod,
1015         .slave          = &dm814x_mmc1_hwmod,
1016         .clk            = "sysclk6_ck",
1017         .user           = OCP_USER_MPU,
1018         .flags          = OMAP_FIREWALL_L4
1019 };
1020
1021 static struct omap_hwmod dm814x_mmc2_hwmod = {
1022         .name           = "mmc2",
1023         .clkdm_name     = "alwon_l3s_clkdm",
1024         .opt_clks       = dm81xx_mmc_opt_clks,
1025         .opt_clks_cnt   = ARRAY_SIZE(dm81xx_mmc_opt_clks),
1026         .main_clk       = "sysclk8_ck",
1027         .prcm           = {
1028                 .omap4 = {
1029                         .clkctrl_offs = DM814X_CM_ALWON_MMCHS_1_CLKCTRL,
1030                         .modulemode = MODULEMODE_SWCTRL,
1031                 },
1032         },
1033         .dev_attr       = &mmc_dev_attr,
1034         .class          = &dm81xx_mmc_class,
1035 };
1036
1037 static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc2 = {
1038         .master         = &dm81xx_l4_ls_hwmod,
1039         .slave          = &dm814x_mmc2_hwmod,
1040         .clk            = "sysclk6_ck",
1041         .user           = OCP_USER_MPU,
1042         .flags          = OMAP_FIREWALL_L4
1043 };
1044
1045 static struct omap_hwmod dm814x_mmc3_hwmod = {
1046         .name           = "mmc3",
1047         .clkdm_name     = "alwon_l3_med_clkdm",
1048         .opt_clks       = dm81xx_mmc_opt_clks,
1049         .opt_clks_cnt   = ARRAY_SIZE(dm81xx_mmc_opt_clks),
1050         .main_clk       = "sysclk8_ck",
1051         .prcm           = {
1052                 .omap4 = {
1053                         .clkctrl_offs = DM814X_CM_ALWON_MMCHS_2_CLKCTRL,
1054                         .modulemode = MODULEMODE_SWCTRL,
1055                 },
1056         },
1057         .dev_attr       = &mmc_dev_attr,
1058         .class          = &dm81xx_mmc_class,
1059 };
1060
1061 static struct omap_hwmod_ocp_if dm814x_alwon_l3_med__mmc3 = {
1062         .master         = &dm81xx_alwon_l3_med_hwmod,
1063         .slave          = &dm814x_mmc3_hwmod,
1064         .clk            = "sysclk4_ck",
1065         .user           = OCP_USER_MPU,
1066 };
1067
1068 static struct omap_hwmod dm816x_mmc1_hwmod = {
1069         .name           = "mmc1",
1070         .clkdm_name     = "alwon_l3s_clkdm",
1071         .opt_clks       = dm81xx_mmc_opt_clks,
1072         .opt_clks_cnt   = ARRAY_SIZE(dm81xx_mmc_opt_clks),
1073         .main_clk       = "sysclk10_ck",
1074         .prcm           = {
1075                 .omap4 = {
1076                         .clkctrl_offs = DM816X_CM_ALWON_SDIO_CLKCTRL,
1077                         .modulemode = MODULEMODE_SWCTRL,
1078                 },
1079         },
1080         .dev_attr       = &mmc_dev_attr,
1081         .class          = &dm81xx_mmc_class,
1082 };
1083
1084 static struct omap_hwmod_ocp_if dm816x_l4_ls__mmc1 = {
1085         .master         = &dm81xx_l4_ls_hwmod,
1086         .slave          = &dm816x_mmc1_hwmod,
1087         .clk            = "sysclk6_ck",
1088         .user           = OCP_USER_MPU,
1089         .flags          = OMAP_FIREWALL_L4
1090 };
1091
1092 static struct omap_hwmod_class_sysconfig dm816x_mcspi_sysc = {
1093         .rev_offs       = 0x0,
1094         .sysc_offs      = 0x110,
1095         .syss_offs      = 0x114,
1096         .sysc_flags     = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1097                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1098                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
1099         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
1100         .sysc_fields    = &omap_hwmod_sysc_type1,
1101 };
1102
1103 static struct omap_hwmod_class dm816x_mcspi_class = {
1104         .name = "mcspi",
1105         .sysc = &dm816x_mcspi_sysc,
1106         .rev = OMAP3_MCSPI_REV,
1107 };
1108
1109 static struct omap2_mcspi_dev_attr dm816x_mcspi1_dev_attr = {
1110         .num_chipselect = 4,
1111 };
1112
1113 static struct omap_hwmod dm81xx_mcspi1_hwmod = {
1114         .name           = "mcspi1",
1115         .clkdm_name     = "alwon_l3s_clkdm",
1116         .main_clk       = "sysclk10_ck",
1117         .prcm           = {
1118                 .omap4 = {
1119                         .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
1120                         .modulemode = MODULEMODE_SWCTRL,
1121                 },
1122         },
1123         .class          = &dm816x_mcspi_class,
1124         .dev_attr       = &dm816x_mcspi1_dev_attr,
1125 };
1126
1127 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = {
1128         .master         = &dm81xx_l4_ls_hwmod,
1129         .slave          = &dm81xx_mcspi1_hwmod,
1130         .clk            = "sysclk6_ck",
1131         .user           = OCP_USER_MPU,
1132 };
1133
1134 static struct omap_hwmod_class_sysconfig dm81xx_mailbox_sysc = {
1135         .rev_offs       = 0x000,
1136         .sysc_offs      = 0x010,
1137         .syss_offs      = 0x014,
1138         .sysc_flags     = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1139                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE,
1140         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
1141         .sysc_fields    = &omap_hwmod_sysc_type1,
1142 };
1143
1144 static struct omap_hwmod_class dm81xx_mailbox_hwmod_class = {
1145         .name = "mailbox",
1146         .sysc = &dm81xx_mailbox_sysc,
1147 };
1148
1149 static struct omap_hwmod dm81xx_mailbox_hwmod = {
1150         .name           = "mailbox",
1151         .clkdm_name     = "alwon_l3s_clkdm",
1152         .class          = &dm81xx_mailbox_hwmod_class,
1153         .main_clk       = "sysclk6_ck",
1154         .prcm           = {
1155                 .omap4 = {
1156                         .clkctrl_offs = DM81XX_CM_ALWON_MAILBOX_CLKCTRL,
1157                         .modulemode = MODULEMODE_SWCTRL,
1158                 },
1159         },
1160 };
1161
1162 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mailbox = {
1163         .master         = &dm81xx_l4_ls_hwmod,
1164         .slave          = &dm81xx_mailbox_hwmod,
1165         .clk            = "sysclk6_ck",
1166         .user           = OCP_USER_MPU,
1167 };
1168
1169 static struct omap_hwmod_class_sysconfig dm81xx_spinbox_sysc = {
1170         .rev_offs       = 0x000,
1171         .sysc_offs      = 0x010,
1172         .syss_offs      = 0x014,
1173         .sysc_flags     = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1174                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE,
1175         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
1176         .sysc_fields    = &omap_hwmod_sysc_type1,
1177 };
1178
1179 static struct omap_hwmod_class dm81xx_spinbox_hwmod_class = {
1180         .name = "spinbox",
1181         .sysc = &dm81xx_spinbox_sysc,
1182 };
1183
1184 static struct omap_hwmod dm81xx_spinbox_hwmod = {
1185         .name           = "spinbox",
1186         .clkdm_name     = "alwon_l3s_clkdm",
1187         .class          = &dm81xx_spinbox_hwmod_class,
1188         .main_clk       = "sysclk6_ck",
1189         .prcm           = {
1190                 .omap4 = {
1191                         .clkctrl_offs = DM81XX_CM_ALWON_SPINBOX_CLKCTRL,
1192                         .modulemode = MODULEMODE_SWCTRL,
1193                 },
1194         },
1195 };
1196
1197 static struct omap_hwmod_ocp_if dm81xx_l4_ls__spinbox = {
1198         .master         = &dm81xx_l4_ls_hwmod,
1199         .slave          = &dm81xx_spinbox_hwmod,
1200         .clk            = "sysclk6_ck",
1201         .user           = OCP_USER_MPU,
1202 };
1203
1204 static struct omap_hwmod_class dm81xx_tpcc_hwmod_class = {
1205         .name           = "tpcc",
1206 };
1207
1208 static struct omap_hwmod dm81xx_tpcc_hwmod = {
1209         .name           = "tpcc",
1210         .class          = &dm81xx_tpcc_hwmod_class,
1211         .clkdm_name     = "alwon_l3s_clkdm",
1212         .main_clk       = "sysclk4_ck",
1213         .prcm           = {
1214                 .omap4  = {
1215                         .clkctrl_offs   = DM81XX_CM_ALWON_TPCC_CLKCTRL,
1216                         .modulemode     = MODULEMODE_SWCTRL,
1217                 },
1218         },
1219 };
1220
1221 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tpcc = {
1222         .master         = &dm81xx_alwon_l3_fast_hwmod,
1223         .slave          = &dm81xx_tpcc_hwmod,
1224         .clk            = "sysclk4_ck",
1225         .user           = OCP_USER_MPU,
1226 };
1227
1228 static struct omap_hwmod_addr_space dm81xx_tptc0_addr_space[] = {
1229         {
1230                 .pa_start       = 0x49800000,
1231                 .pa_end         = 0x49800000 + SZ_8K - 1,
1232                 .flags          = ADDR_TYPE_RT,
1233         },
1234         { },
1235 };
1236
1237 static struct omap_hwmod_class dm81xx_tptc0_hwmod_class = {
1238         .name           = "tptc0",
1239 };
1240
1241 static struct omap_hwmod dm81xx_tptc0_hwmod = {
1242         .name           = "tptc0",
1243         .class          = &dm81xx_tptc0_hwmod_class,
1244         .clkdm_name     = "alwon_l3s_clkdm",
1245         .main_clk       = "sysclk4_ck",
1246         .prcm           = {
1247                 .omap4  = {
1248                         .clkctrl_offs   = DM81XX_CM_ALWON_TPTC0_CLKCTRL,
1249                         .modulemode     = MODULEMODE_SWCTRL,
1250                 },
1251         },
1252 };
1253
1254 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc0 = {
1255         .master         = &dm81xx_alwon_l3_fast_hwmod,
1256         .slave          = &dm81xx_tptc0_hwmod,
1257         .clk            = "sysclk4_ck",
1258         .addr           = dm81xx_tptc0_addr_space,
1259         .user           = OCP_USER_MPU,
1260 };
1261
1262 static struct omap_hwmod_ocp_if dm81xx_tptc0__alwon_l3_fast = {
1263         .master         = &dm81xx_tptc0_hwmod,
1264         .slave          = &dm81xx_alwon_l3_fast_hwmod,
1265         .clk            = "sysclk4_ck",
1266         .addr           = dm81xx_tptc0_addr_space,
1267         .user           = OCP_USER_MPU,
1268 };
1269
1270 static struct omap_hwmod_addr_space dm81xx_tptc1_addr_space[] = {
1271         {
1272                 .pa_start       = 0x49900000,
1273                 .pa_end         = 0x49900000 + SZ_8K - 1,
1274                 .flags          = ADDR_TYPE_RT,
1275         },
1276         { },
1277 };
1278
1279 static struct omap_hwmod_class dm81xx_tptc1_hwmod_class = {
1280         .name           = "tptc1",
1281 };
1282
1283 static struct omap_hwmod dm81xx_tptc1_hwmod = {
1284         .name           = "tptc1",
1285         .class          = &dm81xx_tptc1_hwmod_class,
1286         .clkdm_name     = "alwon_l3s_clkdm",
1287         .main_clk       = "sysclk4_ck",
1288         .prcm           = {
1289                 .omap4  = {
1290                         .clkctrl_offs   = DM81XX_CM_ALWON_TPTC1_CLKCTRL,
1291                         .modulemode     = MODULEMODE_SWCTRL,
1292                 },
1293         },
1294 };
1295
1296 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc1 = {
1297         .master         = &dm81xx_alwon_l3_fast_hwmod,
1298         .slave          = &dm81xx_tptc1_hwmod,
1299         .clk            = "sysclk4_ck",
1300         .addr           = dm81xx_tptc1_addr_space,
1301         .user           = OCP_USER_MPU,
1302 };
1303
1304 static struct omap_hwmod_ocp_if dm81xx_tptc1__alwon_l3_fast = {
1305         .master         = &dm81xx_tptc1_hwmod,
1306         .slave          = &dm81xx_alwon_l3_fast_hwmod,
1307         .clk            = "sysclk4_ck",
1308         .addr           = dm81xx_tptc1_addr_space,
1309         .user           = OCP_USER_MPU,
1310 };
1311
1312 static struct omap_hwmod_addr_space dm81xx_tptc2_addr_space[] = {
1313         {
1314                 .pa_start       = 0x49a00000,
1315                 .pa_end         = 0x49a00000 + SZ_8K - 1,
1316                 .flags          = ADDR_TYPE_RT,
1317         },
1318         { },
1319 };
1320
1321 static struct omap_hwmod_class dm81xx_tptc2_hwmod_class = {
1322         .name           = "tptc2",
1323 };
1324
1325 static struct omap_hwmod dm81xx_tptc2_hwmod = {
1326         .name           = "tptc2",
1327         .class          = &dm81xx_tptc2_hwmod_class,
1328         .clkdm_name     = "alwon_l3s_clkdm",
1329         .main_clk       = "sysclk4_ck",
1330         .prcm           = {
1331                 .omap4  = {
1332                         .clkctrl_offs   = DM81XX_CM_ALWON_TPTC2_CLKCTRL,
1333                         .modulemode     = MODULEMODE_SWCTRL,
1334                 },
1335         },
1336 };
1337
1338 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc2 = {
1339         .master         = &dm81xx_alwon_l3_fast_hwmod,
1340         .slave          = &dm81xx_tptc2_hwmod,
1341         .clk            = "sysclk4_ck",
1342         .addr           = dm81xx_tptc2_addr_space,
1343         .user           = OCP_USER_MPU,
1344 };
1345
1346 static struct omap_hwmod_ocp_if dm81xx_tptc2__alwon_l3_fast = {
1347         .master         = &dm81xx_tptc2_hwmod,
1348         .slave          = &dm81xx_alwon_l3_fast_hwmod,
1349         .clk            = "sysclk4_ck",
1350         .addr           = dm81xx_tptc2_addr_space,
1351         .user           = OCP_USER_MPU,
1352 };
1353
1354 static struct omap_hwmod_addr_space dm81xx_tptc3_addr_space[] = {
1355         {
1356                 .pa_start       = 0x49b00000,
1357                 .pa_end         = 0x49b00000 + SZ_8K - 1,
1358                 .flags          = ADDR_TYPE_RT,
1359         },
1360         { },
1361 };
1362
1363 static struct omap_hwmod_class dm81xx_tptc3_hwmod_class = {
1364         .name           = "tptc3",
1365 };
1366
1367 static struct omap_hwmod dm81xx_tptc3_hwmod = {
1368         .name           = "tptc3",
1369         .class          = &dm81xx_tptc3_hwmod_class,
1370         .clkdm_name     = "alwon_l3s_clkdm",
1371         .main_clk       = "sysclk4_ck",
1372         .prcm           = {
1373                 .omap4  = {
1374                         .clkctrl_offs   = DM81XX_CM_ALWON_TPTC3_CLKCTRL,
1375                         .modulemode     = MODULEMODE_SWCTRL,
1376                 },
1377         },
1378 };
1379
1380 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc3 = {
1381         .master         = &dm81xx_alwon_l3_fast_hwmod,
1382         .slave          = &dm81xx_tptc3_hwmod,
1383         .clk            = "sysclk4_ck",
1384         .addr           = dm81xx_tptc3_addr_space,
1385         .user           = OCP_USER_MPU,
1386 };
1387
1388 static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = {
1389         .master         = &dm81xx_tptc3_hwmod,
1390         .slave          = &dm81xx_alwon_l3_fast_hwmod,
1391         .clk            = "sysclk4_ck",
1392         .addr           = dm81xx_tptc3_addr_space,
1393         .user           = OCP_USER_MPU,
1394 };
1395
1396 /*
1397  * REVISIT: Test and enable the following once clocks work:
1398  * dm81xx_l4_ls__mailbox
1399  *
1400  * Also note that some devices share a single clkctrl_offs..
1401  * For example, i2c1 and 3 share one, and i2c2 and 4 share one.
1402  */
1403 static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = {
1404         &dm814x_mpu__alwon_l3_slow,
1405         &dm814x_mpu__alwon_l3_med,
1406         &dm81xx_alwon_l3_slow__l4_ls,
1407         &dm81xx_alwon_l3_slow__l4_hs,
1408         &dm81xx_l4_ls__uart1,
1409         &dm81xx_l4_ls__uart2,
1410         &dm81xx_l4_ls__uart3,
1411         &dm81xx_l4_ls__wd_timer1,
1412         &dm81xx_l4_ls__i2c1,
1413         &dm81xx_l4_ls__i2c2,
1414         &dm81xx_l4_ls__gpio1,
1415         &dm81xx_l4_ls__gpio2,
1416         &dm81xx_l4_ls__elm,
1417         &dm81xx_l4_ls__mcspi1,
1418         &dm814x_l4_ls__mmc1,
1419         &dm814x_l4_ls__mmc2,
1420         &ti81xx_l4_ls__rtc,
1421         &dm81xx_alwon_l3_fast__tpcc,
1422         &dm81xx_alwon_l3_fast__tptc0,
1423         &dm81xx_alwon_l3_fast__tptc1,
1424         &dm81xx_alwon_l3_fast__tptc2,
1425         &dm81xx_alwon_l3_fast__tptc3,
1426         &dm81xx_tptc0__alwon_l3_fast,
1427         &dm81xx_tptc1__alwon_l3_fast,
1428         &dm81xx_tptc2__alwon_l3_fast,
1429         &dm81xx_tptc3__alwon_l3_fast,
1430         &dm814x_l4_ls__timer1,
1431         &dm814x_l4_ls__timer2,
1432         &dm814x_l4_hs__cpgmac0,
1433         &dm814x_cpgmac0__mdio,
1434         &dm81xx_alwon_l3_slow__gpmc,
1435         &dm814x_default_l3_slow__usbss,
1436         &dm814x_alwon_l3_med__mmc3,
1437         NULL,
1438 };
1439
1440 int __init dm814x_hwmod_init(void)
1441 {
1442         omap_hwmod_init();
1443         return omap_hwmod_register_links(dm814x_hwmod_ocp_ifs);
1444 }
1445
1446 static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = {
1447         &dm816x_mpu__alwon_l3_slow,
1448         &dm816x_mpu__alwon_l3_med,
1449         &dm81xx_alwon_l3_slow__l4_ls,
1450         &dm81xx_alwon_l3_slow__l4_hs,
1451         &dm81xx_l4_ls__uart1,
1452         &dm81xx_l4_ls__uart2,
1453         &dm81xx_l4_ls__uart3,
1454         &dm81xx_l4_ls__wd_timer1,
1455         &dm81xx_l4_ls__i2c1,
1456         &dm81xx_l4_ls__i2c2,
1457         &dm81xx_l4_ls__gpio1,
1458         &dm81xx_l4_ls__gpio2,
1459         &dm81xx_l4_ls__elm,
1460         &ti81xx_l4_ls__rtc,
1461         &dm816x_l4_ls__mmc1,
1462         &dm816x_l4_ls__timer1,
1463         &dm816x_l4_ls__timer2,
1464         &dm816x_l4_ls__timer3,
1465         &dm816x_l4_ls__timer4,
1466         &dm816x_l4_ls__timer5,
1467         &dm816x_l4_ls__timer6,
1468         &dm816x_l4_ls__timer7,
1469         &dm81xx_l4_ls__mcspi1,
1470         &dm81xx_l4_ls__mailbox,
1471         &dm81xx_l4_ls__spinbox,
1472         &dm81xx_l4_hs__emac0,
1473         &dm81xx_emac0__mdio,
1474         &dm816x_l4_hs__emac1,
1475         &dm81xx_alwon_l3_fast__tpcc,
1476         &dm81xx_alwon_l3_fast__tptc0,
1477         &dm81xx_alwon_l3_fast__tptc1,
1478         &dm81xx_alwon_l3_fast__tptc2,
1479         &dm81xx_alwon_l3_fast__tptc3,
1480         &dm81xx_tptc0__alwon_l3_fast,
1481         &dm81xx_tptc1__alwon_l3_fast,
1482         &dm81xx_tptc2__alwon_l3_fast,
1483         &dm81xx_tptc3__alwon_l3_fast,
1484         &dm81xx_alwon_l3_slow__gpmc,
1485         &dm816x_default_l3_slow__usbss,
1486         NULL,
1487 };
1488
1489 int __init dm816x_hwmod_init(void)
1490 {
1491         omap_hwmod_init();
1492         return omap_hwmod_register_links(dm816x_hwmod_ocp_ifs);
1493 }